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entity record1 is
end entity;
architecture test of record1 is
type r1 is record
x, y : integer;
end record;
begin
process is
variable a, b : r1 := (1, 2);
begin
assert a.x = 1;
a.x := 5;
a := b;
assert a.x = 1;
assert a = b;
wait;
end process;
end architecture;
|
entity record1 is
end entity;
architecture test of record1 is
type r1 is record
x, y : integer;
end record;
begin
process is
variable a, b : r1 := (1, 2);
begin
assert a.x = 1;
a.x := 5;
a := b;
assert a.x = 1;
assert a = b;
wait;
end process;
end architecture;
|
entity record1 is
end entity;
architecture test of record1 is
type r1 is record
x, y : integer;
end record;
begin
process is
variable a, b : r1 := (1, 2);
begin
assert a.x = 1;
a.x := 5;
a := b;
assert a.x = 1;
assert a = b;
wait;
end process;
end architecture;
|
entity record1 is
end entity;
architecture test of record1 is
type r1 is record
x, y : integer;
end record;
begin
process is
variable a, b : r1 := (1, 2);
begin
assert a.x = 1;
a.x := 5;
a := b;
assert a.x = 1;
assert a = b;
wait;
end process;
end architecture;
|
use std.textio.all;
entity sliding_index is
end entity;
architecture foo of sliding_index is
type integer_vector is array (natural range <>) of integer;
function to_string(inp: integer_vector) return string is
variable retn: line;
begin
for i in inp'range loop
if i = inp'RIGHT then
write (retn, integer'image(inp(i)));
else
write (retn, integer'image(inp(i)) & ',');
end if;
end loop;
return retn(1 to retn'length); -- the string value of the line
end function;
constant ivec: integer_vector := (1,2,3,4,5,6,7);
signal sum: integer_vector (ivec'range);
-- signal sum: integer_vector (0 to 6);
begin
sum <= (
0 => ( ivec(0) + ivec(1)),
1 => (ivec(0) + ivec(1) + ivec(2)),
2 => (ivec(1) + ivec(2) + ivec(3)),
3 => (ivec(2) + ivec(3) + ivec(4)),
4 => (ivec(3) + ivec(4) + ivec(5)),
5 => (ivec(4) + ivec(5) + ivec(6)),
6 => (ivec(5) + ivec(6) )
);
process
begin
wait for 0 ns;
report "ivec = " & to_string(ivec);
report "sum = " & to_string(sum);
wait;
end process;
end architecture;
|
use std.textio.all;
entity sliding_index is
end entity;
architecture foo of sliding_index is
type integer_vector is array (natural range <>) of integer;
function to_string(inp: integer_vector) return string is
variable retn: line;
begin
for i in inp'range loop
if i = inp'RIGHT then
write (retn, integer'image(inp(i)));
else
write (retn, integer'image(inp(i)) & ',');
end if;
end loop;
return retn(1 to retn'length); -- the string value of the line
end function;
constant ivec: integer_vector := (1,2,3,4,5,6,7);
signal sum: integer_vector (ivec'range);
-- signal sum: integer_vector (0 to 6);
begin
sum <= (
0 => ( ivec(0) + ivec(1)),
1 => (ivec(0) + ivec(1) + ivec(2)),
2 => (ivec(1) + ivec(2) + ivec(3)),
3 => (ivec(2) + ivec(3) + ivec(4)),
4 => (ivec(3) + ivec(4) + ivec(5)),
5 => (ivec(4) + ivec(5) + ivec(6)),
6 => (ivec(5) + ivec(6) )
);
process
begin
wait for 0 ns;
report "ivec = " & to_string(ivec);
report "sum = " & to_string(sum);
wait;
end process;
end architecture;
|
--========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_gpio;
use bitvis_vip_gpio.gpio_bfm_pkg.all;
use bitvis_vip_gpio.vvc_cmd_pkg.all;
use bitvis_vip_gpio.vvc_methods_pkg.all;
use bitvis_vip_gpio.td_vvc_framework_common_methods_pkg.all;
end context; |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/Complex3Multiply.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din2_re_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
din2_im_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
di2_vld_dly3 : IN std_logic;
twdl_3_2_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_2_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_2_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_2_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin2_vld : OUT std_logic
);
END Complex3Multiply;
ARCHITECTURE rtl OF Complex3Multiply IS
-- Signals
SIGNAL din2_re_dly3_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din_re_reg : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din2_im_dly3_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din_im_reg : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL adder_add_cast : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL adder_add_cast_1 : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din_sum : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdl_3_2_re_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_re_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_2_im_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_im_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL adder_add_cast_2 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL adder_add_cast_3 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL twdl_sum : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(31 DOWNTO 0); -- sfix32
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(31 DOWNTO 0); -- sfix32
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL prodOfRe : signed(31 DOWNTO 0); -- sfix32_En27
SIGNAL prodOfIm : signed(31 DOWNTO 0); -- sfix32_En27
SIGNAL prodOfSum : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Add_multRes_re_reg1 : signed(32 DOWNTO 0); -- sfix33
SIGNAL Complex3Add_multRes_re_reg2 : signed(32 DOWNTO 0); -- sfix33
SIGNAL Complex3Add_multRes_im_reg : signed(34 DOWNTO 0); -- sfix35
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Add_tmpResult_reg_next : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL Complex3Add_multRes_re_reg1_next : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL Complex3Add_multRes_re_reg2_next : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL Complex3Add_multRes_im_reg_next : signed(34 DOWNTO 0); -- sfix35_En27
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL multResFP_re : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL multResFP_im : signed(34 DOWNTO 0); -- sfix35_En27
SIGNAL twdlXdin_2_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_2_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
din2_re_dly3_signed <= signed(din2_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#0000#, 16);
ELSE
din_re_reg <= din2_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din2_im_dly3_signed <= signed(din2_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#0000#, 16);
ELSE
din_im_reg <= din2_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
adder_add_cast <= resize(din_re_reg, 17);
adder_add_cast_1 <= resize(din_im_reg, 17);
din_sum <= adder_add_cast + adder_add_cast_1;
twdl_3_2_re_signed <= signed(twdl_3_2_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSE
twdl_re_reg <= twdl_3_2_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_2_im_signed <= signed(twdl_3_2_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSE
twdl_im_reg <= twdl_3_2_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast_2 <= resize(twdl_re_reg, 17);
adder_add_cast_3 <= resize(twdl_im_reg, 17);
twdl_sum <= adder_add_cast_2 + adder_add_cast_3;
-- Complex3Multiply
Complex3Multiply_1_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_1_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly1 <= di2_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 34);
Complex3Add_tmpResult_reg <= to_signed(0, 34);
Complex3Add_multRes_re_reg1 <= to_signed(0, 33);
Complex3Add_multRes_re_reg2 <= to_signed(0, 33);
Complex3Add_multRes_im_reg <= to_signed(0, 35);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(32 DOWNTO 0);
VARIABLE sub_cast_0 : signed(32 DOWNTO 0);
VARIABLE sub_cast_1 : signed(34 DOWNTO 0);
VARIABLE sub_cast_2 : signed(34 DOWNTO 0);
VARIABLE add_cast : signed(32 DOWNTO 0);
VARIABLE add_cast_0 : signed(32 DOWNTO 0);
VARIABLE add_temp : signed(32 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 33);
sub_cast_0 := resize(prodOfIm, 33);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 35);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 35);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 33);
add_cast_0 := resize(prodOfIm, 33);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 34);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin2_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_2_re_tmp <= multResFP_re(29 DOWNTO 14);
twdlXdin_2_re <= std_logic_vector(twdlXdin_2_re_tmp);
twdlXdin_2_im_tmp <= multResFP_im(29 DOWNTO 14);
twdlXdin_2_im <= std_logic_vector(twdlXdin_2_im_tmp);
END rtl;
|
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: modulo2Hz.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity modulo2Hz is
Port ( clk_50MHz : in STD_LOGIC;
ena : in STD_LOGIC;
rst: in std_logic;
pulso_2Hz : out STD_LOGIC
);
end modulo2Hz;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture rtl of modulo2Hz is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal pulso_2Hz_aux: std_logic;
-----------------------------------------------------------------------------
-- Componentes
-----------------------------------------------------------------------------
COMPONENT cont50
PORT(
clk : IN std_logic;
ena : IN std_logic;
rst : IN std_logic;
fin : OUT std_logic
);
END COMPONENT;
begin
-----------------------------------------------------------------------------
-- Conexion de senales
-----------------------------------------------------------------------------
pulso_2Hz <= pulso_2Hz_aux;
-----------------------------------------------------------------------------
-- Conexion de componentes
-----------------------------------------------------------------------------
cont50_0: cont50 PORT MAP(
clk => clk_50MHz,
ena => ena,
rst => rst,
fin => pulso_2Hz_aux
);
end rtl;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_bram_if_cntlr_v4_0;
USE lmb_bram_if_cntlr_v4_0.lmb_bram_if_cntlr;
ENTITY design_1_ilmb_bram_if_cntlr_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
);
END design_1_ilmb_bram_if_cntlr_0;
ARCHITECTURE design_1_ilmb_bram_if_cntlr_0_arch OF design_1_ilmb_bram_if_cntlr_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_bram_if_cntlr IS
GENERIC (
C_FAMILY : STRING;
C_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_NUM_LMB : INTEGER;
C_MASK : STD_LOGIC_VECTOR(0 TO 31);
C_MASK1 : STD_LOGIC_VECTOR(0 TO 31);
C_MASK2 : STD_LOGIC_VECTOR(0 TO 31);
C_MASK3 : STD_LOGIC_VECTOR(0 TO 31);
C_LMB_AWIDTH : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_ECC : INTEGER;
C_INTERCONNECT : INTEGER;
C_FAULT_INJECT : INTEGER;
C_CE_FAILING_REGISTERS : INTEGER;
C_UE_FAILING_REGISTERS : INTEGER;
C_ECC_STATUS_REGISTERS : INTEGER;
C_ECC_ONOFF_REGISTER : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER;
C_CE_COUNTER_WIDTH : INTEGER;
C_WRITE_ACCESS : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_AddrStrobe : IN STD_LOGIC;
LMB1_ReadStrobe : IN STD_LOGIC;
LMB1_WriteStrobe : IN STD_LOGIC;
LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl1_Ready : OUT STD_LOGIC;
Sl1_Wait : OUT STD_LOGIC;
Sl1_UE : OUT STD_LOGIC;
Sl1_CE : OUT STD_LOGIC;
LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_AddrStrobe : IN STD_LOGIC;
LMB2_ReadStrobe : IN STD_LOGIC;
LMB2_WriteStrobe : IN STD_LOGIC;
LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl2_Ready : OUT STD_LOGIC;
Sl2_Wait : OUT STD_LOGIC;
Sl2_UE : OUT STD_LOGIC;
Sl2_CE : OUT STD_LOGIC;
LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_AddrStrobe : IN STD_LOGIC;
LMB3_ReadStrobe : IN STD_LOGIC;
LMB3_WriteStrobe : IN STD_LOGIC;
LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl3_Ready : OUT STD_LOGIC;
Sl3_Wait : OUT STD_LOGIC;
Sl3_UE : OUT STD_LOGIC;
Sl3_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
S_AXI_CTRL_ACLK : IN STD_LOGIC;
S_AXI_CTRL_ARESETN : IN STD_LOGIC;
S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_AWVALID : IN STD_LOGIC;
S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_CTRL_WVALID : IN STD_LOGIC;
S_AXI_CTRL_WREADY : OUT STD_LOGIC;
S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_BVALID : OUT STD_LOGIC;
S_AXI_CTRL_BREADY : IN STD_LOGIC;
S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_ARVALID : IN STD_LOGIC;
S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_RVALID : OUT STD_LOGIC;
S_AXI_CTRL_RREADY : IN STD_LOGIC;
UE : OUT STD_LOGIC;
CE : OUT STD_LOGIC;
Interrupt : OUT STD_LOGIC
);
END COMPONENT lmb_bram_if_cntlr;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "lmb_bram_if_cntlr,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_ilmb_bram_if_cntlr_0_arch : ARCHITECTURE IS "design_1_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "design_1_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_HIGHADDR=0x00007FFF,C_BASEADDR=0x00000000,C_NUM_LMB=1,C_MASK=0x20000000,C_MASK1=0x00800000,C_MASK2=0x00800000,C_MASK3=0x00800000,C_LMB_AWIDTH=32,C_LMB_DWIDTH=32,C_ECC=0,C_INTERCONNECT=0,C_FAULT_INJECT=0,C_CE_FAILING_REGISTERS=0,C_UE_FAILING_REGISTERS=0,C_ECC_STATUS_REGISTERS=0,C_ECC_ONOFF_REGISTER=0,C_ECC_ONOFF_RESET_VALUE=1,C_CE_COUNTER_WIDTH=0,C_WRITE_ACCESS=2,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
BEGIN
U0 : lmb_bram_if_cntlr
GENERIC MAP (
C_FAMILY => "artix7",
C_HIGHADDR => X"00007FFF",
C_BASEADDR => X"00000000",
C_NUM_LMB => 1,
C_MASK => X"20000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
PORT MAP (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_AddrStrobe => '0',
LMB1_ReadStrobe => '0',
LMB1_WriteStrobe => '0',
LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_AddrStrobe => '0',
LMB2_ReadStrobe => '0',
LMB2_WriteStrobe => '0',
LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_AddrStrobe => '0',
LMB3_ReadStrobe => '0',
LMB3_WriteStrobe => '0',
LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Din_A => BRAM_Din_A,
S_AXI_CTRL_ACLK => '0',
S_AXI_CTRL_ARESETN => '0',
S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_AWVALID => '0',
S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_CTRL_WVALID => '0',
S_AXI_CTRL_BREADY => '0',
S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_ARVALID => '0',
S_AXI_CTRL_RREADY => '0'
);
END design_1_ilmb_bram_if_cntlr_0_arch;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_bram_if_cntlr_v4_0;
USE lmb_bram_if_cntlr_v4_0.lmb_bram_if_cntlr;
ENTITY design_1_ilmb_bram_if_cntlr_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
);
END design_1_ilmb_bram_if_cntlr_0;
ARCHITECTURE design_1_ilmb_bram_if_cntlr_0_arch OF design_1_ilmb_bram_if_cntlr_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_bram_if_cntlr IS
GENERIC (
C_FAMILY : STRING;
C_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_NUM_LMB : INTEGER;
C_MASK : STD_LOGIC_VECTOR(0 TO 31);
C_MASK1 : STD_LOGIC_VECTOR(0 TO 31);
C_MASK2 : STD_LOGIC_VECTOR(0 TO 31);
C_MASK3 : STD_LOGIC_VECTOR(0 TO 31);
C_LMB_AWIDTH : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_ECC : INTEGER;
C_INTERCONNECT : INTEGER;
C_FAULT_INJECT : INTEGER;
C_CE_FAILING_REGISTERS : INTEGER;
C_UE_FAILING_REGISTERS : INTEGER;
C_ECC_STATUS_REGISTERS : INTEGER;
C_ECC_ONOFF_REGISTER : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER;
C_CE_COUNTER_WIDTH : INTEGER;
C_WRITE_ACCESS : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_AddrStrobe : IN STD_LOGIC;
LMB1_ReadStrobe : IN STD_LOGIC;
LMB1_WriteStrobe : IN STD_LOGIC;
LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl1_Ready : OUT STD_LOGIC;
Sl1_Wait : OUT STD_LOGIC;
Sl1_UE : OUT STD_LOGIC;
Sl1_CE : OUT STD_LOGIC;
LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_AddrStrobe : IN STD_LOGIC;
LMB2_ReadStrobe : IN STD_LOGIC;
LMB2_WriteStrobe : IN STD_LOGIC;
LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl2_Ready : OUT STD_LOGIC;
Sl2_Wait : OUT STD_LOGIC;
Sl2_UE : OUT STD_LOGIC;
Sl2_CE : OUT STD_LOGIC;
LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_AddrStrobe : IN STD_LOGIC;
LMB3_ReadStrobe : IN STD_LOGIC;
LMB3_WriteStrobe : IN STD_LOGIC;
LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl3_Ready : OUT STD_LOGIC;
Sl3_Wait : OUT STD_LOGIC;
Sl3_UE : OUT STD_LOGIC;
Sl3_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
S_AXI_CTRL_ACLK : IN STD_LOGIC;
S_AXI_CTRL_ARESETN : IN STD_LOGIC;
S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_AWVALID : IN STD_LOGIC;
S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_CTRL_WVALID : IN STD_LOGIC;
S_AXI_CTRL_WREADY : OUT STD_LOGIC;
S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_BVALID : OUT STD_LOGIC;
S_AXI_CTRL_BREADY : IN STD_LOGIC;
S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_ARVALID : IN STD_LOGIC;
S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_RVALID : OUT STD_LOGIC;
S_AXI_CTRL_RREADY : IN STD_LOGIC;
UE : OUT STD_LOGIC;
CE : OUT STD_LOGIC;
Interrupt : OUT STD_LOGIC
);
END COMPONENT lmb_bram_if_cntlr;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "lmb_bram_if_cntlr,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_ilmb_bram_if_cntlr_0_arch : ARCHITECTURE IS "design_1_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "design_1_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_HIGHADDR=0x00007FFF,C_BASEADDR=0x00000000,C_NUM_LMB=1,C_MASK=0x20000000,C_MASK1=0x00800000,C_MASK2=0x00800000,C_MASK3=0x00800000,C_LMB_AWIDTH=32,C_LMB_DWIDTH=32,C_ECC=0,C_INTERCONNECT=0,C_FAULT_INJECT=0,C_CE_FAILING_REGISTERS=0,C_UE_FAILING_REGISTERS=0,C_ECC_STATUS_REGISTERS=0,C_ECC_ONOFF_REGISTER=0,C_ECC_ONOFF_RESET_VALUE=1,C_CE_COUNTER_WIDTH=0,C_WRITE_ACCESS=2,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
BEGIN
U0 : lmb_bram_if_cntlr
GENERIC MAP (
C_FAMILY => "artix7",
C_HIGHADDR => X"00007FFF",
C_BASEADDR => X"00000000",
C_NUM_LMB => 1,
C_MASK => X"20000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
PORT MAP (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_AddrStrobe => '0',
LMB1_ReadStrobe => '0',
LMB1_WriteStrobe => '0',
LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_AddrStrobe => '0',
LMB2_ReadStrobe => '0',
LMB2_WriteStrobe => '0',
LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_AddrStrobe => '0',
LMB3_ReadStrobe => '0',
LMB3_WriteStrobe => '0',
LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Din_A => BRAM_Din_A,
S_AXI_CTRL_ACLK => '0',
S_AXI_CTRL_ARESETN => '0',
S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_AWVALID => '0',
S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_CTRL_WVALID => '0',
S_AXI_CTRL_BREADY => '0',
S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_ARVALID => '0',
S_AXI_CTRL_RREADY => '0'
);
END design_1_ilmb_bram_if_cntlr_0_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity ctl_unit is
port(clk : in std_logic;
rst : in std_logic;
instruction_in : in std_logic_vector(11 downto 0);
instruction_addr : out std_logic_vector(31 downto 0);
immediate_in : in std_logic_vector(31 downto 0);
immediate_addr : out std_logic_vector(5 downto 0);
ctl_immediate : out std_logic_vector(31 downto 0);
PC_data_out : in std_logic_vector(31 downto 0);
ALU_flags : in std_logic_vector(3 downto 0);
stack_e0 : in std_logic_vector(31 downto 0);
stack_e1 : in std_logic_vector(31 downto 0);
--Control signals
ALU_sel : out std_logic_vector(3 downto 0);
stack_e0_sel : out std_logic_vector(1 downto 0);
stack_e1_sel : out std_logic_vector(1 downto 0);
stack_e2_sel : out std_logic_vector(1 downto 0);
stack_e0_en : out std_logic;
stack_e1_en : out std_logic;
stack_e2_en : out std_logic;
stack_push : out std_logic;
stack_pop : out std_logic;
stack_pop2 : out std_logic;
RS_push : out std_logic;
RS_pop : out std_logic;
mem_we : out std_logic;
PC_load : out std_logic;
PC_inc : out std_logic;
IO_oport_en : out std_logic;
IO_opins_en : out std_logic;
stack_MUX_sel : out std_logic_vector(2 downto 0);
PC_MUX_sel : out std_logic);
end ctl_unit;
architecture Behavioral of ctl_unit is
signal instruction : std_logic_vector(11 downto 0);
signal opcode : std_logic_vector(5 downto 0);
signal ALU_flags_r : std_logic_vector(3 downto 0);
signal ALU_flags_en, ALU_flags_en_r : std_logic;
signal stack_e0_r, stack_e1_r : std_logic_vector(31 downto 0);
begin
--Split the instruction and send addresses out
instruction_addr <= PC_data_out;
immediate_addr <= instruction(5 downto 0);
opcode <= instruction(11 downto 6);
ctl_immediate <= immediate_in;
--Latch in the instruction and other data
latch : process (clk, rst) is
begin
if rst = '1' then
instruction <= (others => '0');
ALU_flags_r <= (others => '0');
stack_e0_r <= (others => '0');
stack_e1_r <= (others => '0');
elsif rising_edge(clk) then
instruction <= instruction_in;
if ALU_flags_en_r = '1' then
ALU_flags_r <= ALU_flags;
end if;
stack_e0_r <= stack_e0;
stack_e1_r <= stack_e1;
end if;
end process;
--Latch the ALU_flags_en signal on falling
latch_fall : process(clk, rst) is
begin
if rst = '1' then
ALU_flags_en_r <= '0';
elsif falling_edge(clk) then
ALU_flags_en_r <= ALU_flags_en;
end if;
end process;
--Decode the instruction
decode : process (opcode, immediate_in, ALU_flags_r, stack_e0_r, stack_e1_r) is
begin
--Default outputs
ALU_sel <= (others => '0');
stack_e0_sel <= (others => '0');
stack_e1_sel <= (others => '0');
stack_e2_sel <= (others => '0');
stack_e0_en <= '0';
stack_e1_en <= '0';
stack_e2_en <= '0';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '0';
RS_push <= '0';
RS_pop <= '0';
mem_we <= '0';
PC_load <= '0';
PC_inc <= '1';
IO_oport_en <= '0';
IO_opins_en <= '0';
stack_MUX_sel <= (others => '0');
PC_MUX_sel <= '0';
ALU_flags_en <= '0';
if opcode(5 downto 4) = "00" then --Arithmetic/Logic instruction
--Update the flags register
ALU_flags_en <= '1';
--Catch a couple special cases, nop and cp
if opcode(3 downto 0) = "0000" then --nop
--do nothing, leave the defaults as defaults
elsif opcode(3 downto 0) = "0110" then --cp
--send the operands to the ALU to generate condition flags, but don't manipulate the stack
ALU_sel <= opcode(3 downto 0) - 1;
elsif ((opcode(3 downto 0) >= "0001") and (opcode(3 downto 0) <= "0101"))
or (opcode(3 downto 0) = "1011") or (opcode(3 downto 0) = "1100") then --Two-operand instructions
ALU_sel <= opcode(3 downto 0) - 1;
stack_e0_sel <= (others => '0'); --e0 gets data_in
stack_e1_sel <= "01"; --e1 gets e2
stack_e2_sel <= "01"; --e2 gets the top of the storage elements
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '1'; --Pop one off the storage elements
stack_pop2 <= '0';
stack_MUX_sel <= "001"; --Data_in gets ALU_result
elsif (opcode(3 downto 0) >= "0111") and (opcode(3 downto 0) <= "1010") then --Single-operand instructions
ALU_sel <= opcode(3 downto 0) - 1;
stack_e0_sel <= (others => '0'); --e0 gets data_in
stack_e1_sel <= (others => '0');
stack_e2_sel <= (others => '0');
stack_e0_en <= '1';
stack_e1_en <= '0';
stack_e2_en <= '0';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '0';
stack_MUX_sel <= "001"; --Data_in gets ALU_result
end if;
elsif opcode(5 downto 4) = "01" then --Stack manipulation instruction
--This is just going to have to be brute-force, no real decoding here
case opcode(3 downto 0) is
when x"0" => --drop
stack_e0_sel <= "01";
stack_e1_sel <= "01";
stack_e2_sel <= "01";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '1';
stack_pop2 <= '0';
when x"1" => --swap
stack_e0_sel <= "01";
stack_e1_sel <= "00";
stack_e2_sel <= "00";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '0';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '0';
when x"2" => --nrot
stack_e0_sel <= "01";
stack_e1_sel <= "01";
stack_e2_sel <= "10";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '0';
when x"3" => --rot
stack_e0_sel <= "10";
stack_e1_sel <= "00";
stack_e2_sel <= "00";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '0';
when x"4" => --push
stack_e0_sel <= "00";
stack_e1_sel <= "00";
stack_e2_sel <= "00";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '1';
stack_pop <= '0';
stack_pop2 <= '0';
stack_MUX_sel <= "000"; --Data_in gets ctl_immediate
when x"5" => --dup
stack_e0_sel <= "00";
stack_e1_sel <= "00";
stack_e2_sel <= "00";
stack_e0_en <= '0';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '1';
stack_pop <= '0';
stack_pop2 <= '0';
when x"6" => --nrd
stack_e0_sel <= "10";
stack_e1_sel <= "00";
stack_e2_sel <= "01";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '1';
stack_pop2 <= '0';
when x"7" => --rd
stack_e0_sel <= "00";
stack_e1_sel <= "00";
stack_e2_sel <= "01";
stack_e0_en <= '0';
stack_e1_en <= '0';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '1';
stack_pop2 <= '0';
when x"8" => --nrds
stack_e0_sel <= "00";
stack_e1_sel <= "01";
stack_e2_sel <= "01";
stack_e0_en <= '0';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '1';
stack_pop2 <= '0';
when x"9" => --rds
stack_e0_sel <= "01";
stack_e1_sel <= "00";
stack_e2_sel <= "01";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '1';
stack_pop2 <= '0';
when x"A" => --over
stack_e0_sel <= "01";
stack_e1_sel <= "00";
stack_e2_sel <= "00";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '1';
stack_pop <= '0';
stack_pop2 <= '0';
when others =>
--do nothing
end case;
elsif opcode(5 downto 4) = "10" then --Program control instruction
if opcode(3 downto 0) = "0000" then --JP instruction
--Pop one from the stack
stack_e0_sel <= "01";
stack_e1_sel <= "01";
stack_e2_sel <= "01";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '1';
stack_pop2 <= '0';
--Set up the PC to take the top element of the data stack
PC_MUX_sel <= '0';
PC_load <= '1';
PC_inc <= '0';
elsif opcode(3 downto 0) = "0001" then --BRN instruction
--Pop two from the stack
stack_e0_sel <= "10";
stack_e1_sel <= "10";
stack_e2_sel <= "11";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '1';
--Check the selected flag to see if it's true
if ALU_flags_r(conv_integer(unsigned(stack_e1_r))) = '1' then
--Set up the PC to take the top element of the data stack
PC_MUX_sel <= '0';
PC_load <= '1';
PC_inc <= '0';
end if;
elsif opcode(3 downto 0) = "0010" then --RET instruction
--Set up the PC to take the top element of the return stack and pop the return stack
PC_MUX_sel <= '1';
PC_load <= '1';
PC_inc <= '0';
RS_pop <= '1';
elsif opcode(3 downto 0) = "0011" then --PSHPC instruction
RS_push <= '1';
end if;
elsif opcode(5 downto 4) = "11" then --Memory and I/O instruction
if opcode(3 downto 0) = "0000" then --RD_MEM instruction
--Replace the top element of the stack
stack_e0_sel <= "00";
stack_e1_sel <= "00";
stack_e2_sel <= "00";
stack_e0_en <= '1';
stack_e1_en <= '0';
stack_e2_en <= '0';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '0';
stack_MUX_sel <= "100"; --Data_in gets mem_data_out
elsif opcode(3 downto 0) = "0001" then --WR_MEM instruction
--Pop two from the stack
stack_e0_sel <= "10";
stack_e1_sel <= "10";
stack_e2_sel <= "11";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '1';
--enable writing
mem_we <= '1';
elsif opcode(3 downto 0) = "0010" then --RD_PRT instruction
--Push data onto the stack
stack_e0_sel <= "00";
stack_e1_sel <= "00";
stack_e2_sel <= "00";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '1';
stack_pop <= '0';
stack_pop2 <= '0';
stack_MUX_sel <= "011"; --Data_in gets IO_iport_data
elsif opcode(3 downto 0) = "0011" then --WR_PRT instruction
--Pop one from the stack
stack_e0_sel <= "01";
stack_e1_sel <= "01";
stack_e2_sel <= "01";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '1';
stack_pop2 <= '0';
--enable writing to the port
IO_oport_en <= '1';
elsif opcode(3 downto 0) = "0100" then --RD_PIN instruction
--Replace the top element of the stack
stack_e0_sel <= "00";
stack_e1_sel <= "00";
stack_e2_sel <= "00";
stack_e0_en <= '1';
stack_e1_en <= '0';
stack_e2_en <= '0';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '0';
stack_MUX_sel <= "010"; --Data_in gets IO_ipins_data
elsif opcode(3 downto 0) = "0101" then --WR_PIN instruction
--Pop two from the stack
stack_e0_sel <= "10";
stack_e1_sel <= "10";
stack_e2_sel <= "11";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '1';
--enable writing to the pins
IO_opins_en <= '1';
end if;
end if;
end process;
end Behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cordic:6.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cordic_v6_0_11;
USE cordic_v6_0_11.cordic_v6_0_11;
ENTITY arctan IS
PORT (
aclk : IN STD_LOGIC;
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END arctan;
ARCHITECTURE arctan_arch OF arctan IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF arctan_arch: ARCHITECTURE IS "yes";
COMPONENT cordic_v6_0_11 IS
GENERIC (
C_ARCHITECTURE : INTEGER;
C_CORDIC_FUNCTION : INTEGER;
C_COARSE_ROTATE : INTEGER;
C_DATA_FORMAT : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_ACLKEN : INTEGER;
C_HAS_ACLK : INTEGER;
C_HAS_S_AXIS_CARTESIAN : INTEGER;
C_HAS_S_AXIS_PHASE : INTEGER;
C_HAS_ARESETN : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_ITERATIONS : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_FORMAT : INTEGER;
C_PIPELINE_MODE : INTEGER;
C_PRECISION : INTEGER;
C_ROUND_MODE : INTEGER;
C_SCALE_COMP : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_HAS_S_AXIS_PHASE_TUSER : INTEGER;
C_HAS_S_AXIS_PHASE_TLAST : INTEGER;
C_S_AXIS_PHASE_TDATA_WIDTH : INTEGER;
C_S_AXIS_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TUSER : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TLAST : INTEGER;
C_S_AXIS_CARTESIAN_TDATA_WIDTH : INTEGER;
C_S_AXIS_CARTESIAN_TUSER_WIDTH : INTEGER;
C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tready : OUT STD_LOGIC;
s_axis_cartesian_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_cartesian_tlast : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tready : IN STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tlast : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT cordic_v6_0_11;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
BEGIN
U0 : cordic_v6_0_11
GENERIC MAP (
C_ARCHITECTURE => 2,
C_CORDIC_FUNCTION => 3,
C_COARSE_ROTATE => 0,
C_DATA_FORMAT => 0,
C_XDEVICEFAMILY => "zynq",
C_HAS_ACLKEN => 0,
C_HAS_ACLK => 1,
C_HAS_S_AXIS_CARTESIAN => 1,
C_HAS_S_AXIS_PHASE => 0,
C_HAS_ARESETN => 0,
C_INPUT_WIDTH => 16,
C_ITERATIONS => 0,
C_OUTPUT_WIDTH => 16,
C_PHASE_FORMAT => 0,
C_PIPELINE_MODE => -2,
C_PRECISION => 0,
C_ROUND_MODE => 0,
C_SCALE_COMP => 0,
C_THROTTLE_SCHEME => 3,
C_TLAST_RESOLUTION => 0,
C_HAS_S_AXIS_PHASE_TUSER => 0,
C_HAS_S_AXIS_PHASE_TLAST => 0,
C_S_AXIS_PHASE_TDATA_WIDTH => 16,
C_S_AXIS_PHASE_TUSER_WIDTH => 1,
C_HAS_S_AXIS_CARTESIAN_TUSER => 0,
C_HAS_S_AXIS_CARTESIAN_TLAST => 0,
C_S_AXIS_CARTESIAN_TDATA_WIDTH => 32,
C_S_AXIS_CARTESIAN_TUSER_WIDTH => 1,
C_M_AXIS_DOUT_TDATA_WIDTH => 16,
C_M_AXIS_DOUT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_phase_tlast => '0',
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
s_axis_cartesian_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_cartesian_tlast => '0',
s_axis_cartesian_tdata => s_axis_cartesian_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tready => '0',
m_axis_dout_tdata => m_axis_dout_tdata
);
END arctan_arch;
|
--------------------------------------------------------------------------------
-- Title : Whisbone Bus Interconnection
-- Project :
--------------------------------------------------------------------------------
-- File : wb_bus.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created :
--------------------------------------------------------------------------------
-- Simulator : Modelsim
-- Synthesis : Quartus II
--------------------------------------------------------------------------------
-- Description :
-- Master # 0 1 2
-- Slave : 0 1 0 0
-- Slave : 1 1 0 0
-- Slave : 2 1 0 1
-- Slave : 3 1 1 1
-- Slave : 4 0 1 1
-- Master 0 = 4 connection(s)
-- Master 1 = 2 connection(s)
-- Master 2 = 3 connection(s)
-- Slave 0 = 1 connection(s)
-- Slave 1 = 1 connection(s)
-- Slave 2 = 2 connection(s)
-- Slave 3 = 3 connection(s)
-- Slave 4 = 2 connection(s)
--
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wb_pkg.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- Revision: 1.6
--
--------------------------------------------------------------------------------
LIBRARY ieee, work;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.wb_pkg.ALL;
ENTITY wb_bus IS
GENERIC (
sets : std_logic_vector(3 DOWNTO 0) := "1110";
timeout : integer := 5000 );
PORT (
clk : IN std_logic;
rst : IN std_logic;
-- Master Bus
wbmo_0 : IN wbo_type;
wbmi_0 : OUT wbi_type;
wbmo_0_cyc : IN std_logic_vector(3 DOWNTO 0);
wbmo_1 : IN wbo_type;
wbmi_1 : OUT wbi_type;
wbmo_1_cyc : IN std_logic_vector(1 DOWNTO 0);
wbmo_2 : IN wbo_type;
wbmi_2 : OUT wbi_type;
wbmo_2_cyc : IN std_logic_vector(2 DOWNTO 0);
-- Slave Bus
wbso_0 : IN wbi_type;
wbsi_0 : OUT wbo_type;
wbsi_0_cyc : OUT std_logic;
wbso_1 : IN wbi_type;
wbsi_1 : OUT wbo_type;
wbsi_1_cyc : OUT std_logic;
wbso_2 : IN wbi_type;
wbsi_2 : OUT wbo_type;
wbsi_2_cyc : OUT std_logic;
wbso_3 : IN wbi_type;
wbsi_3 : OUT wbo_type;
wbsi_3_cyc : OUT std_logic;
wbso_4 : IN wbi_type;
wbsi_4 : OUT wbo_type;
wbsi_4_cyc : OUT std_logic
);
END wb_bus;
ARCHITECTURE wb_bus_arch OF wb_bus IS
-- COMPONENT DECLARATIONS
COMPONENT switch_fab_1
GENERIC (
registered : IN boolean
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic
);
END COMPONENT;
COMPONENT switch_fab_2
GENERIC (
registered : IN boolean
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
cyc_1 : IN std_logic;
ack_1 : OUT std_logic;
err_1 : OUT std_logic;
wbo_1 : IN wbo_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic
);
END COMPONENT;
COMPONENT switch_fab_3
GENERIC (
registered : IN boolean
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
cyc_1 : IN std_logic;
ack_1 : OUT std_logic;
err_1 : OUT std_logic;
wbo_1 : IN wbo_type;
cyc_2 : IN std_logic;
ack_2 : OUT std_logic;
err_2 : OUT std_logic;
wbo_2 : IN wbo_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic
);
END COMPONENT;
-- synthesis translate_off
COMPONENT wbmon
GENERIC (
wbname : string := "wbmon";
sets : std_logic_vector(3 DOWNTO 0) := "1110";
-- 1110
-- ||||
-- |||+- write notes to Modelsim out
-- ||+-- write errors to Modelsim out
-- |+--- write notes to file out
-- +---- write errors to file out
timeout : integer := 100
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
adr : IN std_logic_vector(31 DOWNTO 0);
sldat_i : IN std_logic_vector(31 DOWNTO 0);
sldat_o : IN std_logic_vector(31 DOWNTO 0);
cti : IN std_logic_vector(2 DOWNTO 0);
sel : IN std_logic_vector(3 DOWNTO 0);
cyc : IN std_logic;
stb : IN std_logic;
ack : IN std_logic;
err : IN std_logic;
we : IN std_logic
);
END COMPONENT;
-- synthesis translate_on
-- SIGNAL DEFINITIONS
SIGNAL wbs_0_ack : std_logic;
SIGNAL wbs_0_err : std_logic;
SIGNAL wbs_1_ack : std_logic;
SIGNAL wbs_1_err : std_logic;
SIGNAL wbs_2_ack : std_logic_vector(1 DOWNTO 0);
SIGNAL wbs_2_err : std_logic_vector(1 DOWNTO 0);
SIGNAL wbs_3_ack : std_logic_vector(2 DOWNTO 0);
SIGNAL wbs_3_err : std_logic_vector(2 DOWNTO 0);
SIGNAL wbs_4_ack : std_logic_vector(1 DOWNTO 0);
SIGNAL wbs_4_err : std_logic_vector(1 DOWNTO 0);
SIGNAL wbsi_0_int : wbo_type;
SIGNAL wbsi_0_cyc_int : std_logic;
SIGNAL wbsi_1_int : wbo_type;
SIGNAL wbsi_1_cyc_int : std_logic;
SIGNAL wbsi_2_int : wbo_type;
SIGNAL wbsi_2_cyc_int : std_logic;
SIGNAL wbsi_3_int : wbo_type;
SIGNAL wbsi_3_cyc_int : std_logic;
SIGNAL wbsi_4_int : wbo_type;
SIGNAL wbsi_4_cyc_int : std_logic;
SIGNAL wbmi_0_int : wbi_type;
SIGNAL wbmo_0_cyc_s : std_logic;
SIGNAL wbmi_1_int : wbi_type;
SIGNAL wbmo_1_cyc_s : std_logic;
SIGNAL wbmi_2_int : wbi_type;
SIGNAL wbmo_2_cyc_s : std_logic;
BEGIN
wbsi_0 <= wbsi_0_int;
wbsi_0_cyc <= wbsi_0_cyc_int;
wbsi_1 <= wbsi_1_int;
wbsi_1_cyc <= wbsi_1_cyc_int;
wbsi_2 <= wbsi_2_int;
wbsi_2_cyc <= wbsi_2_cyc_int;
wbsi_3 <= wbsi_3_int;
wbsi_3_cyc <= wbsi_3_cyc_int;
wbsi_4 <= wbsi_4_int;
wbsi_4_cyc <= wbsi_4_cyc_int;
wbmi_0 <= wbmi_0_int;
wbmi_1 <= wbmi_1_int;
wbmi_2 <= wbmi_2_int;
-- data multiplexer for master #0
data_mux (
cyc => wbmo_0_cyc,
data_in_0 => wbso_0.dat,
data_in_1 => wbso_1.dat,
data_in_2 => wbso_2.dat,
data_in_3 => wbso_3.dat,
data_out => wbmi_0_int.dat
);
wbmi_0_int.ack <= wbs_0_ack OR wbs_1_ack OR wbs_2_ack(0) OR wbs_3_ack(0);
wbmi_0_int.err <= wbs_0_err OR wbs_1_err OR wbs_2_err(0) OR wbs_3_err(0);
-- data multiplexer for master #1
data_mux (
cyc => wbmo_1_cyc,
data_in_0 => wbso_3.dat,
data_in_1 => wbso_4.dat,
data_out => wbmi_1_int.dat
);
wbmi_1_int.ack <= wbs_3_ack(1) OR wbs_4_ack(0);
wbmi_1_int.err <= wbs_3_err(1) OR wbs_4_err(0);
-- data multiplexer for master #2
data_mux (
cyc => wbmo_2_cyc,
data_in_0 => wbso_2.dat,
data_in_1 => wbso_3.dat,
data_in_2 => wbso_4.dat,
data_out => wbmi_2_int.dat
);
wbmi_2_int.ack <= wbs_2_ack(1) OR wbs_3_ack(2) OR wbs_4_ack(1);
wbmi_2_int.err <= wbs_2_err(1) OR wbs_3_err(2) OR wbs_4_err(1);
-- sf for slave #0:
sf_0: switch_fab_1
GENERIC MAP (
registered => FALSE
)
PORT MAP (
clk => clk,
rst => rst,
-- master busses:
wbo_0 => wbmo_0,
cyc_0 => wbmo_0_cyc(0),
ack_0 => wbs_0_ack,
err_0 => wbs_0_err,
-- slave bus:
wbo_slave => wbso_0,
wbi_slave => wbsi_0_int,
wbi_slave_cyc => wbsi_0_cyc_int
);
-- sf for slave #1:
sf_1: switch_fab_1
GENERIC MAP (
registered => FALSE
)
PORT MAP (
clk => clk,
rst => rst,
-- master busses:
wbo_0 => wbmo_0,
cyc_0 => wbmo_0_cyc(1),
ack_0 => wbs_1_ack,
err_0 => wbs_1_err,
-- slave bus:
wbo_slave => wbso_1,
wbi_slave => wbsi_1_int,
wbi_slave_cyc => wbsi_1_cyc_int
);
-- sf for slave #2:
sf_2: switch_fab_2
GENERIC MAP (
registered => FALSE
)
PORT MAP (
clk => clk,
rst => rst,
-- master busses:
wbo_0 => wbmo_0,
cyc_0 => wbmo_0_cyc(2),
ack_0 => wbs_2_ack(0),
err_0 => wbs_2_err(0),
wbo_1 => wbmo_2,
cyc_1 => wbmo_2_cyc(0),
ack_1 => wbs_2_ack(1),
err_1 => wbs_2_err(1),
-- slave bus:
wbo_slave => wbso_2,
wbi_slave => wbsi_2_int,
wbi_slave_cyc => wbsi_2_cyc_int
);
-- sf for slave #3:
sf_3: switch_fab_3
GENERIC MAP (
registered => FALSE
)
PORT MAP (
clk => clk,
rst => rst,
-- master busses:
wbo_0 => wbmo_0,
cyc_0 => wbmo_0_cyc(3),
ack_0 => wbs_3_ack(0),
err_0 => wbs_3_err(0),
wbo_1 => wbmo_1,
cyc_1 => wbmo_1_cyc(0),
ack_1 => wbs_3_ack(1),
err_1 => wbs_3_err(1),
wbo_2 => wbmo_2,
cyc_2 => wbmo_2_cyc(1),
ack_2 => wbs_3_ack(2),
err_2 => wbs_3_err(2),
-- slave bus:
wbo_slave => wbso_3,
wbi_slave => wbsi_3_int,
wbi_slave_cyc => wbsi_3_cyc_int
);
-- sf for slave #4:
sf_4: switch_fab_2
GENERIC MAP (
registered => FALSE
)
PORT MAP (
clk => clk,
rst => rst,
-- master busses:
wbo_0 => wbmo_1,
cyc_0 => wbmo_1_cyc(1),
ack_0 => wbs_4_ack(0),
err_0 => wbs_4_err(0),
wbo_1 => wbmo_2,
cyc_1 => wbmo_2_cyc(2),
ack_1 => wbs_4_ack(1),
err_1 => wbs_4_err(1),
-- slave bus:
wbo_slave => wbso_4,
wbi_slave => wbsi_4_int,
wbi_slave_cyc => wbsi_4_cyc_int
);
-- synthesis translate_off
wbmo_0_cyc_s <= '1' WHEN wbmo_0_cyc = 0 ELSE '1';
wbm_0: wbmon
GENERIC MAP (
wbname => "wbm_0",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbmo_0.adr,
sldat_i => wbmo_0.dat,
sldat_o => wbmi_0_int.dat,
cti => wbmo_0.cti,
sel => wbmo_0.sel,
cyc => wbmo_0_cyc_s,
stb => wbmo_0.stb,
ack => wbmi_0_int.ack,
err => wbmi_0_int.err,
we => wbmo_0.we
);
wbmo_1_cyc_s <= '1' WHEN wbmo_1_cyc = 0 ELSE '1';
wbm_1: wbmon
GENERIC MAP (
wbname => "wbm_1",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbmo_1.adr,
sldat_i => wbmo_1.dat,
sldat_o => wbmi_1_int.dat,
cti => wbmo_1.cti,
sel => wbmo_1.sel,
cyc => wbmo_1_cyc_s,
stb => wbmo_1.stb,
ack => wbmi_1_int.ack,
err => wbmi_1_int.err,
we => wbmo_1.we
);
wbmo_2_cyc_s <= '1' WHEN wbmo_2_cyc = 0 ELSE '1';
wbm_2: wbmon
GENERIC MAP (
wbname => "wbm_2",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbmo_2.adr,
sldat_i => wbmo_2.dat,
sldat_o => wbmi_2_int.dat,
cti => wbmo_2.cti,
sel => wbmo_2.sel,
cyc => wbmo_2_cyc_s,
stb => wbmo_2.stb,
ack => wbmi_2_int.ack,
err => wbmi_2_int.err,
we => wbmo_2.we
);
wbs_0: wbmon
GENERIC MAP (
wbname => "wbs_0",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbsi_0_int.adr,
sldat_i => wbsi_0_int.dat,
sldat_o => wbso_0.dat,
cti => wbsi_0_int.cti,
sel => wbsi_0_int.sel,
cyc => wbsi_0_cyc_int,
stb => wbsi_0_int.stb,
ack => wbso_0.ack,
err => wbso_0.err,
we => wbsi_0_int.we
);
wbs_1: wbmon
GENERIC MAP (
wbname => "wbs_1",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbsi_1_int.adr,
sldat_i => wbsi_1_int.dat,
sldat_o => wbso_1.dat,
cti => wbsi_1_int.cti,
sel => wbsi_1_int.sel,
cyc => wbsi_1_cyc_int,
stb => wbsi_1_int.stb,
ack => wbso_1.ack,
err => wbso_1.err,
we => wbsi_1_int.we
);
wbs_2: wbmon
GENERIC MAP (
wbname => "wbs_2",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbsi_2_int.adr,
sldat_i => wbsi_2_int.dat,
sldat_o => wbso_2.dat,
cti => wbsi_2_int.cti,
sel => wbsi_2_int.sel,
cyc => wbsi_2_cyc_int,
stb => wbsi_2_int.stb,
ack => wbso_2.ack,
err => wbso_2.err,
we => wbsi_2_int.we
);
wbs_3: wbmon
GENERIC MAP (
wbname => "wbs_3",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbsi_3_int.adr,
sldat_i => wbsi_3_int.dat,
sldat_o => wbso_3.dat,
cti => wbsi_3_int.cti,
sel => wbsi_3_int.sel,
cyc => wbsi_3_cyc_int,
stb => wbsi_3_int.stb,
ack => wbso_3.ack,
err => wbso_3.err,
we => wbsi_3_int.we
);
wbs_4: wbmon
GENERIC MAP (
wbname => "wbs_4",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbsi_4_int.adr,
sldat_i => wbsi_4_int.dat,
sldat_o => wbso_4.dat,
cti => wbsi_4_int.cti,
sel => wbsi_4_int.sel,
cyc => wbsi_4_cyc_int,
stb => wbsi_4_int.stb,
ack => wbso_4.ack,
err => wbso_4.err,
we => wbsi_4_int.we
);
-- synthesis translate_on
END wb_bus_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc219.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p06n03i00219ent IS
type e is (EMIN,ETYP,EMAX);
END c03s01b01x00p06n03i00219ent;
ARCHITECTURE c03s01b01x00p06n03i00219arch OF c03s01b01x00p06n03i00219ent IS
BEGIN
TESTING: PROCESS
variable e1:integer;
BEGIN
e1 := e'pos(EMIN);
assert NOT(e1=0)
report "***PASSED TEST: c03s01b01x00p06n03i00219"
severity NOTE;
assert (e1=0)
report "***FAILED TEST: c03s01b01x00p06n03i00219 - The position number of the value of the first listed enumeration literal is zero."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p06n03i00219arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc219.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p06n03i00219ent IS
type e is (EMIN,ETYP,EMAX);
END c03s01b01x00p06n03i00219ent;
ARCHITECTURE c03s01b01x00p06n03i00219arch OF c03s01b01x00p06n03i00219ent IS
BEGIN
TESTING: PROCESS
variable e1:integer;
BEGIN
e1 := e'pos(EMIN);
assert NOT(e1=0)
report "***PASSED TEST: c03s01b01x00p06n03i00219"
severity NOTE;
assert (e1=0)
report "***FAILED TEST: c03s01b01x00p06n03i00219 - The position number of the value of the first listed enumeration literal is zero."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p06n03i00219arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc219.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p06n03i00219ent IS
type e is (EMIN,ETYP,EMAX);
END c03s01b01x00p06n03i00219ent;
ARCHITECTURE c03s01b01x00p06n03i00219arch OF c03s01b01x00p06n03i00219ent IS
BEGIN
TESTING: PROCESS
variable e1:integer;
BEGIN
e1 := e'pos(EMIN);
assert NOT(e1=0)
report "***PASSED TEST: c03s01b01x00p06n03i00219"
severity NOTE;
assert (e1=0)
report "***FAILED TEST: c03s01b01x00p06n03i00219 - The position number of the value of the first listed enumeration literal is zero."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p06n03i00219arch;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity tb_05_04 is
end entity tb_05_04;
architecture test of tb_05_04 is
signal a, b, sel, z : bit;
begin
dut : entity work.mux2(behavioral)
port map ( a => a, b => b, sel => sel, z => z );
stimulus : process is
subtype stim_vector_type is bit_vector(0 to 3);
type stim_vector_array is array ( natural range <> ) of stim_vector_type;
constant stim_vector : stim_vector_array
:= ( "0000",
"0100",
"1001",
"1101",
"0010",
"0111",
"1010",
"1111" );
begin
for i in stim_vector'range loop
(a, b, sel) <= stim_vector(i)(0 to 2);
wait for 10 ns;
assert z = stim_vector(i)(3);
end loop;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity tb_05_04 is
end entity tb_05_04;
architecture test of tb_05_04 is
signal a, b, sel, z : bit;
begin
dut : entity work.mux2(behavioral)
port map ( a => a, b => b, sel => sel, z => z );
stimulus : process is
subtype stim_vector_type is bit_vector(0 to 3);
type stim_vector_array is array ( natural range <> ) of stim_vector_type;
constant stim_vector : stim_vector_array
:= ( "0000",
"0100",
"1001",
"1101",
"0010",
"0111",
"1010",
"1111" );
begin
for i in stim_vector'range loop
(a, b, sel) <= stim_vector(i)(0 to 2);
wait for 10 ns;
assert z = stim_vector(i)(3);
end loop;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity tb_05_04 is
end entity tb_05_04;
architecture test of tb_05_04 is
signal a, b, sel, z : bit;
begin
dut : entity work.mux2(behavioral)
port map ( a => a, b => b, sel => sel, z => z );
stimulus : process is
subtype stim_vector_type is bit_vector(0 to 3);
type stim_vector_array is array ( natural range <> ) of stim_vector_type;
constant stim_vector : stim_vector_array
:= ( "0000",
"0100",
"1001",
"1101",
"0010",
"0111",
"1010",
"1111" );
begin
for i in stim_vector'range loop
(a, b, sel) <= stim_vector(i)(0 to 2);
wait for 10 ns;
assert z = stim_vector(i)(3);
end loop;
wait;
end process stimulus;
end architecture test;
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
use work.dspalu_pac.all;
-------------------------------------------------------------------------------
entity setmem is
port (
--@inputs
clk : in std_logic;
op_en : in std_logic;
length_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
newval_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
--@outputs;
dsp_bus : out t_dsp_bus
);
end setmem;
--=----------------------------------------------------------------------------
architecture archi_setmem of setmem is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_dsp_bus : t_dsp_bus;
type t_setmem_state is (st_init, st_set);
signal s_state : t_setmem_state;
signal s_length : unsigned((cmdreg_width - 1) downto 0);
signal s_length_moins : unsigned((cmdreg_width - 1) downto 0);
signal s_new_val : std_logic_vector((sig_width - 1) downto 0);
signal s_wr : std_logic;
begin -- archs_setmem
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_setmem : process (clk)
begin -- process p_setmem
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_state <= st_init;
--s_dsp_bus <= c_dsp_bus_init;
s_dsp_bus.op_done <= '0';
-- memory 0
-- s_dsp_bus.data_out_m0 <= (others => '0');
--s_dsp_bus.c_en_m0 <= '0';
-- memory 1
-- s_dsp_bus.data_out_m1 <= (others => '0');
--s_dsp_bus.c_en_m1 <= '0';
-- memory 2
-- s_dsp_bus.data_out_m2 <= (others => '0');
--s_dsp_bus.c_en_m2 <= '0';
-- alu
--s_dsp_bus.mul_in_a1 <= (others <= '0');
--s_dsp_bus.mul_in_b1 <= (others <= '0');
--s_dsp_bus.mul_in_a2 <= (others <= '0');
--s_dsp_bus.mul_in_b2 <= (others <= '0');
s_dsp_bus.addr_m1 <= (others => '0');
s_dsp_bus.acc_mode1 <= acc_store;
s_dsp_bus.acc_mode2 <= acc_store;
s_dsp_bus.alu_select <= alu_mul;
-- global counter
--s_dsp_bus.gcounter_reset <= '0';
-------------------------------------------------------------------------------
-- operation management
-------------------------------------------------------------------------------
else
case s_state is
when st_init =>
s_dsp_bus.addr_m1 <= (others => '0');
s_wr <= '0';
if s_dsp_bus.op_done = '0' then
s_state <= st_set;
s_wr <= '1';
end if;
when st_set =>
s_wr <= '1';
if(s_dsp_bus.addr_m1 = s_length_moins) then
s_state <= st_init;
s_dsp_bus.op_done <= '1';
s_wr <= '0';
else
s_dsp_bus.addr_m1 <= s_dsp_bus.addr_m1 + 1;
end if;
when others => null;
end case;
end if;
end if;
end process p_setmem;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
dsp_bus <= s_dsp_bus;
s_dsp_bus.addr_w_m0 <= s_dsp_bus.addr_m1;
s_dsp_bus.data_out_m2 <= s_new_val;
s_dsp_bus.data_out_m0 <= s_new_val;
s_dsp_bus.data_out_m1 <= s_new_val;
-- s_dsp_bus.data_out_m1 <= s_dsp_bus.addr_m1;
s_dsp_bus.addr_w_m0 <= s_dsp_bus.addr_m1;
s_dsp_bus.addr_m2 <= s_dsp_bus.addr_m1;
-- write bit ctrl
s_dsp_bus.wr_en_m0 <= s_wr when opflag_select(opflagbit_m0) = '1' else '0';
s_dsp_bus.wr_en_m1 <= s_wr when opflag_select(opflagbit_m1) = '1' else '0';
s_dsp_bus.wr_en_m2 <= s_wr when opflag_select(opflagbit_m2) = '1' else '0';
-- chip enable
s_dsp_bus.c_en_m0 <= '1';
s_dsp_bus.c_en_m1 <= '1';
s_dsp_bus.c_en_m2 <= '1';
s_dsp_bus.gcounter_reset <= '1';
s_length <= unsigned(length_reg);
s_length_moins <= s_length - 1;
s_new_val <= newval_reg;
end archi_setmem;
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
use work.dspalu_pac.all;
-------------------------------------------------------------------------------
entity setmem is
port (
--@inputs
clk : in std_logic;
op_en : in std_logic;
length_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
newval_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
--@outputs;
dsp_bus : out t_dsp_bus
);
end setmem;
--=----------------------------------------------------------------------------
architecture archi_setmem of setmem is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_dsp_bus : t_dsp_bus;
type t_setmem_state is (st_init, st_set);
signal s_state : t_setmem_state;
signal s_length : unsigned((cmdreg_width - 1) downto 0);
signal s_length_moins : unsigned((cmdreg_width - 1) downto 0);
signal s_new_val : std_logic_vector((sig_width - 1) downto 0);
signal s_wr : std_logic;
begin -- archs_setmem
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_setmem : process (clk)
begin -- process p_setmem
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_state <= st_init;
--s_dsp_bus <= c_dsp_bus_init;
s_dsp_bus.op_done <= '0';
-- memory 0
-- s_dsp_bus.data_out_m0 <= (others => '0');
--s_dsp_bus.c_en_m0 <= '0';
-- memory 1
-- s_dsp_bus.data_out_m1 <= (others => '0');
--s_dsp_bus.c_en_m1 <= '0';
-- memory 2
-- s_dsp_bus.data_out_m2 <= (others => '0');
--s_dsp_bus.c_en_m2 <= '0';
-- alu
--s_dsp_bus.mul_in_a1 <= (others <= '0');
--s_dsp_bus.mul_in_b1 <= (others <= '0');
--s_dsp_bus.mul_in_a2 <= (others <= '0');
--s_dsp_bus.mul_in_b2 <= (others <= '0');
s_dsp_bus.addr_m1 <= (others => '0');
s_dsp_bus.acc_mode1 <= acc_store;
s_dsp_bus.acc_mode2 <= acc_store;
s_dsp_bus.alu_select <= alu_mul;
-- global counter
--s_dsp_bus.gcounter_reset <= '0';
-------------------------------------------------------------------------------
-- operation management
-------------------------------------------------------------------------------
else
case s_state is
when st_init =>
s_dsp_bus.addr_m1 <= (others => '0');
s_wr <= '0';
if s_dsp_bus.op_done = '0' then
s_state <= st_set;
s_wr <= '1';
end if;
when st_set =>
s_wr <= '1';
if(s_dsp_bus.addr_m1 = s_length_moins) then
s_state <= st_init;
s_dsp_bus.op_done <= '1';
s_wr <= '0';
else
s_dsp_bus.addr_m1 <= s_dsp_bus.addr_m1 + 1;
end if;
when others => null;
end case;
end if;
end if;
end process p_setmem;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
dsp_bus <= s_dsp_bus;
s_dsp_bus.addr_w_m0 <= s_dsp_bus.addr_m1;
s_dsp_bus.data_out_m2 <= s_new_val;
s_dsp_bus.data_out_m0 <= s_new_val;
s_dsp_bus.data_out_m1 <= s_new_val;
-- s_dsp_bus.data_out_m1 <= s_dsp_bus.addr_m1;
s_dsp_bus.addr_w_m0 <= s_dsp_bus.addr_m1;
s_dsp_bus.addr_m2 <= s_dsp_bus.addr_m1;
-- write bit ctrl
s_dsp_bus.wr_en_m0 <= s_wr when opflag_select(opflagbit_m0) = '1' else '0';
s_dsp_bus.wr_en_m1 <= s_wr when opflag_select(opflagbit_m1) = '1' else '0';
s_dsp_bus.wr_en_m2 <= s_wr when opflag_select(opflagbit_m2) = '1' else '0';
-- chip enable
s_dsp_bus.c_en_m0 <= '1';
s_dsp_bus.c_en_m1 <= '1';
s_dsp_bus.c_en_m2 <= '1';
s_dsp_bus.gcounter_reset <= '1';
s_length <= unsigned(length_reg);
s_length_moins <= s_length - 1;
s_new_val <= newval_reg;
end archi_setmem;
|
entity test is
subtype t is foo(open)(bar);
end;
|
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: data_path - Behavioral
-- Create Date: 13:24:10 10/29/2009
-- Description: the data path of a CPU.
--
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
use work.common.ALL;
entity data_path is
port( I_CLK : in std_logic;
I_CE : in std_logic;
I_ALU_OP : in std_logic_vector( 4 downto 0);
I_AMOD : in std_logic_vector( 5 downto 0);
I_BIT : in std_logic_vector( 3 downto 0);
I_DDDDD : in std_logic_vector( 4 downto 0);
I_DIN : in std_logic_vector(15 downto 0);
I_IMM : in std_logic_vector(15 downto 0);
I_JADR : in std_logic_vector(15 downto 0);
I_OPC : in std_logic_vector(15 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_PC_OP : in std_logic_vector( 2 downto 0);
I_PMS : in std_logic; -- program memory select
I_RD_M : in std_logic;
I_RRRRR : in std_logic_vector( 4 downto 0);
I_RSEL : in std_logic_vector( 1 downto 0);
I_WE_01 : in std_logic;
I_WE_D : in std_logic_vector( 1 downto 0);
I_WE_F : in std_logic;
I_WE_M : in std_logic_vector( 1 downto 0);
I_WE_XYZS : in std_logic;
Q_ADR : out std_logic_vector(15 downto 0);
Q_DOUT : out std_logic_vector(15 downto 0);
Q_INT_ENA : out std_logic;
Q_LOAD_PC : out std_logic;
Q_NEW_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector(15 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_RD_IO : out std_logic;
Q_SKIP : out std_logic;
Q_WE_IO : out std_logic;
Q_WE_SRAM : out std_logic_vector(1 downto 0));
end data_path;
architecture Behavioral of data_path is
component alu
port ( I_ALU_OP : in std_logic_vector( 4 downto 0);
I_BIT : in std_logic_vector( 3 downto 0);
I_D : in std_logic_vector(15 downto 0);
I_D0 : in std_logic;
I_DIN : in std_logic_vector( 7 downto 0);
I_FLAGS : in std_logic_vector( 7 downto 0);
I_IMM : in std_logic_vector( 7 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_R : in std_logic_vector(15 downto 0);
I_R0 : in std_logic;
I_RSEL : in std_logic_vector( 1 downto 0);
Q_FLAGS : out std_logic_vector( 9 downto 0);
Q_DOUT : out std_logic_vector(15 downto 0));
end component;
signal A_DOUT : std_logic_vector(15 downto 0);
signal A_FLAGS : std_logic_vector( 9 downto 0);
component register_file
port ( I_CLK : in std_logic;
I_AMOD : in std_logic_vector( 5 downto 0);
I_COND : in std_logic_vector( 3 downto 0);
I_DDDDD : in std_logic_vector( 4 downto 0);
I_DIN : in std_logic_vector(15 downto 0);
I_FLAGS : in std_logic_vector( 7 downto 0);
I_IMM : in std_logic_vector(15 downto 0);
I_RRRR : in std_logic_vector( 4 downto 1);
I_WE_01 : in std_logic;
I_WE_D : in std_logic_vector( 1 downto 0);
I_WE_F : in std_logic;
I_WE_M : in std_logic;
I_WE_XYZS : in std_logic;
Q_ADR : out std_logic_vector(15 downto 0);
Q_CC : out std_logic;
Q_D : out std_logic_vector(15 downto 0);
Q_FLAGS : out std_logic_vector( 7 downto 0);
Q_R : out std_logic_vector(15 downto 0);
Q_S : out std_logic_vector( 7 downto 0);
Q_Z : out std_logic_vector(15 downto 0));
end component;
signal F_ADR : std_logic_vector(15 downto 0);
signal F_CC : std_logic;
signal F_D : std_logic_vector(15 downto 0);
signal F_FLAGS : std_logic_vector( 7 downto 0);
signal F_R : std_logic_vector(15 downto 0);
signal F_S : std_logic_vector( 7 downto 0);
signal F_Z : std_logic_vector(15 downto 0);
signal L_DIN : std_logic_vector( 7 downto 0);
signal L_WE_SRAM : std_logic_vector( 1 downto 0);
signal L_FLAGS_98 : std_logic_vector( 9 downto 8);
begin
alui : alu
port map( I_ALU_OP => I_ALU_OP,
I_BIT => I_BIT,
I_D => F_D,
I_D0 => I_DDDDD(0),
I_DIN => L_DIN,
I_FLAGS => F_FLAGS,
I_IMM => I_IMM(7 downto 0),
I_PC => I_PC,
I_R => F_R,
I_R0 => I_RRRRR(0),
I_RSEL => I_RSEL,
Q_FLAGS => A_FLAGS,
Q_DOUT => A_DOUT);
regs : register_file
port map( I_CLK => I_CLK,
I_AMOD => I_AMOD,
I_COND(3) => I_OPC(10),
I_COND(2 downto 0)=> I_OPC(2 downto 0),
I_DDDDD => I_DDDDD,
I_DIN => A_DOUT,
I_FLAGS => A_FLAGS(7 downto 0),
I_IMM => I_IMM,
I_RRRR => I_RRRRR(4 downto 1),
I_WE_01 => I_WE_01,
I_WE_D => I_WE_D,
I_WE_F => I_WE_F,
I_WE_M => I_WE_M(0),
I_WE_XYZS => I_WE_XYZS,
Q_ADR => F_ADR,
Q_CC => F_CC,
Q_D => F_D,
Q_FLAGS => F_FLAGS,
Q_R => F_R,
Q_S => F_S, -- Q_Rxx(F_ADR)
Q_Z => F_Z);
-- remember A_FLAGS(9 downto 8) (within the current instruction).
--
flg98: process(I_CE, I_CLK)
begin
if (I_CE = '1' and rising_edge(I_CLK)) then
L_FLAGS_98 <= A_FLAGS(9 downto 8);
end if;
end process;
-- whether PC shall be loaded with NEW_PC or not.
-- I.e. if a branch shall be taken or not.
--
process(I_PC_OP, F_CC)
begin
case I_PC_OP is
when PC_BCC => Q_LOAD_PC <= F_CC; -- maybe (PC on I_JADR)
when PC_LD_I => Q_LOAD_PC <= '1'; -- yes: new PC on I_JADR
when PC_LD_Z => Q_LOAD_PC <= '1'; -- yes: new PC in Z
when PC_LD_S => Q_LOAD_PC <= '1'; -- yes: new PC on stack
when others => Q_LOAD_PC <= '0'; -- no.
end case;
end process;
-- whether the next instruction shall be skipped or not.
--
process(I_PC_OP, L_FLAGS_98, F_CC)
begin
case I_PC_OP is
when PC_BCC => Q_SKIP <= F_CC; -- if cond met
when PC_LD_I => Q_SKIP <= '1'; -- yes
when PC_LD_Z => Q_SKIP <= '1'; -- yes
when PC_LD_S => Q_SKIP <= '1'; -- yes
when PC_SKIP_Z => Q_SKIP <= L_FLAGS_98(8); -- if Z set
when PC_SKIP_T => Q_SKIP <= L_FLAGS_98(9); -- if T set
when others => Q_SKIP <= '0'; -- no.
end case;
end process;
Q_ADR <= F_ADR;
Q_DOUT <= A_DOUT;
Q_INT_ENA <= A_FLAGS(7);
Q_OPC <= I_OPC;
Q_PC <= I_PC;
Q_RD_IO <= '0' when (F_ADR < X"20")
else (I_RD_M and not I_PMS) when (F_ADR < X"5D")
else '0';
Q_WE_IO <= '0' when (F_ADR < X"20")
else I_WE_M(0) when (F_ADR < X"5D")
else '0';
Q_WE_SRAM <= "00" when (F_ADR < X"0060") else I_WE_M;
L_DIN <= I_DIN(7 downto 0) when (I_PMS = '1')
else F_S when (F_ADR < X"0020")
else I_DIN(7 downto 0) when (F_ADR < X"005D")
else F_S when (F_ADR < X"0060")
else I_DIN(7 downto 0);
-- compute potential new PC value from Z, (SP), or IMM.
--
Q_NEW_PC <= F_Z when I_PC_OP = PC_LD_Z -- IJMP, ICALL
else I_DIN when I_PC_OP = PC_LD_S -- RET, RETI
else I_JADR; -- JMP adr
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use work.MIPS_lib.all;
entity main_control is
port(
op_code : in std_logic_vector(5 downto 0);
RegDst : out std_logic;
ALUsrc : out std_logic;
RegWrite : out std_logic;
ALUOp : out std_logic_vector(2 downto 0);
ExtOp : out std_logic
);
end main_control;
architecture BHV of main_control is
begin
process(op_code) -- process for state determination
begin
RegDst <= '0'; -- RegDst is Rt
ALUsrc <= '0';
RegWrite <= '0';
ALUOp <= (others => '0');
ExtOp <= '0';
case op_code is
when OPC_R =>
RegDst <= '1'; -- Set RegWrite mux write to Rd
RegWrite <= '1'; -- Enable register write to store value in destination reg
ALUOp <= R_TYPE; -- ALUop is an R-Type
when OPC_ORI =>
ALUsrc <= '1'; -- Select zero-extend 32-bit value
RegWrite <= '1'; -- Write to Regfile
ALUOp <= ORI; -- Do an or operation
when OPC_LUI =>
ALUsrc <= '1'; -- Select zero-extended 32-bit value
RegWrite <= '1'; -- Enable register write to store value in destination reg
ALUOp <= LUI; -- Set ALUOp to LUI
when OPC_ADDI =>
ALUsrc <= '1'; -- Select zero-extended 32-bit value
ExtOp <= '1'; -- Sign extend
RegWrite <= '1'; -- Enable register write to store value in destination reg
ALUOp <= ADD; -- Set ALUOp to ADD
when OPC_ADDIU =>
ALUsrc <= '1'; -- Select zero-extended 32-bit value
ExtOp <= '1'; -- Sign extend
RegWrite <= '1'; -- Enable register write to store value in destination reg
ALUOp <= ADD; -- Set ALUOp to ADD
when OPC_ANDI =>
ALUsrc <= '1'; -- Select zero-extend 32-bit value
RegWrite <= '1'; -- Write to Regfile
ALUOp <= ANDI; -- Do an and operation
when OPC_SLTI =>
ALUsrc <= '1'; -- Select zero-extend 32-bit value
ExtOp <= '1'; -- Sign extend
RegWrite <= '1'; -- Write to Regfile
ALUOp <= SLTI; -- Do an slt operation
when OPC_SLTIU =>
ALUsrc <= '1'; -- Select zero-extend 32-bit value
ExtOp <= '1'; -- Sign extend
RegWrite <= '1'; -- Write to Regfile
ALUOp <= SLTIU; -- Do an slt operation
when OPC_BEQ =>
ALUsrc <= '1'; -- Select zero-extend 32-bit value
ExtOp <= '1'; -- Sign extend
RegWrite <= '1'; -- Write to Regfile
ALUOp <= BEQ; -- Do an subtract operation
when others =>
end case;
end process;
end BHV;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram128bw
-- File: syncram128bw.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 128-bit syncronous 1-port ram with 8-bit write strobes
-- and tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncram128bw is
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits: integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none
);
end;
architecture rtl of syncram128bw is
component unisim_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end component;
component altera_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end component;
component tm65gplus_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (3 downto 0) := "0000"
);
end component;
component ut90nhbd_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
tdbn : in std_ulogic
);
end component;
signal xenable, xwrite : std_logic_vector(15 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
custominx <= (others => '0');
nocust: if syncram_has_customif(tech)=0 or has_sram128bw(tech)=0 generate
customoutx <= (others => '0');
end generate;
s64 : if has_sram128bw(tech) = 1 generate
xc2v : if (is_unisim(tech) = 1) generate
x0 : unisim_syncram128bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
alt : if (tech = stratix2) or (tech = stratix3) or (tech = stratix4) or
(tech = cyclone3) or (tech = altera) generate
x0 : altera_syncram128bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
tm65: if tech = tm65gplus generate
x0 : tm65gplus_syncram128bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite, testin);
end generate;
ut09: if tech = ut90 generate
x0 : ut90nhbd_syncram128bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite, testin(TESTIN_WIDTH-3));
end generate;
-- pragma translate_off
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram128bw: " & tost(2**abits) & "x128" &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end generate;
nos64 : if has_sram128bw(tech) = 0 generate
rx : for i in 0 to 15 generate
x0 : syncram generic map (tech, abits, 8, testen, custombits)
port map (clk, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable(i), write(i), testin
);
end generate;
end generate;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity t80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end t80_Reg;
architecture rtl of t80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;
|
--
-- UART for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
entity zpuino_uart is
generic (
bits: integer := 11
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
enabled: out std_logic;
tx: out std_logic;
rx: in std_logic
);
end entity zpuino_uart;
architecture behave of zpuino_uart is
component zpuino_uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end component zpuino_uart_rx;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- Tx in progress
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
component fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end component fifo;
signal uart_read: std_logic;
signal uart_write: std_logic;
signal divider_tx: std_logic_vector(15 downto 0) := x"000f";
signal divider_rx_q: std_logic_vector(15 downto 0);
signal data_ready: std_logic;
signal received_data: std_logic_vector(7 downto 0);
signal fifo_data: std_logic_vector(7 downto 0);
signal uart_busy: std_logic;
signal uart_intx: std_logic;
signal fifo_empty: std_logic;
signal rx_br: std_logic;
signal tx_br: std_logic;
signal rx_en: std_logic;
signal dready_q: std_logic;
signal data_ready_dly_q: std_logic;
signal fifo_rd: std_logic;
signal enabled_q: std_logic;
begin
enabled <= enabled_q;
wb_inta_o <= '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
rx_inst: zpuino_uart_rx
port map(
clk => wb_clk_i,
rst => wb_rst_i,
rxclk => rx_br,
read => uart_read,
rx => rx,
data_av => data_ready,
data => received_data
);
uart_read <= dready_q;
tx_core: TxUnit
port map(
clk_i => wb_clk_i,
reset_i => wb_rst_i,
enable_i => tx_br,
load_i => uart_write,
txd_o => tx,
busy_o => uart_busy,
intx_o => uart_intx,
datai_i => wb_dat_i(7 downto 0)
);
-- TODO: check multiple writes
uart_write <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='0' else '0';
-- Rx timing
rx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => '1',
clkout => rx_br,
count => divider_rx_q
);
-- Tx timing
tx_timer: uart_brgen
port map(
clk => wb_clk_i,
rst => wb_rst_i,
en => rx_br,
clkout => tx_br,
count => divider_tx
);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
dready_q<='0';
data_ready_dly_q<='0';
else
data_ready_dly_q<=data_ready;
if data_ready='1' and data_ready_dly_q='0' then
dready_q<='1';
else
dready_q<='0';
end if;
end if;
end if;
end process;
fifo_instance: fifo
generic map (
bits => bits
)
port map (
clk => wb_clk_i,
rst => wb_rst_i,
wr => dready_q,
rd => fifo_rd,
write => received_data,
read => fifo_data,
full => open,
empty => fifo_empty
);
fifo_rd<='1' when wb_adr_i(2)='0' and (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0') else '0';
process(wb_adr_i, received_data, uart_busy, data_ready, fifo_empty, fifo_data,uart_intx)
begin
case wb_adr_i(2) is
when '1' =>
wb_dat_o <= (others => Undefined);
wb_dat_o(0) <= not fifo_empty;
wb_dat_o(1) <= uart_busy;
wb_dat_o(2) <= uart_intx;
when '0' =>
wb_dat_o <= (others => '0');
wb_dat_o(7 downto 0) <= fifo_data;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
enabled_q<='0';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='1' then
divider_rx_q <= wb_dat_i(15 downto 0);
enabled_q <= wb_dat_i(16);
end if;
end if;
end if;
end if;
end process;
end behave;
|
architecture rtl of fifo is
begin
process
begin
var1 := '0'when rd_en = '1' else '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0'when rd_en = '1' else '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0' when rd_en = '1' else '1';
concurrent_wr_en_b <= '0' when rd_en = '1' else '1';
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity regtable is
port (
clk : in std_logic;
rst : in std_logic;
raddrA : in std_logic_vector(4 downto 0);
raddrB : in std_logic_vector(4 downto 0);
wen : in std_logic;
waddr : in std_logic_vector(4 downto 0);
din : in std_logic_vector(31 downto 0);
doutA : out std_logic_vector(31 downto 0);
doutB : out std_logic_vector(31 downto 0);
extaddr : in std_logic_vector(4 downto 0);
extdout : out std_logic_vector(31 downto 0)
);
end regtable;
architecture arch_regtable of regtable is
type regdata is array (0 to 31) of std_logic_vector(31 downto 0);
signal RT : regdata;
begin
process(clk, rst)
variable addri : integer;
begin
if rst = '1' then
RT(0) <= (others => '0');
RT(1) <= (others => '0');
RT(2) <= (others => '0');
RT(3) <= (others => '0');
RT(4) <= (others => '0');
RT(5) <= (others => '0');
RT(6) <= (others => '0');
RT(7) <= (others => '0');
RT(8) <= (others => '0');
RT(9) <= (others => '0');
RT(10) <= (others => '0');
RT(11) <= (others => '0');
RT(12) <= (others => '0');
RT(13) <= (others => '0');
RT(14) <= (others => '0');
RT(15) <= (others => '0');
RT(16) <= (others => '0');
RT(17) <= (others => '0');
RT(18) <= (others => '0');
RT(19) <= (others => '0');
RT(20) <= (others => '0');
RT(21) <= (others => '0');
RT(22) <= (others => '0');
RT(23) <= (others => '0');
RT(24) <= (others => '0');
RT(25) <= (others => '0');
RT(26) <= (others => '0');
RT(27) <= (others => '0');
RT(28) <= "00000000000000001100000000000000";
RT(29) <= "00000000000000001111111111111100";
RT(30) <= (others => '0');
RT(31) <= (others => '0');
elsif clk'event and clk = '1' then
if wen = '1' then
addri := conv_integer(waddr);
if not(addri = 0) then
RT(addri) <= din;
end if;
end if;
end if;
end process;
process(raddrA, raddrB, extaddr, RT)
variable addrAi, addrBi, extaddri : integer;
begin
addrAi := conv_integer(raddrA);
addrBi := conv_integer(raddrB);
extaddri := conv_integer(extaddr);
doutA <= RT(addrAi);
doutB <= RT(addrBi);
extdout <= RT(extaddri);
end process;
end arch_regtable;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2544.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p14n01i02544ent IS
END c07s03b05x00p14n01i02544ent;
ARCHITECTURE c07s03b05x00p14n01i02544arch OF c07s03b05x00p14n01i02544ent IS
BEGIN
TESTING: PROCESS
type X1 is range 1.0 to 100.0 ;
type X2 is range 1.0 to 100.0 ;
type I1 is range 1 to 1000000;
type I2 is range 1 to 10000000 ;
variable RE1 : X1 ;
variable RE2 : X2 ;
variable IN1 : I1 ;
variable IN2 : I2 ;
BEGIN
IN2 := IN2 - IN1; -- Failure_here
-- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
-- UNIVERSAL INTEGER OR UNIVERSAL REAL.
assert FALSE
report "***FAILED TEST: c07s03b05x00p14n01i02544 - Type conversion can only occur on operand of universal real or integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p14n01i02544arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2544.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p14n01i02544ent IS
END c07s03b05x00p14n01i02544ent;
ARCHITECTURE c07s03b05x00p14n01i02544arch OF c07s03b05x00p14n01i02544ent IS
BEGIN
TESTING: PROCESS
type X1 is range 1.0 to 100.0 ;
type X2 is range 1.0 to 100.0 ;
type I1 is range 1 to 1000000;
type I2 is range 1 to 10000000 ;
variable RE1 : X1 ;
variable RE2 : X2 ;
variable IN1 : I1 ;
variable IN2 : I2 ;
BEGIN
IN2 := IN2 - IN1; -- Failure_here
-- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
-- UNIVERSAL INTEGER OR UNIVERSAL REAL.
assert FALSE
report "***FAILED TEST: c07s03b05x00p14n01i02544 - Type conversion can only occur on operand of universal real or integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p14n01i02544arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2544.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p14n01i02544ent IS
END c07s03b05x00p14n01i02544ent;
ARCHITECTURE c07s03b05x00p14n01i02544arch OF c07s03b05x00p14n01i02544ent IS
BEGIN
TESTING: PROCESS
type X1 is range 1.0 to 100.0 ;
type X2 is range 1.0 to 100.0 ;
type I1 is range 1 to 1000000;
type I2 is range 1 to 10000000 ;
variable RE1 : X1 ;
variable RE2 : X2 ;
variable IN1 : I1 ;
variable IN2 : I2 ;
BEGIN
IN2 := IN2 - IN1; -- Failure_here
-- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
-- UNIVERSAL INTEGER OR UNIVERSAL REAL.
assert FALSE
report "***FAILED TEST: c07s03b05x00p14n01i02544 - Type conversion can only occur on operand of universal real or integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p14n01i02544arch;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "goertzel"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel_tb is
end goertzel_tb;
-------------------------------------------------------------------------------
architecture tb of goertzel_tb is
-- component generics
constant SAMPLES : natural := 250;
constant INPUT_WIDTH : natural := 14;
constant CALC_WIDTH : natural := 18;
constant Q : natural := 13;
-- component ports
signal start_p : std_logic;
signal adc_value_p : signed(INPUT_WIDTH-1 downto 0) := (others => '0');
signal result_p : goertzel_result_type;
signal done_s : std_logic;
-- clock
signal clk : std_logic := '1';
-- signal generation
signal PHASE : real := 0.0;
constant SCALE : real := 2.0**7 - 10.0;
constant OFFSET : real := 2.0**13;
constant FSAMPLE : real := 75000.0; -- Sample Frequency in Hertz
constant FSIGNAL : real := 16750.0; -- Signal Frequency in Hertz
signal PHASE_INCREMENT : real := 2.0 * 3.1415 * FSIGNAL / FSAMPLE;
-- calculate Goertzel Coefficient
-- TODO
constant COEF : unsigned := to_unsigned(2732, CALC_WIDTH);
-- debugging signal for goertzel
signal goertzel_value_s : real := 0.0;
begin -- tb
-- component instantiation
DUT : goertzel
generic map (
Q => Q,
SAMPLES => SAMPLES
)
port map (
clk => clk,
coef_p => COEF,
start_p => start_p,
adc_value_p => adc_value_p,
result_p => result_p,
done_p => done_s
);
-- clock generation
clk <= not clk after 20 ns;
-- every 5 clock cycles a start_p signal from ADC
start_gen_proc : process
begin -- process start_gen_proc
start_p <= '0';
wait until clk = '1';
start_p <= '1';
wait until clk = '1';
start_p <= '0';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
end process start_gen_proc;
-- Test signal waveform generation
WaveGen_Proc : process
begin
for n in 0 to 10000 loop
wait until start_p = '1';
-- raw ADC values
-- adc_value_p <= std_logic_vector(to_unsigned(integer(offset + scale*sin(phase)), 14));
-- signed values
adc_value_p <= to_signed(integer(SCALE * sin(PHASE)), INPUT_WIDTH);
-- test
-- adc_value_p <= "00000000001000";
PHASE <= PHASE + PHASE_INCREMENT;
end loop;
-- end, do not repeat pattern
wait for 10 ms;
end process WaveGen_Proc;
-- Calculate Goertzel Value in this test bench. This will not be implemented
-- in VHDL. It is done in the processor in floating point.
GoertzelCheck_proc : process
variable d1 : real := 0.0;
variable d2 : real := 0.0;
variable c : real := 0.0;
begin -- process GoertzelCheck_proc
wait until done_s = '1';
-- new values are available in the result registers
-- convert results from Q-format to real
-- only the upper 16 bits of result_p are stored, so do not shift by 18
-- bits.
d1 := real(to_integer(result_p(0))) / 2.0**(Q-2);
d2 := real(to_integer(result_p(1))) / 2.0**(Q-2);
c := real(to_integer(coef)) / 2.0**Q;
-- calculate goertzel value
goertzel_value_s <= d1**2 + d2**2 - (d2 * d1 * c);
end process GoertzelCheck_proc;
end tb;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "goertzel"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel_tb is
end goertzel_tb;
-------------------------------------------------------------------------------
architecture tb of goertzel_tb is
-- component generics
constant SAMPLES : natural := 250;
constant INPUT_WIDTH : natural := 14;
constant CALC_WIDTH : natural := 18;
constant Q : natural := 13;
-- component ports
signal start_p : std_logic;
signal adc_value_p : signed(INPUT_WIDTH-1 downto 0) := (others => '0');
signal result_p : goertzel_result_type;
signal done_s : std_logic;
-- clock
signal clk : std_logic := '1';
-- signal generation
signal PHASE : real := 0.0;
constant SCALE : real := 2.0**7 - 10.0;
constant OFFSET : real := 2.0**13;
constant FSAMPLE : real := 75000.0; -- Sample Frequency in Hertz
constant FSIGNAL : real := 16750.0; -- Signal Frequency in Hertz
signal PHASE_INCREMENT : real := 2.0 * 3.1415 * FSIGNAL / FSAMPLE;
-- calculate Goertzel Coefficient
-- TODO
constant COEF : unsigned := to_unsigned(2732, CALC_WIDTH);
-- debugging signal for goertzel
signal goertzel_value_s : real := 0.0;
begin -- tb
-- component instantiation
DUT : goertzel
generic map (
Q => Q,
SAMPLES => SAMPLES
)
port map (
clk => clk,
coef_p => COEF,
start_p => start_p,
adc_value_p => adc_value_p,
result_p => result_p,
done_p => done_s
);
-- clock generation
clk <= not clk after 20 ns;
-- every 5 clock cycles a start_p signal from ADC
start_gen_proc : process
begin -- process start_gen_proc
start_p <= '0';
wait until clk = '1';
start_p <= '1';
wait until clk = '1';
start_p <= '0';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
end process start_gen_proc;
-- Test signal waveform generation
WaveGen_Proc : process
begin
for n in 0 to 10000 loop
wait until start_p = '1';
-- raw ADC values
-- adc_value_p <= std_logic_vector(to_unsigned(integer(offset + scale*sin(phase)), 14));
-- signed values
adc_value_p <= to_signed(integer(SCALE * sin(PHASE)), INPUT_WIDTH);
-- test
-- adc_value_p <= "00000000001000";
PHASE <= PHASE + PHASE_INCREMENT;
end loop;
-- end, do not repeat pattern
wait for 10 ms;
end process WaveGen_Proc;
-- Calculate Goertzel Value in this test bench. This will not be implemented
-- in VHDL. It is done in the processor in floating point.
GoertzelCheck_proc : process
variable d1 : real := 0.0;
variable d2 : real := 0.0;
variable c : real := 0.0;
begin -- process GoertzelCheck_proc
wait until done_s = '1';
-- new values are available in the result registers
-- convert results from Q-format to real
-- only the upper 16 bits of result_p are stored, so do not shift by 18
-- bits.
d1 := real(to_integer(result_p(0))) / 2.0**(Q-2);
d2 := real(to_integer(result_p(1))) / 2.0**(Q-2);
c := real(to_integer(coef)) / 2.0**Q;
-- calculate goertzel value
goertzel_value_s <= d1**2 + d2**2 - (d2 * d1 * c);
end process GoertzelCheck_proc;
end tb;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Tue Sep 17 19:45:28 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_auto_pc_0/gcd_zynq_snick_auto_pc_0_sim_netlist.vhdl
-- Design : gcd_zynq_snick_auto_pc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg400-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[0]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[2]_0\ : out STD_LOGIC;
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
\m_axi_awaddr[11]\ : out STD_LOGIC;
\m_axi_awaddr[5]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
\next\ : in STD_LOGIC;
axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd : entity is "axi_protocol_converter_v2_1_17_b2s_incr_cmd";
end gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd is
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \axaddr_incr[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[9]_i_1_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \axaddr_incr_reg[11]_i_4_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[2]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal next_pending_r_i_5_n_0 : STD_LOGIC;
signal \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_axi_awaddr[11]_INST_0_i_1\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_1\ : label is "soft_lutpair113";
begin
Q(0) <= \^q\(0);
\axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\;
\axaddr_incr_reg[11]_0\(10 downto 0) <= \^axaddr_incr_reg[11]_0\(10 downto 0);
\axlen_cnt_reg[2]_0\ <= \^axlen_cnt_reg[2]_0\;
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_7\,
O => \axaddr_incr[0]_i_1_n_0\
);
\axaddr_incr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(10),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_5\,
O => \axaddr_incr[10]_i_1_n_0\
);
\axaddr_incr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \next\,
O => \axaddr_incr[11]_i_1_n_0\
);
\axaddr_incr[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(11),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_4\,
O => \axaddr_incr[11]_i_2_n_0\
);
\axaddr_incr[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_6\,
O => \axaddr_incr[1]_i_1_n_0\
);
\axaddr_incr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_5\,
O => \axaddr_incr[2]_i_1_n_0\
);
\axaddr_incr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_4\,
O => \axaddr_incr[3]_i_1_n_0\
);
\axaddr_incr[3]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"0102"
)
port map (
I0 => \m_payload_i_reg[46]\(0),
I1 => \m_payload_i_reg[46]\(6),
I2 => \m_payload_i_reg[46]\(5),
I3 => \next\,
O => S(0)
);
\axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\(3),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(6),
O => \axaddr_incr[3]_i_11_n_0\
);
\axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\(2),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(6),
O => \axaddr_incr[3]_i_12_n_0\
);
\axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\(1),
I1 => \m_payload_i_reg[46]\(6),
I2 => \m_payload_i_reg[46]\(5),
O => \axaddr_incr[3]_i_13_n_0\
);
\axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\(0),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(6),
O => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \m_payload_i_reg[46]\(6),
I2 => \m_payload_i_reg[46]\(5),
I3 => \next\,
O => S(3)
);
\axaddr_incr[3]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"262A"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \m_payload_i_reg[46]\(6),
I2 => \m_payload_i_reg[46]\(5),
I3 => \next\,
O => S(2)
);
\axaddr_incr[3]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"060A"
)
port map (
I0 => \m_payload_i_reg[46]\(1),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(6),
I3 => \next\,
O => S(1)
);
\axaddr_incr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(4),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_7\,
O => \axaddr_incr[4]_i_1_n_0\
);
\axaddr_incr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(5),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_6\,
O => \axaddr_incr[5]_i_1_n_0\
);
\axaddr_incr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(6),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_5\,
O => \axaddr_incr[6]_i_1_n_0\
);
\axaddr_incr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(7),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_4\,
O => \axaddr_incr[7]_i_1_n_0\
);
\axaddr_incr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(8),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_7\,
O => \axaddr_incr[8]_i_1_n_0\
);
\axaddr_incr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(9),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_6\,
O => \axaddr_incr[9]_i_1_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[0]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[10]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(9),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[11]_i_2_n_0\,
Q => \^axaddr_incr_reg[11]_0\(10),
R => '0'
);
\axaddr_incr_reg[11]_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_3_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_4_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_4_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[11]_i_4_n_4\,
O(2) => \axaddr_incr_reg[11]_i_4_n_5\,
O(1) => \axaddr_incr_reg[11]_i_4_n_6\,
O(0) => \axaddr_incr_reg[11]_i_4_n_7\,
S(3 downto 0) => \^axaddr_incr_reg[11]_0\(10 downto 7)
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[1]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[2]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[3]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[3]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_3_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_3_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_3_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^axaddr_incr_reg[11]_0\(3 downto 0),
O(3) => \axaddr_incr_reg[3]_i_3_n_4\,
O(2) => \axaddr_incr_reg[3]_i_3_n_5\,
O(1) => \axaddr_incr_reg[3]_i_3_n_6\,
O(0) => \axaddr_incr_reg[3]_i_3_n_7\,
S(3) => \axaddr_incr[3]_i_11_n_0\,
S(2) => \axaddr_incr[3]_i_12_n_0\,
S(1) => \axaddr_incr[3]_i_13_n_0\,
S(0) => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[4]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[5]_i_1_n_0\,
Q => \axaddr_incr_reg_n_0_[5]\,
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[6]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[7]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_3_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_3_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_3_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_3_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[7]_i_3_n_4\,
O(2) => \axaddr_incr_reg[7]_i_3_n_5\,
O(1) => \axaddr_incr_reg[7]_i_3_n_6\,
O(0) => \axaddr_incr_reg[7]_i_3_n_7\,
S(3 downto 2) => \^axaddr_incr_reg[11]_0\(6 downto 5),
S(1) => \axaddr_incr_reg_n_0_[5]\,
S(0) => \^axaddr_incr_reg[11]_0\(4)
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[8]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(7),
R => '0'
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[9]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(8),
R => '0'
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(8),
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \^q\(0),
I4 => \^axlen_cnt_reg[2]_0\,
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \^q\(0),
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \^axlen_cnt_reg[2]_0\,
I4 => E(0),
I5 => \m_payload_i_reg[46]\(9),
O => \axlen_cnt[2]_i_1_n_0\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEBAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[47]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \^q\(0),
I5 => \^axlen_cnt_reg[2]_0\,
O => \axlen_cnt[3]_i_2_n_0\
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \^q\(0),
O => \axlen_cnt[4]_i_1_n_0\
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_1_n_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt[7]_i_3_n_0\,
O => \axlen_cnt[6]_i_1_n_0\
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A9AA"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \axlen_cnt_reg_n_0_[6]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt[7]_i_3_n_0\,
O => \axlen_cnt[7]_i_2_n_0\
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[4]\,
O => \axlen_cnt[7]_i_3_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \state_reg[1]\(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[2]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[3]_i_2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[4]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => \state_reg[0]_rep\
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[5]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => \state_reg[0]_rep\
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[6]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => \state_reg[0]_rep\
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[7]_i_2_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => \state_reg[0]_rep\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \m_payload_i_reg[46]\(7),
O => \m_axi_awaddr[11]\
);
\m_axi_awaddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \axaddr_incr_reg_n_0_[5]\,
I2 => \m_payload_i_reg[46]\(7),
I3 => \m_payload_i_reg[46]\(4),
O => \m_axi_awaddr[5]\
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55545555"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt_reg_n_0_[6]\,
I4 => next_pending_r_i_5_n_0,
O => \^axlen_cnt_reg[2]_0\
);
next_pending_r_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_i_5_n_0
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_0,
Q => \^axaddr_incr_reg[0]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 is
port (
incr_next_pending : out STD_LOGIC;
\axaddr_incr_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[0]_0\ : out STD_LOGIC;
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\m_axi_araddr[11]\ : out STD_LOGIC;
\m_axi_araddr[5]\ : out STD_LOGIC;
\m_axi_araddr[3]\ : out STD_LOGIC;
\m_axi_araddr[2]\ : out STD_LOGIC;
\m_axi_araddr[1]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
si_rs_arvalid : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_17_b2s_incr_cmd";
end gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 is
signal \axaddr_incr[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \axaddr_incr_reg[11]_i_4__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_incr_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_incr_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \next_pending_r_i_2__0_n_0\ : STD_LOGIC;
signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_axi_araddr[11]_INST_0_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \next_pending_r_i_2__0\ : label is "soft_lutpair7";
begin
\axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\;
\axaddr_incr_reg[11]_0\(7 downto 0) <= \^axaddr_incr_reg[11]_0\(7 downto 0);
\axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\;
incr_next_pending <= \^incr_next_pending\;
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_7\,
O => \axaddr_incr[0]_i_1__0_n_0\
);
\axaddr_incr[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_5\,
O => \axaddr_incr[10]_i_1__0_n_0\
);
\axaddr_incr[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_4\,
O => \axaddr_incr[11]_i_2__0_n_0\
);
\axaddr_incr[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_6\,
O => \axaddr_incr[1]_i_1__0_n_0\
);
\axaddr_incr[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_5\,
O => \axaddr_incr[2]_i_1__0_n_0\
);
\axaddr_incr[3]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"0201020202020202"
)
port map (
I0 => Q(0),
I1 => Q(6),
I2 => Q(5),
I3 => \state_reg[1]_0\(1),
I4 => \state_reg[1]_0\(0),
I5 => m_axi_arready,
O => S(0)
);
\axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_incr_reg_n_0_[3]\,
I1 => Q(5),
I2 => Q(6),
O => \axaddr_incr[3]_i_11_n_0\
);
\axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_incr_reg_n_0_[2]\,
I1 => Q(5),
I2 => Q(6),
O => \axaddr_incr[3]_i_12_n_0\
);
\axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_incr_reg_n_0_[1]\,
I1 => Q(6),
I2 => Q(5),
O => \axaddr_incr[3]_i_13_n_0\
);
\axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\(0),
I1 => Q(5),
I2 => Q(6),
O => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_4\,
O => \axaddr_incr[3]_i_1__0_n_0\
);
\axaddr_incr[3]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => Q(3),
I1 => Q(6),
I2 => Q(5),
I3 => \state_reg[1]_0\(1),
I4 => \state_reg[1]_0\(0),
I5 => m_axi_arready,
O => S(3)
);
\axaddr_incr[3]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A262A2A2A2A2A2A"
)
port map (
I0 => Q(2),
I1 => Q(6),
I2 => Q(5),
I3 => \state_reg[1]_0\(1),
I4 => \state_reg[1]_0\(0),
I5 => m_axi_arready,
O => S(2)
);
\axaddr_incr[3]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A060A0A0A0A0A0A"
)
port map (
I0 => Q(1),
I1 => Q(5),
I2 => Q(6),
I3 => \state_reg[1]_0\(1),
I4 => \state_reg[1]_0\(0),
I5 => m_axi_arready,
O => S(1)
);
\axaddr_incr[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_7\,
O => \axaddr_incr[4]_i_1__0_n_0\
);
\axaddr_incr[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_6\,
O => \axaddr_incr[5]_i_1__0_n_0\
);
\axaddr_incr[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_5\,
O => \axaddr_incr[6]_i_1__0_n_0\
);
\axaddr_incr[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_4\,
O => \axaddr_incr[7]_i_1__0_n_0\
);
\axaddr_incr[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_7\,
O => \axaddr_incr[8]_i_1__0_n_0\
);
\axaddr_incr[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_6\,
O => \axaddr_incr[9]_i_1__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[0]_i_1__0_n_0\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[10]_i_1__0_n_0\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[11]_i_2__0_n_0\,
Q => \^axaddr_incr_reg[11]_0\(7),
R => '0'
);
\axaddr_incr_reg[11]_i_4__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_3__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_4__0_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_4__0_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_4__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[11]_i_4__0_n_4\,
O(2) => \axaddr_incr_reg[11]_i_4__0_n_5\,
O(1) => \axaddr_incr_reg[11]_i_4__0_n_6\,
O(0) => \axaddr_incr_reg[11]_i_4__0_n_7\,
S(3 downto 0) => \^axaddr_incr_reg[11]_0\(7 downto 4)
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[1]_i_1__0_n_0\,
Q => \axaddr_incr_reg_n_0_[1]\,
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[2]_i_1__0_n_0\,
Q => \axaddr_incr_reg_n_0_[2]\,
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[3]_i_1__0_n_0\,
Q => \axaddr_incr_reg_n_0_[3]\,
R => '0'
);
\axaddr_incr_reg[3]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_3__0_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_3__0_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_3__0_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_3__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr_reg_n_0_[3]\,
DI(2) => \axaddr_incr_reg_n_0_[2]\,
DI(1) => \axaddr_incr_reg_n_0_[1]\,
DI(0) => \^axaddr_incr_reg[11]_0\(0),
O(3) => \axaddr_incr_reg[3]_i_3__0_n_4\,
O(2) => \axaddr_incr_reg[3]_i_3__0_n_5\,
O(1) => \axaddr_incr_reg[3]_i_3__0_n_6\,
O(0) => \axaddr_incr_reg[3]_i_3__0_n_7\,
S(3) => \axaddr_incr[3]_i_11_n_0\,
S(2) => \axaddr_incr[3]_i_12_n_0\,
S(1) => \axaddr_incr[3]_i_13_n_0\,
S(0) => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[4]_i_1__0_n_0\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[5]_i_1__0_n_0\,
Q => \axaddr_incr_reg_n_0_[5]\,
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[6]_i_1__0_n_0\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[7]_i_1__0_n_0\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[7]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_3__0_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_3__0_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_3__0_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_3__0_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[7]_i_3__0_n_4\,
O(2) => \axaddr_incr_reg[7]_i_3__0_n_5\,
O(1) => \axaddr_incr_reg[7]_i_3__0_n_6\,
O(0) => \axaddr_incr_reg[7]_i_3__0_n_7\,
S(3 downto 2) => \^axaddr_incr_reg[11]_0\(3 downto 2),
S(1) => \axaddr_incr_reg_n_0_[5]\,
S(0) => \^axaddr_incr_reg[11]_0\(1)
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[8]_i_1__0_n_0\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[9]_i_1__0_n_0\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"20FF2020"
)
port map (
I0 => si_rs_arvalid,
I1 => \state_reg[0]_rep\,
I2 => Q(8),
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => Q(9),
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[1]_i_1__1_n_0\
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \^axlen_cnt_reg[0]_0\,
I4 => E(0),
I5 => Q(10),
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEBAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[47]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[3]_i_2__0_n_0\
);
\axlen_cnt[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"55545555"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt_reg_n_0_[6]\,
I4 => \next_pending_r_i_4__0_n_0\,
O => \^axlen_cnt_reg[0]_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[4]\,
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt[7]_i_3__0_n_0\,
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A9AA"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \axlen_cnt_reg_n_0_[6]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => \state_reg[1]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => Q(7),
O => \m_axi_araddr[11]\
);
\m_axi_araddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \axaddr_incr_reg_n_0_[1]\,
I2 => Q(7),
I3 => Q(1),
O => \m_axi_araddr[1]\
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \axaddr_incr_reg_n_0_[2]\,
I2 => Q(7),
I3 => Q(2),
O => \m_axi_araddr[2]\
);
\m_axi_araddr[3]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \axaddr_incr_reg_n_0_[3]\,
I2 => Q(7),
I3 => Q(3),
O => \m_axi_araddr[3]\
);
\m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \axaddr_incr_reg_n_0_[5]\,
I2 => Q(7),
I3 => Q(4),
O => \m_axi_araddr[5]\
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF505C"
)
port map (
I0 => \next_pending_r_i_2__0_n_0\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep\,
I3 => E(0),
I4 => \m_payload_i_reg[47]_0\,
O => \^incr_next_pending\
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \next_pending_r_i_4__0_n_0\,
I1 => \axlen_cnt_reg_n_0_[6]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
O => \next_pending_r_i_2__0_n_0\
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[4]\,
O => \next_pending_r_i_4__0_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^incr_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_0,
Q => \^axaddr_incr_reg[0]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[7]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_valid_i0 : out STD_LOGIC;
s_ready_i0 : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[7]_0\ : in STD_LOGIC;
s_axburst_eq1_reg : in STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
\wrap_second_len_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg_1 : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[5]\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm : entity is "axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm";
end gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \next_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[11]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_ready_i_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair1";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \state_reg[0]\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute FSM_ENCODED_STATES of \state_reg[0]_rep\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute FSM_ENCODED_STATES of \state_reg[1]\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute FSM_ENCODED_STATES of \state_reg[1]_rep\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_4__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_6__0\ : label is "soft_lutpair4";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\axaddr_incr[11]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAEA"
)
port map (
I0 => sel_first,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_incr_reg[0]\(0)
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[46]\(0),
I2 => \^m_payload_i_reg[0]_0\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]\,
I5 => \m_payload_i_reg[5]\,
O => \axaddr_offset_r_reg[2]\(0)
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00CA"
)
port map (
I0 => si_rs_arvalid,
I1 => m_axi_arready,
I2 => \^q\(0),
I3 => \^q\(1),
O => E(0)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00005140"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => m_axi_arready,
I3 => si_rs_arvalid,
I4 => \axlen_cnt_reg[7]_0\,
O => \axlen_cnt_reg[7]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i_reg[0]_1\(0)
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF70FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
I2 => si_rs_arvalid,
I3 => s_axi_arvalid,
I4 => s_ready_i_reg,
O => m_valid_i0
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => m_axi_arready,
O => r_push_r_reg
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8F8F"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
I2 => si_rs_arvalid,
I3 => s_axi_arvalid,
I4 => s_ready_i_reg,
O => s_ready_i0
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_1,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first,
I2 => \^m_payload_i_reg[0]\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]_0\,
I5 => areset_d1,
O => sel_first_reg_0
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFFFFCCCECCCE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => \^m_payload_i_reg[0]\,
I3 => \^m_payload_i_reg[0]_0\,
I4 => m_axi_arready,
I5 => sel_first_reg_2,
O => sel_first_i
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003030303E3E3E3E"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => m_axi_arready,
I4 => s_axburst_eq1_reg,
I5 => \cnt_read_reg[2]_rep__0\,
O => \next_state__0\(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00AAB000"
)
port map (
I0 => \cnt_read_reg[2]_rep__0\,
I1 => s_axburst_eq1_reg,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]_0\,
I4 => \^m_payload_i_reg[0]\,
O => \next_state__0\(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \next_state__0\(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \next_state__0\(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \next_state__0\(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \next_state__0\(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \wrap_boundary_axaddr_r_reg[11]\(0)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8A5575AA8A5545"
)
port map (
I0 => \wrap_second_len_r_reg[0]_0\(0),
I1 => \^q\(0),
I2 => si_rs_arvalid,
I3 => \^q\(1),
I4 => \axaddr_offset_r_reg[3]\,
I5 => axaddr_offset(0),
O => D(0)
);
\wrap_cnt_r[3]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(1),
I1 => \^m_payload_i_reg[0]_0\,
I2 => si_rs_arvalid,
I3 => \^m_payload_i_reg[0]\,
O => \wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \^m_payload_i_reg[0]_0\,
I2 => si_rs_arvalid,
I3 => \^m_payload_i_reg[0]\,
O => \wrap_cnt_r_reg[3]_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8AAA8AAA8AAABA"
)
port map (
I0 => \wrap_second_len_r_reg[0]_0\(0),
I1 => \^q\(0),
I2 => si_rs_arvalid,
I3 => \^q\(1),
I4 => \axaddr_offset_r_reg[3]\,
I5 => axaddr_offset(0),
O => \wrap_second_len_r_reg[0]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__0_0\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
bresp_push : out STD_LOGIC;
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
bvalid_i_reg_0 : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo";
end gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo is
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \bresp_cnt[7]_i_5_n_0\ : STD_LOGIC;
signal \^bresp_push\ : STD_LOGIC;
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_2__0_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair121";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
bresp_push <= \^bresp_push\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__0_0\ <= \^cnt_read_reg[1]_rep__0_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABAA"
)
port map (
I0 => areset_d1,
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt[7]_i_4_n_0\,
I3 => \bresp_cnt[7]_i_5_n_0\,
O => SR(0)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEFEFFFFFFFFEEFE"
)
port map (
I0 => \bresp_cnt_reg[7]\(7),
I1 => \bresp_cnt_reg[7]\(6),
I2 => \bresp_cnt_reg[7]\(0),
I3 => \memory_reg[3][0]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF6FFFF"
)
port map (
I0 => \bresp_cnt_reg[7]\(1),
I1 => \memory_reg[3][1]_srl4_n_0\,
I2 => \bresp_cnt_reg[7]\(4),
I3 => \bresp_cnt_reg[7]\(5),
I4 => mhandshake_r,
O => \bresp_cnt[7]_i_4_n_0\
);
\bresp_cnt[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000D00DD00DD00D"
)
port map (
I0 => \memory_reg[3][0]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(0),
I2 => \bresp_cnt_reg[7]\(2),
I3 => \memory_reg[3][2]_srl4_n_0\,
I4 => \^cnt_read_reg[1]_rep__0_0\,
I5 => \^cnt_read_reg[0]_rep__0_0\,
O => \bresp_cnt[7]_i_5_n_0\
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0444"
)
port map (
I0 => areset_d1,
I1 => bvalid_i_i_2_n_0,
I2 => si_rs_bready,
I3 => bvalid_i_reg_0,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[1]_rep__0_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(1),
I4 => Q(0),
I5 => bvalid_i_reg_0,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^bresp_push\,
I1 => shandshake_r,
I2 => Q(0),
O => D(0)
);
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__0_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__0_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000041004141"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_2__0_n_0\,
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \bresp_cnt_reg[7]\(2),
I3 => \bresp_cnt_reg[7]\(0),
I4 => \memory_reg[3][0]_srl4_n_0\,
I5 => \memory_reg[3][0]_srl4_i_3_n_0\,
O => \^bresp_push\
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^cnt_read_reg[1]_rep__0_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
O => \memory_reg[3][0]_srl4_i_2__0_n_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFBFFFFFFFFFFFB"
)
port map (
I0 => \bresp_cnt[7]_i_3_n_0\,
I1 => mhandshake_r,
I2 => \bresp_cnt_reg[7]\(5),
I3 => \bresp_cnt_reg[7]\(4),
I4 => \memory_reg[3][1]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(1),
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \out\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ is
port (
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
mhandshake : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
shandshake_r : in STD_LOGIC;
sel : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo";
end \gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair122";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair122";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => shandshake_r,
I3 => sel,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_2\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo";
end \gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_5_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_2\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair18";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__3\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__3\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__3\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair19";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair19";
begin
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
\cnt_read_reg[4]_rep__2_2\ <= \^cnt_read_reg[4]_rep__2_2\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \cnt_read[4]_i_5_n_0\,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AA6"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => s_ready_i_reg,
I3 => \cnt_read[4]_i_5_n_0\,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A9AAAA6A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[0]_rep__2_n_0\,
I3 => \cnt_read[4]_i_5_n_0\,
I4 => s_ready_i_reg,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA6AA9AAAAAA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read[4]_i_5_n_0\,
I4 => s_ready_i_reg,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"99AA99AA99AA55A6"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_1\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_2\,
I3 => \cnt_read[4]_i_3__0_n_0\,
I4 => s_ready_i_reg,
I5 => \cnt_read[4]_i_5_n_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \cnt_read_reg[0]_rep__3_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_2\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000100000"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read[4]_i_5_n_0\,
I3 => \cnt_read_reg[4]_rep__0_0\,
I4 => si_rs_rready,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6000E000FFFFFFFF"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \^cnt_read_reg[4]_rep__2_1\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[0]_rep__3_n_0\,
I5 => m_axi_rvalid,
O => \cnt_read[4]_i_5_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__3\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__3_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_1\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"9FFF1FFF"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \^cnt_read_reg[4]_rep__2_1\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[0]_rep__3_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAA0AAA0AAAAAAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \cnt_read_reg[0]_rep__3_n_0\,
I2 => \^cnt_read_reg[4]_rep__2_0\,
I3 => \^cnt_read_reg[4]_rep__2_1\,
I4 => \cnt_read_reg[1]_rep__2_n_0\,
I5 => \cnt_read_reg[2]_rep__2_n_0\,
O => wr_en0
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"40C0C000"
)
port map (
I0 => \cnt_read_reg[0]_rep__3_n_0\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_1\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ is
port (
m_valid_i_reg : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
s_ready_i_reg : in STD_LOGIC;
r_push_r : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__3\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__3_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo";
end \gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal m_valid_i_i_3_n_0 : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair20";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => r_push_r,
I2 => s_ready_i_reg,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DB24"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
I3 => \cnt_read_reg[1]_rep__0_n_0\,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[1]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF7F0080FEFF0100"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9A999AAA"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read_reg[2]_rep__0_n_0\,
I3 => \cnt_read_reg[3]_rep__0_n_0\,
I4 => \cnt_read[4]_i_3_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2AAAAAAA2AAA2AAA"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__1_n_0\,
I3 => r_push_r,
I4 => \^m_valid_i_reg\,
I5 => si_rs_rready,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => r_push_r,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => \cnt_read_reg[0]_rep__1_n_0\,
I4 => \cnt_read_reg[1]_rep__0_n_0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"80808080FF808080"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read_reg[3]_rep__0_n_0\,
I2 => m_valid_i_i_3_n_0,
I3 => \cnt_read_reg[3]_rep__2\,
I4 => \cnt_read_reg[4]_rep__2\,
I5 => \cnt_read_reg[0]_rep__3\,
O => \^m_valid_i_reg\
);
m_valid_i_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__1_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
O => m_valid_i_i_3_n_0
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFEEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__3_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__1_n_0\,
I3 => \cnt_read_reg[1]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[4]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm is
port (
\axlen_cnt_reg[7]\ : out STD_LOGIC;
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
\axlen_cnt_reg[7]_1\ : out STD_LOGIC;
\next\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[7]_2\ : in STD_LOGIC;
\wrap_second_len_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wrap_next_pending : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_0 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[5]\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm : entity is "axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm";
end gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axlen_cnt_reg[7]\ : STD_LOGIC;
signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC;
signal \^b_push\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^next\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__0\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair110";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair109";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_4\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_6\ : label is "soft_lutpair111";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axlen_cnt_reg[7]\ <= \^axlen_cnt_reg[7]\;
\axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\;
b_push <= \^b_push\;
incr_next_pending <= \^incr_next_pending\;
\next\ <= \^next\;
sel_first_i <= \^sel_first_i\;
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[46]\(2),
I2 => \^axlen_cnt_reg[7]_0\,
I3 => si_rs_awvalid,
I4 => \^axlen_cnt_reg[7]\,
I5 => \m_payload_i_reg[5]\,
O => \axaddr_offset_r_reg[2]\(0)
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[46]\(1),
I4 => \axlen_cnt_reg[0]_0\(0),
I5 => \axlen_cnt_reg[7]_2\,
O => \axlen_cnt_reg[0]\(0)
);
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF04"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \^next\,
O => \axaddr_wrap_reg[11]\(0)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FF04"
)
port map (
I0 => \^axlen_cnt_reg[7]_0\,
I1 => si_rs_awvalid,
I2 => \^axlen_cnt_reg[7]\,
I3 => \^next\,
I4 => \axlen_cnt_reg[7]_2\,
O => \axlen_cnt_reg[7]_1\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^axlen_cnt_reg[7]_0\,
I1 => \^axlen_cnt_reg[7]\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^b_push\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88008888A800A8A8"
)
port map (
I0 => \^axlen_cnt_reg[7]_0\,
I1 => \^axlen_cnt_reg[7]\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__0\,
I5 => s_axburst_eq1_reg_0,
O => \^b_push\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF404"
)
port map (
I0 => \^e\(0),
I1 => next_pending_r_reg,
I2 => \^next\,
I3 => \axlen_cnt_reg[7]_2\,
I4 => \m_payload_i_reg[47]\,
O => \^incr_next_pending\
);
next_pending_r_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F3FFFF51000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__0\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^axlen_cnt_reg[7]_0\,
I5 => \^axlen_cnt_reg[7]\,
O => \^next\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => \^incr_next_pending\,
I1 => \^sel_first_i\,
I2 => \m_payload_i_reg[46]\(0),
I3 => wrap_next_pending,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => \^incr_next_pending\,
I1 => \m_payload_i_reg[46]\(0),
I2 => \^sel_first_i\,
I3 => wrap_next_pending,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44444F44"
)
port map (
I0 => \^next\,
I1 => sel_first,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44444F44"
)
port map (
I0 => \^next\,
I1 => sel_first_0,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF04FFFFFF04FF04"
)
port map (
I0 => \^axlen_cnt_reg[7]\,
I1 => si_rs_awvalid,
I2 => \^axlen_cnt_reg[7]_0\,
I3 => areset_d1,
I4 => \^next\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\state[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BBBA"
)
port map (
I0 => \state[0]_i_2_n_0\,
I1 => \^q\(0),
I2 => si_rs_awvalid,
I3 => \^q\(1),
O => \state[0]_i_1_n_0\
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00F000F055750000"
)
port map (
I0 => m_axi_awready,
I1 => s_axburst_eq1_reg_0,
I2 => \cnt_read_reg[1]_rep__0\,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \^axlen_cnt_reg[7]_0\,
I5 => \^axlen_cnt_reg[7]\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0CAE0000000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__0\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^axlen_cnt_reg[7]\,
I5 => \^axlen_cnt_reg[7]_0\,
O => \state[1]_i_1__0_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => \^axlen_cnt_reg[7]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^axlen_cnt_reg[7]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^axlen_cnt_reg[7]\,
I1 => si_rs_awvalid,
I2 => \^axlen_cnt_reg[7]_0\,
O => \^e\(0)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8A5575AA8A5545"
)
port map (
I0 => \wrap_second_len_r_reg[0]_0\(0),
I1 => \^q\(0),
I2 => si_rs_awvalid,
I3 => \^q\(1),
I4 => \axaddr_offset_r_reg[3]\,
I5 => axaddr_offset(0),
O => D(0)
);
\wrap_cnt_r[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(1),
I1 => \^axlen_cnt_reg[7]_0\,
I2 => si_rs_awvalid,
I3 => \^axlen_cnt_reg[7]\,
O => \wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \^axlen_cnt_reg[7]_0\,
I2 => si_rs_awvalid,
I3 => \^axlen_cnt_reg[7]\,
O => \wrap_cnt_r_reg[3]_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8AAA8AAA8AAABA"
)
port map (
I0 => \wrap_second_len_r_reg[0]_0\(0),
I1 => \^q\(0),
I2 => si_rs_awvalid,
I3 => \^q\(1),
I4 => \axaddr_offset_r_reg[3]\,
I5 => axaddr_offset(0),
O => \wrap_second_len_r_reg[0]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd is
port (
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
\next\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd : entity is "axi_protocol_converter_v2_1_17_b2s_wrap_cmd";
end gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_2__1_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0);
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(0),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(0),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(10),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(10),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(11),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(11),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => wrap_cnt_r(1),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => wrap_cnt_r(2),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(1),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(1),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(2),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(2),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(3),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(3),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(4),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(4),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(5),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(5),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(6),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(6),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(7),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(7),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(8),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(8),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(9),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(9),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3 downto 0) => axaddr_wrap(11 downto 8)
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3 downto 0) => axaddr_wrap(7 downto 4)
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1_n_0\
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAC3AAC3AAC3AAC0"
)
port map (
I0 => \m_payload_i_reg[47]\(16),
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => E(0),
I4 => \axlen_cnt_reg_n_0_[3]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[1]_i_1_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAACCCCCCC0"
)
port map (
I0 => \m_payload_i_reg[47]\(18),
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
I5 => E(0),
O => \axlen_cnt[3]_i_1_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[0]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[1]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[3]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(0),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(10),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(9),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(11),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(10),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(1),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(1),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(1),
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(2),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(3),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(4),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(5),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(5),
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_3,
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(6),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(5),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(7),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(6),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(8),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(7),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(9),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(8),
O => m_axi_awaddr(9)
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEAAFEAE"
)
port map (
I0 => \m_payload_i_reg[47]_0\,
I1 => next_pending_r_reg_n_0,
I2 => \next\,
I3 => \next_pending_r_i_2__1_n_0\,
I4 => E(0),
O => \^wrap_next_pending\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[1]\(0),
I1 => si_rs_awvalid,
I2 => \state_reg[1]\(1),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_2__1_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^wrap_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3D310E02"
)
port map (
I0 => \^wrap_second_len_r_reg[3]_0\(0),
I1 => E(0),
I2 => \axaddr_offset_r_reg[3]_2\,
I3 => D(1),
I4 => \^wrap_second_len_r_reg[3]_0\(1),
O => wrap_cnt(1)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000CAAA8000C0000"
)
port map (
I0 => \^wrap_second_len_r_reg[3]_0\(1),
I1 => \axaddr_offset_r_reg[3]_1\,
I2 => D(1),
I3 => D(0),
I4 => E(0),
I5 => \^wrap_second_len_r_reg[3]_0\(0),
O => \wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_cnt(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \^wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \^wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \^wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \^wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 is
port (
sel_first_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axburst_eq0_reg : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_arvalid : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_i : in STD_LOGIC;
incr_next_pending : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
sel_first_reg_5 : in STD_LOGIC;
sel_first_reg_6 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_17_b2s_wrap_cmd";
end gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_2__2_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r[1]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair16";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0);
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I3 => \state_reg[1]_rep\,
I4 => Q(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\,
I3 => \state_reg[1]_rep\,
I4 => Q(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\,
I3 => \state_reg[1]_rep\,
I4 => Q(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4__0_n_0\,
I1 => \wrap_cnt_r_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \wrap_cnt_r_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \wrap_cnt_r_reg_n_0_[1]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I3 => \state_reg[1]_rep\,
I4 => Q(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I3 => \state_reg[1]_rep\,
I4 => Q(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I3 => \state_reg[1]_rep\,
I4 => Q(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => Q(12),
I2 => Q(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => Q(12),
I2 => Q(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => Q(13),
I2 => Q(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => Q(12),
I2 => Q(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I3 => \state_reg[1]_rep\,
I4 => Q(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I3 => \state_reg[1]_rep\,
I4 => Q(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I3 => \state_reg[1]_rep\,
I4 => Q(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I3 => \state_reg[1]_rep\,
I4 => Q(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\,
I3 => \state_reg[1]_rep\,
I4 => Q(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\,
I3 => \state_reg[1]_rep\,
I4 => Q(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\,
S(3) => \axaddr_wrap_reg_n_0_[11]\,
S(2) => \axaddr_wrap_reg_n_0_[10]\,
S(1) => \axaddr_wrap_reg_n_0_[9]\,
S(0) => \axaddr_wrap_reg_n_0_[8]\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap_reg_n_0_[7]\,
S(2) => \axaddr_wrap_reg_n_0_[6]\,
S(1) => \axaddr_wrap_reg_n_0_[5]\,
S(0) => \axaddr_wrap_reg_n_0_[4]\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => Q(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1__1_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAC3AAC3AAC3AAC0"
)
port map (
I0 => Q(16),
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => E(0),
I4 => \axlen_cnt_reg_n_0_[3]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => Q(17),
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAACCCCCCC0"
)
port map (
I0 => Q(18),
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
I5 => E(0),
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => Q(14),
I3 => Q(0),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => Q(14),
I3 => Q(10),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(6),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => Q(14),
I3 => Q(11),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(7),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(1),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[1]\,
I3 => Q(14),
I4 => sel_first_reg_6,
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(2),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[2]\,
I3 => Q(14),
I4 => sel_first_reg_5,
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(3),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[3]\,
I3 => Q(14),
I4 => sel_first_reg_4,
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => Q(14),
I3 => Q(4),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(1),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(5),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[5]\,
I3 => Q(14),
I4 => sel_first_reg_3,
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => Q(14),
I3 => Q(6),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(2),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => Q(14),
I3 => Q(7),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(3),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => Q(14),
I3 => Q(8),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(4),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => Q(14),
I3 => Q(9),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(5),
O => m_axi_araddr(9)
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEAAFEAE"
)
port map (
I0 => \m_payload_i_reg[47]\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep\,
I3 => \next_pending_r_i_2__2_n_0\,
I4 => E(0),
O => wrap_next_pending
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[1]\(0),
I1 => si_rs_arvalid,
I2 => \state_reg[1]\(1),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_2__2_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_n_0,
R => '0'
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => wrap_next_pending,
I1 => Q(14),
I2 => sel_first_i,
I3 => incr_next_pending,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wrap_next_pending,
I1 => Q(14),
I2 => sel_first_i,
I3 => incr_next_pending,
O => s_axburst_eq1_reg
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"3D310E02"
)
port map (
I0 => \^wrap_second_len_r_reg[3]_0\(0),
I1 => E(0),
I2 => \axaddr_offset_r_reg[3]_2\,
I3 => D(1),
I4 => \^wrap_second_len_r_reg[3]_0\(1),
O => \wrap_cnt_r[1]_i_1__0_n_0\
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000CAAA8000C0000"
)
port map (
I0 => \^wrap_second_len_r_reg[3]_0\(1),
I1 => \axaddr_offset_r_reg[3]_1\,
I2 => D(1),
I3 => D(0),
I4 => E(0),
I5 => \^wrap_second_len_r_reg[3]_0\(0),
O => \wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_cnt_r[1]_i_1__0_n_0\,
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \^wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \^wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \^wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \^wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 54 downto 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[2]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
axaddr_offset_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\aresetn_d_reg[0]\ : in STD_LOGIC;
s_ready_i0 : in STD_LOGIC;
aclk : in STD_LOGIC;
m_valid_i0 : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_1\ : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice : entity is "axi_register_slice_v2_1_17_axic_register_slice";
end gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 );
signal \axaddr_incr[3]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \^axaddr_offset_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[52]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_5__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[2]\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_3__0_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair21";
begin
Q(54 downto 0) <= \^q\(54 downto 0);
axaddr_offset_0(1 downto 0) <= \^axaddr_offset_0\(1 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axaddr_offset_r_reg[3]\ <= \^axaddr_offset_r_reg[3]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
s_axi_arready <= \^s_axi_arready\;
\wrap_cnt_r_reg[2]\ <= \^wrap_cnt_r_reg[2]\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[3]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[3]_i_4__0_n_0\
);
\axaddr_incr[3]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[3]_i_5__0_n_0\
);
\axaddr_incr[3]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[3]_i_6__0_n_0\
);
\axaddr_incr_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => O(3 downto 0),
S(3 downto 0) => \^q\(11 downto 8)
);
\axaddr_incr_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[3]_i_4__0_n_0\,
DI(1) => \axaddr_incr[3]_i_5__0_n_0\,
DI(0) => \axaddr_incr[3]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3 downto 0) => \^q\(7 downto 4)
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \state_reg[1]\(1),
I3 => \^axaddr_offset_r_reg[3]\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]_0\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(2),
I2 => \^q\(36),
I3 => \^q\(1),
I4 => \^q\(35),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2__0_n_0\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \axaddr_offset_r[1]_i_2__0_n_0\,
I1 => \^q\(40),
I2 => \state_reg[1]\(1),
I3 => \^axaddr_offset_r_reg[3]\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]_0\(1),
O => \^axaddr_offset_0\(0)
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(4),
I1 => \^q\(3),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(5),
I1 => \^q\(4),
I2 => \^q\(36),
I3 => \^q\(3),
I4 => \^q\(35),
I5 => \^q\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \axaddr_offset_r[3]_i_2__0_n_0\,
I1 => \^q\(42),
I2 => \state_reg[1]\(1),
I3 => \^axaddr_offset_r_reg[3]\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]_0\(2),
O => \^axaddr_offset_0\(1)
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(5),
I2 => \^q\(36),
I3 => \^q\(4),
I4 => \^q\(35),
I5 => \^q\(3),
O => \axaddr_offset_r[3]_i_2__0_n_0\
);
\axlen_cnt[3]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[1]\(0),
I2 => \^axaddr_offset_r_reg[3]\,
I3 => \state_reg[1]\(1),
O => \^axlen_cnt_reg[3]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[52]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => \m_payload_i[52]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[52]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^axaddr_offset_r_reg[3]\,
R => \^m_valid_i_reg_0\
);
next_pending_r_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \^q\(42),
I2 => \^q\(40),
I3 => \^q\(39),
I4 => \^q\(41),
O => next_pending_r_reg
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(39),
I3 => \^q\(36),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0F553300000000"
)
port map (
I0 => \^q\(40),
I1 => \^q\(41),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(36),
I5 => \^q\(2),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"503F5F3F00000000"
)
port map (
I0 => \^q\(40),
I1 => \^q\(41),
I2 => \^q\(36),
I3 => \^q\(35),
I4 => \^q\(42),
I5 => \^q\(4),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(42),
I2 => \^q\(35),
I3 => \^q\(36),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6AA56AAAAAAAA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]_rep\,
I3 => \^wrap_cnt_r_reg[2]\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^wrap_second_len_r_reg[3]\(0),
O => \wrap_cnt_r_reg[3]\(0)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => \wrap_second_len_r_reg[1]\,
I2 => \^wrap_second_len_r_reg[3]\(1),
O => \wrap_cnt_r_reg[3]\(1)
);
\wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEAEAFFEA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_1\,
I1 => \^axlen_cnt_reg[3]\,
I2 => \axaddr_offset_r[3]_i_2__0_n_0\,
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \wrap_cnt_r[3]_i_5__0_n_0\,
I5 => \axaddr_offset_r_reg[2]_1\,
O => \wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r[3]_i_5__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(41),
I1 => \state_reg[0]_rep\,
I2 => \^axaddr_offset_r_reg[3]\,
I3 => \state_reg[1]_rep_0\,
O => \wrap_cnt_r[3]_i_5__0_n_0\
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000010001"
)
port map (
I0 => \^axaddr_offset_r_reg[0]\,
I1 => \^axaddr_offset_0\(0),
I2 => \axaddr_offset_r_reg[2]_0\(0),
I3 => \wrap_second_len_r[3]_i_2__0_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_0\(2),
O => \^wrap_cnt_r_reg[2]\
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F00EFFFFF00E0000"
)
port map (
I0 => \^axaddr_offset_0\(1),
I1 => \axaddr_offset_r_reg[2]_0\(0),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_0\(0),
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCC2FFFFCCC20000"
)
port map (
I0 => \^axaddr_offset_0\(1),
I1 => \axaddr_offset_r_reg[2]_0\(0),
I2 => \^axaddr_offset_0\(0),
I3 => \^axaddr_offset_r_reg[0]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(2),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE00FFFFFE00FE00"
)
port map (
I0 => \^axaddr_offset_r_reg[0]\,
I1 => \^axaddr_offset_0\(0),
I2 => \axaddr_offset_r_reg[2]_0\(0),
I3 => \wrap_second_len_r[3]_i_2__0_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(3),
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \^axlen_cnt_reg[3]\,
I1 => \wrap_second_len_r[3]_i_3__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(5),
I4 => \^q\(35),
I5 => \^q\(6),
O => \wrap_second_len_r[3]_i_2__0_n_0\
);
\wrap_second_len_r[3]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(3),
O => \wrap_second_len_r[3]_i_3__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 54 downto 0 );
axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 );
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[2]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_1\ : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 : entity is "axi_register_slice_v2_1_17_axic_register_slice";
end gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 is
signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 61 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_5_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[2]\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair49";
begin
Q(54 downto 0) <= \^q\(54 downto 0);
axaddr_offset(1 downto 0) <= \^axaddr_offset\(1 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[2]\ <= \^wrap_cnt_r_reg[2]\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[3]_i_4_n_0\
);
\axaddr_incr[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[3]_i_5_n_0\
);
\axaddr_incr[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[3]_i_6_n_0\
);
\axaddr_incr_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_3_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_3_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_incr(11 downto 8),
S(3 downto 0) => \^q\(11 downto 8)
);
\axaddr_incr_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_2_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[3]_i_4_n_0\,
DI(1) => \axaddr_incr[3]_i_5_n_0\,
DI(0) => \axaddr_incr[3]_i_6_n_0\,
O(3 downto 0) => axaddr_incr(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_2_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_2_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_incr(7 downto 4),
S(3 downto 0) => \^q\(7 downto 4)
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(2),
I2 => \^q\(36),
I3 => \^q\(1),
I4 => \^q\(35),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \axaddr_offset_r[1]_i_2_n_0\,
I1 => \^q\(40),
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]\(1),
O => \^axaddr_offset\(0)
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(4),
I1 => \^q\(3),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \^q\(1),
O => \axaddr_offset_r[1]_i_2_n_0\
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(5),
I1 => \^q\(4),
I2 => \^q\(36),
I3 => \^q\(3),
I4 => \^q\(35),
I5 => \^q\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \axaddr_offset_r[3]_i_2_n_0\,
I1 => \^q\(42),
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]\(2),
O => \^axaddr_offset\(1)
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(5),
I2 => \^q\(36),
I3 => \^q\(4),
I4 => \^q\(35),
I5 => \^q\(3),
O => \axaddr_offset_r[3]_i_2_n_0\
);
\axlen_cnt[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[1]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \^axlen_cnt_reg[3]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => skid_buffer(52)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(52),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \^q\(42),
I2 => \^q\(40),
I3 => \^q\(39),
I4 => \^q\(41),
O => next_pending_r_reg
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_awvalid,
I1 => \^s_axi_awready\,
I2 => b_push,
I3 => \^m_valid_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(39),
I3 => \^q\(36),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0F553300000000"
)
port map (
I0 => \^q\(40),
I1 => \^q\(41),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(36),
I5 => \^q\(2),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"503F5F3F00000000"
)
port map (
I0 => \^q\(40),
I1 => \^q\(41),
I2 => \^q\(36),
I3 => \^q\(35),
I4 => \^q\(42),
I5 => \^q\(4),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(42),
I2 => \^q\(35),
I3 => \^q\(36),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6AA56AAAAAAAA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]_rep\,
I3 => \^wrap_cnt_r_reg[2]\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^wrap_second_len_r_reg[3]\(0),
O => D(0)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => \wrap_second_len_r_reg[1]\,
I2 => \^wrap_second_len_r_reg[3]\(1),
O => D(1)
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEAEAFFEA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\,
I1 => \^axlen_cnt_reg[3]\,
I2 => \axaddr_offset_r[3]_i_2_n_0\,
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \wrap_cnt_r[3]_i_5_n_0\,
I5 => \axaddr_offset_r_reg[2]_1\,
O => \wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(41),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \wrap_cnt_r[3]_i_5_n_0\
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000010001"
)
port map (
I0 => \^axaddr_offset_r_reg[0]\,
I1 => \^axaddr_offset\(0),
I2 => \axaddr_offset_r_reg[2]_0\(0),
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]\(2),
O => \^wrap_cnt_r_reg[2]\
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F00EFFFFF00E0000"
)
port map (
I0 => \^axaddr_offset\(1),
I1 => \axaddr_offset_r_reg[2]_0\(0),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset\(0),
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCC2FFFFCCC20000"
)
port map (
I0 => \^axaddr_offset\(1),
I1 => \axaddr_offset_r_reg[2]_0\(0),
I2 => \^axaddr_offset\(0),
I3 => \^axaddr_offset_r_reg[0]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(2),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE00FFFFFE00FE00"
)
port map (
I0 => \^axaddr_offset_r_reg[0]\,
I1 => \^axaddr_offset\(0),
I2 => \axaddr_offset_r_reg[2]_0\(0),
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(3),
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \^axlen_cnt_reg[3]\,
I1 => \wrap_second_len_r[3]_i_3_n_0\,
I2 => \^q\(36),
I3 => \^q\(5),
I4 => \^q\(35),
I5 => \^q\(6),
O => \wrap_second_len_r[3]_i_2_n_0\
);
\wrap_second_len_r[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(3),
O => \wrap_second_len_r[3]_i_3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_17_axic_register_slice";
end \gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\;
architecture STRUCTURE of \gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair79";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_17_axic_register_slice";
end \gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\;
architecture STRUCTURE of \gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[4]_i_4\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_valid_i_i_1__2\ : label is "soft_lutpair84";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[4]_rep__0\,
O => \cnt_read_reg[2]_rep__0\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \cnt_read_reg[4]_rep__0\,
I3 => \^skid_buffer_reg[0]_0\,
O => \m_valid_i_i_1__2_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__2_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \cnt_read_reg[4]_rep__0\,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel : entity is "axi_protocol_converter_v2_1_17_b2s_b_channel";
end gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel is
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_5 : STD_LOGIC;
signal \bresp_cnt[7]_i_6_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair124";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_3,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bresp_push => bresp_push,
bvalid_i_reg => bid_fifo_0_n_5,
bvalid_i_reg_0 => \^si_rs_bvalid\,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0\,
\in\(15 downto 0) => \in\(15 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(1),
I1 => \bresp_cnt_reg__0\(0),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_6_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_6_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_6_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_3,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_5,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACEAAAA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[0]\,
I1 => m_axi_bresp(0),
I2 => m_axi_bresp(1),
I3 => \s_bresp_acc_reg_n_0_[1]\,
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EC"
)
port map (
I0 => m_axi_bresp(1),
I1 => \s_bresp_acc_reg_n_0_[1]\,
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^si_rs_bvalid\,
I1 => si_rs_bready,
O => shandshake
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
sel_first_0 : out STD_LOGIC;
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[2]\ : out STD_LOGIC;
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
\m_payload_i_reg[47]_1\ : in STD_LOGIC;
\next\ : in STD_LOGIC;
axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator : entity is "axi_protocol_converter_v2_1_17_b2s_cmd_translator";
end gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator is
signal incr_cmd_0_n_10 : STD_LOGIC;
signal incr_cmd_0_n_11 : STD_LOGIC;
signal incr_cmd_0_n_12 : STD_LOGIC;
signal incr_cmd_0_n_13 : STD_LOGIC;
signal incr_cmd_0_n_14 : STD_LOGIC;
signal incr_cmd_0_n_15 : STD_LOGIC;
signal incr_cmd_0_n_16 : STD_LOGIC;
signal incr_cmd_0_n_4 : STD_LOGIC;
signal incr_cmd_0_n_5 : STD_LOGIC;
signal incr_cmd_0_n_6 : STD_LOGIC;
signal incr_cmd_0_n_7 : STD_LOGIC;
signal incr_cmd_0_n_8 : STD_LOGIC;
signal incr_cmd_0_n_9 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
incr_cmd_0: entity work.gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd
port map (
E(0) => E(0),
Q(0) => Q(0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_incr_reg[0]_0\ => sel_first_0,
\axaddr_incr_reg[11]_0\(10) => incr_cmd_0_n_4,
\axaddr_incr_reg[11]_0\(9) => incr_cmd_0_n_5,
\axaddr_incr_reg[11]_0\(8) => incr_cmd_0_n_6,
\axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_7,
\axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_8,
\axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_9,
\axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_10,
\axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_11,
\axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_12,
\axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_13,
\axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_14,
\axlen_cnt_reg[2]_0\ => \axlen_cnt_reg[2]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[11]\ => incr_cmd_0_n_15,
\m_axi_awaddr[5]\ => incr_cmd_0_n_16,
\m_payload_i_reg[46]\(9 downto 8) => \m_payload_i_reg[47]\(18 downto 17),
\m_payload_i_reg[46]\(7 downto 5) => \m_payload_i_reg[47]\(14 downto 12),
\m_payload_i_reg[46]\(4) => \m_payload_i_reg[47]\(5),
\m_payload_i_reg[46]\(3 downto 0) => \m_payload_i_reg[47]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\,
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg,
sel_first_reg_0 => sel_first_reg_1,
\state_reg[0]\(0) => \state_reg[0]\(0),
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(0) => \state_reg[1]_0\(0)
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[47]\(15),
I2 => s_axburst_eq0,
O => \state_reg[1]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
aclk => aclk,
\axaddr_incr_reg[11]\(10) => incr_cmd_0_n_4,
\axaddr_incr_reg[11]\(9) => incr_cmd_0_n_5,
\axaddr_incr_reg[11]\(8) => incr_cmd_0_n_6,
\axaddr_incr_reg[11]\(7) => incr_cmd_0_n_7,
\axaddr_incr_reg[11]\(6) => incr_cmd_0_n_8,
\axaddr_incr_reg[11]\(5) => incr_cmd_0_n_9,
\axaddr_incr_reg[11]\(4) => incr_cmd_0_n_10,
\axaddr_incr_reg[11]\(3) => incr_cmd_0_n_11,
\axaddr_incr_reg[11]\(2) => incr_cmd_0_n_12,
\axaddr_incr_reg[11]\(1) => incr_cmd_0_n_13,
\axaddr_incr_reg[11]\(0) => incr_cmd_0_n_14,
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_2\ => \axaddr_offset_r_reg[3]_1\,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[47]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[47]\(13 downto 0),
\m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_1\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
\next\ => \next\,
sel_first_reg_0 => sel_first,
sel_first_reg_1 => sel_first_reg_2,
sel_first_reg_2 => incr_cmd_0_n_15,
sel_first_reg_3 => incr_cmd_0_n_16,
si_rs_awvalid => si_rs_awvalid,
\state_reg[0]\(0) => \state_reg[0]\(0),
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 is
port (
sel_first_reg_0 : out STD_LOGIC;
sel_first : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[0]\ : out STD_LOGIC;
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 19 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_arvalid : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
sel_first_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_17_b2s_cmd_translator";
end gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 is
signal incr_cmd_0_n_10 : STD_LOGIC;
signal incr_cmd_0_n_11 : STD_LOGIC;
signal incr_cmd_0_n_12 : STD_LOGIC;
signal incr_cmd_0_n_13 : STD_LOGIC;
signal incr_cmd_0_n_14 : STD_LOGIC;
signal incr_cmd_0_n_15 : STD_LOGIC;
signal incr_cmd_0_n_3 : STD_LOGIC;
signal incr_cmd_0_n_4 : STD_LOGIC;
signal incr_cmd_0_n_5 : STD_LOGIC;
signal incr_cmd_0_n_6 : STD_LOGIC;
signal incr_cmd_0_n_7 : STD_LOGIC;
signal incr_cmd_0_n_8 : STD_LOGIC;
signal incr_cmd_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
signal wrap_cmd_0_n_6 : STD_LOGIC;
signal wrap_cmd_0_n_7 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair17";
begin
incr_cmd_0: entity work.gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2
port map (
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(10 downto 8) => Q(18 downto 16),
Q(7 downto 5) => Q(14 downto 12),
Q(4) => Q(5),
Q(3 downto 0) => Q(3 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[0]_0\ => sel_first,
\axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_3,
\axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_4,
\axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_5,
\axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_6,
\axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_7,
\axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_8,
\axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_9,
\axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_10,
\axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\,
incr_next_pending => incr_next_pending,
\m_axi_araddr[11]\ => incr_cmd_0_n_11,
\m_axi_araddr[1]\ => incr_cmd_0_n_15,
\m_axi_araddr[2]\ => incr_cmd_0_n_14,
\m_axi_araddr[3]\ => incr_cmd_0_n_13,
\m_axi_araddr[5]\ => incr_cmd_0_n_12,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\,
\m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1(0) => sel_first_reg_4(0),
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\ => \state_reg[1]_0\,
\state_reg[1]_0\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => Q(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_cmd_0_n_6,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_cmd_0_n_7,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => Q(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
Q(18 downto 14) => Q(19 downto 15),
Q(13 downto 0) => Q(13 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\(7) => incr_cmd_0_n_3,
\axaddr_incr_reg[11]\(6) => incr_cmd_0_n_4,
\axaddr_incr_reg[11]\(5) => incr_cmd_0_n_5,
\axaddr_incr_reg[11]\(4) => incr_cmd_0_n_6,
\axaddr_incr_reg[11]\(3) => incr_cmd_0_n_7,
\axaddr_incr_reg[11]\(2) => incr_cmd_0_n_8,
\axaddr_incr_reg[11]\(1) => incr_cmd_0_n_9,
\axaddr_incr_reg[11]\(0) => incr_cmd_0_n_10,
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_2\ => \axaddr_offset_r_reg[3]_1\,
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
s_axburst_eq0_reg => wrap_cmd_0_n_6,
s_axburst_eq1_reg => wrap_cmd_0_n_7,
sel_first_i => sel_first_i,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_11,
sel_first_reg_3 => incr_cmd_0_n_12,
sel_first_reg_4 => incr_cmd_0_n_13,
sel_first_reg_5 => incr_cmd_0_n_14,
sel_first_reg_6 => incr_cmd_0_n_15,
si_rs_arvalid => si_rs_arvalid,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]\,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel is
port (
m_valid_i_reg : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel : entity is "axi_protocol_converter_v2_1_17_b2s_r_channel";
end gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_1 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_4 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \state_reg[1]_rep_0\,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_1,
\cnt_read_reg[4]_rep__2_2\ => rd_data_fifo_0_n_2,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_4
);
transaction_fifo_0: entity work.\gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__3\ => rd_data_fifo_0_n_2,
\cnt_read_reg[0]_rep__3_0\ => rd_data_fifo_0_n_4,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => rd_data_fifo_0_n_1,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 54 downto 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 54 downto 0 );
axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[2]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[2]_0\ : out STD_LOGIC;
axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]_0\ : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
s_ready_i0 : in STD_LOGIC;
m_valid_i0 : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_2\ : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
b_push : in STD_LOGIC;
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_4\ : in STD_LOGIC;
\state_reg[0]_rep_0\ : in STD_LOGIC;
\state_reg[1]_rep_2\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice : entity is "axi_register_slice_v2_1_17_axi_register_slice";
end gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice is
signal \ar.ar_pipe_n_2\ : STD_LOGIC;
signal \aw.aw_pipe_n_1\ : STD_LOGIC;
signal \aw.aw_pipe_n_90\ : STD_LOGIC;
begin
\ar.ar_pipe\: entity work.gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice
port map (
O(3 downto 0) => O(3 downto 0),
Q(54 downto 0) => \s_arid_r_reg[11]\(54 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\,
\aresetn_d_reg[0]_0\ => \aw.aw_pipe_n_90\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
axaddr_offset_0(1 downto 0) => axaddr_offset_0(2 downto 1),
\axaddr_offset_r_reg[0]\ => axaddr_offset_0(0),
\axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]_0\,
\axaddr_offset_r_reg[2]_0\(0) => \axaddr_offset_r_reg[2]_3\(0),
\axaddr_offset_r_reg[2]_1\ => \axaddr_offset_r_reg[2]_4\,
\axaddr_offset_r_reg[3]\ => si_rs_arvalid,
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \axaddr_offset_r_reg[3]_1\(2 downto 0),
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_2\,
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i0 => m_valid_i0,
m_valid_i_reg_0 => \ar.ar_pipe_n_2\,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
next_pending_r_reg => next_pending_r_reg_0,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_ready_i0 => s_ready_i0,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_2\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
\wrap_cnt_r_reg[2]\ => \wrap_cnt_r_reg[2]_0\,
\wrap_cnt_r_reg[3]\(1 downto 0) => \wrap_cnt_r_reg[3]_0\(1 downto 0),
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
\wrap_second_len_r_reg[1]\ => \wrap_second_len_r_reg[1]_0\,
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_2\(3 downto 0)
);
\aw.aw_pipe\: entity work.gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0
port map (
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
Q(54 downto 0) => Q(54 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => \aw.aw_pipe_n_90\,
\aresetn_d_reg[1]_inv_0\ => \ar.ar_pipe_n_2\,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
axaddr_offset(1 downto 0) => axaddr_offset(2 downto 1),
\axaddr_offset_r_reg[0]\ => axaddr_offset(0),
\axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]\,
\axaddr_offset_r_reg[2]_0\(0) => \axaddr_offset_r_reg[2]_1\(0),
\axaddr_offset_r_reg[2]_1\ => \axaddr_offset_r_reg[2]_2\,
\axaddr_offset_r_reg[3]\(2 downto 0) => \axaddr_offset_r_reg[3]\(2 downto 0),
\axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_0\,
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => \aw.aw_pipe_n_1\,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_cnt_r_reg[2]\ => \wrap_cnt_r_reg[2]\,
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
\wrap_second_len_r_reg[1]\ => \wrap_second_len_r_reg[1]\,
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
\b.b_pipe\: entity work.\gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\,
\aresetn_d_reg[1]_inv\ => \ar.ar_pipe_n_2\,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
\r.r_pipe\: entity work.\gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\,
\aresetn_d_reg[1]_inv\ => \ar.ar_pipe_n_2\,
\cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
\cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\,
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel is
port (
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_valid_i0 : out STD_LOGIC;
s_ready_i0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
r_rlast : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arready : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[5]\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel : entity is "axi_protocol_converter_v2_1_17_b2s_ar_channel";
end gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel is
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_10 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_6 : STD_LOGIC;
signal ar_cmd_fsm_0_n_8 : STD_LOGIC;
signal ar_cmd_fsm_0_n_9 : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_3 : STD_LOGIC;
signal \incr_cmd_0/sel_first\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push_r_reg\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^state_reg[0]_rep\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\axaddr_offset_r_reg[2]\(0) <= \^axaddr_offset_r_reg[2]\(0);
\axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
\state_reg[0]_rep\(1 downto 0) <= \^state_reg[0]_rep\(1 downto 0);
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
\wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0);
ar_cmd_fsm_0: entity work.gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm
port map (
D(0) => ar_cmd_fsm_0_n_6,
E(0) => ar_cmd_fsm_0_n_8,
Q(1 downto 0) => \^state_reg[0]_rep\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[0]\(0) => ar_cmd_fsm_0_n_16,
axaddr_offset(0) => axaddr_offset(0),
\axaddr_offset_r_reg[2]\(0) => \^axaddr_offset_r_reg[2]\(0),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_0\(1) => \^axaddr_offset_r_reg[3]\(2),
\axaddr_offset_r_reg[3]_0\(0) => \wrap_cmd_0/axaddr_offset_r\(2),
\axlen_cnt_reg[7]\ => ar_cmd_fsm_0_n_0,
\axlen_cnt_reg[7]_0\ => cmd_translator_0_n_3,
\cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \m_payload_i_reg[0]\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[46]\(0) => Q(18),
\m_payload_i_reg[5]\ => \m_payload_i_reg[5]\,
m_valid_i0 => m_valid_i0,
r_push_r_reg => \^r_push_r_reg\,
s_axburst_eq1_reg => cmd_translator_0_n_10,
s_axi_arvalid => s_axi_arvalid,
s_ready_i0 => s_ready_i0,
s_ready_i_reg => s_ready_i_reg,
sel_first => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_9,
sel_first_reg_0 => ar_cmd_fsm_0_n_10,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => cmd_translator_0_n_0,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\(0) => \^wrap_boundary_axaddr_r_reg[11]\,
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]_0\,
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
\wrap_second_len_r_reg[0]\(0) => \wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[0]_0\(0) => \^wrap_second_len_r_reg[3]\(0)
);
cmd_translator_0: entity work.gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1
port map (
D(3) => axaddr_offset(2),
D(2) => \^axaddr_offset_r_reg[2]\(0),
D(1 downto 0) => axaddr_offset(1 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(19 downto 0) => Q(19 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_offset_r_reg[3]\(3) => \^axaddr_offset_r_reg[3]\(2),
\axaddr_offset_r_reg[3]\(2) => \wrap_cmd_0/axaddr_offset_r\(2),
\axaddr_offset_r_reg[3]\(1 downto 0) => \^axaddr_offset_r_reg[3]\(1 downto 0),
\axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_1\,
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\,
\axlen_cnt_reg[0]\ => cmd_translator_0_n_3,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
\m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_8,
r_rlast => r_rlast,
sel_first => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_0,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => ar_cmd_fsm_0_n_10,
sel_first_reg_3 => ar_cmd_fsm_0_n_9,
sel_first_reg_4(0) => ar_cmd_fsm_0_n_16,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => cmd_translator_0_n_10,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]\(1 downto 0) => \^state_reg[0]_rep\(1 downto 0),
\state_reg[1]_0\ => ar_cmd_fsm_0_n_0,
\state_reg[1]_rep\ => \^r_push_r_reg\,
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
\wrap_second_len_r_reg[3]\(3 downto 0) => \^wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 1) => D(2 downto 0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => \wrap_second_len_r_reg[3]_0\(1 downto 0),
\wrap_second_len_r_reg[3]_1\(0) => ar_cmd_fsm_0_n_6
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(20),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(30),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(31),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(21),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(22),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(23),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(24),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(25),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(26),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(27),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(28),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(29),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel is
port (
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[5]\ : in STD_LOGIC;
axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel : entity is "axi_protocol_converter_v2_1_17_b2s_aw_channel";
end gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel is
signal aw_cmd_fsm_0_n_12 : STD_LOGIC;
signal aw_cmd_fsm_0_n_14 : STD_LOGIC;
signal aw_cmd_fsm_0_n_15 : STD_LOGIC;
signal aw_cmd_fsm_0_n_16 : STD_LOGIC;
signal aw_cmd_fsm_0_n_2 : STD_LOGIC;
signal aw_cmd_fsm_0_n_8 : STD_LOGIC;
signal aw_cmd_fsm_0_n_9 : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_5 : STD_LOGIC;
signal cmd_translator_0_n_6 : STD_LOGIC;
signal \incr_cmd_0/sel_first\ : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \next\ : STD_LOGIC;
signal sel_first : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^state_reg[0]_rep\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 0 to 0 );
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\axaddr_offset_r_reg[2]\(0) <= \^axaddr_offset_r_reg[2]\(0);
\axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0);
\state_reg[0]_rep\(1 downto 0) <= \^state_reg[0]_rep\(1 downto 0);
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
\wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0);
aw_cmd_fsm_0: entity work.gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm
port map (
D(0) => wrap_cnt(0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^state_reg[0]_rep\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
axaddr_offset(0) => axaddr_offset(0),
\axaddr_offset_r_reg[2]\(0) => \^axaddr_offset_r_reg[2]\(0),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_0\(1) => \^axaddr_offset_r_reg[3]\(2),
\axaddr_offset_r_reg[3]_0\(0) => \wrap_cmd_0/axaddr_offset_r\(2),
\axaddr_wrap_reg[11]\(0) => aw_cmd_fsm_0_n_14,
\axlen_cnt_reg[0]\(0) => aw_cmd_fsm_0_n_8,
\axlen_cnt_reg[0]_0\(0) => cmd_translator_0_n_5,
\axlen_cnt_reg[7]\ => \axlen_cnt_reg[7]\,
\axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]_0\,
\axlen_cnt_reg[7]_1\ => aw_cmd_fsm_0_n_2,
\axlen_cnt_reg[7]_2\ => cmd_translator_0_n_6,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\(0) => E(0),
\m_payload_i_reg[46]\(2) => Q(18),
\m_payload_i_reg[46]\(1 downto 0) => Q(16 downto 15),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\,
\m_payload_i_reg[5]\ => \m_payload_i_reg[5]\,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_9,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_12,
s_axburst_eq1_reg_0 => cmd_translator_0_n_12,
sel_first => sel_first,
sel_first_0 => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_15,
sel_first_reg_0 => aw_cmd_fsm_0_n_16,
sel_first_reg_1 => cmd_translator_0_n_2,
si_rs_awvalid => si_rs_awvalid,
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]_0\,
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[0]\(0) => \wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[0]_0\(0) => \^wrap_second_len_r_reg[3]\(0)
);
cmd_translator_0: entity work.gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator
port map (
D(3) => axaddr_offset(2),
D(2) => \^axaddr_offset_r_reg[2]\(0),
D(1 downto 0) => axaddr_offset(1 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(0) => cmd_translator_0_n_5,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_offset_r_reg[3]\(3) => \^axaddr_offset_r_reg[3]\(2),
\axaddr_offset_r_reg[3]\(2) => \wrap_cmd_0/axaddr_offset_r\(2),
\axaddr_offset_r_reg[3]\(1 downto 0) => \^axaddr_offset_r_reg[3]\(1 downto 0),
\axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_1\,
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\,
\axlen_cnt_reg[2]\ => cmd_translator_0_n_6,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_9,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_12,
\m_payload_i_reg[47]\(19 downto 0) => Q(19 downto 0),
\m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[47]_1\ => \m_payload_i_reg[47]_0\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
sel_first => sel_first,
sel_first_0 => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_16,
sel_first_reg_2 => aw_cmd_fsm_0_n_15,
si_rs_awvalid => si_rs_awvalid,
\state_reg[0]\(0) => aw_cmd_fsm_0_n_14,
\state_reg[0]_rep\ => aw_cmd_fsm_0_n_2,
\state_reg[1]\(1 downto 0) => \^state_reg[0]_rep\(1 downto 0),
\state_reg[1]_0\(0) => aw_cmd_fsm_0_n_8,
\state_reg[1]_rep\ => cmd_translator_0_n_12,
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 0) => \^wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => D(1 downto 0),
\wrap_second_len_r_reg[3]_0\(0) => wrap_cnt(0),
\wrap_second_len_r_reg[3]_1\(3 downto 1) => \wrap_second_len_r_reg[3]_0\(2 downto 0),
\wrap_second_len_r_reg[3]_1\(0) => \wrap_cmd_0/wrap_second_len\(0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(20),
Q => \in\(4),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(21),
Q => \in\(5),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(22),
Q => \in\(6),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(23),
Q => \in\(7),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(29),
Q => \in\(13),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(19),
Q => \in\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awvalid : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s : entity is "axi_protocol_converter_v2_1_17_b2s";
end gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s is
signal \RD.ar_channel_0_n_0\ : STD_LOGIC;
signal \RD.ar_channel_0_n_10\ : STD_LOGIC;
signal \RD.ar_channel_0_n_11\ : STD_LOGIC;
signal \RD.ar_channel_0_n_16\ : STD_LOGIC;
signal \RD.ar_channel_0_n_3\ : STD_LOGIC;
signal \RD.ar_channel_0_n_4\ : STD_LOGIC;
signal \RD.ar_channel_0_n_46\ : STD_LOGIC;
signal \RD.ar_channel_0_n_47\ : STD_LOGIC;
signal \RD.ar_channel_0_n_48\ : STD_LOGIC;
signal \RD.ar_channel_0_n_49\ : STD_LOGIC;
signal \RD.ar_channel_0_n_5\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_1\ : STD_LOGIC;
signal SI_REG_n_132 : STD_LOGIC;
signal SI_REG_n_133 : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_137 : STD_LOGIC;
signal SI_REG_n_138 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_153 : STD_LOGIC;
signal SI_REG_n_154 : STD_LOGIC;
signal SI_REG_n_155 : STD_LOGIC;
signal SI_REG_n_156 : STD_LOGIC;
signal SI_REG_n_157 : STD_LOGIC;
signal SI_REG_n_161 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_168 : STD_LOGIC;
signal SI_REG_n_169 : STD_LOGIC;
signal SI_REG_n_170 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_172 : STD_LOGIC;
signal SI_REG_n_173 : STD_LOGIC;
signal SI_REG_n_174 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_181 : STD_LOGIC;
signal SI_REG_n_182 : STD_LOGIC;
signal SI_REG_n_26 : STD_LOGIC;
signal SI_REG_n_64 : STD_LOGIC;
signal SI_REG_n_8 : STD_LOGIC;
signal SI_REG_n_82 : STD_LOGIC;
signal \WR.aw_channel_0_n_0\ : STD_LOGIC;
signal \WR.aw_channel_0_n_10\ : STD_LOGIC;
signal \WR.aw_channel_0_n_15\ : STD_LOGIC;
signal \WR.aw_channel_0_n_3\ : STD_LOGIC;
signal \WR.aw_channel_0_n_4\ : STD_LOGIC;
signal \WR.aw_channel_0_n_47\ : STD_LOGIC;
signal \WR.aw_channel_0_n_48\ : STD_LOGIC;
signal \WR.aw_channel_0_n_49\ : STD_LOGIC;
signal \WR.aw_channel_0_n_50\ : STD_LOGIC;
signal \WR.aw_channel_0_n_9\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \ar.ar_pipe/m_valid_i0\ : STD_LOGIC;
signal \ar.ar_pipe/p_1_in\ : STD_LOGIC;
signal \ar.ar_pipe/s_ready_i0\ : STD_LOGIC;
signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw.aw_pipe/p_1_in\ : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axaddr_incr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
s_axi_arready <= \^s_axi_arready\;
\RD.ar_channel_0\: entity work.gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel
port map (
D(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 1),
E(0) => \ar.ar_pipe/p_1_in\,
O(3) => SI_REG_n_140,
O(2) => SI_REG_n_141,
O(1) => SI_REG_n_142,
O(0) => SI_REG_n_143,
Q(31 downto 20) => s_arid(11 downto 0),
Q(19 downto 16) => si_rs_arlen(3 downto 0),
Q(15) => si_rs_arburst(1),
Q(14) => SI_REG_n_82,
Q(13 downto 12) => si_rs_arsize(1 downto 0),
Q(11 downto 0) => si_rs_araddr(11 downto 0),
S(3) => \RD.ar_channel_0_n_46\,
S(2) => \RD.ar_channel_0_n_47\,
S(1) => \RD.ar_channel_0_n_48\,
S(0) => \RD.ar_channel_0_n_49\,
aclk => aclk,
areset_d1 => areset_d1,
axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(1 downto 0),
\axaddr_offset_r_reg[2]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2),
\axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3),
\axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(1 downto 0),
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_161,
\axaddr_offset_r_reg[3]_1\ => SI_REG_n_165,
\cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_1\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_4\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_5\,
\m_payload_i_reg[3]\(3) => SI_REG_n_132,
\m_payload_i_reg[3]\(2) => SI_REG_n_133,
\m_payload_i_reg[3]\(1) => SI_REG_n_134,
\m_payload_i_reg[3]\(0) => SI_REG_n_135,
\m_payload_i_reg[47]\ => SI_REG_n_64,
\m_payload_i_reg[47]_0\ => SI_REG_n_167,
\m_payload_i_reg[5]\ => SI_REG_n_166,
\m_payload_i_reg[6]\(6) => SI_REG_n_176,
\m_payload_i_reg[6]\(5) => SI_REG_n_177,
\m_payload_i_reg[6]\(4) => SI_REG_n_178,
\m_payload_i_reg[6]\(3) => SI_REG_n_179,
\m_payload_i_reg[6]\(2) => SI_REG_n_180,
\m_payload_i_reg[6]\(1) => SI_REG_n_181,
\m_payload_i_reg[6]\(0) => SI_REG_n_182,
\m_payload_i_reg[7]\(3) => SI_REG_n_136,
\m_payload_i_reg[7]\(2) => SI_REG_n_137,
\m_payload_i_reg[7]\(1) => SI_REG_n_138,
\m_payload_i_reg[7]\(0) => SI_REG_n_139,
m_valid_i0 => \ar.ar_pipe/m_valid_i0\,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push_r_reg => \RD.ar_channel_0_n_3\,
r_rlast => r_rlast,
s_axi_arvalid => s_axi_arvalid,
s_ready_i0 => \ar.ar_pipe/s_ready_i0\,
s_ready_i_reg => \^s_axi_arready\,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_0\,
\wrap_cnt_r_reg[3]\ => \RD.ar_channel_0_n_10\,
\wrap_cnt_r_reg[3]_0\ => \RD.ar_channel_0_n_11\,
\wrap_cnt_r_reg[3]_1\ => \RD.ar_channel_0_n_16\,
\wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_156,
\wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_157
);
\RD.r_channel_0\: entity work.gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_0\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_168,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_1\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_3\
);
SI_REG: entity work.gcd_zynq_snick_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice
port map (
D(1 downto 0) => wrap_cnt(3 downto 2),
E(0) => \aw.aw_pipe/p_1_in\,
O(3) => SI_REG_n_140,
O(2) => SI_REG_n_141,
O(1) => SI_REG_n_142,
O(0) => SI_REG_n_143,
Q(54 downto 43) => s_awid(11 downto 0),
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_26,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_47\,
S(2) => \WR.aw_channel_0_n_48\,
S(1) => \WR.aw_channel_0_n_49\,
S(0) => \WR.aw_channel_0_n_50\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_incr_reg[3]\(3) => SI_REG_n_132,
\axaddr_incr_reg[3]\(2) => SI_REG_n_133,
\axaddr_incr_reg[3]\(1) => SI_REG_n_134,
\axaddr_incr_reg[3]\(0) => SI_REG_n_135,
\axaddr_incr_reg[7]\(3) => SI_REG_n_136,
\axaddr_incr_reg[7]\(2) => SI_REG_n_137,
\axaddr_incr_reg[7]\(1) => SI_REG_n_138,
\axaddr_incr_reg[7]\(0) => SI_REG_n_139,
axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(1 downto 0),
axaddr_offset_0(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
axaddr_offset_0(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(1 downto 0),
\axaddr_offset_r_reg[2]\ => SI_REG_n_154,
\axaddr_offset_r_reg[2]_0\ => SI_REG_n_166,
\axaddr_offset_r_reg[2]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2),
\axaddr_offset_r_reg[2]_2\ => \WR.aw_channel_0_n_15\,
\axaddr_offset_r_reg[2]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2),
\axaddr_offset_r_reg[2]_4\ => \RD.ar_channel_0_n_16\,
\axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3),
\axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(1 downto 0),
\axaddr_offset_r_reg[3]_0\ => \WR.aw_channel_0_n_10\,
\axaddr_offset_r_reg[3]_1\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3),
\axaddr_offset_r_reg[3]_1\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(1 downto 0),
\axaddr_offset_r_reg[3]_2\ => \RD.ar_channel_0_n_11\,
\axlen_cnt_reg[3]\ => SI_REG_n_8,
\axlen_cnt_reg[3]_0\ => SI_REG_n_64,
b_push => b_push,
\cnt_read_reg[2]_rep__0\ => SI_REG_n_168,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_0\,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_46\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_47\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_48\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_49\,
m_valid_i0 => \ar.ar_pipe/m_valid_i0\,
m_valid_i_reg(0) => \ar.ar_pipe/p_1_in\,
next_pending_r_reg => SI_REG_n_155,
next_pending_r_reg_0 => SI_REG_n_167,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(54 downto 43) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_82,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => \^s_axi_arready\,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
s_ready_i0 => \ar.ar_pipe/s_ready_i0\,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \WR.aw_channel_0_n_4\,
\state_reg[0]_rep_0\ => \RD.ar_channel_0_n_5\,
\state_reg[1]\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_0\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_0\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_3\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_0\,
\state_reg[1]_rep_2\ => \RD.ar_channel_0_n_4\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_169,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_170,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_171,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_172,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_173,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_174,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_175,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_176,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_177,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_178,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_179,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_180,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_181,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_182,
\wrap_cnt_r_reg[2]\ => SI_REG_n_149,
\wrap_cnt_r_reg[2]_0\ => SI_REG_n_161,
\wrap_cnt_r_reg[3]\ => SI_REG_n_153,
\wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_156,
\wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_157,
\wrap_cnt_r_reg[3]_1\ => SI_REG_n_165,
\wrap_second_len_r_reg[1]\ => \WR.aw_channel_0_n_9\,
\wrap_second_len_r_reg[1]_0\ => \RD.ar_channel_0_n_10\,
\wrap_second_len_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 1),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 1),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0)
);
\WR.aw_channel_0\: entity work.gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel
port map (
D(1 downto 0) => wrap_cnt(3 downto 2),
E(0) => \aw.aw_pipe/p_1_in\,
Q(31 downto 20) => s_awid(11 downto 0),
Q(19 downto 16) => si_rs_awlen(3 downto 0),
Q(15) => si_rs_awburst(1),
Q(14) => SI_REG_n_26,
Q(13 downto 12) => si_rs_awsize(1 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_47\,
S(2) => \WR.aw_channel_0_n_48\,
S(1) => \WR.aw_channel_0_n_49\,
S(0) => \WR.aw_channel_0_n_50\,
aclk => aclk,
areset_d1 => areset_d1,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(1 downto 0),
\axaddr_offset_r_reg[2]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2),
\axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3),
\axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(1 downto 0),
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_149,
\axaddr_offset_r_reg[3]_1\ => SI_REG_n_153,
\axlen_cnt_reg[7]\ => \WR.aw_channel_0_n_3\,
\axlen_cnt_reg[7]_0\ => \WR.aw_channel_0_n_4\,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\,
\in\(15 downto 4) => b_awid(11 downto 0),
\in\(3 downto 0) => b_awlen(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[47]\ => SI_REG_n_8,
\m_payload_i_reg[47]_0\ => SI_REG_n_155,
\m_payload_i_reg[5]\ => SI_REG_n_154,
\m_payload_i_reg[6]\(6) => SI_REG_n_169,
\m_payload_i_reg[6]\(5) => SI_REG_n_170,
\m_payload_i_reg[6]\(4) => SI_REG_n_171,
\m_payload_i_reg[6]\(3) => SI_REG_n_172,
\m_payload_i_reg[6]\(2) => SI_REG_n_173,
\m_payload_i_reg[6]\(1) => SI_REG_n_174,
\m_payload_i_reg[6]\(0) => SI_REG_n_175,
si_rs_awvalid => si_rs_awvalid,
\state_reg[0]_rep\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_0\,
\wrap_cnt_r_reg[3]\ => \WR.aw_channel_0_n_9\,
\wrap_cnt_r_reg[3]_0\ => \WR.aw_channel_0_n_10\,
\wrap_cnt_r_reg[3]_1\ => \WR.aw_channel_0_n_15\,
\wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 1)
);
\WR.b_channel_0\: entity work.gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\,
\in\(15 downto 4) => b_awid(11 downto 0),
\in\(3 downto 0) => b_awlen(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0)
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "axi_protocol_converter_v2_1_17_axi_protocol_converter";
attribute P_AXI3 : integer;
attribute P_AXI3 of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b10";
end gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_zynq_snick_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of gcd_zynq_snick_auto_pc_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of gcd_zynq_snick_auto_pc_0 : entity is "gcd_zynq_snick_auto_pc_0,axi_protocol_converter_v2_1_17_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of gcd_zynq_snick_auto_pc_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of gcd_zynq_snick_auto_pc_0 : entity is "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2";
end gcd_zynq_snick_auto_pc_0;
architecture STRUCTURE of gcd_zynq_snick_auto_pc_0 is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN";
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST RST";
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 49999947, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute X_INTERFACE_INFO of s_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 49999947, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute X_INTERFACE_INFO of s_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute X_INTERFACE_INFO of s_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
attribute X_INTERFACE_INFO of s_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
attribute X_INTERFACE_INFO of s_axi_arid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARID";
attribute X_INTERFACE_INFO of s_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
attribute X_INTERFACE_INFO of s_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
attribute X_INTERFACE_INFO of s_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARQOS";
attribute X_INTERFACE_INFO of s_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute X_INTERFACE_INFO of s_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
attribute X_INTERFACE_INFO of s_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
attribute X_INTERFACE_INFO of s_axi_awid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWID";
attribute X_INTERFACE_INFO of s_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
attribute X_INTERFACE_INFO of s_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
attribute X_INTERFACE_INFO of s_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWQOS";
attribute X_INTERFACE_INFO of s_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
attribute X_INTERFACE_INFO of s_axi_bid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BID";
attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute X_INTERFACE_INFO of s_axi_rid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RID";
attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute X_INTERFACE_INFO of s_axi_wid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WID";
attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
inst: entity work.gcd_zynq_snick_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
entity nor104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity nor104;
architecture rtl of nor104 is
begin
c_o <= a_i nor b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity nor104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity nor104;
architecture rtl of nor104 is
begin
c_o <= a_i nor b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity nor104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity nor104;
architecture rtl of nor104 is
begin
c_o <= a_i nor b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity nor104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity nor104;
architecture rtl of nor104 is
begin
c_o <= a_i nor b_i;
end architecture rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr1spax_ddr
-- File: ddr1spax_ddr.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Merged 16/32/64-bit DDR/mobile-DDR backend
-- Based on ddrsp*a and ddr2spax_ddr
--------------------------------------------------------------------------------
-- Added features from the original ddrspa:
-- * Separated AHB,DDR parts of controller like for DDR2SPA
-- * 64/32/16 bit interfaces in the same entity
-- * Checkbit support for use with ft_ddr2spax_ahb front-end.
-- * Extended timing fields plus tRAS setting to meet DDR400 timing.
-- * Configurable burst length
-- * Support for PHY:s with read data valid signaling and extra latency
-- Incompatibility/differences to the original ddrspa:
-- * The mobile DDR had an undocumented feature that tRFC was extended with 8
-- cycles if the TRP bit was set. This is replaced by the extended
-- timing fields.
-- * ddrsp16a used a separate read-clock supplied only from the Spartan PHY.
-- * Reads/writes are made as multiple length-2 burst commands.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ddr1spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
nosync : integer := 0;
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
hasdqvalid : integer := 0;
readdly : integer := 0;
regoutput : integer := 1;
ddr400 : integer := 1;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end ddr1spax_ddr;
architecture rtl of ddr1spax_ddr is
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(ddrbits*2);
constant l2ddr_burstlen: integer := l2blen-l2ddrw;
-- constant oepols: std_logic := tosl(oepol);
-- Write buffer dimensions
-- Write buffer is addressable down to 32-bit level on write (AHB) side.
constant wbuf_rabits: integer := 1+l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant wbuf_rdbits: integer := 2*ddrbits;
-- Read buffer dimensions
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := 2*(ddrbits+chkbits);
type ddrstate is (dsidle,dsact1,dsact2,dsact3,dswr1,dswr2,dswr3,dswr4,dswr5,dswr6,
dsrd1,dsrd2,dsrd3,dsrd4,dsreg1,dsreg2,dscmd1,dscmd2,dspdown1,dspdown2,dsref1,
dssrr1,dssrr2);
type ddrinitstate is (disrstdel,disidle,disrun,disfinished);
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(4 downto 0);
trp : std_logic_vector(1 downto 0); -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
ds : std_logic_vector(5 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
mobileen : std_logic; -- Mobile SD support, Mobile SD enabled
txsr : std_logic_vector(5 downto 0); -- Exit Self Refresh timing
txp : std_logic_vector(1 downto 0); -- Exit Power-Down timing
tcke : std_logic; -- Clock enable timing
cl : std_logic; -- CAS latency 2/3 (0/1)
conf : std_logic_vector(63 downto 0); -- PHY control
tras : std_logic_vector(1 downto 0); -- tRAS minimum (6-9 cycles)
twr : std_logic; -- tWR write recovery, 2/3 cycles
end record;
type ddr_reg_type is record
s : ddrstate;
initstate : ddrinitstate;
cfg : sdram_cfg_type;
resp,resp2 : ddr_response_type;
req1,req2 : ddr_request_type;
start1,start2 : std_logic;
start3 : std_logic;
ramaddr : std_logic_vector(rbuf_wabits-1 downto 0);
readpipe : std_logic_vector(4+readdly downto 0);
initpos : std_logic_vector(2 downto 0);
cmdctr : std_logic_vector(7 downto 0);
readdone : std_logic;
refctr : std_logic_vector(17 downto 0);
refpend : std_logic;
idlectr : std_logic_vector(3 downto 0);
pdowns : std_logic_vector(1 downto 0);
sdo_casn : std_logic;
sdo_rasn : std_logic;
sdo_wen : std_logic;
sdo_csn : std_logic_vector(1 downto 0);
sdo_ba : std_logic_vector(1 downto 0);
sdo_address : std_logic_vector(14 downto 0);
sdo_data : std_logic_vector(2*ddrbits-1 downto 0);
sdo_dqm : std_logic_vector(ddrbits/4-1 downto 0);
sdo_cb : std_logic_vector(2*chkbits downto 0);
sdo_ck : std_logic_vector(2 downto 0);
sdo_bdrive : std_logic;
sdo_qdrive : std_logic;
end record;
signal dr,ndr: ddr_reg_type;
constant onev: std_logic_vector(15 downto 0) := x"FFFF";
constant zerov: std_logic_vector(15 downto 0) := x"0000";
signal arst : std_ulogic;
begin
arst <= testrst when (scantest/=0 and ddr_syncrst=0) and testen='1' else ddr_rst;
ddrcomb: process(ddr_rst,sdi,request,frequest,start_tog,dr,wbrdata,testen,testoen)
variable dv: ddr_reg_type;
variable o: ddrctrl_out_type;
variable rbw: std_logic;
variable rbwd: std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
variable vstart, vstartd, vdone, incdone: std_logic;
variable vrctr: std_logic_vector(3 downto 0);
variable vreq,vreqf: ddr_request_type;
variable regsd1 : std_logic_vector(31 downto 0);
variable regsd2 : std_logic_vector(31 downto 0);
variable regsd3 : std_logic_vector(31 downto 0);
variable lastreadcmd: std_logic;
variable lastwrite : std_logic;
variable vmaskfirst, vmasklast: std_logic_vector(ddrbits/4-1 downto 0);
variable ea: std_logic_vector(3 downto 2);
variable inc_sdoaddr, inc_ramaddr: std_logic;
variable datavalid: std_logic;
variable vcsf: std_logic_vector(1 downto 0);
variable vrowf: std_logic_vector(14 downto 0);
variable vbankf: std_logic_vector(1 downto 0);
variable vcol,vcoladdr: std_logic_vector(14 downto 1);
variable seqin,seqout: std_logic_vector(3 downto 0);
variable regrdata: std_logic_vector(2*ddrbits-1 downto 0);
variable regad: std_logic_vector(2 downto 0);
variable wrdreg1,wrdreg2,wrdreg3: std_logic_vector(31 downto 0);
variable reqselv: std_logic_vector(3 downto 0);
begin
---------------------------------------------------------------------------
-- Init vars
---------------------------------------------------------------------------
dv := dr;
o := ddrctrl_out_none;
o.bdrive := '1'; o.qdrive := '1';
vdone := dr.resp.done_tog or dr.resp2.done_tog;
vrctr := dr.resp.rctr_gray or dr.resp2.rctr_gray;
incdone := '0';
lastreadcmd := '0';
lastwrite := '0';
reqselv := reqsel & reqsel & reqsel & reqsel;
-- Config registers
regsd1 := (others => '0');
regsd1(31 downto 15) := dr.cfg.refon & dr.cfg.trp(0) & dr.cfg.trfc(2 downto 0) &
dr.cfg.trcd & dr.cfg.bsize & dr.cfg.csize & dr.cfg.command &
dr.cfg.dllrst & dr.cfg.renable & dr.cfg.cke;
regsd1(11 downto 0) := dr.cfg.refresh;
regsd2 := (others => '0');
regsd2(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd2(14 downto 12) := conv_std_logic_vector(log2(ddrbits/8),3);
if mobile/=0 then regsd2(15):='1'; end if;-- Mobile DDR support
regsd2(19 downto 16) := conv_std_logic_vector(confapi, 4);
regsd3 := (others => '0');
regsd3(31) := dr.cfg.mobileen; -- Mobile DDR enable
regsd3(30) := dr.cfg.cl;
regsd3(24 downto 19) := dr.cfg.tcke & dr.cfg.txsr(3 downto 0) & dr.cfg.txp(0);
regsd3(18 downto 16) := dr.cfg.pmode;
regsd3( 7 downto 0) := dr.cfg.ds(2 downto 0) & dr.cfg.tcsr(1 downto 0)
& dr.cfg.pasr(2 downto 0);
-- Extended timing fields for DDR400
if ddr400 /= 0 then
regsd2(20) := '1'; -- Ext. fields available
regsd3(29 downto 28) := dr.cfg.tras;
regsd3(27 downto 26) := dr.cfg.txsr(5 downto 4);
regsd3(25) := dr.cfg.txp(1);
regsd3(11) := dr.cfg.twr;
regsd3(10) := dr.cfg.trp(1);
regsd3(9 downto 8) := dr.cfg.trfc(4 downto 3);
end if;
-- Data path
rbw := '0';
rbwd := (others => '0');
rbwd(ddrbits-1 downto 0) := sdi.data(ddrbits-1 downto 0);
rbwd(2*ddrbits+chkbits-1 downto ddrbits+chkbits) :=
sdi.data(2*ddrbits-1 downto ddrbits);
if chkbits > 0 then
rbwd(ddrbits+chkbits-1 downto ddrbits) := sdi.cb(chkbits-1 downto 0);
rbwd(2*(ddrbits+chkbits)-1 downto 2*ddrbits+chkbits) :=
sdi.cb(2*chkbits-1 downto chkbits);
end if;
dv.sdo_data(ddrbits-1 downto 0) := wbrdata(ddrbits-1 downto 0);
dv.sdo_data(2*ddrbits-1 downto ddrbits) :=
wbrdata(2*ddrbits+chkbits-1 downto ddrbits+chkbits);
dv.sdo_cb(chkbits) := '0'; -- dummy bit just to ensure length>0
if chkbits > 0 then
dv.sdo_cb(chkbits-1 downto 0) := wbrdata(ddrbits+chkbits-1 downto ddrbits);
dv.sdo_cb(2*chkbits-1 downto chkbits) :=
wbrdata(2*(ddrbits+chkbits)-1 downto 2*ddrbits+chkbits);
end if;
---------------------------------------------------------------------------
-- Request handling logic
---------------------------------------------------------------------------
-- Sync request inputs
dv.req1 := request;
dv.req2 := dr.req1;
dv.start1 := start_tog;
dv.start2 := dr.start1;
dv.start3 := dr.start2;
vstart := dr.start2;
vstartd := dr.start3;
vreq := dr.req2;
vreqf := dr.req1;
if nosync/=0 then
vstart:=start_tog;
vstartd:=start_tog;
vreq:=request;
vreqf:=request;
end if;
if nosync > 1 then
vreqf := frequest;
end if;
-- Address muxing
vcsf(0) := genmux(dr.cfg.bsize, vreqf.startaddr(30 downto 23));
vcsf(1) := not vcsf(0);
vbankf := genmux(dr.cfg.bsize, vreqf.startaddr(29 downto 22)) &
genmux(dr.cfg.bsize, vreqf.startaddr(28 downto 21));
case dr.cfg.csize is
when "00" => vrowf := vreqf.startaddr(19+l2ddrw downto 5+l2ddrw);
when "01" => vrowf := vreqf.startaddr(20+l2ddrw downto 6+l2ddrw);
when "10" => vrowf := vreqf.startaddr(21+l2ddrw downto 7+l2ddrw);
when others => vrowf := vreqf.startaddr(22+l2ddrw downto 8+l2ddrw);
end case;
vcol := vreq.startaddr(l2ddrw+10 downto l2ddrw-3);
-- vcoladdr==vcol when dr.ramaddr==lsb of vcol
vcoladdr := vcol(14 downto rbuf_wabits+1) & dr.ramaddr;
-- Generate data mask
-- Mask for 32-bit and larger bursts and single access
vmaskfirst := (others => '0');
vmasklast := (others => '0');
ea := vreq.endaddr(3 downto 2);
if vreq.hsize(1 downto 0)="11" then ea(2):='1'; end if;
if vreq.hsize(2)='1' then ea(3 downto 2):="11"; end if;
case ddrbits is
when 64 =>
-- 64-bit DDR width
case vreq.startaddr(3 downto 2) is
when "11" => vmaskfirst := "1111111111110000";
when "10" => vmaskfirst := "1111111100000000";
when "01" => vmaskfirst := "1111000000000000";
when others => vmaskfirst := "0000000000000000";
end case;
case ea(3 downto 2) is
when "11" => vmasklast := "0000000000000000";
when "10" => vmasklast := "0000000000001111";
when "01" => vmasklast := "0000000011111111";
when others => vmasklast := "0000111111111111";
end case;
if vreq.hsize(2 downto 1)="00" then
if vreq.startaddr(1)='1' then
vmaskfirst := vmaskfirst or "1100110011001100";
else
vmaskfirst := vmaskfirst or "0011001100110011";
end if;
end if;
if vreq.hsize="000" then
if vreq.startaddr(0)='1' then
vmaskfirst := vmaskfirst or "1010101010101010";
else
vmaskfirst := vmaskfirst or "0101010101010101";
end if;
end if;
when 32 =>
-- 32-bit DDR width
case vreq.startaddr(2) is
when '1' => vmaskfirst := "11110000";
when others => vmaskfirst := "00000000";
end case;
case ea(2) is
when '1' => vmasklast := "00000000";
when others => vmasklast := "00001111";
end case;
if vreq.hsize(2 downto 1)="00" then
if vreq.startaddr(1)='1' then
vmaskfirst := vmaskfirst or "11001100";
else
vmaskfirst := vmaskfirst or "00110011";
end if;
end if;
if vreq.hsize="000" then
if vreq.startaddr(0)='1' then
vmaskfirst := vmaskfirst or "10101010";
else
vmaskfirst := vmaskfirst or "01010101";
end if;
end if;
when others =>
-- 16-bit DDR width
if vreq.hsize(2 downto 1)="00" then
if vreq.startaddr(1)='1' then
vmaskfirst := vmaskfirst or "1100";
else
vmaskfirst := vmaskfirst or "0011";
end if;
end if;
if vreq.hsize="000" then
if vreq.startaddr(0)='1' then
vmaskfirst := vmaskfirst or "1010";
else
vmaskfirst := vmaskfirst or "0101";
end if;
end if;
end case;
-- Register read/write data muxing
regrdata := (others => '0');
case ddrbits is
when 64 =>
regad := vreq.startaddr(4 downto 2);
regrdata := regsd1 & regsd2 & regsd3 & x"00000000";
if confapi /= 0 and regad(2)='1' then
regrdata(95 downto 32) := dr.cfg.conf(31 downto 0) & dr.cfg.conf(63 downto 32);
end if;
wrdreg1 := wbrdata(128+chkbits-1 downto 96+chkbits);
wrdreg2 := wbrdata(96+chkbits-1 downto 64+chkbits);
wrdreg3 := wbrdata(63 downto 32);
when 32 =>
regad := dr.ramaddr(1 downto 0) & vreq.startaddr(2);
if regad(1)='0' then
regrdata := regsd1 & regsd2;
if confapi /= 0 and regad(2)='1' then
regrdata := regsd1 & dr.cfg.conf(31 downto 0);
end if;
else
regrdata := regsd3 & regsd2;
if confapi /= 0 and regad(2)='1' then
regrdata := dr.cfg.conf(63 downto 0);
end if;
end if;
wrdreg1 := wbrdata(64+chkbits-1 downto 32+chkbits);
wrdreg2 := wbrdata(31 downto 0);
wrdreg3 := wbrdata(64+chkbits-1 downto 32+chkbits);
when others =>
regad := dr.ramaddr(2 downto 0);
case regad is
when "000"|"100" => regrdata := regsd1;
when "001" => regrdata := regsd2;
when "010" => regrdata := regsd3;
when "101" =>
if confapi /= 0 then
regrdata := dr.cfg.conf(31 downto 0);
else
regrdata := regsd2;
end if;
when "110" =>
if confapi /= 0 then
regrdata := dr.cfg.conf(63 downto 32);
else
regrdata := regsd3;
end if;
when others => regrdata := regsd3;
end case;
wrdreg1 := wbrdata(31+chkbits downto 16+chkbits) & wbrdata(15 downto 0);
wrdreg2 := wbrdata(31+chkbits downto 16+chkbits) & wbrdata(15 downto 0);
wrdreg3 := wbrdata(31+chkbits downto 16+chkbits) & wbrdata(15 downto 0);
end case;
---------------------------------------------------------------------------
-- Main DDR-SDRAM access FSM
---------------------------------------------------------------------------
dv.sdo_ck := "111";
dv.sdo_rasn := '1';
dv.sdo_casn := '1';
dv.sdo_wen := '1';
dv.sdo_dqm := (others => '1');
dv.sdo_bdrive := '1';
dv.sdo_qdrive := '1';
inc_sdoaddr := '0';
inc_ramaddr := '0';
dv.readpipe := dr.readpipe(3+readdly downto 0) & '0';
datavalid := '0';
if hasdqvalid/=0 then
datavalid := sdi.datavalid;
if dr.s/=dsrd1 and dr.s/=dsrd2 and dr.s/=dsrd3 and dr.s/=dsrd4 and dr.s/=dssrr2 then
datavalid := '0';
end if;
end if;
if hasdqvalid=0 then
if dr.cfg.cl='0' then
datavalid := dr.readpipe(3+readdly);
else
datavalid := dr.readpipe(4+readdly);
end if;
end if;
if datavalid='1' and dr.s/=dsidle then
inc_ramaddr := '1';
rbw := '1';
vrctr(l2ddr_burstlen-1 downto 0) :=
nextgray(vrctr(l2ddr_burstlen-1 downto 0));
if dr.ramaddr=onev(dr.ramaddr'length-1 downto 0) then
dv.readdone := '1';
incdone:='1';
vrctr := "0000";
end if;
end if;
if dr.sdo_address((l2blen-l2ddrw) downto 1)=onev((l2blen-l2ddrw) downto 1) then
lastreadcmd := '1';
end if;
if dr.ramaddr=vreq.endaddr((l2blen-3)-1 downto (l2ddrw-3)) then
lastwrite := '1';
end if;
-- Update EMR when ds, tcsr or pasr change
if dr.cfg.command="000" and
( dr.cfg.ds(2 downto 0) /= dr.cfg.ds(5 downto 3) or
dr.cfg.tcsr(1 downto 0) /= dr.cfg.tcsr(3 downto 2) or
dr.cfg.pasr(2 downto 0) /= dr.cfg.pasr(5 downto 3) ) then
dv.cfg.command := "111";
end if;
-- Auto-refresh counter
dv.refctr := std_logic_vector(unsigned(dr.refctr)+1);
if (dr.refctr(11 downto 0)=dr.cfg.refresh and dr.cfg.refon='1') then
dv.refpend := '1';
dv.refctr := (others => '0');
end if;
if dr.initstate/=disrstdel and (dr.cfg.refon='0' or dr.cfg.pmode(1)='1') then
dv.refpend := '0';
dv.refctr := (others => '0');
end if;
dv.idlectr := "0000";
dv.pdowns(0) := '0';
if not (dr.cmdctr=(dr.cmdctr'range => '0')) and dr.pdowns(0)='0' then
dv.cmdctr := std_logic_vector(unsigned(dr.cmdctr)-1);
end if;
case dr.s is
when dsidle =>
vrctr := "0000";
dv.sdo_ck := "111";
if dr.cfg.pmode /= "000" then
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
end if;
dv.sdo_csn := "11";
if dr.refpend='1' then
dv.sdo_csn := "00";
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.s := dsref1;
dv.refpend := '0';
elsif vstart /= vdone and dr.cfg.renable='0' then
-- Transfer
dv.sdo_csn := vcsf;
dv.sdo_address := vrowf;
dv.sdo_ba := vbankf;
dv.sdo_rasn := '0' or vreqf.hio;
dv.s := dsact1;
elsif dr.cfg.command /= "000" then
dv.s := dscmd1;
elsif dr.idlectr="1111" then
dv.s := dspdown1;
end if;
when dsact1 =>
dv.ramaddr := vcol(rbuf_wabits downto 1);
if ddr400 /= 0 then
dv.cmdctr(2 downto 0) := "1" & dr.cfg.tras; -- t(RAS)-2t(CK) = TRAS+6-2 = TRAS+4
else
dv.cmdctr(2 downto 0) := "10" & dr.cfg.trcd;
end if;
dv.readdone := '0';
if dr.cfg.trcd='1' then
dv.s := dsact2;
else
dv.s := dsact3;
end if;
if vreq.hio='1' then
dv.s := dsreg1;
end if;
when dsact2 =>
dv.s := dsact3;
when dsact3 =>
dv.sdo_casn := '0';
dv.sdo_wen := not vreq.hwrite;
dv.sdo_qdrive := not vreq.hwrite;
-- dv.sdo_address := vcol(12 downto 10) & '0' & vcol(9 downto 1) & '0';
-- Since part of column is stored in ramaddr in dsact1, use that to
-- reduce fanout on vreq.startaddr
dv.sdo_address := vcoladdr(13 downto 10) & '0' & vcoladdr(9 downto 1) & '0';
if vreq.hwrite='1' then
dv.s := dswr1;
else
dv.s := dsrd1;
dv.readpipe(0) := '1';
end if;
when dswr1 =>
-- NOP,NOP,[WR]: issue either WR+D or NOP+D
dv.sdo_bdrive := '0';
dv.sdo_qdrive := '0';
inc_sdoaddr := '1';
inc_ramaddr := '1';
if lastwrite='1' then
dv.sdo_dqm := vmaskfirst or vmasklast;
dv.s := dswr3;
else
dv.sdo_casn := '0';
dv.sdo_wen := '0';
dv.sdo_dqm := vmaskfirst;
dv.s := dswr2;
end if;
when dswr2 =>
dv.sdo_dqm := (others => '0');
dv.sdo_bdrive := '0';
dv.sdo_qdrive := '0';
inc_sdoaddr := '1';
inc_ramaddr := '1';
if lastwrite='0' then
dv.sdo_casn := '0';
dv.sdo_wen := '0';
else
dv.s := dswr3;
dv.sdo_dqm := vmasklast;
end if;
when dswr3 =>
-- ...,WR+D,WR+D,[NOP+D]: issue NOP
dv.sdo_qdrive := '0';
dv.sdo_dqm := (others => '1');
dv.s := dswr4;
incdone := '1';
when dswr4 =>
-- Issue more NOP:s to meet tWR
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
if dr.idlectr(0)=dr.cfg.twr then
dv.s := dswr5;
end if;
when dswr5 =>
-- Issue NOP:s until tRAS met.
if dr.cmdctr(2 downto 0)="000" then
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.s := dswr6;
end if;
when dswr6 =>
-- PRE: issue one or two NOP:s depending on trp setting
if dr.idlectr(1 downto 0)=dr.cfg.trp then
dv.s := dsidle;
else
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
end if;
when dsrd1 =>
inc_sdoaddr := '1';
if lastreadcmd='0' then
dv.sdo_casn := '0';
dv.readpipe(0):='1';
elsif dr.cmdctr(2 downto 0)="000" then
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.s := dsrd3;
else
dv.s := dsrd2;
end if;
when dsrd2 =>
if dr.cmdctr(2 downto 0)="000" then
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.s := dsrd3;
end if;
when dsrd3 =>
if dr.idlectr(1 downto 0)=dr.cfg.trp then
if dv.readdone='1' then
dv.s := dsidle;
else
dv.s := dsrd4;
end if;
else
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
end if;
when dsrd4 =>
if dv.readdone='1' then
dv.s := dsidle;
end if;
when dsreg1 =>
rbw := '1';
rbwd(2*ddrbits+chkbits-1 downto ddrbits+chkbits) := regrdata(2*ddrbits-1 downto ddrbits);
rbwd(ddrbits-1 downto 0) := regrdata(ddrbits-1 downto 0);
if vreq.hwrite='1' then
dv.s := dsreg2;
elsif regad="100" and dr.cfg.mobileen='1' then
dv.sdo_address := (others => '0');
dv.sdo_ba := "01";
dv.sdo_csn := "10";
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.sdo_wen := '0';
dv.s := dssrr1;
dv.cmdctr(0) := '1';
null;
else
incdone := '1';
dv.s := dsidle;
end if;
when dsreg2 =>
case regad is
when "000" =>
dv.cfg.refon := wrdreg1(31);
dv.cfg.trp(0) := wrdreg1(30);
dv.cfg.trfc(2 downto 0) := wrdreg1(29 downto 27);
dv.cfg.trcd := wrdreg1(26);
dv.cfg.bsize := wrdreg1(25 downto 23);
dv.cfg.csize := wrdreg1(22 downto 21);
dv.cfg.command := wrdreg1(20 downto 18);
dv.cfg.dllrst := wrdreg1(17);
dv.cfg.renable := wrdreg1(16);
dv.cfg.cke := wrdreg1(15);
dv.cfg.refresh := wrdreg1(11 downto 0);
when "010" =>
dv.cfg.mobileen := wrdreg3(31);
dv.cfg.cl := wrdreg3(30);
dv.cfg.tcke := wrdreg3(24);
dv.cfg.txsr(3 downto 0) := wrdreg3(23 downto 20);
dv.cfg.txp(0) := wrdreg3(19);
dv.cfg.pmode := wrdreg3(18 downto 16);
dv.cfg.ds (5 downto 3) := wrdreg3(7 downto 5);
dv.cfg.tcsr(3 downto 2) := wrdreg3(4 downto 3);
dv.cfg.pasr(5 downto 3) := wrdreg3(2 downto 0);
-- Extended DDR400 fields
dv.cfg.tras := wrdreg3(29 downto 28);
dv.cfg.txsr(5 downto 4) := wrdreg3(27 downto 26);
dv.cfg.txp(1) := wrdreg3(25);
dv.cfg.twr := wrdreg3(11);
dv.cfg.trp(1) := wrdreg3(10);
dv.cfg.trfc(4 downto 3) := wrdreg3(9 downto 8);
when "101" =>
if confapi /= 0 then
dv.cfg.conf(31 downto 0) := wrdreg2;
end if;
when "110" =>
if confapi /= 0 then
dv.cfg.conf(63 downto 32) := wrdreg3;
end if;
when others =>
null;
end case;
incdone := '1';
dv.s := dsidle;
when dscmd1 =>
dv.sdo_csn := (others => '0');
dv.sdo_address(10) := '1';
dv.cfg.command := "000";
dv.s := dscmd2;
case dr.cfg.command is
when "010" => -- PRECHARGE ALL
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.cmdctr(1 downto 0) := "11";
when "100" => -- AUTO-REFRESH
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.cmdctr(4 downto 0) := dr.cfg.trfc;
when "110" => -- MODE REGISTER
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.sdo_wen := '0';
dv.sdo_ba := "00";
dv.sdo_address := "00000000" & "01" & dr.cfg.cl & "0001";
if dr.cfg.mobileen='0' then
dv.sdo_address(8) := dr.cfg.dllrst;
end if;
if dr.cfg.dllrst='1' then
dv.cmdctr := std_logic_vector(to_unsigned(200,dr.cmdctr'length));
end if;
when "111" => -- EXT. MODE REGISTER
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.sdo_wen := '0';
if dr.cfg.mobileen='1' then
dv.sdo_ba := "10";
dv.sdo_address := "0000000" & dr.cfg.ds(5 downto 3) & dr.cfg.tcsr(3 downto 2)
& dr.cfg.pasr(5 downto 3);
else
dv.sdo_ba := "01";
dv.sdo_address := "000000000000000"; -- bit0=0 -> DLL enable
end if;
dv.cfg.pasr(2 downto 0) := dr.cfg.pasr(5 downto 3);
dv.cfg.ds(2 downto 0) := dr.cfg.ds(5 downto 3);
dv.cfg.tcsr(1 downto 0) := dr.cfg.tcsr(3 downto 2);
when others => null;
end case;
when dscmd2 =>
if dr.cmdctr=(dr.cmdctr'range => '0') then
dv.s := dsidle;
end if;
when dspdown1 =>
dv.sdo_csn := "00";
if dr.cfg.pmode(0)='1' or dr.cfg.pmode(1)='1' then
dv.cfg.cke := '0';
end if;
if dr.cfg.pmode(1)='1' then
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
end if;
if dr.cfg.pmode(2)='1' and dr.cfg.pmode(0)='1' then
dv.sdo_wen := '0';
end if;
if dr.cfg.pmode(0)='1' then
dv.cmdctr(1 downto 0) := dr.cfg.txp;
end if;
if dr.cfg.pmode(1)='1' then
if dr.cfg.mobileen='1' then
dv.cmdctr(5 downto 0) := dr.cfg.txsr;
else
dv.cmdctr(7 downto 0) := std_logic_vector(to_unsigned(200,8));
end if;
end if;
dv.pdowns(1) := '0';
dv.s := dspdown2;
when dspdown2 =>
dv.pdowns(0) := '1';
if dr.pdowns(0)='0' and dr.cmdctr=(dr.cmdctr'range => '0') then
dv.pdowns(1):='1';
end if;
if dr.cfg.pmode(2)='1' and dr.cfg.pmode(0)='0' then
dv.sdo_ck := "000";
end if;
if dr.cfg.pmode(1)='1' then
dv.refpend := '1';
end if;
if (dr.refpend='1' and dr.cfg.pmode(1)='0') or vstart /= vdone then
if (dr.pdowns(0) or not dr.cfg.tcke)='1' then
dv.cfg.cke := '1';
if dr.pdowns(1)='1' then
dv.s := dsidle;
else
dv.s := dscmd2;
dv.pdowns(0) := '0';
end if;
end if;
end if;
when dsref1 =>
dv.s := dscmd2;
dv.cmdctr(4 downto 0) := dr.cfg.trfc;
when dssrr1 =>
if dr.cmdctr(0)='0' then
dv.sdo_casn := '0';
dv.readpipe(0):='1';
dv.s := dssrr2;
end if;
when dssrr2 =>
if datavalid='1' then
incdone := '1';
dv.s := dsidle;
end if;
end case;
if inc_sdoaddr='1' then
dv.sdo_address(l2blen-l2ddrw downto 1) :=
std_logic_vector(unsigned(dr.sdo_address(l2blen-l2ddrw downto 1))+1);
end if;
if inc_ramaddr='1' then
dv.ramaddr := std_logic_vector(unsigned(dr.ramaddr)+1);
end if;
-- Update the done flags
dv.resp.done_tog := (dr.resp.done_tog xor incdone) and (not reqsel);
dv.resp.rctr_gray := vrctr and (not reqselv);
dv.resp2.done_tog := (dr.resp2.done_tog xor incdone) and reqsel;
dv.resp2.rctr_gray := vrctr and reqselv;
---------------------------------------------------------------------------
-- DDR Init Sequence FSM
---------------------------------------------------------------------------
-- Command sequence lookup table
seqin := dr.cfg.mobileen & dr.initpos;
case seqin is
-- Mobile DDR
when "1100" => seqout := "0010"; -- PRECHARGE ALL
when "1011" => seqout := "0100"; -- AUTO REFRESH #1
when "1010" => seqout := "0100"; -- AUTO REFRESH #2
when "1001" => seqout := "0110"; -- MODE REG
when "1000" => seqout := "0111"; -- EXT MODE REG
-- Normal DDR
when "0110" => seqout := "0010"; -- PRECHARGE ALL
when "0101" => seqout := "0111"; -- EXT MODE REG En DLL
when "0100" => seqout := "1110"; -- MODE REG Rst DLL
when "0011" => seqout := "0010"; -- PRECHARGE ALL
when "0010" => seqout := "0100"; -- AUTO REFRESH #1
when "0001" => seqout := "0100"; -- AUTO REFRESH #2
when "0000" => seqout := "0110"; -- MODE REG NoRst DLL
when others => seqout := "0000";
end case;
case dr.initstate is
when disrstdel =>
if dr.refctr=std_logic_vector(to_unsigned(MHz*rstdel,dr.refctr'length)) then
dv.initstate := disidle;
if pwron=0 then dv.cfg.renable:='0'; end if;
end if;
-- Bypass reset delay by writing anything to regsd2
if vstartd='1' and (vreq.hio='1' and vreq.hwrite='1' and vreq.endaddr(4 downto 2)="001") then
dv.initstate := disidle;
if pwron=0 then dv.cfg.renable:='0'; end if;
end if;
when disidle =>
if dr.cfg.renable='1' then
dv.cfg.cke := '1';
if dr.cfg.cke='1' then
dv.initpos := "111";
dv.initstate := disrun;
end if;
end if;
when disrun =>
if dr.cfg.command="000" then
dv.cfg.dllrst := seqout(3);
dv.cfg.command := seqout(2 downto 0);
dv.initpos := std_logic_vector(unsigned(dr.initpos)-1);
if dr.initpos="000" then
dv.initstate := disfinished;
end if;
end if;
when disfinished =>
if dr.cfg.command="000" then
dv.cfg.renable := '0';
dv.cfg.refon := '1';
dv.initstate := disidle;
end if;
end case;
---------------------------------------------------------------------------
-- Reset
---------------------------------------------------------------------------
if ddr_rst='0' then
dv.s := dsidle;
dv.cmdctr := (others => '0');
dv.refctr := (others => '0');
dv.resp := ddr_response_none;
dv.resp2 := ddr_response_none;
dv.initstate := disrstdel;
dv.refpend := '0';
-- Reset cfg record
dv.cfg.command := "000";
dv.cfg.csize := conv_std_logic_vector(col-9, 2);
dv.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
dv.cfg.refon := '0';
dv.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
dv.cfg.dllrst := '0';
dv.cfg.pasr := (others => '0');
dv.cfg.tcsr := (others => '0');
dv.cfg.ds := (others => '0');
dv.cfg.pmode := (others => '0');
dv.cfg.txsr := conv_std_logic_vector(120*MHz/1000, 6);
dv.cfg.txp := "01";
dv.cfg.cl := '0'; -- CL = 3/2 -- ****
dv.cfg.tcke := '1';
if MHz > 100 then
dv.cfg.trcd := '1';
else dv.cfg.trcd := '0';
end if;
if MHz > 100 then
dv.cfg.trp := "01";
else dv.cfg.trp := "00";
end if;
dv.cfg.renable := '1'; -- Updated in disrstdel state
if mobile >= 2 then
dv.cfg.mobileen := '1'; -- Default: Mobile DDR
else dv.cfg.mobileen := '0';
end if;
if mobile >= 2 then
dv.cfg.trfc := conv_std_logic_vector(98*MHz/1000-2, 5);
else dv.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 5);
end if;
if ddr_syncrst /= 0 then
dv.sdo_ck := "000";
if mobile >= 2 then
dv.cfg.cke := '1';
else dv.cfg.cke := '0';
end if;
end if;
if confapi /= 0 then
dv.cfg.conf(31 downto 0) := conv_std_logic_vector(conf0, 32); --x"0000A0A0";
dv.cfg.conf(63 downto 32) := conv_std_logic_vector(conf1, 32); --x"00060606";
else
dv.cfg.conf := (others => '0');
end if;
if MHz > 175 then
dv.cfg.tras := "10";
elsif MHz > 150 then
dv.cfg.tras := "01";
else
dv.cfg.tras := "00";
end if;
if MHz > 133 then
dv.cfg.twr := '1';
else
dv.cfg.twr := '0';
end if;
dv.sdo_csn := "11";
dv.sdo_dqm := (others => '1');
dv.sdo_wen := '1';
dv.sdo_rasn := '1';
dv.sdo_casn := '1';
-- Extra reset for X-sensitive techs
dv.ramaddr := (others => '0');
end if;
---------------------------------------------------------------------------
-- Static logic/forced regs, etc
---------------------------------------------------------------------------
-- Force mobile disable/enabled
if mobile=0 then dv.cfg.mobileen := '0'; end if;
if mobile=3 then dv.cfg.mobileen := '1'; end if;
if mobile=0 then
dv.cfg.pasr := (others => '0');
dv.cfg.tcsr := (others => '0');
dv.cfg.ds := (others => '0');
dv.cfg.pmode := (others => '0');
dv.cfg.txp := "00";
dv.cfg.txsr := (others => '0');
dv.cfg.tcke := '0';
end if;
if ddr400=0 then
dv.cfg.tras := "00";
dv.cfg.txsr(5 downto 4) := "00";
dv.cfg.txp(1) := '0';
dv.cfg.trp(1) := '0';
dv.cfg.trfc(4 downto 3) := "00";
dv.cfg.twr := '0';
end if;
-- Assign sdo
o.bdrive := '1'; o.qdrive := '1'; --Temp.
o.sdck := dr.sdo_ck;
if ddr_syncrst/=0 and phyptctrl/=0 then
o.sdck := o.sdck and (o.sdck'range => ddr_rst);
end if;
if regoutput /= 0 then
o.casn := dr.sdo_casn;
o.rasn := dr.sdo_rasn;
o.sdwen := dr.sdo_wen;
o.sdcsn := dr.sdo_csn;
o.ba := '0' & dr.sdo_ba;
o.address := dr.sdo_address;
o.sdcke := (others => dr.cfg.cke);
if ddr_syncrst /= 0 and phyptctrl /= 0 then
if ddr_rst='0' then
if mobile >= 2 then o.sdcke := (others => '1');
else o.sdcke := (others => '0');
end if;
end if;
end if;
o.data(2*ddrbits-1 downto 0) := dr.sdo_data;
o.dqm(ddrbits/4-1 downto 0) := dr.sdo_dqm;
if chkbits > 0 then
o.cb(2*chkbits-1 downto 0) := dr.sdo_cb(2*chkbits-1 downto 0);
end if;
o.bdrive := dr.sdo_bdrive;
o.qdrive := dr.sdo_qdrive;
else
o.casn := dv.sdo_casn;
o.rasn := dv.sdo_rasn;
o.sdwen := dv.sdo_wen;
o.sdcsn := dv.sdo_csn;
o.ba := '0' & dv.sdo_ba;
o.address := dv.sdo_address;
o.sdcke := (others => dv.cfg.cke);
o.data(2*ddrbits-1 downto 0) := dv.sdo_data;
o.dqm(ddrbits/4-1 downto 0) := dv.sdo_dqm;
if chkbits > 0 then
o.cb(2*chkbits-1 downto 0) := dv.sdo_cb(2*chkbits-1 downto 0);
end if;
o.bdrive := dv.sdo_bdrive;
o.qdrive := dv.sdo_qdrive;
end if;
for x in 7 downto 0 loop
o.cbdqm(x) := o.dqm(2*x);
end loop;
-- Diag access
if vreq.maskcb='1' then
o.cbdqm := (others => '1');
end if;
if vreq.maskdata='1' then
o.dqm := (others => '1');
end if;
if scantest/=0 and phyptctrl/=0 then
if testen='1' then
o.bdrive := testoen;
o.qdrive := testoen;
end if;
end if;
---------------------------------------------------------------------------
-- Drive outputs
---------------------------------------------------------------------------
ndr <= dv;
sdo <= o;
response <= dr.resp;
response2 <= dr.resp2;
rbwrite <= rbw;
rbwaddr <= dr.ramaddr;
rbwdata <= rbwd;
wbraddr <= vdone & dv.ramaddr;
end process;
ddrregs: process(clk_ddr,arst)
begin
if rising_edge(clk_ddr) then
dr <= ndr;
end if;
if ddr_syncrst=0 and arst='0' then
dr.sdo_ck <= "000";
if mobile >= 2 then
dr.cfg.cke <= '1';
else dr.cfg.cke <= '0';
end if;
end if;
end process;
end;
|
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_rr_base is
end tb_rr_base;
architecture bhv of tb_rr_base is
----------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------
-- System
constant c_spi_rate : natural := 99E5; -- Should be something weird => Detect more errors
constant c_bit_with_half_t : time := 1E9 ns / (2 * c_spi_rate);
constant c_byte_pad_t : time := 5 * c_bit_with_half_t;
constant SPI_USER_CS_IDX : natural := 1;
-- User
constant c_clk_frequency : natural := 50E6;
constant c_use_issi_sdram : std_ulogic := '1';
constant c_use_sdram_pll : std_ulogic := '1';
constant num_gpios : natural := 6;
-- Derived
----------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------
signal clk : std_ulogic := '1';
signal keys : std_ulogic_vector(1 downto 0);
signal switches : std_ulogic_vector(3 downto 0);
signal leds : std_ulogic_vector(7 downto 0);
signal spi_cs : std_ulogic_vector(1 downto 0) := (others => '1');
signal spi_clk : std_ulogic := '0';
signal spi_mosi : std_ulogic := '0';
signal spi_miso : std_ulogic := '0';
signal spi_epcs_cs : std_ulogic;
signal spi_epcs_clk : std_ulogic;
signal spi_epcs_mosi : std_ulogic;
signal spi_epcs_miso : std_ulogic;
signal arReconf : std_ulogic;
signal gpios : std_logic_vector(0 to num_gpios - 1);
begin
clk <= not clk after 1E9 ns / (2 * c_clk_frequency);
keys <= (others => '1');
switches <= (others => '0');
testbed: entity work.tbd_rr_base(rtl)
generic map
(
use_sdram_pll => c_use_sdram_pll,
num_gpios => num_gpios
)
port map
(
clock_50mhz => clk,
keys => keys,
switches => switches,
leds => leds,
spi_cs => spi_cs,
spi_clk => spi_clk,
spi_mosi => spi_mosi,
spi_miso => spi_miso,
spi_epcs_cs => spi_epcs_cs,
spi_epcs_clk => spi_epcs_clk,
spi_epcs_mosi => spi_epcs_mosi,
spi_epcs_miso => spi_epcs_miso,
arReconf => arReconf,
gpios => gpios
);
----------------------------------------------------------------------------------------------------------------------------
-- Testing process
Stimu : process
procedure spi_select is
begin
wait for c_byte_pad_t;
wait for c_byte_pad_t;
spi_cs(SPI_USER_CS_IDX) <= '0';
wait for c_byte_pad_t;
end procedure;
procedure spi_deselect is
begin
wait for c_byte_pad_t;
spi_cs(SPI_USER_CS_IDX) <= '1';
wait for c_byte_pad_t;
wait for c_byte_pad_t;
end procedure;
procedure spi_send_byte(dat : in std_ulogic_vector(7 downto 0)) is
begin
for i in 7 downto 0 loop
spi_mosi <= dat(i);
wait for c_bit_with_half_t;
spi_clk <= '1';
wait for c_bit_with_half_t;
spi_clk <= '0';
end loop;
spi_mosi <= '0';
wait for c_byte_pad_t;
end procedure;
procedure spi_send_byte_broken(dat : in std_ulogic_vector(7 downto 0)) is
begin
for i in 3 downto 0 loop
spi_mosi <= dat(i);
wait for c_bit_with_half_t;
spi_clk <= '1';
wait for c_bit_with_half_t;
spi_clk <= '0';
end loop;
spi_mosi <= '0';
wait for c_byte_pad_t;
end procedure;
begin
-- ########################################################################################################
-----------------------------------------------------------------------------------------------------------
-- Testing Code
wait for 10 ns;
gpios <= (others => 'H');
wait for 1 us;
spi_select;
gpios(2) <= 'L';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
gpios(2) <= 'H';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
--spi_send_byte(X"C3"); -- Garbage
wait for 1 us;
gpios(2) <= 'H';
spi_send_byte(X"02"); -- OUT
spi_send_byte(X"01");
spi_send_byte(X"00");
--spi_send_byte(X"C3"); -- Garbage
spi_send_byte(X"02"); -- OUT
spi_send_byte(X"01");
spi_send_byte(X"01");
--spi_send_byte(X"C3"); -- Garbage
spi_send_byte(X"02"); -- OUT
spi_send_byte(X"01");
spi_send_byte(X"00");
wait for 1 us;
gpios(2) <= 'L';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
gpios(2) <= 'H';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"01");
--spi_send_byte(X"C3"); -- Garbage
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"02");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"04");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"03");
wait for 1 us;
gpios(2) <= 'H';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
gpios(2) <= 'L';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
gpios(2) <= 'H';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
--spi_send_byte(X"00");
spi_deselect;
spi_select;
gpios(2) <= 'L';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
gpios(2) <= 'H';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
wait for 1 us;
gpios(2) <= 'H';
spi_send_byte(X"02"); -- OUT
spi_send_byte(X"01");
spi_send_byte(X"00");
spi_send_byte(X"02"); -- OUT
spi_send_byte(X"01");
spi_send_byte(X"01");
spi_send_byte(X"02"); -- OUT
spi_send_byte(X"01");
spi_send_byte(X"00");
wait for 1 us;
gpios(2) <= 'L';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
gpios(2) <= 'H';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"01");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"02");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"04");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"03");
wait for 1 us;
gpios(2) <= 'H';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
gpios(2) <= 'L';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_deselect;
-----------------------------------------------------------------------------------------------------------
-- ########################################################################################################
assert false report "SIMULATION ENDED SUCCESSFULLY" severity note;
wait;
end process;
----------------------------------------------------------------------------------------------------------------------------
end bhv;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_64x18.vhd when simulating
-- the core, fifo_64x18. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY fifo_64x18 IS
port (
din: IN std_logic_VECTOR(17 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
almost_empty: OUT std_logic;
almost_full: OUT std_logic;
dout: OUT std_logic_VECTOR(17 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
END fifo_64x18;
ARCHITECTURE fifo_64x18_a OF fifo_64x18 IS
-- synopsys translate_off
component wrapped_fifo_64x18
port (
din: IN std_logic_VECTOR(17 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
almost_empty: OUT std_logic;
almost_full: OUT std_logic;
dout: OUT std_logic_VECTOR(17 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_fifo_64x18 use entity XilinxCoreLib.fifo_generator_v2_3(behavioral)
generic map(
c_wr_response_latency => 1,
c_has_rd_data_count => 0,
c_din_width => 18,
c_has_wr_data_count => 0,
c_implementation_type => 2,
c_family => "virtex2p",
c_has_wr_rst => 0,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 0,
c_dout_width => 18,
c_rd_depth => 64,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 1,
c_has_rst => 1,
c_data_count_width => 2,
c_has_wr_ack => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 6,
c_has_almost_empty => 1,
c_rd_data_count_width => 2,
c_enable_rlocs => 0,
c_wr_pntr_width => 6,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 2,
c_preload_regs => 1,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 62,
c_wr_depth => 64,
c_prog_empty_thresh_negate_val => 62,
c_prog_empty_thresh_assert_val => 62,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 62,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => 512,
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 2);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_fifo_64x18
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
almost_empty => almost_empty,
almost_full => almost_full,
dout => dout,
empty => empty,
full => full);
-- synopsys translate_on
END fifo_64x18_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_64x18.vhd when simulating
-- the core, fifo_64x18. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY fifo_64x18 IS
port (
din: IN std_logic_VECTOR(17 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
almost_empty: OUT std_logic;
almost_full: OUT std_logic;
dout: OUT std_logic_VECTOR(17 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
END fifo_64x18;
ARCHITECTURE fifo_64x18_a OF fifo_64x18 IS
-- synopsys translate_off
component wrapped_fifo_64x18
port (
din: IN std_logic_VECTOR(17 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
almost_empty: OUT std_logic;
almost_full: OUT std_logic;
dout: OUT std_logic_VECTOR(17 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_fifo_64x18 use entity XilinxCoreLib.fifo_generator_v2_3(behavioral)
generic map(
c_wr_response_latency => 1,
c_has_rd_data_count => 0,
c_din_width => 18,
c_has_wr_data_count => 0,
c_implementation_type => 2,
c_family => "virtex2p",
c_has_wr_rst => 0,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 0,
c_dout_width => 18,
c_rd_depth => 64,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 1,
c_has_rst => 1,
c_data_count_width => 2,
c_has_wr_ack => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 6,
c_has_almost_empty => 1,
c_rd_data_count_width => 2,
c_enable_rlocs => 0,
c_wr_pntr_width => 6,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 2,
c_preload_regs => 1,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 62,
c_wr_depth => 64,
c_prog_empty_thresh_negate_val => 62,
c_prog_empty_thresh_assert_val => 62,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 62,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => 512,
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 2);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_fifo_64x18
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
almost_empty => almost_empty,
almost_full => almost_full,
dout => dout,
empty => empty,
full => full);
-- synopsys translate_on
END fifo_64x18_a;
|
--************************************************************************************************
-- 8Kx16(8 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok
-- Modified by Jack Gassett for use with Papilio
-- Modified 11.06.2009
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
use WORK.prog_mem_init_pkg.all; -- Init file for program memory.
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM8Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(CPROGMEMSIZE downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
we : in std_logic
);
end XPM8Kx16;
architecture RTL of XPM8Kx16 is
type RAMBlDOut_Type is array(2**(address'length-10)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-10)-1 downto 0);
signal gnd : std_logic;
signal DIP : STD_LOGIC_VECTOR(1 downto 0) := "11";
signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 10)=i) else '0';
end generate ;
--RAM_Inst:for i in 0 to 2**(address'length-10)-1 generate
RAM_Word0:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word0_INIT_00,
INIT_01 => PM_Inst_RAM_Word0_INIT_01,
INIT_02 => PM_Inst_RAM_Word0_INIT_02,
INIT_03 => PM_Inst_RAM_Word0_INIT_03,
INIT_04 => PM_Inst_RAM_Word0_INIT_04,
INIT_05 => PM_Inst_RAM_Word0_INIT_05,
INIT_06 => PM_Inst_RAM_Word0_INIT_06,
INIT_07 => PM_Inst_RAM_Word0_INIT_07,
INIT_08 => PM_Inst_RAM_Word0_INIT_08,
INIT_09 => PM_Inst_RAM_Word0_INIT_09,
INIT_0A => PM_Inst_RAM_Word0_INIT_0A,
INIT_0B => PM_Inst_RAM_Word0_INIT_0B,
INIT_0C => PM_Inst_RAM_Word0_INIT_0C,
INIT_0D => PM_Inst_RAM_Word0_INIT_0D,
INIT_0E => PM_Inst_RAM_Word0_INIT_0E,
INIT_0F => PM_Inst_RAM_Word0_INIT_0F,
INIT_10 => PM_Inst_RAM_Word0_INIT_10,
INIT_11 => PM_Inst_RAM_Word0_INIT_11,
INIT_12 => PM_Inst_RAM_Word0_INIT_12,
INIT_13 => PM_Inst_RAM_Word0_INIT_13,
INIT_14 => PM_Inst_RAM_Word0_INIT_14,
INIT_15 => PM_Inst_RAM_Word0_INIT_15,
INIT_16 => PM_Inst_RAM_Word0_INIT_16,
INIT_17 => PM_Inst_RAM_Word0_INIT_17,
INIT_18 => PM_Inst_RAM_Word0_INIT_18,
INIT_19 => PM_Inst_RAM_Word0_INIT_19,
INIT_1A => PM_Inst_RAM_Word0_INIT_1A,
INIT_1B => PM_Inst_RAM_Word0_INIT_1B,
INIT_1C => PM_Inst_RAM_Word0_INIT_1C,
INIT_1D => PM_Inst_RAM_Word0_INIT_1D,
INIT_1E => PM_Inst_RAM_Word0_INIT_1E,
INIT_1F => PM_Inst_RAM_Word0_INIT_1F,
INIT_20 => PM_Inst_RAM_Word0_INIT_20,
INIT_21 => PM_Inst_RAM_Word0_INIT_21,
INIT_22 => PM_Inst_RAM_Word0_INIT_22,
INIT_23 => PM_Inst_RAM_Word0_INIT_23,
INIT_24 => PM_Inst_RAM_Word0_INIT_24,
INIT_25 => PM_Inst_RAM_Word0_INIT_25,
INIT_26 => PM_Inst_RAM_Word0_INIT_26,
INIT_27 => PM_Inst_RAM_Word0_INIT_27,
INIT_28 => PM_Inst_RAM_Word0_INIT_28,
INIT_29 => PM_Inst_RAM_Word0_INIT_29,
INIT_2A => PM_Inst_RAM_Word0_INIT_2A,
INIT_2B => PM_Inst_RAM_Word0_INIT_2B,
INIT_2C => PM_Inst_RAM_Word0_INIT_2C,
INIT_2D => PM_Inst_RAM_Word0_INIT_2D,
INIT_2E => PM_Inst_RAM_Word0_INIT_2E,
INIT_2F => PM_Inst_RAM_Word0_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word0_INIT_30,
INIT_31 => PM_Inst_RAM_Word0_INIT_31,
INIT_32 => PM_Inst_RAM_Word0_INIT_32,
INIT_33 => PM_Inst_RAM_Word0_INIT_33,
INIT_34 => PM_Inst_RAM_Word0_INIT_34,
INIT_35 => PM_Inst_RAM_Word0_INIT_35,
INIT_36 => PM_Inst_RAM_Word0_INIT_36,
INIT_37 => PM_Inst_RAM_Word0_INIT_37,
INIT_38 => PM_Inst_RAM_Word0_INIT_38,
INIT_39 => PM_Inst_RAM_Word0_INIT_39,
INIT_3A => PM_Inst_RAM_Word0_INIT_3A,
INIT_3B => PM_Inst_RAM_Word0_INIT_3B,
INIT_3C => PM_Inst_RAM_Word0_INIT_3C,
INIT_3D => PM_Inst_RAM_Word0_INIT_3D,
INIT_3E => PM_Inst_RAM_Word0_INIT_3E,
INIT_3F => PM_Inst_RAM_Word0_INIT_3F
)
port map(
DO => RAMBlDOut(0)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(0)
);
RAM_Word1:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word1_INIT_00,
INIT_01 => PM_Inst_RAM_Word1_INIT_01,
INIT_02 => PM_Inst_RAM_Word1_INIT_02,
INIT_03 => PM_Inst_RAM_Word1_INIT_03,
INIT_04 => PM_Inst_RAM_Word1_INIT_04,
INIT_05 => PM_Inst_RAM_Word1_INIT_05,
INIT_06 => PM_Inst_RAM_Word1_INIT_06,
INIT_07 => PM_Inst_RAM_Word1_INIT_07,
INIT_08 => PM_Inst_RAM_Word1_INIT_08,
INIT_09 => PM_Inst_RAM_Word1_INIT_09,
INIT_0A => PM_Inst_RAM_Word1_INIT_0A,
INIT_0B => PM_Inst_RAM_Word1_INIT_0B,
INIT_0C => PM_Inst_RAM_Word1_INIT_0C,
INIT_0D => PM_Inst_RAM_Word1_INIT_0D,
INIT_0E => PM_Inst_RAM_Word1_INIT_0E,
INIT_0F => PM_Inst_RAM_Word1_INIT_0F,
INIT_10 => PM_Inst_RAM_Word1_INIT_10,
INIT_11 => PM_Inst_RAM_Word1_INIT_11,
INIT_12 => PM_Inst_RAM_Word1_INIT_12,
INIT_13 => PM_Inst_RAM_Word1_INIT_13,
INIT_14 => PM_Inst_RAM_Word1_INIT_14,
INIT_15 => PM_Inst_RAM_Word1_INIT_15,
INIT_16 => PM_Inst_RAM_Word1_INIT_16,
INIT_17 => PM_Inst_RAM_Word1_INIT_17,
INIT_18 => PM_Inst_RAM_Word1_INIT_18,
INIT_19 => PM_Inst_RAM_Word1_INIT_19,
INIT_1A => PM_Inst_RAM_Word1_INIT_1A,
INIT_1B => PM_Inst_RAM_Word1_INIT_1B,
INIT_1C => PM_Inst_RAM_Word1_INIT_1C,
INIT_1D => PM_Inst_RAM_Word1_INIT_1D,
INIT_1E => PM_Inst_RAM_Word1_INIT_1E,
INIT_1F => PM_Inst_RAM_Word1_INIT_1F,
INIT_20 => PM_Inst_RAM_Word1_INIT_20,
INIT_21 => PM_Inst_RAM_Word1_INIT_21,
INIT_22 => PM_Inst_RAM_Word1_INIT_22,
INIT_23 => PM_Inst_RAM_Word1_INIT_23,
INIT_24 => PM_Inst_RAM_Word1_INIT_24,
INIT_25 => PM_Inst_RAM_Word1_INIT_25,
INIT_26 => PM_Inst_RAM_Word1_INIT_26,
INIT_27 => PM_Inst_RAM_Word1_INIT_27,
INIT_28 => PM_Inst_RAM_Word1_INIT_28,
INIT_29 => PM_Inst_RAM_Word1_INIT_29,
INIT_2A => PM_Inst_RAM_Word1_INIT_2A,
INIT_2B => PM_Inst_RAM_Word1_INIT_2B,
INIT_2C => PM_Inst_RAM_Word1_INIT_2C,
INIT_2D => PM_Inst_RAM_Word1_INIT_2D,
INIT_2E => PM_Inst_RAM_Word1_INIT_2E,
INIT_2F => PM_Inst_RAM_Word1_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word1_INIT_30,
INIT_31 => PM_Inst_RAM_Word1_INIT_31,
INIT_32 => PM_Inst_RAM_Word1_INIT_32,
INIT_33 => PM_Inst_RAM_Word1_INIT_33,
INIT_34 => PM_Inst_RAM_Word1_INIT_34,
INIT_35 => PM_Inst_RAM_Word1_INIT_35,
INIT_36 => PM_Inst_RAM_Word1_INIT_36,
INIT_37 => PM_Inst_RAM_Word1_INIT_37,
INIT_38 => PM_Inst_RAM_Word1_INIT_38,
INIT_39 => PM_Inst_RAM_Word1_INIT_39,
INIT_3A => PM_Inst_RAM_Word1_INIT_3A,
INIT_3B => PM_Inst_RAM_Word1_INIT_3B,
INIT_3C => PM_Inst_RAM_Word1_INIT_3C,
INIT_3D => PM_Inst_RAM_Word1_INIT_3D,
INIT_3E => PM_Inst_RAM_Word1_INIT_3E,
INIT_3F => PM_Inst_RAM_Word1_INIT_3F
)
port map(
DO => RAMBlDOut(1)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(1)
);
RAM_Word2:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word2_INIT_00,
INIT_01 => PM_Inst_RAM_Word2_INIT_01,
INIT_02 => PM_Inst_RAM_Word2_INIT_02,
INIT_03 => PM_Inst_RAM_Word2_INIT_03,
INIT_04 => PM_Inst_RAM_Word2_INIT_04,
INIT_05 => PM_Inst_RAM_Word2_INIT_05,
INIT_06 => PM_Inst_RAM_Word2_INIT_06,
INIT_07 => PM_Inst_RAM_Word2_INIT_07,
INIT_08 => PM_Inst_RAM_Word2_INIT_08,
INIT_09 => PM_Inst_RAM_Word2_INIT_09,
INIT_0A => PM_Inst_RAM_Word2_INIT_0A,
INIT_0B => PM_Inst_RAM_Word2_INIT_0B,
INIT_0C => PM_Inst_RAM_Word2_INIT_0C,
INIT_0D => PM_Inst_RAM_Word2_INIT_0D,
INIT_0E => PM_Inst_RAM_Word2_INIT_0E,
INIT_0F => PM_Inst_RAM_Word2_INIT_0F,
INIT_10 => PM_Inst_RAM_Word2_INIT_10,
INIT_11 => PM_Inst_RAM_Word2_INIT_11,
INIT_12 => PM_Inst_RAM_Word2_INIT_12,
INIT_13 => PM_Inst_RAM_Word2_INIT_13,
INIT_14 => PM_Inst_RAM_Word2_INIT_14,
INIT_15 => PM_Inst_RAM_Word2_INIT_15,
INIT_16 => PM_Inst_RAM_Word2_INIT_16,
INIT_17 => PM_Inst_RAM_Word2_INIT_17,
INIT_18 => PM_Inst_RAM_Word2_INIT_18,
INIT_19 => PM_Inst_RAM_Word2_INIT_19,
INIT_1A => PM_Inst_RAM_Word2_INIT_1A,
INIT_1B => PM_Inst_RAM_Word2_INIT_1B,
INIT_1C => PM_Inst_RAM_Word2_INIT_1C,
INIT_1D => PM_Inst_RAM_Word2_INIT_1D,
INIT_1E => PM_Inst_RAM_Word2_INIT_1E,
INIT_1F => PM_Inst_RAM_Word2_INIT_1F,
INIT_20 => PM_Inst_RAM_Word2_INIT_20,
INIT_21 => PM_Inst_RAM_Word2_INIT_21,
INIT_22 => PM_Inst_RAM_Word2_INIT_22,
INIT_23 => PM_Inst_RAM_Word2_INIT_23,
INIT_24 => PM_Inst_RAM_Word2_INIT_24,
INIT_25 => PM_Inst_RAM_Word2_INIT_25,
INIT_26 => PM_Inst_RAM_Word2_INIT_26,
INIT_27 => PM_Inst_RAM_Word2_INIT_27,
INIT_28 => PM_Inst_RAM_Word2_INIT_28,
INIT_29 => PM_Inst_RAM_Word2_INIT_29,
INIT_2A => PM_Inst_RAM_Word2_INIT_2A,
INIT_2B => PM_Inst_RAM_Word2_INIT_2B,
INIT_2C => PM_Inst_RAM_Word2_INIT_2C,
INIT_2D => PM_Inst_RAM_Word2_INIT_2D,
INIT_2E => PM_Inst_RAM_Word2_INIT_2E,
INIT_2F => PM_Inst_RAM_Word2_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word2_INIT_30,
INIT_31 => PM_Inst_RAM_Word2_INIT_31,
INIT_32 => PM_Inst_RAM_Word2_INIT_32,
INIT_33 => PM_Inst_RAM_Word2_INIT_33,
INIT_34 => PM_Inst_RAM_Word2_INIT_34,
INIT_35 => PM_Inst_RAM_Word2_INIT_35,
INIT_36 => PM_Inst_RAM_Word2_INIT_36,
INIT_37 => PM_Inst_RAM_Word2_INIT_37,
INIT_38 => PM_Inst_RAM_Word2_INIT_38,
INIT_39 => PM_Inst_RAM_Word2_INIT_39,
INIT_3A => PM_Inst_RAM_Word2_INIT_3A,
INIT_3B => PM_Inst_RAM_Word2_INIT_3B,
INIT_3C => PM_Inst_RAM_Word2_INIT_3C,
INIT_3D => PM_Inst_RAM_Word2_INIT_3D,
INIT_3E => PM_Inst_RAM_Word2_INIT_3E,
INIT_3F => PM_Inst_RAM_Word2_INIT_3F
)
port map(
DO => RAMBlDOut(2)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(2)
);
RAM_Word3:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word3_INIT_00,
INIT_01 => PM_Inst_RAM_Word3_INIT_01,
INIT_02 => PM_Inst_RAM_Word3_INIT_02,
INIT_03 => PM_Inst_RAM_Word3_INIT_03,
INIT_04 => PM_Inst_RAM_Word3_INIT_04,
INIT_05 => PM_Inst_RAM_Word3_INIT_05,
INIT_06 => PM_Inst_RAM_Word3_INIT_06,
INIT_07 => PM_Inst_RAM_Word3_INIT_07,
INIT_08 => PM_Inst_RAM_Word3_INIT_08,
INIT_09 => PM_Inst_RAM_Word3_INIT_09,
INIT_0A => PM_Inst_RAM_Word3_INIT_0A,
INIT_0B => PM_Inst_RAM_Word3_INIT_0B,
INIT_0C => PM_Inst_RAM_Word3_INIT_0C,
INIT_0D => PM_Inst_RAM_Word3_INIT_0D,
INIT_0E => PM_Inst_RAM_Word3_INIT_0E,
INIT_0F => PM_Inst_RAM_Word3_INIT_0F,
INIT_10 => PM_Inst_RAM_Word3_INIT_10,
INIT_11 => PM_Inst_RAM_Word3_INIT_11,
INIT_12 => PM_Inst_RAM_Word3_INIT_12,
INIT_13 => PM_Inst_RAM_Word3_INIT_13,
INIT_14 => PM_Inst_RAM_Word3_INIT_14,
INIT_15 => PM_Inst_RAM_Word3_INIT_15,
INIT_16 => PM_Inst_RAM_Word3_INIT_16,
INIT_17 => PM_Inst_RAM_Word3_INIT_17,
INIT_18 => PM_Inst_RAM_Word3_INIT_18,
INIT_19 => PM_Inst_RAM_Word3_INIT_19,
INIT_1A => PM_Inst_RAM_Word3_INIT_1A,
INIT_1B => PM_Inst_RAM_Word3_INIT_1B,
INIT_1C => PM_Inst_RAM_Word3_INIT_1C,
INIT_1D => PM_Inst_RAM_Word3_INIT_1D,
INIT_1E => PM_Inst_RAM_Word3_INIT_1E,
INIT_1F => PM_Inst_RAM_Word3_INIT_1F,
INIT_20 => PM_Inst_RAM_Word3_INIT_20,
INIT_21 => PM_Inst_RAM_Word3_INIT_21,
INIT_22 => PM_Inst_RAM_Word3_INIT_22,
INIT_23 => PM_Inst_RAM_Word3_INIT_23,
INIT_24 => PM_Inst_RAM_Word3_INIT_24,
INIT_25 => PM_Inst_RAM_Word3_INIT_25,
INIT_26 => PM_Inst_RAM_Word3_INIT_26,
INIT_27 => PM_Inst_RAM_Word3_INIT_27,
INIT_28 => PM_Inst_RAM_Word3_INIT_28,
INIT_29 => PM_Inst_RAM_Word3_INIT_29,
INIT_2A => PM_Inst_RAM_Word3_INIT_2A,
INIT_2B => PM_Inst_RAM_Word3_INIT_2B,
INIT_2C => PM_Inst_RAM_Word3_INIT_2C,
INIT_2D => PM_Inst_RAM_Word3_INIT_2D,
INIT_2E => PM_Inst_RAM_Word3_INIT_2E,
INIT_2F => PM_Inst_RAM_Word3_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word3_INIT_30,
INIT_31 => PM_Inst_RAM_Word3_INIT_31,
INIT_32 => PM_Inst_RAM_Word3_INIT_32,
INIT_33 => PM_Inst_RAM_Word3_INIT_33,
INIT_34 => PM_Inst_RAM_Word3_INIT_34,
INIT_35 => PM_Inst_RAM_Word3_INIT_35,
INIT_36 => PM_Inst_RAM_Word3_INIT_36,
INIT_37 => PM_Inst_RAM_Word3_INIT_37,
INIT_38 => PM_Inst_RAM_Word3_INIT_38,
INIT_39 => PM_Inst_RAM_Word3_INIT_39,
INIT_3A => PM_Inst_RAM_Word3_INIT_3A,
INIT_3B => PM_Inst_RAM_Word3_INIT_3B,
INIT_3C => PM_Inst_RAM_Word3_INIT_3C,
INIT_3D => PM_Inst_RAM_Word3_INIT_3D,
INIT_3E => PM_Inst_RAM_Word3_INIT_3E,
INIT_3F => PM_Inst_RAM_Word3_INIT_3F
)
port map(
DO => RAMBlDOut(3)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(3)
);
RAM_Word4:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word4_INIT_00,
INIT_01 => PM_Inst_RAM_Word4_INIT_01,
INIT_02 => PM_Inst_RAM_Word4_INIT_02,
INIT_03 => PM_Inst_RAM_Word4_INIT_03,
INIT_04 => PM_Inst_RAM_Word4_INIT_04,
INIT_05 => PM_Inst_RAM_Word4_INIT_05,
INIT_06 => PM_Inst_RAM_Word4_INIT_06,
INIT_07 => PM_Inst_RAM_Word4_INIT_07,
INIT_08 => PM_Inst_RAM_Word4_INIT_08,
INIT_09 => PM_Inst_RAM_Word4_INIT_09,
INIT_0A => PM_Inst_RAM_Word4_INIT_0A,
INIT_0B => PM_Inst_RAM_Word4_INIT_0B,
INIT_0C => PM_Inst_RAM_Word4_INIT_0C,
INIT_0D => PM_Inst_RAM_Word4_INIT_0D,
INIT_0E => PM_Inst_RAM_Word4_INIT_0E,
INIT_0F => PM_Inst_RAM_Word4_INIT_0F,
INIT_10 => PM_Inst_RAM_Word4_INIT_10,
INIT_11 => PM_Inst_RAM_Word4_INIT_11,
INIT_12 => PM_Inst_RAM_Word4_INIT_12,
INIT_13 => PM_Inst_RAM_Word4_INIT_13,
INIT_14 => PM_Inst_RAM_Word4_INIT_14,
INIT_15 => PM_Inst_RAM_Word4_INIT_15,
INIT_16 => PM_Inst_RAM_Word4_INIT_16,
INIT_17 => PM_Inst_RAM_Word4_INIT_17,
INIT_18 => PM_Inst_RAM_Word4_INIT_18,
INIT_19 => PM_Inst_RAM_Word4_INIT_19,
INIT_1A => PM_Inst_RAM_Word4_INIT_1A,
INIT_1B => PM_Inst_RAM_Word4_INIT_1B,
INIT_1C => PM_Inst_RAM_Word4_INIT_1C,
INIT_1D => PM_Inst_RAM_Word4_INIT_1D,
INIT_1E => PM_Inst_RAM_Word4_INIT_1E,
INIT_1F => PM_Inst_RAM_Word4_INIT_1F,
INIT_20 => PM_Inst_RAM_Word4_INIT_20,
INIT_21 => PM_Inst_RAM_Word4_INIT_21,
INIT_22 => PM_Inst_RAM_Word4_INIT_22,
INIT_23 => PM_Inst_RAM_Word4_INIT_23,
INIT_24 => PM_Inst_RAM_Word4_INIT_24,
INIT_25 => PM_Inst_RAM_Word4_INIT_25,
INIT_26 => PM_Inst_RAM_Word4_INIT_26,
INIT_27 => PM_Inst_RAM_Word4_INIT_27,
INIT_28 => PM_Inst_RAM_Word4_INIT_28,
INIT_29 => PM_Inst_RAM_Word4_INIT_29,
INIT_2A => PM_Inst_RAM_Word4_INIT_2A,
INIT_2B => PM_Inst_RAM_Word4_INIT_2B,
INIT_2C => PM_Inst_RAM_Word4_INIT_2C,
INIT_2D => PM_Inst_RAM_Word4_INIT_2D,
INIT_2E => PM_Inst_RAM_Word4_INIT_2E,
INIT_2F => PM_Inst_RAM_Word4_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word4_INIT_30,
INIT_31 => PM_Inst_RAM_Word4_INIT_31,
INIT_32 => PM_Inst_RAM_Word4_INIT_32,
INIT_33 => PM_Inst_RAM_Word4_INIT_33,
INIT_34 => PM_Inst_RAM_Word4_INIT_34,
INIT_35 => PM_Inst_RAM_Word4_INIT_35,
INIT_36 => PM_Inst_RAM_Word4_INIT_36,
INIT_37 => PM_Inst_RAM_Word4_INIT_37,
INIT_38 => PM_Inst_RAM_Word4_INIT_38,
INIT_39 => PM_Inst_RAM_Word4_INIT_39,
INIT_3A => PM_Inst_RAM_Word4_INIT_3A,
INIT_3B => PM_Inst_RAM_Word4_INIT_3B,
INIT_3C => PM_Inst_RAM_Word4_INIT_3C,
INIT_3D => PM_Inst_RAM_Word4_INIT_3D,
INIT_3E => PM_Inst_RAM_Word4_INIT_3E,
INIT_3F => PM_Inst_RAM_Word4_INIT_3F
)
port map(
DO => RAMBlDOut(4)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(4)
);
RAM_Word5:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word5_INIT_00,
INIT_01 => PM_Inst_RAM_Word5_INIT_01,
INIT_02 => PM_Inst_RAM_Word5_INIT_02,
INIT_03 => PM_Inst_RAM_Word5_INIT_03,
INIT_04 => PM_Inst_RAM_Word5_INIT_04,
INIT_05 => PM_Inst_RAM_Word5_INIT_05,
INIT_06 => PM_Inst_RAM_Word5_INIT_06,
INIT_07 => PM_Inst_RAM_Word5_INIT_07,
INIT_08 => PM_Inst_RAM_Word5_INIT_08,
INIT_09 => PM_Inst_RAM_Word5_INIT_09,
INIT_0A => PM_Inst_RAM_Word5_INIT_0A,
INIT_0B => PM_Inst_RAM_Word5_INIT_0B,
INIT_0C => PM_Inst_RAM_Word5_INIT_0C,
INIT_0D => PM_Inst_RAM_Word5_INIT_0D,
INIT_0E => PM_Inst_RAM_Word5_INIT_0E,
INIT_0F => PM_Inst_RAM_Word5_INIT_0F,
INIT_10 => PM_Inst_RAM_Word5_INIT_10,
INIT_11 => PM_Inst_RAM_Word5_INIT_11,
INIT_12 => PM_Inst_RAM_Word5_INIT_12,
INIT_13 => PM_Inst_RAM_Word5_INIT_13,
INIT_14 => PM_Inst_RAM_Word5_INIT_14,
INIT_15 => PM_Inst_RAM_Word5_INIT_15,
INIT_16 => PM_Inst_RAM_Word5_INIT_16,
INIT_17 => PM_Inst_RAM_Word5_INIT_17,
INIT_18 => PM_Inst_RAM_Word5_INIT_18,
INIT_19 => PM_Inst_RAM_Word5_INIT_19,
INIT_1A => PM_Inst_RAM_Word5_INIT_1A,
INIT_1B => PM_Inst_RAM_Word5_INIT_1B,
INIT_1C => PM_Inst_RAM_Word5_INIT_1C,
INIT_1D => PM_Inst_RAM_Word5_INIT_1D,
INIT_1E => PM_Inst_RAM_Word5_INIT_1E,
INIT_1F => PM_Inst_RAM_Word5_INIT_1F,
INIT_20 => PM_Inst_RAM_Word5_INIT_20,
INIT_21 => PM_Inst_RAM_Word5_INIT_21,
INIT_22 => PM_Inst_RAM_Word5_INIT_22,
INIT_23 => PM_Inst_RAM_Word5_INIT_23,
INIT_24 => PM_Inst_RAM_Word5_INIT_24,
INIT_25 => PM_Inst_RAM_Word5_INIT_25,
INIT_26 => PM_Inst_RAM_Word5_INIT_26,
INIT_27 => PM_Inst_RAM_Word5_INIT_27,
INIT_28 => PM_Inst_RAM_Word5_INIT_28,
INIT_29 => PM_Inst_RAM_Word5_INIT_29,
INIT_2A => PM_Inst_RAM_Word5_INIT_2A,
INIT_2B => PM_Inst_RAM_Word5_INIT_2B,
INIT_2C => PM_Inst_RAM_Word5_INIT_2C,
INIT_2D => PM_Inst_RAM_Word5_INIT_2D,
INIT_2E => PM_Inst_RAM_Word5_INIT_2E,
INIT_2F => PM_Inst_RAM_Word5_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word5_INIT_30,
INIT_31 => PM_Inst_RAM_Word5_INIT_31,
INIT_32 => PM_Inst_RAM_Word5_INIT_32,
INIT_33 => PM_Inst_RAM_Word5_INIT_33,
INIT_34 => PM_Inst_RAM_Word5_INIT_34,
INIT_35 => PM_Inst_RAM_Word5_INIT_35,
INIT_36 => PM_Inst_RAM_Word5_INIT_36,
INIT_37 => PM_Inst_RAM_Word5_INIT_37,
INIT_38 => PM_Inst_RAM_Word5_INIT_38,
INIT_39 => PM_Inst_RAM_Word5_INIT_39,
INIT_3A => PM_Inst_RAM_Word5_INIT_3A,
INIT_3B => PM_Inst_RAM_Word5_INIT_3B,
INIT_3C => PM_Inst_RAM_Word5_INIT_3C,
INIT_3D => PM_Inst_RAM_Word5_INIT_3D,
INIT_3E => PM_Inst_RAM_Word5_INIT_3E,
INIT_3F => PM_Inst_RAM_Word5_INIT_3F
)
port map(
DO => RAMBlDOut(5)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(5)
);
RAM_Word6:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word6_INIT_00,
INIT_01 => PM_Inst_RAM_Word6_INIT_01,
INIT_02 => PM_Inst_RAM_Word6_INIT_02,
INIT_03 => PM_Inst_RAM_Word6_INIT_03,
INIT_04 => PM_Inst_RAM_Word6_INIT_04,
INIT_05 => PM_Inst_RAM_Word6_INIT_05,
INIT_06 => PM_Inst_RAM_Word6_INIT_06,
INIT_07 => PM_Inst_RAM_Word6_INIT_07,
INIT_08 => PM_Inst_RAM_Word6_INIT_08,
INIT_09 => PM_Inst_RAM_Word6_INIT_09,
INIT_0A => PM_Inst_RAM_Word6_INIT_0A,
INIT_0B => PM_Inst_RAM_Word6_INIT_0B,
INIT_0C => PM_Inst_RAM_Word6_INIT_0C,
INIT_0D => PM_Inst_RAM_Word6_INIT_0D,
INIT_0E => PM_Inst_RAM_Word6_INIT_0E,
INIT_0F => PM_Inst_RAM_Word6_INIT_0F,
INIT_10 => PM_Inst_RAM_Word6_INIT_10,
INIT_11 => PM_Inst_RAM_Word6_INIT_11,
INIT_12 => PM_Inst_RAM_Word6_INIT_12,
INIT_13 => PM_Inst_RAM_Word6_INIT_13,
INIT_14 => PM_Inst_RAM_Word6_INIT_14,
INIT_15 => PM_Inst_RAM_Word6_INIT_15,
INIT_16 => PM_Inst_RAM_Word6_INIT_16,
INIT_17 => PM_Inst_RAM_Word6_INIT_17,
INIT_18 => PM_Inst_RAM_Word6_INIT_18,
INIT_19 => PM_Inst_RAM_Word6_INIT_19,
INIT_1A => PM_Inst_RAM_Word6_INIT_1A,
INIT_1B => PM_Inst_RAM_Word6_INIT_1B,
INIT_1C => PM_Inst_RAM_Word6_INIT_1C,
INIT_1D => PM_Inst_RAM_Word6_INIT_1D,
INIT_1E => PM_Inst_RAM_Word6_INIT_1E,
INIT_1F => PM_Inst_RAM_Word6_INIT_1F,
INIT_20 => PM_Inst_RAM_Word6_INIT_20,
INIT_21 => PM_Inst_RAM_Word6_INIT_21,
INIT_22 => PM_Inst_RAM_Word6_INIT_22,
INIT_23 => PM_Inst_RAM_Word6_INIT_23,
INIT_24 => PM_Inst_RAM_Word6_INIT_24,
INIT_25 => PM_Inst_RAM_Word6_INIT_25,
INIT_26 => PM_Inst_RAM_Word6_INIT_26,
INIT_27 => PM_Inst_RAM_Word6_INIT_27,
INIT_28 => PM_Inst_RAM_Word6_INIT_28,
INIT_29 => PM_Inst_RAM_Word6_INIT_29,
INIT_2A => PM_Inst_RAM_Word6_INIT_2A,
INIT_2B => PM_Inst_RAM_Word6_INIT_2B,
INIT_2C => PM_Inst_RAM_Word6_INIT_2C,
INIT_2D => PM_Inst_RAM_Word6_INIT_2D,
INIT_2E => PM_Inst_RAM_Word6_INIT_2E,
INIT_2F => PM_Inst_RAM_Word6_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word6_INIT_30,
INIT_31 => PM_Inst_RAM_Word6_INIT_31,
INIT_32 => PM_Inst_RAM_Word6_INIT_32,
INIT_33 => PM_Inst_RAM_Word6_INIT_33,
INIT_34 => PM_Inst_RAM_Word6_INIT_34,
INIT_35 => PM_Inst_RAM_Word6_INIT_35,
INIT_36 => PM_Inst_RAM_Word6_INIT_36,
INIT_37 => PM_Inst_RAM_Word6_INIT_37,
INIT_38 => PM_Inst_RAM_Word6_INIT_38,
INIT_39 => PM_Inst_RAM_Word6_INIT_39,
INIT_3A => PM_Inst_RAM_Word6_INIT_3A,
INIT_3B => PM_Inst_RAM_Word6_INIT_3B,
INIT_3C => PM_Inst_RAM_Word6_INIT_3C,
INIT_3D => PM_Inst_RAM_Word6_INIT_3D,
INIT_3E => PM_Inst_RAM_Word6_INIT_3E,
INIT_3F => PM_Inst_RAM_Word6_INIT_3F
)
port map(
DO => RAMBlDOut(6)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(6)
);
RAM_Word7:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word7_INIT_00,
INIT_01 => PM_Inst_RAM_Word7_INIT_01,
INIT_02 => PM_Inst_RAM_Word7_INIT_02,
INIT_03 => PM_Inst_RAM_Word7_INIT_03,
INIT_04 => PM_Inst_RAM_Word7_INIT_04,
INIT_05 => PM_Inst_RAM_Word7_INIT_05,
INIT_06 => PM_Inst_RAM_Word7_INIT_06,
INIT_07 => PM_Inst_RAM_Word7_INIT_07,
INIT_08 => PM_Inst_RAM_Word7_INIT_08,
INIT_09 => PM_Inst_RAM_Word7_INIT_09,
INIT_0A => PM_Inst_RAM_Word7_INIT_0A,
INIT_0B => PM_Inst_RAM_Word7_INIT_0B,
INIT_0C => PM_Inst_RAM_Word7_INIT_0C,
INIT_0D => PM_Inst_RAM_Word7_INIT_0D,
INIT_0E => PM_Inst_RAM_Word7_INIT_0E,
INIT_0F => PM_Inst_RAM_Word7_INIT_0F,
INIT_10 => PM_Inst_RAM_Word7_INIT_10,
INIT_11 => PM_Inst_RAM_Word7_INIT_11,
INIT_12 => PM_Inst_RAM_Word7_INIT_12,
INIT_13 => PM_Inst_RAM_Word7_INIT_13,
INIT_14 => PM_Inst_RAM_Word7_INIT_14,
INIT_15 => PM_Inst_RAM_Word7_INIT_15,
INIT_16 => PM_Inst_RAM_Word7_INIT_16,
INIT_17 => PM_Inst_RAM_Word7_INIT_17,
INIT_18 => PM_Inst_RAM_Word7_INIT_18,
INIT_19 => PM_Inst_RAM_Word7_INIT_19,
INIT_1A => PM_Inst_RAM_Word7_INIT_1A,
INIT_1B => PM_Inst_RAM_Word7_INIT_1B,
INIT_1C => PM_Inst_RAM_Word7_INIT_1C,
INIT_1D => PM_Inst_RAM_Word7_INIT_1D,
INIT_1E => PM_Inst_RAM_Word7_INIT_1E,
INIT_1F => PM_Inst_RAM_Word7_INIT_1F,
INIT_20 => PM_Inst_RAM_Word7_INIT_20,
INIT_21 => PM_Inst_RAM_Word7_INIT_21,
INIT_22 => PM_Inst_RAM_Word7_INIT_22,
INIT_23 => PM_Inst_RAM_Word7_INIT_23,
INIT_24 => PM_Inst_RAM_Word7_INIT_24,
INIT_25 => PM_Inst_RAM_Word7_INIT_25,
INIT_26 => PM_Inst_RAM_Word7_INIT_26,
INIT_27 => PM_Inst_RAM_Word7_INIT_27,
INIT_28 => PM_Inst_RAM_Word7_INIT_28,
INIT_29 => PM_Inst_RAM_Word7_INIT_29,
INIT_2A => PM_Inst_RAM_Word7_INIT_2A,
INIT_2B => PM_Inst_RAM_Word7_INIT_2B,
INIT_2C => PM_Inst_RAM_Word7_INIT_2C,
INIT_2D => PM_Inst_RAM_Word7_INIT_2D,
INIT_2E => PM_Inst_RAM_Word7_INIT_2E,
INIT_2F => PM_Inst_RAM_Word7_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word7_INIT_30,
INIT_31 => PM_Inst_RAM_Word7_INIT_31,
INIT_32 => PM_Inst_RAM_Word7_INIT_32,
INIT_33 => PM_Inst_RAM_Word7_INIT_33,
INIT_34 => PM_Inst_RAM_Word7_INIT_34,
INIT_35 => PM_Inst_RAM_Word7_INIT_35,
INIT_36 => PM_Inst_RAM_Word7_INIT_36,
INIT_37 => PM_Inst_RAM_Word7_INIT_37,
INIT_38 => PM_Inst_RAM_Word7_INIT_38,
INIT_39 => PM_Inst_RAM_Word7_INIT_39,
INIT_3A => PM_Inst_RAM_Word7_INIT_3A,
INIT_3B => PM_Inst_RAM_Word7_INIT_3B,
INIT_3C => PM_Inst_RAM_Word7_INIT_3C,
INIT_3D => PM_Inst_RAM_Word7_INIT_3D,
INIT_3E => PM_Inst_RAM_Word7_INIT_3E,
INIT_3F => PM_Inst_RAM_Word7_INIT_3F
)
port map(
DO => RAMBlDOut(7)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(7)
);
--end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 10)));
end RTL;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of syncram_banked_1r1w is
begin
syncram : entity work.syncram_banked_1r1w_inferred(rtl)
generic map (
addr_bits => addr_bits,
word_bits => word_bits,
log2_banks => log2_banks,
write_first => write_first
)
port map (
clk => clk,
we => we,
wbanken => wbanken,
waddr => waddr,
wdata => wdata,
re => re,
rbanken => rbanken,
raddr => raddr,
rdata => rdata
);
end;
|
-- Teste geral para a estrutura do Processador Mips8B
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Ieee.Numeric_Std.all;
Entity test_Memory is
End Entity test_Memory;
Architecture test_general of test_Memory is
Component Mips8B_Core is
Port(Reset_n: In Std_Logic;
Clock: In Std_Logic;
MAddr: Out Std_Logic_Vector(7 downto 0);
MCmd: Out Std_Logic_Vector(1 downto 0);
MData: Out Std_Logic_Vector(7 downto 0);
SData: In Std_Logic_Vector(7 downto 0);
SCmdAccept: In Std_Logic);
End Component Mips8B_Core;
Component memory_test is
Port(Clock_Mem: In Std_Logic;
MAddr: In Std_Logic_Vector(7 downto 0);
MCmd: In Std_Logic_Vector(1 downto 0);
MData: In Std_Logic_Vector(7 downto 0);
SData: Out Std_Logic_Vector(7 downto 0);
SCmdAccept: Out Std_Logic);
End Component memory_test;
Signal Reset_n: Std_Logic;
Signal Clock: Std_Logic := '0';
Signal Clock_Mem: Std_Logic := '0';
Signal MAddr: Std_Logic_Vector(7 downto 0);
Signal MCmd: Std_Logic_Vector(1 downto 0);
Signal MData: Std_Logic_Vector(7 downto 0);
Signal SData: Std_Logic_Vector(7 downto 0);
Signal SCmdAccept: Std_Logic;
Begin
Reset_n <= '1', '0' after 20 ns, '1' after 40 ns;
Clock <= not Clock after 10 ns;
Clock_Mem <= not Clock_Mem after 15 ns;
DUV: Mips8B_Core
Port Map( Reset_n => Reset_n,
Clock => Clock,
MAddr => MAddr,
MCmd => MCmd,
MData => MData,
SData => SData,
SCmdAccept => SCmdAccept);
MEM: memory_test
Port Map( Clock_Mem => Clock_Mem,
MAddr => MAddr,
MCmd => MCmd,
MData => MData,
SData => SData,
SCmdAccept => SCmdAccept);
End Architecture test_general;
Configuration general_test of test_Memory is
For test_general
For DUV: Mips8B_Core Use Configuration Work.Mips8B_Core_struct_conf;
End For;
For MEM: memory_test Use Entity Work.memory_test(behave);
End For;
End For;
End Configuration general_test;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SEUDisp22 is
Port ( Disp22 : in STD_LOGIC_VECTOR(21 downto 0);
S : out STD_LOGIC_VECTOR(31 downto 0)
);
end SEUDisp22;
architecture Behavioral of SEUDisp22 is
begin
process(Disp22)
begin
for i in 22 to 31 loop
S(i)<=Disp22(21);
end loop;
S(21 downto 0)<=Disp22;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity output06 is
port (i : std_logic;
o : out std_logic_vector (3 downto 0));
end output06;
architecture behav of output06 is
signal s : std_logic_vector(3 downto 0);
begin
process (i)
begin
s(0) <= i;
s (1) <= not i;
s (3) <= i;
end process;
s (2) <= '0';
o <= s;
end behav;
|
-- hdlctransmitter.vhd
--
-- takes 8-bit parallel data and sends frame
-- Frame ends when data value is written with "txLast" set.
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
-- debug libraries
use std.textio.all;
use ieee.std_logic_textio.all;
entity HdlcTransmitter is
generic (
TxReqChainSize : integer := 2 -- defines length of metastability chain; must be at least two.
);
port (
-- microprocesser interface
Din : in Std_Logic_Vector (7 downto 0); -- Tx register
txLast : in Std_Logic;
txWR : in Std_Logic;
txReq : out Std_Logic; -- high if space in register
txRST : in Std_Logic;
-- bit clock
txCLK : in Std_Logic;
-- line interface
txD : buffer Std_Logic;
txEn : buffer Std_Logic
);
-- translate_off
-- check bounds of generics -- error reported only on execution
begin
assert( txReqChainSize > 1 )
report "txReqChainSize should be at least 2!"
severity ERROR;
-- translate_on
end HdlcTransmitter;
architecture behavioural of HdlcTransmitter is
type txStateType is (Idle, StartFlag, SendData, SendLast, SendCRC1, SendCRC2, FinalFlag);
signal txState, txNextState : txStateType;
signal txFIFO, txShiftReg : Std_Logic_Vector (7 downto 0);
signal txBitCount : Std_Logic_Vector (2 downto 0);
signal txOneCount : Std_Logic_Vector (2 downto 0);
signal txShiftEnable : Std_Logic;
signal txShiftClk, dontSwallow: Std_Logic;
signal txRq : Std_Logic_Vector (txReqChainSize-1 downto 0); -- shifted through to minimise metastability;
-- 0 means reg is full
-- processor watches top bit, HDLC watches bit 0
-- calculate an initialisation vector for txRq chain (all-ones)
signal txReqChainEmpty : Std_Logic_Vector (txReqChainSize-1 downto 0) := (others => '1');
signal crcReg : Std_Logic_Vector (15 downto 0) := x"AAAA";
signal zeroIns : Std_Logic; -- output of state machine indicating that zero insertion after five 1's is active
-- handy alias
signal DataWaiting : boolean;
component crc16 is
port (clk, reset, ce, din: in std_logic;
crc_sum: out std_logic_vector(15 downto 0));
end component crc16;
signal txCrcEn : Std_Logic;
signal crcReset : Std_Logic;
-- translate_off
-- stuff for debugging simulations
signal stateDecode : integer;
signal nextStateDecode : integer;
-- translate_on
begin
-- translate_off
-- stuff for debugging simulations
process (txState) begin
if txState = Idle then
stateDecode <= 0;
elsif txState = StartFlag then
stateDecode <= 1;
elsif txState = SendData then
stateDecode <= 2;
elsif txState = SendLast then
stateDecode <= 3;
elsif txState = SendCRC1 then
stateDecode <= 4;
elsif txState = SendCRC2 then
stateDecode <= 5;
elsif txState = FinalFlag then
stateDecode <= 6;
end if;
end process;
process (txNextState) begin
if txNextState = Idle then
nextStateDecode <= 0;
elsif txNextState = StartFlag then
nextStateDecode <= 1;
elsif txNextState = SendData then
nextStateDecode <= 2;
elsif txNextState = SendLast then
nextStateDecode <= 3;
elsif txNextState = SendCRC1 then
nextStateDecode <= 4;
elsif txNextState = SendCRC2 then
nextStateDecode <= 5;
elsif txNextState = FinalFlag then
nextStateDecode <= 6;
end if;
end process;
-- translate_on
txReq <= txRq(txReqChainSize-1) AND NOT txRST; -- use top bit so it appears full to processor as soon as reg is written. De-assert when reset
txD <= txShiftReg(0);
DataWaiting <= txRq(0) = '0';
-- pulse dontSwallower: removes a txCLK pulse when zero insertion required
txShiftClk <= txClk and dontSwallow;
pTxShiftClk : process(txCLK, txOneCount)
begin
if falling_edge(txCLK) then
if txOneCount="100" and txD = '1' and zeroIns = '1' then
dontSwallow <= '0';
else
dontSwallow <= '1';
end if;
end if;
end process pTxShiftClk;
-- latching data into tx holding reg (FIFO)
pTxFIFO : process(txRST, txWR)
begin
if txRST = '1' then
txFIFO <= "00000000";
elsif rising_edge(txWR) then
txFIFO <= Din;
end if;
end process pTxFIFO;
-- txEn
pTxEn : process(txRST, txCLK)
begin
if txRST = '1' then
txEn <= '0';
elsif rising_edge(txCLK) then
if txState = Idle then
txEn <= '0';
else
txEn <= '1';
end if;
end if;
end process pTxEn;
-- ZeroIns
pZeroIns : process(txRST, txCLK)
begin
if txRST = '1' then
zeroIns <= '0';
elsif rising_edge(txCLK) then
case txState is
when Idle | StartFlag | FinalFlag => zeroIns <= '0';
when others =>zeroIns <= '1';
end case;
end if;
end process pZeroIns;
-- generate Tx request signal for processor
pTxRq : process(txRST, txWR, txCLK)
begin
if txRST = '1' then
txRq <= txReqChainEmpty; -- mark reg empty
elsif rising_edge(txWR) then
txRq (txReqChainSize-1) <= '0'; -- insert "full" signal at top of metastab chain
elsif rising_edge(txCLK) and dontSwallow = '1' then
if txBitCount = "000" and (txState = SendData OR txState = SendLast) then -- loading byte into shift reg
txRq <= txReqChainEmpty; -- signal that we've taken the data
else
txRq(txReqChainSize-2 downto 0) <= txRq(txReqChainSize-1 downto 1); -- shift the "full" signal through metastab chain
end if;
end if;
end process pTxRq;
-- mark where crc should be calculated
process (txState, txShiftClk)
begin
if rising_edge(txShiftClk) then
if txState = SendData or txState = SendLast then
txCrcEn <= '1';
crcReset <= '0';
else
txCrcEn <= '0';
if txState = idle then
crcReset <='1';
else
crcReset <='0';
end if;
end if;
end if;
end process;
-- calculate CRC -- instantiate CRC engine
TxCrcGen : crc16
port map ( clk => txShiftClk,
reset => crcReset,
ce => txCrcEn,
din => txD,
crc_sum => crcReg
);
-- ******* Main state machine *********
-- register
process(txShiftClk, txRST)
-- clocked on bit count rolling over (8 bits tx'd)
begin
if txRST = '1' then
txState <= Idle;
elsif rising_edge(txShiftClk) then
if txBitCount = "000" then
txState <= txNextState;
else
txState <= txState;
end if;
end if;
end process;
-- state register inputs
process
( DataWaiting, txState --
)
begin
case txState is
when Idle =>
if DataWaiting then
txNextState <= StartFlag;
else
txNextState <= Idle;
end if;
when StartFlag =>
txNextState <= SendData;
when SendData =>
if txLast = '1' then
txNextState <= SendLast;
else
txNextState <= SendData;
end if;
when SendLast =>
txNextState <= SendCRC1;
when SendCRC1 =>
txNextState <= SendCRC2;
when SendCRC2 =>
txNextState <= FinalFlag;
when FinalFlag =>
txNextState <= Idle;
end case;
end process;
-- clocking data into shift reg (out of tx holding reg, CRC, flag or abort)
pTxData : process(txRST, txRq, txCLK, txShiftEnable)
begin
if txRST = '1' then
txBitCount <= "000";
elsif rising_edge(txCLK) then
if txOneCount = "100" and txD ='1' and ZeroIns = '1' then
txShiftReg(0) <= '0';
-- note we're not incrementing the bit count whilst we insert the extra zero
else
txBitCount <= Std_Logic_Vector(unsigned(txBitCount) + 1); -- increment bit count
if txBitCount = "000" and dontSwallow = '1' then -- we've reached a byte boundary
case txState is
when Idle | StartFlag | FinalFlag =>
txShiftReg <= "01111110";
when SendData | SendLast =>
if txRq(0) = '1' then
-- we have underrun
-- TODO: insert underrun handling
else
-- load in next byte
txShiftReg <= txFIFO;
end if;
when SendCRC1 =>
txShiftReg <= crcReg (15 downto 8);
when SendCRC2 =>
txShiftReg <= crcReg (7 downto 0);
end case;
else -- we need to shift out next bit
txShiftReg (6 downto 0) <= txShiftReg (7 downto 1);
end if;
end if;
end if;
end process pTxData;
-- Ones counter counts successive ones when enabled
pTxOneCount : process(txCLK, txRST, txEn)
begin
if txRST = '1' OR txEn = '0' then
txOneCount <= "000";
elsif rising_edge(txCLK) then
if txShiftReg (0) = '0' then
txOneCount <= "000";
else
txOneCount <= Std_Logic_Vector(unsigned(txOneCount) + 1);
end if;
end if;
end process pTxOneCount;
end behavioural;
|
----------------------------------------------------------------------------------
-- Company: Digilent Ro
-- Engineer: Elod Gyorgy
--
-- Create Date: 14:35:21 02/23/2009
-- Design Name:
-- Module Name: VideoTimingCtl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: VideoTimingCtl generates the proper synchronization signals
-- according to the selected resolution.
--
-- Dependencies: digilent.Video
--
-- Revision:
-- Revision 0.03 - Moved the Active Video area to the first part of the counter
-- Revision 0.02 - Added resolution 480x272 progressive
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library digilent;
use digilent.Video.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VideoTimingCtl is
Port (
PCLK_I : in STD_LOGIC; --variable depending on RSEL_I
RST_I : in STD_LOGIC; --reset
RSEL_I : in RESOLUTION;
VDE_O : out STD_LOGIC; --data enable for pixel bus
HS_O : out STD_LOGIC;
VS_O : out STD_LOGIC;
HCNT_O : out NATURAL;
VCNT_O : out NATURAL);
end VideoTimingCtl;
architecture Behavioral of VideoTimingCtl is
----------------------------------------------------------------------------------
-- VGA Timing Signals
----------------------------------------------------------------------------------
signal HCnt : NATURAL range 0 to H_MAX := 0; --horizontal counter
signal VCnt : NATURAL range 0 to V_MAX := 0; --vertical counter
signal H_AV, V_AV, H_AV_FP, V_AV_FP, H_AV_FP_S, V_AV_FP_S, H_AV_FP_S_BP, V_AV_FP_S_BP : NATURAL;
signal hs, vs: std_logic; -- horizontal/vertical sync
signal vde : std_logic; -- data enable
signal SRst : std_logic;
signal H_POL, V_POL : BOOLEAN;
begin
----------------------------------------------------------------------------------
-- Resolution Selector
----------------------------------------------------------------------------------
with RSEL_I select
H_AV <= H_640_480p_AV when R640_480P,
H_720_480p_AV when R720_480P,
H_480_272p_AV when R480_272P,
H_1280_720p_AV when R1280_720P,
H_1600_900p_AV when R1600_900P,
H_800_600p_AV when R800_600P,
H_640_480p_AV when others;
with RSEL_I select
V_AV <= V_640_480p_AV when R640_480P,
V_720_480p_AV when R720_480P,
V_480_272p_AV when R480_272P,
V_1280_720p_AV when R1280_720P,
V_1600_900p_AV when R1600_900P,
V_800_600p_AV when R800_600P,
V_640_480p_AV when others;
with RSEL_I select
H_AV_FP <= H_640_480p_AV_FP when R640_480P,
H_720_480p_AV_FP when R720_480P,
H_480_272p_AV_FP when R480_272P,
H_1280_720p_AV_FP when R1280_720P,
H_1600_900p_AV_FP when R1600_900P,
H_800_600p_AV_FP when R800_600P,
H_640_480p_AV_FP when others;
with RSEL_I select
V_AV_FP <= V_640_480p_AV_FP when R640_480P,
V_720_480p_AV_FP when R720_480P,
V_480_272p_AV_FP when R480_272P,
V_1280_720p_AV_FP when R1280_720P,
V_1600_900p_AV_FP when R1600_900P,
V_800_600p_AV_FP when R800_600P,
V_640_480p_AV_FP when others;
with RSEL_I select
H_AV_FP_S <= H_640_480p_AV_FP_S when R640_480P,
H_720_480p_AV_FP_S when R720_480P,
H_480_272p_AV_FP_S when R480_272P,
H_1280_720p_AV_FP_S when R1280_720P,
H_1600_900p_AV_FP_S when R1600_900P,
H_800_600p_AV_FP_S when R800_600P,
H_640_480p_AV_FP_S when others;
with RSEL_I select
V_AV_FP_S <= V_640_480p_AV_FP_S when R640_480P,
V_720_480p_AV_FP_S when R720_480P,
V_480_272p_AV_FP_S when R480_272P,
V_1280_720p_AV_FP_S when R1280_720P,
V_1600_900p_AV_FP_S when R1600_900P,
V_800_600p_AV_FP_S when R800_600P,
V_640_480p_AV_FP_S when others;
with RSEL_I select
H_AV_FP_S_BP <= H_640_480p_AV_FP_S_BP when R640_480P,
H_720_480p_AV_FP_S_BP when R720_480P,
H_480_272p_AV_FP_S_BP when R480_272P,
H_1280_720p_AV_FP_S_BP when R1280_720P,
H_1600_900p_AV_FP_S_BP when R1600_900P,
H_800_600p_AV_FP_S_BP when R800_600P,
H_640_480p_AV_FP_S_BP when others;
with RSEL_I select
V_AV_FP_S_BP <= V_640_480p_AV_FP_S_BP when R640_480P,
V_720_480p_AV_FP_S_BP when R720_480P,
V_480_272p_AV_FP_S_BP when R480_272P,
V_1280_720p_AV_FP_S_BP when R1280_720P,
V_1600_900p_AV_FP_S_BP when R1600_900P,
V_800_600p_AV_FP_S_BP when R800_600P,
V_640_480p_AV_FP_S_BP when others;
with RSEL_I select
H_POL <= H_640_480p_POL when R640_480P,
H_720_480p_POL when R720_480P,
H_480_272p_POL when R480_272P,
H_1280_720p_POL when R1280_720P,
H_1600_900p_POL when R1600_900P,
H_800_600p_POL when R800_600P,
H_640_480p_POL when others;
with RSEL_I select
V_POL <= V_640_480p_POL when R640_480P,
V_720_480p_POL when R720_480P,
V_480_272p_POL when R480_272P,
V_1280_720p_POL when R1280_720P,
V_1600_900p_POL when R1600_900P,
V_800_600p_POL when R800_600P,
V_640_480p_POL when others;
----------------------------------------------------------------------------------
-- Local Reset
----------------------------------------------------------------------------------
Inst_LocalRst: entity digilent.LocalRst PORT MAP(
RST_I => RST_I,
CLK_I => PCLK_I,
SRST_O => SRst
);
----------------------------------------------------------------------------------
-- Video Timing Counter
----------------------------------------------------------------------------------
process (PCLK_I)
begin
if Rising_Edge(PCLK_I) then
if (SRst = '1') then
HCnt <= H_AV_FP_S_BP - 1; -- 0 is an active pixel
VCnt <= V_AV_FP_S_BP - 1;
vde <= '0';
hs <= '1';
vs <= '1';
else
--pixel/line counters and video data enable
if (HCnt = H_AV_FP_S_BP - 1) then
HCnt <= 0;
if (VCnt = V_AV_FP_S_BP - 1) then
VCnt <= 0;
else
VCnt <= VCnt + 1;
end if;
else
HCnt <= HCnt + 1;
end if;
--sync pulse in sync phase
if (HCnt >= H_AV_FP-1) and (HCnt < H_AV_FP_S-1) then -- one cycle earlier (registered)
hs <= '0';
if (VCnt >= V_AV_FP) and (VCnt < V_AV_FP_S) then
vs <= '0';
else
vs <= '1';
end if;
else
hs <= '1';
end if;
--video data enable
if ((HCnt = H_AV_FP_S_BP - 1 and (VCnt = V_AV_FP_S_BP - 1 or VCnt < V_AV - 1)) or -- first pixel in frame
(HCnt < H_AV - 1 and VCnt < V_AV)) then
vde <= '1';
else
vde <= '0';
end if;
end if;
end if;
end process;
HCNT_O <= HCnt;
VCNT_O <= VCnt;
HS_O <= not hs when H_POL else
hs;
VS_O <= not vs when V_POL else
vs;
VDE_O <= vde;
end Behavioral;
|
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END CosDPStratixVf400_safe_path;
|
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END CosDPStratixVf400_safe_path;
|
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END CosDPStratixVf400_safe_path;
|
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END CosDPStratixVf400_safe_path;
|
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END CosDPStratixVf400_safe_path;
|
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END CosDPStratixVf400_safe_path;
|
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END CosDPStratixVf400_safe_path;
|
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END CosDPStratixVf400_safe_path;
|
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END CosDPStratixVf400_safe_path;
|
-- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END CosDPStratixVf400_safe_path;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: BINARYZACJA_tb_pkg.vhd
--
-- Description:
-- DMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BINARYZACJA_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BINARYZACJA_TB_PKG;
PACKAGE BODY BINARYZACJA_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BINARYZACJA_TB_PKG;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: BINARYZACJA_tb_pkg.vhd
--
-- Description:
-- DMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BINARYZACJA_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BINARYZACJA_TB_PKG;
PACKAGE BODY BINARYZACJA_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BINARYZACJA_TB_PKG;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: BINARYZACJA_tb_pkg.vhd
--
-- Description:
-- DMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BINARYZACJA_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BINARYZACJA_TB_PKG;
PACKAGE BODY BINARYZACJA_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BINARYZACJA_TB_PKG;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: BINARYZACJA_tb_pkg.vhd
--
-- Description:
-- DMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BINARYZACJA_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BINARYZACJA_TB_PKG;
PACKAGE BODY BINARYZACJA_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BINARYZACJA_TB_PKG;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-08 : Mickael Carl (CNES): Creation
-- V1.1: 2018-09-20 : Florent Manni (CNES) : updated to trigger simulation mistake in Modelsim
-------------------------------------------------------------------------------------------------
-- File name : STD_04500_bad.vhd
-- File Creation date : 2015-04-08
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Clock reassignment: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.pkg_HBK.all;
--CODE
entity STD_04500_bad is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
-- D Flip-flop 3 stages pipeline
-- D Flip-Flop A
i_DA : in std_logic; -- Input signal
o_QA : out std_logic; -- Output signal
-- D Flip-flop B
o_QB : out std_logic; -- Output signal
-- D Flip-Flop C
o_QC : out std_logic -- Output signal
);
end STD_04500_bad;
architecture Behavioral of STD_04500_bad is
signal ClockA : std_logic; -- Clock input for A Flip-Flop
signal ClockB : std_logic; -- Clock input for B Flip-Flop
signal ClockC : std_logic; -- Clock input for C Flip-Flop
signal QA : std_logic;
signal QB : std_logic;
begin
ClockC <= ClockB;
ClockB <= ClockA;
ClockA <= i_Clock;
-- First Flip-Flop
P_FlipFlopA : process(ClockA, i_Reset_n)
begin
if (i_Reset_n = '0') then
QA <= '0';
elsif (rising_edge(ClockA)) then
QA <= i_DA;
end if;
end process;
-- Second Flip-Flop
P_FlipFlopB: process(ClockB, i_Reset_n)
begin
if (i_Reset_n = '0') then
QB <= '0';
elsif (rising_edge(ClockB)) then
QB <= QA;
end if;
end process;
-- Third Flip-Flop
P_FlipFlopC: process(ClockC, i_Reset_n)
begin
if (i_Reset_n = '0') then
o_QC <= '0';
elsif (rising_edge(ClockC)) then
o_QC <= QB;
end if;
end process;
o_QA <= QA;
o_QB <= QB;
end Behavioral;
--CODE
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2012 Fredrik Ringhage, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library micron;
use micron.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := true
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal gclk : std_logic := '0';
signal rst : std_logic := '0';
signal button : std_logic_vector(3 downto 0) := (others => '0');
signal switch : std_logic_vector(7 downto 0); -- I/O port
signal led : std_logic_vector(7 downto 0); -- I/O port
signal processing_system7_0_MIO : std_logic_vector(53 downto 0);
signal processing_system7_0_PS_SRSTB : std_logic;
signal processing_system7_0_PS_CLK : std_logic;
signal processing_system7_0_PS_PORB : std_logic;
signal processing_system7_0_DDR_Clk : std_logic;
signal processing_system7_0_DDR_Clk_n : std_logic;
signal processing_system7_0_DDR_CKE : std_logic;
signal processing_system7_0_DDR_CS_n : std_logic;
signal processing_system7_0_DDR_RAS_n : std_logic;
signal processing_system7_0_DDR_CAS_n : std_logic;
signal processing_system7_0_DDR_WEB_pin : std_logic;
signal processing_system7_0_DDR_BankAddr : std_logic_vector(2 downto 0);
signal processing_system7_0_DDR_Addr : std_logic_vector(14 downto 0);
signal processing_system7_0_DDR_ODT : std_logic;
signal processing_system7_0_DDR_DRSTB : std_logic;
signal processing_system7_0_DDR_DQ : std_logic_vector(31 downto 0);
signal processing_system7_0_DDR_DM : std_logic_vector(3 downto 0);
signal processing_system7_0_DDR_DQS : std_logic_vector(3 downto 0);
signal processing_system7_0_DDR_DQS_n : std_logic_vector(3 downto 0);
signal processing_system7_0_DDR_VRN : std_logic;
signal processing_system7_0_DDR_VRP : std_logic;
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false
);
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : in std_logic;
processing_system7_0_PS_CLK : in std_logic;
processing_system7_0_PS_PORB : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0)
);
end component;
begin
-- clock, reset and misc
gclk <= not gclk after 5.0 ns;
rst <= '1' after 1 us;
button <= (others => '0');
switch <= (others => '0');
cpu : leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow,
testahb => testahb
)
port map (
processing_system7_0_MIO => processing_system7_0_MIO,
processing_system7_0_PS_SRSTB => processing_system7_0_PS_SRSTB,
processing_system7_0_PS_CLK => processing_system7_0_PS_CLK,
processing_system7_0_PS_PORB => processing_system7_0_PS_PORB,
processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP,
button => button,
switch => switch,
led => led
);
end ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2662.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02662ent IS
END c13s03b01x00p02n01i02662ent;
ARCHITECTURE c13s03b01x00p02n01i02662arch OF c13s03b01x00p02n01i02662ent IS
BEGIN
TESTING: PROCESS
variable !k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02662 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02662arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2662.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02662ent IS
END c13s03b01x00p02n01i02662ent;
ARCHITECTURE c13s03b01x00p02n01i02662arch OF c13s03b01x00p02n01i02662ent IS
BEGIN
TESTING: PROCESS
variable !k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02662 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02662arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2662.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02662ent IS
END c13s03b01x00p02n01i02662ent;
ARCHITECTURE c13s03b01x00p02n01i02662arch OF c13s03b01x00p02n01i02662ent IS
BEGIN
TESTING: PROCESS
variable !k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02662 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02662arch;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_ds-qn.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
use qsim.qsim_types.all, random.random.all;
architecture queue_net of disk_system is
constant disk_cache_miss_rate : real := 0.2;
constant num_disks : positive := 2;
constant disk_cache_fork_probabilities : probability_vector(1 to num_disks)
:= ( others => disk_cache_miss_rate / real(num_disks) );
signal info_detail_control : info_detail_type := none;
signal new_job, cpu_queue_in, cpu_in, cpu_out,
quantum_expired, job_done, requesting_disk,
disk_cache_hit, request_done : arc_type;
signal disk_cache_miss, disk_done : arc_vector(1 to num_disks);
signal cpu_ready : boolean;
begin
new_jobs : entity source
generic map ( name => "new_jobs",
distribution => exponential,
mean_inter_arrival_time => 2 sec,
seed => sample_seeds(1),
time_unit => ms,
info_file_name => "new_jobs.dat" )
port map ( out_arc => new_job,
info_detail => info_detail_control );
cpu_join : entity join
generic map ( name => "cpu_join",
time_unit => ms,
info_file_name => "cpu_join.dat" )
port map ( in_arc(1) => quantum_expired,
in_arc(2) => new_job,
in_arc(3) => request_done,
out_arc => cpu_queue_in,
info_detail => info_detail_control );
cpu_queue : entity queue
generic map ( name => "cpu_queue",
time_unit => ms,
info_file_name => "cpu_queue.dat" )
port map ( in_arc => cpu_queue_in,
out_arc => cpu_in,
out_ready => cpu_ready,
info_detail => info_detail_control );
cpu : entity server
generic map ( name => "cpu",
distribution => uniform,
mean_service_time => 50 ms,
seed => sample_seeds(2),
time_unit => ms,
info_file_name => "cpu.dat" )
port map ( in_arc => cpu_in,
in_ready => cpu_ready,
out_arc => cpu_out,
info_detail => info_detail_control );
cpu_fork : entity fork
generic map ( name => "cpu_fork",
probabilities => ( 1 => 0.5, 2 => 0.45 ),
seed => sample_seeds(3),
time_unit => ms,
info_file_name => "cpu_fork.dat" )
port map ( in_arc => cpu_out,
out_arc(1) => quantum_expired,
out_arc(2) => requesting_disk,
out_arc(3) => job_done,
info_detail => info_detail_control );
job_sink : entity sink
generic map ( name => "job_sink",
time_unit => ms,
info_file_name => "job_sink.dat" )
port map ( in_arc => job_done,
info_detail => info_detail_control );
disk_cache_fork : entity fork
generic map ( name => "disk_cache_fork",
probabilities => disk_cache_fork_probabilities,
seed => sample_seeds(4),
time_unit => ms,
info_file_name => "disk_cache_fork.dat" )
port map ( in_arc => requesting_disk,
out_arc(1 to num_disks) => disk_cache_miss,
out_arc(num_disks + 1) => disk_cache_hit,
info_detail => info_detail_control );
disk_array : for disk_index in 1 to num_disks generate
constant disk_index_str : string := integer'image(disk_index);
signal disk_in : arc_type;
signal disk_ready : boolean;
begin
disk_queue : entity queue
generic map ( name => "disk_queue_" & disk_index_str,
time_unit => ms,
info_file_name => "disk_queue_" & disk_index_str & ".dat" )
port map ( in_arc => disk_cache_miss(disk_index),
out_arc => disk_in,
out_ready => disk_ready,
info_detail => info_detail_control );
disk : entity server
generic map ( name => "disk_" & disk_index_str,
distribution => exponential,
mean_service_time => 15 ms,
seed => sample_seeds(4 + disk_index),
time_unit => ms,
info_file_name => "disk_" & disk_index_str & ".dat" )
port map ( in_arc => disk_in,
in_ready => disk_ready,
out_arc => disk_done(disk_index),
info_detail => info_detail_control );
end generate disk_array;
disk_cache_join : entity join
generic map ( name => "disk_cache_join",
time_unit => ms,
info_file_name => "disk_cache_join.dat" )
port map ( in_arc(1 to num_disks) => disk_done,
in_arc(num_disks + 1) => disk_cache_hit,
out_arc => request_done,
info_detail => info_detail_control );
end architecture queue_net;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_ds-qn.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
use qsim.qsim_types.all, random.random.all;
architecture queue_net of disk_system is
constant disk_cache_miss_rate : real := 0.2;
constant num_disks : positive := 2;
constant disk_cache_fork_probabilities : probability_vector(1 to num_disks)
:= ( others => disk_cache_miss_rate / real(num_disks) );
signal info_detail_control : info_detail_type := none;
signal new_job, cpu_queue_in, cpu_in, cpu_out,
quantum_expired, job_done, requesting_disk,
disk_cache_hit, request_done : arc_type;
signal disk_cache_miss, disk_done : arc_vector(1 to num_disks);
signal cpu_ready : boolean;
begin
new_jobs : entity source
generic map ( name => "new_jobs",
distribution => exponential,
mean_inter_arrival_time => 2 sec,
seed => sample_seeds(1),
time_unit => ms,
info_file_name => "new_jobs.dat" )
port map ( out_arc => new_job,
info_detail => info_detail_control );
cpu_join : entity join
generic map ( name => "cpu_join",
time_unit => ms,
info_file_name => "cpu_join.dat" )
port map ( in_arc(1) => quantum_expired,
in_arc(2) => new_job,
in_arc(3) => request_done,
out_arc => cpu_queue_in,
info_detail => info_detail_control );
cpu_queue : entity queue
generic map ( name => "cpu_queue",
time_unit => ms,
info_file_name => "cpu_queue.dat" )
port map ( in_arc => cpu_queue_in,
out_arc => cpu_in,
out_ready => cpu_ready,
info_detail => info_detail_control );
cpu : entity server
generic map ( name => "cpu",
distribution => uniform,
mean_service_time => 50 ms,
seed => sample_seeds(2),
time_unit => ms,
info_file_name => "cpu.dat" )
port map ( in_arc => cpu_in,
in_ready => cpu_ready,
out_arc => cpu_out,
info_detail => info_detail_control );
cpu_fork : entity fork
generic map ( name => "cpu_fork",
probabilities => ( 1 => 0.5, 2 => 0.45 ),
seed => sample_seeds(3),
time_unit => ms,
info_file_name => "cpu_fork.dat" )
port map ( in_arc => cpu_out,
out_arc(1) => quantum_expired,
out_arc(2) => requesting_disk,
out_arc(3) => job_done,
info_detail => info_detail_control );
job_sink : entity sink
generic map ( name => "job_sink",
time_unit => ms,
info_file_name => "job_sink.dat" )
port map ( in_arc => job_done,
info_detail => info_detail_control );
disk_cache_fork : entity fork
generic map ( name => "disk_cache_fork",
probabilities => disk_cache_fork_probabilities,
seed => sample_seeds(4),
time_unit => ms,
info_file_name => "disk_cache_fork.dat" )
port map ( in_arc => requesting_disk,
out_arc(1 to num_disks) => disk_cache_miss,
out_arc(num_disks + 1) => disk_cache_hit,
info_detail => info_detail_control );
disk_array : for disk_index in 1 to num_disks generate
constant disk_index_str : string := integer'image(disk_index);
signal disk_in : arc_type;
signal disk_ready : boolean;
begin
disk_queue : entity queue
generic map ( name => "disk_queue_" & disk_index_str,
time_unit => ms,
info_file_name => "disk_queue_" & disk_index_str & ".dat" )
port map ( in_arc => disk_cache_miss(disk_index),
out_arc => disk_in,
out_ready => disk_ready,
info_detail => info_detail_control );
disk : entity server
generic map ( name => "disk_" & disk_index_str,
distribution => exponential,
mean_service_time => 15 ms,
seed => sample_seeds(4 + disk_index),
time_unit => ms,
info_file_name => "disk_" & disk_index_str & ".dat" )
port map ( in_arc => disk_in,
in_ready => disk_ready,
out_arc => disk_done(disk_index),
info_detail => info_detail_control );
end generate disk_array;
disk_cache_join : entity join
generic map ( name => "disk_cache_join",
time_unit => ms,
info_file_name => "disk_cache_join.dat" )
port map ( in_arc(1 to num_disks) => disk_done,
in_arc(num_disks + 1) => disk_cache_hit,
out_arc => request_done,
info_detail => info_detail_control );
end architecture queue_net;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_ds-qn.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
use qsim.qsim_types.all, random.random.all;
architecture queue_net of disk_system is
constant disk_cache_miss_rate : real := 0.2;
constant num_disks : positive := 2;
constant disk_cache_fork_probabilities : probability_vector(1 to num_disks)
:= ( others => disk_cache_miss_rate / real(num_disks) );
signal info_detail_control : info_detail_type := none;
signal new_job, cpu_queue_in, cpu_in, cpu_out,
quantum_expired, job_done, requesting_disk,
disk_cache_hit, request_done : arc_type;
signal disk_cache_miss, disk_done : arc_vector(1 to num_disks);
signal cpu_ready : boolean;
begin
new_jobs : entity source
generic map ( name => "new_jobs",
distribution => exponential,
mean_inter_arrival_time => 2 sec,
seed => sample_seeds(1),
time_unit => ms,
info_file_name => "new_jobs.dat" )
port map ( out_arc => new_job,
info_detail => info_detail_control );
cpu_join : entity join
generic map ( name => "cpu_join",
time_unit => ms,
info_file_name => "cpu_join.dat" )
port map ( in_arc(1) => quantum_expired,
in_arc(2) => new_job,
in_arc(3) => request_done,
out_arc => cpu_queue_in,
info_detail => info_detail_control );
cpu_queue : entity queue
generic map ( name => "cpu_queue",
time_unit => ms,
info_file_name => "cpu_queue.dat" )
port map ( in_arc => cpu_queue_in,
out_arc => cpu_in,
out_ready => cpu_ready,
info_detail => info_detail_control );
cpu : entity server
generic map ( name => "cpu",
distribution => uniform,
mean_service_time => 50 ms,
seed => sample_seeds(2),
time_unit => ms,
info_file_name => "cpu.dat" )
port map ( in_arc => cpu_in,
in_ready => cpu_ready,
out_arc => cpu_out,
info_detail => info_detail_control );
cpu_fork : entity fork
generic map ( name => "cpu_fork",
probabilities => ( 1 => 0.5, 2 => 0.45 ),
seed => sample_seeds(3),
time_unit => ms,
info_file_name => "cpu_fork.dat" )
port map ( in_arc => cpu_out,
out_arc(1) => quantum_expired,
out_arc(2) => requesting_disk,
out_arc(3) => job_done,
info_detail => info_detail_control );
job_sink : entity sink
generic map ( name => "job_sink",
time_unit => ms,
info_file_name => "job_sink.dat" )
port map ( in_arc => job_done,
info_detail => info_detail_control );
disk_cache_fork : entity fork
generic map ( name => "disk_cache_fork",
probabilities => disk_cache_fork_probabilities,
seed => sample_seeds(4),
time_unit => ms,
info_file_name => "disk_cache_fork.dat" )
port map ( in_arc => requesting_disk,
out_arc(1 to num_disks) => disk_cache_miss,
out_arc(num_disks + 1) => disk_cache_hit,
info_detail => info_detail_control );
disk_array : for disk_index in 1 to num_disks generate
constant disk_index_str : string := integer'image(disk_index);
signal disk_in : arc_type;
signal disk_ready : boolean;
begin
disk_queue : entity queue
generic map ( name => "disk_queue_" & disk_index_str,
time_unit => ms,
info_file_name => "disk_queue_" & disk_index_str & ".dat" )
port map ( in_arc => disk_cache_miss(disk_index),
out_arc => disk_in,
out_ready => disk_ready,
info_detail => info_detail_control );
disk : entity server
generic map ( name => "disk_" & disk_index_str,
distribution => exponential,
mean_service_time => 15 ms,
seed => sample_seeds(4 + disk_index),
time_unit => ms,
info_file_name => "disk_" & disk_index_str & ".dat" )
port map ( in_arc => disk_in,
in_ready => disk_ready,
out_arc => disk_done(disk_index),
info_detail => info_detail_control );
end generate disk_array;
disk_cache_join : entity join
generic map ( name => "disk_cache_join",
time_unit => ms,
info_file_name => "disk_cache_join.dat" )
port map ( in_arc(1 to num_disks) => disk_done,
in_arc(num_disks + 1) => disk_cache_hit,
out_arc => request_done,
info_detail => info_detail_control );
end architecture queue_net;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:56:43 10/15/2015
-- Design Name:
-- Module Name: Cont0a23 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Cont0a23 is
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ValorDec : in STD_LOGIC_VECTOR (3 downto 0);
ValorUni : in STD_LOGIC_VECTOR (3 downto 0);
Cuenta : out STD_LOGIC_VECTOR (7 downto 0));
end Cont0a23;
architecture Behavioral of Cont0a23 is
signal Cont : integer range 0 to 23;
constant LIMIT : integer := 23;
constant DEC_LIMIT : integer := 2;
constant UNI_LIMIT : integer := 9;
begin
process (Rst,Clk,Cont)
variable dec : integer;
variable uni : integer;
begin
if (Rst = '1') then
Cont <= 0;
elsif (rising_edge(Clk)) then
if (Load = '1') then
dec := conv_integer(ValorDec);
uni := conv_integer(ValorUni);
if ValorDec > DEC_LIMIT then
dec := 2;
end if;
if ValorUni > UNI_LIMIT then
uni := 9;
end if;
if dec = 2 and uni > 3 then
uni := 3;
end if;
Cont <= dec*10 + uni;
elsif (Enable = '1') then
if Cont = LIMIT then
Cont <= 0;
else
Cont <= Cont + 1;
end if;
end if;
end if;
uni := Cont mod 10;
dec := (Cont - uni) / 10;
Cuenta <= conv_std_logic_vector(dec,4) & conv_std_logic_vector(uni,4);
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library grlib;
--use grlib.stdlib.all;
--library gaisler;
--use gaisler.arith.all;
library ims;
use ims.coprocessor.all;
--type sequential32_in_type is record
-- op1 : std_logic_vector(32 downto 0); -- operand 1
-- op2 : std_logic_vector(32 downto 0); -- operand 2
-- flush : std_logic;
-- signed : std_logic;
-- start : std_logic;
--end record;
--type sequential32_out_type is record
-- ready : std_logic;
-- nready : std_logic;
-- icc : std_logic_vector(3 downto 0);
-- result : std_logic_vector(31 downto 0);
--end record;
entity RESOURCE_CUSTOM_C is
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
inp : in sequential32_in_type;
outp : out sequential32_out_type
);
end;
architecture rtl of RESOURCE_CUSTOM_C is
signal A : std_logic_vector(31 downto 0);
signal B : std_logic_vector(31 downto 0);
signal state : std_logic_vector(2 downto 0);
begin
reg : process(clk)
variable vready, vnready : std_logic;
begin
vready := '0';
vnready := '0';
if rising_edge(clk) then
if (rst = '0') then
state <= "000";
elsif (inp.flush = '1') then
state <= "000";
elsif (holdn = '1') then
state <= state;
else
case state is
-- ON ATTEND LA COMMANDE DE START
when "000" =>
if (inp.start = '1') then
--v.x(64) := divi.y(32);
A <= inp.op1(31 downto 0);
B <= inp.op2(31 downto 0);
state <= "010";
else
state <= "000";
A <= A;
B <= B;
end if;
-- ON COMMENCE LE CALCUL
when "001" =>
if( SIGNED(A) > SIGNED(B) ) then
A <= STD_LOGIC_VECTOR(SIGNED(A) - SIGNED(B));
else
B <= STD_LOGIC_VECTOR(SIGNED(B) - SIGNED(A));
end if;
state <= "010";
-- ON TEST LES DONNEES (FIN D'ITERATION)
when "010" =>
if(SIGNED(A) = SIGNED(B)) then
state <= "011";
vnready := '1';
else
state <= "001";
end if;
when others =>
-- ON INDIQUE QUE LE RESULTAT EST PRET
vready := '1';
-- ON RETOURNE DANS L'ETAT INTIAL
state <= "000";
end case;
outp.ready <= vready;
outp.nready <= vnready;
end if; -- if reset
end if; -- if clock
end process;
outp.result <= A;
outp.icc <= "0000";
end;
|
----------------------------------------------------------------------------------
--Code by: Zachary Rauen
--Date: 10/6/14
--Last Modified: 1/22/15
--
--
--Version: 1.2
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all; -- add to do arithmetic operations
use IEEE.std_logic_arith.all; -- add to do arithmetic operations
entity top_level is
Generic (constant SequenceDisplaySpeed : integer := 1; -- 1 Hz
constant RefreshSpeed : integer := 1000; -- 1 KHz
constant sequenceCount : integer := 8;
constant BoardClock : integer := 100000000;
constant buttonMax: std_logic_vector(15 downto 0) := X"FFFF";
constant baud : integer := 9600;
constant SPIspeed : integer :=250000); -- 1KHz, 1Hz
-- Generic (constant SequenceDisplaySpeed : integer := 1000;
-- constant RefreshSpeed : integer := 100000;
-- constant BoardClock : integer := 100000000;
-- constant sequenceCount : integer := 8;
-- constant buttonMax: std_logic_vector(15 downto 0) := X"0002";
-- constant baud : integer := 2000000;
-- constant SPIspeed : integer :=2000000);
----The above lines are used for simulation and chipscope.
Port ( clk : in std_logic;
reset : in std_logic;
reverse : in std_logic;
enabler : in std_logic;
DispVector : out std_logic_vector(7 downto 0);
SegVector : out std_logic_vector(7 downto 0);
oRx : out std_logic;
oSCK : out std_logic;
oSS : out std_logic;
oMOSI : out std_logic;
i2c_sda : inout std_logic;
i2c_scl : inout std_logic);
end top_level;
architecture Behavioral of top_level is
component BoardDisplay is
Generic (RefreshRate : integer := 1000;
ClockSpeed : integer := 100000000);
Port ( ClockState : in std_logic;
Data : in std_logic_vector(15 downto 0);
DisplayVector : out std_logic_vector(7 downto 0);
SegmentVector : out std_logic_vector(7 downto 0));
end component BoardDisplay;
component SequenceController is
Generic (NumOfSequences : integer := 8;
DesiredDisplaySpeed : integer := 100000;
InputClockSpeed : integer := 100000000);
Port ( ClockState : in std_logic;
Enabler : in std_logic;
Reset : in std_logic;
Reverse : in std_logic;
MemAddress : out integer := 0);
end component SequenceController;
component Serial_TTL_display is
Generic (BaudSpeed : integer :=9600;
Boardspeed : integer :=100000000);
Port ( Clock : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (15 downto 0);
RX : out STD_LOGIC);
end component Serial_TTL_display;
component btn_debounce_toggle is
GENERIC (
CONSTANT CNTR_MAX : std_logic_vector(15 downto 0) := X"FFFF");
Port ( BTN_I : in STD_LOGIC;
CLK : in STD_LOGIC;
BTN_O : out STD_LOGIC;
TOGGLE_O : out STD_LOGIC);
end component btn_debounce_toggle;
-- SequenceStorage should be a Xilinx single port ROM IP-Core
COMPONENT SequenceStorage
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
component SPI_display is
Generic (constant BoardClockSpeed : integer := 100000000;
constant SCKSpeed : integer := 250000);
Port ( BoardClock : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (15 downto 0);
SCK : out STD_LOGIC;
SS : out STD_LOGIC;
MOSI : out STD_LOGIC
);
end component SPI_display;
component i2c_controller is
Port ( Clock : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (15 downto 0);
oSDA : inout STD_LOGIC;
oSCL : inout STD_LOGIC);
end component i2c_controller;
signal resetDebounce, enablerToggle, reverseToggle : std_logic;
signal DataFromRom : std_logic_vector(15 downto 0);
signal DataAddress : integer;
signal DataAddressToRom : std_logic_vector(3 downto 0);
signal notReverseToggle : std_logic;
signal high : std_logic := '1';
begin
notReverseToggle <= NOT reverseToggle;
DataAddressToRom <= std_logic_vector(to_unsigned(DataAddress,4));
Reset_debounce: btn_debounce_toggle
generic map (CNTR_MAX => buttonMax)
port map (BTN_I=>reset,CLK=>clk,BTN_O=>resetDebounce,TOGGLE_O=>OPEN);
Enabler_debounce: btn_debounce_toggle
generic map (CNTR_MAX => buttonMax)
port map (BTN_I=>enabler,CLK=>clk,BTN_O=>OPEN,TOGGLE_O=>enablerToggle);
Reverse_debounce: btn_debounce_toggle
generic map (CNTR_MAX => buttonMax)
port map (BTN_I=>reverse,CLK=>clk,BTN_O=>OPEN,TOGGLE_O=>reverseToggle);
SequenceControl: SequenceController
Generic map (NumOfSequences=>sequenceCount,
DesiredDisplaySpeed=>SequenceDisplaySpeed,
InputClockSpeed=>BoardClock)
Port map (ClockState=>clk,
Enabler=>enablerToggle,
Reset=>resetDebounce,
Reverse=> notReverseToggle,
MemAddress=>DataAddress);
BoardController: BoardDisplay
generic map (RefreshRate=>RefreshSpeed,
ClockSpeed=>BoardClock)
port map ( ClockState=>clk,
Data=>DataFromRom,
DisplayVector=>DispVector,
SegmentVector=>SegVector);
TTL: Serial_TTL_display
generic map (BaudSpeed=>baud,
Boardspeed=>BoardClock)
Port map ( Clock=>clk,
Data=>DataFromRom,
RX=>oRx);
MainRom: SequenceStorage
PORT MAP (
clka => clk,
addra => DataAddressToRom,
douta => DataFromRom
);
SPI: SPI_display
generic map (BoardClockSpeed=>BoardClock,
SCKSpeed=>SPIspeed)
Port map ( BoardClock=>clk,
Data=>DataFromRom,
SCK=>oSCK,
SS=>oSS,
MOSI=>oMOSI
);
I2C: i2c_controller
Port map ( Clock=>clk,
dataIn=>DataFromRom,
oSDA=>i2c_sda,
oSCL=>i2c_scl);
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- T48 Microcontroller Core
--
-- $Id: t48_core-c.vhd,v 1.2 2005-06-11 10:08:43 arniml Exp $
--
-------------------------------------------------------------------------------
configuration t48_core_struct_c0 of t48_core is
for struct
for alu_b : t48_alu
use configuration work.t48_alu_rtl_c0;
end for;
for bus_mux_b : t48_bus_mux
use configuration work.t48_bus_mux_rtl_c0;
end for;
for clock_ctrl_b : t48_clock_ctrl
use configuration work.t48_clock_ctrl_rtl_c0;
end for;
for cond_branch_b : t48_cond_branch
use configuration work.t48_cond_branch_rtl_c0;
end for;
for use_db_bus
for db_bus_b : t48_db_bus
use configuration work.t48_db_bus_rtl_c0;
end for;
end for;
for decoder_b : t48_decoder
use configuration work.t48_decoder_rtl_c0;
end for;
for dmem_ctrl_b : t48_dmem_ctrl
use configuration work.t48_dmem_ctrl_rtl_c0;
end for;
for use_timer
for timer_b : t48_timer
use configuration work.t48_timer_rtl_c0;
end for;
end for;
for use_p1
for p1_b : t48_p1
use configuration work.t48_p1_rtl_c0;
end for;
end for;
for use_p2
for p2_b : t48_p2
use configuration work.t48_p2_rtl_c0;
end for;
end for;
for pmem_ctrl_b : t48_pmem_ctrl
use configuration work.t48_pmem_ctrl_rtl_c0;
end for;
for psw_b : t48_psw
use configuration work.t48_psw_rtl_c0;
end for;
end for;
end t48_core_struct_c0;
|
--------------------------------------------------------------
------------------------------------------------------------
-- clock_signal_per_second.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.numeric_bit.all;
entity clock_signal_per_second is
port(clk:in bit;
second_output:buffer bit);
end entity clock_signal_per_second;
architecture behavior of clock_signal_per_second is
signal counter_for_osc_signal:unsigned(31 downto 0);
constant Terminator:integer:=25000000;--25*1000*1000
begin
process
begin
wait until clk'event and clk='1';
if counter_for_osc_signal<Terminator then counter_for_osc_signal<=counter_for_osc_signal+1;
else counter_for_osc_signal<=(others=>'0');
second_output<=not second_output;
end if;
end process;
end architecture behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- H24_Min60_Sec60.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.numeric_bit.all;
entity H24_Min60_Sec60 is
port(Clk,Ldn:in bit;
Din :in unsigned(16 downto 1);
Qout:out unsigned(23 downto 0));
end entity H24_Min60_Sec60;
architecture Behavior of H24_Min60_Sec60 is
signal Q:unsigned(23 downto 0);
alias Second_low:unsigned(3 downto 0) is Q(3 downto 0);
alias Second_hig:unsigned(3 downto 0) is Q(7 downto 4);
alias Min_low: unsigned(3 downto 0) is Q(11 downto 8);
alias Min_hig: unsigned(3 downto 0) is Q(15 downto 12);
alias Hour_low: unsigned(3 downto 0) is Q(19 downto 16);
alias Hour_hig: unsigned(3 downto 0) is Q(23 downto 20);
--internal logic
signal second_count,min_count:integer range 0 to 59;--(63 downto 0);
signal hour_count: integer range 0 to 23;--(31 downto 0);
--signal carry_from_second,carry_from_min:bit;
begin
Qout<=Q;
process(Clk,Ldn,Din)
begin
if(Ldn='0') then min_count<=to_integer(Din(6 downto 1));hour_count<=to_integer(Din(13 downto 9));
elsif(Clk'event and Clk='1') then
if(second_count=59) then second_count<=0;
if(min_count=59) then min_count<=0;
if(hour_count=23) then hour_count<=0;
else hour_count<=hour_count+1;
end if;
--carry_from_min<='1';
else min_count<=min_count+1;
end if;
--carry_from_second<='1';
else second_count<=second_count+1;
end if;
end if;
end process;
Second_low<=to_unsigned(second_count mod 10,4);
Second_hig<=to_unsigned(second_count/10,4);
Min_low<=to_unsigned(min_count mod 10,4);
Min_hig<=to_unsigned(min_count/10,4);
Hour_low<=to_unsigned(hour_count mod 10,4);
Hour_hig<=to_unsigned(hour_count/10,4);
end architecture Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- H24_Min60_Sec60_v2.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.numeric_bit.all;
entity H24_Min60_Sec60_v2 is
port(Clk,Ldn,Reset:in bit;
Din :in unsigned(15 downto 0);
Qout:out unsigned(23 downto 0));
end entity H24_Min60_Sec60_v2;
architecture Behavior of H24_Min60_Sec60_v2 is
signal Q:unsigned(23 downto 0);
alias Second_low:unsigned(3 downto 0) is Q(3 downto 0);
alias Second_hig:unsigned(3 downto 0) is Q(7 downto 4);
alias Min_low: unsigned(3 downto 0) is Q(11 downto 8);
alias Min_hig: unsigned(3 downto 0) is Q(15 downto 12);
alias Hour_low: unsigned(3 downto 0) is Q(19 downto 16);
alias Hour_hig: unsigned(3 downto 0) is Q(23 downto 20);
--internal logic
-- signal second_count,min_count:integer range 0 to 59;--(63 downto 0);
-- signal hour_count: integer range 0 to 23;--(31 downto 0);
--signal carry_from_second,carry_from_min:bit;
constant CLs:unsigned(3 downto 0):="0000";
begin
Qout<=Q;
process(Clk,Ldn,Reset)
begin
if(Reset='0') then --min_count<=to_integer(Din(6 downto 1));hour_count<=to_integer(Din(13 downto 9));
-- Min_low <=Din(4 downto 1);
-- Min_hig <=Din(8 downto 5);
-- Hour_low<=Din(12 downto 9);
-- Hour_hig<=Din(16 downto 13);
Q<=(others=>'0');
elsif(Ldn='0' and Reset='1') then Q(23 downto 8)<=Din;
elsif(Clk'event and Clk='1') then
if(Second_low=9) then Second_low<=CLs;
if(Second_hig=5) then Second_hig<=CLs;
if(Min_low=9) then Min_low<=CLs;
if(Min_hig=5) then Min_hig<=CLs;
if(Hour_hig<2)then
if(Hour_low=9) then Hour_low<=CLs;Hour_hig<=Hour_hig+1;
else Hour_low<=Hour_low+1;
end if;
else --Hour_hig==2
if(Hour_low=3) then Hour_low<=CLs;Hour_hig<=CLs;
else Hour_low<=Hour_low+1;
end if;
end if;
else Min_hig<=Min_hig+1;
end if;
else Min_low<=Min_low+1;
end if;
else Second_hig<=Second_hig+1;
end if;
else Second_low<=Second_low+1;
end if;
-------------------------------------------old design,too much latchs...--------------------------
-- if(second_count=59) then second_count<=0;
-- if(min_count=59) then min_count<=0;
-- if(hour_count=23) then hour_count<=0;
-- else hour_count<=hour_count+1;
-- end if;
-- --carry_from_min<='1';
-- else min_count<=min_count+1;
-- end if;
-- --carry_from_second<='1';
-- else second_count<=second_count+1;
-- end if;
end if;
end process;
-- Second_low<=to_unsigned(second_count mod 10,4);
-- Second_hig<=to_unsigned(second_count/10,4);
-- Min_low<=to_unsigned(min_count mod 10,4);
-- Min_hig<=to_unsigned(min_count/10,4);
-- Hour_low<=to_unsigned(hour_count mod 10,4);
-- Hour_hig<=to_unsigned(hour_count/10,4);
end architecture Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- Segment7Decoder.vhd
------------------------------------------------------------
--------------------------------------------------------------
library IEEE;
use ieee.numeric_bit.all;
entity Segment7Decoder is
port (bcd : in unsigned(3 downto 0); --BCD input
segment7 : out unsigned(6 downto 0) -- 7 bit decoded output.
);
end Segment7Decoder;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of Segment7Decoder is
begin
process (bcd)
BEGIN
case bcd is
when "0000"=> segment7 <="1000000"; -- '0'
when "0001"=> segment7 <="1111001"; -- '1'
when "0010"=> segment7 <="0100100"; -- '2'
when "0011"=> segment7 <="0110000"; -- '3'
when "0100"=> segment7 <="0011001"; -- '4'
when "0101"=> segment7 <="0010010"; -- '5'
when "0110"=> segment7 <="0000010"; -- '6'
when "0111"=> segment7 <="1111000"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0010000"; -- '9'
when "1010"=> segment7 <="0001000"; --'A'
when "1011"=> segment7 <="0000011"; --'b'
when "1100"=> segment7 <="0100111"; --'c'
when "1101"=> segment7 <="0100001"; --'d'
when "1110"=> segment7 <="0000110"; --'E'
when "1111"=> segment7 <="0001110"; --'f'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end process;
end Behavioral;
--------------------------------------------------------------
------------------------------------------------------------
-- View.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.numeric_bit.all;
entity View is
port(Clk_original,Reset,Ldn:in bit;
Din:in unsigned(15 downto 0);
hex0,hex1,hex2,hex3,hex4,hex5:out unsigned(7 downto 0));
end entity View;
architecture Behave of View is
component clock_signal_per_second is
port(clk:in bit;
second_output:buffer bit);
end component;
component Segment7Decoder is
port (bcd : in unsigned(3 downto 0); --BCD input
segment7 : out unsigned(6 downto 0) -- 7 bit decoded output.
);
end component;
component H24_Min60_Sec60_v2 is
port(Clk,Ldn,Reset:in bit;
Din :in unsigned(15 downto 0);
Qout:out unsigned(23 downto 0));
end component;
signal mid_second:bit;
signal Q:unsigned(23 downto 0);
alias Second_low:unsigned(3 downto 0) is Q(3 downto 0);
alias Second_hig:unsigned(3 downto 0) is Q(7 downto 4);
alias Min_low: unsigned(3 downto 0) is Q(11 downto 8);
alias Min_hig: unsigned(3 downto 0) is Q(15 downto 12);
alias Hour_low: unsigned(3 downto 0) is Q(19 downto 16);
alias Hour_hig: unsigned(3 downto 0) is Q(23 downto 20);
begin
hex0(0)<='1';
hex1(0)<='1';
hex2(0)<='1';
hex3(0)<='1';
hex4(0)<='1';
hex5(0)<='1';
High50Mhz:clock_signal_per_second port map(Clk_original,mid_second);
Core:H24_Min60_Sec60_v2 port map(mid_second,Ldn,Reset,Din,Q);
Hex0_display:Segment7Decoder port map(Second_low,hex0(7 downto 1));
Hex1_display:Segment7Decoder port map(Second_hig,hex1(7 downto 1));
Hex2_display:Segment7Decoder port map(Min_low, hex2(7 downto 1));
Hex3_display:Segment7Decoder port map(Min_hig,hex3(7 downto 1));
Hex4_display:Segment7Decoder port map(Hour_low,hex4(7 downto 1));
Hex5_display:Segment7Decoder port map(Hour_hig,hex5(7 downto 1));
end architecture Behave;
|
-- Acorn Electron for the Altera/Terasic DE1
--
-- Copright (c) 2015 David Banks
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- Generic top-level entity for Altera DE1 board
entity ElectronFpga_de1 is
port (
-- Clocks
CLOCK_24_0 : in std_logic;
CLOCK_24_1 : in std_logic;
CLOCK_27_0 : in std_logic;
CLOCK_27_1 : in std_logic;
CLOCK_50 : in std_logic;
EXT_CLOCK : in std_logic;
-- Switches
SW : in std_logic_vector(9 downto 0);
-- Buttons
KEY : in std_logic_vector(3 downto 0);
-- 7 segment displays
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
-- Red LEDs
LEDR : out std_logic_vector(9 downto 0);
-- Green LEDs
LEDG : out std_logic_vector(7 downto 0);
-- VGA
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_HS : out std_logic;
VGA_VS : out std_logic;
-- Serial
UART_RXD : in std_logic;
UART_TXD : out std_logic;
-- PS/2 Keyboard
PS2_CLK : in std_logic;
PS2_DAT : in std_logic;
-- I2C
I2C_SCLK : inout std_logic;
I2C_SDAT : inout std_logic;
-- Audio
AUD_XCK : out std_logic;
AUD_BCLK : out std_logic;
AUD_ADCLRCK : out std_logic;
AUD_ADCDAT : in std_logic;
AUD_DACLRCK : out std_logic;
AUD_DACDAT : out std_logic;
-- SRAM
SRAM_ADDR : out std_logic_vector(17 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
SRAM_CE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_WE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
-- SDRAM
DRAM_ADDR : out std_logic_vector(11 downto 0);
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_BA_0 : in std_logic;
DRAM_BA_1 : in std_logic;
DRAM_CAS_N : in std_logic;
DRAM_CKE : in std_logic;
DRAM_CLK : in std_logic;
DRAM_CS_N : in std_logic;
DRAM_LDQM : in std_logic;
DRAM_RAS_N : in std_logic;
DRAM_UDQM : in std_logic;
DRAM_WE_N : in std_logic;
-- Flash
FL_ADDR : out std_logic_vector(21 downto 0);
FL_DQ : in std_logic_vector(7 downto 0);
FL_RST_N : out std_logic;
FL_OE_N : out std_logic;
FL_WE_N : out std_logic;
FL_CE_N : out std_logic;
-- SD card (SPI mode)
SD_nCS : out std_logic;
SD_MOSI : out std_logic;
SD_SCLK : out std_logic;
SD_MISO : in std_logic;
-- GPIO
GPIO_0 : inout std_logic_vector(35 downto 0);
GPIO_1 : inout std_logic_vector(35 downto 0)
);
end entity;
architecture rtl of ElectronFpga_de1 is
-------------
-- Signals
-------------
signal clock_16 : std_logic;
signal clock_24 : std_logic;
signal clock_32 : std_logic;
signal clock_33 : std_logic;
signal clock_40 : std_logic;
signal i2s_lrclk : std_logic;
signal audio_l : std_logic;
signal audio_r : std_logic;
signal hard_reset_n : std_logic;
signal pll_reset : std_logic;
signal pll1_locked : std_logic;
signal pll2_locked : std_logic;
signal motor_led : std_logic;
signal caps_led : std_logic;
signal pcm_inl : std_logic_vector(15 downto 0);
signal pcm_inr : std_logic_vector(15 downto 0);
signal pcm_outl : std_logic_vector(15 downto 0);
signal pcm_outr : std_logic_vector(15 downto 0);
signal pcm_mono : std_logic_vector(8 downto 0);
signal pcm_sign : std_logic;
signal pcm_mag : std_logic_vector(7 downto 0);
signal ext_A : std_logic_vector (18 downto 0);
signal ext_Din : std_logic_vector (7 downto 0);
signal ext_Dout : std_logic_vector (7 downto 0);
signal ext_nCS : std_logic;
signal ext_nWE : std_logic;
signal ext_nOE : std_logic;
signal is_done : std_logic;
signal is_error : std_logic;
signal cpu_addr : std_logic_vector (15 downto 0);
signal cas_monitor : std_logic;
signal cas_in : std_logic;
signal cas_out : std_logic; -- currently not used
function hex_to_seven_seg(hex: std_logic_vector(3 downto 0))
return std_logic_vector
is begin
case hex is
-- abcdefg
when x"0" => return "0111111";
when x"1" => return "0000110";
when x"2" => return "1011011";
when x"3" => return "1001111";
when x"4" => return "1100110";
when x"5" => return "1101101";
when x"6" => return "1111101";
when x"7" => return "0000111";
when x"8" => return "1111111";
when x"9" => return "1101111";
when x"a" => return "1110111";
when x"b" => return "1111100";
when x"c" => return "0111001";
when x"d" => return "1011110";
when x"e" => return "1111001";
when x"f" => return "1110001";
when others => return "0000000";
end case;
end;
begin
--------------------------------------------------------
-- Clock Generation
--------------------------------------------------------
pll1: entity work.pll1
port map (
areset => pll_reset,
inclk0 => CLOCK_24_0,
c0 => clock_16,
c1 => clock_32,
c2 => clock_40,
locked => pll1_locked
);
pll2: entity work.pll2
port map (
areset => pll_reset,
inclk0 => CLOCK_50,
c0 => clock_33,
locked => pll2_locked
);
clock_24 <= CLOCK_24_0;
--------------------------------------------------------
-- Electron Core
--------------------------------------------------------
electron_core : entity work.ElectronFpga_core
generic map (
IncludeICEDebugger => false,
IncludeABRRegs => true,
IncludeJafaMode7 => true
)
port map (
clk_16M00 => clock_16,
clk_24M00 => clock_24,
clk_32M00 => clock_32,
clk_33M33 => clock_33,
clk_40M00 => clock_40,
hard_reset_n => hard_reset_n,
ps2_clk => PS2_CLK,
ps2_data => PS2_DAT,
video_red => VGA_R,
video_green => VGA_G,
video_blue => VGA_B,
video_vsync => VGA_VS,
video_hsync => VGA_HS,
audio_l => audio_l,
audio_r => audio_r,
ext_nOE => ext_nOE,
ext_nWE => ext_nWE,
ext_nCS => ext_nCS,
ext_A => ext_A,
ext_Dout => ext_Dout,
ext_Din => ext_Din,
SDMISO => SD_MISO,
SDSS => SD_nCS,
SDCLK => SD_SCLK,
SDMOSI => SD_MOSI,
caps_led => caps_led,
motor_led => motor_led,
cassette_in => cas_in,
cassette_out => cas_out,
vid_mode => SW(8 downto 7),
test => open,
avr_RxD => UART_RXD,
avr_TxD => UART_TXD,
cpu_addr => cpu_addr
);
--------------------------------------------------------
-- Power Up Reset Generation
--------------------------------------------------------
-- Asynchronous reset
-- PLL is reset by external reset switch
pll_reset <= not KEY(0);
hard_reset_n <= not (pll_reset or not pll1_locked or not pll2_locked);
--------------------------------------------------------
-- Audio DACs
--------------------------------------------------------
-- implement tape monitoring controlled by the motor and SW1
cas_monitor <= motor_led and SW(0);
pcm_outl <= "0" & audio_l & "00000000000000" when cas_monitor <= '0' else pcm_inl;
pcm_outr <= "0" & audio_r & "00000000000000" when cas_monitor <= '0' else pcm_inr;
i2s : entity work.i2s_intf
port map (
CLK => clock_32,
nRESET => hard_reset_n,
PCM_INL => pcm_inl,
PCM_INR => pcm_inr,
PCM_OUTL => pcm_outl,
PCM_OUTR => pcm_outr,
I2S_MCLK => AUD_XCK,
I2S_LRCLK => i2s_lrclk,
I2S_BCLK => AUD_BCLK,
I2S_DOUT => AUD_DACDAT,
I2S_DIN => AUD_ADCDAT
);
AUD_DACLRCK <= i2s_lrclk;
AUD_ADCLRCK <= i2s_lrclk;
i2c : entity work.i2c_loader
generic map (
log2_divider => 7
)
port map (
CLK => clock_32,
nRESET => hard_reset_n,
I2C_SCL => I2C_SCLK,
I2C_SDA => I2C_SDAT,
IS_DONE => is_done,
IS_ERROR => is_error
);
--------------------------------------------------------
-- Casette Input (from Line In)
--------------------------------------------------------
-- generate an 9 bit mono audio signal
pcm_mono <= (pcm_INL(15) & pcm_INL(15 downto 8)) + (pcm_INR(15) & pcm_INR(15 downto 8));
-- convert to sign and 8-bit magnitude
pcm_sign <= pcm_mono(8);
pcm_mag <= pcm_mono(7 downto 0) when pcm_mono(8) = '0' else (x"00" - pcm_mono(7 downto 0));
-- the casette input is driven from the sign of the mono signal
cas_in <= pcm_sign;
--------------------------------------------------------
-- LEDs
--------------------------------------------------------
-- Red LEDs
LEDR(0) <= caps_led;
LEDR(1) <= motor_led;
LEDR(3 downto 2) <= (others => '0');
LEDR(4) <= is_error;
LEDR(5) <= not is_done;
LEDR(9 downto 6) <= (others => '0');
-- Green LEDs used as a simple VU meter for the tape input level
-- driven from the magnitude of the mono line-in signal. Reversing
-- the bits gives a more natural left-to-right appearance.
LEDG(0) <= pcm_mag(7) when motor_led = '1' else '0';
LEDG(1) <= pcm_mag(6) when motor_led = '1' else '0';
LEDG(2) <= pcm_mag(5) when motor_led = '1' else '0';
LEDG(3) <= pcm_mag(4) when motor_led = '1' else '0';
LEDG(4) <= pcm_mag(3) when motor_led = '1' else '0';
LEDG(5) <= pcm_mag(2) when motor_led = '1' else '0';
LEDG(6) <= pcm_mag(1) when motor_led = '1' else '0';
LEDG(7) <= pcm_mag(0) when motor_led = '1' else '0';
-- HEX Displays (active low) show current processor address
HEX3 <= hex_to_seven_seg(cpu_addr(15 downto 12)) xor "1111111";
HEX2 <= hex_to_seven_seg(cpu_addr(11 downto 8)) xor "1111111";
HEX1 <= hex_to_seven_seg(cpu_addr( 7 downto 4)) xor "1111111";
HEX0 <= hex_to_seven_seg(cpu_addr( 3 downto 0)) xor "1111111";
--------------------------------------------------------
-- Map external memory bus to SRAM/FLASH
--------------------------------------------------------
-- 4MB FLASH Layout
-- 0x000000-0x05FFFF = BBC ROMs
-- 0x060000-0x07FFFF = Unused
-- 0x080000-0x0BFFFF = Electron ROMs
-- 0x0C0000-0x3FFFFF - Unused
-- ext_a(18) selects between FLASH and SRAM
-- 0x00000-0x3FFFF -> FLASH 0x080000-0x0BFFFF
-- 0x40000-0x7FFFF -> SRAM
ext_Dout <= SRAM_DQ(7 downto 0) when ext_a(18) = '1' else FL_DQ;
-- FLASH control signals
FL_RST_N <= hard_reset_n;
FL_CE_N <= ext_nCS;
FL_OE_N <= ext_nOE;
FL_WE_N <= '1';
-- Flash address change every at most every 16 cycles (2MHz)
-- 001 maps to FLASH address 0x080000
FL_ADDR <= "001" & ext_a;
-- SRAM control signals
SRAM_UB_N <= '1';
SRAM_LB_N <= '0';
SRAM_CE_N <= ext_nCS;
SRAM_OE_N <= ext_nOE;
-- Gate the WE with clock to provide more address/data hold time
SRAM_WE_N <= ext_nWE or not clock_16;
SRAM_ADDR <= ext_a(17 downto 0);
SRAM_DQ(15 downto 8) <= (others => 'Z');
SRAM_DQ(7 downto 0) <= ext_Din when ext_nWE = '0' else (others => 'Z');
-- Unused outputs
DRAM_ADDR <= (others => 'Z');
DRAM_DQ <= (others => 'Z');
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_acache
-- File: mmu_acache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Interface module between (MMU,I/D cache controllers) and Amba AHB
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.leon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmu_acache is
generic (
hindex : integer range 0 to NAHBMST-1 := 0;
ilinesize : integer range 4 to 8 := 4;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mcii : in memory_ic_in_type;
mcio : out memory_ic_out_type;
mcdi : in memory_dc_in_type;
mcdo : out memory_dc_out_type;
mcmmi : in memory_mm_in_type;
mcmmo : out memory_mm_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbso : in ahb_slv_out_vector;
hclken : in std_ulogic
);
end;
architecture rtl of mmu_acache is
type reg_type is record -- cache control register type
bg : std_logic; -- bus grant
bo : std_logic_vector(1 downto 0); -- bus owner
ba : std_logic; -- bus active
lb : std_ulogic; -- last burst cycle
retry : std_logic; -- retry/split pending
retry2 : std_ulogic; -- retry/split pending
werr : std_logic; -- write error
hlocken : std_ulogic; -- ready to perform locked transaction
hcache : std_logic; -- cacheable access
nba : std_ulogic;
nbo : std_logic_vector(1 downto 0); -- bus owner
end record;
type reg2_type is record
reqmsk : std_logic_vector(2 downto 0);
hclken2 : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : reg_type := (
bg => '0',
bo => (others => '0'),
ba => '0',
lb => '0',
retry => '0',
retry2 => '0',
werr => '0',
hlocken => '0',
hcache => '0',
nba => '0',
nbo => (others => '0')
);
constant R2RES : reg2_type := (
reqmsk => (others => '0'), hclken2 => '0'
);
constant L3DI :integer := GAISLER_LEON3
;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, L3DI, 0, LEON3_VERSION, 0),
others => zero32);
constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
function dec_fixed(haddr : std_logic_vector(3 downto 0);
cached : integer)
return std_ulogic is
begin
if (cached /= 0) then return ctbl(conv_integer(haddr(3 downto 0)));
else return('1'); end if;
end;
signal r, rin : reg_type;
signal r2, r2in : reg2_type;
begin
comb : process(ahbi, r, rst, mcii, mcdi, mcmmi, ahbso, hclken, r2)
variable v : reg_type;
variable v2 : reg2_type;
variable haddr : std_logic_vector(31 downto 0); -- address bus
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_logic; -- read/write
variable hlock : std_logic; -- bus lock
variable hsize : std_logic_vector(2 downto 0); -- transfer size
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable hwdata : std_logic_vector(31 downto 0); -- write data
variable hbusreq : std_logic; -- bus request
variable iready, dready, mmready : std_logic;
variable igrant, dgrant, mmgrant : std_logic;
variable iretry, dretry, mmretry : std_logic;
variable ihcache, dhcache, mmhcache, dec_hcache : std_logic;
variable imexc, dmexc, mmmexc : std_logic;
variable dreq : std_logic;
variable nbo : std_logic_vector(1 downto 0);
variable su, nb, bo_icache : std_ulogic;
variable scanen : std_ulogic;
variable vreqmsk: std_ulogic;
variable burst : std_ulogic;
begin
-- initialisation
htrans := HTRANS_IDLE;
v := r; v.werr := '0'; v2 := r2;
iready := '0'; dready := '0'; mmready := '0';
igrant := '0'; dgrant := '0'; mmgrant := '0';
imexc := '0'; dmexc := '0'; mmmexc := '0'; hlock := '0';
iretry := '0'; dretry := '0'; mmretry := '0';
ihcache := '0'; dhcache := '0'; mmhcache := '0'; su := '0';
if (r.bo = "00") then bo_icache := '1'; else bo_icache := '0'; end if;
haddr := (others => '0');
hwrite := '0';
hsize := (others => '0');
hlock := '0';
hburst := (others => '0');
if ahbi.hready = '1' then v.lb := '0'; end if;
v.retry2 := (r.retry or r.retry2) and not (r.ba and not r.retry);
vreqmsk := orv(r2.reqmsk);
-- generate AHB signals
dreq := mcdi.req;
hwdata := mcdi.data;
hbusreq := '0';
if (mcii.req = '1') and ((clk2x = 0) or (r2.reqmsk(2) = '1')) and (r.hlocken = '0') and
not (( ((r.ba and dreq) = '1') and (r.bo = "01")) or
( ((r.ba and mcmmi.req) = '1') and (r.bo = "10"))) then
nbo := "00";
hbusreq := '1'; burst := mcii.burst;
htrans := HTRANS_NONSEQ;
elsif (dreq = '1') and ((clk2x = 0) or (r2.reqmsk(1) = '1')) and
not (( ((r.ba and mcii.req) = '1') and (r.bo = "00")) or
( ((r.ba and mcmmi.req) = '1') and (r.bo = "10"))) then
nbo := "01";
hbusreq := '1'; burst := mcdi.burst;
if (not mcdi.lock or r.hlocken) = '1' then htrans := HTRANS_NONSEQ; end if;
elsif (mcmmi.req = '1') and ((clk2x = 0) or (r2.reqmsk(0) = '1')) and (r.hlocken = '0') and
not (( ((r.ba and mcii.req) = '1') and (r.bo = "00")) or
( ((r.ba and dreq) = '1') and (r.bo = "01"))) then
nbo := "10";
hbusreq := '1'; burst := '0';
htrans := HTRANS_NONSEQ;
else
nbo := "11"; burst := '0';
end if;
-- dont change bus master if we have started driving htrans
if r.nba = '1' then
nbo := r.nbo; hbusreq := '1'; htrans := HTRANS_NONSEQ;
end if;
-- dont change bus master on retry
if (r.retry2 and not r.ba) = '1' then
nbo := r.bo; hbusreq := '1'; htrans := HTRANS_NONSEQ;
end if;
dec_hcache := ahb_slv_dec_cache(mcdi.address, ahbso, cached);
if nbo = "10" then
haddr := mcmmi.address; hwrite := not mcmmi.read; hsize := '0' & mcmmi.size;
hlock := mcmmi.lock;
htrans := HTRANS_NONSEQ; hburst := HBURST_SINGLE;
if (mcmmi.req and r.bg and ahbi.hready and not r.retry) = '1'
then mmgrant := '1'; v.hcache := dec_fixed(haddr(31 downto 28), cached); end if;
elsif nbo = "00" then
haddr := mcii.address; hwrite := '0'; hsize := HSIZE_WORD; hlock := '0';
su := mcii.su;
if ((mcii.req and r.ba) = '1') and (r.bo = "00") and ((not r.retry) = '1') then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
if (((ilinesize = 4) and haddr(3 downto 2) = "10")
or ((ilinesize = 8) and haddr(4 downto 2) = "110")) and (ahbi.hready = '1')
then v.lb := '1'; end if;
end if;
if mcii.burst = '1' then hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if (mcii.req and r.bg and ahbi.hready and not r.retry) = '1'
then igrant := '1'; v.hcache := dec_fixed(haddr(31 downto 28), cached); end if;
elsif nbo = "01" then
haddr := mcdi.address; hwrite := not mcdi.read; hsize := '0' & mcdi.size;
hlock := mcdi.lock;
if mcdi.asi /= "1010" then su := '1'; else su := '0'; end if; --ASI_UDATA
if mcdi.burst = '1' then hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if ((dreq and r.ba) = '1') and (r.bo = "01") and ((not r.retry) = '1') then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
hburst := HBURST_INCR;
end if;
if (dreq and r.bg and ahbi.hready and not r.retry) = '1' then
dgrant := (not mcdi.lock or r.hlocken) or (r.retry2 and (not r.bo(1) and r.bo(0)));
v.hcache := dec_hcache;
end if;
end if;
if (hclken = '1') or (clk2x = 0) then
if (r.ba = '1') and ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT))
then v.retry := not ahbi.hready; else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if r.bo = "10" then
hwdata := mcmmi.data;
if r.ba = '1' then
mmhcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => mmready := '1';
when HRESP_RETRY | HRESP_SPLIT=> mmretry := '1';
when others => mmready := '1'; mmmexc := '1'; v.werr := not mcmmi.read;
end case;
end if;
end if;
elsif r.bo = "00" then
if r.ba = '1' then
ihcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => iready := '1';
when HRESP_RETRY | HRESP_SPLIT=> iretry := '1';
when others => iready := '1'; imexc := '1';
end case;
end if;
end if;
elsif r.bo = "01" then
if r.ba = '1' then
dhcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => dready := '1';
when HRESP_RETRY | HRESP_SPLIT=> dretry := '1';
when others => dready := '1'; dmexc := '1'; v.werr := not mcdi.read;
end case;
end if;
end if;
hlock := mcdi.lock or ((r.retry or (r.retry2 and not r.ba)) and r.hlocken);
end if;
if nbo = "01" and ((hsize = "011") or ((mcdi.read and mcdi.cache) = '1')) then
hsize := "010";
end if;
if (r.bo = "01") and (hlock = '1') then nbo := "01"; end if;
if ahbi.hready = '1' then
if r.retry = '0' then v.bo := nbo; end if;
v.bg := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else v.ba := '0'; end if;
v.hlocken := hlock and ahbi.hgrant(hindex);
if (clk2x /= 0) then
igrant := igrant and vreqmsk;
dgrant := dgrant and vreqmsk;
mmgrant := mmgrant and vreqmsk;
if (r.bo = nbo) then v.ba := v.ba and vreqmsk; end if;
end if;
end if;
if hburst = HBURST_SINGLE then nb := '1'; else nb := '0'; end if;
v.nbo := nbo; v.nba := orv(htrans) and not v.ba;
-- parity generation
if (clk2x /= 0) then
v2.hclken2 := hclken;
if hclken = '1' then
v2.reqmsk := mcii.req & mcdi.req & mcmmi.req;
if (clk2x > 8) and (r2.hclken2 = '1') then v2.reqmsk := "111"; end if;
end if;
end if;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.bg := '0'; v.bo := "00"; v.ba := '0'; v.retry := '0'; v.werr := '0'; v.lb := '0';
v.hcache := '0'; v.hlocken := '0'; v.nba := '0'; v.nbo := "00";
v.retry2 := '0';
end if;
-- drive ports
ahbo.haddr <= haddr ;
ahbo.htrans <= htrans;
-- ahbo.hbusreq <= hbusreq and not r.lb and not ((((not bo_icache) and r.ba) or nb) and r.bg);
-- ahbo.hbusreq <= hbusreq and not r.lb and not((not burst) and r.bg);
ahbo.hbusreq <= hbusreq and (not r.lb or orv(nbo)) and (burst or not r.bg);
ahbo.hwdata <= ahbdrivedata(hwdata);
ahbo.hlock <= hlock;
ahbo.hwrite <= hwrite;
ahbo.hsize <= hsize;
ahbo.hburst <= hburst;
ahbo.hindex <= hindex;
if nbo = "00" then ahbo.hprot <= "11" & su & '0';
else ahbo.hprot <= "11" & su & '1'; end if;
mcio.grant <= igrant;
mcio.ready <= iready;
mcio.mexc <= imexc;
mcio.retry <= iretry;
mcio.cache <= ihcache;
mcdo.grant <= dgrant;
mcdo.ready <= dready;
mcdo.mexc <= dmexc;
mcdo.retry <= dretry;
mcdo.werr <= r.werr;
mcdo.cache <= dhcache;
mcdo.ba <= r.ba;
mcdo.bg <= r.bg and not v.bo(1);
mcmmo.grant <= mmgrant;
mcmmo.ready <= mmready;
mcmmo.mexc <= mmmexc;
mcmmo.retry <= mmretry;
mcmmo.werr <= r.werr;
mcmmo.cache <= mmhcache;
rin <= v; r2in <= v2;
end process;
mcio.data <= ahbreadword(ahbi.hrdata);
mcdo.data <= ahbreadword(ahbi.hrdata);
mcmmo.data <= ahbreadword(ahbi.hrdata);
ahbo.hirq <= (others => '0');
ahbo.hconfig <= hconfig;
reg : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and (rst = '0') then r <= RRES; end if;
end if;
end process;
reg2gen : if (clk2x /= 0) generate
reg2 : process(clk)
begin
if rising_edge(clk) then
r2 <= r2in;
if RESET_ALL and (rst = '0') then r2 <= R2RES; end if;
end if;
end process;
end generate;
noreg2gen : if (clk2x = 0) generate
r2.reqmsk <= "000";
end generate;
end;
|
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: ReaderControlReg0
-- Date:2011-11-10
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ReaderControlReg1 is
port (
data_out : out std_logic_vector (15 downto 0);
------------------ gpib --------------------
-- num of bytes available in fifo
bytes_available_in_fifo : in std_logic_vector (10 downto 0)
);
end ReaderControlReg1;
architecture arch of ReaderControlReg1 is
begin
data_out(10 downto 0) <= bytes_available_in_fifo(10 downto 0);
data_out(15 downto 11) <= "00000";
end arch;
|
-------------------------------------------------------------------------------
-- Address Decoder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_address_decoder.vhd
-- Version: v3.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
library axi_quad_spi_v3_2;
use axi_quad_spi_v3_2.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI4_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI4_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex7" -- "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity qspi_address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of qspi_address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI4_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_quad_spi_v3_2.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_quad_spi_v3_2.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture imp;
|
entity external is
end entity;
architecture test of external is
begin
main: process is
variable i : integer;
begin
i := <<signal foo.bar : integer>>; -- OK
i := << constant x.y.z : integer >>; -- OK
i := <<variable aye.bee : integer>>; -- OK
i := << constant .x.y.z : integer>>; -- OK
i := << constant ^.^.foo : integer >>; -- OK
i := << constant @work.pack.foo : integer >>; -- OK
i := << signal g(0).x(1).baz : integer >>; -- OK
end process;
p2: process is
alias sig is <<signal i_test.sig : bit_vector(1 downto 0)>>;
begin
sig(0) <= '1'; -- OK
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MC6808CpuMonGODIL.vhd
-- /___/ /\ Timestamp : 24/10/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MC6808CpuMonGODIL
--Device: XC3S250E/XC3S500E
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MC6809CpuMonGODIL is
generic (
num_comparators : integer := 8; -- default value correct for GODIL
avr_prog_mem_size : integer := 1024 * 9 -- default value correct for GODIL
);
port (
clock49 : in std_logic;
-- A locally generated test clock
-- 1.8457 MHz in E Mode (6809E) so it can drive E (PIN34)
-- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
clock_test : out std_logic;
-- 6809/6809E mode selection
-- Jumper is between pins B1 and D1
-- Jumper off is 6809 mode, where a 4x clock should be fed into EXTAL (PIN38)
-- Jumper on is 6909E mode, where a 1x clock should be fed into E (PIN34)
EMode_n : in std_logic;
--6809 Signals
PIN33 : inout std_logic;
PIN34 : inout std_logic;
PIN35 : inout std_logic;
PIN36 : inout std_logic;
PIN38 : inout std_logic;
PIN39 : in std_logic;
-- Signals common to both 6809 and 6809E
RES_n : in std_logic;
NMI_n : in std_logic;
IRQ_n : in std_logic;
FIRQ_n : in std_logic;
HALT_n : in std_logic;
BS : out std_logic;
BA : out std_logic;
R_W_n : out std_logic;
Addr : out std_logic_vector(15 downto 0);
Data : inout std_logic_vector(7 downto 0);
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- GODIL Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- GODIL LEDs
led3 : out std_logic;
led6 : out std_logic;
led8 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic;
-- Debugging signals
test1 : out std_logic;
test2 : out std_logic
);
end MC6809CpuMonGODIL;
architecture behavioral of MC6809CpuMonGODIL is
signal clk_count : std_logic_vector(1 downto 0);
signal quadrature : std_logic_vector(1 downto 0);
signal clock7_3728 : std_logic;
signal sw_reset_avr : std_logic;
signal sw_reset_cpu : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
signal E : std_logic;
signal Q : std_logic;
signal DMA_n_BREQ_n : std_logic;
signal MRDY : std_logic;
signal TSC : std_logic;
signal LIC : std_logic;
signal AVMA : std_logic;
signal BUSY : std_logic;
signal XTAL : std_logic;
signal EXTAL : std_logic;
begin
-- Generics allows polarity of switches/LEDs to be tweaked from the project file
sw_reset_cpu <= sw1;
sw_reset_avr <= not sw2;
led3 <= not led_trig0;
led6 <= not led_trig1;
led8 <= not led_bkpt;
wrapper : entity work.MC6809CpuMon
generic map (
ClkMult => 10,
ClkDiv => 31,
ClkPer => 20.345,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
-- Fast clock
clock => clock49,
-- Quadrature clocks
E => E,
Q => Q,
--6809 Signals
DMA_n_BREQ_n => DMA_n_BREQ_n,
-- 6809E Sig
TSC => TSC,
LIC => LIC,
AVMA => AVMA,
BUSY => BUSY,
-- Signals common to both 6809 and 6809E
RES_n => RES_n,
NMI_n => NMI_n,
IRQ_n => IRQ_n,
FIRQ_n => FIRQ_n,
HALT_n => HALT_n,
BS => BS,
BA => BA,
R_W_n => R_W_n,
Addr => Addr,
Data => Data,
-- External trigger inputs
trig => trig,
-- Serial Console
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
-- Switches
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
-- OHO_DY1 connected to test connector
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,
-- Debugging signals
test1 => test1,
test2 => test2
);
-- Pins whose functions are dependent on "E" mode
PIN33 <= BUSY when EMode_n = '0' else 'Z';
DMA_n_BREQ_n <= '1' when EMode_n = '0' else PIN33;
PIN34 <= 'Z' when EMode_n = '0' else E;
E <= PIN34 when EMode_n = '0' else quadrature(1);
PIN35 <= 'Z' when EMode_n = '0' else Q;
Q <= PIN35 when EMode_n = '0' else quadrature(0);
PIN36 <= AVMA when EMode_n = '0' else 'Z';
MRDY <= '1' when EMode_n = '0' else PIN36;
PIN38 <= LIC when EMode_n = '0' else 'Z';
EXTAL <= '0' when EMode_n = '0' else PIN38;
TSC <= PIN39 when EMode_n = '0' else '0';
XTAL <= '0' when EMode_n = '0' else PIN39;
-- A locally generated test clock
-- 1.8457 MHz in E Mode (6809E) so it can drive E (PIN34)
-- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
clock_test <= clk_count(1) when EMode_n = '0' else clock7_3728;
-- Quadrature clock generator, unused in 6809E mode
quadrature_gen : process(EXTAL)
begin
if rising_edge(EXTAL) then
if (MRDY = '1') then
if (quadrature = "00") then
quadrature <= "01";
elsif (quadrature = "01") then
quadrature <= "11";
elsif (quadrature = "11") then
quadrature <= "10";
else
quadrature <= "00";
end if;
end if;
end if;
end process;
-- Seperate piece of circuitry that emits a 7.3728MHz clock
inst_dcm1 : entity work.DCM1 port map(
CLKIN_IN => clock49,
CLK0_OUT => clock7_3728,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
clk_gen : process(clock7_3728)
begin
if rising_edge(clock7_3728) then
clk_count <= clk_count + 1;
end if;
end process;
end behavioral;
|
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MC6808CpuMonGODIL.vhd
-- /___/ /\ Timestamp : 24/10/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MC6808CpuMonGODIL
--Device: XC3S250E/XC3S500E
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MC6809CpuMonGODIL is
generic (
num_comparators : integer := 8; -- default value correct for GODIL
avr_prog_mem_size : integer := 1024 * 9 -- default value correct for GODIL
);
port (
clock49 : in std_logic;
-- A locally generated test clock
-- 1.8457 MHz in E Mode (6809E) so it can drive E (PIN34)
-- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
clock_test : out std_logic;
-- 6809/6809E mode selection
-- Jumper is between pins B1 and D1
-- Jumper off is 6809 mode, where a 4x clock should be fed into EXTAL (PIN38)
-- Jumper on is 6909E mode, where a 1x clock should be fed into E (PIN34)
EMode_n : in std_logic;
--6809 Signals
PIN33 : inout std_logic;
PIN34 : inout std_logic;
PIN35 : inout std_logic;
PIN36 : inout std_logic;
PIN38 : inout std_logic;
PIN39 : in std_logic;
-- Signals common to both 6809 and 6809E
RES_n : in std_logic;
NMI_n : in std_logic;
IRQ_n : in std_logic;
FIRQ_n : in std_logic;
HALT_n : in std_logic;
BS : out std_logic;
BA : out std_logic;
R_W_n : out std_logic;
Addr : out std_logic_vector(15 downto 0);
Data : inout std_logic_vector(7 downto 0);
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- GODIL Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- GODIL LEDs
led3 : out std_logic;
led6 : out std_logic;
led8 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic;
-- Debugging signals
test1 : out std_logic;
test2 : out std_logic
);
end MC6809CpuMonGODIL;
architecture behavioral of MC6809CpuMonGODIL is
signal clk_count : std_logic_vector(1 downto 0);
signal quadrature : std_logic_vector(1 downto 0);
signal clock7_3728 : std_logic;
signal sw_reset_avr : std_logic;
signal sw_reset_cpu : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
signal E : std_logic;
signal Q : std_logic;
signal DMA_n_BREQ_n : std_logic;
signal MRDY : std_logic;
signal TSC : std_logic;
signal LIC : std_logic;
signal AVMA : std_logic;
signal BUSY : std_logic;
signal XTAL : std_logic;
signal EXTAL : std_logic;
begin
-- Generics allows polarity of switches/LEDs to be tweaked from the project file
sw_reset_cpu <= sw1;
sw_reset_avr <= not sw2;
led3 <= not led_trig0;
led6 <= not led_trig1;
led8 <= not led_bkpt;
wrapper : entity work.MC6809CpuMon
generic map (
ClkMult => 10,
ClkDiv => 31,
ClkPer => 20.345,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
-- Fast clock
clock => clock49,
-- Quadrature clocks
E => E,
Q => Q,
--6809 Signals
DMA_n_BREQ_n => DMA_n_BREQ_n,
-- 6809E Sig
TSC => TSC,
LIC => LIC,
AVMA => AVMA,
BUSY => BUSY,
-- Signals common to both 6809 and 6809E
RES_n => RES_n,
NMI_n => NMI_n,
IRQ_n => IRQ_n,
FIRQ_n => FIRQ_n,
HALT_n => HALT_n,
BS => BS,
BA => BA,
R_W_n => R_W_n,
Addr => Addr,
Data => Data,
-- External trigger inputs
trig => trig,
-- Serial Console
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
-- Switches
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
-- OHO_DY1 connected to test connector
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,
-- Debugging signals
test1 => test1,
test2 => test2
);
-- Pins whose functions are dependent on "E" mode
PIN33 <= BUSY when EMode_n = '0' else 'Z';
DMA_n_BREQ_n <= '1' when EMode_n = '0' else PIN33;
PIN34 <= 'Z' when EMode_n = '0' else E;
E <= PIN34 when EMode_n = '0' else quadrature(1);
PIN35 <= 'Z' when EMode_n = '0' else Q;
Q <= PIN35 when EMode_n = '0' else quadrature(0);
PIN36 <= AVMA when EMode_n = '0' else 'Z';
MRDY <= '1' when EMode_n = '0' else PIN36;
PIN38 <= LIC when EMode_n = '0' else 'Z';
EXTAL <= '0' when EMode_n = '0' else PIN38;
TSC <= PIN39 when EMode_n = '0' else '0';
XTAL <= '0' when EMode_n = '0' else PIN39;
-- A locally generated test clock
-- 1.8457 MHz in E Mode (6809E) so it can drive E (PIN34)
-- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
clock_test <= clk_count(1) when EMode_n = '0' else clock7_3728;
-- Quadrature clock generator, unused in 6809E mode
quadrature_gen : process(EXTAL)
begin
if rising_edge(EXTAL) then
if (MRDY = '1') then
if (quadrature = "00") then
quadrature <= "01";
elsif (quadrature = "01") then
quadrature <= "11";
elsif (quadrature = "11") then
quadrature <= "10";
else
quadrature <= "00";
end if;
end if;
end if;
end process;
-- Seperate piece of circuitry that emits a 7.3728MHz clock
inst_dcm1 : entity work.DCM1 port map(
CLKIN_IN => clock49,
CLK0_OUT => clock7_3728,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
clk_gen : process(clock7_3728)
begin
if rising_edge(clock7_3728) then
clk_count <= clk_count + 1;
end if;
end process;
end behavioral;
|
-- This is an implementation of ieee.std_logic_1164 based only on the
-- specifications. This file is part of GHDL.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING3. If not see
-- <http://www.gnu.org/licenses/>.
-- This package is valid for VHDL version until but not including 2008.
-- For VHDL87, the functions xnor should be removed.
package std_logic_1164 is
-- Unresolved logic state.
type std_ulogic is
('U', -- Uninitialized, this is also the default value.
'X', -- Unknown / conflict value (forcing level).
'0', -- 0 (forcing level).
'1', -- 1 (forcing level).
'Z', -- High impedance.
'W', -- Unknown / conflict (weak level).
'L', -- 0 (weak level).
'H', -- 1 (weak level).
'-' -- Don't care.
);
-- Vector of logic state.
type std_ulogic_vector is array (natural range <>) of std_ulogic;
-- Resolution function.
-- If S is empty, returns 'Z'.
-- If S has one element, return the element.
-- Otherwise, 'U' is the strongest.
-- then 'X'
-- then '0' and '1'
-- then 'W'
-- then 'H' and 'L'
-- then 'Z'.
function resolved (s : std_ulogic_vector) return std_ulogic;
-- Resolved logic state.
subtype std_logic is resolved std_ulogic;
-- Vector of std_logic.
type std_logic_vector is array (natural range <>) of std_logic;
-- Subtypes of std_ulogic. The names give the values.
subtype X01 is resolved std_ulogic range 'X' to '1';
subtype X01Z is resolved std_ulogic range 'X' to 'Z';
subtype UX01 is resolved std_ulogic range 'U' to '1';
subtype UX01Z is resolved std_ulogic range 'U' to 'Z';
-- Logical operators.
-- For logical operations, the inputs are first normalized to UX01:
-- 0 and L are normalized to 0, 1 and 1 are normalized to 1, U isnt changed,
-- all other states are normalized to X.
-- Then the classical electric rules are followed.
function "and" (l, r : std_ulogic) return UX01;
function "nand" (l, r : std_ulogic) return UX01;
function "or" (l, r : std_ulogic) return UX01;
function "nor" (l, r : std_ulogic) return UX01;
function "xor" (l, r : std_ulogic) return UX01;
function "xnor" (l, r : std_ulogic) return UX01;
function "not" (l : std_ulogic) return UX01;
-- Logical operators for vectors.
-- An assertion of severity failure fails if the length of L and R aren't
-- equal. The result range is 1 to L'Length.
function "and" (l, r : std_logic_vector) return std_logic_vector;
function "nand" (l, r : std_logic_vector) return std_logic_vector;
function "or" (l, r : std_logic_vector) return std_logic_vector;
function "nor" (l, r : std_logic_vector) return std_logic_vector;
function "xor" (l, r : std_logic_vector) return std_logic_vector;
function "xnor" (l, r : std_logic_vector) return std_logic_vector;
function "not" (l : std_logic_vector) return std_logic_vector;
function "and" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "nand" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "or" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "nor" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "xor" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "xnor" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "not" (l : std_ulogic_vector) return std_ulogic_vector;
-- Conversion functions.
-- The result range (for vectors) is S'Length - 1 downto 0.
-- XMAP is return for values not in '0', '1', 'L', 'H'.
function to_bit (s : std_ulogic; xmap : bit := '0') return bit;
function to_bitvector (s : std_logic_vector; xmap : bit := '0')
return bit_vector;
function to_bitvector (s : std_ulogic_vector; xmap : bit := '0')
return bit_vector;
function to_stdulogic (b : bit) return std_ulogic;
function to_stdlogicvector (b : bit_vector) return std_logic_vector;
function to_stdlogicvector (b : std_ulogic_vector) return std_logic_vector;
function to_stdulogicvector (b : bit_vector) return std_ulogic_vector;
function to_stdulogicvector (b : std_logic_vector) return std_ulogic_vector;
-- Normalization.
-- The result range (for vectors) is 1 to S'Length.
function to_X01 (s : std_logic_vector) return std_logic_vector;
function to_X01 (s : std_ulogic_vector) return std_ulogic_vector;
function to_X01 (s : std_ulogic) return X01;
function to_X01 (b : bit_vector) return std_logic_vector;
function to_X01 (b : bit_vector) return std_ulogic_vector;
function to_X01 (b : bit) return X01;
function to_X01Z (s : std_logic_vector) return std_logic_vector;
function to_X01Z (s : std_ulogic_vector) return std_ulogic_vector;
function to_X01Z (s : std_ulogic) return X01Z;
function to_X01Z (b : bit_vector) return std_logic_vector;
function to_X01Z (b : bit_vector) return std_ulogic_vector;
function to_X01Z (b : bit) return X01Z;
function to_UX01 (s : std_logic_vector) return std_logic_vector;
function to_UX01 (s : std_ulogic_vector) return std_ulogic_vector;
function to_UX01 (s : std_ulogic) return UX01;
function to_UX01 (b : bit_vector) return std_logic_vector;
function to_UX01 (b : bit_vector) return std_ulogic_vector;
function to_UX01 (b : bit) return UX01;
-- Edge detection.
-- An edge is detected in case of event on s, and X01 normalized value
-- rises from 0 to 1 or falls from 1 to 0.
function rising_edge (signal s : std_ulogic) return boolean;
function falling_edge (signal s : std_ulogic) return boolean;
-- Test for unknown. Only 0, 1, L and H are known values.
function is_X (s : std_ulogic_vector) return boolean;
function is_X (s : std_logic_vector) return boolean;
function is_X (s : std_ulogic) return boolean;
end std_logic_1164;
|
-- This is an implementation of ieee.std_logic_1164 based only on the
-- specifications. This file is part of GHDL.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING3. If not see
-- <http://www.gnu.org/licenses/>.
-- This package is valid for VHDL version until but not including 2008.
-- For VHDL87, the functions xnor should be removed.
package std_logic_1164 is
-- Unresolved logic state.
type std_ulogic is
('U', -- Uninitialized, this is also the default value.
'X', -- Unknown / conflict value (forcing level).
'0', -- 0 (forcing level).
'1', -- 1 (forcing level).
'Z', -- High impedance.
'W', -- Unknown / conflict (weak level).
'L', -- 0 (weak level).
'H', -- 1 (weak level).
'-' -- Don't care.
);
-- Vector of logic state.
type std_ulogic_vector is array (natural range <>) of std_ulogic;
-- Resolution function.
-- If S is empty, returns 'Z'.
-- If S has one element, return the element.
-- Otherwise, 'U' is the strongest.
-- then 'X'
-- then '0' and '1'
-- then 'W'
-- then 'H' and 'L'
-- then 'Z'.
function resolved (s : std_ulogic_vector) return std_ulogic;
-- Resolved logic state.
subtype std_logic is resolved std_ulogic;
-- Vector of std_logic.
type std_logic_vector is array (natural range <>) of std_logic;
-- Subtypes of std_ulogic. The names give the values.
subtype X01 is resolved std_ulogic range 'X' to '1';
subtype X01Z is resolved std_ulogic range 'X' to 'Z';
subtype UX01 is resolved std_ulogic range 'U' to '1';
subtype UX01Z is resolved std_ulogic range 'U' to 'Z';
-- Logical operators.
-- For logical operations, the inputs are first normalized to UX01:
-- 0 and L are normalized to 0, 1 and 1 are normalized to 1, U isnt changed,
-- all other states are normalized to X.
-- Then the classical electric rules are followed.
function "and" (l, r : std_ulogic) return UX01;
function "nand" (l, r : std_ulogic) return UX01;
function "or" (l, r : std_ulogic) return UX01;
function "nor" (l, r : std_ulogic) return UX01;
function "xor" (l, r : std_ulogic) return UX01;
function "xnor" (l, r : std_ulogic) return UX01;
function "not" (l : std_ulogic) return UX01;
-- Logical operators for vectors.
-- An assertion of severity failure fails if the length of L and R aren't
-- equal. The result range is 1 to L'Length.
function "and" (l, r : std_logic_vector) return std_logic_vector;
function "nand" (l, r : std_logic_vector) return std_logic_vector;
function "or" (l, r : std_logic_vector) return std_logic_vector;
function "nor" (l, r : std_logic_vector) return std_logic_vector;
function "xor" (l, r : std_logic_vector) return std_logic_vector;
function "xnor" (l, r : std_logic_vector) return std_logic_vector;
function "not" (l : std_logic_vector) return std_logic_vector;
function "and" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "nand" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "or" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "nor" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "xor" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "xnor" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "not" (l : std_ulogic_vector) return std_ulogic_vector;
-- Conversion functions.
-- The result range (for vectors) is S'Length - 1 downto 0.
-- XMAP is return for values not in '0', '1', 'L', 'H'.
function to_bit (s : std_ulogic; xmap : bit := '0') return bit;
function to_bitvector (s : std_logic_vector; xmap : bit := '0')
return bit_vector;
function to_bitvector (s : std_ulogic_vector; xmap : bit := '0')
return bit_vector;
function to_stdulogic (b : bit) return std_ulogic;
function to_stdlogicvector (b : bit_vector) return std_logic_vector;
function to_stdlogicvector (b : std_ulogic_vector) return std_logic_vector;
function to_stdulogicvector (b : bit_vector) return std_ulogic_vector;
function to_stdulogicvector (b : std_logic_vector) return std_ulogic_vector;
-- Normalization.
-- The result range (for vectors) is 1 to S'Length.
function to_X01 (s : std_logic_vector) return std_logic_vector;
function to_X01 (s : std_ulogic_vector) return std_ulogic_vector;
function to_X01 (s : std_ulogic) return X01;
function to_X01 (b : bit_vector) return std_logic_vector;
function to_X01 (b : bit_vector) return std_ulogic_vector;
function to_X01 (b : bit) return X01;
function to_X01Z (s : std_logic_vector) return std_logic_vector;
function to_X01Z (s : std_ulogic_vector) return std_ulogic_vector;
function to_X01Z (s : std_ulogic) return X01Z;
function to_X01Z (b : bit_vector) return std_logic_vector;
function to_X01Z (b : bit_vector) return std_ulogic_vector;
function to_X01Z (b : bit) return X01Z;
function to_UX01 (s : std_logic_vector) return std_logic_vector;
function to_UX01 (s : std_ulogic_vector) return std_ulogic_vector;
function to_UX01 (s : std_ulogic) return UX01;
function to_UX01 (b : bit_vector) return std_logic_vector;
function to_UX01 (b : bit_vector) return std_ulogic_vector;
function to_UX01 (b : bit) return UX01;
-- Edge detection.
-- An edge is detected in case of event on s, and X01 normalized value
-- rises from 0 to 1 or falls from 1 to 0.
function rising_edge (signal s : std_ulogic) return boolean;
function falling_edge (signal s : std_ulogic) return boolean;
-- Test for unknown. Only 0, 1, L and H are known values.
function is_X (s : std_ulogic_vector) return boolean;
function is_X (s : std_logic_vector) return boolean;
function is_X (s : std_ulogic) return boolean;
end std_logic_1164;
|
-------------------------------------------------------------------------------
-- Title : An Wishbone delay buffer
-- Project : General Cores Library (gencores)
-------------------------------------------------------------------------------
-- File : xwb_crossbar.vhd
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2013-12-16
-- Last update: 2013-12-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- Adds a register between two wishbone interfaces.
-- Useful to improve timing closure when placed between crossbars.
-- Be warned: it reduces the available bandwidth by a half.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011 GSI / Wesley W. Terpstra
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-12-16 1.0 wterpstra V1
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity xwb_register_link is
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out);
end xwb_register_link;
architecture rtl of xwb_register_link is
signal r_slave : t_wishbone_slave_out;
signal r_master : t_wishbone_master_out;
begin
slave_o <= r_slave;
master_o <= r_master;
main : process(clk_sys_i, rst_n_i) is
begin
if rst_n_i = '0' then
r_slave <= cc_dummy_slave_out;
r_master <= cc_dummy_master_out;
r_slave.stall <= '0';
elsif rising_edge(clk_sys_i) then
-- no flow control on ack/err
r_slave <= master_i;
-- either we are accepting data (stb=0) or pushing data (stb=1)
if r_master.stb = '0' then
r_master <= slave_i;
r_master.stb <= slave_i.cyc and slave_i.stb;
r_slave.stall <= slave_i.cyc and slave_i.stb;
else
r_master.stb <= r_master.stb and master_i.stall;
r_slave.stall <= r_master.stb and master_i.stall;
end if;
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_mb_700a is
generic (
g_acia : boolean := true;
g_eeprom : boolean := false;
g_dual_drive : boolean := false );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout unsigned(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- memory
SDRAM_A : out std_logic_vector(12 downto 0); -- DRAM A
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- LED Interface
LED_CLK : out std_logic;
LED_DATA : out std_logic;
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end entity;
architecture structural of ultimate_mb_700a is
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
-- signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
signal RSTn_out : std_logic;
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- Slot
signal slot_addr_o : unsigned(15 downto 0);
signal slot_addr_tl : std_logic;
signal slot_addr_th : std_logic;
signal slot_data_o : std_logic_vector(7 downto 0);
signal slot_data_t : std_logic;
signal slot_rwn_o : std_logic;
signal irq_oc, nmi_oc, rst_oc, dma_oc, exrom_oc, game_oc : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- Cassette
signal c2n_read_in : std_logic;
signal c2n_write_in : std_logic;
signal c2n_read_out : std_logic;
signal c2n_write_out : std_logic;
signal c2n_read_en : std_logic;
signal c2n_write_en : std_logic;
signal c2n_sense_in : std_logic;
signal c2n_sense_out : std_logic;
signal c2n_motor_in : std_logic;
signal c2n_motor_out : std_logic;
-- Parallel cable connection
signal drv_track_is_0 : std_logic;
signal drv_via1_port_a_o : std_logic_vector(7 downto 0);
signal drv_via1_port_a_i : std_logic_vector(7 downto 0);
signal drv_via1_port_a_t : std_logic_vector(7 downto 0);
signal drv_via1_ca2_o : std_logic;
signal drv_via1_ca2_i : std_logic;
signal drv_via1_ca2_t : std_logic;
signal drv_via1_cb1_o : std_logic;
signal drv_via1_cb1_i : std_logic;
signal drv_via1_cb1_t : std_logic;
-- Audio outputs
signal audio_left : signed(18 downto 0);
signal audio_right : signed(18 downto 0);
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3a_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_clock_2x => sys_clock_2x );
i_logic: entity work.ultimate_logic_32
generic map (
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => g_dual_drive,
g_mm_drive => false,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => not g_dual_drive,
g_8voices => false,
g_hardware_iec => true,
g_c2n_streamer => true,
g_c2n_recorder => g_dual_drive,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => false,
g_usb_host2 => true,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false,
g_sdcard => true,
g_eeprom => g_eeprom,
g_sampler => not g_dual_drive,
g_acia => g_acia )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
BUFFER_ENn => BUFFER_ENn,
phi2_i => PHI2,
dotclk_i => DOTCLK,
rstn_i => RSTn,
rstn_o => RSTn_out,
slot_addr_o => slot_addr_o,
slot_addr_i => SLOT_ADDR,
slot_addr_tl=> slot_addr_tl,
slot_addr_th=> slot_addr_th,
slot_data_o => slot_data_o,
slot_data_i => SLOT_DATA,
slot_data_t => slot_data_t,
rwn_i => RWn,
rwn_o => slot_rwn_o,
exromn_i => EXROMn,
exromn_o => exrom_oc,
gamen_i => GAMEn,
gamen_o => game_oc,
irqn_i => IRQn,
irqn_o => irq_oc,
nmin_i => NMIn,
nmin_o => nmi_oc,
ba_i => BA,
dman_o => dma_oc,
romhn_i => ROMHn,
romln_i => ROMLn,
io1n_i => IO1n,
io2n_i => IO2n,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- Audio outputs
audio_left => audio_left,
audio_right => audio_right,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
-- Parallel cable pins
drv_track_is_0 => drv_track_is_0,
drv_via1_port_a_o => drv_via1_port_a_o,
drv_via1_port_a_i => drv_via1_port_a_i,
drv_via1_port_a_t => drv_via1_port_a_t,
drv_via1_ca2_o => drv_via1_ca2_o,
drv_via1_ca2_i => drv_via1_ca2_i,
drv_via1_ca2_t => drv_via1_ca2_t,
drv_via1_cb1_o => drv_via1_cb1_o,
drv_via1_cb1_i => drv_via1_cb1_i,
drv_via1_cb1_t => drv_via1_cb1_t,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- LED interface
LED_CLK => LED_CLK,
LED_DATA => LED_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
c2n_read_in => c2n_read_in,
c2n_write_in => c2n_write_in,
c2n_read_out => c2n_read_out,
c2n_write_out => c2n_write_out,
c2n_read_en => c2n_read_en,
c2n_write_en => c2n_write_en,
c2n_sense_in => c2n_sense_in,
c2n_sense_out => c2n_sense_out,
c2n_motor_in => c2n_motor_in,
c2n_motor_out => c2n_motor_out,
-- Buttons
BUTTON => button_i );
-- Parallel cable not implemented. This is the way to stub it...
drv_via1_port_a_i(7 downto 1) <= drv_via1_port_a_o(7 downto 1) or not drv_via1_port_a_t(7 downto 1);
drv_via1_port_a_i(0) <= drv_track_is_0; -- for 1541C
drv_via1_ca2_i <= drv_via1_ca2_o or not drv_via1_ca2_t;
drv_via1_cb1_i <= drv_via1_cb1_o or not drv_via1_cb1_t;
irq_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => irq_oc, oc_out => IRQn);
nmi_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => nmi_oc, oc_out => NMIn);
dma_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => dma_oc, oc_out => DMAn);
exr_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => exrom_oc, oc_out => EXROMn);
gam_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => game_oc, oc_out => GAMEn);
SLOT_ADDR(15 downto 12) <= slot_addr_o(15 downto 12) when slot_addr_th = '1' else (others => 'Z');
SLOT_ADDR(11 downto 00) <= slot_addr_o(11 downto 00) when slot_addr_tl = '1' else (others => 'Z');
SLOT_DATA <= slot_data_o when slot_data_t = '1' else (others => 'Z');
RWn <= slot_rwn_o when slot_addr_tl = '1' else 'Z';
RSTn <= '0' when RSTn_out = '0' else 'Z';
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
-- Tape
c2n_motor_in <= CAS_MOTOR;
CAS_SENSE <= '0' when c2n_sense_out = '1' else 'Z';
c2n_sense_in <= not CAS_SENSE;
CAS_READ <= c2n_read_out when c2n_read_en = '1' else 'Z';
c2n_read_in <= CAS_READ;
CAS_WRITE <= c2n_write_out when c2n_write_en = '1' else 'Z';
c2n_write_in <= CAS_WRITE;
i_mem_ctrl: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => false )
port map (
clock => sys_clock,
clk_2x => sys_clock_2x,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_BA,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ );
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
i_pwm0: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => audio_left'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => audio_left,
dac_out => PWM_OUT(0) );
i_pwm1: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => audio_right'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => audio_right,
dac_out => PWM_OUT(1) );
end structural;
|
--! @file automatic_tb.vhd
--!
--! @authors Salvatore Barone <[email protected]> <br>
--! Alfonso Di Martino <[email protected]> <br>
--! Sossio Fiorillo <[email protected]> <br>
--! Pietro Liguori <[email protected]> <br>
--!
--! @date 05 07 2017
--!
--! @copyright
--! Copyright 2017 Salvatore Barone <[email protected]> <br>
--! Alfonso Di Martino <[email protected]> <br>
--! Sossio Fiorillo <[email protected]> <br>
--! Pietro Liguori <[email protected]> <br>
--!
--!
--! This file is part of Linear-Regression.
--!
--! Linear-Regression is free software; you can redistribute it and/or modify it under the terms of
--! the GNU General Public License as published by the Free Software Foundation; either version 3 of
--! the License, or any later version.
--!
--! Linear-Regression is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
--! without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--! GNU General Public License for more details.
--!
--! You should have received a copy of the GNU General Public License along with this program; if not,
--! write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
--! USA.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all; -- per le operazioni su file
entity automatic_tb is
end automatic_tb;
architecture behavioral of automatic_tb is
component LinearRegression
Port ( clk : in std_logic;
load : in std_logic;
reset_n : in std_logic;
prim : in STD_LOGIC_VECTOR (5 downto 0);
Sum2 : in STD_LOGIC_VECTOR (23 downto 0);
B : in STD_LOGIC_VECTOR (23 downto 0);
Sum1 : in STD_LOGIC_VECTOR (23 downto 0);
C : in STD_LOGIC_VECTOR (23 downto 0);
A : in STD_LOGIC_VECTOR (23 downto 0);
m : out STD_LOGIC_VECTOR (23 downto 0);
q : out STD_LOGIC_VECTOR (23 downto 0));
end component;
constant clock_period : time := 10ns;
signal clk : std_logic := '0';
signal load : std_logic := '0';
signal reset_n : std_logic := '0';
signal prim : std_logic_vector (5 downto 0) := b"011001";
signal a : std_logic_vector (23 downto 0) := x"7B13B1";
signal b : std_logic_vector (23 downto 0) := x"4CCCCC";
signal c : std_logic_vector (23 downto 0) := x"504816";
signal sum1 : std_logic_vector (23 downto 0) := (others=>'0');
signal sum2 : std_logic_vector (23 downto 0) := (others=>'0');
signal m : std_logic_vector (23 downto 0) := (others=>'0');
signal q : std_logic_vector (23 downto 0) := (others=>'0');
-- oggetti per lettura/scrittura su file
file dataset : text;
file results : text;
begin
clock_process : process
begin
clk <= not clk;
wait for clock_period / 2;
end process clock_process;
UUT : LinearRegression
port map( clk => clk,
load => load,
reset_n => reset_n,
prim => prim,
sum2 => sum2,
b => b,
sum1 => sum1,
c => c,
a => a,
m => m,
q => q);
stim_proc : process
variable rline : line;
variable wline : line;
variable r_sum1 : std_logic_vector (23 downto 0) := (others=>'0');
variable r_sum2 : std_logic_vector (23 downto 0) := (others=>'0');
variable r_m : std_logic_vector (23 downto 0) := (others=>'0');
variable r_q : std_logic_vector (23 downto 0) := (others=>'0');
variable w_dm : std_logic_vector (23 downto 0) := (others=>'0');
variable w_dq : std_logic_vector (23 downto 0) := (others=>'0');
variable space : character;
begin
wait for 10*clock_period;
reset_n <= '1';
load <= '1';
file_open(dataset, "/home/ssaa/dataset.txt", read_mode);
file_open(results, "/home/ssaa/outputPostSynth.txt", write_mode);
while not endfile(dataset) loop
readline(dataset, rline);
read(rline, r_sum1); read(rline, space);
read(rline, r_sum2);
sum1 <= r_sum1;
sum2 <= r_sum2;
wait for 4*clock_period;
write(wline, m, right, 24);
write(wline, ' ', right, 1);
write(wline, q, right, 24);
writeline(results, wline);
end loop;
file_close(dataset);
file_close(results);
wait;
end process;
end behavioral;
|
------------------------------------------------------------------------------
--
-- File: axi_dpti_v1_0.vhd
-- Author: Sergiu Arpadi
-- Original Project: AXI DPTI
-- Date: 8 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
--This is the top module for the AXI DPTI project. It defines the top level ports
--for the DPTI interface, AXI Lite interface and the AXI Stream interface. The module
--is also used to declare the FIFOs (RX and TX) and the DPTI to STREAM and STREAM to
--DPTI converters as well as the module responsible for the AXI Lite interface.
--Another function for the module is the clock domain crossings for the LENGTH,
--CONTROL and STATUS AXI Lite registers, using the HandshakeData and SyncAsync
--modules. A PLL is also instantiated here which is used to compensate for the
--prog_clko BUFG delay.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity axi_dpti_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface AXI_LITE
C_AXI_LITE_DATA_WIDTH : integer := 32;
C_AXI_LITE_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
--DPTI INTERFACE
prog_clko : in STD_LOGIC;
prog_rxen : in STD_LOGIC;
prog_txen : in STD_LOGIC;
prog_spien : in STD_LOGIC;
prog_rdn : out STD_LOGIC;
prog_wrn : out STD_LOGIC;
prog_oen : out STD_LOGIC;
prog_siwun : out STD_LOGIC;
prog_d : inout STD_LOGIC_VECTOR (7 downto 0);
--AXI STREAM INTERFACE
m_axis_aclk : in std_logic;
m_axis_aresetn : in std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(31 downto 0);
m_axis_tkeep : out std_logic_vector(3 downto 0);
m_axis_tlast : out std_logic;
m_axis_tvalid : out std_logic;
s_axis_aclk : in std_logic;
s_axis_aresetn : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(31 downto 0);
s_axis_tkeep : in std_logic_vector(3 downto 0);
s_axis_tlast : in std_logic;
s_axis_tvalid : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface AXI_LITE
axi_lite_aclk : in std_logic;
axi_lite_aresetn : in std_logic;
axi_lite_awaddr : in std_logic_vector(C_AXI_LITE_ADDR_WIDTH-1 downto 0);
axi_lite_awprot : in std_logic_vector(2 downto 0);
axi_lite_awvalid : in std_logic;
axi_lite_awready : out std_logic;
axi_lite_wdata : in std_logic_vector(C_AXI_LITE_DATA_WIDTH-1 downto 0);
axi_lite_wstrb : in std_logic_vector((C_AXI_LITE_DATA_WIDTH/8)-1 downto 0);
axi_lite_wvalid : in std_logic;
axi_lite_wready : out std_logic;
axi_lite_bresp : out std_logic_vector(1 downto 0);
axi_lite_bvalid : out std_logic;
axi_lite_bready : in std_logic;
axi_lite_araddr : in std_logic_vector(C_AXI_LITE_ADDR_WIDTH-1 downto 0);
axi_lite_arprot : in std_logic_vector(2 downto 0);
axi_lite_arvalid : in std_logic;
axi_lite_arready : out std_logic;
axi_lite_rdata : out std_logic_vector(C_AXI_LITE_DATA_WIDTH-1 downto 0);
axi_lite_rresp : out std_logic_vector(1 downto 0);
axi_lite_rvalid : out std_logic;
axi_lite_rready : in std_logic
);
end axi_dpti_v1_0;
architecture arch_imp of axi_dpti_v1_0 is
--------------------------------------------------------------------------------------------------------------------------
-- component declaration
component axi_dpti_v1_0_AXI_LITE is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
lAXI_LiteLengthReg : out std_logic_vector (31 downto 0);
lAXI_LiteControlReg : out std_logic_vector (31 downto 0);
lAXI_LiteStatusReg : out std_logic_vector (31 downto 0);
lPushLength : out std_logic;
lPushControl : out std_logic;
lRdyLength : in std_logic;
lRdyControl : in std_logic;
lAckLength : in std_logic;
lAckControl : in std_logic;
TxLengthEmpty : in std_logic;
RxLengthEmpty : in std_logic;
prog_spien : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_dpti_v1_0_AXI_LITE;
--------------------------------------------------------------------------------------------------------------------------
component HandshakeData is
Generic (
kDataWidth : natural := 32);
Port (
InClk : in STD_LOGIC;
OutClk : in STD_LOGIC;
iData : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
oData : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
iPush : in STD_LOGIC;
iRdy : out STD_LOGIC;
oAck : in STD_LOGIC := '1';
oValid : out STD_LOGIC;
aReset : in std_logic
);
end component;
--------------------------------------------------------------------------------------------------------------------------
component fifo_generator_dpti
PORT (
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC
);
end component;
--------------------------------------------------------------------------------------------------------------------------
component AXI_S_to_DPTI_converter is
Port (
pResetnTx : in std_logic;
PROG_CLK : in std_logic;
pTxe : in std_logic;
pWr : out std_logic;
pDataOut : out std_logic_vector (7 downto 0);
pOutTready : out std_logic;
pInTdata : in std_logic_vector (31 downto 0);
pInTvalid : in std_logic;
pInTlast : in std_logic;
pInTkeep : in std_logic_vector (3 downto 0);
pAXI_L_Length : in std_logic_vector (31 downto 0);
pOvalidLength : in std_logic;
pAXI_L_Control : in std_logic_vector (31 downto 0);
pOvalidControl : in std_logic;
pTxLengthEmpty : out std_logic
);
end component;
--------------------------------------------------------------------------------------------------------------------------
component DPTI_to_AXI_S_converter is
Port (
pResetnRx : in std_logic;
PROG_CLK : in std_logic;
pRxf : in std_logic;
pRd : out std_logic;
pOe : out std_logic;
pDataIn : in std_logic_vector (7 downto 0);
pInTready : in std_logic;
pOutTdata : out std_logic_vector (31 downto 0);
pOutTvalid : out std_logic;
pOutTlast : out std_logic;
pOutTkeep : out std_logic_vector (3 downto 0);
pAXI_L_Length : in std_logic_vector (31 downto 0);
pOvalidLength : in std_logic;
pAXI_L_Control : in std_logic_vector (31 downto 0);
pOvalidControl : in std_logic;
pRxLengthEmpty : out std_logic
);
end component;
--------------------------------------------------------------------------------------------------------------------------
signal pCtlDataOut : std_logic_vector (7 downto 0);
signal pCtlDataIn : std_logic_vector (7 downto 0);
signal pCtlOe : std_logic;
signal pCtlInTready : std_logic;
signal pCtlOutTdata : std_logic_vector(31 downto 0);
signal pCtlOutTvalid : std_logic;
signal pCtlOutTlast : std_logic;
signal pCtlOutTkeep : std_logic_vector(3 downto 0);
signal pCtlOutTready : std_logic;
signal pCtlInTdata : std_logic_vector(31 downto 0);
signal pCtlInTvalid : std_logic;
signal pCtlInTlast : std_logic;
signal pCtlInTkeep : std_logic_vector(3 downto 0);
signal lCtlAXI_LiteLengthReg : std_logic_vector(31 downto 0);
signal lCtlAXI_LiteControlReg : std_logic_vector(31 downto 0);
signal lCtlAXI_LiteStatusReg : std_logic_vector(31 downto 0);
signal lCtlPushLength : std_logic;
signal lCtlPushControl : std_logic;
---------------------------------------------------
--SYNC_ASYNC---------------------------------------
---------------------------------------------------
signal pControlRegSyncd : std_logic_vector (31 downto 0);
signal pLengthRegSyncd : std_logic_vector (31 downto 0);
--signal pStatusReg : std_logic_vector (31 downto 0);
signal lCtlRdyLength : std_logic;
signal pCtlAckLength : std_logic := '0';
signal lCtlAckLength : std_logic;
signal pCtlValidLength : std_logic;
signal aCtlResetLength : std_logic :='1';
signal lCtlRdyControl : std_logic;
signal pCtlAckControl : std_logic := '0';
signal lCtlAckControl : std_logic;
signal pCtlValidControl : std_logic;
signal aCtlResetControl : std_logic :='1';
signal iPushStatus : std_logic := '0';
signal iRdyStatus : std_logic;
signal oValidStatus : std_logic;
signal aResetStatus : std_logic :='1';
signal pCtlRxLengthEmpty : std_logic :='1';
signal pCtlTxLengthEmpty : std_logic :='1';
signal lCtlRxLengthEmpty : std_logic :='1';
signal lCtlTxLengthEmpty : std_logic :='1';
--------------------------------------------------------------------------------------------------------------------------
signal spien_syncReg : std_logic;
signal aCtlResetnRx : std_logic;
signal aCtlResetnTx : std_logic;
signal pAXI_LiteReset : std_logic := '0';
signal pM_AXIS_Reset : std_logic := '0';
signal pS_AXIS_Reset : std_logic := '0';
--------------------------------------------------------------------------------------------------------------------------
-- PLL and BUFG signals
--------------------------------------------------------------------------------------------------------------------------
signal PLL_Fb_OutClk : std_logic;
signal PLL_Fb_InClk : std_logic;
signal PROG_CLK : std_logic;
signal aPLL_Reset : std_logic;
signal aPLL_Pwrdwn : std_logic := '0';
signal pPLL_Locked : std_logic := '0';
--------------------------------------------------------------------------------------------------------------------------
signal aSoft_Reset:std_logic;
signal pSoft_Reset:std_logic;
signal prog_rdn_0 :std_logic;
signal prog_wrn_0 : std_logic;
signal prog_oen_0 : std_logic;
signal pCtlOeN :std_logic;
signal clearFlag:std_logic;
begin
pCtlOeN <= not pCtlOe;
aSoft_Reset <= lCtlAXI_LiteControlReg(2);
prog_rdn <= prog_rdn_0;
prog_wrn <= prog_wrn_0;
prog_oen <= prog_oen_0;
-- prog_spien is used as a sync reset signal by the PC.
-- spien_syncReg logic. Latch falling edge of prog_spien, prog_clk will stop. Wait until PROG_CLK is enabled again to disable reset
process (prog_clko, prog_spien)begin
if(prog_spien='1')then
spien_syncreg<=prog_spien;
else if rising_edge(prog_clko)then
spien_syncReg<=prog_spien;
end if;
end if;
end process;
-- reset signals
aCtlResetnTx <= pPLL_Locked and pAXI_LiteReset and pS_AXIS_Reset and not pSoft_Reset and not spien_syncReg; --pPLL_Locked and
aCtlResetnRx <= pPLL_Locked and pAXI_LiteReset and pM_AXIS_Reset and not pSoft_Reset and not spien_syncReg; --pPLL_Locked and
aPLL_Reset <= '0';--prog_spien;
-- status register
--pStatusReg (0) <= pCtlTxLengthEmpty;
--pStatusReg (16) <= pCtlRxLengthEmpty;
--pStatusReg (15 downto 1) <= (others => '0');
--pStatusReg (31 downto 17) <= (others => '0');
-- IOBUF is implemented
DataIOBUFs: for i in 0 to 7 generate
IOBUF_inst : IOBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => pCtlDataIn(i), -- Buffer output
IO => prog_d(i), -- Buffer inout port (connect directly to top-level port)
I => pCtlDataOut(i), -- Buffer input
T => pCtlOeN -- 3-state enable input, high=input, low=output
);
end generate DataIOBUFs;
--prog_d <= pCtlDataOut when pCtlOe = '1' else "ZZZZZZZZ";
--pCtlDataIn <= prog_d;
-- SIWU signal is not used
prog_siwun <= '1';
prog_oen_0 <= pCtlOe;
aCtlResetLength <= not pPLL_Locked;
aCtlResetControl <= not pPLL_Locked;
PROG_CLK <= Pll_Fb_InClk;
--------------------------------------------------------------------------------------------------------------------------
-- Instantiations
--------------------------------------------------------------------------------------------------------------------------
BUFG_inst : BUFG -- used for PLL feedback clock
port map (
O => Pll_Fb_InClk, -- 1-bit output: Clock output
I => Pll_Fb_OutClk -- 1-bit input: Clock input
);
--BUFIO_Inst : BUFR
-- generic map (
-- BUFR_DIVIDE => "BYPASS", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
-- SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
-- )
-- port map (
-- O => PROG_CLK,
-- I => prog_clko,
-- CE => '0', -- Unused in BYPASS mode
-- CLR => '0' -- Unused in BYPASS mode
-- );
--------------------------------------------------------------------------------------------------------------------------
PLLE2_BASE_inst : PLLE2_BASE -- PLL used to correct BUFG delay for prog_clko
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 15, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
CLKIN1_PERIOD => 16.67, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT0_DIVIDE => 15,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
-- CLKOUT0 => PROG_CLK, -- 1-bit output: CLKOUT0
-- CLKOUT1 => CLKOUT1, -- 1-bit output: CLKOUT1
-- CLKOUT2 => CLKOUT2, -- 1-bit output: CLKOUT2
-- CLKOUT3 => CLKOUT3, -- 1-bit output: CLKOUT3
-- CLKOUT4 => CLKOUT4, -- 1-bit output: CLKOUT4
-- CLKOUT5 => CLKOUT5, -- 1-bit output: CLKOUT5
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => Pll_Fb_OutClk, -- 1-bit output: Feedback clock
LOCKED => pPLL_Locked, -- 1-bit output: LOCK
CLKIN1 => prog_clko, -- 1-bit input: Input clock
-- Control Ports: 1-bit (each) input: PLL control ports
PWRDWN => aPLL_Pwrdwn, -- 1-bit input: Power-down
RST => aPLL_Reset, -- 1-bit input: Reset
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => Pll_Fb_InClk -- 1-bit input: Feedback clock
);
--------------------------------------------------------------------------------------------------------------------------
-- Instantiation of Axi Bus Interface AXI_LITE
axi_dpti_v1_0_AXI_LITE_inst : axi_dpti_v1_0_AXI_LITE
generic map (
C_S_AXI_DATA_WIDTH => C_AXI_LITE_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_AXI_LITE_ADDR_WIDTH
)
port map (
lAXI_LiteLengthReg => lCtlAXI_LiteLengthReg,
lAXI_LiteControlReg => lCtlAXI_LiteControlReg,
lAXI_LiteStatusReg => lCtlAXI_LiteStatusReg,
lPushLength => lCtlPushLength,
lPushControl => lCtlPushControl,
lRdyLength => lCtlRdyLength,
lRdyControl => lCtlRdyControl,
lAckLength => lCtlAckLength,
lAckControl => lCtlAckControl,
TxLengthEmpty => lCtlTxLengthEmpty,
RxLengthEmpty => lCtlRxLengthEmpty,
prog_spien => prog_spien,
S_AXI_ACLK => axi_lite_aclk,
S_AXI_ARESETN => axi_lite_aresetn,
S_AXI_AWADDR => axi_lite_awaddr,
S_AXI_AWPROT => axi_lite_awprot,
S_AXI_AWVALID => axi_lite_awvalid,
S_AXI_AWREADY => axi_lite_awready,
S_AXI_WDATA => axi_lite_wdata,
S_AXI_WSTRB => axi_lite_wstrb,
S_AXI_WVALID => axi_lite_wvalid,
S_AXI_WREADY => axi_lite_wready,
S_AXI_BRESP => axi_lite_bresp,
S_AXI_BVALID => axi_lite_bvalid,
S_AXI_BREADY => axi_lite_bready,
S_AXI_ARADDR => axi_lite_araddr,
S_AXI_ARPROT => axi_lite_arprot,
S_AXI_ARVALID => axi_lite_arvalid,
S_AXI_ARREADY => axi_lite_arready,
S_AXI_RDATA => axi_lite_rdata,
S_AXI_RRESP => axi_lite_rresp,
S_AXI_RVALID => axi_lite_rvalid,
S_AXI_RREADY => axi_lite_rready
);
-- Add user logic here
--------------------------------------------------------------------------------------------------------------------------
in_length_sync : HandshakeData -- synchronization module for AXI LITE LENGTH register crossing to PROG_CLK clock domain
Port map (
InClk => axi_lite_aclk,
OutClk => PROG_CLK,
iData => lCtlAXI_LiteLengthReg,
oData => pLengthRegSyncd, -- synchronized output
iPush => lCtlPushLength,
iRdy => lCtlRdyLength,
oAck => pCtlAckLength,
oValid => pCtlValidLength, -- indicates valid synchronized data
aReset => aCtlResetLength
);
--------------------------------------------------------------------------------------------------------------------------
in_control_sync : HandshakeData -- synchronization module for AXI LITE CONTROL register crossing to PROG_CLK clock domain
Port map (
InClk => axi_lite_aclk,
OutClk => PROG_CLK,
iData => lCtlAXI_LiteControlReg,
oData => pControlRegSyncd, -- synchronized output
iPush => lCtlPushControl,
iRdy => lCtlRdyControl,
oAck => pCtlAckControl,
oValid => pCtlValidControl, -- indicates valid synchronized data
aReset => aCtlResetControl
);
--------------------------------------------------------------------------------------------------------------------------
SyncAsync_oAckLength: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => '0',
aIn => pCtlAckLength,
OutClk => axi_lite_aclk,
oOut => lCtlAckLength);
--------------------------------------------------------------------------------------------------------------------------
SyncAsync_oAckControl: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => '0',
aIn => pCtlAckControl,
OutClk => axi_lite_aclk,
oOut => lCtlAckControl);
--------------------------------------------------------------------------------------------------------------------------
--GenSyncStatusReg: for i in 0 to 31 generate -- STATUS register sync module (from PROG_CLK domain to AXI_L_CLK domain)
--SyncAsyncMultiple: entity work.SyncAsync
-- generic map (
-- kResetTo => '0',
-- kStages => 2) --use double FF synchronizer
-- port map (
-- aReset => '0',
-- aIn => pStatusReg(i),
-- OutClk => axi_lite_aclk,
-- oOut => lCtlAXI_LiteStatusReg(i)
-- );
--end generate GenSyncStatusReg;
SyncAsyncTxLenEmpty: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0',
aIn => pCtlTxLengthEmpty,
OutClk => axi_lite_aclk,
oOut => lCtlTxLengthEmpty
);
SyncAsyncRxLenEmpty: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0',
aIn => pCtlRxLengthEmpty,
OutClk => axi_lite_aclk,
oOut => lCtlRxLengthEmpty
);
------------------------------------------------------------------------------------------------
SyncReset_AXI_LITE: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => axi_lite_aresetn,
OutClk => PROG_CLK,
oRst => pAXI_LiteReset);
SyncReset_M_AXIS: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => m_axis_aresetn,
OutClk => PROG_CLK,
oRst => pM_AXIS_Reset);
SyncReset_S_AXIS: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => s_axis_aresetn,
OutClk => PROG_CLK,
oRst => pS_AXIS_Reset);
SyncReset_SoftReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aSoft_Reset,
OutClk => PROG_CLK,
oRst => pSoft_Reset);
------------------------------------------------------------------------------------------------
RX_fifo : fifo_generator_dpti PORT MAP ( -- AXI STREAM FIFO : used only for clock domain crossing. low capacity
m_aclk => m_axis_aclk,
s_aclk => PROG_CLK,
s_aresetn => aCtlResetnRx,
s_axis_tvalid => pCtlOutTvalid,
s_axis_tready => pCtlInTready,
s_axis_tdata => pCtlOutTdata,
s_axis_tkeep => pCtlOutTkeep,
s_axis_tlast => pCtlOutTlast,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tkeep => m_axis_tkeep,
m_axis_tlast => m_axis_tlast
);
----------------------------------------------------------------------------------------------------------
TX_fifo : fifo_generator_dpti PORT MAP ( -- AXI STREAM FIFO : used only for clock domain crossing. low capacity
m_aclk => PROG_CLK,
s_aclk => s_axis_aclk,
s_aresetn => aCtlResetnTx,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tkeep => s_axis_tkeep,
s_axis_tlast => s_axis_tlast,
m_axis_tvalid => pCtlInTvalid,
m_axis_tready => pCtlOutTready,
m_axis_tdata => pCtlInTdata,
m_axis_tkeep => pCtlInTkeep,
m_axis_tlast => pCtlInTlast
);
----------------------------------------------------------------------------------------------------------
AXI_S_to_DPTI_inst : AXI_S_to_DPTI_converter PORT MAP ( -- converts 32bit AXI STREAM from TX_FIFO data to 8bit data which is then sent to the DPTI interface
pResetnTx => aCtlResetnTx,
PROG_CLK => PROG_CLK,
pTxe => prog_txen,
pWr => prog_wrn_0,
pDataOut => pCtlDataOut,
pOutTready => pCtlOutTready,
pInTdata => pCtlInTdata,
pInTvalid => pCtlInTvalid,
pInTlast => pCtlInTlast,
pInTkeep => pCtlInTkeep,
pAXI_L_Length => pLengthRegSyncd,
pOvalidLength => pCtlValidLength,
pAXI_L_Control => pControlRegSyncd,
pOvalidControl => pCtlValidControl,
pTxLengthEmpty => pCtlTxLengthEmpty
);
----------------------------------------------------------------------------------------------------------
DPTI_to_AXI_S_inst : DPTI_to_AXI_S_converter PORT MAP ( -- converts 8bit data received from the DPTI interface to 32bit AXI STREAM data sent to RX_FIFO
pResetnRx => aCtlResetnRx,
PROG_CLK => PROG_CLK,
pRxf => prog_rxen,
pRd => prog_rdn_0,
pOe => pCtlOe,
pDataIn => pCtlDataIn,
pInTready => pCtlInTready,
pOutTdata => pCtlOutTdata,
pOutTvalid => pCtlOutTvalid,
pOutTlast => pCtlOutTlast,
pOutTkeep => pCtlOutTkeep,
pAXI_L_Length => pLengthRegSyncd,
pOvalidLength => pCtlValidLength,
pAXI_L_Control => pControlRegSyncd,
pOvalidControl => pCtlValidControl,
pRxLengthEmpty => pCtlRxLengthEmpty
);
----------------------------------------------------------------------------------------------------------
-- processes
----------------------------------------------------------------------------------------------------------
Length_oACK: process (PROG_CLK, pCtlValidLength) is -- generates auxiliary signals for LENGTH register HandshakeData module
variable count : integer range 0 to 2;
begin
if rising_edge (PROG_CLK) then
if pCtlValidLength = '0' then
count := 2;
pCtlAckLength <= '0';
elsif count = 2 then
pCtlAckLength <= '1';
count := count - 1;
elsif count = 1 then
pCtlAckLength <= '0';
count := 0;
else
pCtlAckLength <= '0';
count := count - 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------------
Control_oACK: process (PROG_CLK, pCtlValidControl) is -- generates auxiliary signals for CONTROL register HandshakeData module
variable count : integer range 0 to 2;
begin
if rising_edge (PROG_CLK) then
if pCtlValidControl = '0' then
count := 2;
pCtlAckControl <= '0';
elsif count = 2 then
pCtlAckControl <= '1';
count := count - 1;
elsif count = 1 then
pCtlAckControl <= '0';
count := 0;
else
pCtlAckControl <= '0';
count := count - 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------------
-- User logic ends
end arch_imp;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_initials is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_get_initials is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_ST_pp0_stg2_fsm_2 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_pp0_stg3_fsm_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "10";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal nfa_initials_buckets_read_reg_59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_131 : BOOLEAN;
signal ap_sig_bdd_130 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0_preg assign process. --
ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
ap_reg_ppiten_pp0_it0_preg <= ap_start;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
elsif (((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))) then
nfa_initials_buckets_read_reg_59 <= nfa_initials_buckets_datain;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_ce , nfa_initials_buckets_rsp_empty_n , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
end if;
when ap_ST_pp0_stg1_fsm_1 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)))) then
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
end if;
when ap_ST_pp0_stg2_fsm_2 =>
if (not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
else
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
end if;
when ap_ST_pp0_stg3_fsm_3 =>
if ((ap_const_logic_1 = ap_ce)) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_initials_buckets_rsp_empty_n)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg)
begin
if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then
ap_reg_ppiten_pp0_it0 <= ap_start;
else
ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg;
end if;
end process;
ap_return_0 <= nfa_initials_buckets_read_reg_59;
ap_return_1 <= nfa_initials_buckets_datain;
-- ap_sig_bdd_130 assign process. --
ap_sig_bdd_130_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce)
begin
ap_sig_bdd_130 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_131 assign process. --
ap_sig_bdd_131_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0)
begin
ap_sig_bdd_131 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- nfa_initials_buckets_address assign process. --
nfa_initials_buckets_address_assign_proc : process(ap_CS_fsm, ap_sig_bdd_131, ap_sig_bdd_130)
begin
if (ap_sig_bdd_130) then
if ((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm)) then
nfa_initials_buckets_address <= ap_const_lv64_1(32 - 1 downto 0);
elsif (ap_sig_bdd_131) then
nfa_initials_buckets_address <= ap_const_lv32_0;
else
nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_initials_buckets_dataout <= ap_const_lv32_0;
nfa_initials_buckets_req_din <= ap_const_logic_0;
-- nfa_initials_buckets_req_write assign process. --
nfa_initials_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
nfa_initials_buckets_req_write <= ap_const_logic_1;
else
nfa_initials_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_initials_buckets_rsp_read assign process. --
nfa_initials_buckets_rsp_read_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_initials_buckets_rsp_empty_n)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))))) then
nfa_initials_buckets_rsp_read <= ap_const_logic_1;
else
nfa_initials_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_initials_buckets_size <= ap_const_lv32_1;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_initials is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_get_initials is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_ST_pp0_stg2_fsm_2 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_pp0_stg3_fsm_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "10";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal nfa_initials_buckets_read_reg_59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_131 : BOOLEAN;
signal ap_sig_bdd_130 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0_preg assign process. --
ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
ap_reg_ppiten_pp0_it0_preg <= ap_start;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
elsif (((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))) then
nfa_initials_buckets_read_reg_59 <= nfa_initials_buckets_datain;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_ce , nfa_initials_buckets_rsp_empty_n , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
end if;
when ap_ST_pp0_stg1_fsm_1 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)))) then
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
end if;
when ap_ST_pp0_stg2_fsm_2 =>
if (not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
else
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
end if;
when ap_ST_pp0_stg3_fsm_3 =>
if ((ap_const_logic_1 = ap_ce)) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_initials_buckets_rsp_empty_n)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg)
begin
if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then
ap_reg_ppiten_pp0_it0 <= ap_start;
else
ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg;
end if;
end process;
ap_return_0 <= nfa_initials_buckets_read_reg_59;
ap_return_1 <= nfa_initials_buckets_datain;
-- ap_sig_bdd_130 assign process. --
ap_sig_bdd_130_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce)
begin
ap_sig_bdd_130 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_131 assign process. --
ap_sig_bdd_131_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0)
begin
ap_sig_bdd_131 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- nfa_initials_buckets_address assign process. --
nfa_initials_buckets_address_assign_proc : process(ap_CS_fsm, ap_sig_bdd_131, ap_sig_bdd_130)
begin
if (ap_sig_bdd_130) then
if ((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm)) then
nfa_initials_buckets_address <= ap_const_lv64_1(32 - 1 downto 0);
elsif (ap_sig_bdd_131) then
nfa_initials_buckets_address <= ap_const_lv32_0;
else
nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_initials_buckets_dataout <= ap_const_lv32_0;
nfa_initials_buckets_req_din <= ap_const_logic_0;
-- nfa_initials_buckets_req_write assign process. --
nfa_initials_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
nfa_initials_buckets_req_write <= ap_const_logic_1;
else
nfa_initials_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_initials_buckets_rsp_read assign process. --
nfa_initials_buckets_rsp_read_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_initials_buckets_rsp_empty_n)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))))) then
nfa_initials_buckets_rsp_read <= ap_const_logic_1;
else
nfa_initials_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_initials_buckets_size <= ap_const_lv32_1;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_initials is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_get_initials is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_ST_pp0_stg2_fsm_2 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_pp0_stg3_fsm_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "10";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal nfa_initials_buckets_read_reg_59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_131 : BOOLEAN;
signal ap_sig_bdd_130 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0_preg assign process. --
ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
ap_reg_ppiten_pp0_it0_preg <= ap_start;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
elsif (((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))) then
nfa_initials_buckets_read_reg_59 <= nfa_initials_buckets_datain;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_ce , nfa_initials_buckets_rsp_empty_n , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
end if;
when ap_ST_pp0_stg1_fsm_1 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)))) then
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
end if;
when ap_ST_pp0_stg2_fsm_2 =>
if (not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
else
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
end if;
when ap_ST_pp0_stg3_fsm_3 =>
if ((ap_const_logic_1 = ap_ce)) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_initials_buckets_rsp_empty_n)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg)
begin
if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then
ap_reg_ppiten_pp0_it0 <= ap_start;
else
ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg;
end if;
end process;
ap_return_0 <= nfa_initials_buckets_read_reg_59;
ap_return_1 <= nfa_initials_buckets_datain;
-- ap_sig_bdd_130 assign process. --
ap_sig_bdd_130_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce)
begin
ap_sig_bdd_130 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_131 assign process. --
ap_sig_bdd_131_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0)
begin
ap_sig_bdd_131 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- nfa_initials_buckets_address assign process. --
nfa_initials_buckets_address_assign_proc : process(ap_CS_fsm, ap_sig_bdd_131, ap_sig_bdd_130)
begin
if (ap_sig_bdd_130) then
if ((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm)) then
nfa_initials_buckets_address <= ap_const_lv64_1(32 - 1 downto 0);
elsif (ap_sig_bdd_131) then
nfa_initials_buckets_address <= ap_const_lv32_0;
else
nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_initials_buckets_dataout <= ap_const_lv32_0;
nfa_initials_buckets_req_din <= ap_const_logic_0;
-- nfa_initials_buckets_req_write assign process. --
nfa_initials_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
nfa_initials_buckets_req_write <= ap_const_logic_1;
else
nfa_initials_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_initials_buckets_rsp_read assign process. --
nfa_initials_buckets_rsp_read_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_initials_buckets_rsp_empty_n)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))))) then
nfa_initials_buckets_rsp_read <= ap_const_logic_1;
else
nfa_initials_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_initials_buckets_size <= ap_const_lv32_1;
end behav;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF1_3_block6.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block6
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_3_block6 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_16_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_16_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block6;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block6 IS
-- Signals
SIGNAL twdlXdin_14_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_14_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_16_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_16_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_15_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_15_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_16_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_16_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
twdlXdin_14_re_signed <= signed(twdlXdin_14_re);
twdlXdin_14_im_signed <= signed(twdlXdin_14_im);
twdlXdin_16_re_signed <= signed(twdlXdin_16_re);
twdlXdin_16_im_signed <= signed(twdlXdin_16_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_14_re_signed,
twdlXdin_14_im_signed, twdlXdin_16_re_signed, twdlXdin_16_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_14_re_signed, 17);
add_cast_0 := resize(twdlXdin_16_re_signed, 17);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_14_re_signed, 17);
sub_cast_0 := resize(twdlXdin_16_re_signed, 17);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_14_im_signed, 17);
add_cast_2 := resize(twdlXdin_16_im_signed, 17);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_14_im_signed, 17);
sub_cast_2 := resize(twdlXdin_16_im_signed, 17);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_15_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_15_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_16_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_16_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_15_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_15_re <= std_logic_vector(dout_15_re_tmp);
dout_15_im <= std_logic_vector(dout_15_im_tmp);
dout_16_re <= std_logic_vector(dout_16_re_tmp);
dout_16_im <= std_logic_vector(dout_16_im_tmp);
END rtl;
|
-- Para recibir datos. Bit RxRdy = 1 cada vez que leyó todos los bits de un dato
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart is
generic (
F : natural := 50000; -- Device clock frequency [KHz]: 50 MHz
min_baud : natural := 1200;
num_data_bits : natural := 8
);
port (
Rx : in std_logic;
Tx : out std_logic;
Din : in std_logic_vector(7 downto 0);
StartTx : in std_logic;
TxBusy : out std_logic;
Dout : out std_logic_vector(7 downto 0);
RxRdy : out std_logic;
RxErr : out std_logic;
Divisor : in std_logic_vector;
clk : in std_logic;
rst : in std_logic
);
end;
architecture uart_arq of uart is
signal top16 : std_logic;
signal toprx : std_logic;
signal toptx : std_logic;
signal Sig_ClrDiv : std_logic;
begin
reception_unit: entity work.receive
generic map (
NDBits => num_data_bits
)
port map (
clk => clk,
rst => rst,
Rx => Rx,
Dout => Dout,
RxErr => RxErr,
RxRdy => RxRdy,
ClrDiv => Sig_ClrDiv,
Top16 => top16,
TopRx => toprx
);
transmission_unit: entity work.transmit
generic map (
NDBits => num_data_bits
)
port map (
clk => clk,
rst => rst,
Tx => Tx,
Din => Din,
TxBusy => TxBusy,
TopTx => toptx,
StartTx => StartTx
);
timings_unit: entity work.timing
generic map (
F => F,
min_baud => min_baud
)
port map (
clk => clk,
rst => rst,
divisor => Divisor,
ClrDiv => Sig_ClrDiv,
Top16 => top16,
TopTx => toptx,
TopRx => toprx
);
end;
|
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 20:43:38 11/14/2011
-- Design Name: RegMultiplexer
-- Module Name: J:/projekty/elektronika/USB_to_HPIB/usbToHpib/src/test/RegMultiplexer_Test.vhd
-- Project Name: usbToGpib
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: RegMultiplexer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.wrapperComponents.all;
ENTITY RegMultiplexer_Test_vhd IS
END RegMultiplexer_Test_vhd;
ARCHITECTURE behavior OF RegMultiplexer_Test_vhd IS
-- clock definitions
constant clk_period : time := 2ps;
signal clk : std_logic := '0';
--Inputs
SIGNAL strobe : std_logic := '0';
SIGNAL data_in : std_logic_vector(15 downto 0) := (others=>'0');
SIGNAL reg_addr : std_logic_vector(14 downto 0) := (others=>'0');
SIGNAL reg_out_0 : std_logic_vector(15 downto 0) := "0000000000000001";
SIGNAL reg_out_1 : std_logic_vector(15 downto 0) := "0000000000000010";
SIGNAL reg_out_2 : std_logic_vector(15 downto 0) := "0000000000000011";
SIGNAL reg_out_3 : std_logic_vector(15 downto 0) := "0000000000000100";
SIGNAL reg_out_4 : std_logic_vector(15 downto 0) := "0000000000000101";
SIGNAL reg_out_5 : std_logic_vector(15 downto 0) := "0000000000000110";
SIGNAL reg_out_6 : std_logic_vector(15 downto 0) := "0000000000000111";
SIGNAL reg_out_7 : std_logic_vector(15 downto 0) := "0000000000001000";
SIGNAL reg_out_8 : std_logic_vector(15 downto 0) := "0000000000001001";
SIGNAL reg_out_9 : std_logic_vector(15 downto 0) := "0000000000001010";
SIGNAL reg_out_10 : std_logic_vector(15 downto 0) := "0000000000001011";
SIGNAL reg_out_11 : std_logic_vector(15 downto 0) := "0000000000001100";
SIGNAL reg_out_writer : std_logic_vector(15 downto 0) := "0000000000001101";
SIGNAL reg_out_reader : std_logic_vector(15 downto 0) := "0000000000001110";
--Outputs
SIGNAL data_out : std_logic_vector(15 downto 0);
SIGNAL reg_strobe_0 : std_logic;
SIGNAL reg_in_0 : std_logic_vector(15 downto 0);
SIGNAL reg_strobe_1 : std_logic;
SIGNAL reg_in_1 : std_logic_vector(15 downto 0);
SIGNAL reg_strobe_2 : std_logic;
SIGNAL reg_in_2 : std_logic_vector(15 downto 0);
SIGNAL reg_strobe_3 : std_logic;
SIGNAL reg_in_3 : std_logic_vector(15 downto 0);
SIGNAL reg_strobe_4 : std_logic;
SIGNAL reg_in_4 : std_logic_vector(15 downto 0);
SIGNAL reg_strobe_5 : std_logic;
SIGNAL reg_in_5 : std_logic_vector(15 downto 0);
SIGNAL reg_strobe_6 : std_logic;
SIGNAL reg_in_6 : std_logic_vector(15 downto 0);
SIGNAL reg_strobe_7 : std_logic;
SIGNAL reg_in_7 : std_logic_vector(15 downto 0);
SIGNAL reg_strobe_8 : std_logic;
SIGNAL reg_in_8 : std_logic_vector(15 downto 0);
SIGNAL reg_strobe_9 : std_logic;
SIGNAL reg_in_9 : std_logic_vector(15 downto 0);
SIGNAL reg_strobe_10 : std_logic;
SIGNAL reg_in_10 : std_logic_vector(15 downto 0);
SIGNAL reg_strobe_11 : std_logic;
SIGNAL reg_in_11 : std_logic_vector(15 downto 0);
SIGNAL reg_strobe_writer : std_logic;
SIGNAL reg_in_writer : std_logic_vector(15 downto 0);
SIGNAL reg_strobe_reader : std_logic;
SIGNAL reg_in_reader : std_logic_vector(15 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RegMultiplexer generic map(READER_WRITER_BUF_LEN => 16) PORT MAP(
strobe => strobe,
data_in => data_in,
data_out => data_out,
reg_addr => reg_addr,
reg_strobe_0 => reg_strobe_0,
reg_in_0 => reg_in_0,
reg_out_0 => reg_out_0,
reg_strobe_1 => reg_strobe_1,
reg_in_1 => reg_in_1,
reg_out_1 => reg_out_1,
reg_strobe_2 => reg_strobe_2,
reg_in_2 => reg_in_2,
reg_out_2 => reg_out_2,
reg_strobe_3 => reg_strobe_3,
reg_in_3 => reg_in_3,
reg_out_3 => reg_out_3,
reg_strobe_4 => reg_strobe_4,
reg_in_4 => reg_in_4,
reg_out_4 => reg_out_4,
reg_strobe_5 => reg_strobe_5,
reg_in_5 => reg_in_5,
reg_out_5 => reg_out_5,
reg_strobe_6 => reg_strobe_6,
reg_in_6 => reg_in_6,
reg_out_6 => reg_out_6,
reg_strobe_7 => reg_strobe_7,
reg_in_7 => reg_in_7,
reg_out_7 => reg_out_7,
reg_strobe_8 => reg_strobe_8,
reg_in_8 => reg_in_8,
reg_out_8 => reg_out_8,
reg_strobe_9 => reg_strobe_9,
reg_in_9 => reg_in_9,
reg_out_9 => reg_out_9,
reg_strobe_10 => reg_strobe_10,
reg_in_10 => reg_in_10,
reg_out_10 => reg_out_10,
reg_strobe_11 => reg_strobe_11,
reg_in_11 => reg_in_11,
reg_out_11 => reg_out_11,
reg_strobe_other0 => reg_strobe_writer,
reg_in_other0 => reg_in_writer,
reg_out_other0 => reg_out_writer,
reg_strobe_other1 => reg_strobe_reader,
reg_in_other1 => reg_in_reader,
reg_out_other1 => reg_out_reader
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
strobe <= clk;
stim_proc : PROCESS
BEGIN
data_in <= "1010101010101010";
wait for clk_period * 10;
report "$$$ begin RegMultiplexer test $$$";
reg_addr <= "000000000000000";
wait for clk_period * 10;
reg_addr <= "000000000000001";
wait for clk_period * 10;
reg_addr <= "000000000000010";
wait for clk_period * 10;
reg_addr <= "000000000000011";
wait for clk_period * 10;
reg_addr <= "000000000000100";
wait for clk_period * 10;
reg_addr <= "000000000000101";
wait for clk_period * 10;
reg_addr <= "000000000000110";
wait for clk_period * 10;
reg_addr <= "000000000000111";
wait for clk_period * 10;
reg_addr <= "000000000001000";
wait for clk_period * 10;
reg_addr <= "000000000001001";
wait for clk_period * 10;
reg_addr <= "000000000001010";
wait for clk_period * 10;
reg_addr <= "000000000001011";
wait for clk_period * 10;
reg_addr <= "000000000001100";
wait for clk_period * 10;
reg_addr <= "000000000011100";
wait for clk_period * 10;
report "$$$ end RegMultiplexer test $$$";
wait; -- will wait forever
END PROCESS;
END;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_uartlite:2.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_uartlite_v2_0;
USE axi_uartlite_v2_0.axi_uartlite;
ENTITY design_1_axi_uartlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END design_1_axi_uartlite_0_0;
ARCHITECTURE design_1_axi_uartlite_0_0_arch OF design_1_axi_uartlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_uartlite IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_BAUDRATE : INTEGER;
C_DATA_BITS : INTEGER;
C_USE_PARITY : INTEGER;
C_ODD_PARITY : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END COMPONENT axi_uartlite;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "axi_uartlite,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_uartlite_0_0_arch : ARCHITECTURE IS "design_1_axi_uartlite_0_0,axi_uartlite,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "design_1_axi_uartlite_0_0,axi_uartlite,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_uartlite,x_ipVersion=2.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ACLK_FREQ_HZ=100000000,C_S_AXI_ADDR_WIDTH=4,C_S_AXI_DATA_WIDTH=32,C_BAUDRATE=9600,C_DATA_BITS=8,C_USE_PARITY=0,C_ODD_PARITY=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT interrupt";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF rx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART RxD";
ATTRIBUTE X_INTERFACE_INFO OF tx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART TxD";
BEGIN
U0 : axi_uartlite
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => 32,
C_BAUDRATE => 9600,
C_DATA_BITS => 8,
C_USE_PARITY => 0,
C_ODD_PARITY => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
interrupt => interrupt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
rx => rx,
tx => tx
);
END design_1_axi_uartlite_0_0_arch;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_uartlite:2.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_uartlite_v2_0;
USE axi_uartlite_v2_0.axi_uartlite;
ENTITY design_1_axi_uartlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END design_1_axi_uartlite_0_0;
ARCHITECTURE design_1_axi_uartlite_0_0_arch OF design_1_axi_uartlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_uartlite IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_BAUDRATE : INTEGER;
C_DATA_BITS : INTEGER;
C_USE_PARITY : INTEGER;
C_ODD_PARITY : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END COMPONENT axi_uartlite;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "axi_uartlite,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_uartlite_0_0_arch : ARCHITECTURE IS "design_1_axi_uartlite_0_0,axi_uartlite,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "design_1_axi_uartlite_0_0,axi_uartlite,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_uartlite,x_ipVersion=2.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ACLK_FREQ_HZ=100000000,C_S_AXI_ADDR_WIDTH=4,C_S_AXI_DATA_WIDTH=32,C_BAUDRATE=9600,C_DATA_BITS=8,C_USE_PARITY=0,C_ODD_PARITY=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT interrupt";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF rx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART RxD";
ATTRIBUTE X_INTERFACE_INFO OF tx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART TxD";
BEGIN
U0 : axi_uartlite
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => 32,
C_BAUDRATE => 9600,
C_DATA_BITS => 8,
C_USE_PARITY => 0,
C_ODD_PARITY => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
interrupt => interrupt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
rx => rx,
tx => tx
);
END design_1_axi_uartlite_0_0_arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbram
-- File: ahbram.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write.
-- Added Sx-Record read function
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use IEEE.Numeric_Std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.stdio.all;
library techmap;
use techmap.gencomp.all;
entity ahbram_sim is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
fname : string := "ram.dat"
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbram_sim is
constant abits : integer := log2ext(kbytes) + 8 - maccsz/64;
constant dw : integer := maccsz;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBRAM, 0, abits+2+maccsz/64, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits-1+log2(dw/8) downto 0);
size : std_logic_vector(2 downto 0);
prdata : std_logic_vector((dw-1)*pipe downto 0);
pwrite : std_ulogic;
pready : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type :=
(hwrite => '0', hready => '1', hsel => '0', addr => (others => '0'),
size => (others => '0'), prdata => (others => '0'), pwrite => '0',
pready => '1');
signal r, c : reg_type;
signal ramsel : std_logic_vector(dw/8-1 downto 0);
signal write : std_logic_vector(dw/8-1 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(dw-1 downto 0);
signal hwdata : std_logic_vector(dw-1 downto 0);
type ram_type is array (0 to (2**ramaddr'length)-1) of std_logic_vector(ramdata'range);
signal ram : ram_type;
signal read_address : std_logic_vector(ramaddr'range);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(dw/8-1 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
variable hrdata : std_logic_vector(dw-1 downto 0);
variable seldata : std_logic_vector(dw-1 downto 0);
variable raddr : std_logic_vector(3 downto 2);
variable adsel : std_logic;
begin
v := r; v.hready := '1'; bs := (others => '0');
v.pready := r.hready;
if pipe=0 then
adsel := r.hwrite or not r.hready;
else
adsel := r.hwrite or r.pwrite;
v.hready := r.hready or not r.pwrite;
end if;
if adsel = '1' then
haddr := r.addr(abits-1+log2(dw/8) downto log2(dw/8));
else
haddr := ahbsi.haddr(abits-1+log2(dw/8) downto log2(dw/8));
bs := (others => '0');
end if;
raddr := (others => '0');
v.pwrite := '0';
if pipe/=0 and (r.hready='1' or r.pwrite='0') then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
if ahbsi.hready = '1' then
if pipe=0 then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.size := ahbsi.hsize(2 downto 0);
v.hwrite := ahbsi.hwrite and v.hsel;
if pipe = 1 and v.hsel = '1' and ahbsi.hwrite = '0' and (r.pready='1' or ahbsi.htrans(0)='0') then
v.hready := '0';
v.pwrite := r.hwrite;
end if;
end if;
if r.hwrite = '1' then
case r.size is
when HSIZE_BYTE =>
bs(bs'left-conv_integer(r.addr(log2(dw/16) downto 0))) := '1';
when HSIZE_HWORD =>
for i in 0 to dw/16-1 loop
if i = conv_integer(r.addr(log2(dw/16) downto 1)) then
bs(bs'left-i*2 downto bs'left-i*2-1) := (others => '1');
end if;
end loop; -- i
when HSIZE_WORD =>
if dw = 32 then bs := (others => '1');
else
for i in 0 to dw/32-1 loop
if i = conv_integer(r.addr(log2(dw/8)-1 downto 2)) then
bs(bs'left-i*4 downto bs'left-i*4-3) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_DWORD =>
if dw = 32 then null;
elsif dw = 64 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_4WORD =>
if dw < 128 then null;
elsif dw = 128 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when others => --HSIZE_8WORD
if dw < 256 then null;
else bs := (others => '1'); end if;
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
-- Duplicate read data on word basis, unless CORE_ACDM is enabled
if CORE_ACDM = 0 then
if dw = 32 then
seldata := ramdata;
elsif dw = 64 then
if r.size = HSIZE_DWORD then seldata := ramdata; else
if r.addr(2) = '0' then
seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else
seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0);
end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
end if;
elsif dw = 128 then
if r.size = HSIZE_4WORD then
seldata := ramdata;
elsif r.size = HSIZE_DWORD then
if r.addr(3) = '0' then seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
else
raddr := r.addr(3 downto 2);
case raddr is
when "00" => seldata(dw/4-1 downto 0) := ramdata(4*dw/4-1 downto 3*dw/4);
when "01" => seldata(dw/4-1 downto 0) := ramdata(3*dw/4-1 downto 2*dw/4);
when "10" => seldata(dw/4-1 downto 0) := ramdata(2*dw/4-1 downto 1*dw/4);
when others => seldata(dw/4-1 downto 0) := ramdata(dw/4-1 downto 0);
end case;
seldata(dw-1 downto dw/4) := seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0);
end if;
else
seldata := ahbselectdata(ramdata, r.addr(4 downto 2), r.size);
end if;
else
seldata := ramdata;
end if;
if pipe = 0 then
v.prdata := (others => '0');
hrdata := seldata;
else
v.prdata := seldata;
hrdata := r.prdata;
end if;
if (not RESET_ALL) and (rst = '0') then
v.hwrite := RES.hwrite; v.hready := RES.hready;
end if;
write <= bs; for i in 0 to dw/8-1 loop ramsel(i) <= v.hsel or r.hwrite; end loop;
ramaddr <= haddr; c <= v;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hready <= r.hready;
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
-- Select correct write data
hwdata <= ahbreaddata(ahbsi.hwdata, r.addr(4 downto 2),
conv_std_logic_vector(log2(dw/8), 3));
-- aram : syncrambw generic map (tech, abits, dw, scantest) port map (
-- clk, ramaddr, hwdata, ramdata, ramsel, write, ahbsi.testin);
RamProc: process(clk) is
variable L1 : line;
variable FIRST : boolean := true;
variable ADR : std_logic_vector(19 downto 0);
variable BUF : std_logic_vector(31 downto 0);
variable CH : character;
variable ai : integer := 0;
variable len : integer := 0;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
begin
if rising_edge(clk) then
if conv_integer(write) > 0 then
for i in 0 to dw/8-1 loop
if (write(i) = '1') then
ram(to_integer(unsigned(ramaddr)))(i*8+7 downto i*8) <= hwdata(i*8+7 downto i*8);
end if;
end loop;
end if;
read_address <= ramaddr;
end if;
if (rst = '0') and (FIRST = true) then
ram <= (others => (others => '0'));
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
when others => next;
end case;
hread(L1, recdata);
recaddr(31 downto abits+2) := (others => '0');
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
ram(ai+i) <= recdata((i*32) to (i*32+31));
end loop;
if ai = 0 then
ai := 1;
end if;
end if;
end if;
end if;
end loop;
FIRST := false;
end if;
end process RamProc;
ramdata <= ram(to_integer(unsigned(read_address)));
reg : process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
bootmsg : report_version
generic map ("ahbram" & tost(hindex) &
": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
end;
-- pragma translate_on
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