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----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 11.11.2013 14:33:32
-- Design Name:
-- Module Name: switch_port_0_rx_path - rtl
--
-- Description: This is the input port to the switch fabric
-- it consists of following modules:
-- - header extraction: extract the destination mac address from the current frame
-- - lookup module and lookup memory: determine the output ports for each incoming frame
-- - input queue module: merge the data and control path, store frame in memory and request access to crossbar matrix
--
-- further information can found in file rxpath.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity switch_port_rx_path is
Generic (
RECEIVER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
PORT_ID : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
DEST_ADDR_WIDTH : integer := 48;
LOOKUP_MEM_ADDR_WIDTH : integer := 9;
LOOKUP_MEM_DATA_WIDTH : integer := 64
);
Port (
rx_path_clock : in std_logic;
rx_path_resetn : in std_logic;
-- mac to rx_path interface
rx_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
rx_in_valid : in std_logic;
rx_in_last : in std_logic;
rx_in_error : in std_logic;
-- rx_path interface to fabric
rx_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
rx_out_valid : out std_logic;
rx_out_last : out std_logic;
rx_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
rx_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
rx_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
rx_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
rx_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0);
-- timestamp
rx_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0)
);
end switch_port_rx_path;
architecture rtl of switch_port_rx_path is
component rx_path_header_extraction
Generic (
RECEIVER_DATA_WIDTH : integer;
DEST_ADDR_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface
hext_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
hext_in_valid : in std_logic;
hext_in_last : in std_logic;
hext_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- output interface
hext_out_dest : out std_logic_vector(DEST_ADDR_WIDTH-1 downto 0);
hext_out_vlan_enable : out std_logic;
hext_out_vlan_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
hext_out_valid : out std_logic;
hext_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
hext_out_ready : in std_logic
);
end component;
component rx_path_lookup
Generic (
DEST_MAC_WIDTH : integer;
NR_PORTS : integer;
PORT_ID : integer;
LOOKUP_MEM_ADDR_WIDTH : integer;
LOOKUP_MEM_DATA_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface
lookup_in_dest : in std_logic_vector(DEST_ADDR_WIDTH-1 downto 0);
lookup_in_vlan_enable : in std_logic;
lookup_in_vlan_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
lookup_in_valid : in std_logic;
lookup_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
lookup_in_ready : out std_logic;
-- output interface
lookup_out_ports : out std_logic_vector(NR_PORTS-1 downto 0);
lookup_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
lookup_out_skip : out std_logic;
lookup_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
lookup_out_valid : out std_logic;
-- lookup memory interface
mem_enable : out std_logic;
mem_addr : out std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_data : in std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0)
);
end component;
component rx_path_lookup_memory
Generic (
LOOKUP_MEM_ADDR_WIDTH : integer;
LOOKUP_MEM_DATA_WIDTH : integer
);
Port (
--Port A -> Processor
mem_in_wenable : in std_logic_vector(0 downto 0);
mem_in_addr : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_in_data : in std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
mem_in_clk : in std_logic;
--Port B -> Lookup module
mem_out_enable : in std_logic; --opt port
mem_out_addr : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_out_data : out std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
mem_out_clk : in std_logic
);
end component;
component rx_path_input_queue
Generic (
RECEIVER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface data
iq_in_mac_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
iq_in_mac_valid : in std_logic;
iq_in_mac_last : in std_logic;
iq_in_mac_error : in std_logic;
-- input interface control
iq_in_lu_ports : in std_logic_vector(NR_PORTS-1 downto 0);
iq_in_lu_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
iq_in_lu_skip : in std_logic;
iq_in_lu_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
iq_in_lu_valid : in std_logic;
-- output interface arbitration
iq_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
iq_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
iq_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
iq_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
iq_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0);
-- output interface data
iq_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
iq_out_last : out std_logic;
iq_out_valid : out std_logic
);
end component;
signal hext2lookup_dest : std_logic_vector(DEST_ADDR_WIDTH-1 downto 0);
signal hext2lookup_vlan_enable : std_logic;
signal hext2lookup_vlan_prio : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal hext2lookup_valid : std_logic;
signal hext2lookup_timestamp : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal hext2lookup_ready : std_logic;
signal mem2lookup_enable : std_logic;
signal mem2lookup_addr : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem2lookup_data : std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
signal lookup2iq_ports_sig : std_logic_vector(NR_PORTS-1 downto 0);
signal lookup2iq_prio_sig : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal lookup2iq_skip_sig : std_logic;
signal lookup2iq_timestamp : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal lookup2iq_valid_sig : std_logic;
signal rx_path_reset : std_logic;
-- attribute mark_debug : string;
-- attribute mark_debug of hext2lookup_header : signal is "true";
-- attribute mark_debug of hext2lookup_valid : signal is "true";
-- attribute mark_debug of hext2lookup_ready : signal is "true";
-- attribute mark_debug of mem2lookup_enable : signal is "true";
-- attribute mark_debug of mem2lookup_addr : signal is "true";
-- attribute mark_debug of mem2lookup_data : signal is "true";
-- attribute mark_debug of lookup2iq_ports_sig : signal is "true";
-- attribute mark_debug of lookup2iq_skip_sig : signal is "true";
-- attribute mark_debug of lookup2iq_valid_sig : signal is "true";
-- attribute mark_debug of lookup2iq_ready_sig : signal is "true";
begin
-- can be moved to a higher layer lateron
rx_path_reset <= not rx_path_resetn;
header_extraction : rx_path_header_extraction
Generic map(
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
DEST_ADDR_WIDTH => DEST_ADDR_WIDTH,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
Port map(
clk => rx_path_clock,
reset => rx_path_reset,
-- input interface
hext_in_data => rx_in_data,
hext_in_valid => rx_in_valid,
hext_in_last => rx_in_last,
hext_in_timestamp_cnt => rx_in_timestamp_cnt,
-- output interface
hext_out_dest => hext2lookup_dest,
hext_out_vlan_enable => hext2lookup_vlan_enable,
hext_out_vlan_prio => hext2lookup_vlan_prio,
hext_out_valid => hext2lookup_valid,
hext_out_timestamp => hext2lookup_timestamp,
hext_out_ready => hext2lookup_ready
);
lookup : rx_path_lookup
Generic map(
DEST_MAC_WIDTH => DEST_ADDR_WIDTH,
NR_PORTS => NR_PORTS,
PORT_ID => PORT_ID,
LOOKUP_MEM_ADDR_WIDTH => LOOKUP_MEM_ADDR_WIDTH,
LOOKUP_MEM_DATA_WIDTH => LOOKUP_MEM_DATA_WIDTH,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
Port map(
clk => rx_path_clock,
reset => rx_path_reset,
-- input interface
lookup_in_dest => hext2lookup_dest,
lookup_in_vlan_enable => hext2lookup_vlan_enable,
lookup_in_vlan_prio => hext2lookup_vlan_prio,
lookup_in_valid => hext2lookup_valid,
lookup_in_timestamp => hext2lookup_timestamp,
lookup_in_ready => hext2lookup_ready,
-- output interface
lookup_out_ports => lookup2iq_ports_sig,
lookup_out_prio => lookup2iq_prio_sig,
lookup_out_skip => lookup2iq_skip_sig,
lookup_out_timestamp => lookup2iq_timestamp,
lookup_out_valid => lookup2iq_valid_sig,
-- lookup memory interface
mem_enable => mem2lookup_enable,
mem_addr => mem2lookup_addr,
mem_data => mem2lookup_data
);
lookup_memory : rx_path_lookup_memory
Generic map(
LOOKUP_MEM_ADDR_WIDTH => LOOKUP_MEM_ADDR_WIDTH,
LOOKUP_MEM_DATA_WIDTH => LOOKUP_MEM_DATA_WIDTH
)
Port map(
--Port A (write interface) -> Processor
mem_in_wenable => (others => '0'),
mem_in_addr => (others => '0'),
mem_in_data => (others => '0'),
mem_in_clk => '0',
--Port B (read interface) -> Lookup module
mem_out_enable => mem2lookup_enable,
mem_out_addr => mem2lookup_addr,
mem_out_data => mem2lookup_data,
mem_out_clk => rx_path_clock
);
input_queue : rx_path_input_queue
Generic map(
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
NR_PORTS => NR_PORTS,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_IQ_FIFOS => NR_IQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
Port map(
clk => rx_path_clock,
reset => rx_path_reset,
-- input interface data
iq_in_mac_data => rx_in_data,
iq_in_mac_valid => rx_in_valid,
iq_in_mac_last => rx_in_last,
iq_in_mac_error => rx_in_error,
-- input interface control
iq_in_lu_ports => lookup2iq_ports_sig,
iq_in_lu_prio => lookup2iq_prio_sig,
iq_in_lu_skip => lookup2iq_skip_sig,
iq_in_lu_timestamp => lookup2iq_timestamp,
iq_in_lu_valid => lookup2iq_valid_sig,
-- output interface arbitration
iq_out_ports_req => rx_out_ports_req,
iq_out_prio => rx_out_prio,
iq_out_timestamp => rx_out_timestamp,
iq_out_length => rx_out_length,
iq_out_ports_gnt => rx_out_ports_gnt,
-- output interface data
iq_out_data => rx_out_data,
iq_out_last => rx_out_last,
iq_out_valid => rx_out_valid
);
end rtl;
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 11.11.2013 14:33:32
-- Design Name:
-- Module Name: switch_port_0_rx_path - rtl
--
-- Description: This is the input port to the switch fabric
-- it consists of following modules:
-- - header extraction: extract the destination mac address from the current frame
-- - lookup module and lookup memory: determine the output ports for each incoming frame
-- - input queue module: merge the data and control path, store frame in memory and request access to crossbar matrix
--
-- further information can found in file rxpath.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity switch_port_rx_path is
Generic (
RECEIVER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
PORT_ID : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
DEST_ADDR_WIDTH : integer := 48;
LOOKUP_MEM_ADDR_WIDTH : integer := 9;
LOOKUP_MEM_DATA_WIDTH : integer := 64
);
Port (
rx_path_clock : in std_logic;
rx_path_resetn : in std_logic;
-- mac to rx_path interface
rx_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
rx_in_valid : in std_logic;
rx_in_last : in std_logic;
rx_in_error : in std_logic;
-- rx_path interface to fabric
rx_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
rx_out_valid : out std_logic;
rx_out_last : out std_logic;
rx_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
rx_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
rx_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
rx_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
rx_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0);
-- timestamp
rx_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0)
);
end switch_port_rx_path;
architecture rtl of switch_port_rx_path is
component rx_path_header_extraction
Generic (
RECEIVER_DATA_WIDTH : integer;
DEST_ADDR_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface
hext_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
hext_in_valid : in std_logic;
hext_in_last : in std_logic;
hext_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- output interface
hext_out_dest : out std_logic_vector(DEST_ADDR_WIDTH-1 downto 0);
hext_out_vlan_enable : out std_logic;
hext_out_vlan_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
hext_out_valid : out std_logic;
hext_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
hext_out_ready : in std_logic
);
end component;
component rx_path_lookup
Generic (
DEST_MAC_WIDTH : integer;
NR_PORTS : integer;
PORT_ID : integer;
LOOKUP_MEM_ADDR_WIDTH : integer;
LOOKUP_MEM_DATA_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface
lookup_in_dest : in std_logic_vector(DEST_ADDR_WIDTH-1 downto 0);
lookup_in_vlan_enable : in std_logic;
lookup_in_vlan_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
lookup_in_valid : in std_logic;
lookup_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
lookup_in_ready : out std_logic;
-- output interface
lookup_out_ports : out std_logic_vector(NR_PORTS-1 downto 0);
lookup_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
lookup_out_skip : out std_logic;
lookup_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
lookup_out_valid : out std_logic;
-- lookup memory interface
mem_enable : out std_logic;
mem_addr : out std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_data : in std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0)
);
end component;
component rx_path_lookup_memory
Generic (
LOOKUP_MEM_ADDR_WIDTH : integer;
LOOKUP_MEM_DATA_WIDTH : integer
);
Port (
--Port A -> Processor
mem_in_wenable : in std_logic_vector(0 downto 0);
mem_in_addr : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_in_data : in std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
mem_in_clk : in std_logic;
--Port B -> Lookup module
mem_out_enable : in std_logic; --opt port
mem_out_addr : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_out_data : out std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
mem_out_clk : in std_logic
);
end component;
component rx_path_input_queue
Generic (
RECEIVER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface data
iq_in_mac_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
iq_in_mac_valid : in std_logic;
iq_in_mac_last : in std_logic;
iq_in_mac_error : in std_logic;
-- input interface control
iq_in_lu_ports : in std_logic_vector(NR_PORTS-1 downto 0);
iq_in_lu_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
iq_in_lu_skip : in std_logic;
iq_in_lu_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
iq_in_lu_valid : in std_logic;
-- output interface arbitration
iq_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
iq_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
iq_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
iq_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
iq_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0);
-- output interface data
iq_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
iq_out_last : out std_logic;
iq_out_valid : out std_logic
);
end component;
signal hext2lookup_dest : std_logic_vector(DEST_ADDR_WIDTH-1 downto 0);
signal hext2lookup_vlan_enable : std_logic;
signal hext2lookup_vlan_prio : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal hext2lookup_valid : std_logic;
signal hext2lookup_timestamp : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal hext2lookup_ready : std_logic;
signal mem2lookup_enable : std_logic;
signal mem2lookup_addr : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem2lookup_data : std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
signal lookup2iq_ports_sig : std_logic_vector(NR_PORTS-1 downto 0);
signal lookup2iq_prio_sig : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal lookup2iq_skip_sig : std_logic;
signal lookup2iq_timestamp : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal lookup2iq_valid_sig : std_logic;
signal rx_path_reset : std_logic;
-- attribute mark_debug : string;
-- attribute mark_debug of hext2lookup_header : signal is "true";
-- attribute mark_debug of hext2lookup_valid : signal is "true";
-- attribute mark_debug of hext2lookup_ready : signal is "true";
-- attribute mark_debug of mem2lookup_enable : signal is "true";
-- attribute mark_debug of mem2lookup_addr : signal is "true";
-- attribute mark_debug of mem2lookup_data : signal is "true";
-- attribute mark_debug of lookup2iq_ports_sig : signal is "true";
-- attribute mark_debug of lookup2iq_skip_sig : signal is "true";
-- attribute mark_debug of lookup2iq_valid_sig : signal is "true";
-- attribute mark_debug of lookup2iq_ready_sig : signal is "true";
begin
-- can be moved to a higher layer lateron
rx_path_reset <= not rx_path_resetn;
header_extraction : rx_path_header_extraction
Generic map(
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
DEST_ADDR_WIDTH => DEST_ADDR_WIDTH,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
Port map(
clk => rx_path_clock,
reset => rx_path_reset,
-- input interface
hext_in_data => rx_in_data,
hext_in_valid => rx_in_valid,
hext_in_last => rx_in_last,
hext_in_timestamp_cnt => rx_in_timestamp_cnt,
-- output interface
hext_out_dest => hext2lookup_dest,
hext_out_vlan_enable => hext2lookup_vlan_enable,
hext_out_vlan_prio => hext2lookup_vlan_prio,
hext_out_valid => hext2lookup_valid,
hext_out_timestamp => hext2lookup_timestamp,
hext_out_ready => hext2lookup_ready
);
lookup : rx_path_lookup
Generic map(
DEST_MAC_WIDTH => DEST_ADDR_WIDTH,
NR_PORTS => NR_PORTS,
PORT_ID => PORT_ID,
LOOKUP_MEM_ADDR_WIDTH => LOOKUP_MEM_ADDR_WIDTH,
LOOKUP_MEM_DATA_WIDTH => LOOKUP_MEM_DATA_WIDTH,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
Port map(
clk => rx_path_clock,
reset => rx_path_reset,
-- input interface
lookup_in_dest => hext2lookup_dest,
lookup_in_vlan_enable => hext2lookup_vlan_enable,
lookup_in_vlan_prio => hext2lookup_vlan_prio,
lookup_in_valid => hext2lookup_valid,
lookup_in_timestamp => hext2lookup_timestamp,
lookup_in_ready => hext2lookup_ready,
-- output interface
lookup_out_ports => lookup2iq_ports_sig,
lookup_out_prio => lookup2iq_prio_sig,
lookup_out_skip => lookup2iq_skip_sig,
lookup_out_timestamp => lookup2iq_timestamp,
lookup_out_valid => lookup2iq_valid_sig,
-- lookup memory interface
mem_enable => mem2lookup_enable,
mem_addr => mem2lookup_addr,
mem_data => mem2lookup_data
);
lookup_memory : rx_path_lookup_memory
Generic map(
LOOKUP_MEM_ADDR_WIDTH => LOOKUP_MEM_ADDR_WIDTH,
LOOKUP_MEM_DATA_WIDTH => LOOKUP_MEM_DATA_WIDTH
)
Port map(
--Port A (write interface) -> Processor
mem_in_wenable => (others => '0'),
mem_in_addr => (others => '0'),
mem_in_data => (others => '0'),
mem_in_clk => '0',
--Port B (read interface) -> Lookup module
mem_out_enable => mem2lookup_enable,
mem_out_addr => mem2lookup_addr,
mem_out_data => mem2lookup_data,
mem_out_clk => rx_path_clock
);
input_queue : rx_path_input_queue
Generic map(
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
NR_PORTS => NR_PORTS,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_IQ_FIFOS => NR_IQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
Port map(
clk => rx_path_clock,
reset => rx_path_reset,
-- input interface data
iq_in_mac_data => rx_in_data,
iq_in_mac_valid => rx_in_valid,
iq_in_mac_last => rx_in_last,
iq_in_mac_error => rx_in_error,
-- input interface control
iq_in_lu_ports => lookup2iq_ports_sig,
iq_in_lu_prio => lookup2iq_prio_sig,
iq_in_lu_skip => lookup2iq_skip_sig,
iq_in_lu_timestamp => lookup2iq_timestamp,
iq_in_lu_valid => lookup2iq_valid_sig,
-- output interface arbitration
iq_out_ports_req => rx_out_ports_req,
iq_out_prio => rx_out_prio,
iq_out_timestamp => rx_out_timestamp,
iq_out_length => rx_out_length,
iq_out_ports_gnt => rx_out_ports_gnt,
-- output interface data
iq_out_data => rx_out_data,
iq_out_last => rx_out_last,
iq_out_valid => rx_out_valid
);
end rtl;
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: RickWare
--
-- Create Date: 07:22:58 10/06/2010
-- Design Name: Reloj Jerarquico
-- Module Name: Top - Behavioral
-- Project Name: Reloj_Jerarquico
-- Target Devices: Nexys 2
-- Tool versions: ISE 11.4
-- Description: Reloj que despliega HH:MM:SS
-- HH y MM seran desplegados en displays de 7 segmentos
-- SS seran desplegados en los LEDs
-- Dependencies:
--
-- Revision: v1.0
-- Revision 0.01 - File Created
-- Additional Comments: Ver diagrama anexo (entregado en clase)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Top is
Port ( DecEnt : in STD_LOGIC_VECTOR (3 downto 0);
UniEnt : in STD_LOGIC_VECTOR (3 downto 0);
HorEn : in STD_LOGIC;
MinEn : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk100MHz : in STD_LOGIC;
Seg : out STD_LOGIC_VECTOR (7 downto 0);
SegOut : out STD_LOGIC_VECTOR (7 downto 0);
Disp : out STD_LOGIC_VECTOR (3 downto 0));
end Top;
architecture Behavioral of Top is
--Declaracion de todos los componentes usados en el diseño
--Componente U1: Genera una señal de 1Hz a partir del reloj de entrada de 50MHz
component Clk1Hz
port (
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkOut : out STD_LOGIC);
end component;
--Componentes U2 y U4: Contadores de 0 a 9 (BCD) usados para las Unidades de Segundo
-- y las Unidades de Minuto respectivamente
component Cont0a9
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Valor : in STD_LOGIC_VECTOR (3 downto 0);
TCO : out STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componentes U3 y U5: Contadores de 0 a 5 (BCD) usados para las Decenas de Segundo
-- y las Decenas de Minuto respectivamente
component Cont0a5
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Valor : in STD_LOGIC_VECTOR (3 downto 0);
TCO : out STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componentes U6: Contadore de 0 a 23 (BCD) usado para las Horas en formado militar (23 horas)
component Cont0a23
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ValorDec : in STD_LOGIC_VECTOR (3 downto 0);
ValorUni : in STD_LOGIC_VECTOR (3 downto 0);
Cuenta : out STD_LOGIC_VECTOR (7 downto 0));
end component;
--Componente U7: Genera una señal de Refresh para los displays de 7 segmentos multiplexados
-- a partir del reloj de entrada de 50MHz
component RefreshDisplay
port (
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkOut : out STD_LOGIC);
end component;
--Componente U8: Contador de 0 a 3 (binario) cuya cuenta determina que valor del tiempo
-- se va a desplegar. Tambien selecciona en que display sera desplegado.
component Cont0a3
port (
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (1 downto 0));
end component;
--Componente U9: Multiplexor de buses de 4-bits de 4 a 1. Su funcion es seleccionar entre
-- uno de los digitos que forman la hora HH:MM y mandarlo al decodificador
-- de BCD a 7 Segmentos
component Mux4to1
port (
DecHor : in STD_LOGIC_VECTOR (3 downto 0);
UniHor : in STD_LOGIC_VECTOR (3 downto 0);
DecMin : in STD_LOGIC_VECTOR (3 downto 0);
UniMin : in STD_LOGIC_VECTOR (3 downto 0);
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Tiempo : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componente U10: Selecciona el Display a encender, mandando un 0 logico a su Anodo
component SelAnodo
port (
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Anodo : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componente U11: Decodificador de BCD a 7 Segmentos
component DecBCD7Seg
port (
BCD : in STD_LOGIC_VECTOR (3 downto 0);
Seg : out STD_LOGIC_VECTOR (7 downto 0));
end component;
--Declaracion de todas las señales embebidas (verde y azul en su esquematico), sufijo "_int"
--Señales embebidas de 1-bit
signal EnHoras_int : STD_LOGIC;
signal EnDecMin_int : STD_LOGIC;
signal EnUniMin_int : STD_LOGIC;
signal EnSeg_int : STD_LOGIC;
signal EnDecSeg_int : STD_LOGIC;
signal Clk1Hz_int : STD_LOGIC;
signal TCODecMin_int : STD_LOGIC;
signal TCOUniMin_int : STD_LOGIC;
signal TCODecSeg_int : STD_LOGIC;
signal TCOUniSeg_int : STD_LOGIC;
signal ClkRefresh_int : STD_LOGIC;
--Señales embebidas de mas de 1-bit
signal Hor_int : STD_LOGIC_VECTOR (7 downto 0);
signal DecMin_int : STD_LOGIC_VECTOR (3 downto 0);
signal UniMin_int : STD_LOGIC_VECTOR (3 downto 0);
signal Tiempo_int : STD_LOGIC_VECTOR (3 downto 0);
signal Sel_int : STD_LOGIC_VECTOR (1 downto 0);
begin
--Instanciar los componentes (alambrar los componentes)
--Se usara el metodo corto in Instantiation
U1 : Clk1Hz
port map (
Rst,
Clk100MHz,
Clk1HZ_int);
U2 : Cont0a9
port map (
EnSeg_int,
Clk1Hz_int,
Rst,
Clk100MHz,
"0000",
TCOUniSeg_int,
SegOut(3 downto 0));
U3 : Cont0a5
port map (
EnSeg_int,
EnDecSeg_int,
Rst,
Clk100MHz,
"0000",
TCODecSeg_int,
SegOut(7 downto 4));
U4 : Cont0a9
port map (
MinEn,
EnUniMin_int,
Rst,
Clk100MHz,
UniEnt,
TCOUniMin_int,
UniMin_int);
U5 : Cont0a5
port map (
MinEn,
EnDecMin_int,
Rst,
Clk100MHz,
DecEnt,
TCODecMin_int,
DecMin_int);
U6 : Cont0a23
port map (
HorEn,
EnHoras_int,
Rst,
Clk100MHz,
DecEnt,
UniEnt,
Hor_int);
U7 : RefreshDisplay
port map (
Rst,
Clk100MHz,
ClkRefresh_int);
U8 : Cont0a3
port map (
ClkRefresh_int,
Rst,
Clk100MHz,
Sel_int);
U9 : Mux4to1
port map (
Hor_int (7 downto 4),
Hor_int (3 downto 0),
DecMin_int,
UniMin_int,
Sel_int,
Tiempo_int);
U10 : SelAnodo
port map (
Sel_int,
Disp);
U11 : DecBCD7Seg
port map (
Tiempo_int,
Seg);
--Instanciar las compuertas
EnHoras_int <= EnDecMin_int and TCODecMin_int and Clk1Hz_int;
EnDecMin_int <= EnUniMin_int and TCOUniMin_int and Clk1Hz_int;
EnUniMin_int <= TCOUniSeg_int and TCODecSeg_int and Clk1Hz_int;
EnSeg_int <= HorEn or MinEn;
EnDecSeg_int <= TCOUniSeg_int and Clk1Hz_int;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: RickWare
--
-- Create Date: 07:22:58 10/06/2010
-- Design Name: Reloj Jerarquico
-- Module Name: Top - Behavioral
-- Project Name: Reloj_Jerarquico
-- Target Devices: Nexys 2
-- Tool versions: ISE 11.4
-- Description: Reloj que despliega HH:MM:SS
-- HH y MM seran desplegados en displays de 7 segmentos
-- SS seran desplegados en los LEDs
-- Dependencies:
--
-- Revision: v1.0
-- Revision 0.01 - File Created
-- Additional Comments: Ver diagrama anexo (entregado en clase)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Top is
Port ( DecEnt : in STD_LOGIC_VECTOR (3 downto 0);
UniEnt : in STD_LOGIC_VECTOR (3 downto 0);
HorEn : in STD_LOGIC;
MinEn : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk100MHz : in STD_LOGIC;
Seg : out STD_LOGIC_VECTOR (7 downto 0);
SegOut : out STD_LOGIC_VECTOR (7 downto 0);
Disp : out STD_LOGIC_VECTOR (3 downto 0));
end Top;
architecture Behavioral of Top is
--Declaracion de todos los componentes usados en el diseño
--Componente U1: Genera una señal de 1Hz a partir del reloj de entrada de 50MHz
component Clk1Hz
port (
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkOut : out STD_LOGIC);
end component;
--Componentes U2 y U4: Contadores de 0 a 9 (BCD) usados para las Unidades de Segundo
-- y las Unidades de Minuto respectivamente
component Cont0a9
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Valor : in STD_LOGIC_VECTOR (3 downto 0);
TCO : out STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componentes U3 y U5: Contadores de 0 a 5 (BCD) usados para las Decenas de Segundo
-- y las Decenas de Minuto respectivamente
component Cont0a5
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Valor : in STD_LOGIC_VECTOR (3 downto 0);
TCO : out STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componentes U6: Contadore de 0 a 23 (BCD) usado para las Horas en formado militar (23 horas)
component Cont0a23
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ValorDec : in STD_LOGIC_VECTOR (3 downto 0);
ValorUni : in STD_LOGIC_VECTOR (3 downto 0);
Cuenta : out STD_LOGIC_VECTOR (7 downto 0));
end component;
--Componente U7: Genera una señal de Refresh para los displays de 7 segmentos multiplexados
-- a partir del reloj de entrada de 50MHz
component RefreshDisplay
port (
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkOut : out STD_LOGIC);
end component;
--Componente U8: Contador de 0 a 3 (binario) cuya cuenta determina que valor del tiempo
-- se va a desplegar. Tambien selecciona en que display sera desplegado.
component Cont0a3
port (
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (1 downto 0));
end component;
--Componente U9: Multiplexor de buses de 4-bits de 4 a 1. Su funcion es seleccionar entre
-- uno de los digitos que forman la hora HH:MM y mandarlo al decodificador
-- de BCD a 7 Segmentos
component Mux4to1
port (
DecHor : in STD_LOGIC_VECTOR (3 downto 0);
UniHor : in STD_LOGIC_VECTOR (3 downto 0);
DecMin : in STD_LOGIC_VECTOR (3 downto 0);
UniMin : in STD_LOGIC_VECTOR (3 downto 0);
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Tiempo : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componente U10: Selecciona el Display a encender, mandando un 0 logico a su Anodo
component SelAnodo
port (
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Anodo : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componente U11: Decodificador de BCD a 7 Segmentos
component DecBCD7Seg
port (
BCD : in STD_LOGIC_VECTOR (3 downto 0);
Seg : out STD_LOGIC_VECTOR (7 downto 0));
end component;
--Declaracion de todas las señales embebidas (verde y azul en su esquematico), sufijo "_int"
--Señales embebidas de 1-bit
signal EnHoras_int : STD_LOGIC;
signal EnDecMin_int : STD_LOGIC;
signal EnUniMin_int : STD_LOGIC;
signal EnSeg_int : STD_LOGIC;
signal EnDecSeg_int : STD_LOGIC;
signal Clk1Hz_int : STD_LOGIC;
signal TCODecMin_int : STD_LOGIC;
signal TCOUniMin_int : STD_LOGIC;
signal TCODecSeg_int : STD_LOGIC;
signal TCOUniSeg_int : STD_LOGIC;
signal ClkRefresh_int : STD_LOGIC;
--Señales embebidas de mas de 1-bit
signal Hor_int : STD_LOGIC_VECTOR (7 downto 0);
signal DecMin_int : STD_LOGIC_VECTOR (3 downto 0);
signal UniMin_int : STD_LOGIC_VECTOR (3 downto 0);
signal Tiempo_int : STD_LOGIC_VECTOR (3 downto 0);
signal Sel_int : STD_LOGIC_VECTOR (1 downto 0);
begin
--Instanciar los componentes (alambrar los componentes)
--Se usara el metodo corto in Instantiation
U1 : Clk1Hz
port map (
Rst,
Clk100MHz,
Clk1HZ_int);
U2 : Cont0a9
port map (
EnSeg_int,
Clk1Hz_int,
Rst,
Clk100MHz,
"0000",
TCOUniSeg_int,
SegOut(3 downto 0));
U3 : Cont0a5
port map (
EnSeg_int,
EnDecSeg_int,
Rst,
Clk100MHz,
"0000",
TCODecSeg_int,
SegOut(7 downto 4));
U4 : Cont0a9
port map (
MinEn,
EnUniMin_int,
Rst,
Clk100MHz,
UniEnt,
TCOUniMin_int,
UniMin_int);
U5 : Cont0a5
port map (
MinEn,
EnDecMin_int,
Rst,
Clk100MHz,
DecEnt,
TCODecMin_int,
DecMin_int);
U6 : Cont0a23
port map (
HorEn,
EnHoras_int,
Rst,
Clk100MHz,
DecEnt,
UniEnt,
Hor_int);
U7 : RefreshDisplay
port map (
Rst,
Clk100MHz,
ClkRefresh_int);
U8 : Cont0a3
port map (
ClkRefresh_int,
Rst,
Clk100MHz,
Sel_int);
U9 : Mux4to1
port map (
Hor_int (7 downto 4),
Hor_int (3 downto 0),
DecMin_int,
UniMin_int,
Sel_int,
Tiempo_int);
U10 : SelAnodo
port map (
Sel_int,
Disp);
U11 : DecBCD7Seg
port map (
Tiempo_int,
Seg);
--Instanciar las compuertas
EnHoras_int <= EnDecMin_int and TCODecMin_int and Clk1Hz_int;
EnDecMin_int <= EnUniMin_int and TCOUniMin_int and Clk1Hz_int;
EnUniMin_int <= TCOUniSeg_int and TCODecSeg_int and Clk1Hz_int;
EnSeg_int <= HorEn or MinEn;
EnDecSeg_int <= TCOUniSeg_int and Clk1Hz_int;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: RickWare
--
-- Create Date: 07:22:58 10/06/2010
-- Design Name: Reloj Jerarquico
-- Module Name: Top - Behavioral
-- Project Name: Reloj_Jerarquico
-- Target Devices: Nexys 2
-- Tool versions: ISE 11.4
-- Description: Reloj que despliega HH:MM:SS
-- HH y MM seran desplegados en displays de 7 segmentos
-- SS seran desplegados en los LEDs
-- Dependencies:
--
-- Revision: v1.0
-- Revision 0.01 - File Created
-- Additional Comments: Ver diagrama anexo (entregado en clase)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Top is
Port ( DecEnt : in STD_LOGIC_VECTOR (3 downto 0);
UniEnt : in STD_LOGIC_VECTOR (3 downto 0);
HorEn : in STD_LOGIC;
MinEn : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk100MHz : in STD_LOGIC;
Seg : out STD_LOGIC_VECTOR (7 downto 0);
SegOut : out STD_LOGIC_VECTOR (7 downto 0);
Disp : out STD_LOGIC_VECTOR (3 downto 0));
end Top;
architecture Behavioral of Top is
--Declaracion de todos los componentes usados en el diseño
--Componente U1: Genera una señal de 1Hz a partir del reloj de entrada de 50MHz
component Clk1Hz
port (
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkOut : out STD_LOGIC);
end component;
--Componentes U2 y U4: Contadores de 0 a 9 (BCD) usados para las Unidades de Segundo
-- y las Unidades de Minuto respectivamente
component Cont0a9
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Valor : in STD_LOGIC_VECTOR (3 downto 0);
TCO : out STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componentes U3 y U5: Contadores de 0 a 5 (BCD) usados para las Decenas de Segundo
-- y las Decenas de Minuto respectivamente
component Cont0a5
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Valor : in STD_LOGIC_VECTOR (3 downto 0);
TCO : out STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componentes U6: Contadore de 0 a 23 (BCD) usado para las Horas en formado militar (23 horas)
component Cont0a23
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ValorDec : in STD_LOGIC_VECTOR (3 downto 0);
ValorUni : in STD_LOGIC_VECTOR (3 downto 0);
Cuenta : out STD_LOGIC_VECTOR (7 downto 0));
end component;
--Componente U7: Genera una señal de Refresh para los displays de 7 segmentos multiplexados
-- a partir del reloj de entrada de 50MHz
component RefreshDisplay
port (
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkOut : out STD_LOGIC);
end component;
--Componente U8: Contador de 0 a 3 (binario) cuya cuenta determina que valor del tiempo
-- se va a desplegar. Tambien selecciona en que display sera desplegado.
component Cont0a3
port (
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (1 downto 0));
end component;
--Componente U9: Multiplexor de buses de 4-bits de 4 a 1. Su funcion es seleccionar entre
-- uno de los digitos que forman la hora HH:MM y mandarlo al decodificador
-- de BCD a 7 Segmentos
component Mux4to1
port (
DecHor : in STD_LOGIC_VECTOR (3 downto 0);
UniHor : in STD_LOGIC_VECTOR (3 downto 0);
DecMin : in STD_LOGIC_VECTOR (3 downto 0);
UniMin : in STD_LOGIC_VECTOR (3 downto 0);
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Tiempo : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componente U10: Selecciona el Display a encender, mandando un 0 logico a su Anodo
component SelAnodo
port (
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Anodo : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componente U11: Decodificador de BCD a 7 Segmentos
component DecBCD7Seg
port (
BCD : in STD_LOGIC_VECTOR (3 downto 0);
Seg : out STD_LOGIC_VECTOR (7 downto 0));
end component;
--Declaracion de todas las señales embebidas (verde y azul en su esquematico), sufijo "_int"
--Señales embebidas de 1-bit
signal EnHoras_int : STD_LOGIC;
signal EnDecMin_int : STD_LOGIC;
signal EnUniMin_int : STD_LOGIC;
signal EnSeg_int : STD_LOGIC;
signal EnDecSeg_int : STD_LOGIC;
signal Clk1Hz_int : STD_LOGIC;
signal TCODecMin_int : STD_LOGIC;
signal TCOUniMin_int : STD_LOGIC;
signal TCODecSeg_int : STD_LOGIC;
signal TCOUniSeg_int : STD_LOGIC;
signal ClkRefresh_int : STD_LOGIC;
--Señales embebidas de mas de 1-bit
signal Hor_int : STD_LOGIC_VECTOR (7 downto 0);
signal DecMin_int : STD_LOGIC_VECTOR (3 downto 0);
signal UniMin_int : STD_LOGIC_VECTOR (3 downto 0);
signal Tiempo_int : STD_LOGIC_VECTOR (3 downto 0);
signal Sel_int : STD_LOGIC_VECTOR (1 downto 0);
begin
--Instanciar los componentes (alambrar los componentes)
--Se usara el metodo corto in Instantiation
U1 : Clk1Hz
port map (
Rst,
Clk100MHz,
Clk1HZ_int);
U2 : Cont0a9
port map (
EnSeg_int,
Clk1Hz_int,
Rst,
Clk100MHz,
"0000",
TCOUniSeg_int,
SegOut(3 downto 0));
U3 : Cont0a5
port map (
EnSeg_int,
EnDecSeg_int,
Rst,
Clk100MHz,
"0000",
TCODecSeg_int,
SegOut(7 downto 4));
U4 : Cont0a9
port map (
MinEn,
EnUniMin_int,
Rst,
Clk100MHz,
UniEnt,
TCOUniMin_int,
UniMin_int);
U5 : Cont0a5
port map (
MinEn,
EnDecMin_int,
Rst,
Clk100MHz,
DecEnt,
TCODecMin_int,
DecMin_int);
U6 : Cont0a23
port map (
HorEn,
EnHoras_int,
Rst,
Clk100MHz,
DecEnt,
UniEnt,
Hor_int);
U7 : RefreshDisplay
port map (
Rst,
Clk100MHz,
ClkRefresh_int);
U8 : Cont0a3
port map (
ClkRefresh_int,
Rst,
Clk100MHz,
Sel_int);
U9 : Mux4to1
port map (
Hor_int (7 downto 4),
Hor_int (3 downto 0),
DecMin_int,
UniMin_int,
Sel_int,
Tiempo_int);
U10 : SelAnodo
port map (
Sel_int,
Disp);
U11 : DecBCD7Seg
port map (
Tiempo_int,
Seg);
--Instanciar las compuertas
EnHoras_int <= EnDecMin_int and TCODecMin_int and Clk1Hz_int;
EnDecMin_int <= EnUniMin_int and TCOUniMin_int and Clk1Hz_int;
EnUniMin_int <= TCOUniSeg_int and TCODecSeg_int and Clk1Hz_int;
EnSeg_int <= HorEn or MinEn;
EnDecSeg_int <= TCOUniSeg_int and Clk1Hz_int;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: RickWare
--
-- Create Date: 07:22:58 10/06/2010
-- Design Name: Reloj Jerarquico
-- Module Name: Top - Behavioral
-- Project Name: Reloj_Jerarquico
-- Target Devices: Nexys 2
-- Tool versions: ISE 11.4
-- Description: Reloj que despliega HH:MM:SS
-- HH y MM seran desplegados en displays de 7 segmentos
-- SS seran desplegados en los LEDs
-- Dependencies:
--
-- Revision: v1.0
-- Revision 0.01 - File Created
-- Additional Comments: Ver diagrama anexo (entregado en clase)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Top is
Port ( DecEnt : in STD_LOGIC_VECTOR (3 downto 0);
UniEnt : in STD_LOGIC_VECTOR (3 downto 0);
HorEn : in STD_LOGIC;
MinEn : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk100MHz : in STD_LOGIC;
Seg : out STD_LOGIC_VECTOR (7 downto 0);
SegOut : out STD_LOGIC_VECTOR (7 downto 0);
Disp : out STD_LOGIC_VECTOR (3 downto 0));
end Top;
architecture Behavioral of Top is
--Declaracion de todos los componentes usados en el diseño
--Componente U1: Genera una señal de 1Hz a partir del reloj de entrada de 50MHz
component Clk1Hz
port (
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkOut : out STD_LOGIC);
end component;
--Componentes U2 y U4: Contadores de 0 a 9 (BCD) usados para las Unidades de Segundo
-- y las Unidades de Minuto respectivamente
component Cont0a9
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Valor : in STD_LOGIC_VECTOR (3 downto 0);
TCO : out STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componentes U3 y U5: Contadores de 0 a 5 (BCD) usados para las Decenas de Segundo
-- y las Decenas de Minuto respectivamente
component Cont0a5
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Valor : in STD_LOGIC_VECTOR (3 downto 0);
TCO : out STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componentes U6: Contadore de 0 a 23 (BCD) usado para las Horas en formado militar (23 horas)
component Cont0a23
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ValorDec : in STD_LOGIC_VECTOR (3 downto 0);
ValorUni : in STD_LOGIC_VECTOR (3 downto 0);
Cuenta : out STD_LOGIC_VECTOR (7 downto 0));
end component;
--Componente U7: Genera una señal de Refresh para los displays de 7 segmentos multiplexados
-- a partir del reloj de entrada de 50MHz
component RefreshDisplay
port (
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkOut : out STD_LOGIC);
end component;
--Componente U8: Contador de 0 a 3 (binario) cuya cuenta determina que valor del tiempo
-- se va a desplegar. Tambien selecciona en que display sera desplegado.
component Cont0a3
port (
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (1 downto 0));
end component;
--Componente U9: Multiplexor de buses de 4-bits de 4 a 1. Su funcion es seleccionar entre
-- uno de los digitos que forman la hora HH:MM y mandarlo al decodificador
-- de BCD a 7 Segmentos
component Mux4to1
port (
DecHor : in STD_LOGIC_VECTOR (3 downto 0);
UniHor : in STD_LOGIC_VECTOR (3 downto 0);
DecMin : in STD_LOGIC_VECTOR (3 downto 0);
UniMin : in STD_LOGIC_VECTOR (3 downto 0);
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Tiempo : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componente U10: Selecciona el Display a encender, mandando un 0 logico a su Anodo
component SelAnodo
port (
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Anodo : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componente U11: Decodificador de BCD a 7 Segmentos
component DecBCD7Seg
port (
BCD : in STD_LOGIC_VECTOR (3 downto 0);
Seg : out STD_LOGIC_VECTOR (7 downto 0));
end component;
--Declaracion de todas las señales embebidas (verde y azul en su esquematico), sufijo "_int"
--Señales embebidas de 1-bit
signal EnHoras_int : STD_LOGIC;
signal EnDecMin_int : STD_LOGIC;
signal EnUniMin_int : STD_LOGIC;
signal EnSeg_int : STD_LOGIC;
signal EnDecSeg_int : STD_LOGIC;
signal Clk1Hz_int : STD_LOGIC;
signal TCODecMin_int : STD_LOGIC;
signal TCOUniMin_int : STD_LOGIC;
signal TCODecSeg_int : STD_LOGIC;
signal TCOUniSeg_int : STD_LOGIC;
signal ClkRefresh_int : STD_LOGIC;
--Señales embebidas de mas de 1-bit
signal Hor_int : STD_LOGIC_VECTOR (7 downto 0);
signal DecMin_int : STD_LOGIC_VECTOR (3 downto 0);
signal UniMin_int : STD_LOGIC_VECTOR (3 downto 0);
signal Tiempo_int : STD_LOGIC_VECTOR (3 downto 0);
signal Sel_int : STD_LOGIC_VECTOR (1 downto 0);
begin
--Instanciar los componentes (alambrar los componentes)
--Se usara el metodo corto in Instantiation
U1 : Clk1Hz
port map (
Rst,
Clk100MHz,
Clk1HZ_int);
U2 : Cont0a9
port map (
EnSeg_int,
Clk1Hz_int,
Rst,
Clk100MHz,
"0000",
TCOUniSeg_int,
SegOut(3 downto 0));
U3 : Cont0a5
port map (
EnSeg_int,
EnDecSeg_int,
Rst,
Clk100MHz,
"0000",
TCODecSeg_int,
SegOut(7 downto 4));
U4 : Cont0a9
port map (
MinEn,
EnUniMin_int,
Rst,
Clk100MHz,
UniEnt,
TCOUniMin_int,
UniMin_int);
U5 : Cont0a5
port map (
MinEn,
EnDecMin_int,
Rst,
Clk100MHz,
DecEnt,
TCODecMin_int,
DecMin_int);
U6 : Cont0a23
port map (
HorEn,
EnHoras_int,
Rst,
Clk100MHz,
DecEnt,
UniEnt,
Hor_int);
U7 : RefreshDisplay
port map (
Rst,
Clk100MHz,
ClkRefresh_int);
U8 : Cont0a3
port map (
ClkRefresh_int,
Rst,
Clk100MHz,
Sel_int);
U9 : Mux4to1
port map (
Hor_int (7 downto 4),
Hor_int (3 downto 0),
DecMin_int,
UniMin_int,
Sel_int,
Tiempo_int);
U10 : SelAnodo
port map (
Sel_int,
Disp);
U11 : DecBCD7Seg
port map (
Tiempo_int,
Seg);
--Instanciar las compuertas
EnHoras_int <= EnDecMin_int and TCODecMin_int and Clk1Hz_int;
EnDecMin_int <= EnUniMin_int and TCOUniMin_int and Clk1Hz_int;
EnUniMin_int <= TCOUniSeg_int and TCODecSeg_int and Clk1Hz_int;
EnSeg_int <= HorEn or MinEn;
EnDecSeg_int <= TCOUniSeg_int and Clk1Hz_int;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: RickWare
--
-- Create Date: 07:22:58 10/06/2010
-- Design Name: Reloj Jerarquico
-- Module Name: Top - Behavioral
-- Project Name: Reloj_Jerarquico
-- Target Devices: Nexys 2
-- Tool versions: ISE 11.4
-- Description: Reloj que despliega HH:MM:SS
-- HH y MM seran desplegados en displays de 7 segmentos
-- SS seran desplegados en los LEDs
-- Dependencies:
--
-- Revision: v1.0
-- Revision 0.01 - File Created
-- Additional Comments: Ver diagrama anexo (entregado en clase)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Top is
Port ( DecEnt : in STD_LOGIC_VECTOR (3 downto 0);
UniEnt : in STD_LOGIC_VECTOR (3 downto 0);
HorEn : in STD_LOGIC;
MinEn : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk100MHz : in STD_LOGIC;
Seg : out STD_LOGIC_VECTOR (7 downto 0);
SegOut : out STD_LOGIC_VECTOR (7 downto 0);
Disp : out STD_LOGIC_VECTOR (3 downto 0));
end Top;
architecture Behavioral of Top is
--Declaracion de todos los componentes usados en el diseño
--Componente U1: Genera una señal de 1Hz a partir del reloj de entrada de 50MHz
component Clk1Hz
port (
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkOut : out STD_LOGIC);
end component;
--Componentes U2 y U4: Contadores de 0 a 9 (BCD) usados para las Unidades de Segundo
-- y las Unidades de Minuto respectivamente
component Cont0a9
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Valor : in STD_LOGIC_VECTOR (3 downto 0);
TCO : out STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componentes U3 y U5: Contadores de 0 a 5 (BCD) usados para las Decenas de Segundo
-- y las Decenas de Minuto respectivamente
component Cont0a5
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Valor : in STD_LOGIC_VECTOR (3 downto 0);
TCO : out STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componentes U6: Contadore de 0 a 23 (BCD) usado para las Horas en formado militar (23 horas)
component Cont0a23
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ValorDec : in STD_LOGIC_VECTOR (3 downto 0);
ValorUni : in STD_LOGIC_VECTOR (3 downto 0);
Cuenta : out STD_LOGIC_VECTOR (7 downto 0));
end component;
--Componente U7: Genera una señal de Refresh para los displays de 7 segmentos multiplexados
-- a partir del reloj de entrada de 50MHz
component RefreshDisplay
port (
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkOut : out STD_LOGIC);
end component;
--Componente U8: Contador de 0 a 3 (binario) cuya cuenta determina que valor del tiempo
-- se va a desplegar. Tambien selecciona en que display sera desplegado.
component Cont0a3
port (
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (1 downto 0));
end component;
--Componente U9: Multiplexor de buses de 4-bits de 4 a 1. Su funcion es seleccionar entre
-- uno de los digitos que forman la hora HH:MM y mandarlo al decodificador
-- de BCD a 7 Segmentos
component Mux4to1
port (
DecHor : in STD_LOGIC_VECTOR (3 downto 0);
UniHor : in STD_LOGIC_VECTOR (3 downto 0);
DecMin : in STD_LOGIC_VECTOR (3 downto 0);
UniMin : in STD_LOGIC_VECTOR (3 downto 0);
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Tiempo : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componente U10: Selecciona el Display a encender, mandando un 0 logico a su Anodo
component SelAnodo
port (
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Anodo : out STD_LOGIC_VECTOR (3 downto 0));
end component;
--Componente U11: Decodificador de BCD a 7 Segmentos
component DecBCD7Seg
port (
BCD : in STD_LOGIC_VECTOR (3 downto 0);
Seg : out STD_LOGIC_VECTOR (7 downto 0));
end component;
--Declaracion de todas las señales embebidas (verde y azul en su esquematico), sufijo "_int"
--Señales embebidas de 1-bit
signal EnHoras_int : STD_LOGIC;
signal EnDecMin_int : STD_LOGIC;
signal EnUniMin_int : STD_LOGIC;
signal EnSeg_int : STD_LOGIC;
signal EnDecSeg_int : STD_LOGIC;
signal Clk1Hz_int : STD_LOGIC;
signal TCODecMin_int : STD_LOGIC;
signal TCOUniMin_int : STD_LOGIC;
signal TCODecSeg_int : STD_LOGIC;
signal TCOUniSeg_int : STD_LOGIC;
signal ClkRefresh_int : STD_LOGIC;
--Señales embebidas de mas de 1-bit
signal Hor_int : STD_LOGIC_VECTOR (7 downto 0);
signal DecMin_int : STD_LOGIC_VECTOR (3 downto 0);
signal UniMin_int : STD_LOGIC_VECTOR (3 downto 0);
signal Tiempo_int : STD_LOGIC_VECTOR (3 downto 0);
signal Sel_int : STD_LOGIC_VECTOR (1 downto 0);
begin
--Instanciar los componentes (alambrar los componentes)
--Se usara el metodo corto in Instantiation
U1 : Clk1Hz
port map (
Rst,
Clk100MHz,
Clk1HZ_int);
U2 : Cont0a9
port map (
EnSeg_int,
Clk1Hz_int,
Rst,
Clk100MHz,
"0000",
TCOUniSeg_int,
SegOut(3 downto 0));
U3 : Cont0a5
port map (
EnSeg_int,
EnDecSeg_int,
Rst,
Clk100MHz,
"0000",
TCODecSeg_int,
SegOut(7 downto 4));
U4 : Cont0a9
port map (
MinEn,
EnUniMin_int,
Rst,
Clk100MHz,
UniEnt,
TCOUniMin_int,
UniMin_int);
U5 : Cont0a5
port map (
MinEn,
EnDecMin_int,
Rst,
Clk100MHz,
DecEnt,
TCODecMin_int,
DecMin_int);
U6 : Cont0a23
port map (
HorEn,
EnHoras_int,
Rst,
Clk100MHz,
DecEnt,
UniEnt,
Hor_int);
U7 : RefreshDisplay
port map (
Rst,
Clk100MHz,
ClkRefresh_int);
U8 : Cont0a3
port map (
ClkRefresh_int,
Rst,
Clk100MHz,
Sel_int);
U9 : Mux4to1
port map (
Hor_int (7 downto 4),
Hor_int (3 downto 0),
DecMin_int,
UniMin_int,
Sel_int,
Tiempo_int);
U10 : SelAnodo
port map (
Sel_int,
Disp);
U11 : DecBCD7Seg
port map (
Tiempo_int,
Seg);
--Instanciar las compuertas
EnHoras_int <= EnDecMin_int and TCODecMin_int and Clk1Hz_int;
EnDecMin_int <= EnUniMin_int and TCOUniMin_int and Clk1Hz_int;
EnUniMin_int <= TCOUniSeg_int and TCODecSeg_int and Clk1Hz_int;
EnSeg_int <= HorEn or MinEn;
EnDecSeg_int <= TCOUniSeg_int and Clk1Hz_int;
end Behavioral;
|
entity e is end entity;
architecture a of e is
procedure f(x, y, z : integer);
signal x : bit;
begin
f(1, 2, 3 + 5);
assert x'active;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc479.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00479ent IS
END c03s02b01x01p19n01i00479ent;
ARCHITECTURE c03s02b01x01p19n01i00479arch OF c03s02b01x01p19n01i00479ent IS
type integer_vector is array (natural range <>) of integer;
function resolution5(i:in integer_vector) return integer is
variable temp : integer := 3;
begin
return temp;
end resolution5;
subtype integer_state is resolution5 integer;
constant C66 : integer_state := 3;
function complex_scalar(s : integer_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return integer_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : integer_state;
signal S2 : integer_state;
signal S3 : integer_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00479"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00479 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00479arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc479.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00479ent IS
END c03s02b01x01p19n01i00479ent;
ARCHITECTURE c03s02b01x01p19n01i00479arch OF c03s02b01x01p19n01i00479ent IS
type integer_vector is array (natural range <>) of integer;
function resolution5(i:in integer_vector) return integer is
variable temp : integer := 3;
begin
return temp;
end resolution5;
subtype integer_state is resolution5 integer;
constant C66 : integer_state := 3;
function complex_scalar(s : integer_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return integer_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : integer_state;
signal S2 : integer_state;
signal S3 : integer_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00479"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00479 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00479arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc479.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00479ent IS
END c03s02b01x01p19n01i00479ent;
ARCHITECTURE c03s02b01x01p19n01i00479arch OF c03s02b01x01p19n01i00479ent IS
type integer_vector is array (natural range <>) of integer;
function resolution5(i:in integer_vector) return integer is
variable temp : integer := 3;
begin
return temp;
end resolution5;
subtype integer_state is resolution5 integer;
constant C66 : integer_state := 3;
function complex_scalar(s : integer_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return integer_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : integer_state;
signal S2 : integer_state;
signal S3 : integer_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00479"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00479 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00479arch;
|
--------------------------------------------------------------------------------
-- company:
-- engineer:
--
-- vhdl test bench created by ise for module: random_number
--
-- dependencies:
--
-- revision:
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_generic_Flip_Flop is
end tb_generic_Flip_Flop;
architecture arch_tb_generic_Flip_Flop of tb_generic_Flip_Flop is
constant data_width_g : natural := 8;
constant input_1 : natural := 7;
constant input_2 : natural := 10;
-- clock period definitions
constant clk_period : time := 10 ns;
-- component declaration for the unit under test (uut)
component generic_Flip_Flop is
generic(
data_width_g : natural := 8 -- Width of the Flip-Flop bus
);
port(
---- Global Inputs
Clk : in std_logic; -- main clock
Reset_n : in std_logic; -- reset synchrone, enable on LOW level
---- Inputs
Locked : in std_logic; -- lock the Flip-Flop, the Load is disable
Load : in std_logic; -- Load the input
Input_Data : in std_logic_vector ( (data_width_g-1) downto 0); --Input of the Flip-Flop
---- Outputs
Output_Data : out std_logic_vector ( (data_width_g-1) downto 0) -- Outputs of the Flip-Flop
);
end component generic_Flip_Flop;
--inputs
signal Clk : std_logic ;
signal reset_n : std_logic ;
signal Locked : std_logic ;
signal Load : std_logic ;
signal Input_Data : std_logic_vector((data_width_g-1) downto 0);
--outputs
signal Output_Data : std_logic_vector((data_width_g-1) downto 0);
--std_logic_vector(to_unsigned(0, n_bits_g))
begin
-- instantiate the unit under test (uut)
uut: generic_Flip_Flop
generic map (
data_width_g => data_width_g -- Width of the Flip-Flop bus
)
port map(
---- Global Inputs
Clk => Clk,
Reset_n => Reset_n,
---- Inputs
Locked => Locked,
Load => Load,
Input_Data => Input_Data,
---- Outputs
Output_Data => Output_Data
);
-- clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- reset process
reset_proc: process
begin
reset_n <= '0';
wait for clk_period;
reset_n <= '1';
wait;
end process;
-- load process
load_proc: process
begin
Load <= '0';
wait for clk_period;
Load <='1';
wait for clk_period;
end process;
-- locked process
locked_proc: process
begin
Locked <= '0';
wait for 2*clk_period;
Locked <='1';
wait for 2*clk_period;
end process;
-- input process
input_proc: process
begin
Input_Data <= std_logic_vector(to_unsigned(input_1, Input_Data'length ));
wait for 10*clk_period;
Input_Data <= std_logic_vector(to_unsigned(input_2, Input_Data'length ));
wait;
end process;
end arch_tb_generic_Flip_Flop;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04:12:05 11/16/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_register_16bit.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: register_16bit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_register_16bit IS
END tb_register_16bit;
ARCHITECTURE behavior OF tb_register_16bit IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT register_16bit
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(15 downto 0) := (others => '0');
signal en : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal Q : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: register_16bit PORT MAP (
D => D,
Q => Q,
en => en,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
en <= '0', '1' after 10 ns;
D <= "0101101011110000", "0000000000000000" after 9 ns, "0101101011110000" after 19ns, "0000000000000000" after 29ns;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04:12:05 11/16/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_register_16bit.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: register_16bit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_register_16bit IS
END tb_register_16bit;
ARCHITECTURE behavior OF tb_register_16bit IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT register_16bit
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(15 downto 0) := (others => '0');
signal en : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal Q : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: register_16bit PORT MAP (
D => D,
Q => Q,
en => en,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
en <= '0', '1' after 10 ns;
D <= "0101101011110000", "0000000000000000" after 9 ns, "0101101011110000" after 19ns, "0000000000000000" after 29ns;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04:12:05 11/16/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_register_16bit.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: register_16bit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_register_16bit IS
END tb_register_16bit;
ARCHITECTURE behavior OF tb_register_16bit IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT register_16bit
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(15 downto 0) := (others => '0');
signal en : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal Q : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: register_16bit PORT MAP (
D => D,
Q => Q,
en => en,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
en <= '0', '1' after 10 ns;
D <= "0101101011110000", "0000000000000000" after 9 ns, "0101101011110000" after 19ns, "0000000000000000" after 29ns;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04:12:05 11/16/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_register_16bit.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: register_16bit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_register_16bit IS
END tb_register_16bit;
ARCHITECTURE behavior OF tb_register_16bit IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT register_16bit
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(15 downto 0) := (others => '0');
signal en : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal Q : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: register_16bit PORT MAP (
D => D,
Q => Q,
en => en,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
en <= '0', '1' after 10 ns;
D <= "0101101011110000", "0000000000000000" after 9 ns, "0101101011110000" after 19ns, "0000000000000000" after 29ns;
END;
|
-------------------------------------------------------------------------------
-- Ce module prends un fil en entrée, 1 si c'est un tick, 0 sinon
-- Sa sortie vaut successivement 0 puis 1 tous les 10 ticks
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
-- diode h10
ENTITY h10 IS
PORT(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
T : in STD_LOGIC;
S : out STD_LOGIC
);
END h10;
ARCHITECTURE montage OF h10 IS
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
TYPE T_CMD IS (INIT, COUNT, NOOP);
-- la commande courante
signal CMD : T_CMD;
-- registre de comptagne 10 => 9 => ... => 0 => 10 => ...
signal C : unsigned(3 downto 0);
signal R : STD_LOGIC ;
-- boolean vaux 1 si C est à 0, 0 sinon
signal C_IS_ZERO: STD_LOGIC;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
type STATE_TYPE is (
ST_INIT, ST_COUNT
);
signal state : STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
process (reset, clk)
begin
IF reset = '1' THEN
C <= to_unsigned(10, 4);
R <= '1';
ELSIF clk'event and clk = '1' then
IF CMD = INIT THEN
C <= to_unsigned(10, 4);
R <= not(R);
ELSIF CMD = COUNT AND T = '1' THEN
C <= C - 1;
END IF;
end if;
end process;
C_IS_ZERO <= '1' WHEN C = 0 ELSE '0' ;
S <= R ;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: T
-- Outputs: S, CMD
-------------------------------------------------------------------------------
-- fonction de transitition
process (reset, clk)
begin
if reset = '1' then
state <= ST_INIT;
elsif clk'event and clk = '1' then
case state is
when ST_INIT =>
state <= ST_COUNT ;
when ST_COUNT =>
IF C_IS_ZERO = '1' THEN
state <= ST_INIT ;
END IF ;
end case;
end if;
end process;
-- fonction de sortie
with state select CMD <=
INIT when ST_INIT,
COUNT when ST_COUNT
;
end montage;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_315 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_315;
architecture augh of add_315 is
signal carry_inA : std_logic_vector(21 downto 0);
signal carry_inB : std_logic_vector(21 downto 0);
signal carry_res : std_logic_vector(21 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(20 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_315 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_315;
architecture augh of add_315 is
signal carry_inA : std_logic_vector(21 downto 0);
signal carry_inB : std_logic_vector(21 downto 0);
signal carry_res : std_logic_vector(21 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(20 downto 1);
end architecture;
|
-- $Id: sn_humanio_demu.vhd 414 2011-10-11 19:38:12Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio_demu - syn
-- Description: All BTN, SWI, LED handling for atlys
--
-- Dependencies: bpgen/bp_swibtnled
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-10-10 413 13.1 O40d xc3s1000-4 67 66 0 55 s 6.1 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-11 414 1.0.1 take care of RESET BTN being active low
-- 2011-10-10 413 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity sn_humanio_demu is -- human i/o handling: swi,btn,led only
generic (
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
BTN : out slv4; -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv6; -- pad-i: buttons
O_LED : out slv8 -- pad-o: leds
);
end sn_humanio_demu;
architecture syn of sn_humanio_demu is
constant c_mode_led : slv2 := "00";
constant c_mode_dp : slv2 := "01";
constant c_mode_datl : slv2 := "10";
constant c_mode_dath : slv2 := "11";
type regs_type is record
mode : slv2; -- current mode
cnt : slv9; -- msec counter
up_1 : slbit; -- btn up last cycle
dn_1 : slbit; -- btn dn last cycle
led : slv8; -- led state
end record regs_type;
constant regs_init : regs_type := (
c_mode_led, -- mode
(others=>'0'), -- cnt
'0','0', -- up_1, dn_1
(others=>'0') -- led
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal BTN_HW : slv6 := (others=>'0');
signal LED_HW : slv8 := (others=>'0');
begin
HIO : bp_swibtnled
generic map (
SWIDTH => 8,
BWIDTH => 6,
LWIDTH => 8,
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN_HW,
LED => LED_HW,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, LED, DSP_DAT, DSP_DP, BTN_HW)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibtn : slv4 := (others=>'0');
variable iup : slbit := '0';
variable idn : slbit := '0';
variable ipuls : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ibtn(0) := not BTN_HW(5); -- RESET button is act. low !
ibtn(1) := BTN_HW(1);
ibtn(2) := BTN_HW(4);
ibtn(3) := BTN_HW(3);
iup := BTN_HW(0);
idn := BTN_HW(2);
ipuls := '0';
n.up_1 := iup;
n.dn_1 := idn;
if iup='0' and idn='0' then
n.cnt := (others=>'0');
else
if CE_MSEC = '1' then
n.cnt := slv(unsigned(r.cnt) + 1);
if r.cnt = "111111111" then
ipuls := '1';
end if;
end if;
end if;
if iup='1' or idn='1' then
n.led := (others=>'0');
case r.mode is
when c_mode_led => n.led(0) := '1';
when c_mode_dp => n.led(1) := '1';
when c_mode_datl => n.led(2) := '1';
when c_mode_dath => n.led(3) := '1';
when others => null;
end case;
if iup='1' and (r.up_1='0' or ipuls='1') then
n.mode := slv(unsigned(r.mode) + 1);
elsif idn='1' and (r.dn_1='0' or ipuls='1') then
n.mode := slv(unsigned(r.mode) - 1);
end if;
else
case r.mode is
when c_mode_led => n.led := LED;
when c_mode_dp => n.led := "0000" & DSP_DP;
when c_mode_datl => n.led := DSP_DAT( 7 downto 0);
when c_mode_dath => n.led := DSP_DAT(15 downto 8);
when others => null;
end case;
end if;
N_REGS <= n;
BTN <= ibtn;
LED_HW <= r.led;
end process proc_next;
end syn;
|
-- $Id: sn_humanio_demu.vhd 414 2011-10-11 19:38:12Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio_demu - syn
-- Description: All BTN, SWI, LED handling for atlys
--
-- Dependencies: bpgen/bp_swibtnled
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-10-10 413 13.1 O40d xc3s1000-4 67 66 0 55 s 6.1 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-11 414 1.0.1 take care of RESET BTN being active low
-- 2011-10-10 413 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity sn_humanio_demu is -- human i/o handling: swi,btn,led only
generic (
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
BTN : out slv4; -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv6; -- pad-i: buttons
O_LED : out slv8 -- pad-o: leds
);
end sn_humanio_demu;
architecture syn of sn_humanio_demu is
constant c_mode_led : slv2 := "00";
constant c_mode_dp : slv2 := "01";
constant c_mode_datl : slv2 := "10";
constant c_mode_dath : slv2 := "11";
type regs_type is record
mode : slv2; -- current mode
cnt : slv9; -- msec counter
up_1 : slbit; -- btn up last cycle
dn_1 : slbit; -- btn dn last cycle
led : slv8; -- led state
end record regs_type;
constant regs_init : regs_type := (
c_mode_led, -- mode
(others=>'0'), -- cnt
'0','0', -- up_1, dn_1
(others=>'0') -- led
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal BTN_HW : slv6 := (others=>'0');
signal LED_HW : slv8 := (others=>'0');
begin
HIO : bp_swibtnled
generic map (
SWIDTH => 8,
BWIDTH => 6,
LWIDTH => 8,
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN_HW,
LED => LED_HW,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, LED, DSP_DAT, DSP_DP, BTN_HW)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibtn : slv4 := (others=>'0');
variable iup : slbit := '0';
variable idn : slbit := '0';
variable ipuls : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ibtn(0) := not BTN_HW(5); -- RESET button is act. low !
ibtn(1) := BTN_HW(1);
ibtn(2) := BTN_HW(4);
ibtn(3) := BTN_HW(3);
iup := BTN_HW(0);
idn := BTN_HW(2);
ipuls := '0';
n.up_1 := iup;
n.dn_1 := idn;
if iup='0' and idn='0' then
n.cnt := (others=>'0');
else
if CE_MSEC = '1' then
n.cnt := slv(unsigned(r.cnt) + 1);
if r.cnt = "111111111" then
ipuls := '1';
end if;
end if;
end if;
if iup='1' or idn='1' then
n.led := (others=>'0');
case r.mode is
when c_mode_led => n.led(0) := '1';
when c_mode_dp => n.led(1) := '1';
when c_mode_datl => n.led(2) := '1';
when c_mode_dath => n.led(3) := '1';
when others => null;
end case;
if iup='1' and (r.up_1='0' or ipuls='1') then
n.mode := slv(unsigned(r.mode) + 1);
elsif idn='1' and (r.dn_1='0' or ipuls='1') then
n.mode := slv(unsigned(r.mode) - 1);
end if;
else
case r.mode is
when c_mode_led => n.led := LED;
when c_mode_dp => n.led := "0000" & DSP_DP;
when c_mode_datl => n.led := DSP_DAT( 7 downto 0);
when c_mode_dath => n.led := DSP_DAT(15 downto 8);
when others => null;
end case;
end if;
N_REGS <= n;
BTN <= ibtn;
LED_HW <= r.led;
end process proc_next;
end syn;
|
----------------------------------------------------------------------------------
-- sampler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Produces samples from input applying a programmable divider to the clock.
-- Sampling rate can be calculated by:
--
-- r = f / (d + 1)
--
-- Where r is the sampling rate, f is the clock frequency and d is the value
-- programmed into the divider register.
--
-- As of version 0.6 sampling on an external clock is also supported. If external
-- is set '1', the external clock will be used to sample data. (Divider is
-- ignored for this.)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sampler is
Port ( input : in STD_LOGIC_VECTOR (31 downto 0); -- 32 input channels
clock : in STD_LOGIC; -- internal clock
exClock : in std_logic; -- external clock
external : in std_logic; -- clock selection
data : in STD_LOGIC_VECTOR (23 downto 0); -- configuration data
wrDivider : in STD_LOGIC; -- write divider register
sample : out STD_LOGIC_VECTOR (31 downto 0); -- sampled data
ready : out STD_LOGIC; -- new sample ready
ready50 : out std_logic); -- low rate sample signal with 50% duty cycle
end sampler;
architecture Behavioral of sampler is
signal divider, counter : std_logic_vector (23 downto 0);
signal lastExClock, syncExClock : std_logic;
begin
-- sample data
process(clock)
begin
if rising_edge(clock) then
syncExClock <= exClock;
if wrDivider = '1' then
divider <= data(23 downto 0);
counter <= (others => '0');
ready <= '0';
elsif external = '1' then
if syncExClock = '0' and lastExClock = '1' then
-- sample <= input(31 downto 10) & exClock & lastExClock & input(7 downto 0);
ready <= '1';
else
sample <= input;
ready <= '0';
end if;
lastExClock <= syncExClock;
elsif counter = divider then
sample <= input;
counter <= (others => '0');
ready <= '1';
else
counter <= counter + 1;
ready <= '0';
end if;
end if;
end process;
-- generate ready50 50% duty cycle sample signal
process(clock)
begin
if rising_edge(clock) then
if counter = divider then
ready50 <= '1';
elsif counter(22 downto 0) = divider(23 downto 1) then
ready50 <= '0';
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- sampler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Produces samples from input applying a programmable divider to the clock.
-- Sampling rate can be calculated by:
--
-- r = f / (d + 1)
--
-- Where r is the sampling rate, f is the clock frequency and d is the value
-- programmed into the divider register.
--
-- As of version 0.6 sampling on an external clock is also supported. If external
-- is set '1', the external clock will be used to sample data. (Divider is
-- ignored for this.)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sampler is
Port ( input : in STD_LOGIC_VECTOR (31 downto 0); -- 32 input channels
clock : in STD_LOGIC; -- internal clock
exClock : in std_logic; -- external clock
external : in std_logic; -- clock selection
data : in STD_LOGIC_VECTOR (23 downto 0); -- configuration data
wrDivider : in STD_LOGIC; -- write divider register
sample : out STD_LOGIC_VECTOR (31 downto 0); -- sampled data
ready : out STD_LOGIC; -- new sample ready
ready50 : out std_logic); -- low rate sample signal with 50% duty cycle
end sampler;
architecture Behavioral of sampler is
signal divider, counter : std_logic_vector (23 downto 0);
signal lastExClock, syncExClock : std_logic;
begin
-- sample data
process(clock)
begin
if rising_edge(clock) then
syncExClock <= exClock;
if wrDivider = '1' then
divider <= data(23 downto 0);
counter <= (others => '0');
ready <= '0';
elsif external = '1' then
if syncExClock = '0' and lastExClock = '1' then
-- sample <= input(31 downto 10) & exClock & lastExClock & input(7 downto 0);
ready <= '1';
else
sample <= input;
ready <= '0';
end if;
lastExClock <= syncExClock;
elsif counter = divider then
sample <= input;
counter <= (others => '0');
ready <= '1';
else
counter <= counter + 1;
ready <= '0';
end if;
end if;
end process;
-- generate ready50 50% duty cycle sample signal
process(clock)
begin
if rising_edge(clock) then
if counter = divider then
ready50 <= '1';
elsif counter(22 downto 0) = divider(23 downto 1) then
ready50 <= '0';
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- sampler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Produces samples from input applying a programmable divider to the clock.
-- Sampling rate can be calculated by:
--
-- r = f / (d + 1)
--
-- Where r is the sampling rate, f is the clock frequency and d is the value
-- programmed into the divider register.
--
-- As of version 0.6 sampling on an external clock is also supported. If external
-- is set '1', the external clock will be used to sample data. (Divider is
-- ignored for this.)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sampler is
Port ( input : in STD_LOGIC_VECTOR (31 downto 0); -- 32 input channels
clock : in STD_LOGIC; -- internal clock
exClock : in std_logic; -- external clock
external : in std_logic; -- clock selection
data : in STD_LOGIC_VECTOR (23 downto 0); -- configuration data
wrDivider : in STD_LOGIC; -- write divider register
sample : out STD_LOGIC_VECTOR (31 downto 0); -- sampled data
ready : out STD_LOGIC; -- new sample ready
ready50 : out std_logic); -- low rate sample signal with 50% duty cycle
end sampler;
architecture Behavioral of sampler is
signal divider, counter : std_logic_vector (23 downto 0);
signal lastExClock, syncExClock : std_logic;
begin
-- sample data
process(clock)
begin
if rising_edge(clock) then
syncExClock <= exClock;
if wrDivider = '1' then
divider <= data(23 downto 0);
counter <= (others => '0');
ready <= '0';
elsif external = '1' then
if syncExClock = '0' and lastExClock = '1' then
-- sample <= input(31 downto 10) & exClock & lastExClock & input(7 downto 0);
ready <= '1';
else
sample <= input;
ready <= '0';
end if;
lastExClock <= syncExClock;
elsif counter = divider then
sample <= input;
counter <= (others => '0');
ready <= '1';
else
counter <= counter + 1;
ready <= '0';
end if;
end if;
end process;
-- generate ready50 50% duty cycle sample signal
process(clock)
begin
if rising_edge(clock) then
if counter = divider then
ready50 <= '1';
elsif counter(22 downto 0) = divider(23 downto 1) then
ready50 <= '0';
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- sampler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Produces samples from input applying a programmable divider to the clock.
-- Sampling rate can be calculated by:
--
-- r = f / (d + 1)
--
-- Where r is the sampling rate, f is the clock frequency and d is the value
-- programmed into the divider register.
--
-- As of version 0.6 sampling on an external clock is also supported. If external
-- is set '1', the external clock will be used to sample data. (Divider is
-- ignored for this.)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sampler is
Port ( input : in STD_LOGIC_VECTOR (31 downto 0); -- 32 input channels
clock : in STD_LOGIC; -- internal clock
exClock : in std_logic; -- external clock
external : in std_logic; -- clock selection
data : in STD_LOGIC_VECTOR (23 downto 0); -- configuration data
wrDivider : in STD_LOGIC; -- write divider register
sample : out STD_LOGIC_VECTOR (31 downto 0); -- sampled data
ready : out STD_LOGIC; -- new sample ready
ready50 : out std_logic); -- low rate sample signal with 50% duty cycle
end sampler;
architecture Behavioral of sampler is
signal divider, counter : std_logic_vector (23 downto 0);
signal lastExClock, syncExClock : std_logic;
begin
-- sample data
process(clock)
begin
if rising_edge(clock) then
syncExClock <= exClock;
if wrDivider = '1' then
divider <= data(23 downto 0);
counter <= (others => '0');
ready <= '0';
elsif external = '1' then
if syncExClock = '0' and lastExClock = '1' then
-- sample <= input(31 downto 10) & exClock & lastExClock & input(7 downto 0);
ready <= '1';
else
sample <= input;
ready <= '0';
end if;
lastExClock <= syncExClock;
elsif counter = divider then
sample <= input;
counter <= (others => '0');
ready <= '1';
else
counter <= counter + 1;
ready <= '0';
end if;
end if;
end process;
-- generate ready50 50% duty cycle sample signal
process(clock)
begin
if rising_edge(clock) then
if counter = divider then
ready50 <= '1';
elsif counter(22 downto 0) = divider(23 downto 1) then
ready50 <= '0';
end if;
end if;
end process;
end Behavioral;
|
-- $Id: pdp11_aunit.vhd 1203 2019-08-19 21:41:03Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_aunit - syn
-- Description: pdp11: arithmetic unit for data (aunit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2019.1; ghdl 0.18-0.36
-- Revision History:
-- Date Rev Version Comment
-- 2019-08-17 1203 1.1.2 fix for ghdl V0.36 -Whide warnings
-- 2014-08-10 581 1.1.1 use c_cc_f_*
-- 2010-09-18 300 1.1 renamed from abox
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
-- arithmetic unit for data, usage:
-- ADD: SRC + DST + 0 (dst+src)
-- SUB: ~SRC + DST + 1 (dst-src)
-- ADC: 0 + DST + CI (dst+ci)
-- SBC: ~0 + DST + ~CI (dst-ci)
-- CMP: SRC + ~DST + 1 (src-dst)
-- COM: 0 + ~DST + 0 (~dst)
-- NEG: 0 + ~DST + 1 (-dst)
-- INC: 0 + DST + 1 (dst+1)
-- DEC: ~0 + DST + 0 (dst-1)
-- CLR: 0 + 0 + 0 (0)
-- SOB: SRC + ~0 + 0 (src-1)
entity pdp11_aunit is -- arithmetic unit for data (aunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CI : in slbit; -- carry flag in
SRCMOD : in slv2; -- src modifier mode
DSTMOD : in slv2; -- dst modifier mode
CIMOD : in slv2; -- ci modifier mode
CC1OP : in slbit; -- use cc modes (1 op instruction)
CCMODE : in slv3; -- cc mode
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end pdp11_aunit;
architecture syn of pdp11_aunit is
-- --------------------------------------
begin
process (DSRC, DDST, CI, CIMOD, CC1OP, CCMODE, SRCMOD, DSTMOD, BYTOP)
variable msrc : slv16 := (others=>'0'); -- effective src data
variable mdst : slv16 := (others=>'0'); -- effective dst data
variable mci : slbit := '0'; -- effective ci
variable sum : slv16 := (others=>'0'); -- sum
variable co8 : slbit := '0'; -- co 8 bit
variable co16 : slbit := '0'; -- co 16 bit
variable nno : slbit := '0'; -- local no
variable nzo : slbit := '0'; -- local zo
variable nvo : slbit := '0'; -- local vo
variable nco : slbit := '0'; -- local co
variable src_msb : slbit := '0'; -- msb from src (bit 15 or 7)
variable dst_msb : slbit := '0'; -- msb from dst (bit 15 or 7)
variable sum_msb : slbit := '0'; -- msb from sum (bit 15 or 7)
alias NO : slbit is CCOUT(c_cc_f_n);
alias ZO : slbit is CCOUT(c_cc_f_z);
alias VO : slbit is CCOUT(c_cc_f_v);
alias CO : slbit is CCOUT(c_cc_f_c);
-- procedure do_add8_ci_co: 8 bit adder with carry in and carry out
-- implemented following the recommended pattern for XST ISE V8.1
procedure do_add8_ci_co (
variable pa : in slv8; -- input a
variable pb : in slv8; -- input b
variable pci : in slbit; -- carry in
variable psum : out slv8; -- sum out
variable pco : out slbit -- carry out
) is
variable tmp: slv9;
begin
tmp := conv_std_logic_vector((conv_integer(pa) + conv_integer(pb) +
conv_integer(pci)),9);
psum := tmp(7 downto 0);
pco := tmp(8);
end procedure do_add8_ci_co;
begin
case SRCMOD is
when c_aunit_mod_pass => msrc := DSRC;
when c_aunit_mod_inv => msrc := not DSRC;
when c_aunit_mod_zero => msrc := (others=>'0');
when c_aunit_mod_one => msrc := (others=>'1');
when others => null;
end case;
case DSTMOD is
when c_aunit_mod_pass => mdst := DDST;
when c_aunit_mod_inv => mdst := not DDST;
when c_aunit_mod_zero => mdst := (others=>'0');
when c_aunit_mod_one => mdst := (others=>'1');
when others => null;
end case;
case CIMOD is
when c_aunit_mod_pass => mci := CI;
when c_aunit_mod_inv => mci := not CI;
when c_aunit_mod_zero => mci := '0';
when c_aunit_mod_one => mci := '1';
when others => null;
end case;
do_add8_ci_co(msrc(7 downto 0), mdst(7 downto 0), mci,
sum(7 downto 0), co8);
do_add8_ci_co(msrc(15 downto 8), mdst(15 downto 8), co8,
sum(15 downto 8), co16);
DOUT <= sum;
-- V ('overflow) bit set if
-- ADD : both operants of same sign but has result opposite sign
-- SUB : both operants of opposide sign and sign source equals sign result
-- CMP : both operants of opposide sign and sign dest. equals sign result
nno := '0';
nzo := '0';
nvo := '0';
nco := '0';
if BYTOP = '1' then
nno := sum(7);
if unsigned(sum(7 downto 0)) = 0 then
nzo := '1';
else
nzo := '0';
end if;
nco := co8;
src_msb := DSRC(7);
dst_msb := DDST(7);
sum_msb := sum(7);
else
nno := sum(15);
if unsigned(sum) = 0 then
nzo := '1';
else
nzo := '0';
end if;
nco := co16;
src_msb := DSRC(15);
dst_msb := DDST(15);
sum_msb := sum(15);
end if;
-- the logic for 2 operand V+C is ugly. It is reverse engineered from
-- the MOD's the operation type.
if CC1OP = '0' then -- 2 operand cases
if unsigned(CIMOD) = unsigned(c_aunit_mod_zero) then -- case ADD
nvo := not(src_msb xor dst_msb) and (src_msb xor sum_msb);
else
if unsigned(SRCMOD) = unsigned(c_aunit_mod_inv) then -- case SUB
nvo := (src_msb xor dst_msb) and not (src_msb xor sum_msb);
else -- case CMP
nvo := (src_msb xor dst_msb) and not (dst_msb xor sum_msb);
end if;
nco := not nco; -- invert C for SUB and CMP
end if;
else -- 1 operand cases
case CCMODE is
when c_aunit_ccmode_clr|c_aunit_ccmode_tst =>
nvo := '0'; -- force v=0 for tst and clr
nco := '0'; -- force c=0 for tst and clr
when c_aunit_ccmode_com =>
nvo := '0'; -- force v=0 for com
nco := '1'; -- force c=1 for com
when c_aunit_ccmode_inc =>
nvo := sum_msb and not dst_msb;
nco := CI; -- C not affected for INC
when c_aunit_ccmode_dec =>
nvo := not sum_msb and dst_msb;
nco := CI; -- C not affected for DEC
when c_aunit_ccmode_neg =>
nvo := sum_msb and dst_msb;
nco := not nzo;
when c_aunit_ccmode_adc =>
nvo := sum_msb and not dst_msb;
when c_aunit_ccmode_sbc =>
nvo := not sum_msb and dst_msb;
nco := not nco;
when others => null;
end case;
end if;
NO <= nno;
ZO <= nzo;
VO <= nvo;
CO <= nco;
end process;
end syn;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity instruction_memory is
port(address : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(11 downto 0);
immediate_addr : in std_logic_vector(5 downto 0);
immediate_out : out std_logic_vector(31 downto 0));
end instruction_memory;
architecture Behavioral of instruction_memory is
type instruction_data_type is array (4095 downto 0) of std_logic_vector(11 downto 0); --4 kB of data memory
signal instruction_data : instruction_data_type;
type immediate_data_type is array (63 downto 0) of std_logic_vector(31 downto 0);
signal immediate_data : immediate_data_type;
signal address_short : std_logic_vector(11 downto 0);
begin
address_short <= address(11 downto 0);
data_out <= instruction_data(conv_integer(unsigned(address_short)));
immediate_out <= immediate_data(conv_integer(unsigned(immediate_addr)));
--Assigning the immediate memory
immediate_data(0) <= x"00000001";
immediate_data(1) <= x"00000003";
immediate_data(2) <= x"40000000";
immediate_data(3) <= x"10000000";
immediate_data(4) <= x"0000007D";
--Assigning the instruction memory
instruction_data(0) <= "000000000000"; --Address zero is zero
instruction_data(1) <= "010100000000"; --PUSH immediate at addr 0 (1)
instruction_data(2) <= "010101000000"; --DUP
instruction_data(3) <= "000001000000"; --ADD
instruction_data(4) <= "010100000000"; --PUSH immediate at addr 0 (1)
instruction_data(5) <= "010100000000"; --PUSH immediate at addr 0 (1)
instruction_data(6) <= "010100000000"; --PUSH immediate at addr 0 (1)
instruction_data(7) <= "000001000000"; --ADD
instruction_data(8) <= "000001000000"; --ADD
instruction_data(9) <= "000001000000"; --ADD
instruction_data(10) <= "010100000001"; --PUSH immediate at addr 1 (3)
instruction_data(11) <= "110001000000"; --WR_MEM
instruction_data(12) <= "010100000010"; --PUSH immediate at addr 2 (2.0)
instruction_data(13) <= "010100000011"; --PUSH immediate at addr 3 (0.5)
instruction_data(14) <= "001011000000"; --FPMUL
instruction_data(15) <= "010100000001"; --PUSH immediate at addr 1 (3)
instruction_data(16) <= "110000000000"; --RD_MEM
instruction_data(17) <= "010000000000"; --DROP
instruction_data(18) <= "010000000000"; --DROP
instruction_data(19) <= "110010000000"; --RD_PRT
instruction_data(20) <= "110011000000"; --WR_PRT
instruction_data(21) <= "010100000001"; --PUSH immediate at addr 1 (3)
instruction_data(22) <= "110100000000"; --RD_PIN
instruction_data(23) <= "010100000000"; --PUSH immediate at addr 0 (1)
instruction_data(24) <= "110101000000"; --WR_PIN
instruction_data(25) <= "010100000000"; --PUSH immediate at addr 0 (1)
instruction_data(26) <= "010100000100"; --PUSH immediate at addr 4 (125) --addr for jp
instruction_data(27) <= "100011000000"; --PSHPC
instruction_data(28) <= "100000000000"; --JP to 125
instruction_data(29) <= "010100000001"; --PUSH immediate at addr 1 (3)
instruction_data(30) <= "000110000000"; --CP
instruction_data(31) <= "010100000001"; --PUSH immediate at addr 1 (3)
instruction_data(32) <= "010100000100"; --PUSH immediate at addr 4 (125)
instruction_data(33) <= "100001000000"; --BRN (if e0 is greater than e1)
instruction_data(125) <= "010100000000"; --PUSH immediate at addr 0 (1)
instruction_data(126) <= "000001000000"; --ADD
instruction_data(127) <= "100010000000"; --RET
end Behavioral;
|
------------------------------------------------------------------------------
-- Copyright (C) 2009 , Emmanuel Amadio
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of the authors nor the names of its contributors
-- may be used to endorse or promote products derived from this software
-- without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_core.vhd
--!
--! @brief fpgaMSP430 Core
--
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; -- standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; -- for the signed, unsigned types and arithmetic ops
use ieee.math_real.all;
use work.fmsp_core_package.all;
use work.fmsp_functions.all;
entity fmsp_core is
generic (
PMEM_SIZE : integer := 32768; -- Program Memory Size
DMEM_SIZE : integer := 16384; -- Data Memory Size
PER_SIZE : integer := 16384; -- Peripheral Memory Size
DMA_IF_EN : boolean := false; -- Include/Exclude DMA interface support
IRQ_NR : integer := 16; -- Number of IRQs
CPUOFF_EN : boolean := false -- Wakeup condition from DMA interface
);
port (
mclk : in std_logic; -- Main system clock
mrst : in std_logic; -- Main system reset
-- Debug Interface
dbg_halt_cmd : in std_logic := '0';
dbg_halt_st : out std_logic := '0';
dbg_reg_din : out std_logic_vector(15 downto 0) := x"0000";
dbg_reg_wr : in std_logic := '0';
dbg_mem_addr : in std_logic_vector(15 downto 0);
dbg_mem_dout : in std_logic_vector(15 downto 0) := x"0000";
dbg_mem_din : out std_logic_vector(15 downto 0) := x"0000";
dbg_mem_en : in std_logic := '0';
dbg_mem_wr : in std_logic_vector(1 downto 0) := "00";
-- Execution unit memory bus
eu_mem_addr : out std_logic_vector(15 downto 0); -- Execution-Unit Memory address bus
eu_mem_en : out std_logic; -- Execution-Unit Memory bus enable
eu_mem_wr : out std_logic_vector(1 downto 0); -- Execution-Unit Memory bus write transfer
-- Frontend memory bus
fe_mem_din : out std_logic_vector(15 downto 0); -- Frontend Memory data bus input
-- DMA access
dma_addr : in std_logic_vector(15 downto 1); -- Direct Memory Access address
dma_dout : out std_logic_vector(15 downto 0); -- Direct Memory Access data output
dma_din : in std_logic_vector(15 downto 0); -- Direct Memory Access data input
dma_en : in std_logic; -- Direct Memory Access enable (high active)
dma_we : in std_logic_vector(1 downto 0); -- Direct Memory Access write byte enable (high active)
dma_priority : in std_logic; -- Direct Memory Access priority (0:low / 1:high)
dma_ready : out std_logic; -- Direct Memory Access is complete
dma_resp : out std_logic; -- Direct Memory Access response (0:Okay / 1:Error)
-- Peripheral memory
per_addr : out std_logic_vector(13 downto 0); -- Peripheral address
per_dout : in std_logic_vector(15 downto 0); -- Peripheral data output
per_din : out std_logic_vector(15 downto 0); -- Peripheral data input
per_en : out std_logic; -- Peripheral enable (high active)
per_we : out std_logic_vector(1 downto 0); -- Peripheral write byte enable (high active)
-- Program memory
pmem_addr : out std_logic_vector(f_log2(PMEM_SIZE)-2 downto 0); -- Program Memory address
pmem_dout : in std_logic_vector(15 downto 0); -- Program Memory data output
pmem_din : out std_logic_vector(15 downto 0); -- Program Memory data input (optional)
pmem_cen : out std_logic; -- Program Memory chip enable (low active)
pmem_wen : out std_logic_vector(1 downto 0); -- Program Memory write enable (low active) (optional)
-- Data memory
dmem_addr : out std_logic_vector(f_log2(DMEM_SIZE)-2 downto 0); -- Data Memory address
dmem_dout : in std_logic_vector(15 downto 0); -- Data Memory data output
dmem_din : out std_logic_vector(15 downto 0); -- Data Memory data input
dmem_cen : out std_logic; -- Data Memory chip enable (low active)
dmem_wen : out std_logic_vector(1 downto 0); -- Data Memory write byte enable (low active)
-- Non maskable interrupt
nmi_acc : out std_logic;
nmi_pnd : in std_logic;
nmi_wkup : in std_logic;
-- Watchdog interrupt
wdt_irq : in std_logic;
wdt_wkup : in std_logic;
-- Interrupts
irq : in std_logic_vector(IRQ_NR-3 downto 0); -- Maskable interrupts (14, 30 or 62)
irq_acc : out std_logic_vector(IRQ_NR-3 downto 0); -- Interrupt request accepted (one-hot signal)
cpu_en_s : in std_logic;
decode_noirq : out std_logic;
pc : out std_logic_vector(15 downto 0);
cpuoff : out std_logic;
oscoff : out std_logic;
scg1 : out std_logic
);
end entity fmsp_core;
architecture RTL of fmsp_core is
--=============================================================================
-- 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
--=============================================================================
type core_wires_type is record
inst_ad : std_logic_vector(7 downto 0);
inst_as : std_logic_vector(7 downto 0);
inst_alu : std_logic_vector(11 downto 0);
inst_bw : std_logic;
inst_irq_rst : std_logic;
inst_mov : std_logic;
inst_dest : std_logic_vector(15 downto 0);
inst_dext : std_logic_vector(15 downto 0);
inst_sext : std_logic_vector(15 downto 0);
inst_so : std_logic_vector(7 downto 0);
inst_src : std_logic_vector(15 downto 0);
inst_type : std_logic_vector(2 downto 0);
inst_jmp : std_logic_vector(7 downto 0);
exec_state : std_logic_vector(3 downto 0);
exec_done : std_logic;
cpu_halt_st : std_logic;
cpu_halt_cmd : std_logic;
-- Execution unit memory bus
eu_mem_addr : std_logic_vector(15 downto 0);
eu_mem_dout : std_logic_vector(15 downto 0);
eu_mem_din : std_logic_vector(15 downto 0);
eu_mem_wr : std_logic_vector(1 downto 0);
eu_mem_en : std_logic;
-- Frontend memory bus
fe_mem_addr : std_logic_vector(15 downto 0);
fe_mem_din : std_logic_vector(15 downto 0);
fe_mem_en : std_logic;
fe_mem_wait : std_logic;
-- Program counter
eu_pc_sw_wr : std_logic;
eu_pc_sw : std_logic_vector(15 downto 0);
fe_pc : std_logic_vector(15 downto 0);
fe_pc_nxt : std_logic_vector(15 downto 0);
cpuoff : std_logic;
oscoff : std_logic;
scg1 : std_logic;
gie : std_logic;
end record;
signal wires : core_wires_type;
begin
--=============================================================================
-- 3) FRONTEND (<=> FETCH & DECODE)
--=============================================================================
frontend_0 : fmsp_frontend
generic map(
CPUOFF_EN => CPUOFF_EN, -- Wakeup condition from DMA interface
DMA_IF_EN => DMA_IF_EN, -- Wakeup condition from DMA interface
IRQ_NR => IRQ_NR -- Number of IRQs
)
port map(
mclk => mclk, -- Main system clock
mrst => mrst, -- Main system reset
-- Memory bus
mdb_in => wires.fe_mem_din, -- Frontend Memory data bus input
mab => wires.fe_mem_addr, -- Frontend Memory address bus
mb_en => wires.fe_mem_en, -- Frontend Memory bus enable
fe_pmem_wait => wires.fe_mem_wait, -- Frontend wait for Instruction fetch
-- INPUTs
cpu_en_s => cpu_en_s, -- Enable CPU code execution (synchronous)
cpu_halt_cmd => wires.cpu_halt_cmd, -- Halt CPU command
cpuoff => wires.cpuoff, -- Turns off the CPU
dbg_reg_sel => dbg_mem_addr(3 downto 0), -- Debug selected register for rd/wr access
dma_en => dma_en, -- Direct Memory Access enable (high active)
gie => wires.gie, -- General interrupt enable
-- Interrupts
irq => irq, -- Maskable interrupts
irq_acc => irq_acc, -- Interrupt request accepted
-- Non maskable interrupt
nmi_acc => nmi_acc, -- Non-Maskable interrupt request accepted
nmi_pnd => nmi_pnd, -- Non-maskable interrupt pending
nmi_wkup => nmi_wkup, -- NMI Wakeup
-- Watchdog interrupt
wdt_irq => wdt_irq, -- Watchdog-timer interrupt
wdt_wkup => wdt_wkup, -- Watchdog Wakeup
-- OUTPUTs
cpu_halt_st => wires.cpu_halt_st, -- Halt/Run status from CPU
decode_noirq => decode_noirq, -- Frontend decode instruction
-- Decoded signals to execution unit
e_state => wires.exec_state, -- Execution state
exec_done => wires.exec_done, -- Execution completed
inst_ad => wires.inst_ad, -- Decoded Inst: destination addressing mode
inst_as => wires.inst_as, -- Decoded Inst: source addressing mode
inst_alu => wires.inst_alu, -- ALU control signals
inst_bw => wires.inst_bw, -- Decoded Inst: byte width
inst_dest => wires.inst_dest, -- Decoded Inst: destination (one hot)
inst_dext => wires.inst_dext, -- Decoded Inst: destination extended instruction word
inst_irq_rst => wires.inst_irq_rst, -- Decoded Inst: Reset interrupt
inst_jmp => wires.inst_jmp, -- Decoded Inst: Conditional jump
inst_mov => wires.inst_mov, -- Decoded Inst: mov instruction
inst_sext => wires.inst_sext, -- Decoded Inst: source extended instruction word
inst_so => wires.inst_so, -- Decoded Inst: Single-operand arithmetic
inst_src => wires.inst_src, -- Decoded Inst: source (one hot)
inst_type => wires.inst_type, -- Decoded Instruction type
-- Program counter
pc_sw => wires.eu_pc_sw, -- Program counter software value
pc_sw_wr => wires.eu_pc_sw_wr, -- Program counter software write
pc => wires.fe_pc, -- Program counter
pc_nxt => wires.fe_pc_nxt -- Next PC value (for CALL & IRQ)
);
--=============================================================================
-- 4) EXECUTION UNIT
--=============================================================================
execution_unit_0 : fmsp_execution_unit
port map(
mclk => mclk, -- Main system clock
mrst => mrst, -- Main system reset
-- INPUTs
gie => wires.gie, -- General interrupt enable
dbg_halt_st => wires.cpu_halt_st, -- Halt/Run status from CPU
dbg_mem_dout => dbg_mem_dout, -- Debug unit data output
dbg_reg_wr => dbg_reg_wr, -- Debug unit CPU register write
dbg_reg_din => dbg_reg_din, -- Debug unit CPU register data input
-- Memory bus
mdb_in => wires.eu_mem_din, -- Memory data bus input
mab => wires.eu_mem_addr, -- Memory address bus
mb_en => wires.eu_mem_en, -- Memory bus enable
mb_wr => wires.eu_mem_wr, -- Memory bus write transfer
mdb_out => wires.eu_mem_dout, -- Memory data bus output
-- Decoded signals from frontend
e_state => wires.exec_state, -- Execution state
exec_done => wires.exec_done, -- Execution completed
inst_ad => wires.inst_ad, -- Decoded Inst: destination addressing mode
inst_as => wires.inst_as, -- Decoded Inst: source addressing mode
inst_alu => wires.inst_alu, -- ALU control signals
inst_bw => wires.inst_bw, -- Decoded Inst: byte width
inst_dest => wires.inst_dest, -- Decoded Inst: destination (one hot)
inst_dext => wires.inst_dext, -- Decoded Inst: destination extended instruction word
inst_irq_rst => wires.inst_irq_rst, -- Decoded Inst: reset interrupt
inst_jmp => wires.inst_jmp, -- Decoded Inst: Conditional jump
inst_mov => wires.inst_mov, -- Decoded Inst: mov instruction
inst_sext => wires.inst_sext, -- Decoded Inst: source extended instruction word
inst_so => wires.inst_so, -- Decoded Inst: Single-operand arithmetic
inst_src => wires.inst_src, -- Decoded Inst: source (one hot)
inst_type => wires.inst_type, -- Decoded Instruction type
-- Program counter
pc => wires.fe_pc, -- Program counter
pc_nxt => wires.fe_pc_nxt, -- Next PC value (for CALL & IRQ)
pc_sw => wires.eu_pc_sw, -- Program counter software value
pc_sw_wr => wires.eu_pc_sw_wr, -- Program counter software write
-- OUTPUTs
cpuoff => wires.cpuoff, -- Turns off the CPU
oscoff => wires.oscoff, -- Turns off LFXT1 clock input
scg1 => wires.scg1 -- System clock generator 1. Turns off the SMCLK
);
--=============================================================================
-- 5) MEMORY BACKBONE
--=============================================================================
mem_backbone_0 : fmsp_mem_backbone
generic map(
PMEM_SIZE => PMEM_SIZE, -- Program Memory Size
DMEM_SIZE => DMEM_SIZE, -- Data Memory Size
PER_SIZE => PER_SIZE, -- Peripheral Memory Size
DMA_IF_EN => DMA_IF_EN -- Wakeup condition from DMA interface
)
port map(
mclk => mclk, -- Main system clock
mrst => mrst, -- Main system reset
-- INPUTs
-- OUTPUTs
cpu_halt_cmd => wires.cpu_halt_cmd, -- Halt CPU command
cpu_halt_st => wires.cpu_halt_st, -- Halt/Run status from CPU
-- Debug interface
dbg_halt_cmd => dbg_halt_cmd, -- Debug interface Halt CPU command
dbg_mem_addr => dbg_mem_addr, -- Debug address for rd/wr access
dbg_mem_dout => dbg_mem_dout, -- Debug unit data output
dbg_mem_din => dbg_mem_din, -- Debug unit Memory data input
dbg_mem_en => dbg_mem_en, -- Debug unit memory enable
dbg_mem_wr => dbg_mem_wr, -- Debug unit memory write
-- Frontend memory bus
fe_mab => wires.fe_mem_addr(15 downto 1), -- Frontend Memory address bus
fe_mdb_in => wires.fe_mem_din, -- Frontend Memory data bus input
fe_mb_en => wires.fe_mem_en, -- Frontend Memory bus enable
fe_pmem_wait => wires.fe_mem_wait, -- Frontend wait for Instruction fetch
-- Execution Unit memory bus
eu_mab => wires.eu_mem_addr(15 downto 1), -- Execution Unit Memory address bus
eu_mdb_out => wires.eu_mem_dout, -- Execution Unit Memory data bus output
eu_mdb_in => wires.eu_mem_din, -- Execution Unit Memory data bus input
eu_mb_en => wires.eu_mem_en, -- Execution Unit Memory bus enable
eu_mb_wr => wires.eu_mem_wr, -- Execution Unit Memory bus write transfer
-- DMA bus
dma_addr => dma_addr&'0', -- Direct Memory Access address
dma_dout => dma_dout, -- Direct Memory Access data output
dma_din => dma_din, -- Direct Memory Access data input
dma_en => dma_en, -- Direct Memory Access enable (high active)
dma_we => dma_we, -- Direct Memory Access write byte enable (high active)
dma_priority => dma_priority, -- Direct Memory Access priority (0:low / 1:high)
dma_ready => dma_ready, -- Direct Memory Access is complete
dma_resp => dma_resp, -- Direct Memory Access response (0:Okay / 1:Error)
-- Peripheral memory
per_addr => per_addr, -- Peripheral address
per_dout => per_dout, -- Peripheral data output
per_din => per_din, -- Peripheral data input
per_en => per_en, -- Peripheral enable (high active)
per_we => per_we, -- Peripheral write enable (high active)
-- Data memory
dmem_addr => dmem_addr, -- Data Memory address
dmem_dout => dmem_dout, -- Data Memory data output
dmem_din => dmem_din, -- Data Memory data input
dmem_cen => dmem_cen, -- Data Memory chip enable (low active)
dmem_wen => dmem_wen, -- Data Memory write enable (low active)
-- Program memory
pmem_addr => pmem_addr, -- Program Memory address
pmem_dout => pmem_dout, -- Program Memory data output
pmem_din => pmem_din, -- Program Memory data input (optional)
pmem_cen => pmem_cen, -- Program Memory chip enable (low active)
pmem_wen => pmem_wen -- Program Memory write enable (low active) (optional)
);
-- Execution unit memory bus
eu_mem_addr <= wires.eu_mem_addr;
eu_mem_en <= wires.eu_mem_en;
eu_mem_wr <= wires.eu_mem_wr;
-- Frontend memory bus
fe_mem_din <= wires.fe_mem_din;
dbg_halt_st <= wires.cpu_halt_st;
cpuoff <= wires.cpuoff;
oscoff <= wires.oscoff;
pc <= wires.fe_pc;
scg1 <= wires.scg1;
end RTL; -- fmsp430
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set_nodre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set_nodre.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set_nodre is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set_nodre;
architecture implementation of axi_datamover_stbs_set_nodre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
function funct_256bit_stbs_set (strb_3 : std_logic_vector(2 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 5;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 24 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "111" =>
lvar_num_set := 24;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_256bit_stbs_set;
function funct_512bit_stbs_set (strb_3 : std_logic_vector(6 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 6;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 56 := 0;
begin
case strb_3 is
-- when "0000000" =>
-- lvar_num_set := 0;
------- 1 bit --------------------------
when "0000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "0000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "0000111" =>
lvar_num_set := 24;
when "0001111" =>
lvar_num_set := 32;
when "0011111" =>
lvar_num_set := 40;
when "0111111" =>
lvar_num_set := 48;
when "1111111" =>
lvar_num_set := 56;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_512bit_stbs_set;
function funct_1024bit_stbs_set (strb_3 : std_logic_vector(14 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 7;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 120 := 0;
begin
case strb_3 is
------- 1 bit --------------------------
when "000000000000001" =>
lvar_num_set := 8;
------- 2 bit --------------------------
when "000000000000011" =>
lvar_num_set := 16;
------- 3 bit --------------------------
when "000000000000111" =>
lvar_num_set := 24;
when "000000000001111" =>
lvar_num_set := 32;
when "000000000011111" =>
lvar_num_set := 40;
when "000000000111111" =>
lvar_num_set := 48;
when "000000001111111" =>
lvar_num_set := 56;
when "000000011111111" =>
lvar_num_set := 64;
when "000000111111111" =>
lvar_num_set := 72;
when "000001111111111" =>
lvar_num_set := 80;
when "000011111111111" =>
lvar_num_set := 88;
when "000111111111111" =>
lvar_num_set := 96;
when "001111111111111" =>
lvar_num_set := 104;
when "011111111111111" =>
lvar_num_set := 112;
when "111111111111111" =>
lvar_num_set := 120;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_1024bit_stbs_set;
-- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
--
-- Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
--
--
-- Variable lvar_num_set : Integer range 0 to 8 := 0;
--
-- begin
--
-- case strb_8 is
--
---- ------- 1 bit --------------------------
-- when "00000001" | "00000010" | "00000100" | "00001000" |
-- "00010000" | "00100000" | "01000000" | "10000000" =>
--
-- lvar_num_set := 1;
--
--
-- ------- 2 bit --------------------------
-- when "00000011" | "00000110" | "00001100" | "00011000" |
-- "00110000" | "01100000" | "11000000" =>
--
-- lvar_num_set := 2;
--
--
-- ------- 3 bit --------------------------
-- when "00000111" | "00001110" | "00011100" | "00111000" |
-- "01110000" | "11100000" =>
--
-- lvar_num_set := 3;
--
--
-- ------- 4 bit --------------------------
-- when "00001111" | "00011110" | "00111100" | "01111000" |
-- "11110000" =>
--
-- lvar_num_set := 4;
--
--
-- ------- 5 bit --------------------------
-- when "00011111" | "00111110" | "01111100" | "11111000" =>
--
-- lvar_num_set := 5;
--
--
-- ------- 6 bit --------------------------
-- when "00111111" | "01111110" | "11111100" =>
--
-- lvar_num_set := 6;
--
--
-- ------- 7 bit --------------------------
-- when "01111111" | "11111110" =>
--
-- lvar_num_set := 7;
--
--
-- ------- 8 bit --------------------------
-- when "11111111" =>
--
-- lvar_num_set := 8;
--
--
-- ------- all zeros or sparse strobes ------
-- When others =>
--
-- lvar_num_set := 0;
--
-- end case;
--
--
-- Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
--
--
--
-- end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (2 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(4 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_256bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (6 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(5 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_512bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "0000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "0000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "0000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "0000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "0001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "0011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "0111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "1111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_total1 : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
signal lsig_new_vect : std_logic_vector (14 downto 0) := (others => '0');
signal lsig_num_new_stbs1 : unsigned(6 downto 0) := (others => '0');
signal lsig_new_vect1 : std_logic_vector (7 downto 0) := (others => '0');
signal lsig_num_new_vect1 : unsigned(3 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
-- lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
-- RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
lsig_new_vect <= sig_strb_input (120) & sig_strb_input (112)
& sig_strb_input(104) & sig_strb_input (96) & sig_strb_input (88)
& sig_strb_input(80) & sig_strb_input (72) & sig_strb_input (64)
& sig_strb_input(56) & sig_strb_input (48) & sig_strb_input (40)
& sig_strb_input(32) & sig_strb_input (24) & sig_strb_input (16) & sig_strb_input (8);
lsig_num_new_stbs1 <= funct_1024bit_stbs_set(lsig_new_vect) ;
lsig_num_new_vect1 <= funct_8bit_stbs_set(lsig_new_vect1);
lsig_num_total <= RESIZE(lsig_num_new_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_new_vect1 , RESULT_BIT_WIDTH);
process (lsig_new_vect, sig_strb_input)
begin
case lsig_new_vect is
------- 1 bit --------------------------
when "000000000000000" =>
lsig_new_vect1 <= sig_strb_input (7 downto 0);
when "000000000000001" =>
lsig_new_vect1 <= sig_strb_input (15 downto 8);
------- 2 bit --------------------------
when "000000000000011" =>
lsig_new_vect1 <= sig_strb_input (23 downto 16);
------- 3 bit --------------------------
when "000000000000111" =>
lsig_new_vect1 <= sig_strb_input (31 downto 24);
when "000000000001111" =>
lsig_new_vect1 <= sig_strb_input (39 downto 32);
when "000000000011111" =>
lsig_new_vect1 <= sig_strb_input (47 downto 40);
when "000000000111111" =>
lsig_new_vect1 <= sig_strb_input (55 downto 48);
when "000000001111111" =>
lsig_new_vect1 <= sig_strb_input (63 downto 56);
when "000000011111111" =>
lsig_new_vect1 <= sig_strb_input (71 downto 64);
when "000000111111111" =>
lsig_new_vect1 <= sig_strb_input (79 downto 72);
when "000001111111111" =>
lsig_new_vect1 <= sig_strb_input (87 downto 80);
when "000011111111111" =>
lsig_new_vect1 <= sig_strb_input (95 downto 88);
when "000111111111111" =>
lsig_new_vect1 <= sig_strb_input (103 downto 96);
when "001111111111111" =>
lsig_new_vect1 <= sig_strb_input (111 downto 104);
when "011111111111111" =>
lsig_new_vect1 <= sig_strb_input (119 downto 112);
when "111111111111111" =>
lsig_new_vect1 <= sig_strb_input (127 downto 120);
------- all zeros or sparse strobes ------
When others =>
lsig_new_vect1 <= (others => '0');
end case;
end process;
end generate GEN_128_STRB;
end implementation;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : R E S A M P L I N G
--
-- In many cases, this function does not have to be changed.
-- Only if you want/need to change/adjust the resampling algorithm
-- you can change it here.
--
-- Here the Residual Systematic Resampling Algorithm is used.
-- It is not easy to change to a complete other resampling algorithm,
-- because the framework is adjusted to use a algorithm, which
-- only uses one cycle of iterations and so without any correction cycle.
--
-- Some basic information about the resampling user function:
--
-- The particle weights are loaded into the local RAM by the Framework
-- The first 63 * 128 bytes (of 64 * 128 bytes) are filled with
-- all the particle weights needed. There will not be any space
-- between the particle weights.
--
-- The last 128 bytes are used for the resampling.
-- The user has to store two values for every particle.
-- 1. the index of the particle (as integer)
-- 2. the replication factor of the particle (as integer)
-- The ordering of this two values must not be changed,
-- because it is used later for the sampling step.
--
-- The two integer values (also known as index_type) are written
-- into the last 128 byte. Since two integer values need 8 bytes,
-- information about 16 particles can be written into the last 128 bytes
-- of the local ram before they have to be written by the Framework.
--
-- The outgoing signal write_burst has to be '1', if the the indexes
-- and replication factors should be written into the Main Memory.
-- This should only happen, if the information about 16
-- particles is resampled or the last particle has been resampled.
--
-- The incoming signal write_burst_done is equal to '1', if the
-- Framework has written the information to the Main Memory
--
-- If resampling is finished the outgoing signal finish has to be set to '1'.
-- A new run of the resampling will be started if the next particles are
-- loaded into local RAM. This is the case when the incoming signal
-- particles_loaded is equal to '1'.
--
------------------------------------------------------------------------------------
entity uf_resampling is
generic (
C_TASK_BURST_AWIDTH : integer := 11;
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- additional incoming signals
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the resampling user process
particles_loaded : in std_logic;
-- number of particles in local RAM
number_of_particles : in integer;
-- number of particles in total
number_of_particles_in_total : in integer;
-- index of first particles (the particles are sorted increasingly)
start_particle_index : in integer;
-- resampling function init
U_init : in integer;
-- address of the last 128 byte burst in local RAM
write_address : in std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
-- information if a write burst has been handled by the Framework
write_burst_done : in std_logic;
-- additional outgoing signals
-- this signal has to be set to '1', if the Framework should write
-- the last burst from local RAM into Maim Memory
write_burst : out std_logic;
-- write burst done acknowledgement
write_burst_done_ack : out std_logic;
-- number of currently written particles
written_values : out integer;
-- if every particle is resampled, this signal has to be set to '1'
finished : out std_logic
);
end uf_resampling;
architecture Behavioral of uf_resampling is
-- GRANULARITY
constant GRANULARITY :integer := 16384;
-- local RAM read/write address
signal local_ram_read_address : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
signal local_ram_write_address : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- particle counter
signal counter : integer := 0;
-- particle counter for allready resampled particles at all
signal counter_resampled_particles : integer := 0;
-- write counter (used bytes)
signal write_counter :integer := 0;
-- current particle weight
signal current_particle_weight : integer := 0;
-- signals needed for residual systematic resampling
signal temp : integer := 0;
signal fact : integer := 0; -- replication factor
signal U : integer := 0;
-- states
type t_state1 is (STATE_INIT,
STATE_LOAD_PARTICLE_1, STATE_LOAD_PARTICLE_2, STATE_LOAD_WEIGHT,
STATE_CALCULATE_REPLICATION_FACTOR_1, STATE_CALCULATE_REPLICATION_FACTOR_2,
STATE_CALCULATE_REPLICATION_FACTOR_3, STATE_CALCULATE_REPLICATION_FACTOR_4,
STATE_CALCULATE_REPLICATION_FACTOR_5, STATE_CALCULATE_REPLICATION_FACTOR_6,
STATE_WRITE_PARTICLE_INDEX, STATE_WRITE_PARTICLE_REPLICATION,
STATE_WRITE_BURST_DECISION, STATE_WRITE_BURST, STATE_WRITE_BURST_DONE_ACK,
STATE_WRITE_BURST_DONE_ACK_2, STATE_FINISH);
-- current state
signal state1 : t_state1 := STATE_INIT;
begin
-- burst ram interface is not used
-- o_RAMAddr <= (others => '0');
-- o_RAMData <= (others => '0');
-- o_RAMWE <= '0';
o_RAMClk <= clk;
state_proc : process(clk, reset)
begin
if (reset = '1') then
state1 <= STATE_INIT;
elsif rising_edge(clk) then
if init = '1' then
state1 <= STATE_INIT;
o_RAMData <= (others=>'0');
o_RAMWE <= '0';
o_RAMAddr <= (others => '0');
U <= U_init;
elsif enable = '1' then
case state1 is
when STATE_INIT =>
--! init data
local_ram_read_address <= (others => '0');
local_ram_write_address <= write_address;
counter_resampled_particles <= 0;
counter <= start_particle_index;
current_particle_weight <= 0;
temp <= 0;
fact <= 0;
--U <= U_init;
write_counter <= 0;
written_values <= 0;
write_burst <= '0';
finished <= '0';
o_RAMWE <= '0';
if (particles_loaded = '1') then
state1 <= STATE_LOAD_PARTICLE_1;
end if;
-- 0) INIT
--
-- i = 0; // current particle
-- j = 0; // current replication factor
-- k = 0; // current number of cloned particles
-- finished = 0;
--
--
-- 1) LOAD_PARTICLE_1/2, LOAD_WEIGHT
--
-- load weight of i-th particle from local memory
-- i ++;
--
--
-- 2) CALCULATE_REPLICATION_FACTOR_1-8
--
-- calculate replication factor
--
--
-- 3) WRITE_PARTICLE_INDEX, WRITE_PARTICLE_REPLICATION
--
-- write particle index + replicationfactor to local ram
--
--
-- 4) WRITE_BURST
--
-- write_burst = 1;
-- if (write_burst_done)
--
-- write_burst = 0;
-- go to step 4
--
--
-- 5) FINISHED
--
-- finished = 1;
-- if (particles_loaded)
-- go to step 0;
when STATE_LOAD_PARTICLE_1 =>
--! load a particle
write_burst <= '0';
if (number_of_particles <= counter_resampled_particles) then
state1 <= STATE_WRITE_BURST_DECISION;
else
o_RAMAddr <= local_ram_read_address;
state1 <= STATE_LOAD_PARTICLE_2;
end if;
when STATE_LOAD_PARTICLE_2 =>
--!needed because reading from local RAM needs two clock steps
state1 <= STATE_LOAD_WEIGHT;
when STATE_LOAD_WEIGHT =>
--! load particle weight
current_particle_weight <= TO_INTEGER(SIGNED(i_RAMData));
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_1;
when STATE_CALCULATE_REPLICATION_FACTOR_1 =>
--! calculate replication factor (step 2/6)
temp <= current_particle_weight * number_of_particles_in_total;
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_2;
when STATE_CALCULATE_REPLICATION_FACTOR_2 =>
--! calculate replication factor (step 2/6)
temp <= temp - U;
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_3;
when STATE_CALCULATE_REPLICATION_FACTOR_3 =>
--! calculate replication factor (step 3/6)
fact <= temp + GRANULARITY;
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_4;
when STATE_CALCULATE_REPLICATION_FACTOR_4 =>
--! calculate replication factor (step 4/6)
fact <= fact / GRANULARITY;
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_5;
when STATE_CALCULATE_REPLICATION_FACTOR_5 =>
--! calculate replication factor (step 5/6)
U <= fact * GRANULARITY;
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_6;
when STATE_CALCULATE_REPLICATION_FACTOR_6 =>
--! calculate replication factor (step 6/6)
U <= U - temp;
state1 <= STATE_WRITE_PARTICLE_INDEX;
-- todo: change back
--state1 <= STATE_WRITE_BURST_DECISION;
when STATE_WRITE_PARTICLE_INDEX =>
--! read particle from local ram
-- copy particle_size / 32 from local RAM to local RAM
o_RAMWE <= '1';
o_RAMAddr <= local_ram_write_address;
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(counter, C_TASK_BURST_DWIDTH));
local_ram_write_address <= local_ram_write_address + 1;
state1 <= STATE_WRITE_PARTICLE_REPLICATION;
when STATE_WRITE_PARTICLE_REPLICATION =>
--! needed because reading takes 2 clock steps
o_RAMWE <= '1';
o_RAMAddr <= local_ram_write_address;
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(fact, C_TASK_BURST_DWIDTH));
local_ram_write_address <= local_ram_write_address + 1;
write_counter <= write_counter + 1;
state1 <= STATE_WRITE_BURST_DECISION;
when STATE_WRITE_BURST_DECISION =>
--! write burst to main memory
o_RAMWE <= '0';
if (16 <= write_counter) then
-- write burst
state1 <= STATE_WRITE_BURST;
-- todo change back
--state1 <= STATE_WRITE_BURST_DECISION;
write_counter <= 0;
local_ram_write_address <= write_address;
written_values <= 16;
elsif (number_of_particles <= counter_resampled_particles and write_counter > 0) then
-- write burst
state1 <= STATE_WRITE_BURST;
--todo: changed back
--state1 <= STATE_WRITE_BURST_DECISION;
write_counter <= 0;
--write_burst <= '1';
written_values <= write_counter;
elsif (number_of_particles <= counter_resampled_particles) then
state1 <= STATE_FINISH;
else
-- get next particle
counter <= counter + 1;
counter_resampled_particles <= counter_resampled_particles + 1;
local_ram_read_address <= local_ram_read_address + 1;
state1 <= STATE_LOAD_PARTICLE_1;
end if;
when STATE_WRITE_BURST =>
--! write burst to main memory
--write_burst <= '1';
--written_values <= write_counter;
--if (rising_edge (write_burst_done)) then
write_burst <= '1';
write_burst_done_ack <= '0';
--change back
--write_counter <= 0;
if (write_burst_done = '1') then
write_burst <= '0';
state1 <= STATE_WRITE_BURST_DONE_ACK;
end if;
when STATE_WRITE_BURST_DONE_ACK =>
--! write burst to main memory
write_burst_done_ack <= '1';
write_counter <= 0;
write_burst <= '0';
if (write_burst_done = '0') then
state1 <= STATE_WRITE_BURST_DONE_ACK_2;
end if;
-- if (number_of_particles <= counter_resampled_particles) then
--
-- state1 <= STATE_FINISH;
-- else
-- --todo: changed for hopefully good
-- --state1 <= STATE_LOAD_PARTICLE_1;
-- state1 <= STATE_WRITE_BURST_DECISION;
-- end if;
when STATE_WRITE_BURST_DONE_ACK_2 =>
--! write burst to main memory
write_burst_done_ack <= '0';
if (number_of_particles <= counter_resampled_particles) then
state1 <= STATE_FINISH;
else
--todo: changed for hopefully good
--state1 <= STATE_LOAD_PARTICLE_1;
state1 <= STATE_WRITE_BURST_DECISION;
end if;
when STATE_FINISH =>
--! write finished signal
write_burst <= '0';
finished <= '1';
if (particles_loaded = '1') then
state1 <= STATE_INIT;
end if;
when others =>
state1 <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_fwft_fifo is
end tb_fwft_fifo;
architecture test of tb_fwft_fifo is
-- 10 MHz -> 100 ns period. Duty cycle = 1/2.
constant CLK_PERIOD : time := 100 ns;
constant CLK_HIGH_PERIOD : time := 50 ns;
constant CLK_LOW_PERIOD : time := 50 ns;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal sim_finished : boolean := false;
-- fwft_fifo ---------------------------------------------------------------
constant DATA_WIDTH : positive := 8;
constant FIFO_DEPTH : positive := 8;
signal clr : std_logic := '0';
signal write_en : std_logic := '0';
signal data_in : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal read_en : std_logic := '0';
signal data_out : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal empty : std_logic := '0';
signal full : std_logic := '0';
signal usedw : std_logic_vector(integer(ceil(log2(real(FIFO_DEPTH + 1)))) - 1 downto 0) := (others => '0');
begin
clk_generation : process
begin
if not sim_finished then
clk <= '1';
wait for CLK_HIGH_PERIOD;
clk <= '0';
wait for CLK_LOW_PERIOD;
else
wait;
end if;
end process clk_generation;
fwft_fifo_inst : entity work.fwft_fifo
generic map(DATA_WIDTH => DATA_WIDTH,
FIFO_DEPTH => FIFO_DEPTH)
port map(
clk => clk,
reset => reset,
clr => clr,
write_en => write_en,
data_in => data_in,
read_en => read_en,
data_out => data_out,
empty => empty,
full => full,
usedw => usedw);
sim : process
procedure async_reset is
begin
wait until rising_edge(clk);
wait for CLK_PERIOD / 4;
reset <= '1';
wait for CLK_PERIOD / 2;
reset <= '0';
end procedure async_reset;
procedure sync_clr is
begin
wait until falling_edge(clk);
clr <= '1';
wait until falling_edge(clk);
clr <= '0';
end procedure sync_clr;
procedure push(constant val : in natural) is
begin
wait until falling_edge(clk);
write_en <= '1';
data_in <= std_logic_vector(to_unsigned(val, data_in'length));
wait until falling_edge(clk);
write_en <= '0';
data_in <= (others => '0');
end procedure push;
procedure pop is
begin
wait until falling_edge(clk);
read_en <= '1';
wait until falling_edge(clk);
read_en <= '0';
end procedure pop;
procedure push_pop(constant val : in natural) is
begin
wait until falling_edge(clk);
write_en <= '1';
data_in <= std_logic_vector(to_unsigned(val, data_in'length));
read_en <= '1';
wait until falling_edge(clk);
write_en <= '0';
data_in <= (others => '0');
read_en <= '0';
end procedure push_pop;
procedure wait_clock_cycles(constant count : in positive) is
begin
wait for count * CLK_PERIOD;
end procedure wait_clock_cycles;
begin
-- async reset
async_reset;
wait_clock_cycles(10);
-- push
for i in 1 to FIFO_DEPTH loop
push(i);
end loop;
wait_clock_cycles(10);
-- pop
for i in 1 to FIFO_DEPTH loop
pop;
end loop;
wait_clock_cycles(10);
-- pushpop
push(FIFO_DEPTH + 1);
for i in 2 to FIFO_DEPTH loop
push_pop(FIFO_DEPTH + i);
end loop;
pop;
wait_clock_cycles(10);
-- sync clr
sync_clr;
wait_clock_cycles(10);
sim_finished <= true;
wait;
end process sim;
end architecture test;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH
);
port (
clk : in std_ulogic; -- FPGA main clock input
-- Buttons & LEDs
btnCpuResetn : in std_ulogic; -- Reset button
Led : out std_logic_vector(15 downto 0);
-- Onboard Cellular RAM
RamOE : out std_ulogic;
RamWE : out std_ulogic;
RamAdv : out std_ulogic;
RamCE : out std_ulogic;
RamClk : out std_ulogic;
RamCRE : out std_ulogic;
RamLB : out std_ulogic;
RamUB : out std_ulogic;
address : out std_logic_vector(22 downto 0);
data : inout std_logic_vector(15 downto 0);
-- USB-RS232 interface
RsRx : in std_logic;
RsTx : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
-- Memory controler signals
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
-- AMBA bus signals
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to 0);
signal irqo : irq_out_vector(0 to 0);
signal dbgi : l3_debug_in_vector(0 to 0);
signal dbgo : l3_debug_out_vector(0 to 0);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ndsuact : std_ulogic;
signal gpti : gptimer_in_type;
signal clkm, rstn : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart (unconnected)
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkm : signal is true;
constant clock_mult : integer := 10; -- Clock multiplier
constant clock_div : integer := 20; -- Clock divider
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * clock_mult / clock_div; -- CPU freq in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 0)
port map (btnCpuResetn, clkm, lock, rstn, rstraw);
lock <= cgo.clklock;
-- clock generator
clkgen0 : clkgen
generic map (fabtech, clock_mult, clock_div, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (clk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (ioen => 1, nahbm => 4, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
u0 : leon3s
generic map (hindex=>0, fabtech=>fabtech, memtech=>memtech, dsu=>1, fpu=>0, v8=>2,
mac=>0, isetsize=>8, dsetsize=>8,icen=>1, dcen=>1,tbuf=>2)
port map (clkm, rstn, ahbmi, ahbmo(0), ahbsi, ahbso, irqi(0), irqo(0), dbgi(0), dbgo(0));
-- LEON3 Debug Support Unit
dsu0 : dsu3
generic map (hindex => 2, ncpu => 1, tech => memtech, irq => 0, kbytes => 2)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
-- Debug UART
dcom0 : ahbuart
generic map (hindex => 1, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(1));
dsurx_pad : inpad generic map (tech => padtech) port map (RsRx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (RsTx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => 3)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(3),
open, open, open, open, open, open, open, gnd);
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0, rommask => 0,
iomask => 0, ram8 => 0, ram16 => 1,srbanks=>1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01"; -- Sets data bus width for PROM accesses.
-- Bidirectional data bus
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(23 downto 16),
memo.bdrive(1), memi.data(23 downto 16));
bdr2 : iopadv generic map (tech => padtech, width => 8)
port map (data(15 downto 8), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
-- Out signals to memory
addr_pad : outpadv generic map (tech => padtech, width => 23) -- Address bus
port map (address, memo.address(23 downto 1));
oen_pad : outpad generic map (tech => padtech) -- Output Enable
port map (RamOE, memo.oen);
cs_pad : outpad generic map (tech => padtech) -- SRAM Chip select
port map (RamCE, memo.ramsn(0));
lb_pad : outpad generic map (tech => padtech)
port map (RamLB, memo.mben(0));
ub_pad : outpad generic map (tech => padtech)
port map (RamUB, memo.mben(1));
wri_pad : outpad generic map (tech => padtech) -- Write enable
port map (RamWE, memo.writen);
RamCRE <= '0'; -- Special SRAM signals specific
RamClk <= '0'; -- to Nexys4 board
RamAdv <= '0';
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- APB Bridge
generic map (hindex => 1, haddr => 16#800#)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
irqctrl0 : irqmp -- Interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => 1)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
timer0 : gptimer -- Time Unit
generic map (pindex => 3, paddr => 3, pirq => 8,
sepirq => 1, ntimers => 2)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => 1)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent NEXYS 3 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity dist_mem_gen_v7_2_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(14-1-(4*0*boolean'pos(14>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(32-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(14-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(14-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(32-1 downto 0)
);
end dist_mem_gen_v7_2_exdes;
architecture xilinx of dist_mem_gen_v7_2_exdes is
component dist_mem_gen_v7_2 is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(14-1-(4*0*boolean'pos(14>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : dist_mem_gen_v7_2
port map (
SPO => SPO,
A => A
);
end xilinx;
|
-- NEED RESULT: ARCH00110.P1: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110.P2: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110.P3: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00110: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00110
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00110(ARCH00110)
-- ENT00110_Test_Bench(ARCH00110_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00110 is
port (
s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
--
end ENT00110 ;
--
architecture ARCH00110 of ENT00110 is
begin
PGEN_CHKP_1 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_rec1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_2(highb).f2 after 10 ns,
c_st_rec1_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00110.P1" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_2(highb).f2 after 10 ns ,
c_st_rec1_vector_1(highb).f2 after 20 ns ,
c_st_rec1_vector_2(highb).f2 after 30 ns ,
c_st_rec1_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00110" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00110" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00110" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_rec2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_rec2_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_2(highb).f2 after 10 ns,
c_st_rec2_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00110.P2" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_2(highb).f2 after 10 ns ,
c_st_rec2_vector_1(highb).f2 after 20 ns ,
c_st_rec2_vector_2(highb).f2 after 30 ns ,
c_st_rec2_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00110" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00110" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00110" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_rec3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_rec3_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_2(highb).f2 after 10 ns,
c_st_rec3_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00110.P3" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_2(highb).f2 after 10 ns ,
c_st_rec3_vector_1(highb).f2 after 20 ns ,
c_st_rec3_vector_2(highb).f2 after 30 ns ,
c_st_rec3_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00110" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00110" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00110" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P3 ;
--
--
end ARCH00110 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00110_Test_Bench is
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
--
end ENT00110_Test_Bench ;
--
architecture ARCH00110_Test_Bench of ENT00110_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00110 ( ARCH00110 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1_vector
, s_st_rec2_vector
, s_st_rec3_vector
) ;
end block L1 ;
end ARCH00110_Test_Bench ;
|
architecture RTL of ENTITY1 is
begin
end architecture RTL;
architecture RTL of ENTITY1 is
begin
end;
architecture RTL of ENTITY1 is
begin
end architecture;
architecture
RTL
of
ENTITY1
is
begin
end
architecture
RTL
;
|
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := (
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"),
(name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
));
constant c_stimulus : t_stimulus_array :=
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"); -- Comment
begin
end architecture rtl;
|
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_steer128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- IPIF_Steer128 - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_steer128.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_steer128.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2-5-2002 -- First version
-- ^^^^^^
-- First version of IPIF steering logic.
-- ~~~~~~
-- BLT 2-12-2002 -- Removed BE_Steer, now generated internally
--
-- DET 2-24-2002 -- Added 'When others' to size case statement
-- in BE_STEER_PROC process.
--
-- BLT 10-10-2002 -- Rewrote to get around some XST synthesis
-- issues.
--
-- BLT 11-18-2002 -- Added addr_bits to sensitivity lists to
-- fix simulation bug
--
-- GAB 06-27-2005
-- ~~~~~~
-- Modified to support C_DWIDTH=128
-- Added second Decode_size input to reduce fanout for 128-bit cases
-- Renamed to ipif_steer128.vhd
-- ^^^^^^
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of host databus attached to the IPIF
-- C_SMALLEST : integer := width of smallest device (not access size)
-- attached to the IPIF
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity ipif_steer128 is
generic (
C_DWIDTH : integer := 32; -- 8, 16, 32, 64, 128
C_SMALLEST : integer := 32; -- 8, 16, 32, 64, 128
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH/8-1);
Decode_size1 : in std_logic_vector(0 to 2);
Decode_size2 : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1)
);
end entity ipif_steer128;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of ipif_steer128 is
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- OPB Data Muxing and Steering
-----------------------------------------------------------------------------
-- GEN_DWIDTH_SMALLEST
GEN_SAME: if C_DWIDTH = C_SMALLEST generate
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
end generate GEN_SAME;
GEN_16_8: if C_DWIDTH = 16 and C_SMALLEST = 8 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-1);
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1) <= '0';
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_16_8;
GEN_32_8: if C_DWIDTH = 32 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2 to C_AWIDTH-1); --a30 to a31
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when "010" => --HW
Rd_Data_Out(8 to 15) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(1) <= BE_In(3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_8;
GEN_32_16: if C_DWIDTH = 32 and C_SMALLEST = 16 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2); --a30
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_16;
GEN_64_8: if C_DWIDTH = 64 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 2);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-1); --a29 to a31
case addr_bits is
when "001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when "010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
-- Rd_Data_Out(24 to 31) <= Rd_Data_In(8 to 15);
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(4);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(32 to 39) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(40 to 47);
Wr_Data_Out(8 to 15) <= Wr_Data_In(40 to 47);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(5);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(40 to 47) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(6);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(48 to 55) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(56 to 63);
Wr_Data_Out(8 to 15) <= Wr_Data_In(56 to 63);
Wr_Data_Out(24 to 31) <= Wr_Data_In(56 to 63);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(7);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(56 to 63) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_8;
GEN_64_16: if C_DWIDTH = 64 and C_SMALLEST = 16 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-2); --a29 to a30
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_16;
GEN_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3); --a29
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "011" =>
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_32;
---------------------
-- 128 Bit Support --
---------------------
GEN_128_8: if C_DWIDTH = 128 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 3);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,
Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4 to C_AWIDTH-1);
case addr_bits is
when "0001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when "0010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "0011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "0100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(4);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(32 to 39) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "0101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(40 to 47);
Wr_Data_Out(8 to 15) <= Wr_Data_In(40 to 47);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(5);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(40 to 47) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "0110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(6);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(48 to 55) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "0111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(56 to 63);
Wr_Data_Out(8 to 15) <= Wr_Data_In(56 to 63);
Wr_Data_Out(24 to 31) <= Wr_Data_In(56 to 63);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(7);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(56 to 63) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "1000" =>
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(8);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(64 to 71) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(8 to 9);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(64 to 79) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(72 to 79);
Wr_Data_Out(8 to 15) <= Wr_Data_In(72 to 79);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(9);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(72 to 79) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(8 to 9);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(64 to 79) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(80 to 95);
Wr_Data_Out(16 to 31) <= Wr_Data_In(80 to 95);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(10);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(80 to 87) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(10 to 11);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(80 to 95) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(88 to 95);
Wr_Data_Out(8 to 15) <= Wr_Data_In(88 to 95);
Wr_Data_Out(24 to 31) <= Wr_Data_In(88 to 95);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(11);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(88 to 95) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(10 to 11);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(80 to 95) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(96 to 127);
Wr_Data_Out(32 to 63) <= Wr_Data_In(96 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(12);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(96 to 103) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(12 to 13);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(96 to 111) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(104 to 111);
Wr_Data_Out(8 to 15) <= Wr_Data_In(104 to 111);
Wr_Data_Out(40 to 47) <= Wr_Data_In(104 to 111);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(13);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(104 to 111) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(12 to 13);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(96 to 111) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(112 to 127);
Wr_Data_Out(16 to 31) <= Wr_Data_In(112 to 127);
Wr_Data_Out(48 to 63) <= Wr_Data_In(112 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(14);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(112 to 119) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(14 to 15);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(112 to 127) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(120 to 127);
Wr_Data_Out(8 to 15) <= Wr_Data_In(120 to 127);
Wr_Data_Out(24 to 31) <= Wr_Data_In(120 to 127);
Wr_Data_Out(56 to 63) <= Wr_Data_In(120 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(15);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(120 to 127) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(14 to 15);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(112 to 127) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_8;
GEN_128_16: if C_DWIDTH = 128 and C_SMALLEST = 16 generate
signal addr_bits : std_logic_vector(0 to 2);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,
Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4 to C_AWIDTH-2);
case addr_bits is
when "001" => --2
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "010" => --4
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "011" => --6
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size1 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "100" => --8
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(8 to 9);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(64 to 79) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "101" => --A
Wr_Data_Out(0 to 15) <= Wr_Data_In(80 to 95);
Wr_Data_Out(16 to 31) <= Wr_Data_In(80 to 95);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(10 to 11);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(80 to 95) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "110" => --C
Wr_Data_Out(0 to 31) <= Wr_Data_In(96 to 127);
Wr_Data_Out(32 to 63) <= Wr_Data_In(96 to 127);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(12 to 13);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(96 to 111) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "111" => --E
Wr_Data_Out(0 to 15) <= Wr_Data_In(112 to 127);
Wr_Data_Out(16 to 31) <= Wr_Data_In(112 to 127);
Wr_Data_Out(48 to 63) <= Wr_Data_In(112 to 127);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(14 to 15);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(112 to 127) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_16;
GEN_128_32: if C_DWIDTH = 128 and C_SMALLEST = 32 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,
Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4 to C_AWIDTH-3);
case addr_bits is
when "01" => --4
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "011" => --FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "10" => --8
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size1 is
when "011" => --FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "11" => --C
Wr_Data_Out(0 to 31) <= Wr_Data_In(96 to 127);
Wr_Data_Out(32 to 63) <= Wr_Data_In(96 to 127);
case Decode_size2 is
when "011" => --FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_32;
GEN_128_64: if C_DWIDTH = 128 and C_SMALLEST = 64 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4);
case addr_bits is
when '1' => --8
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size1 is
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_64;
-- Size indication (Decode_size)
-- n = 001 byte 2^0
-- n = 010 halfword 2^1
-- n = 011 word 2^2
-- n = 100 doubleword 2^3
-- n = 101 128-b
-- n = 110 256-b
-- n = 111 512-b
-- num_bytes = 2^(n-1)
end architecture IMP;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------------------------------
entity Gate_NOT is
Port
(
A : in STD_LOGIC;
B : in STD_LOGIC;
Z : out STD_LOGIC
);
end Gate_NOT;
----------------------------------------------------------------------------------
architecture Behavioral of Gate_NOT is
begin
Z <= A not B;
end Behavioral;
|
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- AXI interface for ppwa --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE work.fLink_definitions.ALL;
USE work.ppwa_pkg.ALL;
entity ppwaDevice_v1_0_S00_AXI is
generic (
-- Users to add parameters here
number_of_ppwas: INTEGER RANGE 1 TO 64 := 1;
unique_id: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
base_clk: INTEGER;--clock frequency which is used on the clock input signal of this block
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of ID for for write address, write data, read address and read data
C_S_AXI_ID_WIDTH : integer := 1;
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 12;
-- Width of optional user defined signal in write address channel
C_S_AXI_AWUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in read address channel
C_S_AXI_ARUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in write data channel
C_S_AXI_WUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in read data channel
C_S_AXI_RUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in write response channel
C_S_AXI_BUSER_WIDTH : integer := 0
);
port (
-- Users to add ports here
S_islv_ppwa : IN STD_LOGIC_VECTOR(number_of_ppwas-1 DOWNTO 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write Address ID
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Write address
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
-- Lock type. Provides additional information about the
-- atomic characteristics of the transfer.
S_AXI_AWLOCK : in std_logic;
-- Memory type. This signal indicates how transactions
-- are required to progress through a system.
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Quality of Service, QoS identifier sent for each
-- write transaction.
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
-- Region identifier. Permits a single physical interface
-- on a slave to be used for multiple logical interfaces.
S_AXI_AWREGION : in std_logic_vector(3 downto 0);
-- Optional User-defined signal in the write address channel.
S_AXI_AWUSER : in std_logic_vector(C_S_AXI_AWUSER_WIDTH-1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid write address and
-- control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that
-- the slave is ready to accept an address and associated
-- control signals.
S_AXI_AWREADY : out std_logic;
-- Write Data
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte
-- lanes hold valid data. There is one write strobe
-- bit for each eight bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write last. This signal indicates the last transfer
-- in a write burst.
S_AXI_WLAST : in std_logic;
-- Optional User-defined signal in the write data channel.
S_AXI_WUSER : in std_logic_vector(C_S_AXI_WUSER_WIDTH-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Response ID tag. This signal is the ID tag of the
-- write response.
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Optional User-defined signal in the write response channel.
S_AXI_BUSER : out std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0);
-- Write response valid. This signal indicates that the
-- channel is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address ID. This signal is the identification
-- tag for the read address group of signals.
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Read address. This signal indicates the initial
-- address of a read burst transaction.
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
-- Lock type. Provides additional information about the
-- atomic characteristics of the transfer.
S_AXI_ARLOCK : in std_logic;
-- Memory type. This signal indicates how transactions
-- are required to progress through a system.
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Quality of Service, QoS identifier sent for each
-- read transaction.
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
-- Region identifier. Permits a single physical interface
-- on a slave to be used for multiple logical interfaces.
S_AXI_ARREGION : in std_logic_vector(3 downto 0);
-- Optional User-defined signal in the read address channel.
S_AXI_ARUSER : in std_logic_vector(C_S_AXI_ARUSER_WIDTH-1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid read address and
-- control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that
-- the slave is ready to accept an address and associated
-- control signals.
S_AXI_ARREADY : out std_logic;
-- Read ID tag. This signal is the identification tag
-- for the read data group of signals generated by the slave.
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Read Data
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of
-- the read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read last. This signal indicates the last transfer
-- in a read burst.
S_AXI_RLAST : out std_logic;
-- Optional User-defined signal in the read address channel.
S_AXI_RUSER : out std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0);
-- Read valid. This signal indicates that the channel
-- is signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end ppwaDevice_v1_0_S00_AXI;
architecture arch_imp of ppwaDevice_v1_0_S00_AXI is
-- AXI4FULL signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_buser : std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rlast : std_logic;
signal axi_ruser : std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0);
signal axi_rvalid : std_logic;
-- aw_wrap_en determines wrap boundary and enables wrapping
signal aw_wrap_en : std_logic;
-- ar_wrap_en determines wrap boundary and enables wrapping
signal ar_wrap_en : std_logic;
-- aw_wrap_size is the size of the write transfer, the
-- write address wraps to a lower address if upper address
-- limit is reached
signal aw_wrap_size : integer;
-- ar_wrap_size is the size of the read transfer, the
-- read address wraps to a lower address if upper address
-- limit is reached
signal ar_wrap_size : integer;
-- The axi_awv_awr_flag flag marks the presence of write address valid
signal axi_awv_awr_flag : std_logic;
--The axi_arv_arr_flag flag marks the presence of read address valid
signal axi_arv_arr_flag : std_logic;
-- The axi_awlen_cntr internal write address counter to keep track of beats in a burst transaction
signal axi_awlen_cntr : std_logic_vector(7 downto 0);
--The axi_arlen_cntr internal read address counter to keep track of beats in a burst transaction
signal axi_arlen_cntr : std_logic_vector(7 downto 0);
signal axi_arburst : std_logic_vector(2-1 downto 0);
signal axi_awburst : std_logic_vector(2-1 downto 0);
signal axi_arlen : std_logic_vector(8-1 downto 0);
signal axi_awlen : std_logic_vector(8-1 downto 0);
--local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
--ADDR_LSB is used for addressing 32/64 bit registers/memories
--ADDR_LSB = 2 for 32 bits (n downto 2)
--ADDR_LSB = 3 for 42 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
constant USER_NUM_MEM: integer := 1;
constant low : std_logic_vector (C_S_AXI_ADDR_WIDTH - 1 downto 0) := (OTHERS => '0');
CONSTANT c_usig_typdef_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_typdef_address*4,C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_mem_size_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_mem_size_address*4,C_S_AXI_ADDR_WIDTH));
CONSTANT c_number_of_channels_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_channels_address*4,C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_unique_id_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_unique_id_address*4,C_S_AXI_ADDR_WIDTH));
CONSTANT c_configuration_reg_address: STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_configuration_address*4,C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_base_clk_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_std_registers*4,C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_period_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(unsigned(c_usig_base_clk_address) + 4);
CONSTANT c_usig_hightime_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(unsigned(c_usig_period_address) + number_of_ppwas*4);
CONSTANT c_usig_max_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(unsigned(c_usig_hightime_address) + number_of_ppwas*4);
CONSTANT id : STD_LOGIC_VECTOR(15 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_ppwa_id,16));
CONSTANT subtype_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS=>'0');
CONSTANT interface_version : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS=>'0');
Type t_ppwa_regs IS ARRAY(number_of_ppwas-1 DOWNTO 0) OF UNSIGNED(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
TYPE t_internal_register IS RECORD
period_regs : t_ppwa_regs;
hightime_regs : t_ppwa_regs;
conf_reg : STD_LOGIC_VECTOR(0 DOWNTO 0);
END RECORD;
CONSTANT INTERNAL_REG_RESET : t_internal_register := (
period_regs => (OTHERS => (OTHERS => '0')),
hightime_regs => (OTHERS => (OTHERS => '0')),
conf_reg => (OTHERS => '0')
);
SIGNAL ri,ri_next : t_internal_register := INTERNAL_REG_RESET;
SIGNAL ppwa_reset : STD_LOGIC := '1';
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BUSER <= axi_buser;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RLAST <= axi_rlast;
S_AXI_RUSER <= axi_ruser;
S_AXI_RVALID <= axi_rvalid;
S_AXI_BID <= S_AXI_AWID;
S_AXI_RID <= S_AXI_ARID;
aw_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(axi_awlen)));
ar_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(axi_arlen)));
aw_wrap_en <= '1' when (((axi_awaddr AND std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
ar_wrap_en <= '1' when (((axi_araddr AND std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
axi_awv_awr_flag <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
-- slave is ready to accept an address and
-- associated control signals
axi_awv_awr_flag <= '1'; -- used for generation of bresp() and bvalid
axi_awready <= '1';
elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
-- preparing to accept next address after current write burst tx completion
axi_awv_awr_flag <= '0';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
axi_awburst <= (others => '0');
axi_awlen <= (others => '0');
axi_awlen_cntr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0') then
-- address latching
axi_awaddr <= S_AXI_AWADDR(C_S_AXI_ADDR_WIDTH - 1 downto 0); ---- start address of transfer
axi_awlen_cntr <= (others => '0');
axi_awburst <= S_AXI_AWBURST;
axi_awlen <= S_AXI_AWLEN;
elsif((axi_awlen_cntr <= axi_awlen) and axi_wready = '1' and S_AXI_WVALID = '1') then
axi_awlen_cntr <= std_logic_vector (unsigned(axi_awlen_cntr) + 1);
case (axi_awburst) is
when "00" => -- fixed burst
-- The write address for all the beats in the transaction are fixed
axi_awaddr <= axi_awaddr; ----for awsize = 4 bytes (010)
when "01" => --incremental burst
-- The write address for all the beats in the transaction are increments by awsize
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--awaddr aligned to 4 byte boundary
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
when "10" => --Wrapping burst
-- The write address wraps when the address reaches wrap boundary
if (aw_wrap_en = '1') then
axi_awaddr <= std_logic_vector (unsigned(axi_awaddr) - (to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH)));
else
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--awaddr aligned to 4 byte boundary
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
end if;
when others => --reserved (incremental burst for example)
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for awsize = 4 bytes (010)
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and axi_awv_awr_flag = '1') then
axi_wready <= '1';
-- elsif (axi_awv_awr_flag = '0') then
elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
axi_buser <= (others => '0');
else
if (axi_awv_awr_flag = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' and S_AXI_WLAST = '1' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
--check if bready is asserted while bvalid is high)
axi_bvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_arv_arr_flag <= '0';
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
axi_arready <= '1';
axi_arv_arr_flag <= '1';
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1' and (axi_arlen_cntr = axi_arlen)) then
-- preparing to accept next address after current read completion
axi_arv_arr_flag <= '0';
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_araddr latching
--This process is used to latch the address when both
--S_AXI_ARVALID and S_AXI_RVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_araddr <= (others => '0');
axi_arburst <= (others => '0');
axi_arlen <= (others => '0');
axi_arlen_cntr <= (others => '0');
axi_rlast <= '0';
axi_ruser <= (others => '0');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_arv_arr_flag = '0') then
-- address latching
axi_araddr <= S_AXI_ARADDR(C_S_AXI_ADDR_WIDTH - 1 downto 0); ---- start address of transfer
axi_arlen_cntr <= (others => '0');
axi_rlast <= '0';
axi_arburst <= S_AXI_ARBURST;
axi_arlen <= S_AXI_ARLEN;
elsif((axi_arlen_cntr <= axi_arlen) and axi_rvalid = '1' and S_AXI_RREADY = '1') then
axi_arlen_cntr <= std_logic_vector (unsigned(axi_arlen_cntr) + 1);
axi_rlast <= '0';
case (axi_arburst) is
when "00" => -- fixed burst
-- The read address for all the beats in the transaction are fixed
axi_araddr <= axi_araddr; ----for arsize = 4 bytes (010)
when "01" => --incremental burst
-- The read address for all the beats in the transaction are increments by awsize
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1); --araddr aligned to 4 byte boundary
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
when "10" => --Wrapping burst
-- The read address wraps when the address reaches wrap boundary
if (ar_wrap_en = '1') then
axi_araddr <= std_logic_vector (unsigned(axi_araddr) - (to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH)));
else
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1); --araddr aligned to 4 byte boundary
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
end if;
when others => --reserved (incremental burst for example)
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for arsize = 4 bytes (010)
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0');
end case;
elsif((axi_arlen_cntr = axi_arlen) and axi_rlast = '0' and axi_arv_arr_flag = '1') then
axi_rlast <= '1';
elsif (S_AXI_RREADY = '1') then
axi_rlast <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arv_arr_flag = '1' and axi_rvalid = '0') then
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- ------------------------------------------
-- -- Example code to access user logic memory region
-- ------------------------------------------
--read data
process( axi_rvalid,axi_araddr,ri ) is
VARIABLE reg_number: INTEGER RANGE 0 TO number_of_ppwas := 0;
begin
if (axi_rvalid = '1') then
-- output the read dada
IF(axi_araddr = c_usig_typdef_address) THEN
axi_rdata(31 DOWNTO 16) <= id;
axi_rdata(15 DOWNTO 8) <= subtype_id;
axi_rdata(7 DOWNTO 0) <= interface_version;
ELSIF(axi_araddr = c_usig_mem_size_address)THEN
axi_rdata <= (others => '0');
axi_rdata(C_S_AXI_ADDR_WIDTH) <= '1';
ELSIF(axi_araddr = c_number_of_channels_address)THEN
axi_rdata <= std_logic_vector(to_unsigned(number_of_ppwas, axi_rdata'length));
ELSIF(axi_araddr = c_usig_unique_id_address) THEN
axi_rdata <= unique_id;
ELSIF(axi_araddr = c_configuration_reg_address) THEN
axi_rdata <= (others => '0');
axi_rdata(c_fLink_reset_bit_num) <= ri.conf_reg(c_fLink_reset_bit_num);
ELSIF(axi_araddr >= c_usig_base_clk_address AND axi_araddr < c_usig_period_address) THEN
axi_rdata <= STD_LOGIC_VECTOR(to_unsigned(base_clk,axi_rdata'length));
ELSIF (axi_araddr >= c_usig_period_address AND axi_araddr < c_usig_hightime_address) THEN
axi_rdata <= STD_LOGIC_VECTOR(ri.period_regs(to_integer(unsigned(axi_araddr) - unsigned(c_usig_period_address))/4));
ELSIF (axi_araddr >= c_usig_hightime_address AND axi_araddr < c_usig_max_address) THEN
axi_rdata <= STD_LOGIC_VECTOR(ri.hightime_regs(to_integer(unsigned(axi_araddr) - unsigned(c_usig_hightime_address))/4));
ELSE
axi_rdata <= (others => '0');
END IF;
else
axi_rdata <= (others => '0');
end if;
end process;
process( axi_wready,S_AXI_WVALID,S_AXI_WDATA,axi_awaddr,S_AXI_WSTRB,ri,S_AXI_ARESETN)
VARIABLE reg_number: INTEGER RANGE 0 TO number_of_ppwas := 0;
VARIABLE vi: t_internal_register := INTERNAL_REG_RESET;
BEGIN
vi := ri;
IF(axi_awaddr = c_configuration_reg_address) THEN
IF(S_AXI_WSTRB(0) = '1')THEN
vi.conf_reg(c_fLink_reset_bit_num) := S_AXI_WDATA(c_fLink_reset_bit_num);
END IF;
END IF;
IF(S_AXI_ARESETN = '0' OR vi.conf_reg(c_fLink_reset_bit_num) = '1' )THEN
vi := INTERNAL_REG_RESET;
ppwa_reset <= '0';
ELSE
ppwa_reset <= '1';
END IF;
END PROCESS;
-- Add user logic here
--create component
gen_ppwa:
FOR i IN 0 TO number_of_ppwas-1 GENERATE
my_ppwa : ppwa
GENERIC MAP (counter_resolution => C_S_AXI_DATA_WIDTH)
PORT MAP (S_AXI_ACLK,ppwa_reset,S_islv_ppwa(i),ri.period_regs(i),ri.hightime_regs(i));
END GENERATE gen_ppwa;
-- Add user logic here
-- User logic ends
end arch_imp;
|
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_never_unknown_async is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 1;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
reset : in std_logic;
enable : in std_logic;
test_expr : in std_logic_vector(width - 1 downto 0);
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_never_unknown_async;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : JPEG_PKG
-- Design : JPEG_ENC
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : JPEG_PKG.VHD
-- Created : Sat Mar 7 2009
--
--------------------------------------------------------------------------------
--
-- Description : Package for JPEG core
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package JPEG_PKG is
-- do not change, constant
constant C_HDR_SIZE : integer := 623;
-- warning! this parameter heavily affects memory size required
-- if expected image width is known change this parameter to match this
-- otherwise some onchip RAM will be wasted and never used
constant C_MAX_LINE_WIDTH : integer := 2048;
-- memory/performance tradeoff
-- 8 extra lines highest performance
-- 0 extra lines lowest area
constant C_EXTRA_LINES : integer := 8; -- from 0 to 8
-- 24 bit format RGB/YCbCr 888 bits
-- 16 bit format RGB/YCbCr 565 bits
constant C_PIXEL_BITS : integer := 24;
-- 0 = RGB
-- 1 = YUV/YCbCr
constant C_YUV_INPUT : std_logic := '0';
type T_SM_SETTINGS is record
x_cnt : unsigned(15 downto 0);
y_cnt : unsigned(15 downto 0);
cmp_idx : unsigned(2 downto 0);
end record;
constant C_SM_SETTINGS : T_SM_SETTINGS :=
(
(others => '0'),
(others => '0'),
(others => '0')
);
function log2(n : natural) return natural;
end package JPEG_PKG;
package body JPEG_PKG is
-----------------------------------------------------------------------------
function log2(n : natural)
return natural is
begin
for i in 0 to 31 loop
if (2**i) >= n then
return i;
end if;
end loop;
return 32;
end log2;
-----------------------------------------------------------------------------
end package body JPEG_PKG; |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
generic(G_SIZE : integer := 10;
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
port (
I_PORT1 : in std_logic := '0';
I_PORT2 : out std_logic :='1'
);
end entity FIFO;
|
------------------------------------------------------------------------------
-- Context register file
--
-- Project :
-- File : contextregfile.vhd
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/03/06
-- Last changed: $LastChangedDate: 2005-01-13 18:02:10 +0100 (Thu, 13 Jan 2005) $
------------------------------------------------------------------------------
-- generates the register file that holds the state of a context. Used
-- in the processing element.
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-06 CP added documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
entity ContextRegFile is
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ClrContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEI : in std_logic;
ContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
EnxEI : in std_logic;
DinxDI : in data_word;
DoutxDO : out data_word);
end ContextRegFile;
architecture simple of ContextRegFile is
signal Clr : std_logic_vector(N_CONTEXTS-1 downto 0);
signal En : std_logic_vector(N_CONTEXTS-1 downto 0);
signal Dout : data_vector(N_CONTEXTS-1 downto 0);
begin -- simple
Regs : for i in N_CONTEXTS-1 downto 0 generate
Reg_i : Reg_Clr_En
generic map (
WIDTH => DATAWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ClrxEI => Clr(i),
EnxEI => En(i),
DinxDI => DinxDI,
DoutxDO => Dout(i));
end generate Regs;
-- FIXME: this can be written more elegantly
ClrDemux : process (ClrContextxSI, ClrContextxEI)
begin
for i in N_CONTEXTS-1 downto 0 loop
Clr(i) <= '0';
end loop; -- i
Clr(to_integer(unsigned(ClrContextxSI))) <= ClrContextxEI;
end process ClrDemux;
EnDemux : process (ContextxSI, EnxEI)
begin
for i in N_CONTEXTS-1 downto 0 loop
En(i) <= '0';
end loop; -- i
En(to_integer(unsigned(ContextxSI))) <= EnxEI;
end process EnDemux;
-- out mux
DoutxDO <= Dout(to_integer(unsigned(ContextxSI)));
end simple;
|
--
-- Copyright (C) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package hexutil is
function to_1(c : character) return std_logic;
function to_2(c : character) return std_logic_vector;
function to_3(c : character) return std_logic_vector;
function to_4(c : character) return std_logic_vector;
end package;
package body hexutil is
-- Return the bits of the supplied hex nibble
function to_4(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
case c is
when '0' =>
nibble := "0000";
when '1' =>
nibble := "0001";
when '2' =>
nibble := "0010";
when '3' =>
nibble := "0011";
when '4' =>
nibble := "0100";
when '5' =>
nibble := "0101";
when '6' =>
nibble := "0110";
when '7' =>
nibble := "0111";
when '8' =>
nibble := "1000";
when '9' =>
nibble := "1001";
when 'a' =>
nibble := "1010";
when 'A' =>
nibble := "1010";
when 'b' =>
nibble := "1011";
when 'B' =>
nibble := "1011";
when 'c' =>
nibble := "1100";
when 'C' =>
nibble := "1100";
when 'd' =>
nibble := "1101";
when 'D' =>
nibble := "1101";
when 'e' =>
nibble := "1110";
when 'E' =>
nibble := "1110";
when 'f' =>
nibble := "1111";
when 'F' =>
nibble := "1111";
when 'X' =>
nibble := "XXXX";
when 'x' =>
nibble := "XXXX";
when 'Z' =>
nibble := "ZZZZ";
when 'z' =>
nibble := "ZZZZ";
when others =>
nibble := "UUUU";
end case;
return nibble;
end function;
-- Return the least-significant bit of the supplied hex nibble
function to_1(c : character) return std_logic is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(0);
end function;
-- Return two least-significant bits of the supplied hex nibble
function to_2(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(1 downto 0);
end function;
-- Return three least-significant bits of the supplied hex nibble
function to_3(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(2 downto 0);
end function;
end package body;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of mux_1hot_inferred is
type mux_type is array (sel_bits-1 downto 0) of std_ulogic_vector(data_bits-1 downto 0);
type comb_type is record
m : mux_type;
end record;
signal c : comb_type;
begin
sel_bit_loop : for n in sel_bits-1 downto 0 generate
data_bit_loop : for m in data_bits-1 downto 0 generate
c.m(n)(m) <= din(n, m);
end generate;
end generate;
sel_bits_0 : if sel_bits = 0 generate
dout <= "";
end generate;
sel_bits_1 : if sel_bits = 1 generate
mux : block
signal sel_tmp : std_ulogic_vector(0 downto 0);
begin
sel_tmp <= sel(0 downto 0);
with sel_tmp select
dout <= c.m(0) when "1",
(others => 'X') when others;
end block;
end generate;
sel_bits_2 : if sel_bits = 2 generate
mux : block
signal sel_tmp : std_ulogic_vector(1 downto 0);
begin
sel_tmp <= sel(1 downto 0);
with sel_tmp select
dout <= c.m(0) when "01",
c.m(1) when "10",
(others => 'X') when others;
end block;
end generate;
sel_bits_3 : if sel_bits = 3 generate
mux : block
signal sel_tmp : std_ulogic_vector(2 downto 0);
begin
sel_tmp <= sel(2 downto 0);
with sel_tmp select
dout <= c.m(0) when "001",
c.m(1) when "010",
c.m(2) when "100",
(others => 'X') when others;
end block;
end generate;
sel_bits_4 : if sel_bits = 4 generate
mux : block
signal sel_tmp : std_ulogic_vector(3 downto 0);
begin
sel_tmp <= sel(3 downto 0);
with sel_tmp select
dout <= c.m(0) when "0001",
c.m(1) when "0010",
c.m(2) when "0100",
c.m(3) when "1000",
(others => 'X') when others;
end block;
end generate;
sel_bits_5 : if sel_bits = 5 generate
mux : block
signal sel_tmp : std_ulogic_vector(4 downto 0);
begin
sel_tmp <= sel(4 downto 0);
with sel_tmp select
dout <= c.m(0) when "00001",
c.m(1) when "00010",
c.m(2) when "00100",
c.m(3) when "01000",
c.m(4) when "10000",
(others => 'X') when others;
end block;
end generate;
sel_bits_6 : if sel_bits = 6 generate
mux : block
signal sel_tmp : std_ulogic_vector(5 downto 0);
begin
sel_tmp <= sel(5 downto 0);
with sel_tmp select
dout <= c.m(0) when "000001",
c.m(1) when "000010",
c.m(2) when "000100",
c.m(3) when "001000",
c.m(4) when "010000",
c.m(5) when "100000",
(others => 'X') when others;
end block;
end generate;
sel_bits_7 : if sel_bits = 7 generate
mux : block
signal sel_tmp : std_ulogic_vector(6 downto 0);
begin
sel_tmp <= sel(6 downto 0);
with sel_tmp select
dout <= c.m(0) when "0000001",
c.m(1) when "0000010",
c.m(2) when "0000100",
c.m(3) when "0001000",
c.m(4) when "0010000",
c.m(5) when "0100000",
c.m(6) when "1000000",
(others => 'X') when others;
end block;
end generate;
sel_bits_8 : if sel_bits = 8 generate
mux : block
signal sel_tmp : std_ulogic_vector(7 downto 0);
begin
sel_tmp <= sel(7 downto 0);
with sel_tmp select
dout <= c.m(0) when "00000001",
c.m(1) when "00000010",
c.m(2) when "00000100",
c.m(3) when "00001000",
c.m(4) when "00010000",
c.m(5) when "00100000",
c.m(6) when "01000000",
c.m(7) when "10000000",
(others => 'X') when others;
end block;
end generate;
sel_bits_out_of_range : if sel_bits > 8 generate
error_process : process is
begin
assert sel_bits <= 8 report "sel_bits out of range" severity failure;
wait;
end process;
end generate;
end;
|
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009. 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: blk_mem_gen_wrapper.vhd
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library blk_mem_gen_v8_2;
use blk_mem_gen_v8_2.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity blk_mem_gen_wrapper is
generic
(
-- Device Family
c_family : string := "virtex7";
c_xdevicefamily : string := "virtex7";
c_elaboration_dir : string := "";
-- Memory Specific Configurations
c_mem_type : integer := 2;
-- This wrapper only supports the True Dual Port RAM
-- 0: Single Port RAM
-- 1: Simple Dual Port RAM
-- 2: True Dual Port RAM
-- 3: Single Port Rom
-- 4: Dual Port RAM
c_algorithm : integer := 1;
-- 0: Selectable Primative
-- 1: Minimum Area
c_prim_type : integer := 1;
-- 0: ( 1-bit wide)
-- 1: ( 2-bit wide)
-- 2: ( 4-bit wide)
-- 3: ( 9-bit wide)
-- 4: (18-bit wide)
-- 5: (36-bit wide)
-- 6: (72-bit wide, single port only)
c_byte_size : integer := 9; -- 8 or 9
-- Simulation Behavior Options
c_sim_collision_check : string := "NONE";
-- "None"
-- "Generate_X"
-- "All"
-- "Warnings_only"
c_common_clk : integer := 1; -- 0, 1
c_disable_warn_bhv_coll : integer := 0; -- 0, 1
c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- Initialization Configuration Options
c_load_init_file : integer := 0;
c_init_file_name : string := "no_coe_file_loaded";
c_use_default_data : integer := 0; -- 0, 1
c_default_data : string := "0"; -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a : integer := 0; -- 0, 1
c_has_mux_output_regs_a : integer := 0; -- 0, 1
c_write_width_a : integer := 32; -- 1 to 1152
c_read_width_a : integer := 32; -- 1 to 1152
c_write_depth_a : integer := 64; -- 2 to 9011200
c_read_depth_a : integer := 64; -- 2 to 9011200
c_addra_width : integer := 6; -- 1 to 24
c_write_mode_a : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_ena : integer := 1; -- 0, 1
c_has_regcea : integer := 0; -- 0, 1
c_has_ssra : integer := 0; -- 0, 1
c_sinita_val : string := "0"; --"..."
c_use_byte_wea : integer := 0; -- 0, 1
c_wea_width : integer := 1; -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b : integer := 0; -- 0, 1
c_has_mux_output_regs_b : integer := 0; -- 0, 1
c_write_width_b : integer := 32; -- 1 to 1152
c_read_width_b : integer := 32; -- 1 to 1152
c_write_depth_b : integer := 64; -- 2 to 9011200
c_read_depth_b : integer := 64; -- 2 to 9011200
c_addrb_width : integer := 6; -- 1 to 24
c_write_mode_b : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_enb : integer := 1; -- 0, 1
c_has_regceb : integer := 0; -- 0, 1
c_has_ssrb : integer := 0; -- 0, 1
c_sinitb_val : string := "0"; -- "..."
c_use_byte_web : integer := 0; -- 0, 1
c_web_width : integer := 1; -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- The number of pipeline stages within the MUX
-- for both Port A and Port B
c_use_ecc : integer := 0;
-- See DS512 for the limited core option selections for ECC support
c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- c_corename : string := "blk_mem_gen_v2_7"
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
);
port
(
clka : in std_logic;
ssra : in std_logic := '0';
dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
addra : in std_logic_vector(c_addra_width-1 downto 0);
ena : in std_logic := '1';
regcea : in std_logic := '1';
wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
douta : out std_logic_vector(c_read_width_a-1 downto 0);
clkb : in std_logic := '0';
ssrb : in std_logic := '0';
dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
enb : in std_logic := '1';
regceb : in std_logic := '1';
web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
doutb : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr : out std_logic;
-- Double bit error that that cannot be auto corrected by ECC
sbiterr : out std_logic
-- Single Bit Error that has been auto corrected on the output bus
);
end entity blk_mem_gen_wrapper;
architecture implementation of blk_mem_gen_wrapper is
-- directly passing C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_AWREADY : STD_LOGIC;
signal S_AXI_WREADY : STD_LOGIC;
signal S_AXI_BID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_BVALID : STD_LOGIC;
signal S_AXI_ARREADY : STD_LOGIC;
signal S_AXI_RID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_RDATA : STD_LOGIC_VECTOR(c_write_width_b-1 DOWNTO 0);
signal S_AXI_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_RLAST : STD_LOGIC;
signal S_AXI_RVALID : STD_LOGIC;
signal S_AXI_SBITERR : STD_LOGIC;
signal S_AXI_DBITERR : STD_LOGIC;
signal S_AXI_RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_WSTRB : STD_LOGIC_VECTOR(c_wea_width-1 downto 0);
signal S_AXI_WDATA : STD_LOGIC_VECTOR(c_write_width_a-1 downto 0);
begin
S_AXI_WSTRB <= (others => '0');
S_AXI_WDATA <= (others => '0');
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until clka = '1';
-- wait until clka = '0';
-- Wait until clka = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low
-- douta <= (others => '0'); -- : out std_logic_vector(c_read_width_a-1 downto 0);
-- doutb <= (others => '0'); -- : out std_logic_vector(c_read_width_b-1 downto 0);
-- dbiterr <= '0' ; -- : out std_logic;
-- sbiterr <= '0' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the Block Memeory using blk_mem_gen 5.2.
-- This is for new cores designed and tested with FPGA
-- Families of Virtex-6, Spartan-6 and later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen Block Memory Generator Call module
-- for new IP BRAM implementations.
--
-------------------------------------------------------------------------------
I_TRUE_DUAL_PORT_BLK_MEM_GEN : entity blk_mem_gen_v8_2.blk_mem_gen_v8_2
generic map
(
--C_CORENAME => c_corename ,
-- Device Family
C_FAMILY => FAMILY_TO_USE ,
C_XDEVICEFAMILY => c_xdevicefamily ,
C_ELABORATION_DIR => c_elaboration_dir ,
------------------
C_INTERFACE_TYPE => 0 ,
C_USE_BRAM_BLOCK => 0 ,
C_AXI_TYPE => 0 ,
C_AXI_SLAVE_TYPE => 0 ,
C_HAS_AXI_ID => 0 ,
C_AXI_ID_WIDTH => 4 ,
------------------
-- Memory Specific Configurations
C_MEM_TYPE => c_mem_type ,
C_BYTE_SIZE => c_byte_size ,
C_ALGORITHM => c_algorithm ,
C_PRIM_TYPE => c_prim_type ,
C_LOAD_INIT_FILE => c_load_init_file ,
C_INIT_FILE_NAME => c_init_file_name ,
C_INIT_FILE => "" ,
C_USE_DEFAULT_DATA => c_use_default_data ,
C_DEFAULT_DATA => c_default_data ,
-- Port A Specific Configurations
--C_RST_TYPE => "SYNC" , --Removed in version v8_2
C_HAS_RSTA => c_has_ssra ,
C_RST_PRIORITY_A => "CE" ,
C_RSTRAM_A => 0 ,
C_INITA_VAL => c_sinita_val ,
C_HAS_ENA => c_has_ena ,
C_HAS_REGCEA => c_has_regcea ,
C_USE_BYTE_WEA => c_use_byte_wea ,
C_WEA_WIDTH => c_wea_width ,
C_WRITE_MODE_A => c_write_mode_a ,
C_WRITE_WIDTH_A => c_write_width_a ,
C_READ_WIDTH_A => c_read_width_a ,
C_WRITE_DEPTH_A => c_write_depth_a ,
C_READ_DEPTH_A => c_read_depth_a ,
C_ADDRA_WIDTH => c_addra_width ,
-- Port B Specific Configurations
C_HAS_RSTB => c_has_ssrb ,
C_RST_PRIORITY_B => "CE" ,
C_RSTRAM_B => 0 ,
C_INITB_VAL => c_sinitb_val ,
C_HAS_ENB => c_has_enb ,
C_HAS_REGCEB => c_has_regceb ,
C_USE_BYTE_WEB => c_use_byte_web ,
C_WEB_WIDTH => c_web_width ,
C_WRITE_MODE_B => c_write_mode_b ,
C_WRITE_WIDTH_B => c_write_width_b ,
C_READ_WIDTH_B => c_read_width_b ,
C_WRITE_DEPTH_B => c_write_depth_b ,
C_READ_DEPTH_B => c_read_depth_b ,
C_ADDRB_WIDTH => c_addrb_width ,
C_HAS_MEM_OUTPUT_REGS_A => c_has_mem_output_regs_a ,
C_HAS_MEM_OUTPUT_REGS_B => c_has_mem_output_regs_b ,
C_HAS_MUX_OUTPUT_REGS_A => c_has_mux_output_regs_a ,
C_HAS_MUX_OUTPUT_REGS_B => c_has_mux_output_regs_b ,
C_HAS_SOFTECC_INPUT_REGS_A => 0 ,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0 ,
-- Other Miscellaneous Configurations
C_MUX_PIPELINE_STAGES => c_mux_pipeline_stages ,
C_USE_SOFTECC => 0 ,
C_USE_ECC => c_use_ecc ,
C_EN_ECC_PIPE => 0 ,
-- New features in 2015.1
C_EN_DEEPSLEEP_PIN => 0 ,
C_EN_SHUTDOWN_PIN => 0 ,
C_USE_URAM => 0 ,
C_EN_RDADDRA_CHG => 0 ,
C_EN_RDADDRB_CHG => 0 ,
-- Simulation Behavior Options
C_HAS_INJECTERR => 0 ,
C_SIM_COLLISION_CHECK => c_sim_collision_check ,
C_COMMON_CLK => c_common_clk ,
C_DISABLE_WARN_BHV_COLL => c_disable_warn_bhv_coll ,
C_EN_SLEEP_PIN => 0 ,
C_DISABLE_WARN_BHV_RANGE => c_disable_warn_bhv_range
)
port map
(
CLKA => clka ,
RSTA => ssra ,
ENA => ena ,
REGCEA => regcea ,
WEA => wea ,
ADDRA => addra ,
DINA => dina ,
DOUTA => douta ,
CLKB => clkb ,
RSTB => ssrb ,
ENB => enb ,
REGCEB => regceb ,
WEB => web ,
ADDRB => addrb ,
DINB => dinb ,
DOUTB => doutb ,
INJECTSBITERR => '0' , -- input
INJECTDBITERR => '0' , -- input
SBITERR => sbiterr ,
DBITERR => dbiterr ,
RDADDRECC => RDADDRECC , -- output
ECCPIPECE => '0' ,
SLEEP => '0' ,
SHUTDOWN => '0' ,
DEEPSLEEP => '0' ,
-- AXI BMG Input and Output Port Declarations -- new for v6.2
-- new for v6.2
-- AXI Global Signals -- new for v6.2
S_AClk => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_ARESETN => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Write (write side) -- new for v6.2
S_AXI_AWID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_AWREADY => S_AXI_AWREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_WDATA => S_AXI_WDATA , -- : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WSTRB => S_AXI_WSTRB , -- : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WLAST => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WREADY => S_AXI_WREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BID => S_AXI_BID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_BRESP => S_AXI_BRESP , -- : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- new for v6.2
S_AXI_BVALID => S_AXI_BVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Read (Write side) -- new for v6.2
S_AXI_ARID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_ARREADY => S_AXI_ARREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RID => S_AXI_RID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_RDATA => S_AXI_RDATA , -- : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); -- new for v6.2
S_AXI_RRESP => S_AXI_RRESP , -- : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); -- new for v6.2
S_AXI_RLAST => S_AXI_RLAST , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RVALID => S_AXI_RVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Sideband Signals -- new for v6.2
S_AXI_INJECTSBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_INJECTDBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_SBITERR => S_AXI_SBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_DBITERR => S_AXI_DBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RDADDRECC => S_AXI_RDADDRECC -- : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) -- new for v6.2
);
end generate FAMILY_SUPPORTED;
end implementation;
|
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009. 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: blk_mem_gen_wrapper.vhd
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library blk_mem_gen_v8_2;
use blk_mem_gen_v8_2.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity blk_mem_gen_wrapper is
generic
(
-- Device Family
c_family : string := "virtex7";
c_xdevicefamily : string := "virtex7";
c_elaboration_dir : string := "";
-- Memory Specific Configurations
c_mem_type : integer := 2;
-- This wrapper only supports the True Dual Port RAM
-- 0: Single Port RAM
-- 1: Simple Dual Port RAM
-- 2: True Dual Port RAM
-- 3: Single Port Rom
-- 4: Dual Port RAM
c_algorithm : integer := 1;
-- 0: Selectable Primative
-- 1: Minimum Area
c_prim_type : integer := 1;
-- 0: ( 1-bit wide)
-- 1: ( 2-bit wide)
-- 2: ( 4-bit wide)
-- 3: ( 9-bit wide)
-- 4: (18-bit wide)
-- 5: (36-bit wide)
-- 6: (72-bit wide, single port only)
c_byte_size : integer := 9; -- 8 or 9
-- Simulation Behavior Options
c_sim_collision_check : string := "NONE";
-- "None"
-- "Generate_X"
-- "All"
-- "Warnings_only"
c_common_clk : integer := 1; -- 0, 1
c_disable_warn_bhv_coll : integer := 0; -- 0, 1
c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- Initialization Configuration Options
c_load_init_file : integer := 0;
c_init_file_name : string := "no_coe_file_loaded";
c_use_default_data : integer := 0; -- 0, 1
c_default_data : string := "0"; -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a : integer := 0; -- 0, 1
c_has_mux_output_regs_a : integer := 0; -- 0, 1
c_write_width_a : integer := 32; -- 1 to 1152
c_read_width_a : integer := 32; -- 1 to 1152
c_write_depth_a : integer := 64; -- 2 to 9011200
c_read_depth_a : integer := 64; -- 2 to 9011200
c_addra_width : integer := 6; -- 1 to 24
c_write_mode_a : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_ena : integer := 1; -- 0, 1
c_has_regcea : integer := 0; -- 0, 1
c_has_ssra : integer := 0; -- 0, 1
c_sinita_val : string := "0"; --"..."
c_use_byte_wea : integer := 0; -- 0, 1
c_wea_width : integer := 1; -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b : integer := 0; -- 0, 1
c_has_mux_output_regs_b : integer := 0; -- 0, 1
c_write_width_b : integer := 32; -- 1 to 1152
c_read_width_b : integer := 32; -- 1 to 1152
c_write_depth_b : integer := 64; -- 2 to 9011200
c_read_depth_b : integer := 64; -- 2 to 9011200
c_addrb_width : integer := 6; -- 1 to 24
c_write_mode_b : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_enb : integer := 1; -- 0, 1
c_has_regceb : integer := 0; -- 0, 1
c_has_ssrb : integer := 0; -- 0, 1
c_sinitb_val : string := "0"; -- "..."
c_use_byte_web : integer := 0; -- 0, 1
c_web_width : integer := 1; -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- The number of pipeline stages within the MUX
-- for both Port A and Port B
c_use_ecc : integer := 0;
-- See DS512 for the limited core option selections for ECC support
c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- c_corename : string := "blk_mem_gen_v2_7"
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
);
port
(
clka : in std_logic;
ssra : in std_logic := '0';
dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
addra : in std_logic_vector(c_addra_width-1 downto 0);
ena : in std_logic := '1';
regcea : in std_logic := '1';
wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
douta : out std_logic_vector(c_read_width_a-1 downto 0);
clkb : in std_logic := '0';
ssrb : in std_logic := '0';
dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
enb : in std_logic := '1';
regceb : in std_logic := '1';
web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
doutb : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr : out std_logic;
-- Double bit error that that cannot be auto corrected by ECC
sbiterr : out std_logic
-- Single Bit Error that has been auto corrected on the output bus
);
end entity blk_mem_gen_wrapper;
architecture implementation of blk_mem_gen_wrapper is
-- directly passing C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_AWREADY : STD_LOGIC;
signal S_AXI_WREADY : STD_LOGIC;
signal S_AXI_BID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_BVALID : STD_LOGIC;
signal S_AXI_ARREADY : STD_LOGIC;
signal S_AXI_RID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_RDATA : STD_LOGIC_VECTOR(c_write_width_b-1 DOWNTO 0);
signal S_AXI_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_RLAST : STD_LOGIC;
signal S_AXI_RVALID : STD_LOGIC;
signal S_AXI_SBITERR : STD_LOGIC;
signal S_AXI_DBITERR : STD_LOGIC;
signal S_AXI_RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_WSTRB : STD_LOGIC_VECTOR(c_wea_width-1 downto 0);
signal S_AXI_WDATA : STD_LOGIC_VECTOR(c_write_width_a-1 downto 0);
begin
S_AXI_WSTRB <= (others => '0');
S_AXI_WDATA <= (others => '0');
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until clka = '1';
-- wait until clka = '0';
-- Wait until clka = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low
-- douta <= (others => '0'); -- : out std_logic_vector(c_read_width_a-1 downto 0);
-- doutb <= (others => '0'); -- : out std_logic_vector(c_read_width_b-1 downto 0);
-- dbiterr <= '0' ; -- : out std_logic;
-- sbiterr <= '0' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the Block Memeory using blk_mem_gen 5.2.
-- This is for new cores designed and tested with FPGA
-- Families of Virtex-6, Spartan-6 and later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen Block Memory Generator Call module
-- for new IP BRAM implementations.
--
-------------------------------------------------------------------------------
I_TRUE_DUAL_PORT_BLK_MEM_GEN : entity blk_mem_gen_v8_2.blk_mem_gen_v8_2
generic map
(
--C_CORENAME => c_corename ,
-- Device Family
C_FAMILY => FAMILY_TO_USE ,
C_XDEVICEFAMILY => c_xdevicefamily ,
C_ELABORATION_DIR => c_elaboration_dir ,
------------------
C_INTERFACE_TYPE => 0 ,
C_USE_BRAM_BLOCK => 0 ,
C_AXI_TYPE => 0 ,
C_AXI_SLAVE_TYPE => 0 ,
C_HAS_AXI_ID => 0 ,
C_AXI_ID_WIDTH => 4 ,
------------------
-- Memory Specific Configurations
C_MEM_TYPE => c_mem_type ,
C_BYTE_SIZE => c_byte_size ,
C_ALGORITHM => c_algorithm ,
C_PRIM_TYPE => c_prim_type ,
C_LOAD_INIT_FILE => c_load_init_file ,
C_INIT_FILE_NAME => c_init_file_name ,
C_INIT_FILE => "" ,
C_USE_DEFAULT_DATA => c_use_default_data ,
C_DEFAULT_DATA => c_default_data ,
-- Port A Specific Configurations
--C_RST_TYPE => "SYNC" , --Removed in version v8_2
C_HAS_RSTA => c_has_ssra ,
C_RST_PRIORITY_A => "CE" ,
C_RSTRAM_A => 0 ,
C_INITA_VAL => c_sinita_val ,
C_HAS_ENA => c_has_ena ,
C_HAS_REGCEA => c_has_regcea ,
C_USE_BYTE_WEA => c_use_byte_wea ,
C_WEA_WIDTH => c_wea_width ,
C_WRITE_MODE_A => c_write_mode_a ,
C_WRITE_WIDTH_A => c_write_width_a ,
C_READ_WIDTH_A => c_read_width_a ,
C_WRITE_DEPTH_A => c_write_depth_a ,
C_READ_DEPTH_A => c_read_depth_a ,
C_ADDRA_WIDTH => c_addra_width ,
-- Port B Specific Configurations
C_HAS_RSTB => c_has_ssrb ,
C_RST_PRIORITY_B => "CE" ,
C_RSTRAM_B => 0 ,
C_INITB_VAL => c_sinitb_val ,
C_HAS_ENB => c_has_enb ,
C_HAS_REGCEB => c_has_regceb ,
C_USE_BYTE_WEB => c_use_byte_web ,
C_WEB_WIDTH => c_web_width ,
C_WRITE_MODE_B => c_write_mode_b ,
C_WRITE_WIDTH_B => c_write_width_b ,
C_READ_WIDTH_B => c_read_width_b ,
C_WRITE_DEPTH_B => c_write_depth_b ,
C_READ_DEPTH_B => c_read_depth_b ,
C_ADDRB_WIDTH => c_addrb_width ,
C_HAS_MEM_OUTPUT_REGS_A => c_has_mem_output_regs_a ,
C_HAS_MEM_OUTPUT_REGS_B => c_has_mem_output_regs_b ,
C_HAS_MUX_OUTPUT_REGS_A => c_has_mux_output_regs_a ,
C_HAS_MUX_OUTPUT_REGS_B => c_has_mux_output_regs_b ,
C_HAS_SOFTECC_INPUT_REGS_A => 0 ,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0 ,
-- Other Miscellaneous Configurations
C_MUX_PIPELINE_STAGES => c_mux_pipeline_stages ,
C_USE_SOFTECC => 0 ,
C_USE_ECC => c_use_ecc ,
C_EN_ECC_PIPE => 0 ,
-- New features in 2015.1
C_EN_DEEPSLEEP_PIN => 0 ,
C_EN_SHUTDOWN_PIN => 0 ,
C_USE_URAM => 0 ,
C_EN_RDADDRA_CHG => 0 ,
C_EN_RDADDRB_CHG => 0 ,
-- Simulation Behavior Options
C_HAS_INJECTERR => 0 ,
C_SIM_COLLISION_CHECK => c_sim_collision_check ,
C_COMMON_CLK => c_common_clk ,
C_DISABLE_WARN_BHV_COLL => c_disable_warn_bhv_coll ,
C_EN_SLEEP_PIN => 0 ,
C_DISABLE_WARN_BHV_RANGE => c_disable_warn_bhv_range
)
port map
(
CLKA => clka ,
RSTA => ssra ,
ENA => ena ,
REGCEA => regcea ,
WEA => wea ,
ADDRA => addra ,
DINA => dina ,
DOUTA => douta ,
CLKB => clkb ,
RSTB => ssrb ,
ENB => enb ,
REGCEB => regceb ,
WEB => web ,
ADDRB => addrb ,
DINB => dinb ,
DOUTB => doutb ,
INJECTSBITERR => '0' , -- input
INJECTDBITERR => '0' , -- input
SBITERR => sbiterr ,
DBITERR => dbiterr ,
RDADDRECC => RDADDRECC , -- output
ECCPIPECE => '0' ,
SLEEP => '0' ,
SHUTDOWN => '0' ,
DEEPSLEEP => '0' ,
-- AXI BMG Input and Output Port Declarations -- new for v6.2
-- new for v6.2
-- AXI Global Signals -- new for v6.2
S_AClk => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_ARESETN => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Write (write side) -- new for v6.2
S_AXI_AWID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_AWREADY => S_AXI_AWREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_WDATA => S_AXI_WDATA , -- : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WSTRB => S_AXI_WSTRB , -- : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WLAST => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WREADY => S_AXI_WREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BID => S_AXI_BID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_BRESP => S_AXI_BRESP , -- : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- new for v6.2
S_AXI_BVALID => S_AXI_BVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Read (Write side) -- new for v6.2
S_AXI_ARID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_ARREADY => S_AXI_ARREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RID => S_AXI_RID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_RDATA => S_AXI_RDATA , -- : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); -- new for v6.2
S_AXI_RRESP => S_AXI_RRESP , -- : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); -- new for v6.2
S_AXI_RLAST => S_AXI_RLAST , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RVALID => S_AXI_RVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Sideband Signals -- new for v6.2
S_AXI_INJECTSBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_INJECTDBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_SBITERR => S_AXI_SBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_DBITERR => S_AXI_DBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RDADDRECC => S_AXI_RDADDRECC -- : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) -- new for v6.2
);
end generate FAMILY_SUPPORTED;
end implementation;
|
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009. 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: blk_mem_gen_wrapper.vhd
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library blk_mem_gen_v8_2;
use blk_mem_gen_v8_2.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity blk_mem_gen_wrapper is
generic
(
-- Device Family
c_family : string := "virtex7";
c_xdevicefamily : string := "virtex7";
c_elaboration_dir : string := "";
-- Memory Specific Configurations
c_mem_type : integer := 2;
-- This wrapper only supports the True Dual Port RAM
-- 0: Single Port RAM
-- 1: Simple Dual Port RAM
-- 2: True Dual Port RAM
-- 3: Single Port Rom
-- 4: Dual Port RAM
c_algorithm : integer := 1;
-- 0: Selectable Primative
-- 1: Minimum Area
c_prim_type : integer := 1;
-- 0: ( 1-bit wide)
-- 1: ( 2-bit wide)
-- 2: ( 4-bit wide)
-- 3: ( 9-bit wide)
-- 4: (18-bit wide)
-- 5: (36-bit wide)
-- 6: (72-bit wide, single port only)
c_byte_size : integer := 9; -- 8 or 9
-- Simulation Behavior Options
c_sim_collision_check : string := "NONE";
-- "None"
-- "Generate_X"
-- "All"
-- "Warnings_only"
c_common_clk : integer := 1; -- 0, 1
c_disable_warn_bhv_coll : integer := 0; -- 0, 1
c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- Initialization Configuration Options
c_load_init_file : integer := 0;
c_init_file_name : string := "no_coe_file_loaded";
c_use_default_data : integer := 0; -- 0, 1
c_default_data : string := "0"; -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a : integer := 0; -- 0, 1
c_has_mux_output_regs_a : integer := 0; -- 0, 1
c_write_width_a : integer := 32; -- 1 to 1152
c_read_width_a : integer := 32; -- 1 to 1152
c_write_depth_a : integer := 64; -- 2 to 9011200
c_read_depth_a : integer := 64; -- 2 to 9011200
c_addra_width : integer := 6; -- 1 to 24
c_write_mode_a : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_ena : integer := 1; -- 0, 1
c_has_regcea : integer := 0; -- 0, 1
c_has_ssra : integer := 0; -- 0, 1
c_sinita_val : string := "0"; --"..."
c_use_byte_wea : integer := 0; -- 0, 1
c_wea_width : integer := 1; -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b : integer := 0; -- 0, 1
c_has_mux_output_regs_b : integer := 0; -- 0, 1
c_write_width_b : integer := 32; -- 1 to 1152
c_read_width_b : integer := 32; -- 1 to 1152
c_write_depth_b : integer := 64; -- 2 to 9011200
c_read_depth_b : integer := 64; -- 2 to 9011200
c_addrb_width : integer := 6; -- 1 to 24
c_write_mode_b : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_enb : integer := 1; -- 0, 1
c_has_regceb : integer := 0; -- 0, 1
c_has_ssrb : integer := 0; -- 0, 1
c_sinitb_val : string := "0"; -- "..."
c_use_byte_web : integer := 0; -- 0, 1
c_web_width : integer := 1; -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- The number of pipeline stages within the MUX
-- for both Port A and Port B
c_use_ecc : integer := 0;
-- See DS512 for the limited core option selections for ECC support
c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- c_corename : string := "blk_mem_gen_v2_7"
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
);
port
(
clka : in std_logic;
ssra : in std_logic := '0';
dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
addra : in std_logic_vector(c_addra_width-1 downto 0);
ena : in std_logic := '1';
regcea : in std_logic := '1';
wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
douta : out std_logic_vector(c_read_width_a-1 downto 0);
clkb : in std_logic := '0';
ssrb : in std_logic := '0';
dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
enb : in std_logic := '1';
regceb : in std_logic := '1';
web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
doutb : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr : out std_logic;
-- Double bit error that that cannot be auto corrected by ECC
sbiterr : out std_logic
-- Single Bit Error that has been auto corrected on the output bus
);
end entity blk_mem_gen_wrapper;
architecture implementation of blk_mem_gen_wrapper is
-- directly passing C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_AWREADY : STD_LOGIC;
signal S_AXI_WREADY : STD_LOGIC;
signal S_AXI_BID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_BVALID : STD_LOGIC;
signal S_AXI_ARREADY : STD_LOGIC;
signal S_AXI_RID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_RDATA : STD_LOGIC_VECTOR(c_write_width_b-1 DOWNTO 0);
signal S_AXI_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_RLAST : STD_LOGIC;
signal S_AXI_RVALID : STD_LOGIC;
signal S_AXI_SBITERR : STD_LOGIC;
signal S_AXI_DBITERR : STD_LOGIC;
signal S_AXI_RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_WSTRB : STD_LOGIC_VECTOR(c_wea_width-1 downto 0);
signal S_AXI_WDATA : STD_LOGIC_VECTOR(c_write_width_a-1 downto 0);
begin
S_AXI_WSTRB <= (others => '0');
S_AXI_WDATA <= (others => '0');
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until clka = '1';
-- wait until clka = '0';
-- Wait until clka = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low
-- douta <= (others => '0'); -- : out std_logic_vector(c_read_width_a-1 downto 0);
-- doutb <= (others => '0'); -- : out std_logic_vector(c_read_width_b-1 downto 0);
-- dbiterr <= '0' ; -- : out std_logic;
-- sbiterr <= '0' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the Block Memeory using blk_mem_gen 5.2.
-- This is for new cores designed and tested with FPGA
-- Families of Virtex-6, Spartan-6 and later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen Block Memory Generator Call module
-- for new IP BRAM implementations.
--
-------------------------------------------------------------------------------
I_TRUE_DUAL_PORT_BLK_MEM_GEN : entity blk_mem_gen_v8_2.blk_mem_gen_v8_2
generic map
(
--C_CORENAME => c_corename ,
-- Device Family
C_FAMILY => FAMILY_TO_USE ,
C_XDEVICEFAMILY => c_xdevicefamily ,
C_ELABORATION_DIR => c_elaboration_dir ,
------------------
C_INTERFACE_TYPE => 0 ,
C_USE_BRAM_BLOCK => 0 ,
C_AXI_TYPE => 0 ,
C_AXI_SLAVE_TYPE => 0 ,
C_HAS_AXI_ID => 0 ,
C_AXI_ID_WIDTH => 4 ,
------------------
-- Memory Specific Configurations
C_MEM_TYPE => c_mem_type ,
C_BYTE_SIZE => c_byte_size ,
C_ALGORITHM => c_algorithm ,
C_PRIM_TYPE => c_prim_type ,
C_LOAD_INIT_FILE => c_load_init_file ,
C_INIT_FILE_NAME => c_init_file_name ,
C_INIT_FILE => "" ,
C_USE_DEFAULT_DATA => c_use_default_data ,
C_DEFAULT_DATA => c_default_data ,
-- Port A Specific Configurations
--C_RST_TYPE => "SYNC" , --Removed in version v8_2
C_HAS_RSTA => c_has_ssra ,
C_RST_PRIORITY_A => "CE" ,
C_RSTRAM_A => 0 ,
C_INITA_VAL => c_sinita_val ,
C_HAS_ENA => c_has_ena ,
C_HAS_REGCEA => c_has_regcea ,
C_USE_BYTE_WEA => c_use_byte_wea ,
C_WEA_WIDTH => c_wea_width ,
C_WRITE_MODE_A => c_write_mode_a ,
C_WRITE_WIDTH_A => c_write_width_a ,
C_READ_WIDTH_A => c_read_width_a ,
C_WRITE_DEPTH_A => c_write_depth_a ,
C_READ_DEPTH_A => c_read_depth_a ,
C_ADDRA_WIDTH => c_addra_width ,
-- Port B Specific Configurations
C_HAS_RSTB => c_has_ssrb ,
C_RST_PRIORITY_B => "CE" ,
C_RSTRAM_B => 0 ,
C_INITB_VAL => c_sinitb_val ,
C_HAS_ENB => c_has_enb ,
C_HAS_REGCEB => c_has_regceb ,
C_USE_BYTE_WEB => c_use_byte_web ,
C_WEB_WIDTH => c_web_width ,
C_WRITE_MODE_B => c_write_mode_b ,
C_WRITE_WIDTH_B => c_write_width_b ,
C_READ_WIDTH_B => c_read_width_b ,
C_WRITE_DEPTH_B => c_write_depth_b ,
C_READ_DEPTH_B => c_read_depth_b ,
C_ADDRB_WIDTH => c_addrb_width ,
C_HAS_MEM_OUTPUT_REGS_A => c_has_mem_output_regs_a ,
C_HAS_MEM_OUTPUT_REGS_B => c_has_mem_output_regs_b ,
C_HAS_MUX_OUTPUT_REGS_A => c_has_mux_output_regs_a ,
C_HAS_MUX_OUTPUT_REGS_B => c_has_mux_output_regs_b ,
C_HAS_SOFTECC_INPUT_REGS_A => 0 ,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0 ,
-- Other Miscellaneous Configurations
C_MUX_PIPELINE_STAGES => c_mux_pipeline_stages ,
C_USE_SOFTECC => 0 ,
C_USE_ECC => c_use_ecc ,
C_EN_ECC_PIPE => 0 ,
-- New features in 2015.1
C_EN_DEEPSLEEP_PIN => 0 ,
C_EN_SHUTDOWN_PIN => 0 ,
C_USE_URAM => 0 ,
C_EN_RDADDRA_CHG => 0 ,
C_EN_RDADDRB_CHG => 0 ,
-- Simulation Behavior Options
C_HAS_INJECTERR => 0 ,
C_SIM_COLLISION_CHECK => c_sim_collision_check ,
C_COMMON_CLK => c_common_clk ,
C_DISABLE_WARN_BHV_COLL => c_disable_warn_bhv_coll ,
C_EN_SLEEP_PIN => 0 ,
C_DISABLE_WARN_BHV_RANGE => c_disable_warn_bhv_range
)
port map
(
CLKA => clka ,
RSTA => ssra ,
ENA => ena ,
REGCEA => regcea ,
WEA => wea ,
ADDRA => addra ,
DINA => dina ,
DOUTA => douta ,
CLKB => clkb ,
RSTB => ssrb ,
ENB => enb ,
REGCEB => regceb ,
WEB => web ,
ADDRB => addrb ,
DINB => dinb ,
DOUTB => doutb ,
INJECTSBITERR => '0' , -- input
INJECTDBITERR => '0' , -- input
SBITERR => sbiterr ,
DBITERR => dbiterr ,
RDADDRECC => RDADDRECC , -- output
ECCPIPECE => '0' ,
SLEEP => '0' ,
SHUTDOWN => '0' ,
DEEPSLEEP => '0' ,
-- AXI BMG Input and Output Port Declarations -- new for v6.2
-- new for v6.2
-- AXI Global Signals -- new for v6.2
S_AClk => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_ARESETN => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Write (write side) -- new for v6.2
S_AXI_AWID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_AWREADY => S_AXI_AWREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_WDATA => S_AXI_WDATA , -- : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WSTRB => S_AXI_WSTRB , -- : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WLAST => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WREADY => S_AXI_WREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BID => S_AXI_BID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_BRESP => S_AXI_BRESP , -- : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- new for v6.2
S_AXI_BVALID => S_AXI_BVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Read (Write side) -- new for v6.2
S_AXI_ARID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_ARREADY => S_AXI_ARREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RID => S_AXI_RID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_RDATA => S_AXI_RDATA , -- : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); -- new for v6.2
S_AXI_RRESP => S_AXI_RRESP , -- : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); -- new for v6.2
S_AXI_RLAST => S_AXI_RLAST , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RVALID => S_AXI_RVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Sideband Signals -- new for v6.2
S_AXI_INJECTSBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_INJECTDBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_SBITERR => S_AXI_SBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_DBITERR => S_AXI_DBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RDADDRECC => S_AXI_RDADDRECC -- : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) -- new for v6.2
);
end generate FAMILY_SUPPORTED;
end implementation;
|
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009. 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: blk_mem_gen_wrapper.vhd
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library blk_mem_gen_v8_2;
use blk_mem_gen_v8_2.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity blk_mem_gen_wrapper is
generic
(
-- Device Family
c_family : string := "virtex7";
c_xdevicefamily : string := "virtex7";
c_elaboration_dir : string := "";
-- Memory Specific Configurations
c_mem_type : integer := 2;
-- This wrapper only supports the True Dual Port RAM
-- 0: Single Port RAM
-- 1: Simple Dual Port RAM
-- 2: True Dual Port RAM
-- 3: Single Port Rom
-- 4: Dual Port RAM
c_algorithm : integer := 1;
-- 0: Selectable Primative
-- 1: Minimum Area
c_prim_type : integer := 1;
-- 0: ( 1-bit wide)
-- 1: ( 2-bit wide)
-- 2: ( 4-bit wide)
-- 3: ( 9-bit wide)
-- 4: (18-bit wide)
-- 5: (36-bit wide)
-- 6: (72-bit wide, single port only)
c_byte_size : integer := 9; -- 8 or 9
-- Simulation Behavior Options
c_sim_collision_check : string := "NONE";
-- "None"
-- "Generate_X"
-- "All"
-- "Warnings_only"
c_common_clk : integer := 1; -- 0, 1
c_disable_warn_bhv_coll : integer := 0; -- 0, 1
c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- Initialization Configuration Options
c_load_init_file : integer := 0;
c_init_file_name : string := "no_coe_file_loaded";
c_use_default_data : integer := 0; -- 0, 1
c_default_data : string := "0"; -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a : integer := 0; -- 0, 1
c_has_mux_output_regs_a : integer := 0; -- 0, 1
c_write_width_a : integer := 32; -- 1 to 1152
c_read_width_a : integer := 32; -- 1 to 1152
c_write_depth_a : integer := 64; -- 2 to 9011200
c_read_depth_a : integer := 64; -- 2 to 9011200
c_addra_width : integer := 6; -- 1 to 24
c_write_mode_a : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_ena : integer := 1; -- 0, 1
c_has_regcea : integer := 0; -- 0, 1
c_has_ssra : integer := 0; -- 0, 1
c_sinita_val : string := "0"; --"..."
c_use_byte_wea : integer := 0; -- 0, 1
c_wea_width : integer := 1; -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b : integer := 0; -- 0, 1
c_has_mux_output_regs_b : integer := 0; -- 0, 1
c_write_width_b : integer := 32; -- 1 to 1152
c_read_width_b : integer := 32; -- 1 to 1152
c_write_depth_b : integer := 64; -- 2 to 9011200
c_read_depth_b : integer := 64; -- 2 to 9011200
c_addrb_width : integer := 6; -- 1 to 24
c_write_mode_b : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_enb : integer := 1; -- 0, 1
c_has_regceb : integer := 0; -- 0, 1
c_has_ssrb : integer := 0; -- 0, 1
c_sinitb_val : string := "0"; -- "..."
c_use_byte_web : integer := 0; -- 0, 1
c_web_width : integer := 1; -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- The number of pipeline stages within the MUX
-- for both Port A and Port B
c_use_ecc : integer := 0;
-- See DS512 for the limited core option selections for ECC support
c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- c_corename : string := "blk_mem_gen_v2_7"
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
);
port
(
clka : in std_logic;
ssra : in std_logic := '0';
dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
addra : in std_logic_vector(c_addra_width-1 downto 0);
ena : in std_logic := '1';
regcea : in std_logic := '1';
wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
douta : out std_logic_vector(c_read_width_a-1 downto 0);
clkb : in std_logic := '0';
ssrb : in std_logic := '0';
dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
enb : in std_logic := '1';
regceb : in std_logic := '1';
web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
doutb : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr : out std_logic;
-- Double bit error that that cannot be auto corrected by ECC
sbiterr : out std_logic
-- Single Bit Error that has been auto corrected on the output bus
);
end entity blk_mem_gen_wrapper;
architecture implementation of blk_mem_gen_wrapper is
-- directly passing C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_AWREADY : STD_LOGIC;
signal S_AXI_WREADY : STD_LOGIC;
signal S_AXI_BID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_BVALID : STD_LOGIC;
signal S_AXI_ARREADY : STD_LOGIC;
signal S_AXI_RID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_RDATA : STD_LOGIC_VECTOR(c_write_width_b-1 DOWNTO 0);
signal S_AXI_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_RLAST : STD_LOGIC;
signal S_AXI_RVALID : STD_LOGIC;
signal S_AXI_SBITERR : STD_LOGIC;
signal S_AXI_DBITERR : STD_LOGIC;
signal S_AXI_RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_WSTRB : STD_LOGIC_VECTOR(c_wea_width-1 downto 0);
signal S_AXI_WDATA : STD_LOGIC_VECTOR(c_write_width_a-1 downto 0);
begin
S_AXI_WSTRB <= (others => '0');
S_AXI_WDATA <= (others => '0');
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until clka = '1';
-- wait until clka = '0';
-- Wait until clka = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low
-- douta <= (others => '0'); -- : out std_logic_vector(c_read_width_a-1 downto 0);
-- doutb <= (others => '0'); -- : out std_logic_vector(c_read_width_b-1 downto 0);
-- dbiterr <= '0' ; -- : out std_logic;
-- sbiterr <= '0' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the Block Memeory using blk_mem_gen 5.2.
-- This is for new cores designed and tested with FPGA
-- Families of Virtex-6, Spartan-6 and later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen Block Memory Generator Call module
-- for new IP BRAM implementations.
--
-------------------------------------------------------------------------------
I_TRUE_DUAL_PORT_BLK_MEM_GEN : entity blk_mem_gen_v8_2.blk_mem_gen_v8_2
generic map
(
--C_CORENAME => c_corename ,
-- Device Family
C_FAMILY => FAMILY_TO_USE ,
C_XDEVICEFAMILY => c_xdevicefamily ,
C_ELABORATION_DIR => c_elaboration_dir ,
------------------
C_INTERFACE_TYPE => 0 ,
C_USE_BRAM_BLOCK => 0 ,
C_AXI_TYPE => 0 ,
C_AXI_SLAVE_TYPE => 0 ,
C_HAS_AXI_ID => 0 ,
C_AXI_ID_WIDTH => 4 ,
------------------
-- Memory Specific Configurations
C_MEM_TYPE => c_mem_type ,
C_BYTE_SIZE => c_byte_size ,
C_ALGORITHM => c_algorithm ,
C_PRIM_TYPE => c_prim_type ,
C_LOAD_INIT_FILE => c_load_init_file ,
C_INIT_FILE_NAME => c_init_file_name ,
C_INIT_FILE => "" ,
C_USE_DEFAULT_DATA => c_use_default_data ,
C_DEFAULT_DATA => c_default_data ,
-- Port A Specific Configurations
--C_RST_TYPE => "SYNC" , --Removed in version v8_2
C_HAS_RSTA => c_has_ssra ,
C_RST_PRIORITY_A => "CE" ,
C_RSTRAM_A => 0 ,
C_INITA_VAL => c_sinita_val ,
C_HAS_ENA => c_has_ena ,
C_HAS_REGCEA => c_has_regcea ,
C_USE_BYTE_WEA => c_use_byte_wea ,
C_WEA_WIDTH => c_wea_width ,
C_WRITE_MODE_A => c_write_mode_a ,
C_WRITE_WIDTH_A => c_write_width_a ,
C_READ_WIDTH_A => c_read_width_a ,
C_WRITE_DEPTH_A => c_write_depth_a ,
C_READ_DEPTH_A => c_read_depth_a ,
C_ADDRA_WIDTH => c_addra_width ,
-- Port B Specific Configurations
C_HAS_RSTB => c_has_ssrb ,
C_RST_PRIORITY_B => "CE" ,
C_RSTRAM_B => 0 ,
C_INITB_VAL => c_sinitb_val ,
C_HAS_ENB => c_has_enb ,
C_HAS_REGCEB => c_has_regceb ,
C_USE_BYTE_WEB => c_use_byte_web ,
C_WEB_WIDTH => c_web_width ,
C_WRITE_MODE_B => c_write_mode_b ,
C_WRITE_WIDTH_B => c_write_width_b ,
C_READ_WIDTH_B => c_read_width_b ,
C_WRITE_DEPTH_B => c_write_depth_b ,
C_READ_DEPTH_B => c_read_depth_b ,
C_ADDRB_WIDTH => c_addrb_width ,
C_HAS_MEM_OUTPUT_REGS_A => c_has_mem_output_regs_a ,
C_HAS_MEM_OUTPUT_REGS_B => c_has_mem_output_regs_b ,
C_HAS_MUX_OUTPUT_REGS_A => c_has_mux_output_regs_a ,
C_HAS_MUX_OUTPUT_REGS_B => c_has_mux_output_regs_b ,
C_HAS_SOFTECC_INPUT_REGS_A => 0 ,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0 ,
-- Other Miscellaneous Configurations
C_MUX_PIPELINE_STAGES => c_mux_pipeline_stages ,
C_USE_SOFTECC => 0 ,
C_USE_ECC => c_use_ecc ,
C_EN_ECC_PIPE => 0 ,
-- New features in 2015.1
C_EN_DEEPSLEEP_PIN => 0 ,
C_EN_SHUTDOWN_PIN => 0 ,
C_USE_URAM => 0 ,
C_EN_RDADDRA_CHG => 0 ,
C_EN_RDADDRB_CHG => 0 ,
-- Simulation Behavior Options
C_HAS_INJECTERR => 0 ,
C_SIM_COLLISION_CHECK => c_sim_collision_check ,
C_COMMON_CLK => c_common_clk ,
C_DISABLE_WARN_BHV_COLL => c_disable_warn_bhv_coll ,
C_EN_SLEEP_PIN => 0 ,
C_DISABLE_WARN_BHV_RANGE => c_disable_warn_bhv_range
)
port map
(
CLKA => clka ,
RSTA => ssra ,
ENA => ena ,
REGCEA => regcea ,
WEA => wea ,
ADDRA => addra ,
DINA => dina ,
DOUTA => douta ,
CLKB => clkb ,
RSTB => ssrb ,
ENB => enb ,
REGCEB => regceb ,
WEB => web ,
ADDRB => addrb ,
DINB => dinb ,
DOUTB => doutb ,
INJECTSBITERR => '0' , -- input
INJECTDBITERR => '0' , -- input
SBITERR => sbiterr ,
DBITERR => dbiterr ,
RDADDRECC => RDADDRECC , -- output
ECCPIPECE => '0' ,
SLEEP => '0' ,
SHUTDOWN => '0' ,
DEEPSLEEP => '0' ,
-- AXI BMG Input and Output Port Declarations -- new for v6.2
-- new for v6.2
-- AXI Global Signals -- new for v6.2
S_AClk => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_ARESETN => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Write (write side) -- new for v6.2
S_AXI_AWID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_AWREADY => S_AXI_AWREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_WDATA => S_AXI_WDATA , -- : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WSTRB => S_AXI_WSTRB , -- : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WLAST => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WREADY => S_AXI_WREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BID => S_AXI_BID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_BRESP => S_AXI_BRESP , -- : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- new for v6.2
S_AXI_BVALID => S_AXI_BVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Read (Write side) -- new for v6.2
S_AXI_ARID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_ARREADY => S_AXI_ARREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RID => S_AXI_RID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_RDATA => S_AXI_RDATA , -- : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); -- new for v6.2
S_AXI_RRESP => S_AXI_RRESP , -- : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); -- new for v6.2
S_AXI_RLAST => S_AXI_RLAST , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RVALID => S_AXI_RVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Sideband Signals -- new for v6.2
S_AXI_INJECTSBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_INJECTDBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_SBITERR => S_AXI_SBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_DBITERR => S_AXI_DBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RDADDRECC => S_AXI_RDADDRECC -- : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) -- new for v6.2
);
end generate FAMILY_SUPPORTED;
end implementation;
|
package ffaccel_imem_mau is
-- created by generatebits
constant IMEMMAUWIDTH : positive := 43;
end ffaccel_imem_mau;
|
package ffaccel_imem_mau is
-- created by generatebits
constant IMEMMAUWIDTH : positive := 43;
end ffaccel_imem_mau;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:37:35 10/06/2016
-- Design Name:
-- Module Name: C:/Users/utp.CRIE/Desktop/sparcv8-monocicle/Test_alu.vhd
-- Project Name: monocicle-sparcv8
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: alu
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_alu IS
END Test_alu;
ARCHITECTURE behavior OF Test_alu IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT alu
PORT(
aluop : IN std_logic_vector(5 downto 0);
crs1 : IN std_logic_vector(31 downto 0);
crs2 : IN std_logic_vector(31 downto 0);
r : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal aluop : std_logic_vector(5 downto 0) := (others => '0');
signal crs1 : std_logic_vector(31 downto 0) := (others => '0');
signal crs2 : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal r : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: alu PORT MAP (
aluop => aluop,
crs1 => crs1,
crs2 => crs2,
r => r
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
crs1 <= x"00000005";
crs2 <= x"00000004";
aluop<= "000000";
wait for 100 ns;
aluop<= "000001";
wait for 100 ns;
aluop<= "000010";
wait for 100 ns;
aluop<= "000011";
wait for 100 ns;
aluop<= "000100";
wait for 100 ns;
aluop<= "000101";
wait for 100 ns;
aluop<= "000110";
wait for 100 ns;
aluop<= "000111";
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_mb_700a is
generic (
g_version : unsigned(7 downto 0) := X"04" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- memory
SDRAM_A : out std_logic_vector(12 downto 0); -- DRAM A
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- LED Interface
LED_CLK : out std_logic;
LED_DATA : out std_logic;
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end entity;
architecture structural of ultimate_mb_700a is
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
-- signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3a_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_clock_2x => sys_clock_2x );
i_logic: entity work.ultimate_logic_32
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => false,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_hardware_iec => true,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => false,
g_usb_host => false,
g_usb_host2 => true,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false,
g_sampler => true,
g_analyzer => false,
g_profiler => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- LED interface
LED_CLK => LED_CLK,
LED_DATA => LED_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
vid_clock => sys_clock,
vid_reset => sys_reset,
vid_h_count => X"000",
vid_v_count => X"000",
vid_active => open,
vid_opaque => open,
vid_data => open,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_mem_ctrl: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => false )
port map (
clock => sys_clock,
clk_2x => sys_clock_2x,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_BA,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ );
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 09:06:21 2017
-- Host : Shaun running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/Shaun/Desktop/ip_repo/axi_compression_1.0/src/output_fifo/output_fifo_sim_netlist.vhdl
-- Design : output_fifo
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end output_fifo_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of output_fifo_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_16\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_17\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_24\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_25\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35\ : STD_LOGIC;
signal tmp_ram_regce : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 4) => Q(9 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 4) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(3 downto 0) => B"0000",
CLKARDCLK => clk,
CLKBWRCLK => clk,
DIADI(15 downto 14) => B"00",
DIADI(13 downto 8) => din(11 downto 6),
DIADI(7 downto 6) => B"00",
DIADI(5 downto 0) => din(5 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_16\,
DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_17\,
DOBDO(13 downto 8) => dout(11 downto 6),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_24\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_25\,
DOBDO(5 downto 0) => dout(5 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35\,
ENARDEN => WEA(0),
ENBWREN => tmp_ram_rd_en,
REGCEAREGCE => '0',
REGCEB => tmp_ram_regce,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => srst,
WEA(1) => WEA(0),
WEA(0) => WEA(0),
WEBWE(3 downto 0) => B"0000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => srst,
I1 => ram_rd_en_d1,
O => tmp_ram_regce
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_compare is
port (
ram_full_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
\out\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_compare : entity is "compare";
end output_fifo_compare;
architecture STRUCTURE of output_fifo_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFC0FFC05500FFC0"
)
port map (
I0 => comp0,
I1 => wr_en,
I2 => comp1,
I3 => \out\,
I4 => rd_en,
I5 => ram_empty_fb_i_reg,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_compare_0 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_compare_0 : entity is "compare";
end output_fifo_compare_0;
architecture STRUCTURE of output_fifo_compare_0 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_compare_1 is
port (
ram_empty_i_reg : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_compare_1 : entity is "compare";
end output_fifo_compare_1;
architecture STRUCTURE of output_fifo_compare_1 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gcc0.gc0.count_d1_reg[6]\,
S(2) => \gcc0.gc0.count_d1_reg[4]\,
S(1) => \gcc0.gc0.count_d1_reg[2]\,
S(0) => \gcc0.gc0.count_d1_reg[0]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gcc0.gc0.count_d1_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCF0FCF05050FCF0"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
I4 => wr_en,
I5 => ram_full_fb_i_reg,
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_compare_2 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_compare_2 : entity is "compare";
end output_fifo_compare_2;
architecture STRUCTURE of output_fifo_compare_2 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_rd_bin_cntr : entity is "rd_bin_cntr";
end output_fifo_rd_bin_cntr;
architecture STRUCTURE of output_fifo_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair0";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
I2 => \^q\(7),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(7),
I3 => \^q\(8),
O => plusOp(8)
);
\gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(7),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(8),
I4 => \^q\(9),
O => plusOp(9)
);
\gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gc0.count[9]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(0),
R => srst
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(1),
R => srst
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(2),
R => srst
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(3),
R => srst
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(4),
R => srst
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(5),
R => srst
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(6),
R => srst
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(7),
R => srst
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(8),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(8),
R => srst
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(9),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9),
R => srst
);
\gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
Q => \^q\(0),
S => srst
);
\gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(1),
Q => \^q\(1),
R => srst
);
\gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(2),
Q => \^q\(2),
R => srst
);
\gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(3),
Q => \^q\(3),
R => srst
);
\gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(4),
Q => \^q\(4),
R => srst
);
\gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(5),
Q => \^q\(5),
R => srst
);
\gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(6),
Q => \^q\(6),
R => srst
);
\gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(7),
Q => \^q\(7),
R => srst
);
\gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(8),
Q => \^q\(8),
R => srst
);
\gc0.count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(9),
Q => \^q\(9),
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_wr_bin_cntr is
port (
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_wr_bin_cntr : entity is "wr_bin_cntr";
end output_fifo_wr_bin_cntr;
architecture STRUCTURE of output_fifo_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gcc0.gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[6]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gcc0.gc0.count[9]_i_1\ : label is "soft_lutpair4";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
I2 => p_12_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(1),
I1 => p_12_out(0),
I2 => p_12_out(2),
I3 => p_12_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
I4 => p_12_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => p_12_out(3),
I1 => p_12_out(1),
I2 => p_12_out(0),
I3 => p_12_out(2),
I4 => p_12_out(4),
I5 => p_12_out(5),
O => \plusOp__0\(5)
);
\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gcc0.gc0.count[9]_i_2_n_0\,
I1 => p_12_out(6),
O => \plusOp__0\(6)
);
\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gcc0.gc0.count[9]_i_2_n_0\,
I1 => p_12_out(6),
I2 => p_12_out(7),
O => \plusOp__0\(7)
);
\gcc0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(6),
I1 => \gcc0.gc0.count[9]_i_2_n_0\,
I2 => p_12_out(7),
I3 => p_12_out(8),
O => \plusOp__0\(8)
);
\gcc0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(7),
I1 => \gcc0.gc0.count[9]_i_2_n_0\,
I2 => p_12_out(6),
I3 => p_12_out(8),
I4 => p_12_out(9),
O => \plusOp__0\(9)
);
\gcc0.gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => p_12_out(5),
I1 => p_12_out(3),
I2 => p_12_out(1),
I3 => p_12_out(0),
I4 => p_12_out(2),
I5 => p_12_out(4),
O => \gcc0.gc0.count[9]_i_2_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(0),
Q => \^q\(0),
R => srst
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(1),
Q => \^q\(1),
R => srst
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(2),
Q => \^q\(2),
R => srst
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(3),
Q => \^q\(3),
R => srst
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(4),
Q => \^q\(4),
R => srst
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(5),
Q => \^q\(5),
R => srst
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(6),
Q => \^q\(6),
R => srst
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(7),
Q => \^q\(7),
R => srst
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(8),
Q => \^q\(8),
R => srst
);
\gcc0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(9),
Q => \^q\(9),
R => srst
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
Q => p_12_out(0),
S => srst
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(1),
Q => p_12_out(1),
R => srst
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(2),
Q => p_12_out(2),
R => srst
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(3),
Q => p_12_out(3),
R => srst
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(4),
Q => p_12_out(4),
R => srst
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(5),
Q => p_12_out(5),
R => srst
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(6),
Q => p_12_out(6),
R => srst
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(7),
Q => p_12_out(7),
R => srst
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(8),
Q => p_12_out(8),
R => srst
);
\gcc0.gc0.count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(9),
Q => p_12_out(9),
R => srst
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_reg[9]\(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => ram_empty_i_reg
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_reg[9]\(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => ram_empty_i_reg_0
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_reg[9]\(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => p_12_out(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => ram_empty_i_reg_1
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_reg[9]\(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => p_12_out(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => ram_empty_i_reg_2
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_reg[9]\(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => p_12_out(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => v1_reg_1(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => ram_empty_i_reg_3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end output_fifo_blk_mem_gen_prim_width;
architecture STRUCTURE of output_fifo_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.output_fifo_blk_mem_gen_prim_wrapper
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_rd_status_flags_ss : entity is "rd_status_flags_ss";
end output_fifo_rd_status_flags_ss;
architecture STRUCTURE of output_fifo_rd_status_flags_ss is
signal c1_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => ram_empty_fb_i,
I1 => rd_en,
I2 => srst,
O => tmp_ram_rd_en
);
c1: entity work.output_fifo_compare_1
port map (
comp1 => comp1,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => ram_empty_fb_i,
ram_empty_i_reg => c1_n_0,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
wr_en => wr_en
);
c2: entity work.output_fifo_compare_2
port map (
comp1 => comp1,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
\gbm.gregce.ram_rd_en_d1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
Q => ram_empty_fb_i,
S => srst
);
ram_empty_i_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
Q => ram_empty_i,
S => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_wr_status_flags_ss : entity is "wr_status_flags_ss";
end output_fifo_wr_status_flags_ss;
architecture STRUCTURE of output_fifo_wr_status_flags_ss is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
c0: entity work.output_fifo_compare
port map (
comp1 => comp1,
\out\ => ram_full_fb_i,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
wr_en => wr_en
);
c1: entity work.output_fifo_compare_0
port map (
comp1 => comp1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => c0_n_0,
Q => ram_full_fb_i,
R => srst
);
ram_full_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => c0_n_0,
Q => ram_full_i,
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end output_fifo_blk_mem_gen_generic_cstr;
architecture STRUCTURE of output_fifo_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.output_fifo_blk_mem_gen_prim_width
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_rd_logic : entity is "rd_logic";
end output_fifo_rd_logic;
architecture STRUCTURE of output_fifo_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
E(0) <= \^e\(0);
\grss.rsts\: entity work.output_fifo_rd_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => \out\,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
wr_en => wr_en
);
rpntr: entity work.output_fifo_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0),
E(0) => \^e\(0),
Q(9 downto 0) => Q(9 downto 0),
clk => clk,
srst => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_wr_logic is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
WEA : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
srst : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_wr_logic : entity is "wr_logic";
end output_fifo_wr_logic;
architecture STRUCTURE of output_fifo_wr_logic is
signal \^wea\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
WEA(0) <= \^wea\(0);
\gwss.wsts\: entity work.output_fifo_wr_status_flags_ss
port map (
E(0) => \^wea\(0),
clk => clk,
full => full,
\out\ => \out\,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
rd_en => rd_en,
srst => srst,
v1_reg(4 downto 0) => \c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \c1/v1_reg\(4 downto 0),
wr_en => wr_en
);
wpntr: entity work.output_fifo_wr_bin_cntr
port map (
E(0) => \^wea\(0),
Q(9 downto 0) => Q(9 downto 0),
clk => clk,
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => \gc0.count_reg[9]\(9 downto 0),
ram_empty_i_reg => ram_empty_i_reg,
ram_empty_i_reg_0 => ram_empty_i_reg_0,
ram_empty_i_reg_1 => ram_empty_i_reg_1,
ram_empty_i_reg_2 => ram_empty_i_reg_2,
ram_empty_i_reg_3 => ram_empty_i_reg_3,
srst => srst,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => \c0/v1_reg\(4 downto 0),
v1_reg_1(4 downto 0) => \c1/v1_reg\(4 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_top : entity is "blk_mem_gen_top";
end output_fifo_blk_mem_gen_top;
architecture STRUCTURE of output_fifo_blk_mem_gen_top is
begin
\valid.cstr\: entity work.output_fifo_blk_mem_gen_generic_cstr
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_v8_3_5_synth is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end output_fifo_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of output_fifo_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.output_fifo_blk_mem_gen_top
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_v8_3_5 is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
end output_fifo_blk_mem_gen_v8_3_5;
architecture STRUCTURE of output_fifo_blk_mem_gen_v8_3_5 is
begin
inst_blk_mem_gen: entity work.output_fifo_blk_mem_gen_v8_3_5_synth
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_memory is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_memory : entity is "memory";
end output_fifo_memory;
architecture STRUCTURE of output_fifo_memory is
signal ram_rd_en_d1 : STD_LOGIC;
begin
\gbm.gbmg.gbmgc.ngecc.bmg\: entity work.output_fifo_blk_mem_gen_v8_3_5
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\gbm.gregce.ram_rd_en_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => E(0),
Q => ram_rd_en_d1,
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end output_fifo_fifo_generator_ramfifo;
architecture STRUCTURE of output_fifo_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.rd_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_18\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_19\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_20\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_21\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_22\ : STD_LOGIC;
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal tmp_ram_rd_en : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.output_fifo_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) => p_0_out(9 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(9 downto 0) => rd_pntr_plus1(9 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_18\,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_19\,
\gcc0.gc0.count_d1_reg[4]\ => \gntv_or_sync_fifo.gl0.wr_n_20\,
\gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_21\,
\gcc0.gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.wr_n_22\,
\out\ => p_2_out,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.output_fifo_wr_logic
port map (
Q(9 downto 0) => p_11_out(9 downto 0),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
clk => clk,
full => full,
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_18\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_19\,
ram_empty_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_20\,
ram_empty_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_21\,
ram_empty_i_reg_3 => \gntv_or_sync_fifo.gl0.wr_n_22\,
rd_en => rd_en,
srst => srst,
v1_reg(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.output_fifo_memory
port map (
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(9 downto 0) => p_11_out(9 downto 0),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_fifo_generator_top : entity is "fifo_generator_top";
end output_fifo_fifo_generator_top;
architecture STRUCTURE of output_fifo_fifo_generator_top is
begin
\grf.rf\: entity work.output_fifo_fifo_generator_ramfifo
port map (
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_fifo_generator_v13_1_3_synth is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_fifo_generator_v13_1_3_synth : entity is "fifo_generator_v13_1_3_synth";
end output_fifo_fifo_generator_v13_1_3_synth;
architecture STRUCTURE of output_fifo_fifo_generator_v13_1_3_synth is
begin
\gconvfifo.rf\: entity work.output_fifo_fifo_generator_top
port map (
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_fifo_generator_v13_1_3 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of output_fifo_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 12;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of output_fifo_fifo_generator_v13_1_3 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 12;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of output_fifo_fifo_generator_v13_1_3 : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of output_fifo_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of output_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of output_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_fifo_generator_v13_1_3 : entity is "fifo_generator_v13_1_3";
end output_fifo_fifo_generator_v13_1_3;
architecture STRUCTURE of output_fifo_fifo_generator_v13_1_3 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.output_fifo_fifo_generator_v13_1_3_synth
port map (
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo is
port (
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of output_fifo : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of output_fifo : entity is "output_fifo,fifo_generator_v13_1_3,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of output_fifo : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of output_fifo : entity is "fifo_generator_v13_1_3,Vivado 2016.4";
end output_fifo;
architecture STRUCTURE of output_fifo is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 12;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 12;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 2;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 1;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.output_fifo_fifo_generator_v13_1_3
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => '0',
rd_data_count(9 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(9 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => '0',
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => srst,
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(9 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(9 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 09:06:21 2017
-- Host : Shaun running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/Shaun/Desktop/ip_repo/axi_compression_1.0/src/output_fifo/output_fifo_sim_netlist.vhdl
-- Design : output_fifo
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end output_fifo_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of output_fifo_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_16\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_17\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_24\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_25\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35\ : STD_LOGIC;
signal tmp_ram_regce : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 4) => Q(9 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 4) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(3 downto 0) => B"0000",
CLKARDCLK => clk,
CLKBWRCLK => clk,
DIADI(15 downto 14) => B"00",
DIADI(13 downto 8) => din(11 downto 6),
DIADI(7 downto 6) => B"00",
DIADI(5 downto 0) => din(5 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_16\,
DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_17\,
DOBDO(13 downto 8) => dout(11 downto 6),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_24\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_25\,
DOBDO(5 downto 0) => dout(5 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35\,
ENARDEN => WEA(0),
ENBWREN => tmp_ram_rd_en,
REGCEAREGCE => '0',
REGCEB => tmp_ram_regce,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => srst,
WEA(1) => WEA(0),
WEA(0) => WEA(0),
WEBWE(3 downto 0) => B"0000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => srst,
I1 => ram_rd_en_d1,
O => tmp_ram_regce
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_compare is
port (
ram_full_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
\out\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_compare : entity is "compare";
end output_fifo_compare;
architecture STRUCTURE of output_fifo_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFC0FFC05500FFC0"
)
port map (
I0 => comp0,
I1 => wr_en,
I2 => comp1,
I3 => \out\,
I4 => rd_en,
I5 => ram_empty_fb_i_reg,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_compare_0 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_compare_0 : entity is "compare";
end output_fifo_compare_0;
architecture STRUCTURE of output_fifo_compare_0 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_compare_1 is
port (
ram_empty_i_reg : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_compare_1 : entity is "compare";
end output_fifo_compare_1;
architecture STRUCTURE of output_fifo_compare_1 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gcc0.gc0.count_d1_reg[6]\,
S(2) => \gcc0.gc0.count_d1_reg[4]\,
S(1) => \gcc0.gc0.count_d1_reg[2]\,
S(0) => \gcc0.gc0.count_d1_reg[0]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gcc0.gc0.count_d1_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCF0FCF05050FCF0"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
I4 => wr_en,
I5 => ram_full_fb_i_reg,
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_compare_2 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_compare_2 : entity is "compare";
end output_fifo_compare_2;
architecture STRUCTURE of output_fifo_compare_2 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_rd_bin_cntr : entity is "rd_bin_cntr";
end output_fifo_rd_bin_cntr;
architecture STRUCTURE of output_fifo_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair0";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
I2 => \^q\(7),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(7),
I3 => \^q\(8),
O => plusOp(8)
);
\gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(7),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(8),
I4 => \^q\(9),
O => plusOp(9)
);
\gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gc0.count[9]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(0),
R => srst
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(1),
R => srst
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(2),
R => srst
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(3),
R => srst
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(4),
R => srst
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(5),
R => srst
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(6),
R => srst
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(7),
R => srst
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(8),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(8),
R => srst
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(9),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9),
R => srst
);
\gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
Q => \^q\(0),
S => srst
);
\gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(1),
Q => \^q\(1),
R => srst
);
\gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(2),
Q => \^q\(2),
R => srst
);
\gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(3),
Q => \^q\(3),
R => srst
);
\gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(4),
Q => \^q\(4),
R => srst
);
\gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(5),
Q => \^q\(5),
R => srst
);
\gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(6),
Q => \^q\(6),
R => srst
);
\gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(7),
Q => \^q\(7),
R => srst
);
\gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(8),
Q => \^q\(8),
R => srst
);
\gc0.count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(9),
Q => \^q\(9),
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_wr_bin_cntr is
port (
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_wr_bin_cntr : entity is "wr_bin_cntr";
end output_fifo_wr_bin_cntr;
architecture STRUCTURE of output_fifo_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gcc0.gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[6]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gcc0.gc0.count[9]_i_1\ : label is "soft_lutpair4";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
I2 => p_12_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(1),
I1 => p_12_out(0),
I2 => p_12_out(2),
I3 => p_12_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
I4 => p_12_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => p_12_out(3),
I1 => p_12_out(1),
I2 => p_12_out(0),
I3 => p_12_out(2),
I4 => p_12_out(4),
I5 => p_12_out(5),
O => \plusOp__0\(5)
);
\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gcc0.gc0.count[9]_i_2_n_0\,
I1 => p_12_out(6),
O => \plusOp__0\(6)
);
\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gcc0.gc0.count[9]_i_2_n_0\,
I1 => p_12_out(6),
I2 => p_12_out(7),
O => \plusOp__0\(7)
);
\gcc0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(6),
I1 => \gcc0.gc0.count[9]_i_2_n_0\,
I2 => p_12_out(7),
I3 => p_12_out(8),
O => \plusOp__0\(8)
);
\gcc0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(7),
I1 => \gcc0.gc0.count[9]_i_2_n_0\,
I2 => p_12_out(6),
I3 => p_12_out(8),
I4 => p_12_out(9),
O => \plusOp__0\(9)
);
\gcc0.gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => p_12_out(5),
I1 => p_12_out(3),
I2 => p_12_out(1),
I3 => p_12_out(0),
I4 => p_12_out(2),
I5 => p_12_out(4),
O => \gcc0.gc0.count[9]_i_2_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(0),
Q => \^q\(0),
R => srst
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(1),
Q => \^q\(1),
R => srst
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(2),
Q => \^q\(2),
R => srst
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(3),
Q => \^q\(3),
R => srst
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(4),
Q => \^q\(4),
R => srst
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(5),
Q => \^q\(5),
R => srst
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(6),
Q => \^q\(6),
R => srst
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(7),
Q => \^q\(7),
R => srst
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(8),
Q => \^q\(8),
R => srst
);
\gcc0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(9),
Q => \^q\(9),
R => srst
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
Q => p_12_out(0),
S => srst
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(1),
Q => p_12_out(1),
R => srst
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(2),
Q => p_12_out(2),
R => srst
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(3),
Q => p_12_out(3),
R => srst
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(4),
Q => p_12_out(4),
R => srst
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(5),
Q => p_12_out(5),
R => srst
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(6),
Q => p_12_out(6),
R => srst
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(7),
Q => p_12_out(7),
R => srst
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(8),
Q => p_12_out(8),
R => srst
);
\gcc0.gc0.count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(9),
Q => p_12_out(9),
R => srst
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_reg[9]\(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => ram_empty_i_reg
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_reg[9]\(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => ram_empty_i_reg_0
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_reg[9]\(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => p_12_out(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => ram_empty_i_reg_1
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_reg[9]\(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => p_12_out(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => ram_empty_i_reg_2
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_reg[9]\(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => p_12_out(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => v1_reg_1(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => ram_empty_i_reg_3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end output_fifo_blk_mem_gen_prim_width;
architecture STRUCTURE of output_fifo_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.output_fifo_blk_mem_gen_prim_wrapper
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_rd_status_flags_ss : entity is "rd_status_flags_ss";
end output_fifo_rd_status_flags_ss;
architecture STRUCTURE of output_fifo_rd_status_flags_ss is
signal c1_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => ram_empty_fb_i,
I1 => rd_en,
I2 => srst,
O => tmp_ram_rd_en
);
c1: entity work.output_fifo_compare_1
port map (
comp1 => comp1,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => ram_empty_fb_i,
ram_empty_i_reg => c1_n_0,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
wr_en => wr_en
);
c2: entity work.output_fifo_compare_2
port map (
comp1 => comp1,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
\gbm.gregce.ram_rd_en_d1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
Q => ram_empty_fb_i,
S => srst
);
ram_empty_i_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
Q => ram_empty_i,
S => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_wr_status_flags_ss : entity is "wr_status_flags_ss";
end output_fifo_wr_status_flags_ss;
architecture STRUCTURE of output_fifo_wr_status_flags_ss is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
c0: entity work.output_fifo_compare
port map (
comp1 => comp1,
\out\ => ram_full_fb_i,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
wr_en => wr_en
);
c1: entity work.output_fifo_compare_0
port map (
comp1 => comp1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => c0_n_0,
Q => ram_full_fb_i,
R => srst
);
ram_full_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => c0_n_0,
Q => ram_full_i,
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end output_fifo_blk_mem_gen_generic_cstr;
architecture STRUCTURE of output_fifo_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.output_fifo_blk_mem_gen_prim_width
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_rd_logic : entity is "rd_logic";
end output_fifo_rd_logic;
architecture STRUCTURE of output_fifo_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
E(0) <= \^e\(0);
\grss.rsts\: entity work.output_fifo_rd_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => \out\,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
wr_en => wr_en
);
rpntr: entity work.output_fifo_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0),
E(0) => \^e\(0),
Q(9 downto 0) => Q(9 downto 0),
clk => clk,
srst => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_wr_logic is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
WEA : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
srst : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_wr_logic : entity is "wr_logic";
end output_fifo_wr_logic;
architecture STRUCTURE of output_fifo_wr_logic is
signal \^wea\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
WEA(0) <= \^wea\(0);
\gwss.wsts\: entity work.output_fifo_wr_status_flags_ss
port map (
E(0) => \^wea\(0),
clk => clk,
full => full,
\out\ => \out\,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
rd_en => rd_en,
srst => srst,
v1_reg(4 downto 0) => \c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \c1/v1_reg\(4 downto 0),
wr_en => wr_en
);
wpntr: entity work.output_fifo_wr_bin_cntr
port map (
E(0) => \^wea\(0),
Q(9 downto 0) => Q(9 downto 0),
clk => clk,
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => \gc0.count_reg[9]\(9 downto 0),
ram_empty_i_reg => ram_empty_i_reg,
ram_empty_i_reg_0 => ram_empty_i_reg_0,
ram_empty_i_reg_1 => ram_empty_i_reg_1,
ram_empty_i_reg_2 => ram_empty_i_reg_2,
ram_empty_i_reg_3 => ram_empty_i_reg_3,
srst => srst,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => \c0/v1_reg\(4 downto 0),
v1_reg_1(4 downto 0) => \c1/v1_reg\(4 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_top : entity is "blk_mem_gen_top";
end output_fifo_blk_mem_gen_top;
architecture STRUCTURE of output_fifo_blk_mem_gen_top is
begin
\valid.cstr\: entity work.output_fifo_blk_mem_gen_generic_cstr
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_v8_3_5_synth is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end output_fifo_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of output_fifo_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.output_fifo_blk_mem_gen_top
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_v8_3_5 is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
end output_fifo_blk_mem_gen_v8_3_5;
architecture STRUCTURE of output_fifo_blk_mem_gen_v8_3_5 is
begin
inst_blk_mem_gen: entity work.output_fifo_blk_mem_gen_v8_3_5_synth
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_memory is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_memory : entity is "memory";
end output_fifo_memory;
architecture STRUCTURE of output_fifo_memory is
signal ram_rd_en_d1 : STD_LOGIC;
begin
\gbm.gbmg.gbmgc.ngecc.bmg\: entity work.output_fifo_blk_mem_gen_v8_3_5
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\gbm.gregce.ram_rd_en_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => E(0),
Q => ram_rd_en_d1,
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end output_fifo_fifo_generator_ramfifo;
architecture STRUCTURE of output_fifo_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.rd_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_18\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_19\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_20\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_21\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_22\ : STD_LOGIC;
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal tmp_ram_rd_en : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.output_fifo_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) => p_0_out(9 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(9 downto 0) => rd_pntr_plus1(9 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_18\,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_19\,
\gcc0.gc0.count_d1_reg[4]\ => \gntv_or_sync_fifo.gl0.wr_n_20\,
\gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_21\,
\gcc0.gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.wr_n_22\,
\out\ => p_2_out,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.output_fifo_wr_logic
port map (
Q(9 downto 0) => p_11_out(9 downto 0),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
clk => clk,
full => full,
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_18\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_19\,
ram_empty_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_20\,
ram_empty_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_21\,
ram_empty_i_reg_3 => \gntv_or_sync_fifo.gl0.wr_n_22\,
rd_en => rd_en,
srst => srst,
v1_reg(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.output_fifo_memory
port map (
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(9 downto 0) => p_11_out(9 downto 0),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_fifo_generator_top : entity is "fifo_generator_top";
end output_fifo_fifo_generator_top;
architecture STRUCTURE of output_fifo_fifo_generator_top is
begin
\grf.rf\: entity work.output_fifo_fifo_generator_ramfifo
port map (
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_fifo_generator_v13_1_3_synth is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_fifo_generator_v13_1_3_synth : entity is "fifo_generator_v13_1_3_synth";
end output_fifo_fifo_generator_v13_1_3_synth;
architecture STRUCTURE of output_fifo_fifo_generator_v13_1_3_synth is
begin
\gconvfifo.rf\: entity work.output_fifo_fifo_generator_top
port map (
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_fifo_generator_v13_1_3 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of output_fifo_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 12;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of output_fifo_fifo_generator_v13_1_3 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 12;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of output_fifo_fifo_generator_v13_1_3 : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of output_fifo_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of output_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of output_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_fifo_generator_v13_1_3 : entity is "fifo_generator_v13_1_3";
end output_fifo_fifo_generator_v13_1_3;
architecture STRUCTURE of output_fifo_fifo_generator_v13_1_3 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.output_fifo_fifo_generator_v13_1_3_synth
port map (
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo is
port (
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of output_fifo : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of output_fifo : entity is "output_fifo,fifo_generator_v13_1_3,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of output_fifo : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of output_fifo : entity is "fifo_generator_v13_1_3,Vivado 2016.4";
end output_fifo;
architecture STRUCTURE of output_fifo is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 12;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 12;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 2;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 1;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.output_fifo_fifo_generator_v13_1_3
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => '0',
rd_data_count(9 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(9 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => '0',
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => srst,
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(9 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(9 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
entity test is
type t is range 0 to 1e2;
end;
|
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is begin
end block;
BLOCK_LABEL : block is begin
end block;
end architecture RTL;
|
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, component, if-then-else, procedure, constant.
entity ENT00006 is
port(
latch : in boolean
);
end entity;
architecture ARCH00006 of ENT00006 is
constant flag_const : boolean := true;
signal flag : boolean := false;
signal cond : boolean;
procedure print_report_valid (cond : in boolean) is
begin
if cond then
report "OK. flag = flag_const" severity NOTE;
else
report "error: flag /= flag_const" severity NOTE;
end if;
end procedure;
type boolVec is array (integer range <>) of boolean;
signal step : boolVec(1 to 3) := (others => false);
signal flag2 : boolean;
begin
flag2 <= flag_const;
process(step)
variable init : boolean := true;
variable v : boolean;
begin
if init then
step(1) <= true;
init := false;
elsif step(1) then
step(1) <= false;
step(2) <= true;
flag <= flag_const;
v := cond;
elsif step(2) then
cond <= flag = flag_const;
step(2) <= false;
step(3) <= true;
v := cond;
elsif step(3) then
v := cond;
print_report_valid(cond);
step(3) <= false;
else
null;
end if;
end process;
end ARCH00006;
entity ENT00006_Test_Bench is
end entity;
architecture ARCH00006_Test_Bench of ENT00006_Test_Bench is
component ENT00006 is
port(
latch : in boolean
);
end component;
signal latch : boolean := false;
begin
latch <= not latch after 1 us;
UUT1: ENT00006
port map (
latch => latch
);
UUT2: ENT00006
port map (
latch => latch
);
end ARCH00006_Test_Bench; |
-- This file is part of the ethernet_mac_test project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
library ieee;
use ieee.std_logic_1164.all;
entity reset_generator is
generic(
-- 20 ms at 125 MHz clock
-- Minimum 88E1111 reset pulse width: 10 ms
RESET_DELAY : positive := 2500000
);
port(
clock_i : in std_ulogic;
locked_i : in std_ulogic;
reset_o : out std_ulogic
);
end entity;
architecture rtl of reset_generator is
signal reset_cnt : natural range 0 to RESET_DELAY := 0;
begin
reset_proc : process(clock_i, locked_i)
begin
if locked_i = '1' then
if rising_edge(clock_i) then
-- When locked, wait for RESET_DELAY ticks, then deassert reset
if reset_cnt < RESET_DELAY then
reset_cnt <= reset_cnt + 1;
reset_o <= '1';
else
reset_o <= '0';
end if;
end if;
else
-- Keep in reset when not locked
reset_cnt <= 0;
reset_o <= '1';
end if;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2779.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ARRAY is
end ARRAY;
ENTITY c13s09b00x00p99n01i02779ent IS
END c13s09b00x00p99n01i02779ent;
ARCHITECTURE c13s09b00x00p99n01i02779arch OF c13s09b00x00p99n01i02779ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02779 - Reserved word ARRAY can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02779_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2779.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ARRAY is
end ARRAY;
ENTITY c13s09b00x00p99n01i02779ent IS
END c13s09b00x00p99n01i02779ent;
ARCHITECTURE c13s09b00x00p99n01i02779arch OF c13s09b00x00p99n01i02779ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02779 - Reserved word ARRAY can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02779_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2779.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ARRAY is
end ARRAY;
ENTITY c13s09b00x00p99n01i02779ent IS
END c13s09b00x00p99n01i02779ent;
ARCHITECTURE c13s09b00x00p99n01i02779arch OF c13s09b00x00p99n01i02779ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02779 - Reserved word ARRAY can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02779_arch;
|
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
entity halfAdder is
-- Half, 1 bit adder
port(
a, b : in std_logic;
s, c : out std_logic
);
end entity halfAdder;
architecture rtl of halfAdder is
begin
s <= a xor b;
c <= a and b;
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2849.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity WHILE is
end WHILE;
ENTITY c13s09b00x00p99n01i02849ent IS
END c13s09b00x00p99n01i02849ent;
ARCHITECTURE c13s09b00x00p99n01i02849arch OF c13s09b00x00p99n01i02849ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02849 - Reserved word WHILE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02849arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2849.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity WHILE is
end WHILE;
ENTITY c13s09b00x00p99n01i02849ent IS
END c13s09b00x00p99n01i02849ent;
ARCHITECTURE c13s09b00x00p99n01i02849arch OF c13s09b00x00p99n01i02849ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02849 - Reserved word WHILE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02849arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2849.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity WHILE is
end WHILE;
ENTITY c13s09b00x00p99n01i02849ent IS
END c13s09b00x00p99n01i02849ent;
ARCHITECTURE c13s09b00x00p99n01i02849arch OF c13s09b00x00p99n01i02849ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02849 - Reserved word WHILE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02849arch;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fx2_fifo_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fx2_fifo_pkg.ALL;
ENTITY fx2_fifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fx2_fifo_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fx2_fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:56:37 06/19/2014
-- Design Name:
-- Module Name: C:/Users/fafik/Dropbox/infa/git/ethernet/ethernet4b/control_unit_test1.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: control_unit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY control_unit_test1 IS
END control_unit_test1;
ARCHITECTURE behavior OF control_unit_test1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT control_unit
PORT(
clk : IN std_logic;
reset : IN std_logic;
data_in : IN std_logic_vector(3 downto 0);
data_received_in : IN std_logic;
interrupt : IN std_logic;
crc_en : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal data_in : std_logic_vector(3 downto 0) := (others => '0');
signal data_received_in : std_logic := '0';
signal interrupt : std_logic := '0';
--Outputs
signal crc_en : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: control_unit PORT MAP (
clk => clk,
reset => reset,
data_in => data_in,
data_received_in => data_received_in,
interrupt => interrupt,
crc_en => crc_en
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset <= '0';
data_received_in <= '0', '1' after 100 ns, '0' after 120 ns;
interrupt <= '0', '1' after 500 ns, '0' after 520 ns;
END;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
-- library UNISIM;
-- use UNISIM.VComponents.all;
entity Mux2to1_8bit is
port(A, B : in std_logic_vector(7 downto 0);
sel : in std_logic;
S : out std_logic_vector(7 downto 0));
end Mux2to1_8bit;
architecture Behavioral of Mux2to1_8bit is
begin
with sel select
s <= A when '0',
B when '1',
"XXXXXXXX" when others;
end Behavioral; |
-------------------------------------------------------------------------------
-- system_dlmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_10_c;
use lmb_bram_if_cntlr_v3_10_c.all;
entity system_dlmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_dlmb_cntlr_wrapper : entity is "lmb_bram_if_cntlr_v3_10_c";
end system_dlmb_cntlr_wrapper;
architecture STRUCTURE of system_dlmb_cntlr_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_FAMILY : string;
C_MASK : std_logic_vector(0 to 31);
C_MASK1 : std_logic_vector(0 to 31);
C_MASK2 : std_logic_vector(0 to 31);
C_MASK3 : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_ECC : integer;
C_INTERCONNECT : integer;
C_FAULT_INJECT : integer;
C_CE_FAILING_REGISTERS : integer;
C_UE_FAILING_REGISTERS : integer;
C_ECC_STATUS_REGISTERS : integer;
C_ECC_ONOFF_REGISTER : integer;
C_ECC_ONOFF_RESET_VALUE : integer;
C_CE_COUNTER_WIDTH : integer;
C_WRITE_ACCESS : integer;
C_NUM_LMB : integer;
C_SPLB_CTRL_BASEADDR : std_logic_vector;
C_SPLB_CTRL_HIGHADDR : std_logic_vector;
C_SPLB_CTRL_AWIDTH : INTEGER;
C_SPLB_CTRL_DWIDTH : INTEGER;
C_SPLB_CTRL_P2P : INTEGER;
C_SPLB_CTRL_MID_WIDTH : INTEGER;
C_SPLB_CTRL_NUM_MASTERS : INTEGER;
C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER;
C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER;
C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1));
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1));
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
begin
dlmb_cntlr : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00000fff",
C_FAMILY => "virtex5",
C_MASK => X"80000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_NUM_LMB => 1,
C_SPLB_CTRL_BASEADDR => X"FFFFFFFF",
C_SPLB_CTRL_HIGHADDR => X"00000000",
C_SPLB_CTRL_AWIDTH => 32,
C_SPLB_CTRL_DWIDTH => 32,
C_SPLB_CTRL_P2P => 0,
C_SPLB_CTRL_MID_WIDTH => 1,
C_SPLB_CTRL_NUM_MASTERS => 1,
C_SPLB_CTRL_SUPPORT_BURSTS => 0,
C_SPLB_CTRL_NATIVE_DWIDTH => 32,
C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF",
C_S_AXI_CTRL_HIGHADDR => X"00000000",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
Interrupt => Interrupt,
UE => UE,
CE => CE,
SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus,
SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid,
SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID,
SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW,
SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE,
SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size,
SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type,
SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus,
SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck,
SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize,
SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait,
SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate,
SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck,
SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp,
SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus,
SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck,
SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp,
SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy,
SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr,
SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr,
SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus,
SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid,
SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim,
SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim,
SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort,
SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock,
SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize,
SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr,
SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst,
SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst,
SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq,
SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq,
SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri,
SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri,
SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri,
SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute,
SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm,
SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr,
SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm,
SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ,
S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY
);
end architecture STRUCTURE;
|
-- $Id: ib_intmap.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ib_intmap - syn
-- Description: pdp11: external interrupt mapper (15 line)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2017.2; ghdl 0.18-0.35
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic MHz
-- 2016-05-26 641 2016.4 xc7a100t-1 0 30 0 0 - -
-- 2015-02-22 641 i 14.7 xc6slx16-2 0 20 0 0 9 -
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-23 1136 1.2 BUGFIX: ensure ACK send to correct device
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2008-08-22 161 1.2.1 renamed pdp11_ -> ib_; use iblib
-- 2008-01-20 112 1.2 add INTMAP generic to externalize config
-- 2008-01-06 111 1.1 add EI_ACK output lines, remove EI_LINE
-- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_intmap is -- external interrupt mapper
generic (
INTMAP : intmap_array_type := intmap_array_init);
port (
CLK : in slbit; -- clock
EI_REQ : in slv16_1; -- interrupt request lines
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_ACK : out slv16_1; -- interrupt acknowledge (to requestor)
EI_PRI : out slv3; -- interrupt priority
EI_VECT : out slv9_2 -- interrupt vector
);
end ib_intmap;
architecture syn of ib_intmap is
signal EI_LINE : slv4 := (others=>'0'); -- external interrupt line
signal R_LINE : slv4 := (others=>'0'); -- line on last cycle
type intp_type is array (15 downto 0) of slv3;
type intv_type is array (15 downto 0) of slv9;
constant conf_intp : intp_type :=
(slv(to_unsigned(INTMAP(15).pri,3)), -- line 15
slv(to_unsigned(INTMAP(14).pri,3)), -- line 14
slv(to_unsigned(INTMAP(13).pri,3)), -- line 13
slv(to_unsigned(INTMAP(12).pri,3)), -- line 12
slv(to_unsigned(INTMAP(11).pri,3)), -- line 11
slv(to_unsigned(INTMAP(10).pri,3)), -- line 10
slv(to_unsigned(INTMAP( 9).pri,3)), -- line 9
slv(to_unsigned(INTMAP( 8).pri,3)), -- line 8
slv(to_unsigned(INTMAP( 7).pri,3)), -- line 7
slv(to_unsigned(INTMAP( 6).pri,3)), -- line 6
slv(to_unsigned(INTMAP( 5).pri,3)), -- line 5
slv(to_unsigned(INTMAP( 4).pri,3)), -- line 4
slv(to_unsigned(INTMAP( 3).pri,3)), -- line 3
slv(to_unsigned(INTMAP( 2).pri,3)), -- line 2
slv(to_unsigned(INTMAP( 1).pri,3)), -- line 1
slv(to_unsigned( 0,3)) -- line 0 (always 0 !!)
);
constant conf_intv : intv_type :=
(slv(to_unsigned(INTMAP(15).vec,9)), -- line 15
slv(to_unsigned(INTMAP(14).vec,9)), -- line 14
slv(to_unsigned(INTMAP(13).vec,9)), -- line 13
slv(to_unsigned(INTMAP(12).vec,9)), -- line 12
slv(to_unsigned(INTMAP(11).vec,9)), -- line 11
slv(to_unsigned(INTMAP(10).vec,9)), -- line 10
slv(to_unsigned(INTMAP( 9).vec,9)), -- line 9
slv(to_unsigned(INTMAP( 8).vec,9)), -- line 8
slv(to_unsigned(INTMAP( 7).vec,9)), -- line 7
slv(to_unsigned(INTMAP( 6).vec,9)), -- line 6
slv(to_unsigned(INTMAP( 5).vec,9)), -- line 5
slv(to_unsigned(INTMAP( 4).vec,9)), -- line 4
slv(to_unsigned(INTMAP( 3).vec,9)), -- line 3
slv(to_unsigned(INTMAP( 2).vec,9)), -- line 2
slv(to_unsigned(INTMAP( 1).vec,9)), -- line 1
slv(to_unsigned( 0,9)) -- line 0 (always 0 !!)
);
-- attribute PRIORITY_EXTRACT : string;
-- attribute PRIORITY_EXTRACT of EI_LINE : signal is "force";
begin
EI_LINE <= "1111" when EI_REQ(15)='1' else
"1110" when EI_REQ(14)='1' else
"1101" when EI_REQ(13)='1' else
"1100" when EI_REQ(12)='1' else
"1011" when EI_REQ(11)='1' else
"1010" when EI_REQ(10)='1' else
"1001" when EI_REQ( 9)='1' else
"1000" when EI_REQ( 8)='1' else
"0111" when EI_REQ( 7)='1' else
"0110" when EI_REQ( 6)='1' else
"0101" when EI_REQ( 5)='1' else
"0100" when EI_REQ( 4)='1' else
"0011" when EI_REQ( 3)='1' else
"0010" when EI_REQ( 2)='1' else
"0001" when EI_REQ( 1)='1' else
"0000";
proc_line: process (CLK)
begin
if rising_edge(CLK) then
R_LINE <= EI_LINE;
end if;
end process proc_line;
-- Note: EI_ACKM comes one cycle after vector is latched ! Therefore
-- - use EI_LINE to select vector to send to EI_PRI and EI_VECT
-- - use R_LINE to select EI_ACM line for acknowledge
proc_intmap : process (EI_LINE, EI_ACKM, R_LINE)
variable ilinecur : integer := 0;
variable ilinelst : integer := 0;
variable iei_ack : slv16 := (others=>'0');
begin
ilinecur := to_integer(unsigned(EI_LINE));
ilinelst := to_integer(unsigned(R_LINE));
-- send info of currently highest priority request
EI_PRI <= conf_intp(ilinecur);
EI_VECT <= conf_intv(ilinecur)(8 downto 2);
-- route acknowledge back to winner line of last cycle
iei_ack := (others=>'0');
if EI_ACKM = '1' then
iei_ack(ilinelst) := '1';
end if;
EI_ACK <= iei_ack(EI_ACK'range);
end process proc_intmap;
end syn;
|
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic := '0'; -- Comment
sig2 : std_logic := '1'; -- Comment
sig3 : std_logic := 'Z' -- Comment
);
end entity fifo;
-- Failures below
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic := '0'; -- Comment
sig2 : std_logic := '1'; -- Comment
sig3 : std_logic := 'Z' -- Comment
);
end entity fifo;
|
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic := '0'; -- Comment
sig2 : std_logic := '1'; -- Comment
sig3 : std_logic := 'Z' -- Comment
);
end entity fifo;
-- Failures below
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic := '0'; -- Comment
sig2 : std_logic := '1'; -- Comment
sig3 : std_logic := 'Z' -- Comment
);
end entity fifo;
|
architecture RTL of FIFO is
begin
a <= b;
a <= when c = '0' else '1';
block_label: block is
begin
a <= b;
a <= c;
end block;
a <= b;
a <= when c = '0' else '1';
end architecture RTL;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_sp605
-- File: ahb2mig_sp605.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus, while
-- a second read-only port can be enabled for a VGA frame buffer.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_sp605 is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
vgamst : integer := 0;
vgaburst : integer := 0
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
ahbmi : out ahb_mst_in_type;
ahbmo : in ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
clk_mem_p : in std_logic;
clk_mem_n : in std_logic;
clk_125 : out std_logic;
clk_50 : out std_logic
);
end ;
architecture rtl of ahb2mig_sp605 is
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
type reg2_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
end record;
type p2_if_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_bl : std_logic_vector(5 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
rd_en : std_logic;
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
end record;
signal r, rin : reg_type;
signal r2, r2in : reg2_type;
signal i : mcb_type;
signal p2 : p2_if_type;
begin
comb: process( rst_n_syn, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r <= rin;
end if;
end process;
port2 : if vgamst /= 0 generate
comb2: process( rst_n_syn, r2, ahbmo, p2 )
variable v2 : reg2_type;
variable cmd_en : std_logic;
variable rd_en : std_logic;
begin
v2 := r2; cmd_en := '0'; rd_en := '0';
case r2.bstate is
when idle =>
if ahbmo.htrans(1) = '1' then
v2.bstate := start;
v2.hready := '0';
v2.haddr := ahbmo.haddr;
else v2.hready := '1'; end if;
v2.cmd_bl := (others => '0');
when start =>
if p2.cmd_full = '0' then
cmd_en := '1';
v2.cmd_bl := conv_std_logic_vector(vgaburst-1, 6);
v2.bstate := read1;
end if;
when read1 =>
v2.hready := '0';
if (r2.rd_cnt = "000000") then -- flush data from previous line
if (p2.rd_empty = '0') or ((r2.hready = '1') and (ahbmo.htrans /= "11")) then
v2.hrdata(31 downto 0) := p2.rd_data(15 downto 0) & p2.rd_data(31 downto 16);
v2.hready := '1';
if (p2.rd_empty = '0') then v2.cmd_bl := r2.cmd_bl - 1; rd_en := '1'; end if;
if (r2.cmd_bl = "000000") or (ahbmo.htrans /= "11") then
if (ahbmo.htrans = "10") and (r2.hready = '1') then
v2.bstate := start; v2.hready := '0';
v2.cmd_bl := (others => '0');
else
v2.bstate := idle;
end if;
if (p2.rd_empty = '1') then v2.rd_cnt := r2.cmd_bl + 1;
else v2.rd_cnt := r2.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
if (r2.rd_cnt /= "000000") and (p2.rd_empty = '0') then
rd_en := '1'; v2.rd_cnt := r2.rd_cnt - 1;
end if;
v2.haddr(1 downto 0) := "00";
if rst_n_syn = '0' then
v2.rd_cnt := "000000"; v2.bstate := idle; v2.hready := '1';
end if;
r2in <= v2;
p2.rd_en <= rd_en;
p2.cmd_bl <= v2.cmd_bl;
p2.cmd_en <= cmd_en;
p2.cmd_instr <= "001";
end process;
ahbmi.hrdata <= r2.hrdata;
ahbmi.hresp <= "00";
ahbmi.hgrant <= (others => '1');
ahbmi.hready <= r2.hready;
ahbmi.hirq <= (others => '0');
ahbmi.testen <= '0';
ahbmi.testrst <= '0';
ahbmi.scanen <= '0';
ahbmi.testoen <= '0';
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r2 <= r2in;
end if;
end process;
end generate;
noport2 : if vgamst = 0 generate
p2.cmd_en <= '0';
p2.rd_en <= '0';
end generate;
MCB_inst : entity work.mig_38 generic map(
C3_P0_MASK_SIZE => 4,
C3_P0_DATA_PORT_SIZE => 32,
C3_P1_MASK_SIZE => 4,
C3_P1_DATA_PORT_SIZE => 32,
-- C3_MEMCLK_PERIOD => 5000,
C3_RST_ACT_LOW => 1,
C3_INPUT_CLK_TYPE => "DIFFERENTIAL",
C3_CALIB_SOFT_IP => "TRUE",
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN",
C3_NUM_DQ_PINS => 16,
C3_MEM_ADDR_WIDTH => 13,
C3_MEM_BANKADDR_WIDTH => 3
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
c3_sys_clk_p => clk_mem_p,
c3_sys_clk_n => clk_mem_n,
c3_sys_rst_i => rst_n_async,
c3_calib_done => calib_done,
c3_clk0 => open,
c3_rst0 => open,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_p0_cmd_clk => clk_amba,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error,
c3_p2_cmd_clk => clk_amba,
c3_p2_cmd_en => p2.cmd_en,
c3_p2_cmd_instr => p2.cmd_instr,
c3_p2_cmd_bl => p2.cmd_bl,
c3_p2_cmd_byte_addr => r2.haddr(29 downto 0),
c3_p2_cmd_empty => p2.cmd_empty,
c3_p2_cmd_full => p2.cmd_full,
c3_p2_rd_clk => clk_amba,
c3_p2_rd_en => p2.rd_en,
c3_p2_rd_data => p2.rd_data,
c3_p2_rd_full => p2.rd_full,
c3_p2_rd_empty => p2.rd_empty,
c3_p2_rd_count => p2.rd_count,
c3_p2_rd_overflow => p2.rd_overflow,
c3_p2_rd_error => p2.rd_error,
clk_125 => clk_125,
clk_50 => clk_50
);
end;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_eab_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eab_e-e.vhd,v 1.1 2004/04/06 10:49:57 wig Exp $
-- $Date: 2004/04/06 10:49:57 $
-- $Log: inst_eab_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:49:57 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_eab_e
--
entity inst_eab_e is
-- Generics:
-- No Generated Generics for Entity inst_eab_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_eab_e
nreset : in std_ulogic;
nreset_s : in std_ulogic;
v_select : in std_ulogic_vector(5 downto 0)
-- End of Generated Port for Entity inst_eab_e
);
end inst_eab_e;
--
-- End of Generated Entity inst_eab_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Solving_Key_Equation_1_v2
-- Module Name: Controller_Solving_Key_Equation_1_v2
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 2nd step in Goppa Code Decoding.
--
-- This is a state machine circuit that controls solving_key_equation_1_v2.
-- This state machine have 3 phases: first phase variable initialization,
-- second computation of polynomial sigma, third step writing the polynomial sigma
-- on a specific memory position.
--
-- This is the second circuit version. It is a non pipeline version of the algorithm,
-- each coefficient takes more than 1 cycle to be computed.
-- A more optimized pipelined version was made called solving_key_equation_2
--
-- Dependencies:
--
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_solving_key_equation_1_v2 is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
FB_equal_zero : in STD_LOGIC;
i_equal_zero : in STD_LOGIC;
i_minus_j_less_than_zero : in STD_LOGIC;
degree_G_less_equal_final_degree : in STD_LOGIC;
degree_F_less_than_degree_G : in STD_LOGIC;
degree_B_equal_degree_C_plus_j : in STD_LOGIC;
degree_B_less_than_degree_C_plus_j : in STD_LOGIC;
reg_looking_degree_q : in STD_LOGIC_VECTOR(0 downto 0);
key_equation_found : out STD_LOGIC;
signal_inv : out STD_LOGIC;
sel_new_value_inv : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
sel_base_mul : out STD_LOGIC;
reg_h_ce : out STD_LOGIC;
ctr_i_ce : out STD_LOGIC;
ctr_i_load : out STD_LOGIC;
ctr_i_rst : out STD_LOGIC;
sel_ctr_i_rst_value : out STD_LOGIC;
sel_ctr_i_d : out STD_LOGIC;
reg_j_ce : out STD_LOGIC;
reg_j_rst : out STD_LOGIC;
reg_FB_ce : out STD_LOGIC;
reg_FB_rst : out STD_LOGIC;
sel_reg_FB : out STD_LOGIC;
sel_load_new_value_FB : out STD_LOGIC;
reg_GC_ce : out STD_LOGIC;
reg_GC_rst : out STD_LOGIC;
sel_reg_GC : out STD_LOGIC;
ctr_degree_F_ce : out STD_LOGIC;
ctr_degree_F_load : out STD_LOGIC;
ctr_degree_F_rst : out STD_LOGIC;
reg_degree_G_ce : out STD_LOGIC;
reg_degree_G_rst : out STD_LOGIC;
ctr_degree_B_ce : out STD_LOGIC;
ctr_degree_B_load : out STD_LOGIC;
ctr_degree_B_rst : out STD_LOGIC;
sel_ctr_degree_B : out STD_LOGIC;
reg_degree_C_ce : out STD_LOGIC;
reg_degree_C_rst : out STD_LOGIC;
reg_looking_degree_d : out STD_LOGIC_VECTOR(0 downto 0);
reg_looking_degree_ce : out STD_LOGIC;
reg_swap_ce : out STD_LOGIC;
reg_swap_rst : out STD_LOGIC;
sel_address_FB : out STD_LOGIC;
sel_address_GC : out STD_LOGIC;
ctr_address_FB_ce : out STD_LOGIC;
ctr_address_FB_load : out STD_LOGIC;
ctr_address_GC_ce : out STD_LOGIC;
ctr_address_GC_load : out STD_LOGIC;
BC_calculation : out STD_LOGIC;
enable_external_swap : out STD_LOGIC
);
end controller_solving_key_equation_1_v2;
architecture Behavioral of controller_solving_key_equation_1_v2 is
type State is (reset, load_counter, store_G2t, load_first_inv, send_first_inv, prepare_load_F_store_G, load_F_store_G, wait_F, prepare_store_B_C, store_B_C, last_store_B_C, swap_F_G_B_C, prepare_load_j, load_j, load_first_G_first_F, load_h, prepare_load_F_G, load_F_G, mult_add_F_G, store_F, finalize_i, prepare_i, prepare_load_B_C, load_B_C, mult_add_B_C, store_B, prepare_final_swap, preparel_swap_address, prepare_load_sigma, load_sigma, store_sigma, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process(actual_state, FB_equal_zero, i_equal_zero, i_minus_j_less_than_zero, degree_G_less_equal_final_degree, degree_F_less_than_degree_G, degree_B_equal_degree_C_plus_j, degree_B_less_than_degree_C_plus_j, reg_looking_degree_q)
begin
case (actual_state) is
when reset =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '1';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '1';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when load_counter =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '1';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '1';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
sel_reg_GC <= '1';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
sel_address_FB <= '0';
sel_address_GC <= '1';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '1';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '1';
BC_calculation <= '0';
enable_external_swap <= '1';
when store_G2t =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '1';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "1";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '1';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '1';
BC_calculation <= '0';
enable_external_swap <= '1';
when load_first_inv =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when send_first_inv =>
key_equation_found <= '0';
signal_inv <= '1';
sel_new_value_inv <= '1';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when prepare_load_F_store_G =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when load_F_store_G =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when wait_F =>
if(i_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
elsif(reg_looking_degree_q(0) = '1' and FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
end if;
when prepare_store_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '1';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '1';
BC_calculation <= '1';
enable_external_swap <= '1';
when store_B_C =>
if(i_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '1';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
end if;
when last_store_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '1';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
BC_calculation <= '1';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
enable_external_swap <= '1';
when swap_F_G_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '1';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '1';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '1';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '1';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '1';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when prepare_load_j =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_rst <= '0';
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '1';
sel_address_GC <= '1';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '1';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '1';
BC_calculation <= '0';
enable_external_swap <= '1';
when load_j =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '1';
reg_j_ce <= '1';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '1';
sel_address_GC <= '1';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when load_first_G_first_F =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '1';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when load_h =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '1';
reg_h_ce <= '1';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "1";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when prepare_load_F_G =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when load_F_G =>
if(i_minus_j_less_than_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
end if;
when mult_add_F_G =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when store_F =>
if(i_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_load_new_value_FB <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
elsif(reg_looking_degree_q(0) = '1') then
if(FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
elsif(degree_F_less_than_degree_G = '1') then
key_equation_found <= '0';
signal_inv <= '1';
sel_new_value_inv <= '1';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
end if;
else
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
end if;
when prepare_i =>
if(degree_B_equal_degree_C_plus_j = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "1";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
elsif(degree_B_less_than_degree_C_plus_j = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '1';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '1';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
end if;
when finalize_i =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '1';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '1';
BC_calculation <= '1';
enable_external_swap <= '1';
when prepare_load_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
when load_B_C =>
if(i_minus_j_less_than_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
end if;
when mult_add_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
when store_B =>
if(i_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
elsif(reg_looking_degree_q(0) = '1' and FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
end if;
when prepare_final_swap =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
when preparel_swap_address =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '1';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '1';
BC_calculation <= '1';
enable_external_swap <= '1';
when prepare_load_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
when load_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '1';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '1';
BC_calculation <= '0';
enable_external_swap <= '1';
when store_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '1';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '1';
BC_calculation <= '0';
enable_external_swap <= '0';
when final =>
key_equation_found <= '1';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '0';
when others =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '0';
end case;
end process;
New_State : process(actual_state, FB_equal_zero, i_equal_zero, i_minus_j_less_than_zero, degree_G_less_equal_final_degree, degree_F_less_than_degree_G, degree_B_equal_degree_C_plus_j, degree_B_less_than_degree_C_plus_j, reg_looking_degree_q)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= store_G2t;
when store_G2t =>
next_state <= load_first_inv;
when load_first_inv =>
next_state <= send_first_inv;
when send_first_inv =>
next_state <= prepare_load_F_store_G;
when prepare_load_F_store_G =>
next_state <= load_F_store_G;
when load_F_store_G =>
next_state <= wait_F;
when wait_F =>
if(i_equal_zero = '1') then
next_state <= prepare_store_B_C;
else
next_state <= prepare_load_F_store_G;
end if;
when prepare_store_B_C =>
next_state <= store_B_C;
when store_B_C =>
if(i_equal_zero = '1') then
next_state <= last_store_B_C;
else
next_state <= store_B_C;
end if;
when last_store_B_C =>
next_state <= swap_F_G_B_C;
when swap_F_G_B_C =>
next_state <= prepare_load_j;
when prepare_load_j =>
next_state <= load_j;
when load_j =>
next_state <= load_first_G_first_F;
when load_first_G_first_F =>
next_state <= load_h;
when load_h =>
next_state <= prepare_load_F_G;
when prepare_load_F_G =>
next_state <= load_F_G;
when load_F_G =>
next_state <= mult_add_F_G;
when mult_add_F_G =>
next_state <= store_F;
when store_F =>
if(i_equal_zero = '1') then
next_state <= prepare_i;
else
next_state <= prepare_load_F_G;
end if;
when prepare_i =>
next_state <= finalize_i;
when finalize_i =>
next_state <= prepare_load_B_C;
when prepare_load_B_C =>
next_state <= load_B_C;
when load_B_C =>
next_state <= mult_add_B_C;
when mult_add_B_C =>
next_state <= store_B;
when store_B =>
if(i_equal_zero = '1') then
if(degree_G_less_equal_final_degree = '1') then
next_state <= prepare_final_swap;
elsif(degree_F_less_than_degree_G = '1') then
next_state <= swap_F_G_B_C;
else
next_state <= prepare_load_j;
end if;
else
next_state <= prepare_load_B_C;
end if;
when prepare_final_swap =>
next_state <= preparel_swap_address;
when preparel_swap_address =>
next_state <= prepare_load_sigma;
when prepare_load_sigma =>
next_state <= load_sigma;
when load_sigma =>
next_state <= store_sigma;
when store_sigma =>
if(i_equal_zero = '1') then
next_state <= final;
else
next_state <= preparel_swap_address;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
-- Quartus II VHDL Template
-- Binary Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity thirda is
port(
clk, enable : in std_logic;
reset: buffer std_logic;
q : out integer range 0 to 64
);
end entity;
architecture rtl of thirda is
component binary_counter_mod_16 is
port(
clk, reset, enable : in std_logic;
q : out integer range 0 to 15;
carry: out std_logic
);
end component;
signal carry : std_logic;
signal a, b: integer range 0 to 16;
begin
coun1 :binary_counter_mod_16 port map(
clk, reset, enable, a, carry
);
coun2 : binary_counter_mod_16 port map(
carry, reset, enable, b
);
q <= b * 16 + a;
process (a, b)
begin
if b = 3 and a = 7 then
reset <= '1';
else reset <= '0';
end if;
end process;
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.txt_util.all;
entity common_tb is
generic (
clock_period : time
);
port (
clk : in STD_LOGIC;
done : out boolean;
success : out boolean
);
end common_tb;
architecture Behavioral of common_tb is
signal data_safe_8_bit_rst : STD_LOGIC := '1';
signal data_safe_8_bit_read : STD_LOGIC := '0';
signal data_safe_8_bit_data_in : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
signal data_safe_8_bit_data_out : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal b_to_s_p_reset : STD_LOGIC := '1';
signal b_to_s_p_pulse_out : STD_LOGIC;
signal b_to_s_p_pulse_in : STD_LOGIC := '0';
signal debouncer_pulse_in : STD_LOGIC;
signal debouncer_pulse_out : STD_LOGIC;
signal simple_multishot_timer_rst : STD_LOGIC := '1';
signal simple_multishot_timer_done : STD_LOGIC;
signal simple_multishot_test_done : boolean := false;
signal data_safe_test_done : boolean := false;
signal b_to_s_p_test_done : boolean := false;
signal debouncer_test_done : boolean := false;
signal simple_multishot_test_success : boolean := true;
signal data_safe_test_success : boolean := true;
signal b_to_s_p_test_success : boolean := true;
signal debouncer_test_success : boolean := true;
constant simple_multishot_maxval : natural := 10;
begin
done <= simple_multishot_test_done and data_safe_test_done and b_to_s_p_test_done and debouncer_test_done;
success <= simple_multishot_test_success and data_safe_test_success and b_to_s_p_test_success and debouncer_test_success;
simple_multishot_timer_500 : entity work.simple_multishot_timer
generic map (
match_val => simple_multishot_maxval
)
port map (
clk => clk,
rst => simple_multishot_timer_rst,
done => simple_multishot_timer_done
);
debouncer : entity work.static_debouncer
generic map (
debounce_ticks => 10
)
port map (
clk => clk,
pulse_in => debouncer_pulse_in,
pulse_out => debouncer_pulse_out
);
button_to_single_pulse_500 : entity work.button_to_single_pulse
generic map (
debounce_ticks => 500
)
port map (
clk => clk,
rst => b_to_s_p_reset,
pulse_in => b_to_s_p_pulse_in,
pulse_out => b_to_s_p_pulse_out
);
data_safe : entity work.data_safe_8_bit
port map (
clk => clk,
rst => data_safe_8_bit_rst,
read => data_safe_8_bit_read,
data_in => data_safe_8_bit_data_in,
data_out => data_safe_8_bit_data_out
);
debounce_tester : process
begin
debouncer_pulse_in <= '0';
-- Wait half a clock to get out of sync
wait for clock_period / 2;
-- Let the debouncer relax for a while
for I in 0 to 10 loop
wait for clock_period;
end loop;
if debouncer_pulse_out /= '0' then
debouncer_test_success <= false;
report "debouncer failure, expected 0 got 1" severity error;
end if;
-- Detect normal edge change behaviour
debouncer_pulse_in <= '1';
-- We give it one cycle to detect the change and then 10 to respond to it
for I in 0 to 10 loop
wait for clock_period;
end loop;
if debouncer_pulse_out /= '1' then
debouncer_test_success <= false;
report "debouncer failure, expected 1 got 0" severity error;
end if;
-- Weird, halfway change
debouncer_pulse_in <= '0';
for I in 0 to 5 loop
wait for clock_period;
end loop;
debouncer_pulse_in <= '1';
for I in 0 to 10 loop
wait for clock_period;
end loop;
if debouncer_pulse_out /= '1' then
debouncer_test_success <= false;
report "debouncer failure, expected 1 got 0" severity error;
end if;
report "debouncer test done" severity note;
debouncer_test_done <= true;
wait;
end process;
simple_multishot_tester : process
variable suc : boolean := true;
begin
simple_multishot_timer_rst <= '0';
wait until rising_edge(clk);
for J in 0 to 5 loop
for I in 0 to (simple_multishot_maxval-1) loop
wait until rising_edge(clk);
end loop;
wait for clock_period/2;
if simple_multishot_timer_done /= '1' then
report "Simple multishot timer was expected to be one, but was zero" severity error;
suc := false;
end if;
end loop;
-- Check the workings of the reset
for I in 0 to (simple_multishot_maxval/2) loop
wait until rising_edge(clk);
end loop;
simple_multishot_timer_rst <= '1';
wait for clock_period/2;
simple_multishot_timer_rst <= '0';
wait until rising_edge(clk);
for J in 0 to 5 loop
for I in 0 to (simple_multishot_maxval-1) loop
wait until rising_edge(clk);
end loop;
wait for clock_period/2;
if simple_multishot_timer_done /= '1' then
report "Simple multishot timer was expected to be one, but was zero (after reset test)" severity error;
suc := false;
end if;
end loop;
report "Simple multishot timer finished" severity note;
simple_multishot_test_done <= true;
simple_multishot_test_success <= suc;
wait;
end process;
button_to_single_pulse_tester : process
variable suc : boolean := true;
begin
b_to_s_p_reset <= '0';
b_to_s_p_pulse_in <= '1';
wait for 10065 ns;
if b_to_s_p_pulse_out /= '1' then
report "Button to single pulse pulse_out value is zero where it should be one" severity error;
suc := false;
end if;
report "Button to single pulse test done" severity note;
b_to_s_p_test_done <= true;
b_to_s_p_test_success <= suc;
wait;
end process;
data_safe_tester : process
variable test_data : STD_LOGIC_VECTOR(7 DOWNTO 0 ) := "01100010";
variable suc : boolean := true;
begin
data_safe_8_bit_data_in <= test_data;
data_safe_8_bit_rst <= '0';
for I in 0 to 5 loop
wait until rising_edge(clk);
end loop;
if data_safe_8_bit_data_out /= "00000000" then
report "data_safe_8_bit_data_out has changed to early" severity error;
suc := false;
end if;
data_safe_8_bit_read <= '1';
for I in 0 to 5 loop
wait until rising_edge(clk);
end loop;
if data_safe_8_bit_data_out /= test_data then
report "data_safe_8_bit_data_out has not changed while this was expected" severity error;
suc := false;
end if;
data_safe_8_bit_read <= '0';
data_safe_8_bit_data_in <= "01010101";
for I in 0 to 5 loop
wait until rising_edge(clk);
end loop;
if data_safe_8_bit_data_out /= test_data then
report "data_safe_8_bit_data_out has changed unexpected" severity error;
suc := false;
end if;
report "data_safe_8_bit tests done" severity note;
data_safe_test_done <= true;
data_safe_test_success <= suc;
wait;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity decode_7seg is
port(
clk : in std_logic; -- Clock
reset : in std_logic; -- Reset
data_in : in std_logic_vector(15 downto 0);-- Number to be displayed 4 bits for each segements
segments : out std_logic_vector(6 downto 0); -- Seven segments
anode_selected : out std_logic_vector(3 downto 0) -- Selecting one of the four seven segments
);
end decode_7seg;
architecture rtl of decode_7seg is
constant c_1_ms : integer := 50000;
signal r_cnt : unsigned(31 downto 0) := (others => '0');
signal r_segments : std_logic_vector(6 downto 0) := (others => '1');
signal r_data_4b : std_logic_vector(3 downto 0) := (others => '0');
signal r_anode_selected : std_logic_vector(3 downto 0) := "1110";
begin
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
r_segments <= "1111111";
r_cnt <= (others => '0');
r_anode_selected <= "1110";
else
-- Mux data_in
for i in 0 to r_anode_selected'length-1 loop
if r_anode_selected(i) = '0' then
r_data_4b <= data_in(4*(i+1)-1 downto 4*i);
end if;
end loop;
-- Display
case r_data_4b is
when "0000" => -- Display 0
r_segments <= "1000000";
when "0001" => -- Display 1
r_segments <= "1111001";
when "0010" => -- Display 2
r_segments <= "0100100";
when "0011" => -- Display 3
r_segments <= "0110000";
when "0100" => -- Display 4
r_segments <= "0011001";
when "0101" => -- Display 5
r_segments <= "0010010";
when "0110" => -- Display 6
r_segments <= "0000010";
when "0111" => -- Display 7
r_segments <= "1111000";
when "1000" => -- Display 8
r_segments <= "0000000";
when "1001" => -- Display 9
r_segments <= "0010000";
when others =>
r_segments <= "0000000";
end case;
-- Switch anode every 10 ms
if r_cnt = c_1_ms then
r_cnt <= (others => '0');
r_anode_selected <= r_anode_selected(2 downto 0) & r_anode_selected(3);
else
r_cnt <= r_cnt + 1;
end if;
end if;
end if;
end process;
segments <= r_segments;
anode_selected <= r_anode_selected;
end rtl;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_aa
--
-- Generated
-- by: wig
-- on: Mon Aug 9 17:44:47 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../typecast.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_aa-e.vhd,v 1.1 2004/08/09 15:47:10 wig Exp $
-- $Date: 2004/08/09 15:47:10 $
-- $Log: inst_aa-e.vhd,v $
-- Revision 1.1 2004/08/09 15:47:10 wig
-- added typecast/intbus testcase
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.43 2004/08/04 12:49:37 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_aa
--
entity inst_aa is
-- Generics:
-- No Generated Generics for Entity inst_aa
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_aa
port_a_1 : out std_ulogic;
port_a_11 : out std_ulogic_vector(7 downto 0);
port_a_3 : out std_ulogic_vector(7 downto 0);
port_a_5 : out std_ulogic;
port_a_7 : out std_logic_vector(7 downto 0);
port_a_9 : out std_ulogic;
signal_10 : out std_logic;
signal_12 : out std_logic_vector(15 downto 0);
signal_2 : out std_logic;
signal_4 : out std_logic_vector(15 downto 0);
signal_6 : out std_logic;
signal_8 : out std_ulogic_vector(15 downto 0)
-- End of Generated Port for Entity inst_aa
);
end inst_aa;
--
-- End of Generated Entity inst_aa
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: RAM_ram_bank_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY RAM_ram_bank_tb IS
END ENTITY;
ARCHITECTURE RAM_ram_bank_tb_ARCH OF RAM_ram_bank_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
RAM_ram_bank_synth_inst:ENTITY work.RAM_ram_bank_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2630.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02630ent IS
END c13s03b01x00p02n01i02630ent;
ARCHITECTURE c13s03b01x00p02n01i02630arch OF c13s03b01x00p02n01i02630ent IS
BEGIN
TESTING: PROCESS
variable k:k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02630 - Identifier can not contain ':'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02630arch;
|
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