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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc737.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s01b01x01p04n01i00737ent_a is
generic (
constant gc1 : in integer;
constant gc2 : in real;
constant gc3 : in boolean
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x01p04n01i00737ent_a;
architecture c01s01b01x01p04n01i00737arch_a of c01s01b01x01p04n01i00737ent_a is
begin
p0: process
begin
wait for 1 ns;
if (gc1 = 5) AND (gc2 = 0.1234) AND (gc3) then
assert FALSE
report "***PASSED TEST: c01s01b01x01p04n01i00737"
severity NOTE;
else
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n01i00737 - Simple generic association in component instantiation (type conversion done on actual in generic map failed)."
severity ERROR;
end if;
wait;
end process;
end c01s01b01x01p04n01i00737arch_a;
ENTITY c01s01b01x01p04n01i00737ent IS
generic ( constant gen_con : integer := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x01p04n01i00737ent;
ARCHITECTURE c01s01b01x01p04n01i00737arch OF c01s01b01x01p04n01i00737ent IS
constant c1 : integer := 33;
constant c2 : real := 1.23557;
constant c3 : boolean := FALSE;
signal s1 : integer;
signal s2 : integer;
signal s3 : integer;
component comp1
generic (
constant dgc1 : integer;
constant dgc2 : real;
constant dgc3 : boolean
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x01p04n01i00737ent_a(c01s01b01x01p04n01i00737_arch_a)
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
function BoolToInt(bin : boolean) return integer is
begin
if bin then
return 5;
else
return 99;
end if;
end;
function IntegerToReal(iin : integer) return real is
begin
return 0.1234;
end;
function BitToBool(bin : bit) return boolean is
begin
if (bin = '1') then
return TRUE;
else
return FALSE;
end if;
end;
BEGIN
u1 : comp1
generic map (BoolToInt(TRUE), IntegerToReal(1234), BitToBool('1'))
port map (ee1,ee2);
END c01s01b01x01p04n01i00737arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELAY.VHD ***
--*** ***
--*** Function: Delay an arbitrary width an ***
--*** arbitrary number of stages ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delay IS
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_delay;
ARCHITECTURE rtl OF hcc_delay IS
type delmemfftype IS ARRAY (delay DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delmemff : delmemfftype;
signal delinff, deloutff : STD_LOGIC_VECTOR (width DOWNTO 1);
component hcc_delmem
GENERIC (
width : positive := 64;
delay : positive := 18
);
PORT (
sysclk : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gda: IF (delay = 1) GENERATE
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delinff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delinff <= aa;
END IF;
END IF;
END PROCESS;
cc <= delinff;
END GENERATE;
gdb: IF ( ((delay > 1) AND (delay < 5) AND synthesize = 1) OR ((delay > 1) AND synthesize = 0)) GENERATE
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR j IN 1 TO delay LOOP
FOR k IN 1 TO width LOOP
delmemff(j)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delmemff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO delay LOOP
delmemff(k)(width DOWNTO 1) <= delmemff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delmemff(delay)(width DOWNTO 1);
END GENERATE;
gdc: IF (delay > 4 AND synthesize = 1) GENERATE
core: hcc_delmem
GENERIC MAP (width=>width,delay=>delay)
PORT MAP (sysclk=>sysclk,enable=>enable,
aa=>aa,cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELAY.VHD ***
--*** ***
--*** Function: Delay an arbitrary width an ***
--*** arbitrary number of stages ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delay IS
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_delay;
ARCHITECTURE rtl OF hcc_delay IS
type delmemfftype IS ARRAY (delay DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delmemff : delmemfftype;
signal delinff, deloutff : STD_LOGIC_VECTOR (width DOWNTO 1);
component hcc_delmem
GENERIC (
width : positive := 64;
delay : positive := 18
);
PORT (
sysclk : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gda: IF (delay = 1) GENERATE
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delinff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delinff <= aa;
END IF;
END IF;
END PROCESS;
cc <= delinff;
END GENERATE;
gdb: IF ( ((delay > 1) AND (delay < 5) AND synthesize = 1) OR ((delay > 1) AND synthesize = 0)) GENERATE
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR j IN 1 TO delay LOOP
FOR k IN 1 TO width LOOP
delmemff(j)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delmemff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO delay LOOP
delmemff(k)(width DOWNTO 1) <= delmemff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delmemff(delay)(width DOWNTO 1);
END GENERATE;
gdc: IF (delay > 4 AND synthesize = 1) GENERATE
core: hcc_delmem
GENERIC MAP (width=>width,delay=>delay)
PORT MAP (sysclk=>sysclk,enable=>enable,
aa=>aa,cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELAY.VHD ***
--*** ***
--*** Function: Delay an arbitrary width an ***
--*** arbitrary number of stages ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delay IS
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_delay;
ARCHITECTURE rtl OF hcc_delay IS
type delmemfftype IS ARRAY (delay DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delmemff : delmemfftype;
signal delinff, deloutff : STD_LOGIC_VECTOR (width DOWNTO 1);
component hcc_delmem
GENERIC (
width : positive := 64;
delay : positive := 18
);
PORT (
sysclk : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gda: IF (delay = 1) GENERATE
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delinff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delinff <= aa;
END IF;
END IF;
END PROCESS;
cc <= delinff;
END GENERATE;
gdb: IF ( ((delay > 1) AND (delay < 5) AND synthesize = 1) OR ((delay > 1) AND synthesize = 0)) GENERATE
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR j IN 1 TO delay LOOP
FOR k IN 1 TO width LOOP
delmemff(j)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delmemff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO delay LOOP
delmemff(k)(width DOWNTO 1) <= delmemff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delmemff(delay)(width DOWNTO 1);
END GENERATE;
gdc: IF (delay > 4 AND synthesize = 1) GENERATE
core: hcc_delmem
GENERIC MAP (width=>width,delay=>delay)
PORT MAP (sysclk=>sysclk,enable=>enable,
aa=>aa,cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELAY.VHD ***
--*** ***
--*** Function: Delay an arbitrary width an ***
--*** arbitrary number of stages ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delay IS
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_delay;
ARCHITECTURE rtl OF hcc_delay IS
type delmemfftype IS ARRAY (delay DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delmemff : delmemfftype;
signal delinff, deloutff : STD_LOGIC_VECTOR (width DOWNTO 1);
component hcc_delmem
GENERIC (
width : positive := 64;
delay : positive := 18
);
PORT (
sysclk : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gda: IF (delay = 1) GENERATE
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delinff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delinff <= aa;
END IF;
END IF;
END PROCESS;
cc <= delinff;
END GENERATE;
gdb: IF ( ((delay > 1) AND (delay < 5) AND synthesize = 1) OR ((delay > 1) AND synthesize = 0)) GENERATE
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR j IN 1 TO delay LOOP
FOR k IN 1 TO width LOOP
delmemff(j)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delmemff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO delay LOOP
delmemff(k)(width DOWNTO 1) <= delmemff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delmemff(delay)(width DOWNTO 1);
END GENERATE;
gdc: IF (delay > 4 AND synthesize = 1) GENERATE
core: hcc_delmem
GENERIC MAP (width=>width,delay=>delay)
PORT MAP (sysclk=>sysclk,enable=>enable,
aa=>aa,cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELAY.VHD ***
--*** ***
--*** Function: Delay an arbitrary width an ***
--*** arbitrary number of stages ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delay IS
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_delay;
ARCHITECTURE rtl OF hcc_delay IS
type delmemfftype IS ARRAY (delay DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delmemff : delmemfftype;
signal delinff, deloutff : STD_LOGIC_VECTOR (width DOWNTO 1);
component hcc_delmem
GENERIC (
width : positive := 64;
delay : positive := 18
);
PORT (
sysclk : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gda: IF (delay = 1) GENERATE
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delinff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delinff <= aa;
END IF;
END IF;
END PROCESS;
cc <= delinff;
END GENERATE;
gdb: IF ( ((delay > 1) AND (delay < 5) AND synthesize = 1) OR ((delay > 1) AND synthesize = 0)) GENERATE
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR j IN 1 TO delay LOOP
FOR k IN 1 TO width LOOP
delmemff(j)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delmemff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO delay LOOP
delmemff(k)(width DOWNTO 1) <= delmemff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delmemff(delay)(width DOWNTO 1);
END GENERATE;
gdc: IF (delay > 4 AND synthesize = 1) GENERATE
core: hcc_delmem
GENERIC MAP (width=>width,delay=>delay)
PORT MAP (sysclk=>sysclk,enable=>enable,
aa=>aa,cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELAY.VHD ***
--*** ***
--*** Function: Delay an arbitrary width an ***
--*** arbitrary number of stages ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delay IS
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_delay;
ARCHITECTURE rtl OF hcc_delay IS
type delmemfftype IS ARRAY (delay DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delmemff : delmemfftype;
signal delinff, deloutff : STD_LOGIC_VECTOR (width DOWNTO 1);
component hcc_delmem
GENERIC (
width : positive := 64;
delay : positive := 18
);
PORT (
sysclk : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gda: IF (delay = 1) GENERATE
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delinff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delinff <= aa;
END IF;
END IF;
END PROCESS;
cc <= delinff;
END GENERATE;
gdb: IF ( ((delay > 1) AND (delay < 5) AND synthesize = 1) OR ((delay > 1) AND synthesize = 0)) GENERATE
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR j IN 1 TO delay LOOP
FOR k IN 1 TO width LOOP
delmemff(j)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delmemff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO delay LOOP
delmemff(k)(width DOWNTO 1) <= delmemff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delmemff(delay)(width DOWNTO 1);
END GENERATE;
gdc: IF (delay > 4 AND synthesize = 1) GENERATE
core: hcc_delmem
GENERIC MAP (width=>width,delay=>delay)
PORT MAP (sysclk=>sysclk,enable=>enable,
aa=>aa,cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELAY.VHD ***
--*** ***
--*** Function: Delay an arbitrary width an ***
--*** arbitrary number of stages ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delay IS
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_delay;
ARCHITECTURE rtl OF hcc_delay IS
type delmemfftype IS ARRAY (delay DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delmemff : delmemfftype;
signal delinff, deloutff : STD_LOGIC_VECTOR (width DOWNTO 1);
component hcc_delmem
GENERIC (
width : positive := 64;
delay : positive := 18
);
PORT (
sysclk : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gda: IF (delay = 1) GENERATE
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delinff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delinff <= aa;
END IF;
END IF;
END PROCESS;
cc <= delinff;
END GENERATE;
gdb: IF ( ((delay > 1) AND (delay < 5) AND synthesize = 1) OR ((delay > 1) AND synthesize = 0)) GENERATE
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR j IN 1 TO delay LOOP
FOR k IN 1 TO width LOOP
delmemff(j)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delmemff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO delay LOOP
delmemff(k)(width DOWNTO 1) <= delmemff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delmemff(delay)(width DOWNTO 1);
END GENERATE;
gdc: IF (delay > 4 AND synthesize = 1) GENERATE
core: hcc_delmem
GENERIC MAP (width=>width,delay=>delay)
PORT MAP (sysclk=>sysclk,enable=>enable,
aa=>aa,cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELAY.VHD ***
--*** ***
--*** Function: Delay an arbitrary width an ***
--*** arbitrary number of stages ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delay IS
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_delay;
ARCHITECTURE rtl OF hcc_delay IS
type delmemfftype IS ARRAY (delay DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delmemff : delmemfftype;
signal delinff, deloutff : STD_LOGIC_VECTOR (width DOWNTO 1);
component hcc_delmem
GENERIC (
width : positive := 64;
delay : positive := 18
);
PORT (
sysclk : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gda: IF (delay = 1) GENERATE
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delinff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delinff <= aa;
END IF;
END IF;
END PROCESS;
cc <= delinff;
END GENERATE;
gdb: IF ( ((delay > 1) AND (delay < 5) AND synthesize = 1) OR ((delay > 1) AND synthesize = 0)) GENERATE
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR j IN 1 TO delay LOOP
FOR k IN 1 TO width LOOP
delmemff(j)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delmemff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO delay LOOP
delmemff(k)(width DOWNTO 1) <= delmemff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delmemff(delay)(width DOWNTO 1);
END GENERATE;
gdc: IF (delay > 4 AND synthesize = 1) GENERATE
core: hcc_delmem
GENERIC MAP (width=>width,delay=>delay)
PORT MAP (sysclk=>sysclk,enable=>enable,
aa=>aa,cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELAY.VHD ***
--*** ***
--*** Function: Delay an arbitrary width an ***
--*** arbitrary number of stages ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delay IS
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_delay;
ARCHITECTURE rtl OF hcc_delay IS
type delmemfftype IS ARRAY (delay DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delmemff : delmemfftype;
signal delinff, deloutff : STD_LOGIC_VECTOR (width DOWNTO 1);
component hcc_delmem
GENERIC (
width : positive := 64;
delay : positive := 18
);
PORT (
sysclk : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gda: IF (delay = 1) GENERATE
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delinff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delinff <= aa;
END IF;
END IF;
END PROCESS;
cc <= delinff;
END GENERATE;
gdb: IF ( ((delay > 1) AND (delay < 5) AND synthesize = 1) OR ((delay > 1) AND synthesize = 0)) GENERATE
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR j IN 1 TO delay LOOP
FOR k IN 1 TO width LOOP
delmemff(j)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delmemff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO delay LOOP
delmemff(k)(width DOWNTO 1) <= delmemff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delmemff(delay)(width DOWNTO 1);
END GENERATE;
gdc: IF (delay > 4 AND synthesize = 1) GENERATE
core: hcc_delmem
GENERIC MAP (width=>width,delay=>delay)
PORT MAP (sysclk=>sysclk,enable=>enable,
aa=>aa,cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELAY.VHD ***
--*** ***
--*** Function: Delay an arbitrary width an ***
--*** arbitrary number of stages ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delay IS
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_delay;
ARCHITECTURE rtl OF hcc_delay IS
type delmemfftype IS ARRAY (delay DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delmemff : delmemfftype;
signal delinff, deloutff : STD_LOGIC_VECTOR (width DOWNTO 1);
component hcc_delmem
GENERIC (
width : positive := 64;
delay : positive := 18
);
PORT (
sysclk : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gda: IF (delay = 1) GENERATE
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delinff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delinff <= aa;
END IF;
END IF;
END PROCESS;
cc <= delinff;
END GENERATE;
gdb: IF ( ((delay > 1) AND (delay < 5) AND synthesize = 1) OR ((delay > 1) AND synthesize = 0)) GENERATE
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR j IN 1 TO delay LOOP
FOR k IN 1 TO width LOOP
delmemff(j)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delmemff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO delay LOOP
delmemff(k)(width DOWNTO 1) <= delmemff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delmemff(delay)(width DOWNTO 1);
END GENERATE;
gdc: IF (delay > 4 AND synthesize = 1) GENERATE
core: hcc_delmem
GENERIC MAP (width=>width,delay=>delay)
PORT MAP (sysclk=>sysclk,enable=>enable,
aa=>aa,cc=>cc);
END GENERATE;
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_528 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_528;
architecture augh of sub_528 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_528 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_528;
architecture augh of sub_528 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00238
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (8)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00238)
-- ENT00238_Test_Bench(ARCH00238_Test_Bench)
--
-- REVISION HISTORY:
--
-- 15-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES ;
use STANDARD_TYPES.test_report, STANDARD_TYPES.switch,
STANDARD_TYPES.up, STANDARD_TYPES.down, STANDARD_TYPES.toggle,
STANDARD_TYPES."=" ;
architecture ARCH00238 of GENERIC_STANDARD_TYPES is
signal i_bit_vector_1, i_bit_vector_2 : st_bit_vector
:= c_st_bit_vector_1 ;
signal i_string_1, i_string_2 : st_string
:= c_st_string_1 ;
signal i_t_rec1_1, i_t_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_t_rec2_1, i_t_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_t_rec3_1, i_t_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_t_arr1_1, i_t_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_t_arr2_1, i_t_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_t_arr3_1, i_t_arr3_2 : st_arr3
:= c_st_arr3_1 ;
signal i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1 ;
--
begin
L1:
block
port (
toggle : buffer switch := down;
i_bit_vector_1, i_bit_vector_2 : buffer bit_vector
:= c_st_bit_vector_1
;
i_string_1, i_string_2 : buffer string
:= c_st_string_1
;
i_t_rec1_1, i_t_rec1_2 : buffer t_rec1
:= c_st_rec1_1
;
i_st_rec1_1, i_st_rec1_2 : buffer st_rec1
:= c_st_rec1_1
;
i_t_rec2_1, i_t_rec2_2 : buffer t_rec2
:= c_st_rec2_1
;
i_st_rec2_1, i_st_rec2_2 : buffer st_rec2
:= c_st_rec2_1
;
i_t_rec3_1, i_t_rec3_2 : buffer t_rec3
:= c_st_rec3_1
;
i_st_rec3_1, i_st_rec3_2 : buffer st_rec3
:= c_st_rec3_1
;
i_t_arr1_1, i_t_arr1_2 : buffer t_arr1
:= c_st_arr1_1
;
i_st_arr1_1, i_st_arr1_2 : buffer st_arr1
:= c_st_arr1_1
;
i_t_arr2_1, i_t_arr2_2 : buffer t_arr2
:= c_st_arr2_1
;
i_st_arr2_1, i_st_arr2_2 : buffer st_arr2
:= c_st_arr2_1
;
i_t_arr3_1, i_t_arr3_2 : buffer t_arr3
:= c_st_arr3_1
;
i_st_arr3_1, i_st_arr3_2 : buffer st_arr3
:= c_st_arr3_1
) ;
port map (
toggle ,
i_bit_vector_1, i_bit_vector_2,
i_string_1, i_string_2,
i_t_rec1_1, i_t_rec1_2,
i_st_rec1_1, i_st_rec1_2,
i_t_rec2_1, i_t_rec2_2,
i_st_rec2_1, i_st_rec2_2,
i_t_rec3_1, i_t_rec3_2,
i_st_rec3_1, i_st_rec3_2,
i_t_arr1_1, i_t_arr1_2,
i_st_arr1_1, i_st_arr1_2,
i_t_arr2_1, i_t_arr2_2,
i_st_arr2_1, i_st_arr2_2,
i_t_arr3_1, i_t_arr3_2,
i_st_arr3_1, i_st_arr3_2
) ;
--
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_bit_vector_1 = c_st_bit_vector_1
and i_bit_vector_2 = c_st_bit_vector_1 ;
correct := correct and i_string_1 = c_st_string_1
and i_string_2 = c_st_string_1 ;
correct := correct and i_t_rec1_1 = c_st_rec1_1
and i_t_rec1_2 = c_st_rec1_1 ;
correct := correct and i_st_rec1_1 = c_st_rec1_1
and i_st_rec1_2 = c_st_rec1_1 ;
correct := correct and i_t_rec2_1 = c_st_rec2_1
and i_t_rec2_2 = c_st_rec2_1 ;
correct := correct and i_st_rec2_1 = c_st_rec2_1
and i_st_rec2_2 = c_st_rec2_1 ;
correct := correct and i_t_rec3_1 = c_st_rec3_1
and i_t_rec3_2 = c_st_rec3_1 ;
correct := correct and i_st_rec3_1 = c_st_rec3_1
and i_st_rec3_2 = c_st_rec3_1 ;
correct := correct and i_t_arr1_1 = c_st_arr1_1
and i_t_arr1_2 = c_st_arr1_1 ;
correct := correct and i_st_arr1_1 = c_st_arr1_1
and i_st_arr1_2 = c_st_arr1_1 ;
correct := correct and i_t_arr2_1 = c_st_arr2_1
and i_t_arr2_2 = c_st_arr2_1 ;
correct := correct and i_st_arr2_1 = c_st_arr2_1
and i_st_arr2_2 = c_st_arr2_1 ;
correct := correct and i_t_arr3_1 = c_st_arr3_1
and i_t_arr3_2 = c_st_arr3_1 ;
correct := correct and i_st_arr3_1 = c_st_arr3_1
and i_st_arr3_2 = c_st_arr3_1 ;
--
test_report ( "ENT00238" ,
"Associated composite buffer ports with generic subtypes" ,
correct) ;
--
toggle <= up ;
i_bit_vector_1 <= c_st_bit_vector_2 ;
i_bit_vector_2 <= c_st_bit_vector_2 ;
i_string_1 <= c_st_string_2 ;
i_string_2 <= c_st_string_2 ;
i_t_rec1_1 <= c_st_rec1_2 ;
i_t_rec1_2 <= c_st_rec1_2 ;
i_st_rec1_1 <= c_st_rec1_2 ;
i_st_rec1_2 <= c_st_rec1_2 ;
i_t_rec2_1 <= c_st_rec2_2 ;
i_t_rec2_2 <= c_st_rec2_2 ;
i_st_rec2_1 <= c_st_rec2_2 ;
i_st_rec2_2 <= c_st_rec2_2 ;
i_t_rec3_1 <= c_st_rec3_2 ;
i_t_rec3_2 <= c_st_rec3_2 ;
i_st_rec3_1 <= c_st_rec3_2 ;
i_st_rec3_2 <= c_st_rec3_2 ;
i_t_arr1_1 <= c_st_arr1_2 ;
i_t_arr1_2 <= c_st_arr1_2 ;
i_st_arr1_1 <= c_st_arr1_2 ;
i_st_arr1_2 <= c_st_arr1_2 ;
i_t_arr2_1 <= c_st_arr2_2 ;
i_t_arr2_2 <= c_st_arr2_2 ;
i_st_arr2_1 <= c_st_arr2_2 ;
i_st_arr2_2 <= c_st_arr2_2 ;
i_t_arr3_1 <= c_st_arr3_2 ;
i_t_arr3_2 <= c_st_arr3_2 ;
i_st_arr3_1 <= c_st_arr3_2 ;
i_st_arr3_2 <= c_st_arr3_2 ;
wait ;
end process ;
end block L1 ;
P00238 :
process ( toggle )
variable correct : boolean := true ;
begin
if toggle = up then
correct := correct and i_bit_vector_1 = c_st_bit_vector_2
and i_bit_vector_2 = c_st_bit_vector_2 ;
correct := correct and i_string_1 = c_st_string_2
and i_string_2 = c_st_string_2 ;
correct := correct and i_t_rec1_1 = c_st_rec1_2
and i_t_rec1_2 = c_st_rec1_2 ;
correct := correct and i_st_rec1_1 = c_st_rec1_2
and i_st_rec1_2 = c_st_rec1_2 ;
correct := correct and i_t_rec2_1 = c_st_rec2_2
and i_t_rec2_2 = c_st_rec2_2 ;
correct := correct and i_st_rec2_1 = c_st_rec2_2
and i_st_rec2_2 = c_st_rec2_2 ;
correct := correct and i_t_rec3_1 = c_st_rec3_2
and i_t_rec3_2 = c_st_rec3_2 ;
correct := correct and i_st_rec3_1 = c_st_rec3_2
and i_st_rec3_2 = c_st_rec3_2 ;
correct := correct and i_t_arr1_1 = c_st_arr1_2
and i_t_arr1_2 = c_st_arr1_2 ;
correct := correct and i_st_arr1_1 = c_st_arr1_2
and i_st_arr1_2 = c_st_arr1_2 ;
correct := correct and i_t_arr2_1 = c_st_arr2_2
and i_t_arr2_2 = c_st_arr2_2 ;
correct := correct and i_st_arr2_1 = c_st_arr2_2
and i_st_arr2_2 = c_st_arr2_2 ;
correct := correct and i_t_arr3_1 = c_st_arr3_2
and i_t_arr3_2 = c_st_arr3_2 ;
correct := correct and i_st_arr3_1 = c_st_arr3_2
and i_st_arr3_2 = c_st_arr3_2 ;
end if ;
--
test_report ( "ENT00238.P00238" ,
"Associated composite buffer ports with generic subtypes",
correct) ;
end process P00238 ;
end ARCH00238 ;
--
entity ENT00238_Test_Bench is
end ENT00238_Test_Bench ;
--
architecture ARCH00238_Test_Bench of ENT00238_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00238 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00238_Test_Bench ;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := saed32;
constant CFG_MEMTECH : integer := saed32;
constant CFG_PADTECH : integer := saed32;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 1;
constant CFG_SCAN : integer := 1;
-- JTAG boundary-scan chain
constant CFG_BOUNDSCAN_EN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := saed32;
constant CFG_CLKMUL : integer := 2;
constant CFG_CLKDIV : integer := 2;
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 0;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 8;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (6);
constant CFG_SPICTRL_FIFO : integer := (4);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 1;
constant CFG_UART2_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (4);
constant CFG_GPT_SW : integer := (12);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 0;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FE#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-------------------------------------------------------------------------------
--
-- Title : fp23_float2fix
-- Design : fpfftk
-- Author : Kapitanov
-- Company :
--
-------------------------------------------------------------------------------
--
-- Description : Float fp23 to signed fix converter
--
-------------------------------------------------------------------------------
--
-- Version 1.0 15.08.2013
-- Description:
-- Bus width for:
-- din = 23
-- dout = 16
-- exp = 6
-- sign = 1
-- mant = 15 + 1
-- Math expression:
-- A = (-1)^sign(A) * 2^(exp(A)-31) * mant(A)
-- NB:
-- Converting from float to fixed takes only 7 clock cycles
--
-- Another algorithm: double precision with 2 DSP48E1.
--
-- Version 1.1 22.08.2014
-- Description: Data width has been changed from 27 to 24.
-- 16 bits - fraction,
-- 1 bit - sign,
-- 7 bits - exponent
--
-- > 2 DSP48E1 blocks used (MEGA_DSP);
--
-- Version 1.2 14.05.2015
-- > SLICEL logic has been simplified;
--
-- Version 1.3 01.11.2015
-- > remove 1 block DSP48E1;
--
-- Version 1.4 01.11.2015
-- > Clear all unrouted signals and components;
--
-- Version 1.5 01.02.2016
-- > Add Barrel shifter instead of DSP48E1;
--
-- Version 1.6 04.04.2016
-- > Careful: check all conditions of input fp data
-- Example: exp = 0x1F, sig = 0, man = 0x0;
--
-- Version 1.7 05.04.2016
-- > Data out width is only 16 bits.
--
-- Version 1.8 07.04.2016
-- > Add constant for negative data converter.
--
-- Version 1.9 22.01.2018
-- > Change exp shift logic.
--
-- Version 1.10 23.01.2018
-- > Overflow and underflow logic has been improved.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- The MIT License (MIT)
-- Copyright (c) 2016 Kapitanov Alexander
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library unisim;
--use unisim.vcomponents.LUT6;
library work;
use work.fp_m1_pkg.fp23_data;
entity fp23_float2fix is
generic(
DW : integer:=16 --! Output data width
);
port(
din : in fp23_data; --! Float input data
ena : in std_logic; --! Data enable
scale : in std_logic_vector(05 downto 0); --! Scale factor
dout : out std_logic_vector(DW-1 downto 0); --! Fixed output data
vld : out std_logic; --! Data out valid
clk : in std_logic; --! Clock
reset : in std_logic; --! Negative reset
overflow : out std_logic --! Flag overflow
);
end fp23_float2fix;
architecture fp23_float2fix of fp23_float2fix is
signal exp_dif : std_logic_vector(4 downto 0);
signal exp_dift : std_logic_vector(5 downto 0);
signal mant : std_logic_vector(DW downto 0);
signal implied : std_logic;
signal frac : std_logic_vector(DW-1 downto 0); --
signal sign_z : std_logic_vector(2 downto 0);
signal valid : std_logic_vector(3 downto 0);
signal shift : std_logic_vector(5 downto 0);
--signal man_shift : std_logic_vector(31 downto 0);
signal norm_man : std_logic_vector(DW-1 downto 0);
signal overflow_i : std_logic;
signal exp_null : std_logic;
signal exp_nullz : std_logic;
signal exp_nullt : std_logic;
signal exp_cmp : std_logic;
signal exp_ovr : std_logic;
begin
shift <= scale when rising_edge(clk);
---- exp difference ----
pr_exp: process(clk) is
begin
if rising_edge(clk) then
exp_dift <= din.exp - shift;
end if;
end process;
pr_cmp: process(clk) is
begin
if rising_edge(clk) then
if (din.exp < shift) then
exp_cmp <= '1';
else
exp_cmp <= '0';
end if;
end if;
end process;
exp_null <= exp_cmp when rising_edge(clk);
exp_nullz <= exp_null when rising_edge(clk);
pr_ovf: process(clk) is
begin
if rising_edge(clk) then
if ("001110" < exp_dift) then
exp_ovr <= '1';
else
exp_ovr <= '0';
end if;
end if;
end process;
exp_nullt <= exp_ovr when rising_edge(clk);
-- implied for mantissa and find sign
pr_impl: process(clk) is
begin
if rising_edge(clk) then
if (din.exp = x"00") then
implied <='0';
else
implied <='1';
end if;
end if;
end process;
-- find fraction --
frac <= din.man when rising_edge(clk);
pr_man: process(clk) is
begin
if rising_edge(clk) then
mant <= implied & frac;
end if;
end process;
sign_z <= sign_z(sign_z'left-1 downto 0) & din.sig when rising_edge(clk);
-- barrel shifter --
exp_dif <= not exp_dift(4 downto 0) when rising_edge(clk);
norm_man <= STD_LOGIC_VECTOR(SHR(UNSIGNED(mant(DW downto 1)), UNSIGNED(exp_dif(3 downto 0)))) when rising_edge(clk);
-- data valid and data out --
pr_out: process(clk) is
begin
if rising_edge(clk) then
if (reset = '1') then
dout <= (others => '0');
else
if (exp_nullz = '1') then
dout <= (others => '0');
else
if (exp_nullt = '1') then
dout(DW-1) <= sign_z(2);
for ii in 0 to DW-2 loop
dout(ii) <= not sign_z(2);
end loop;
else
if (sign_z(2) = '1') then
dout <= (not norm_man) + 1;
else
dout <= norm_man;
end if;
end if;
end if;
end if;
end if;
end process;
valid <= valid(valid'left-1 downto 0) & ena when rising_edge(clk);
vld <= valid(valid'left-1) when rising_edge(clk);
pr_ovr: process(clk) is
begin
if rising_edge(clk) then
overflow_i <= exp_nullt and not exp_nullz;--(exp_hi or exp_lo);
end if;
end process;
overflow <= overflow_i when rising_edge(clk);
end fp23_float2fix; |
-- David Wolf if12b096
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_cntr is
end tb_cntr;
architecture sim of tb_cntr is
component cntr
port (
clk50 : in std_logic; -- Takt
reset_n : in std_logic; -- Externer Reset
ctup_i : in std_logic; -- Zählt rauf
ctdown_i : in std_logic; -- Zahlt ab
ctreset_i : in std_logic; -- Interner Reset
cthold_i : in std_logic; -- Zählt nicht
cntr0_o : out std_logic_vector(3 downto 0); -- Erste Ziffer
cntr1_o : out std_logic_vector(3 downto 0); -- Zweite Ziffer
cntr2_o : out std_logic_vector(3 downto 0); -- Dritte Ziffer
cntr3_o : out std_logic_vector(3 downto 0)); -- Vierte Ziffer
end component;
signal s_clk50 : std_logic := '0';
signal s_reset_n : std_logic := '0';
signal s_ctup_i : std_logic := '0';
signal s_ctdown_i : std_logic := '0';
signal s_ctreset_i : std_logic := '0';
signal s_cthold_i : std_logic := '0';
signal s_cntr0_o : std_logic_vector(3 downto 0) := (others => '0');
signal s_cntr1_o : std_logic_vector(3 downto 0) := "0000";
signal s_cntr2_o : std_logic_vector(3 downto 0) := (others => '0');
signal s_cntr3_o : std_logic_vector(3 downto 0) := "0000";
begin
s_clk50 <= not s_clk50 after 20 ps;
-- Erstellt ein Testobjekt
tb_cntr : cntr
port map (
clk50 => s_clk50,
reset_n => s_reset_n,
ctup_i => s_ctup_i,
ctdown_i => s_ctdown_i,
cthold_i => s_cthold_i,
ctreset_i => s_ctreset_i,
cntr0_o => s_cntr0_o,
cntr1_o => s_cntr1_o,
cntr2_o => s_cntr2_o,
cntr3_o => s_cntr3_o);
p_test : process
begin
-- Testfall: Externer Reset
-- Externer Reset '0' der Rest deaktiviert
s_reset_n <= '0';
s_ctup_i <= '1';
s_ctdown_i <= '1';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 1 ns;
-- Testfall: DOWN
-- s_ctdown_i auf '1'
s_reset_n <= '1';
s_ctup_i <= '1';
s_ctdown_i <= '0';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 17 ns;
-- Testfall: HOLD
-- s_ctdown_i auf '1'
s_reset_n <= '1';
s_ctup_i <= '0';
s_ctdown_i <= '0';
s_cthold_i <= '1';
s_ctreset_i <= '0';
wait for 1 ns;
-- Testfall: HOLD auf DOWN
-- s_ctdown_i auf '1'
s_reset_n <= '1';
s_ctup_i <= '1';
s_ctdown_i <= '1';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 1 ns;
-- Testfall: UP
-- s_ctdup_i auf '1'
s_reset_n <= '1';
s_ctup_i <= '0';
s_ctdown_i <= '1';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 30 ns;
-- Testfall: HOLD
-- s_ctdown_i auf '1'
s_reset_n <= '1';
s_ctup_i <= '0';
s_ctdown_i <= '0';
s_cthold_i <= '1';
s_ctreset_i <= '0';
wait for 1 ns;
-- Testfall: HOLD auf UP
-- s_ctdown_i auf '1'
s_reset_n <= '1';
s_ctup_i <= '1';
s_ctdown_i <= '1';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 1 ns;
-- Testfall: UP auf DOWN
s_reset_n <= '1';
s_ctup_i <= '1';
s_ctdown_i <= '0';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 1 ns;
-- Testfall: DOWN auf UP
s_reset_n <= '1';
s_ctup_i <= '0';
s_ctdown_i <= '1';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 1 ns;
-- Testfall: RESET
-- s_ctdown_i auf '1'
s_reset_n <= '1';
s_ctup_i <= '0';
s_ctdown_i <= '0';
s_cthold_i <= '0';
s_ctreset_i <= '1';
wait for 1 ns;
-- Testfall: Alle Eingänge auf '1'
s_reset_n <= '1';
s_ctup_i <= '1';
s_ctdown_i <= '1';
s_cthold_i <= '1';
s_ctreset_i <= '1';
wait for 1 ns;
-- Testfall: Externer Reset
-- Alle Eingänge '0'
s_reset_n <= '0';
s_ctup_i <= '0';
s_ctdown_i <= '0';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 1 ns;
-- Testfall: Nach Reset sollte der Zustand UP sein.
-- Alle Eingänge auf '0'
s_reset_n <= '1';
s_ctup_i <= '0';
s_ctdown_i <= '0';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 100 ps;
end process p_test;
end sim;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
|
------------------------------------------------------------------------------
---- ----
---- zwishbone DECODE component testbench ----
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- This is the testbench for the gmZPU core ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zwishbone_TB ----
---- File name: gmzpu_tb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: n/a ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Modelsim ----
---- Simulation tools: Modelsim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library gmzpu;
use gmzpu.zwishbone;
entity zwishbone_regs_TB is
end entity zwishbone_regs_TB;
architecture Behave of zwishbone_regs_TB is
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
constant ADR_WIDTH : natural:=11;
constant DATA_WIDTH : natural:=32;
component zwishbone_c_regs is
generic(
ADR_WIDTH : natural:=15;
DATA_WIDTH : natural:=32
);
port (
-- syscon
clk_i : in std_logic;
rst_i : in std_logic;
-- memory control
busy_o : out std_logic;
ready_o : out std_logic;
en_i : in std_logic;
we_i : in std_logic;
adr_i : in unsigned(ADR_WIDTH-1 downto 0);
dat_i : in unsigned(DATA_WIDTH-1 downto 0);
dat_o : out unsigned(DATA_WIDTH-1 downto 0);
-- bus
to_inc_i : in std_logic;
to_rst_i : in std_logic;
to_o : out std_logic;
-- config register value (0x0000, for c_control)
cfg_o : out unsigned(DATA_WIDTH-1 downto 0);
-- status register value (0x0004, from c_control / bus)
err_i : in std_logic;
rty_i : in std_logic
);
end component zwishbone_c_regs;
type sample is record
-- inputs
reset : std_logic;
en_i : std_logic;
we_i : std_logic;
adr_i : unsigned(ADR_WIDTH-1 downto 0);
dat_i : unsigned(DATA_WIDTH-1 downto 0);
to_inc_i : std_logic;
to_rst_i : std_logic;
err_i : std_logic;
rty_i : std_logic;
-- outputs
--dat_o : std_logic_vector(DATA_WIDTH-1 downto 0);
--reg_o : std_logic_vector(DATA_WIDTH-1 downto 0);
--bus_o : std_logic_vector(DATA_WIDTH-1 downto 0);
--radr_o : std_logic_vector(ADR_WIDTH-CS_WIDTH-2 downto 0);
--badr_o : std_logic_vector(ADR_WIDTH-CS_WIDTH-2 downto 0);
--cs_o : std_logic_vector(CS_WIDTH-1 downto 0);
to_o : std_logic;
end record;
type sample_array is array(natural range <>) of sample;
constant test_data : sample_array :=
(
-- rst en we adr dat_i to_inc, to_rst, err rty | to_o
('1','0','0',"00000000000",X"00000000",'0', '0', '1','1', 'U' ),
('1','0','0',"00000000000",X"00000000",'0', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'0', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'0', '0', '1','1', '0' ),
('0','1','0',"00000000000",X"00000000",'0', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'0', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'0', '0', '1','1', '0' ),
('0','1','0',"00000000100",X"00000000",'0', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'0', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'0', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'0', '1', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '0' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '1' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '1' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '1' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '1' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '1' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '1' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '1' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '1' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '1' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '1' ),
('0','0','0',"00000000000",X"00000000",'1', '0', '1','1', '1' ),
('0','0','0',"00000000000",X"00000000",'0', '0', '1','1', '1' ),
('0','0','0',"00000000000",X"00000000",'0', '0', '1','1', '1' ),
('0','0','0',"00000000000",X"00000000",'0', '0', '1','1', '1' ),
('0','0','0',"00000000000",X"00000000",'0', '0', '1','1', '1' )
);
signal clk : std_logic;
signal reset : std_logic:='1';
signal en_i : std_logic;
signal we_i : std_logic;
signal adr_i : unsigned(ADR_WIDTH-1 downto 0);
signal dat_o : unsigned(DATA_WIDTH-1 downto 0);
signal dat_i : unsigned(DATA_WIDTH-1 downto 0);
signal to_rst_i : std_logic;
signal to_inc_i : std_logic;
signal busy_o : std_logic;
signal ready_o : std_logic;
signal rty_i : std_logic;
signal err_i : std_logic;
signal to_o : std_logic;
begin
c_regs : zwishbone_c_regs
generic map( ADR_WIDTH => ADR_WIDTH, DATA_WIDTH => DATA_WIDTH )
port map (adr_i => adr_i, dat_i => dat_i, dat_o => dat_o, en_i => en_i, rst_i => reset, we_i => we_i,
err_i => err_i, rty_i => rty_i, busy_o => busy_o, ready_o => ready_o, clk_i => clk,
to_rst_i => to_rst_i, to_inc_i => to_inc_i, to_o => to_o );
process
variable cycle_count : integer:=0;
begin
for i in test_data'range loop
reset <= test_data(i).reset;
en_i <= test_data(i).en_i;
we_i <= test_data(i).we_i;
adr_i <= test_data(i).adr_i;
dat_i <= test_data(i).dat_i;
to_inc_i <= test_data(i).to_inc_i;
to_rst_i <= test_data(i).to_rst_i;
rty_i <= test_data(i).rty_i;
err_i <= test_data(i).err_i;
clk <= '1';
wait for CLK_S_PER;
clk <= '0';
wait for CLK_S_PER;
assert (to_o = test_data(i).to_o)
report "to_o output mismatch"
severity failure;
end loop;
clk <= '0';
wait;
end process;
end architecture Behave; -- Entity: zwishbone_TB
|
-- NEED RESULT: ARCH00672: Signal default initial values - generic subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00672
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.2 (2)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00672)
-- ENT00672_Test_Bench(ARCH00672_Test_Bench)
--
-- REVISION HISTORY:
--
-- 01-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00672 of GENERIC_STANDARD_TYPES is
signal si_boolean_1 : boolean ;
signal si_boolean_2 : boolean
:= d_boolean ;
signal si_bit_1 : bit ;
signal si_bit_2 : bit
:= d_bit ;
signal si_severity_level_1 : severity_level ;
signal si_severity_level_2 : severity_level
:= d_severity_level ;
signal si_character_1 : character ;
signal si_character_2 : character
:= d_character ;
signal si_t_enum1_1 : t_enum1 ;
signal si_t_enum1_2 : t_enum1
:= d_t_enum1 ;
signal si_st_enum1_1 : st_enum1 ;
signal si_st_enum1_2 : st_enum1
:= d_st_enum1 ;
signal si_integer_1 : integer ;
signal si_integer_2 : integer
:= d_integer ;
signal si_t_int1_1 : t_int1 ;
signal si_t_int1_2 : t_int1
:= d_t_int1 ;
signal si_st_int1_1 : st_int1 ;
signal si_st_int1_2 : st_int1
:= d_st_int1 ;
signal si_time_1 : time ;
signal si_time_2 : time
:= d_time ;
signal si_t_phys1_1 : t_phys1 ;
signal si_t_phys1_2 : t_phys1
:= d_t_phys1 ;
signal si_st_phys1_1 : st_phys1 ;
signal si_st_phys1_2 : st_phys1
:= d_st_phys1 ;
signal si_real_1 : real ;
signal si_real_2 : real
:= d_real ;
signal si_t_real1_1 : t_real1 ;
signal si_t_real1_2 : t_real1
:= d_t_real1 ;
signal si_st_real1_1 : st_real1 ;
signal si_st_real1_2 : st_real1
:= d_st_real1 ;
signal si_st_bit_vector_1 : st_bit_vector ;
signal si_st_bit_vector_2 : st_bit_vector
:= d_st_bit_vector ;
signal si_st_string_1 : st_string ;
signal si_st_string_2 : st_string
:= d_st_string ;
signal si_t_rec1_1 : t_rec1 ;
signal si_t_rec1_2 : t_rec1
:= d_t_rec1 ;
signal si_st_rec1_1 : st_rec1 ;
signal si_st_rec1_2 : st_rec1
:= d_st_rec1 ;
signal si_t_rec2_1 : t_rec2 ;
signal si_t_rec2_2 : t_rec2
:= d_t_rec2 ;
signal si_st_rec2_1 : st_rec2 ;
signal si_st_rec2_2 : st_rec2
:= d_st_rec2 ;
signal si_t_rec3_1 : t_rec3 ;
signal si_t_rec3_2 : t_rec3
:= d_t_rec3 ;
signal si_st_rec3_1 : st_rec3 ;
signal si_st_rec3_2 : st_rec3
:= d_st_rec3 ;
signal si_st_arr1_1 : st_arr1 ;
signal si_st_arr1_2 : st_arr1
:= d_st_arr1 ;
signal si_st_arr2_1 : st_arr2 ;
signal si_st_arr2_2 : st_arr2
:= d_st_arr2 ;
signal si_st_arr3_1 : st_arr3 ;
signal si_st_arr3_2 : st_arr3
:= d_st_arr3 ;
begin
process
variable correct : boolean := true ;
begin
correct := correct and
si_boolean_1 = si_boolean_2 and
si_boolean_2 = d_boolean ;
correct := correct and
si_bit_1 = si_bit_2 and
si_bit_2 = d_bit ;
correct := correct and
si_severity_level_1 = si_severity_level_2 and
si_severity_level_2 = d_severity_level ;
correct := correct and
si_character_1 = si_character_2 and
si_character_2 = d_character ;
correct := correct and
si_t_enum1_1 = si_t_enum1_2 and
si_t_enum1_2 = d_t_enum1 ;
correct := correct and
si_st_enum1_1 = si_st_enum1_2 and
si_st_enum1_2 = d_st_enum1 ;
correct := correct and
si_integer_1 = si_integer_2 and
si_integer_2 = d_integer ;
correct := correct and
si_t_int1_1 = si_t_int1_2 and
si_t_int1_2 = d_t_int1 ;
correct := correct and
si_st_int1_1 = si_st_int1_2 and
si_st_int1_2 = d_st_int1 ;
correct := correct and
si_time_1 = si_time_2 and
si_time_2 = d_time ;
correct := correct and
si_t_phys1_1 = si_t_phys1_2 and
si_t_phys1_2 = d_t_phys1 ;
correct := correct and
si_st_phys1_1 = si_st_phys1_2 and
si_st_phys1_2 = d_st_phys1 ;
correct := correct and
si_real_1 = si_real_2 and
si_real_2 = d_real ;
correct := correct and
si_t_real1_1 = si_t_real1_2 and
si_t_real1_2 = d_t_real1 ;
correct := correct and
si_st_real1_1 = si_st_real1_2 and
si_st_real1_2 = d_st_real1 ;
correct := correct and
si_st_bit_vector_1 = si_st_bit_vector_2 and
si_st_bit_vector_2 = d_st_bit_vector ;
correct := correct and
si_st_string_1 = si_st_string_2 and
si_st_string_2 = d_st_string ;
correct := correct and
si_t_rec1_1 = si_t_rec1_2 and
si_t_rec1_2 = d_t_rec1 ;
correct := correct and
si_st_rec1_1 = si_st_rec1_2 and
si_st_rec1_2 = d_st_rec1 ;
correct := correct and
si_t_rec2_1 = si_t_rec2_2 and
si_t_rec2_2 = d_t_rec2 ;
correct := correct and
si_st_rec2_1 = si_st_rec2_2 and
si_st_rec2_2 = d_st_rec2 ;
correct := correct and
si_t_rec3_1 = si_t_rec3_2 and
si_t_rec3_2 = d_t_rec3 ;
correct := correct and
si_st_rec3_1 = si_st_rec3_2 and
si_st_rec3_2 = d_st_rec3 ;
correct := correct and
si_st_arr1_1 = si_st_arr1_2 and
si_st_arr1_2 = d_st_arr1 ;
correct := correct and
si_st_arr2_1 = si_st_arr2_2 and
si_st_arr2_2 = d_st_arr2 ;
correct := correct and
si_st_arr3_1 = si_st_arr3_2 and
si_st_arr3_2 = d_st_arr3 ;
test_report ( "ARCH00672" ,
"Signal default initial values - generic subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00672 ;
--
entity ENT00672_Test_Bench is
end ENT00672_Test_Bench ;
--
architecture ARCH00672_Test_Bench of ENT00672_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00672 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00672_Test_Bench ;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_1_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_dma_0_wrapper_fifo_generator_v9_3_1_exdes IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(39-1 DOWNTO 0);
DOUT : OUT std_logic_vector(39-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg;
PACKAGE BODY system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_ba
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ba-e.vhd,v 1.3 2005/07/19 07:13:12 wig Exp $
-- $Date: 2005/07/19 07:13:12 $
-- $Log: ent_ba-e.vhd,v $
-- Revision 1.3 2005/07/19 07:13:12 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_ba
--
entity ent_ba is
-- Generics:
-- No Generated Generics for Entity ent_ba
-- Generated Port Declaration:
-- No Generated Port for Entity ent_ba
end ent_ba;
--
-- End of Generated Entity ent_ba
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- *********************************************************************
-- Copyright 2008, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of Cypress.
--
-- Disclaimer: Cypress makes no warranty of any kind, express or
-- implied, with regard to this material, including, but not limited to,
-- the implied warranties of merchantability and fitness for a particular
-- purpose. Cypress reserves the right to make changes without further
-- notice to the materials described herein. Cypress does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. Cypress' products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the Cypress Software License Agreement.
--
-- *********************************************************************
-- Author : $Author: fwi $ @ cypress.com
-- Department : MPD_BE
-- Date : $Date: 2010-07-02 09:41:24 +0200 (Fri, 02 Jul 2010) $
-- Revision : $Revision: 531 $
-- *********************************************************************
-- Description
--
-- *********************************************************************
-------------------
-- LIBRARY USAGE --
-------------------
--common:
---------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
--user:
-----------
--library work;
--use work.all;
--use work.app_pack.all;
entity spi_seq is
generic (
gSIMULATION : integer := 0;
gSysClkSpeed : integer := 50;
gDATA_WIDTH : integer := 26;
gSyncTriggerWidth : integer := 1; -- min 1, max 15
gRWbitposition : integer := 0; -- seen from LSB, when > 32
gRWbitpolarity : integer := 0 -- '0': On SPI channel write = 1, read = 0. '1': inverse
);
port (
-- system:
CLK : in std_logic;
RESET : in std_logic;
BUSY : out std_logic;
--synchro signals
synctriggers : in std_logic_vector(gSyncTriggerWidth-1 downto 0);
sync1_select : in std_logic_vector(3 downto 0);
sync2_select : in std_logic_vector(3 downto 0);
-- Fifo signals
-- read fifo interface (SPI write path/SPI read address path)
APP_RDFIFO_CLK : out std_logic;
APP_RDFIFO_EN : out std_logic;
APP_RDFIFO_DATA_OUT : in std_logic_vector( 31 downto 0);
APP_RDFIFO_EMPTY : in std_logic;
-- write fifo interface (SPI read data path)
APP_WRFIFO_CLK : out std_logic;
APP_WRFIFO_EN : out std_logic;
APP_WRFIFO_DATA_IN : out std_logic_vector( 31 downto 0);
APP_WRFIFO_FULL : in std_logic;
ERROR : out std_logic;
SPI_START : out std_logic;
SPI_BUSY : in std_logic;
SPI_DATA_TX : out std_logic_Vector(gDATA_WIDTH-1 downto 0);
SPI_DATA_RX : in std_logic_vector(gDATA_WIDTH-1 downto 0)
);
end spi_seq;
Architecture behaviour of spi_seq is
----------------------
--constant definition:
----------------------
type spi_seqtp is (
Idle,
WaitSync1,
WaitSync1First,
WaitSync2,
Check_Fifo_Empty,
Read_En_Active,
Read_En_Active2,
GetFifoValue,
DoSpiComm,
Wait_spi_comm_busy,
Wait_spi_comm_busy_off
);
---------------------
-- signal definition:
---------------------
signal spi_seq : spi_seqtp;
signal SpiRw : std_logic; --'0' = write, '1' = read
signal Sync1_rising : std_logic;
signal Sync2_rising : std_logic;
signal synctriggers_prev : std_logic_vector(gSyncTriggerWidth-1 downto 0);
begin
--------------------------
-- default values --
--------------------------
APP_RDFIFO_CLK <= CLK;
APP_WRFIFO_CLK <= CLK;
--------------------------
-- Process definition: --
--------------------------
-- APP_RDFIFO_DATA_OUT bit assignments
-- bit 31 sync 2
-- bit 30 sync 1
-- bit 29 NOP bit
-- bits 28 RW (W = 0, R = 1)
-- bits 27 dt 0: address + data
spi_sequencer: Process (CLK, RESET)
variable RWbit : std_logic;
begin
if (RESET='1') then
BUSY <= '0';
SPI_START <= '0';
SPI_DATA_TX <= (others => '0');
SpiRw <= '0';
RWbit := '0';
APP_RDFIFO_EN <= '0';
APP_WRFIFO_EN <= '0';
APP_WRFIFO_DATA_IN <= (others => '0');
ERROR <= '0';
spi_seq <= Idle;
elsif (CLK'event and CLK='1') then
SPI_START <= '0';
APP_RDFIFO_EN <= '0';
APP_WRFIFO_EN <= '0';
Case spi_seq is
when Idle =>
BUSY <= '0';
if (APP_RDFIFO_EMPTY = '0') then
APP_RDFIFO_EN <= '1';
spi_seq <= Read_En_Active;
end if;
when Check_Fifo_Empty =>
if (APP_RDFIFO_EMPTY = '0') then
APP_RDFIFO_EN <= '1';
spi_seq <= Read_En_Active;
else
spi_seq <= Idle;
end if;
when Read_En_Active =>
spi_seq <= Read_En_Active2;
when Read_En_Active2 =>
spi_seq <= GetFifoValue;
when GetFifoValue =>
case APP_RDFIFO_DATA_OUT(31 downto 30) is
when "00" => --Immediate =>
spi_seq <= DoSpiComm;
when "01" => --Sync1 =>
spi_seq <= WaitSync1;
when "10" => --Sync2 =>
spi_seq <= WaitSync2;
when "11" => --FirstSync1ThenSync2 =>
spi_seq <= WaitSync1First;
when others =>
spi_seq <= DoSpiComm;
end case;
when WaitSync1 =>
if (Sync1_rising = '1') then
spi_seq <= DoSpiComm;
end if;
when WaitSync1First =>
if (Sync1_rising = '1') then
spi_seq <= WaitSync2;
end if;
when WaitSync2 =>
if (Sync2_rising = '1') then
spi_seq <= DoSpiComm;
end if;
when DoSpiComm =>
if (APP_RDFIFO_DATA_OUT(29) = '0') then
SpiRw <= APP_RDFIFO_DATA_OUT(28);
SPI_START <= '1';
--
--
if (gRWbitpolarity > 0) then
RWbit := APP_RDFIFO_DATA_OUT(28);
else
RWbit := not APP_RDFIFO_DATA_OUT(28);
end if;
if (gRWbitposition = 0) then
SPI_DATA_TX <= APP_RDFIFO_DATA_OUT(gDATA_WIDTH-2 downto 0) & RWbit;
elsif (gRWbitposition = 27) then
SPI_DATA_TX <= RWbit & APP_RDFIFO_DATA_OUT(gDATA_WIDTH-2 downto 0);
elsif (gRWbitposition > 32) then
SPI_DATA_TX <= APP_RDFIFO_DATA_OUT(gDATA_WIDTH-1 downto 0);
else
SPI_DATA_TX <= APP_RDFIFO_DATA_OUT(gDATA_WIDTH-2 downto gRWbitposition) & RWbit & APP_RDFIFO_DATA_OUT(gRWbitposition-1 downto 0);
end if;
spi_seq <= Wait_spi_comm_busy;
else --NOP bit set
spi_seq <= Check_Fifo_Empty;
end if;
when Wait_spi_comm_busy =>
if (SPI_BUSY = '1') then
spi_seq <= Wait_spi_comm_busy_off;
end if;
when Wait_spi_comm_busy_off =>
if (SPI_BUSY = '0') then
if (SpiRw = '1') then --a read was performed, so write the result to FIFO
APP_WRFIFO_DATA_IN(31 downto gDATA_WIDTH) <= (others => '0');
APP_WRFIFO_DATA_IN(gDATA_WIDTH-1 downto 0) <= SPI_DATA_RX;
APP_WRFIFO_EN <= '1';
ERROR <= APP_WRFIFO_FULL;
end if;
spi_seq <= Check_Fifo_Empty;
end if;
when others =>
spi_seq <= Idle;
end case;
end if;
end process;
spi_triggerselector: Process (CLK, RESET)
begin
if (RESET='1') then
Sync1_rising <= '0';
Sync2_rising <= '0';
synctriggers_prev <= (others => '0');
elsif (CLK'event and CLK='1') then
synctriggers_prev <= synctriggers;
for i in 0 to gSyncTriggerWidth-1 loop
if (TO_INTEGER(UNSIGNED(sync1_select)) = i) then
Sync1_rising <= synctriggers_prev(i) and not synctriggers(i);
end if;
if (TO_INTEGER(UNSIGNED(sync2_select)) = i) then
Sync2_rising <= synctriggers_prev(i) and not synctriggers(i);
end if;
end loop;
end if;
end process;
end behaviour; |
library ieee;
use ieee.std_logic_1164.all;
package sync_pkg is
component sync is
generic
(
SYNC_STAGES : integer range 2 to integer'high;
RESET_VALUE : std_logic
);
port
(
sys_clk : in std_logic;
sys_res_n : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component sync;
end package sync_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
package sync_pkg is
component sync is
generic
(
SYNC_STAGES : integer range 2 to integer'high;
RESET_VALUE : std_logic
);
port
(
sys_clk : in std_logic;
sys_res_n : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component sync;
end package sync_pkg;
|
entity e is end entity;
architecture a of e is
signal bar, boo : integer;
function func (x : integer; b : boolean) return boolean;
function func return integer;
procedure proc (x : integer);
procedure proc;
alias foo is bar;
alias blah : integer is boo;
alias funci is func [integer, boolean return boolean];
alias proci is proc [integer];
alias proce is proc [];
alias funce is func [return integer];
begin
end architecture;
|
-- NEED RESULT: ENT00202: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00202: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00202: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00202: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00202
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00202(ARCH00202)
-- ENT00202_Test_Bench(ARCH00202_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00202 is
generic (G : integer) ;
port (
s_st_int1_vector : inout st_int1_vector
) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00202 ;
--
--
architecture ARCH00202 of ENT00202 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_int1_vector : inout st_int1_vector
; variable counter : inout integer
; variable correct : inout boolean
; variable savtime : inout time
; signal chk_st_int1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_2(1) ;
s_st_int1_vector(2) <= transport
c_st_int1_vector_2(2) after 10 ns ;
wait until s_st_int1_vector(2) =
c_st_int1_vector_2(2) ;
Test_Report (
"ENT00202",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(2) =
c_st_int1_vector_2(2) )) ;
--
when 1
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_1(1) ;
s_st_int1_vector(G) <= transport
c_st_int1_vector_2(G) after 10 ns ;
wait until s_st_int1_vector(G) =
c_st_int1_vector_2(G) ;
Test_Report (
"ENT00202",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(G) =
c_st_int1_vector_2(G) )) ;
--
when 2
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_2(1) ;
s_st_int1_vector(CG) <= transport
c_st_int1_vector_2(CG) after 10 ns ;
wait until s_st_int1_vector(CG) =
c_st_int1_vector_2(CG) ;
Test_Report (
"ENT00202",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(CG) =
c_st_int1_vector_2(CG) )) ;
--
when 3
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_1(1) ;
s_st_int1_vector(CG'Attr) <= transport
c_st_int1_vector_2(CG'Attr) after 10 ns ;
wait until s_st_int1_vector(CG'Attr) =
c_st_int1_vector_2(CG'Attr) ;
Test_Report (
"ENT00202",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(CG'Attr) =
c_st_int1_vector_2(CG'Attr) )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
Proc1 (
s_st_int1_vector
, counter
, correct
, savtime
, chk_st_int1_vector
) ;
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_int1_vector = 3 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00202 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00202_Test_Bench is
end ENT00202_Test_Bench ;
--
--
architecture ARCH00202_Test_Bench of ENT00202_Test_Bench is
begin
L1:
block
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
--
component UUT
generic (G : integer) ;
port (
s_st_int1_vector : inout st_int1_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00202 ( ARCH00202 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
port map (
s_st_int1_vector
)
;
end block L1 ;
end ARCH00202_Test_Bench ;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
use work.cpu_types_pkg.all;
use work.cpu_mmu_inst_types_pkg.all;
architecture rtl of cpu_mmu_inst_pass is
type reg_type is record
mmuen : std_ulogic;
vpn : cpu_vpn_type;
end record;
signal r, r_next : reg_type;
type comb_type is record
ppn : cpu_ppn_type;
end record;
signal c : comb_type;
begin
ppn_large_vpn_gen : if cpu_ppn_bits > 0 and cpu_ppn_bits <= cpu_vpn_bits generate
bit_loop : for n in cpu_ppn_bits-1 downto 0 generate
c.ppn(n) <= r.vpn(n);
end generate;
end generate;
ppn_small_vpn_gen : if cpu_ppn_bits > 0 and cpu_ppn_bits > cpu_vpn_bits generate
c.ppn(cpu_ppn_bits-1 downto cpu_vpn_bits) <= (others => '0');
c.ppn(cpu_vpn_bits-1 downto 0) <= r.vpn;
end generate;
r_next <= (
mmuen => cpu_mmu_inst_pass_ctrl_in.mmuen,
vpn => cpu_mmu_inst_pass_dp_in.vpn
);
seq : process (clk) is
begin
if rising_edge(clk) then
case rstn is
when '0' =>
r <= (
mmuen => '0',
vpn => (others => 'X')
);
when '1' =>
r <= r_next;
when others =>
r <= (
mmuen => 'X',
vpn => (others => 'X')
);
end case;
end if;
end process;
--cpu_mmu_inst_pass_ctrl_out <= (
-- );
cpu_mmu_inst_pass_ctrl_out <= (
ready => '1',
result => (
cpu_mmu_inst_result_code_index_valid => not r.mmuen,
cpu_mmu_inst_result_code_index_error => '0',
cpu_mmu_inst_result_code_index_tlbmiss => r.mmuen,
cpu_mmu_inst_result_code_index_pf => '0'
)
);
cpu_mmu_inst_pass_dp_out <= (
ppn => c.ppn
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_469 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_469;
architecture augh of mul_469 is
signal tmp_res : signed(45 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(30 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_469 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_469;
architecture augh of mul_469 is
signal tmp_res : signed(45 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(30 downto 0));
end architecture;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity array_io is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
d_o_din : OUT STD_LOGIC_VECTOR (15 downto 0);
d_o_full_n : IN STD_LOGIC;
d_o_write : OUT STD_LOGIC;
d_i_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
d_i_ce0 : OUT STD_LOGIC;
d_i_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
d_i_address1 : OUT STD_LOGIC_VECTOR (4 downto 0);
d_i_ce1 : OUT STD_LOGIC;
d_i_q1 : IN STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of array_io is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"array_io,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.361000,HLS_SYN_LAT=33,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=3962,HLS_SYN_LUT=2021}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000100000000000000";
constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000001000000000000000";
constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000010000000000000000";
constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000100000000000000000";
constant ap_ST_fsm_state19 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000001000000000000000000";
constant ap_ST_fsm_state20 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000010000000000000000000";
constant ap_ST_fsm_state21 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000100000000000000000000";
constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000001000000000000000000000";
constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000010000000000000000000000";
constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000100000000000000000000000";
constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (33 downto 0) := "0000000001000000000000000000000000";
constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (33 downto 0) := "0000000010000000000000000000000000";
constant ap_ST_fsm_state27 : STD_LOGIC_VECTOR (33 downto 0) := "0000000100000000000000000000000000";
constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (33 downto 0) := "0000001000000000000000000000000000";
constant ap_ST_fsm_state29 : STD_LOGIC_VECTOR (33 downto 0) := "0000010000000000000000000000000000";
constant ap_ST_fsm_state30 : STD_LOGIC_VECTOR (33 downto 0) := "0000100000000000000000000000000000";
constant ap_ST_fsm_state31 : STD_LOGIC_VECTOR (33 downto 0) := "0001000000000000000000000000000000";
constant ap_ST_fsm_state32 : STD_LOGIC_VECTOR (33 downto 0) := "0010000000000000000000000000000000";
constant ap_ST_fsm_state33 : STD_LOGIC_VECTOR (33 downto 0) := "0100000000000000000000000000000000";
constant ap_ST_fsm_state34 : STD_LOGIC_VECTOR (33 downto 0) := "1000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal acc_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal acc_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal d_o_blk_n : STD_LOGIC;
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal ap_CS_fsm_state11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
signal ap_CS_fsm_state12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal ap_CS_fsm_state13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none";
signal ap_CS_fsm_state14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state14 : signal is "none";
signal ap_CS_fsm_state15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state15 : signal is "none";
signal ap_CS_fsm_state16 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state16 : signal is "none";
signal ap_CS_fsm_state17 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state17 : signal is "none";
signal ap_CS_fsm_state18 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state18 : signal is "none";
signal ap_CS_fsm_state19 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state19 : signal is "none";
signal ap_CS_fsm_state20 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state20 : signal is "none";
signal ap_CS_fsm_state21 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state21 : signal is "none";
signal ap_CS_fsm_state22 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state22 : signal is "none";
signal ap_CS_fsm_state23 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state23 : signal is "none";
signal ap_CS_fsm_state24 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state24 : signal is "none";
signal ap_CS_fsm_state25 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state25 : signal is "none";
signal ap_CS_fsm_state26 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state26 : signal is "none";
signal ap_CS_fsm_state27 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state27 : signal is "none";
signal ap_CS_fsm_state28 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state28 : signal is "none";
signal ap_CS_fsm_state29 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state29 : signal is "none";
signal ap_CS_fsm_state30 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state30 : signal is "none";
signal ap_CS_fsm_state31 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state31 : signal is "none";
signal ap_CS_fsm_state32 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state32 : signal is "none";
signal ap_CS_fsm_state33 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state33 : signal is "none";
signal ap_CS_fsm_state34 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state34 : signal is "none";
signal reg_406 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal reg_410 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_414 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_418 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_422 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_426 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_fu_438_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_reg_1080 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_1_fu_453_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_1_reg_1100 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_4_reg_1105 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_5_reg_1111 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_2_fu_468_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_2_reg_1132 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_6_reg_1137 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_7_reg_1143 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_3_fu_483_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_3_reg_1164 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_4_fu_498_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_4_reg_1184 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_10_reg_1189 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_11_reg_1195 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_5_fu_512_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_5_reg_1216 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_12_reg_1221 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_13_reg_1227 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_6_fu_526_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_6_reg_1248 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_14_reg_1253 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_15_reg_1259 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_7_fu_540_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_7_reg_1280 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_16_reg_1285 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_17_reg_1291 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_8_fu_546_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_8_reg_1307 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_18_reg_1312 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_19_reg_1318 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_9_fu_552_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_9_reg_1334 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_20_reg_1339 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_21_reg_1345 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_s_fu_558_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_s_reg_1361 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_22_reg_1366 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_23_reg_1372 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_10_fu_563_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_10_reg_1388 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_24_reg_1393 : STD_LOGIC_VECTOR (15 downto 0);
signal d_i_load_25_reg_1399 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_11_fu_576_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_11_reg_1415 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_15_fu_584_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_15_reg_1420 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_16_fu_591_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_16_reg_1426 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp2_fu_608_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp2_reg_1432 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp5_fu_627_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp5_reg_1437 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_1_12_fu_647_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_12_reg_1452 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_17_fu_655_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_17_reg_1457 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_18_fu_662_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_18_reg_1463 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp8_fu_720_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp8_reg_1469 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp11_fu_740_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp11_reg_1474 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_1_13_fu_760_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_13_reg_1489 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_19_fu_768_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_19_reg_1494 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_20_fu_775_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_20_reg_1500 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp14_fu_833_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp14_reg_1506 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp17_fu_853_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp17_reg_1511 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_1_21_fu_879_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_21_reg_1516 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_22_fu_886_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_22_reg_1522 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp20_fu_945_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp20_reg_1528 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp23_fu_965_p2 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp23_reg_1533 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_1_23_fu_977_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_23_reg_1538 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_24_fu_1021_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_24_reg_1543 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_25_fu_1025_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_25_reg_1548 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_26_fu_1030_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_26_reg_1553 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_27_fu_1035_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_27_reg_1558 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_28_fu_1040_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_28_reg_1563 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_29_fu_1045_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_29_reg_1568 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_30_fu_1050_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_30_reg_1573 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_14_fu_871_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal temp_s_fu_674_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_1_fu_694_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_2_fu_787_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_3_fu_807_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_4_fu_899_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_5_fu_919_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_6_fu_989_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal temp_7_fu_1009_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_434_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_9_fu_449_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_10_fu_464_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_11_fu_479_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_12_fu_494_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_13_fu_508_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_14_fu_522_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_15_fu_536_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_16_cast_fu_581_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_24_cast_fu_595_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp3_fu_598_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp3_cast_fu_604_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_8_cast_fu_568_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_17_cast_fu_588_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_25_cast_fu_614_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp6_fu_617_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp6_cast_fu_623_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_9_cast_fu_572_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_fu_633_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp2_cast_fu_671_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp1_fu_666_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_s_fu_637_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp5_cast_fu_691_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp4_fu_686_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_cast_fu_652_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_26_cast_fu_706_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp9_fu_710_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp9_cast_fu_716_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_10_cast_fu_641_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_19_cast_fu_659_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_27_cast_fu_726_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp12_fu_730_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp12_cast_fu_736_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_11_cast_fu_644_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_2_fu_746_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp8_cast_fu_784_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp7_fu_779_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_750_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp11_cast_fu_804_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp10_fu_799_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_cast_fu_765_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_28_cast_fu_819_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp15_fu_823_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp15_cast_fu_829_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_12_cast_fu_754_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_21_cast_fu_772_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_29_cast_fu_839_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp18_fu_843_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp18_cast_fu_849_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_13_cast_fu_757_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_4_fu_859_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp14_cast_fu_896_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp13_fu_891_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_fu_862_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp17_cast_fu_916_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp16_fu_911_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_cast_fu_876_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_30_cast_fu_931_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp21_fu_935_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp21_cast_fu_941_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_14_cast_fu_865_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_23_cast_fu_883_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_31_cast_fu_951_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp24_fu_955_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp24_cast_fu_961_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_15_cast_fu_868_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_6_fu_971_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp20_cast_fu_986_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp19_fu_981_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_fu_974_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp23_cast_fu_1006_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp22_fu_1001_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (33 downto 0);
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state16) and (d_o_full_n = ap_const_logic_1))) then
acc_0 <= temp_s_fu_674_p2;
acc_1 <= temp_1_fu_694_p2;
tmp11_reg_1474 <= tmp11_fu_740_p2;
tmp8_reg_1469 <= tmp8_fu_720_p2;
tmp_1_12_reg_1452 <= tmp_1_12_fu_647_p2;
tmp_1_17_reg_1457 <= tmp_1_17_fu_655_p2;
tmp_1_18_reg_1463 <= tmp_1_18_fu_662_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state17) and (d_o_full_n = ap_const_logic_1))) then
acc_2 <= temp_2_fu_787_p2;
acc_3 <= temp_3_fu_807_p2;
tmp14_reg_1506 <= tmp14_fu_833_p2;
tmp17_reg_1511 <= tmp17_fu_853_p2;
tmp_1_13_reg_1489 <= tmp_1_13_fu_760_p2;
tmp_1_19_reg_1494 <= tmp_1_19_fu_768_p2;
tmp_1_20_reg_1500 <= tmp_1_20_fu_775_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state18) and (d_o_full_n = ap_const_logic_1))) then
acc_4 <= temp_4_fu_899_p2;
acc_5 <= temp_5_fu_919_p2;
tmp20_reg_1528 <= tmp20_fu_945_p2;
tmp23_reg_1533 <= tmp23_fu_965_p2;
tmp_1_21_reg_1516 <= tmp_1_21_fu_879_p2;
tmp_1_22_reg_1522 <= tmp_1_22_fu_886_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state19) and (d_o_full_n = ap_const_logic_1))) then
acc_6 <= temp_6_fu_989_p2;
acc_7 <= temp_7_fu_1009_p2;
tmp_1_23_reg_1538 <= tmp_1_23_fu_977_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_10_reg_1189 <= d_i_q0;
d_i_load_11_reg_1195 <= d_i_q1;
tmp_1_4_reg_1184 <= tmp_1_4_fu_498_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state8) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_12_reg_1221 <= d_i_q0;
d_i_load_13_reg_1227 <= d_i_q1;
tmp_1_5_reg_1216 <= tmp_1_5_fu_512_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state9) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_14_reg_1253 <= d_i_q0;
d_i_load_15_reg_1259 <= d_i_q1;
tmp_1_6_reg_1248 <= tmp_1_6_fu_526_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state10) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_16_reg_1285 <= d_i_q0;
d_i_load_17_reg_1291 <= d_i_q1;
tmp_1_7_reg_1280 <= tmp_1_7_fu_540_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state11) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_18_reg_1312 <= d_i_q0;
d_i_load_19_reg_1318 <= d_i_q1;
tmp_1_8_reg_1307 <= tmp_1_8_fu_546_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state12) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_20_reg_1339 <= d_i_q0;
d_i_load_21_reg_1345 <= d_i_q1;
tmp_1_9_reg_1334 <= tmp_1_9_fu_552_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state13) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_22_reg_1366 <= d_i_q0;
d_i_load_23_reg_1372 <= d_i_q1;
tmp_1_s_reg_1361 <= tmp_1_s_fu_558_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state14) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_24_reg_1393 <= d_i_q0;
d_i_load_25_reg_1399 <= d_i_q1;
tmp_1_10_reg_1388 <= tmp_1_10_fu_563_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_4_reg_1105 <= d_i_q0;
d_i_load_5_reg_1111 <= d_i_q1;
tmp_1_1_reg_1100 <= tmp_1_1_fu_453_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (d_o_full_n = ap_const_logic_1))) then
d_i_load_6_reg_1137 <= d_i_q0;
d_i_load_7_reg_1143 <= d_i_q1;
tmp_1_2_reg_1132 <= tmp_1_2_fu_468_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) or ((ap_const_logic_1 = ap_CS_fsm_state16) and (d_o_full_n = ap_const_logic_1)))) then
reg_406 <= d_i_q0;
reg_410 <= d_i_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_CS_fsm_state3) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state17) and (d_o_full_n = ap_const_logic_1)))) then
reg_414 <= d_i_q0;
reg_418 <= d_i_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_CS_fsm_state6) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state15) and (d_o_full_n = ap_const_logic_1)))) then
reg_422 <= d_i_q0;
reg_426 <= d_i_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state15) and (d_o_full_n = ap_const_logic_1))) then
tmp2_reg_1432 <= tmp2_fu_608_p2;
tmp5_reg_1437 <= tmp5_fu_627_p2;
tmp_1_11_reg_1415 <= tmp_1_11_fu_576_p2;
tmp_1_15_reg_1420 <= tmp_1_15_fu_584_p2;
tmp_1_16_reg_1426 <= tmp_1_16_fu_591_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state20) and (d_o_full_n = ap_const_logic_1))) then
tmp_1_24_reg_1543 <= tmp_1_24_fu_1021_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state21) and (d_o_full_n = ap_const_logic_1))) then
tmp_1_25_reg_1548 <= tmp_1_25_fu_1025_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state22) and (d_o_full_n = ap_const_logic_1))) then
tmp_1_26_reg_1553 <= tmp_1_26_fu_1030_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state23) and (d_o_full_n = ap_const_logic_1))) then
tmp_1_27_reg_1558 <= tmp_1_27_fu_1035_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state24) and (d_o_full_n = ap_const_logic_1))) then
tmp_1_28_reg_1563 <= tmp_1_28_fu_1040_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state25) and (d_o_full_n = ap_const_logic_1))) then
tmp_1_29_reg_1568 <= tmp_1_29_fu_1045_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state26) and (d_o_full_n = ap_const_logic_1))) then
tmp_1_30_reg_1573 <= tmp_1_30_fu_1050_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (d_o_full_n = ap_const_logic_1))) then
tmp_1_3_reg_1164 <= tmp_1_3_fu_483_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (d_o_full_n = ap_const_logic_1))) then
tmp_8_reg_1080 <= tmp_8_fu_438_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, d_o_full_n, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state17, ap_CS_fsm_state18, ap_CS_fsm_state19, ap_CS_fsm_state20, ap_CS_fsm_state21, ap_CS_fsm_state22, ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32, ap_CS_fsm_state33, ap_CS_fsm_state34)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state4;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state4 =>
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state5;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state5 =>
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_state5;
end if;
when ap_ST_fsm_state6 =>
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_state6;
end if;
when ap_ST_fsm_state7 =>
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state8;
else
ap_NS_fsm <= ap_ST_fsm_state7;
end if;
when ap_ST_fsm_state8 =>
if (((ap_const_logic_1 = ap_CS_fsm_state8) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state9;
else
ap_NS_fsm <= ap_ST_fsm_state8;
end if;
when ap_ST_fsm_state9 =>
if (((ap_const_logic_1 = ap_CS_fsm_state9) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state10;
else
ap_NS_fsm <= ap_ST_fsm_state9;
end if;
when ap_ST_fsm_state10 =>
if (((ap_const_logic_1 = ap_CS_fsm_state10) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state11;
else
ap_NS_fsm <= ap_ST_fsm_state10;
end if;
when ap_ST_fsm_state11 =>
if (((ap_const_logic_1 = ap_CS_fsm_state11) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state12;
else
ap_NS_fsm <= ap_ST_fsm_state11;
end if;
when ap_ST_fsm_state12 =>
if (((ap_const_logic_1 = ap_CS_fsm_state12) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state13;
else
ap_NS_fsm <= ap_ST_fsm_state12;
end if;
when ap_ST_fsm_state13 =>
if (((ap_const_logic_1 = ap_CS_fsm_state13) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_state13;
end if;
when ap_ST_fsm_state14 =>
if (((ap_const_logic_1 = ap_CS_fsm_state14) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state15;
else
ap_NS_fsm <= ap_ST_fsm_state14;
end if;
when ap_ST_fsm_state15 =>
if (((ap_const_logic_1 = ap_CS_fsm_state15) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state16;
else
ap_NS_fsm <= ap_ST_fsm_state15;
end if;
when ap_ST_fsm_state16 =>
if (((ap_const_logic_1 = ap_CS_fsm_state16) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state17;
else
ap_NS_fsm <= ap_ST_fsm_state16;
end if;
when ap_ST_fsm_state17 =>
if (((ap_const_logic_1 = ap_CS_fsm_state17) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state18;
else
ap_NS_fsm <= ap_ST_fsm_state17;
end if;
when ap_ST_fsm_state18 =>
if (((ap_const_logic_1 = ap_CS_fsm_state18) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state19;
else
ap_NS_fsm <= ap_ST_fsm_state18;
end if;
when ap_ST_fsm_state19 =>
if (((ap_const_logic_1 = ap_CS_fsm_state19) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state20;
else
ap_NS_fsm <= ap_ST_fsm_state19;
end if;
when ap_ST_fsm_state20 =>
if (((ap_const_logic_1 = ap_CS_fsm_state20) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state21;
else
ap_NS_fsm <= ap_ST_fsm_state20;
end if;
when ap_ST_fsm_state21 =>
if (((ap_const_logic_1 = ap_CS_fsm_state21) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state22;
else
ap_NS_fsm <= ap_ST_fsm_state21;
end if;
when ap_ST_fsm_state22 =>
if (((ap_const_logic_1 = ap_CS_fsm_state22) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state23;
else
ap_NS_fsm <= ap_ST_fsm_state22;
end if;
when ap_ST_fsm_state23 =>
if (((ap_const_logic_1 = ap_CS_fsm_state23) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state24;
else
ap_NS_fsm <= ap_ST_fsm_state23;
end if;
when ap_ST_fsm_state24 =>
if (((ap_const_logic_1 = ap_CS_fsm_state24) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state25;
else
ap_NS_fsm <= ap_ST_fsm_state24;
end if;
when ap_ST_fsm_state25 =>
if (((ap_const_logic_1 = ap_CS_fsm_state25) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state26;
else
ap_NS_fsm <= ap_ST_fsm_state25;
end if;
when ap_ST_fsm_state26 =>
if (((ap_const_logic_1 = ap_CS_fsm_state26) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state27;
else
ap_NS_fsm <= ap_ST_fsm_state26;
end if;
when ap_ST_fsm_state27 =>
if (((ap_const_logic_1 = ap_CS_fsm_state27) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state28;
else
ap_NS_fsm <= ap_ST_fsm_state27;
end if;
when ap_ST_fsm_state28 =>
if (((ap_const_logic_1 = ap_CS_fsm_state28) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state29;
else
ap_NS_fsm <= ap_ST_fsm_state28;
end if;
when ap_ST_fsm_state29 =>
if (((ap_const_logic_1 = ap_CS_fsm_state29) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state30;
else
ap_NS_fsm <= ap_ST_fsm_state29;
end if;
when ap_ST_fsm_state30 =>
if (((ap_const_logic_1 = ap_CS_fsm_state30) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state31;
else
ap_NS_fsm <= ap_ST_fsm_state30;
end if;
when ap_ST_fsm_state31 =>
if (((ap_const_logic_1 = ap_CS_fsm_state31) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state32;
else
ap_NS_fsm <= ap_ST_fsm_state31;
end if;
when ap_ST_fsm_state32 =>
if (((ap_const_logic_1 = ap_CS_fsm_state32) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state33;
else
ap_NS_fsm <= ap_ST_fsm_state32;
end if;
when ap_ST_fsm_state33 =>
if (((ap_const_logic_1 = ap_CS_fsm_state33) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state34;
else
ap_NS_fsm <= ap_ST_fsm_state33;
end if;
when ap_ST_fsm_state34 =>
if (((ap_const_logic_1 = ap_CS_fsm_state34) and (d_o_full_n = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state34;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(9);
ap_CS_fsm_state11 <= ap_CS_fsm(10);
ap_CS_fsm_state12 <= ap_CS_fsm(11);
ap_CS_fsm_state13 <= ap_CS_fsm(12);
ap_CS_fsm_state14 <= ap_CS_fsm(13);
ap_CS_fsm_state15 <= ap_CS_fsm(14);
ap_CS_fsm_state16 <= ap_CS_fsm(15);
ap_CS_fsm_state17 <= ap_CS_fsm(16);
ap_CS_fsm_state18 <= ap_CS_fsm(17);
ap_CS_fsm_state19 <= ap_CS_fsm(18);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state20 <= ap_CS_fsm(19);
ap_CS_fsm_state21 <= ap_CS_fsm(20);
ap_CS_fsm_state22 <= ap_CS_fsm(21);
ap_CS_fsm_state23 <= ap_CS_fsm(22);
ap_CS_fsm_state24 <= ap_CS_fsm(23);
ap_CS_fsm_state25 <= ap_CS_fsm(24);
ap_CS_fsm_state26 <= ap_CS_fsm(25);
ap_CS_fsm_state27 <= ap_CS_fsm(26);
ap_CS_fsm_state28 <= ap_CS_fsm(27);
ap_CS_fsm_state29 <= ap_CS_fsm(28);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state30 <= ap_CS_fsm(29);
ap_CS_fsm_state31 <= ap_CS_fsm(30);
ap_CS_fsm_state32 <= ap_CS_fsm(31);
ap_CS_fsm_state33 <= ap_CS_fsm(32);
ap_CS_fsm_state34 <= ap_CS_fsm(33);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state9 <= ap_CS_fsm(8);
ap_done_assign_proc : process(d_o_full_n, ap_CS_fsm_state34)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state34) and (d_o_full_n = ap_const_logic_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(d_o_full_n, ap_CS_fsm_state34)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state34) and (d_o_full_n = ap_const_logic_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
d_i_address0_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state16)) then
d_i_address0 <= ap_const_lv32_1E(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state15)) then
d_i_address0 <= ap_const_lv32_1C(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state14)) then
d_i_address0 <= ap_const_lv32_1A(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then
d_i_address0 <= ap_const_lv32_18(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state12)) then
d_i_address0 <= ap_const_lv32_16(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
d_i_address0 <= ap_const_lv32_14(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
d_i_address0 <= ap_const_lv32_12(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
d_i_address0 <= ap_const_lv32_10(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_i_address0 <= ap_const_lv32_E(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_i_address0 <= ap_const_lv32_C(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_i_address0 <= ap_const_lv32_A(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_i_address0 <= ap_const_lv32_8(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
d_i_address0 <= ap_const_lv32_6(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_i_address0 <= ap_const_lv32_4(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
d_i_address0 <= ap_const_lv32_2(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state1)) then
d_i_address0 <= ap_const_lv32_0(5 - 1 downto 0);
else
d_i_address0 <= "XXXXX";
end if;
end process;
d_i_address1_assign_proc : process(ap_CS_fsm_state1, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state16)) then
d_i_address1 <= ap_const_lv32_1F(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state15)) then
d_i_address1 <= ap_const_lv32_1D(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state14)) then
d_i_address1 <= ap_const_lv32_1B(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then
d_i_address1 <= ap_const_lv32_19(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state12)) then
d_i_address1 <= ap_const_lv32_17(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
d_i_address1 <= ap_const_lv32_15(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
d_i_address1 <= ap_const_lv32_13(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
d_i_address1 <= ap_const_lv32_11(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_i_address1 <= ap_const_lv32_F(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_i_address1 <= ap_const_lv32_D(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_i_address1 <= ap_const_lv32_B(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_i_address1 <= ap_const_lv32_9(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
d_i_address1 <= ap_const_lv32_7(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_i_address1 <= ap_const_lv32_5(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
d_i_address1 <= ap_const_lv32_3(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state1)) then
d_i_address1 <= ap_const_lv32_1(5 - 1 downto 0);
else
d_i_address1 <= "XXXXX";
end if;
end process;
d_i_ce0_assign_proc : process(ap_start, ap_CS_fsm_state1, d_o_full_n, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or ((ap_const_logic_1 = ap_CS_fsm_state16) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state3) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state6) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state15) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state4) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state5) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state7) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state8) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state9) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state10) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state11) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state12) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state13) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state14) and (d_o_full_n = ap_const_logic_1)))) then
d_i_ce0 <= ap_const_logic_1;
else
d_i_ce0 <= ap_const_logic_0;
end if;
end process;
d_i_ce1_assign_proc : process(ap_start, ap_CS_fsm_state1, d_o_full_n, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or ((ap_const_logic_1 = ap_CS_fsm_state16) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state3) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state6) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state15) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state4) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state5) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state7) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state8) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state9) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state10) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state11) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state12) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state13) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state14) and (d_o_full_n = ap_const_logic_1)))) then
d_i_ce1 <= ap_const_logic_1;
else
d_i_ce1 <= ap_const_logic_0;
end if;
end process;
d_o_blk_n_assign_proc : process(d_o_full_n, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state17, ap_CS_fsm_state18, ap_CS_fsm_state19, ap_CS_fsm_state20, ap_CS_fsm_state21, ap_CS_fsm_state22, ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32, ap_CS_fsm_state33, ap_CS_fsm_state34)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) or (ap_const_logic_1 = ap_CS_fsm_state4) or (ap_const_logic_1 = ap_CS_fsm_state5) or (ap_const_logic_1 = ap_CS_fsm_state6) or (ap_const_logic_1 = ap_CS_fsm_state7) or (ap_const_logic_1 = ap_CS_fsm_state8) or (ap_const_logic_1 = ap_CS_fsm_state9) or (ap_const_logic_1 = ap_CS_fsm_state10) or (ap_const_logic_1 = ap_CS_fsm_state11) or (ap_const_logic_1 = ap_CS_fsm_state12) or (ap_const_logic_1 = ap_CS_fsm_state13) or (ap_const_logic_1 = ap_CS_fsm_state14) or (ap_const_logic_1 = ap_CS_fsm_state15) or (ap_const_logic_1 = ap_CS_fsm_state16) or (ap_const_logic_1 = ap_CS_fsm_state17) or (ap_const_logic_1 = ap_CS_fsm_state18) or (ap_const_logic_1 = ap_CS_fsm_state19) or (ap_const_logic_1 = ap_CS_fsm_state20) or (ap_const_logic_1 = ap_CS_fsm_state21) or (ap_const_logic_1 = ap_CS_fsm_state22) or (ap_const_logic_1 = ap_CS_fsm_state23) or (ap_const_logic_1 = ap_CS_fsm_state24) or (ap_const_logic_1 = ap_CS_fsm_state25) or (ap_const_logic_1 = ap_CS_fsm_state26) or (ap_const_logic_1 = ap_CS_fsm_state27) or (ap_const_logic_1 = ap_CS_fsm_state28) or (ap_const_logic_1 = ap_CS_fsm_state29) or (ap_const_logic_1 = ap_CS_fsm_state30) or (ap_const_logic_1 = ap_CS_fsm_state31) or (ap_const_logic_1 = ap_CS_fsm_state32) or (ap_const_logic_1 = ap_CS_fsm_state33) or (ap_const_logic_1 = ap_CS_fsm_state34))) then
d_o_blk_n <= d_o_full_n;
else
d_o_blk_n <= ap_const_logic_1;
end if;
end process;
d_o_din_assign_proc : process(d_o_full_n, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state17, ap_CS_fsm_state18, ap_CS_fsm_state19, ap_CS_fsm_state20, ap_CS_fsm_state21, ap_CS_fsm_state22, ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32, ap_CS_fsm_state33, ap_CS_fsm_state34, tmp_8_fu_438_p2, tmp_1_1_fu_453_p2, tmp_1_2_fu_468_p2, tmp_1_3_fu_483_p2, tmp_1_4_fu_498_p2, tmp_1_5_fu_512_p2, tmp_1_6_fu_526_p2, tmp_1_7_fu_540_p2, tmp_1_8_fu_546_p2, tmp_1_9_fu_552_p2, tmp_1_s_fu_558_p2, tmp_1_10_fu_563_p2, tmp_1_11_fu_576_p2, tmp_1_15_reg_1420, tmp_1_16_reg_1426, tmp_1_12_fu_647_p2, tmp_1_17_reg_1457, tmp_1_18_reg_1463, tmp_1_13_fu_760_p2, tmp_1_19_reg_1494, tmp_1_20_reg_1500, tmp_1_21_reg_1516, tmp_1_22_reg_1522, tmp_1_23_reg_1538, tmp_1_24_reg_1543, tmp_1_25_reg_1548, tmp_1_26_reg_1553, tmp_1_27_reg_1558, tmp_1_28_reg_1563, tmp_1_29_reg_1568, tmp_1_30_reg_1573, tmp_1_14_fu_871_p2)
begin
if ((d_o_full_n = ap_const_logic_1)) then
if ((ap_const_logic_1 = ap_CS_fsm_state34)) then
d_o_din <= tmp_1_30_reg_1573;
elsif ((ap_const_logic_1 = ap_CS_fsm_state33)) then
d_o_din <= tmp_1_29_reg_1568;
elsif ((ap_const_logic_1 = ap_CS_fsm_state32)) then
d_o_din <= tmp_1_28_reg_1563;
elsif ((ap_const_logic_1 = ap_CS_fsm_state31)) then
d_o_din <= tmp_1_27_reg_1558;
elsif ((ap_const_logic_1 = ap_CS_fsm_state30)) then
d_o_din <= tmp_1_26_reg_1553;
elsif ((ap_const_logic_1 = ap_CS_fsm_state29)) then
d_o_din <= tmp_1_25_reg_1548;
elsif ((ap_const_logic_1 = ap_CS_fsm_state28)) then
d_o_din <= tmp_1_24_reg_1543;
elsif ((ap_const_logic_1 = ap_CS_fsm_state27)) then
d_o_din <= tmp_1_23_reg_1538;
elsif ((ap_const_logic_1 = ap_CS_fsm_state26)) then
d_o_din <= tmp_1_22_reg_1522;
elsif ((ap_const_logic_1 = ap_CS_fsm_state25)) then
d_o_din <= tmp_1_21_reg_1516;
elsif ((ap_const_logic_1 = ap_CS_fsm_state24)) then
d_o_din <= tmp_1_20_reg_1500;
elsif ((ap_const_logic_1 = ap_CS_fsm_state23)) then
d_o_din <= tmp_1_19_reg_1494;
elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then
d_o_din <= tmp_1_18_reg_1463;
elsif ((ap_const_logic_1 = ap_CS_fsm_state21)) then
d_o_din <= tmp_1_17_reg_1457;
elsif ((ap_const_logic_1 = ap_CS_fsm_state20)) then
d_o_din <= tmp_1_16_reg_1426;
elsif ((ap_const_logic_1 = ap_CS_fsm_state19)) then
d_o_din <= tmp_1_15_reg_1420;
elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then
d_o_din <= tmp_1_14_fu_871_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state17)) then
d_o_din <= tmp_1_13_fu_760_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state16)) then
d_o_din <= tmp_1_12_fu_647_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state15)) then
d_o_din <= tmp_1_11_fu_576_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state14)) then
d_o_din <= tmp_1_10_fu_563_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then
d_o_din <= tmp_1_s_fu_558_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state12)) then
d_o_din <= tmp_1_9_fu_552_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then
d_o_din <= tmp_1_8_fu_546_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
d_o_din <= tmp_1_7_fu_540_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then
d_o_din <= tmp_1_6_fu_526_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
d_o_din <= tmp_1_5_fu_512_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
d_o_din <= tmp_1_4_fu_498_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
d_o_din <= tmp_1_3_fu_483_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state5)) then
d_o_din <= tmp_1_2_fu_468_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
d_o_din <= tmp_1_1_fu_453_p2;
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
d_o_din <= tmp_8_fu_438_p2;
else
d_o_din <= "XXXXXXXXXXXXXXXX";
end if;
else
d_o_din <= "XXXXXXXXXXXXXXXX";
end if;
end process;
d_o_write_assign_proc : process(d_o_full_n, ap_CS_fsm_state3, ap_CS_fsm_state4, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, ap_CS_fsm_state8, ap_CS_fsm_state9, ap_CS_fsm_state10, ap_CS_fsm_state11, ap_CS_fsm_state12, ap_CS_fsm_state13, ap_CS_fsm_state14, ap_CS_fsm_state15, ap_CS_fsm_state16, ap_CS_fsm_state17, ap_CS_fsm_state18, ap_CS_fsm_state19, ap_CS_fsm_state20, ap_CS_fsm_state21, ap_CS_fsm_state22, ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32, ap_CS_fsm_state33, ap_CS_fsm_state34)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state16) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state3) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state17) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state6) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state15) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state4) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state5) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state7) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state8) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state9) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state10) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state11) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state12) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state13) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state14) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state18) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state19) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state20) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state21) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state22) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state23) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state24) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state25) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state26) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state27) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state28) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state29) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state30) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state31) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state32) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state33) and (d_o_full_n = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_state34) and (d_o_full_n = ap_const_logic_1)))) then
d_o_write <= ap_const_logic_1;
else
d_o_write <= ap_const_logic_0;
end if;
end process;
temp_1_fu_694_p2 <= std_logic_vector(signed(tmp5_cast_fu_691_p1) + signed(tmp4_fu_686_p2));
temp_2_fu_787_p2 <= std_logic_vector(signed(tmp8_cast_fu_784_p1) + signed(tmp7_fu_779_p2));
temp_3_fu_807_p2 <= std_logic_vector(signed(tmp11_cast_fu_804_p1) + signed(tmp10_fu_799_p2));
temp_4_fu_899_p2 <= std_logic_vector(signed(tmp14_cast_fu_896_p1) + signed(tmp13_fu_891_p2));
temp_5_fu_919_p2 <= std_logic_vector(signed(tmp17_cast_fu_916_p1) + signed(tmp16_fu_911_p2));
temp_6_fu_989_p2 <= std_logic_vector(signed(tmp20_cast_fu_986_p1) + signed(tmp19_fu_981_p2));
temp_7_fu_1009_p2 <= std_logic_vector(signed(tmp23_cast_fu_1006_p1) + signed(tmp22_fu_1001_p2));
temp_s_fu_674_p2 <= std_logic_vector(signed(tmp2_cast_fu_671_p1) + signed(tmp1_fu_666_p2));
tmp10_fu_799_p2 <= std_logic_vector(unsigned(acc_3) + unsigned(tmp_3_fu_750_p1));
tmp11_cast_fu_804_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp11_reg_1474),32));
tmp11_fu_740_p2 <= std_logic_vector(signed(tmp12_cast_fu_736_p1) + signed(tmp_11_cast_fu_644_p1));
tmp12_cast_fu_736_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp12_fu_730_p2),18));
tmp12_fu_730_p2 <= std_logic_vector(signed(tmp_19_cast_fu_659_p1) + signed(tmp_27_cast_fu_726_p1));
tmp13_fu_891_p2 <= std_logic_vector(unsigned(acc_4) + unsigned(tmp_4_fu_859_p1));
tmp14_cast_fu_896_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp14_reg_1506),32));
tmp14_fu_833_p2 <= std_logic_vector(signed(tmp15_cast_fu_829_p1) + signed(tmp_12_cast_fu_754_p1));
tmp15_cast_fu_829_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp15_fu_823_p2),18));
tmp15_fu_823_p2 <= std_logic_vector(signed(tmp_20_cast_fu_765_p1) + signed(tmp_28_cast_fu_819_p1));
tmp16_fu_911_p2 <= std_logic_vector(unsigned(acc_5) + unsigned(tmp_5_fu_862_p1));
tmp17_cast_fu_916_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp17_reg_1511),32));
tmp17_fu_853_p2 <= std_logic_vector(signed(tmp18_cast_fu_849_p1) + signed(tmp_13_cast_fu_757_p1));
tmp18_cast_fu_849_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp18_fu_843_p2),18));
tmp18_fu_843_p2 <= std_logic_vector(signed(tmp_21_cast_fu_772_p1) + signed(tmp_29_cast_fu_839_p1));
tmp19_fu_981_p2 <= std_logic_vector(unsigned(acc_6) + unsigned(tmp_6_fu_971_p1));
tmp1_fu_666_p2 <= std_logic_vector(unsigned(acc_0) + unsigned(tmp_fu_633_p1));
tmp20_cast_fu_986_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp20_reg_1528),32));
tmp20_fu_945_p2 <= std_logic_vector(signed(tmp21_cast_fu_941_p1) + signed(tmp_14_cast_fu_865_p1));
tmp21_cast_fu_941_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp21_fu_935_p2),18));
tmp21_fu_935_p2 <= std_logic_vector(signed(tmp_22_cast_fu_876_p1) + signed(tmp_30_cast_fu_931_p1));
tmp22_fu_1001_p2 <= std_logic_vector(unsigned(acc_7) + unsigned(tmp_7_fu_974_p1));
tmp23_cast_fu_1006_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp23_reg_1533),32));
tmp23_fu_965_p2 <= std_logic_vector(signed(tmp24_cast_fu_961_p1) + signed(tmp_15_cast_fu_868_p1));
tmp24_cast_fu_961_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp24_fu_955_p2),18));
tmp24_fu_955_p2 <= std_logic_vector(signed(tmp_23_cast_fu_883_p1) + signed(tmp_31_cast_fu_951_p1));
tmp2_cast_fu_671_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp2_reg_1432),32));
tmp2_fu_608_p2 <= std_logic_vector(signed(tmp3_cast_fu_604_p1) + signed(tmp_8_cast_fu_568_p1));
tmp3_cast_fu_604_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp3_fu_598_p2),18));
tmp3_fu_598_p2 <= std_logic_vector(signed(tmp_16_cast_fu_581_p1) + signed(tmp_24_cast_fu_595_p1));
tmp4_fu_686_p2 <= std_logic_vector(unsigned(acc_1) + unsigned(tmp_s_fu_637_p1));
tmp5_cast_fu_691_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp5_reg_1437),32));
tmp5_fu_627_p2 <= std_logic_vector(signed(tmp6_cast_fu_623_p1) + signed(tmp_9_cast_fu_572_p1));
tmp6_cast_fu_623_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp6_fu_617_p2),18));
tmp6_fu_617_p2 <= std_logic_vector(signed(tmp_17_cast_fu_588_p1) + signed(tmp_25_cast_fu_614_p1));
tmp7_fu_779_p2 <= std_logic_vector(unsigned(acc_2) + unsigned(tmp_2_fu_746_p1));
tmp8_cast_fu_784_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp8_reg_1469),32));
tmp8_fu_720_p2 <= std_logic_vector(signed(tmp9_cast_fu_716_p1) + signed(tmp_10_cast_fu_641_p1));
tmp9_cast_fu_716_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp9_fu_710_p2),18));
tmp9_fu_710_p2 <= std_logic_vector(signed(tmp_18_cast_fu_652_p1) + signed(tmp_26_cast_fu_706_p1));
tmp_10_cast_fu_641_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_10_reg_1189),18));
tmp_10_fu_464_p1 <= acc_2(16 - 1 downto 0);
tmp_11_cast_fu_644_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_11_reg_1195),18));
tmp_11_fu_479_p1 <= acc_3(16 - 1 downto 0);
tmp_12_cast_fu_754_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_12_reg_1221),18));
tmp_12_fu_494_p1 <= acc_4(16 - 1 downto 0);
tmp_13_cast_fu_757_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_13_reg_1227),18));
tmp_13_fu_508_p1 <= acc_5(16 - 1 downto 0);
tmp_14_cast_fu_865_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_14_reg_1253),18));
tmp_14_fu_522_p1 <= acc_6(16 - 1 downto 0);
tmp_15_cast_fu_868_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_15_reg_1259),18));
tmp_15_fu_536_p1 <= acc_7(16 - 1 downto 0);
tmp_16_cast_fu_581_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_16_reg_1285),17));
tmp_17_cast_fu_588_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_17_reg_1291),17));
tmp_18_cast_fu_652_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_18_reg_1312),17));
tmp_19_cast_fu_659_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_19_reg_1318),17));
tmp_1_10_fu_563_p2 <= std_logic_vector(unsigned(d_i_load_11_reg_1195) + unsigned(tmp_1_3_reg_1164));
tmp_1_11_fu_576_p2 <= std_logic_vector(unsigned(d_i_load_12_reg_1221) + unsigned(tmp_1_4_reg_1184));
tmp_1_12_fu_647_p2 <= std_logic_vector(unsigned(d_i_load_13_reg_1227) + unsigned(tmp_1_5_reg_1216));
tmp_1_13_fu_760_p2 <= std_logic_vector(unsigned(d_i_load_14_reg_1253) + unsigned(tmp_1_6_reg_1248));
tmp_1_14_fu_871_p2 <= std_logic_vector(unsigned(d_i_load_15_reg_1259) + unsigned(tmp_1_7_reg_1280));
tmp_1_15_fu_584_p2 <= std_logic_vector(unsigned(d_i_load_16_reg_1285) + unsigned(tmp_1_8_reg_1307));
tmp_1_16_fu_591_p2 <= std_logic_vector(unsigned(d_i_load_17_reg_1291) + unsigned(tmp_1_9_reg_1334));
tmp_1_17_fu_655_p2 <= std_logic_vector(unsigned(d_i_load_18_reg_1312) + unsigned(tmp_1_s_reg_1361));
tmp_1_18_fu_662_p2 <= std_logic_vector(unsigned(d_i_load_19_reg_1318) + unsigned(tmp_1_10_reg_1388));
tmp_1_19_fu_768_p2 <= std_logic_vector(unsigned(d_i_load_20_reg_1339) + unsigned(tmp_1_11_reg_1415));
tmp_1_1_fu_453_p2 <= std_logic_vector(unsigned(reg_410) + unsigned(tmp_9_fu_449_p1));
tmp_1_20_fu_775_p2 <= std_logic_vector(unsigned(d_i_load_21_reg_1345) + unsigned(tmp_1_12_reg_1452));
tmp_1_21_fu_879_p2 <= std_logic_vector(unsigned(d_i_load_22_reg_1366) + unsigned(tmp_1_13_reg_1489));
tmp_1_22_fu_886_p2 <= std_logic_vector(unsigned(d_i_load_23_reg_1372) + unsigned(tmp_1_14_fu_871_p2));
tmp_1_23_fu_977_p2 <= std_logic_vector(unsigned(d_i_load_24_reg_1393) + unsigned(tmp_1_15_reg_1420));
tmp_1_24_fu_1021_p2 <= std_logic_vector(unsigned(d_i_load_25_reg_1399) + unsigned(tmp_1_16_reg_1426));
tmp_1_25_fu_1025_p2 <= std_logic_vector(unsigned(reg_422) + unsigned(tmp_1_17_reg_1457));
tmp_1_26_fu_1030_p2 <= std_logic_vector(unsigned(reg_426) + unsigned(tmp_1_18_reg_1463));
tmp_1_27_fu_1035_p2 <= std_logic_vector(unsigned(reg_406) + unsigned(tmp_1_19_reg_1494));
tmp_1_28_fu_1040_p2 <= std_logic_vector(unsigned(reg_410) + unsigned(tmp_1_20_reg_1500));
tmp_1_29_fu_1045_p2 <= std_logic_vector(unsigned(reg_414) + unsigned(tmp_1_21_reg_1516));
tmp_1_2_fu_468_p2 <= std_logic_vector(unsigned(reg_414) + unsigned(tmp_10_fu_464_p1));
tmp_1_30_fu_1050_p2 <= std_logic_vector(unsigned(reg_418) + unsigned(tmp_1_22_reg_1522));
tmp_1_3_fu_483_p2 <= std_logic_vector(unsigned(reg_418) + unsigned(tmp_11_fu_479_p1));
tmp_1_4_fu_498_p2 <= std_logic_vector(unsigned(d_i_load_4_reg_1105) + unsigned(tmp_12_fu_494_p1));
tmp_1_5_fu_512_p2 <= std_logic_vector(unsigned(d_i_load_5_reg_1111) + unsigned(tmp_13_fu_508_p1));
tmp_1_6_fu_526_p2 <= std_logic_vector(unsigned(d_i_load_6_reg_1137) + unsigned(tmp_14_fu_522_p1));
tmp_1_7_fu_540_p2 <= std_logic_vector(unsigned(d_i_load_7_reg_1143) + unsigned(tmp_15_fu_536_p1));
tmp_1_8_fu_546_p2 <= std_logic_vector(unsigned(reg_422) + unsigned(tmp_8_reg_1080));
tmp_1_9_fu_552_p2 <= std_logic_vector(unsigned(reg_426) + unsigned(tmp_1_1_reg_1100));
tmp_1_fu_434_p1 <= acc_0(16 - 1 downto 0);
tmp_1_s_fu_558_p2 <= std_logic_vector(unsigned(d_i_load_10_reg_1189) + unsigned(tmp_1_2_reg_1132));
tmp_20_cast_fu_765_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_20_reg_1339),17));
tmp_21_cast_fu_772_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_21_reg_1345),17));
tmp_22_cast_fu_876_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_22_reg_1366),17));
tmp_23_cast_fu_883_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_23_reg_1372),17));
tmp_24_cast_fu_595_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_24_reg_1393),17));
tmp_25_cast_fu_614_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_25_reg_1399),17));
tmp_26_cast_fu_706_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_422),17));
tmp_27_cast_fu_726_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_426),17));
tmp_28_cast_fu_819_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_406),17));
tmp_29_cast_fu_839_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_410),17));
tmp_2_fu_746_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_414),32));
tmp_30_cast_fu_931_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_414),17));
tmp_31_cast_fu_951_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_418),17));
tmp_3_fu_750_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_418),32));
tmp_4_fu_859_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_4_reg_1105),32));
tmp_5_fu_862_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_5_reg_1111),32));
tmp_6_fu_971_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_6_reg_1137),32));
tmp_7_fu_974_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_load_7_reg_1143),32));
tmp_8_cast_fu_568_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_422),18));
tmp_8_fu_438_p2 <= std_logic_vector(unsigned(reg_406) + unsigned(tmp_1_fu_434_p1));
tmp_9_cast_fu_572_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_426),18));
tmp_9_fu_449_p1 <= acc_1(16 - 1 downto 0);
tmp_fu_633_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_406),32));
tmp_s_fu_637_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_410),32));
end behav;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Multisalida is
Port (
aa: in std_logic;
bb: in std_logic;
cc: in std_logic;
dd: in std_logic;
s1: out std_logic;
s2: out std_logic;
s3: out std_logic
);
end Multisalida;
architecture behavioral of Multisalida is
begin
s1<='0'
s2<='1'
s3<=((aa and dd) or (aa and bb) or (bb and dd) or (not(aa) and cc and not(dd)) or (not(aa) and not(bb) and not(cc)))
end behavioral;
|
---------------------------------------------------------------------------
-- NES-Controller Module
---------------------------------------------------------------------------
-- This file is a part of "Aeon Lite" project
-- Dmitriy Schapotschkin aka ILoveSpeccy '2014
-- [email protected]
-- Project homepage: www.speccyland.net
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
------------------
-- Bit - Button --
-- (1 = pressed)
------------------
-- 7 A
-- 6 B
-- 5 Select
-- 4 Start
-- 3 Up
-- 2 Down
-- 1 Left
-- 0 Right
------------------
entity nes_gamepad is
generic (
CLK_FREQ : integer := 25000000;
TICK_FREQ : integer := 20000 );
port (
CLK : in std_logic;
RESET : in std_logic;
JOY_CLK : out std_logic;
JOY_LOAD : out std_logic;
JOY_DATA0 : in std_logic;
JOY_DATA1 : in std_logic;
JOY0_BUTTONS : out std_logic_vector(7 downto 0);
JOY1_BUTTONS : out std_logic_vector(7 downto 0);
JOY0_CONNECTED : out std_logic; -- 1 when gamepad connected
JOY1_CONNECTED : out std_logic );
end nes_gamepad;
architecture RTL of nes_gamepad is
signal TICK : integer range 0 to (CLK_FREQ / TICK_FREQ);
signal STATE : integer range 0 to 17;
signal DATA0 : std_logic_vector(7 downto 0);
signal DATA1 : std_logic_vector(7 downto 0);
begin
process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
STATE <= 0;
JOY_CLK <= '0';
JOY_LOAD <= '0';
TICK <= 0;
JOY0_BUTTONS <= "00000000";
JOY0_BUTTONS <= "00000000";
JOY0_CONNECTED <= '0';
JOY1_CONNECTED <= '0';
else
TICK <= TICK + 1;
if TICK = (CLK_FREQ / TICK_FREQ) then
TICK <= 0;
STATE <= STATE + 1;
case STATE is
when 0 =>
JOY_LOAD <= '1';
when 1 =>
JOY_LOAD <= '0';
DATA0(7) <= JOY_DATA0;
DATA1(7) <= JOY_DATA1;
when 2 | 4 | 6 | 8 | 10 | 12 | 14 | 16 =>
JOY_CLK <= '1';
when 3 =>
JOY_CLK <= '0';
DATA0(6) <= JOY_DATA0;
DATA1(6) <= JOY_DATA1;
when 5 =>
JOY_CLK <= '0';
DATA0(5) <= JOY_DATA0;
DATA1(5) <= JOY_DATA1;
when 7 =>
JOY_CLK <= '0';
DATA0(4) <= JOY_DATA0;
DATA1(4) <= JOY_DATA1;
when 9 =>
JOY_CLK <= '0';
DATA0(3) <= JOY_DATA0;
DATA1(3) <= JOY_DATA1;
when 11 =>
JOY_CLK <= '0';
DATA0(2) <= JOY_DATA0;
DATA1(2) <= JOY_DATA1;
when 13 =>
JOY_CLK <= '0';
DATA0(1) <= JOY_DATA0;
DATA1(1) <= JOY_DATA1;
when 15 =>
JOY_CLK <= '0';
DATA0(0) <= JOY_DATA0;
DATA1(0) <= JOY_DATA1;
when 17 =>
JOY_CLK <= '0';
JOY0_BUTTONS <= "00000000";
JOY1_BUTTONS <= "00000000";
JOY0_CONNECTED <= '0';
JOY1_CONNECTED <= '0';
STATE <= 0;
if DATA0 /= "00000000" then -- gamepad connected
JOY0_BUTTONS <= not DATA0;
JOY0_CONNECTED <= '1';
end if;
if DATA1 /= "00000000" then -- gamepad connected
JOY1_BUTTONS <= not DATA1;
JOY1_CONNECTED <= '1';
end if;
when OTHERS =>
NULL;
end case;
end if;
end if;
end if;
end process;
end RTL;
|
---------------------------------------------------------------------------
-- NES-Controller Module
---------------------------------------------------------------------------
-- This file is a part of "Aeon Lite" project
-- Dmitriy Schapotschkin aka ILoveSpeccy '2014
-- [email protected]
-- Project homepage: www.speccyland.net
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
------------------
-- Bit - Button --
-- (1 = pressed)
------------------
-- 7 A
-- 6 B
-- 5 Select
-- 4 Start
-- 3 Up
-- 2 Down
-- 1 Left
-- 0 Right
------------------
entity nes_gamepad is
generic (
CLK_FREQ : integer := 25000000;
TICK_FREQ : integer := 20000 );
port (
CLK : in std_logic;
RESET : in std_logic;
JOY_CLK : out std_logic;
JOY_LOAD : out std_logic;
JOY_DATA0 : in std_logic;
JOY_DATA1 : in std_logic;
JOY0_BUTTONS : out std_logic_vector(7 downto 0);
JOY1_BUTTONS : out std_logic_vector(7 downto 0);
JOY0_CONNECTED : out std_logic; -- 1 when gamepad connected
JOY1_CONNECTED : out std_logic );
end nes_gamepad;
architecture RTL of nes_gamepad is
signal TICK : integer range 0 to (CLK_FREQ / TICK_FREQ);
signal STATE : integer range 0 to 17;
signal DATA0 : std_logic_vector(7 downto 0);
signal DATA1 : std_logic_vector(7 downto 0);
begin
process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
STATE <= 0;
JOY_CLK <= '0';
JOY_LOAD <= '0';
TICK <= 0;
JOY0_BUTTONS <= "00000000";
JOY0_BUTTONS <= "00000000";
JOY0_CONNECTED <= '0';
JOY1_CONNECTED <= '0';
else
TICK <= TICK + 1;
if TICK = (CLK_FREQ / TICK_FREQ) then
TICK <= 0;
STATE <= STATE + 1;
case STATE is
when 0 =>
JOY_LOAD <= '1';
when 1 =>
JOY_LOAD <= '0';
DATA0(7) <= JOY_DATA0;
DATA1(7) <= JOY_DATA1;
when 2 | 4 | 6 | 8 | 10 | 12 | 14 | 16 =>
JOY_CLK <= '1';
when 3 =>
JOY_CLK <= '0';
DATA0(6) <= JOY_DATA0;
DATA1(6) <= JOY_DATA1;
when 5 =>
JOY_CLK <= '0';
DATA0(5) <= JOY_DATA0;
DATA1(5) <= JOY_DATA1;
when 7 =>
JOY_CLK <= '0';
DATA0(4) <= JOY_DATA0;
DATA1(4) <= JOY_DATA1;
when 9 =>
JOY_CLK <= '0';
DATA0(3) <= JOY_DATA0;
DATA1(3) <= JOY_DATA1;
when 11 =>
JOY_CLK <= '0';
DATA0(2) <= JOY_DATA0;
DATA1(2) <= JOY_DATA1;
when 13 =>
JOY_CLK <= '0';
DATA0(1) <= JOY_DATA0;
DATA1(1) <= JOY_DATA1;
when 15 =>
JOY_CLK <= '0';
DATA0(0) <= JOY_DATA0;
DATA1(0) <= JOY_DATA1;
when 17 =>
JOY_CLK <= '0';
JOY0_BUTTONS <= "00000000";
JOY1_BUTTONS <= "00000000";
JOY0_CONNECTED <= '0';
JOY1_CONNECTED <= '0';
STATE <= 0;
if DATA0 /= "00000000" then -- gamepad connected
JOY0_BUTTONS <= not DATA0;
JOY0_CONNECTED <= '1';
end if;
if DATA1 /= "00000000" then -- gamepad connected
JOY1_BUTTONS <= not DATA1;
JOY1_CONNECTED <= '1';
end if;
when OTHERS =>
NULL;
end case;
end if;
end if;
end if;
end process;
end RTL;
|
entity call1 is
end;
use work.pkg.all;
architecture behav of call1 is
function func return rec is
variable res : rec_4;
begin
return res;
end func;
begin
process
variable v : rec_4 := func;
begin
wait;
end process;
end behav;
|
entity call1 is
end;
use work.pkg.all;
architecture behav of call1 is
function func return rec is
variable res : rec_4;
begin
return res;
end func;
begin
process
variable v : rec_4 := func;
begin
wait;
end process;
end behav;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Mar 5 07:51:26 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-conf-c.vhd,v 1.1 2007/03/05 08:59:00 wig Exp $
-- $Date: 2007/03/05 08:59:00 $
-- $Log: inst_t_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2007/03/05 08:59:00 wig
-- Upgraded testcases
-- case/force still not fully operational (internal names keep case).
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_t_e_rtl_conf / inst_t_e
--
configuration inst_t_e_rtl_conf of inst_t_e is
for rtl
-- Generated Configuration
for inst_a : inst_A_e
use configuration work.inst_A_e_rtl_conf;
end for;
for inst_b : inst_b_e
use configuration work.inst_b_e_rtl_conf;
end for;
end for;
end inst_t_e_rtl_conf;
--
-- End of Generated Configuration inst_t_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:43:54 12/25/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs2/tb_roundcounter.vhd
-- Project Name: idea_rcs2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: roundcounter
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_roundcounter IS
END tb_roundcounter;
ARCHITECTURE behavior OF tb_roundcounter IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT roundcounter
PORT(
Start : IN std_logic;
Clock : IN std_logic;
Ready : OUT std_logic;
S_i : OUT std_logic;
Result : IN std_logic;
Round : OUT std_logic;
Init : OUT std_logic;
Trafo : OUT std_logic
);
END COMPONENT;
--Inputs
signal Start : std_logic := '0';
signal Clock : std_logic := '0';
signal Result : std_logic := '0';
--Outputs
signal Ready : std_logic;
signal S_i : std_logic;
signal Round : std_logic;
signal Init : std_logic;
signal Trafo : std_logic;
-- Clock period definitions
constant Clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: roundcounter PORT MAP (
Start => Start,
Clock => Clock,
Ready => Ready,
S_i => S_i,
Result => Result,
Round => Round,
Init => Init,
Trafo => Trafo
);
-- Clock process definitions
Clock_process :process
begin
Clock <= '0';
wait for Clock_period/2;
Clock <= '1';
wait for Clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clock_period*10;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:43:54 12/25/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs2/tb_roundcounter.vhd
-- Project Name: idea_rcs2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: roundcounter
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_roundcounter IS
END tb_roundcounter;
ARCHITECTURE behavior OF tb_roundcounter IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT roundcounter
PORT(
Start : IN std_logic;
Clock : IN std_logic;
Ready : OUT std_logic;
S_i : OUT std_logic;
Result : IN std_logic;
Round : OUT std_logic;
Init : OUT std_logic;
Trafo : OUT std_logic
);
END COMPONENT;
--Inputs
signal Start : std_logic := '0';
signal Clock : std_logic := '0';
signal Result : std_logic := '0';
--Outputs
signal Ready : std_logic;
signal S_i : std_logic;
signal Round : std_logic;
signal Init : std_logic;
signal Trafo : std_logic;
-- Clock period definitions
constant Clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: roundcounter PORT MAP (
Start => Start,
Clock => Clock,
Ready => Ready,
S_i => S_i,
Result => Result,
Round => Round,
Init => Init,
Trafo => Trafo
);
-- Clock process definitions
Clock_process :process
begin
Clock <= '0';
wait for Clock_period/2;
Clock <= '1';
wait for Clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clock_period*10;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:06 08/14/2014
-- Design Name:
-- Module Name: C:/Xilinx/14.7/workspace/prac3/test_bcd_1_adder.vhd
-- Project Name: prac3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: bcd_1_adder
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY test_bcd_1_adder IS
END test_bcd_1_adder;
ARCHITECTURE behavior OF test_bcd_1_adder IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bcd_1_adder
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
C_IN : IN std_logic;
SUM : OUT std_logic_vector(3 downto 0);
C_OUT : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal C_IN : std_logic := '0';
--Outputs
signal SUM : std_logic_vector(3 downto 0);
signal C_OUT : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bcd_1_adder PORT MAP (
A => A,
B => B,
C_IN => C_IN,
SUM => SUM,
C_OUT => C_OUT
);
-- Stimulus process
stim_proc: process begin
A <= (others => '0');
B <= (others => '0');
C_IN <= '0';
wait for 10ps;
for I in 0 to 7 loop
wait for 1ps;
for J in 0 to 7 loop
wait for 1ps;
for K in 0 to 1 loop
wait for 1ps;
--Black Box testing
--0 input
if (A = "0000" and B = "0000" and C_IN = '0') then
assert (sum = "0000") report "bad gate - stuck at 0S0" severity error;
assert (C_OUT = '0') report "bad gate - stuck at 0C0" severity error;
elsif (A = "0000" and B = "0000" and C_IN = '1') then
assert (sum = "0001") report "bad gate - stuck at 0S1" severity error;
assert (C_OUT = '0') report "bad gate - stuck at 0C1" severity error;
--less than 9
elsif (A = "0100" and B = "0001" and C_IN = '0') then
assert (sum = "0101") report "bad gate - stuck at less than 9S0" severity error;
assert (C_OUT = '0') report "bad gate - stuck at less than 9C0" severity error;
elsif (A = "0100" and B = "0001" and C_IN = '1') then
assert (sum = "0110") report "bad gate - stuck at less than 9S1" severity error;
assert (C_OUT = '0') report "bad gate - stuck at less than 9C1" severity error;
--At 9
elsif (A = "0101" and B = "0100" and C_IN = '0') then
assert (sum = "1001") report "bad gate - stuck at 9S0" severity error;
assert (C_OUT = '0') report "bad gate - stuck at 9C0" severity error;
elsif (A = "0100" and B = "0100" and C_IN = '1') then
assert (sum = "1001") report "bad gate - stuck at 9S1" severity error;
assert (C_OUT = '0') report "bad gate - stuck at 9C1" severity error;
--More than 9
elsif (A = "0111" and B = "0100" and C_IN = '0') then
assert (sum = "0111") report "bad gate - stuck at more than 9S0" severity error;
assert (C_OUT = '1') report "bad gate - stuck at more than 9C0" severity error;
elsif (A = "0111" and B = "0100" and C_IN = '1') then
assert (sum = "0010") report "bad gate - stuck at more than 9S1" severity error;
assert (C_OUT = '1') report "bad gate - stuck at more than 9C1" severity error;
--More than 7 + 9
elsif (A = "0111" and B = "1001" and C_IN = '0') then
assert (sum = "0110") report "bad gate - stuck at 7S0" severity error;
assert (C_OUT = '1') report "bad gate - stuck at 7C0" severity error;
elsif (A = "0111" and B = "1001" and C_IN = '1') then
assert (sum = "0111") report "bad gate - stuck at 7S1" severity error;
assert (C_OUT = '1') report "bad gate - stuck at 7C1" severity error;
--More than 8 + 9
elsif (A = "1000" and B = "1001" and C_IN = '0') then
assert (sum = "0111") report "bad gate - stuck at 7S0" severity error;
assert (C_OUT = '1') report "bad gate - stuck at 7C0" severity error;
elsif (A = "1000" and B = "1001" and C_IN = '1') then
assert (sum = "1000") report "bad gate - stuck at 7S1" severity error;
assert (C_OUT = '1') report "bad gate - stuck at 7C1" severity error;
end if;
C_IN <= NOT(C_IN);
end loop;
B <= B + '1';
end loop;
A <= A + '1';
end loop;
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:06 08/14/2014
-- Design Name:
-- Module Name: C:/Xilinx/14.7/workspace/prac3/test_bcd_1_adder.vhd
-- Project Name: prac3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: bcd_1_adder
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY test_bcd_1_adder IS
END test_bcd_1_adder;
ARCHITECTURE behavior OF test_bcd_1_adder IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bcd_1_adder
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
C_IN : IN std_logic;
SUM : OUT std_logic_vector(3 downto 0);
C_OUT : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal C_IN : std_logic := '0';
--Outputs
signal SUM : std_logic_vector(3 downto 0);
signal C_OUT : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bcd_1_adder PORT MAP (
A => A,
B => B,
C_IN => C_IN,
SUM => SUM,
C_OUT => C_OUT
);
-- Stimulus process
stim_proc: process begin
A <= (others => '0');
B <= (others => '0');
C_IN <= '0';
wait for 10ps;
for I in 0 to 7 loop
wait for 1ps;
for J in 0 to 7 loop
wait for 1ps;
for K in 0 to 1 loop
wait for 1ps;
--Black Box testing
--0 input
if (A = "0000" and B = "0000" and C_IN = '0') then
assert (sum = "0000") report "bad gate - stuck at 0S0" severity error;
assert (C_OUT = '0') report "bad gate - stuck at 0C0" severity error;
elsif (A = "0000" and B = "0000" and C_IN = '1') then
assert (sum = "0001") report "bad gate - stuck at 0S1" severity error;
assert (C_OUT = '0') report "bad gate - stuck at 0C1" severity error;
--less than 9
elsif (A = "0100" and B = "0001" and C_IN = '0') then
assert (sum = "0101") report "bad gate - stuck at less than 9S0" severity error;
assert (C_OUT = '0') report "bad gate - stuck at less than 9C0" severity error;
elsif (A = "0100" and B = "0001" and C_IN = '1') then
assert (sum = "0110") report "bad gate - stuck at less than 9S1" severity error;
assert (C_OUT = '0') report "bad gate - stuck at less than 9C1" severity error;
--At 9
elsif (A = "0101" and B = "0100" and C_IN = '0') then
assert (sum = "1001") report "bad gate - stuck at 9S0" severity error;
assert (C_OUT = '0') report "bad gate - stuck at 9C0" severity error;
elsif (A = "0100" and B = "0100" and C_IN = '1') then
assert (sum = "1001") report "bad gate - stuck at 9S1" severity error;
assert (C_OUT = '0') report "bad gate - stuck at 9C1" severity error;
--More than 9
elsif (A = "0111" and B = "0100" and C_IN = '0') then
assert (sum = "0111") report "bad gate - stuck at more than 9S0" severity error;
assert (C_OUT = '1') report "bad gate - stuck at more than 9C0" severity error;
elsif (A = "0111" and B = "0100" and C_IN = '1') then
assert (sum = "0010") report "bad gate - stuck at more than 9S1" severity error;
assert (C_OUT = '1') report "bad gate - stuck at more than 9C1" severity error;
--More than 7 + 9
elsif (A = "0111" and B = "1001" and C_IN = '0') then
assert (sum = "0110") report "bad gate - stuck at 7S0" severity error;
assert (C_OUT = '1') report "bad gate - stuck at 7C0" severity error;
elsif (A = "0111" and B = "1001" and C_IN = '1') then
assert (sum = "0111") report "bad gate - stuck at 7S1" severity error;
assert (C_OUT = '1') report "bad gate - stuck at 7C1" severity error;
--More than 8 + 9
elsif (A = "1000" and B = "1001" and C_IN = '0') then
assert (sum = "0111") report "bad gate - stuck at 7S0" severity error;
assert (C_OUT = '1') report "bad gate - stuck at 7C0" severity error;
elsif (A = "1000" and B = "1001" and C_IN = '1') then
assert (sum = "1000") report "bad gate - stuck at 7S1" severity error;
assert (C_OUT = '1') report "bad gate - stuck at 7C1" severity error;
end if;
C_IN <= NOT(C_IN);
end loop;
B <= B + '1';
end loop;
A <= A + '1';
end loop;
wait;
end process;
END;
|
entity Top_PhysicalTest_Simple is
end entity;
architecture top of Top_PhysicalTest_Simple is
type my_int is range 1 to 5;
constant int_1 : INTEGER := natural(0.5); -- OK
constant int_2 : INTEGER := natural(-1.5); -- Error
constant int_3 : my_int := my_int(integer'(-1)); -- Error
begin
end;
|
entity Top_PhysicalTest_Simple is
end entity;
architecture top of Top_PhysicalTest_Simple is
type my_int is range 1 to 5;
constant int_1 : INTEGER := natural(0.5); -- OK
constant int_2 : INTEGER := natural(-1.5); -- Error
constant int_3 : my_int := my_int(integer'(-1)); -- Error
begin
end;
|
entity Top_PhysicalTest_Simple is
end entity;
architecture top of Top_PhysicalTest_Simple is
type my_int is range 1 to 5;
constant int_1 : INTEGER := natural(0.5); -- OK
constant int_2 : INTEGER := natural(-1.5); -- Error
constant int_3 : my_int := my_int(integer'(-1)); -- Error
begin
end;
|
entity Top_PhysicalTest_Simple is
end entity;
architecture top of Top_PhysicalTest_Simple is
type my_int is range 1 to 5;
constant int_1 : INTEGER := natural(0.5); -- OK
constant int_2 : INTEGER := natural(-1.5); -- Error
constant int_3 : my_int := my_int(integer'(-1)); -- Error
begin
end;
|
entity Top_PhysicalTest_Simple is
end entity;
architecture top of Top_PhysicalTest_Simple is
type my_int is range 1 to 5;
constant int_1 : INTEGER := natural(0.5); -- OK
constant int_2 : INTEGER := natural(-1.5); -- Error
constant int_3 : my_int := my_int(integer'(-1)); -- Error
begin
end;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:23:48 10/19/2014
-- Design Name:
-- Module Name: C:/Users/John/Code/vhdl_fft/cap_controller_tb.vhd
-- Project Name: fft
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: cap_controller
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY cap_controller_tb IS
END cap_controller_tb;
ARCHITECTURE behavior OF cap_controller_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cap_controller
PORT(
CLK1 : IN std_logic;
start: IN std_logic;
busy: OUT std_logic;
rst : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK1 : std_logic := '0';
signal rst : std_logic := '0';
signal start : std_logic := '0';
signal busy : std_logic := '0';
-- Clock period definitions -- 50 MHz
constant CLK1_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cap_controller PORT MAP (
CLK1 => CLK1,
start => start,
busy => busy,
rst => rst
);
-- Clock process definitions
CLK1_process :process
begin
CLK1 <= '0';
wait for CLK1_period/2;
CLK1 <= '1';
wait for CLK1_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
rst <= '0';
wait for 300 ns;
loop
start <= '1';
wait for 100 ns;
start <= '0';
wait until busy = '0';
wait for 50 us;
end loop;
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:23:48 10/19/2014
-- Design Name:
-- Module Name: C:/Users/John/Code/vhdl_fft/cap_controller_tb.vhd
-- Project Name: fft
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: cap_controller
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY cap_controller_tb IS
END cap_controller_tb;
ARCHITECTURE behavior OF cap_controller_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cap_controller
PORT(
CLK1 : IN std_logic;
start: IN std_logic;
busy: OUT std_logic;
rst : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK1 : std_logic := '0';
signal rst : std_logic := '0';
signal start : std_logic := '0';
signal busy : std_logic := '0';
-- Clock period definitions -- 50 MHz
constant CLK1_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cap_controller PORT MAP (
CLK1 => CLK1,
start => start,
busy => busy,
rst => rst
);
-- Clock process definitions
CLK1_process :process
begin
CLK1 <= '0';
wait for CLK1_period/2;
CLK1 <= '1';
wait for CLK1_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
rst <= '0';
wait for 300 ns;
loop
start <= '1';
wait for 100 ns;
start <= '0';
wait until busy = '0';
wait for 50 us;
end loop;
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:23:48 10/19/2014
-- Design Name:
-- Module Name: C:/Users/John/Code/vhdl_fft/cap_controller_tb.vhd
-- Project Name: fft
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: cap_controller
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY cap_controller_tb IS
END cap_controller_tb;
ARCHITECTURE behavior OF cap_controller_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cap_controller
PORT(
CLK1 : IN std_logic;
start: IN std_logic;
busy: OUT std_logic;
rst : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK1 : std_logic := '0';
signal rst : std_logic := '0';
signal start : std_logic := '0';
signal busy : std_logic := '0';
-- Clock period definitions -- 50 MHz
constant CLK1_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cap_controller PORT MAP (
CLK1 => CLK1,
start => start,
busy => busy,
rst => rst
);
-- Clock process definitions
CLK1_process :process
begin
CLK1 <= '0';
wait for CLK1_period/2;
CLK1 <= '1';
wait for CLK1_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
rst <= '0';
wait for 300 ns;
loop
start <= '1';
wait for 100 ns;
start <= '0';
wait until busy = '0';
wait for 50 us;
end loop;
wait;
end process;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3050.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b04x00p03n01i03050ent IS
END c12s02b04x00p03n01i03050ent;
ARCHITECTURE c12s02b04x00p03n01i03050arch OF c12s02b04x00p03n01i03050ent IS
signal si:integer;
signal sr:real;
signal sb:bit;
BEGIN
-- test for no associated ports
bl1: block
port (i:integer:=4;r:real:=6.4;b:bit:='1');
begin
assert (i=4)
report "Default expression for unassociated integer port I incorrect"
severity failure;
assert (r=6.4)
report "Default expression for unassociated real port R incorrect"
severity failure;
assert (b='1')
report "Default expression for unassociated bit port B incorrect"
severity failure;
TESTING: PROCESS
BEGIN
assert NOT( i=4 and r=6.4 and b='1' )
report "***PASSED TEST: c12s02b04x00p03n01i03050"
severity NOTE;
assert ( i=4 and r=6.4 and b='1' )
report "***FAILED TEST: c12s02b04x00p03n01i03050 - Unassociated ports are not correctly evaluated for the ports of a block."
severity ERROR;
wait;
END PROCESS TESTING;
end block;
END c12s02b04x00p03n01i03050arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3050.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b04x00p03n01i03050ent IS
END c12s02b04x00p03n01i03050ent;
ARCHITECTURE c12s02b04x00p03n01i03050arch OF c12s02b04x00p03n01i03050ent IS
signal si:integer;
signal sr:real;
signal sb:bit;
BEGIN
-- test for no associated ports
bl1: block
port (i:integer:=4;r:real:=6.4;b:bit:='1');
begin
assert (i=4)
report "Default expression for unassociated integer port I incorrect"
severity failure;
assert (r=6.4)
report "Default expression for unassociated real port R incorrect"
severity failure;
assert (b='1')
report "Default expression for unassociated bit port B incorrect"
severity failure;
TESTING: PROCESS
BEGIN
assert NOT( i=4 and r=6.4 and b='1' )
report "***PASSED TEST: c12s02b04x00p03n01i03050"
severity NOTE;
assert ( i=4 and r=6.4 and b='1' )
report "***FAILED TEST: c12s02b04x00p03n01i03050 - Unassociated ports are not correctly evaluated for the ports of a block."
severity ERROR;
wait;
END PROCESS TESTING;
end block;
END c12s02b04x00p03n01i03050arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3050.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b04x00p03n01i03050ent IS
END c12s02b04x00p03n01i03050ent;
ARCHITECTURE c12s02b04x00p03n01i03050arch OF c12s02b04x00p03n01i03050ent IS
signal si:integer;
signal sr:real;
signal sb:bit;
BEGIN
-- test for no associated ports
bl1: block
port (i:integer:=4;r:real:=6.4;b:bit:='1');
begin
assert (i=4)
report "Default expression for unassociated integer port I incorrect"
severity failure;
assert (r=6.4)
report "Default expression for unassociated real port R incorrect"
severity failure;
assert (b='1')
report "Default expression for unassociated bit port B incorrect"
severity failure;
TESTING: PROCESS
BEGIN
assert NOT( i=4 and r=6.4 and b='1' )
report "***PASSED TEST: c12s02b04x00p03n01i03050"
severity NOTE;
assert ( i=4 and r=6.4 and b='1' )
report "***FAILED TEST: c12s02b04x00p03n01i03050 - Unassociated ports are not correctly evaluated for the ports of a block."
severity ERROR;
wait;
END PROCESS TESTING;
end block;
END c12s02b04x00p03n01i03050arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 10:19:56 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux2x1_10_0_0/RAT_Mux2x1_10_0_0_stub.vhdl
-- Design : RAT_Mux2x1_10_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAT_Mux2x1_10_0_0 is
Port (
A : in STD_LOGIC_VECTOR ( 9 downto 0 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
SEL : in STD_LOGIC;
X : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end RAT_Mux2x1_10_0_0;
architecture stub of RAT_Mux2x1_10_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "A[9:0],B[9:0],SEL,X[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "Mux2x1_10,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:53:17 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_rgb565_to_rgb888_0_0 -prefix
-- system_rgb565_to_rgb888_0_0_ system_rgb565_to_rgb888_1_0_stub.vhdl
-- Design : system_rgb565_to_rgb888_1_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_rgb565_to_rgb888_0_0 is
Port (
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_rgb565_to_rgb888_0_0;
architecture stub of system_rgb565_to_rgb888_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rgb_565[15:0],rgb_888[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "rgb565_to_rgb888,Vivado 2016.4";
begin
end;
|
--
-- File Name: MessagePkg.vhd
-- Design Unit Name: MessagePkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for multi-line name/message to be associated with a data structure.
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 06/2010 0.1 Initial revision
-- 07/2014 2014.07 Moved specialization required by CoveragePkg to CoveragePkg
-- 07/2014 2014.07a Removed initialized pointers which can lead to memory leaks.
-- 01/2015 2015.01 Removed initialized parameter from Get
-- 04/2018 2018.04 Minor updates to alert message
-- 01/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2010 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use std.textio.all ;
package MessagePkg is
type MessagePType is protected
procedure Set (MessageIn : String) ;
impure function Get (ItemNumber : integer) return string ;
impure function GetCount return integer ;
impure function IsSet return boolean ;
procedure Clear ; -- clear message
procedure Deallocate ; -- clear message
end protected MessagePType ;
end package MessagePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body MessagePkg is
-- Local Data Structure Types
type LineArrayType is array (natural range <>) of line ;
type LineArrayPtrType is access LineArrayType ;
type MessagePType is protected body
variable MessageCount : integer := 0 ;
constant INITIAL_ITEM_COUNT : integer := 16 ;
variable MaxMessageCount : integer := 0 ;
variable MessagePtr : LineArrayPtrType ;
------------------------------------------------------------
procedure Set (MessageIn : String) is
------------------------------------------------------------
variable NamePtr : line ;
variable OldMaxMessageCount : integer ;
variable OldMessagePtr : LineArrayPtrType ;
begin
MessageCount := MessageCount + 1 ;
if MessageCount > MaxMessageCount then
OldMaxMessageCount := MaxMessageCount ;
MaxMessageCount := MaxMessageCount + INITIAL_ITEM_COUNT ;
OldMessagePtr := MessagePtr ;
MessagePtr := new LineArrayType(1 to MaxMessageCount) ;
for i in 1 to OldMaxMessageCount loop
MessagePtr(i) := OldMessagePtr(i) ;
end loop ;
Deallocate( OldMessagePtr ) ;
end if ;
MessagePtr(MessageCount) := new string'(MessageIn) ;
end procedure Set ;
------------------------------------------------------------
impure function Get (ItemNumber : integer) return string is
------------------------------------------------------------
begin
if MessageCount > 0 then
if ItemNumber >= 1 and ItemNumber <= MessageCount then
return MessagePtr(ItemNumber).all ;
else
Alert(OSVVM_ALERTLOG_ID, "OSVVM.MessagePkg.Get input value out of range", FAILURE) ;
return "" ; -- error if this happens
end if ;
else
Alert(OSVVM_ALERTLOG_ID, "OSVVM.MessagePkg.Get message is not set", FAILURE) ;
return "" ; -- error if this happens
end if ;
end function Get ;
------------------------------------------------------------
impure function GetCount return integer is
------------------------------------------------------------
begin
return MessageCount ;
end function GetCount ;
------------------------------------------------------------
impure function IsSet return boolean is
------------------------------------------------------------
begin
return MessageCount > 0 ;
end function IsSet ;
------------------------------------------------------------
procedure Deallocate is -- clear message
------------------------------------------------------------
variable CurPtr : LineArrayPtrType ;
begin
for i in 1 to MessageCount loop
deallocate( MessagePtr(i) ) ;
end loop ;
MessageCount := 0 ;
MaxMessageCount := 0 ;
deallocate( MessagePtr ) ;
end procedure Deallocate ;
------------------------------------------------------------
procedure Clear is -- clear
------------------------------------------------------------
begin
Deallocate ;
end procedure Clear ;
end protected body MessagePType ;
end package body MessagePkg ; |
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_test1
-- Date:2015-01-27
-- Author: Gideon
-- Description: Testcase 1 for USB host
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_bfm_pkg.all;
use work.tl_sctb_pkg.all;
use work.usb_cmd_pkg.all;
use work.tl_string_util_pkg.all;
use work.nano_addresses_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity usb_test_nano1 is
generic (
g_report_file_name : string := "work/usb_test_nano1.rpt"
);
end entity;
architecture arch of usb_test_nano1 is
signal clocks_stopped : boolean := false;
constant c_rx_size : integer := 4096 + 512;
constant c_tx_size : integer := 4096 + 512;
begin
i_harness: entity work.usb_harness_nano
port map (
clocks_stopped => clocks_stopped );
process
variable io : p_io_bus_bfm_object;
variable mem : h_mem_object;
variable data : std_logic_vector(15 downto 0);
variable res : std_logic_vector(7 downto 0);
variable start, stop : time;
variable transferred : integer;
variable micros, kbps : real;
procedure io_write_word(addr : unsigned(19 downto 0); word : std_logic_vector(15 downto 0)) is
begin
io_write(io => io, addr => (addr + 0), data => word(7 downto 0));
io_write(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure io_read_word(addr : unsigned(19 downto 0); word : out std_logic_vector(15 downto 0)) is
begin
io_read(io => io, addr => (addr + 0), data => word(7 downto 0));
io_read(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure wait_command_done is
begin
L1: while true loop
io_read(io => io, addr => Command+1, data => res);
if res(1) = '1' then -- check if paused bit has been set
exit L1;
end if;
end loop;
end procedure;
begin
bind_io_bus_bfm("io", io);
bind_mem_model("memory", mem);
sctb_open_simulation("path:path", g_report_file_name);
sctb_open_region("Testing Setup request", 0);
sctb_set_log_level(c_log_level_trace);
wait for 70 ns;
io_write_word(c_nano_simulation, X"0001" ); -- set nano to simulation mode
io_write_word(c_nano_busspeed, X"0002" ); -- set bus speed to HS
io_write(io, c_nano_enable, X"01" ); -- enable nano
wait for 4 us;
write_memory_8(mem, X"00041328", X"11");
write_memory_8(mem, X"00041329", X"22");
write_memory_8(mem, X"0004132A", X"33");
write_memory_8(mem, X"0004132B", X"44");
write_memory_8(mem, X"0004132C", X"55");
write_memory_8(mem, X"0004132D", X"66");
write_memory_8(mem, X"0004132E", X"77");
write_memory_8(mem, X"0004132F", X"88");
io_write_word(Command_DevEP, X"0000");
io_write_word(Command_MaxTrans, X"0040");
io_write_word(Command_MemHi, X"0004");
io_write_word(Command_MemLo, X"1328");
io_write_word(Command_Length, X"0008");
io_write_word(Command_Timeout, X"0004");
io_write_word(Command_Started, X"0000");
io_write_word(Command, X"8040"); -- setup with mem read
wait_command_done;
sctb_close_region;
sctb_open_region("Testing In request", 0);
start := now;
io_write_word(Command_DevEP, X"0004");
io_write_word(Command_MaxTrans, X"0100");
io_write_word(Command_Length, X"0FFF");
io_write_word(Command, X"4042"); -- in with mem write
wait_command_done;
stop := now;
io_read_word(Command_Result, data);
sctb_trace("Command result: " & hstr(data));
io_read_word(Command_Length, data);
sctb_trace("Command length: " & hstr(data));
transferred := 4095 - to_integer(signed(data));
sctb_trace("Transferred: " & integer'image(transferred));
sctb_assert(transferred = 4096, "Expected 4096 bytes.");
micros := real((stop - start) / 1.0 us);
kbps := (real(transferred) * 1000.0) / micros;
sctb_trace("Got " & integer'image(integer(kbps)) & " KB/s");
sctb_close_region;
wait for 20 us;
sctb_open_region("Testing Out request", 0);
start := now;
io_write_word(Command_MemHi, X"0004");
io_write_word(Command_MemLo, X"1328");
io_write_word(Command_MaxTrans, X"0200");
io_write_word(Command_DevEP, X"0005");
io_write_word(Command_Length, std_logic_vector(to_unsigned(c_tx_size, 16)));
io_write_word(Command, X"8041"); -- out with mem read
wait_command_done;
stop := now;
io_read_word(Command_Result, data);
sctb_trace("Command result: " & hstr(data));
io_read_word(Command_Length, data);
transferred := c_tx_size - to_integer(signed(data));
sctb_trace("Transferred: " & integer'image(transferred));
sctb_check(transferred, c_tx_size, "Expected to send c_tx_size bytes.");
micros := real((stop - start) / 1.0 us);
kbps := (real(transferred) * 1000.0) / micros;
sctb_trace("Got " & integer'image(integer(kbps)) & " KB/s");
sctb_close_region;
sctb_close_simulation;
clocks_stopped <= true;
wait;
end process;
end arch;
-- restart; mem load -infile nano_code.hex -format hex /usb_test_nano1/i_harness/i_host/i_nano/i_buf_ram/mem; run 1100 us |
library verilog;
use verilog.vl_types.all;
entity IF_ID_Seg is
port(
Clk : in vl_logic;
stall : in vl_logic;
flush : in vl_logic;
PC_Add : in vl_logic_vector(31 downto 0);
IR_out : in vl_logic_vector(31 downto 0);
PC_Add_out : out vl_logic_vector(31 downto 0);
Op : out vl_logic_vector(5 downto 0);
Rs : out vl_logic_vector(4 downto 0);
Rt : out vl_logic_vector(4 downto 0);
Rd : out vl_logic_vector(4 downto 0);
Shamt : out vl_logic_vector(4 downto 0);
Func : out vl_logic_vector(5 downto 0)
);
end IF_ID_Seg;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:40 04/04/2014
-- Design Name:
-- Module Name: amplitude_adjust - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity amplitude_adjust is
port(
sine_in: in std_logic_vector(11 downto 0);
sine_out: out std_logic_vector(11 downto 0);
adjust: in std_logic_vector(5 downto 0);
clk: in std_logic
);
end amplitude_adjust;
architecture Behavioral of amplitude_adjust is
signal one_shift: unsigned(10 downto 0);
signal two_shift: unsigned(9 downto 0);
signal three_shift: unsigned(8 downto 0);
signal four_shift: unsigned(7 downto 0);
signal five_shift: unsigned(6 downto 0);
signal six_shift: unsigned(6 downto 0);
signal one_shift_temp: unsigned(11 downto 0);
signal two_shift_temp: unsigned(11 downto 0);
signal three_shift_temp: unsigned(11 downto 0);
signal four_shift_temp: unsigned(11 downto 0);
signal five_shift_temp: unsigned(11 downto 0);
signal six_shift_temp: unsigned(11 downto 0);
begin
-- Placed into a process to improve timing
process(clk)
begin
if(rising_edge(clk)) then
if adjust(5) = '1' then
one_shift <= (unsigned(sine_in) srl 1);
else
one_shift <= (others => '0');
end if;
if adjust(4) = '1' then
two_shift <= unsigned(sine_in) srl 2;
else
two_shift <= (others => '0');
end if;
if adjust(3) = '1' then
three_shift <= unsigned(sine_in) srl 3;
else
three_shift <= (others => '0');
end if;
if adjust(2) = '1' then
four_shift <= unsigned(sine_in) srl 4;
else
four_shift <= (others => '0');
end if;
if adjust(1) = '1' then
five_shift <= unsigned(sine_in) srl 5;
else
five_shift <= (others => '0');
end if;
if adjust(0) = '1' then
six_shift <= unsigned(sine_in) srl 5;
else
six_shift <= (others => '0');
end if;
--
-- four_shift <= unsigned(sine_in) srl 4 if adjust(2) = '1' else (others => '0');
-- five_shift <= unsigned(sine_in) srl 5 if adjust(1) = '1' else (others => '0');
-- six_shift <= unsigned(sine_in) srl 5 if adjust(0) = '1' else (others => '0');
if(adjust = "111111") then
sine_out <= sine_in;
else
sine_out <= std_logic_vector(one_shift_temp + two_shift_temp + three_shift_temp + four_shift_temp + five_shift_temp + six_shift_temp);
end if;
end if;
end process;
one_shift_temp <= '0' & one_shift;
two_shift_temp <= "00" & two_shift;
three_shift_temp <= "000" & three_shift;
four_shift_temp <= "0000" & four_shift;
five_shift_temp <= "00000" & five_shift;
six_shift_temp <= "00000" & six_shift;
end Behavioral;
|
-----------------------------------------------------------------------------------------
-- Generated by WISHBONE Builder. Do not edit this file.
--
-- For defines see wb_devices.defines
--
-- Package: WBDevInterconPkg (WBDevIntercon_package.vhdl)
--
-- Generated Tue May 30 10:23:57 2017
--
-- Wishbone masters:
-- cpu
--
-- Wishbone slaves:
-- rs2
-- baseadr 0x00000000 - size 0x40
-- ad
-- baseadr 0x00000040 - size 0x40
-- tmr
-- baseadr 0x00000080 - size 0x40
-- t16
-- baseadr 0x000000C0 - size 0x40
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package WBDevInterconIntPackage is
function "and"(l : std_logic_vector;
r : std_logic) return std_logic_vector;
end package WBDevInterconIntPackage;
package body WBDevInterconIntPackage is
function "and"(l : std_logic_vector;
r : std_logic) return std_logic_vector is
variable result : std_logic_vector(l'range);
begin -- "and"
for i in l'range loop
result(i):=l(i) and r;
end loop; -- i
return result;
end function "and";
end package body WBDevInterconIntPackage;
library IEEE;
use IEEE.std_logic_1164.all;
use work.WBDevInterconIntPackage.all;
entity WBDevIntercon is
port(
-- wishbone master port(s)
-- cpu
cpu_dat_o : out std_logic_vector(7 downto 0);
cpu_ack_o : out std_logic;
cpu_dat_i : in std_logic_vector(7 downto 0);
cpu_we_i : in std_logic;
cpu_adr_i : in std_logic_vector(7 downto 0);
cpu_cyc_i : in std_logic;
cpu_stb_i : in std_logic;
-- wishbone slave port(s)
-- rs2
rs2_dat_i : in std_logic_vector(7 downto 0);
rs2_ack_i : in std_logic;
rs2_dat_o : out std_logic_vector(7 downto 0);
rs2_we_o : out std_logic;
rs2_adr_o : out std_logic_vector(0 downto 0);
rs2_stb_o : out std_logic;
-- ad
ad_dat_i : in std_logic_vector(7 downto 0);
ad_ack_i : in std_logic;
ad_dat_o : out std_logic_vector(7 downto 0);
ad_we_o : out std_logic;
ad_adr_o : out std_logic_vector(0 downto 0);
ad_stb_o : out std_logic;
-- tmr
tmr_dat_i : in std_logic_vector(7 downto 0);
tmr_ack_i : in std_logic;
tmr_dat_o : out std_logic_vector(7 downto 0);
tmr_we_o : out std_logic;
tmr_adr_o : out std_logic_vector(2 downto 0);
tmr_stb_o : out std_logic;
-- t16
t16_dat_i : in std_logic_vector(7 downto 0);
t16_ack_i : in std_logic;
t16_dat_o : out std_logic_vector(7 downto 0);
t16_we_o : out std_logic;
t16_adr_o : out std_logic_vector(0 downto 0);
t16_stb_o : out std_logic;
-- clock and reset
wb_clk_i : in std_logic;
wb_rst_i : in std_logic);
end entity WBDevIntercon;
architecture RTL of WBDevIntercon is
signal rs2_ss : std_logic; -- slave select
signal ad_ss : std_logic; -- slave select
signal tmr_ss : std_logic; -- slave select
signal t16_ss : std_logic; -- slave select
begin -- RTL
decoder:
block
signal adr : std_logic_vector(7 downto 0);
begin
adr <= cpu_adr_i;
rs2_ss <= '1' when adr(7 downto 6)="00" else '0';
ad_ss <= '1' when adr(7 downto 6)="01" else '0';
tmr_ss <= '1' when adr(7 downto 6)="10" else '0';
t16_ss <= '1' when adr(7 downto 6)="11" else '0';
rs2_adr_o <= adr(0 downto 0);
ad_adr_o <= adr(0 downto 0);
tmr_adr_o <= adr(2 downto 0);
t16_adr_o <= adr(0 downto 0);
end block decoder;
mux:
block
signal stb_m2s : std_logic;
signal we_m2s : std_logic;
signal ack_s2m : std_logic;
signal dat_m2s : std_logic_vector(7 downto 0);
signal dat_s2m : std_logic_vector(7 downto 0);
begin
-- stb Master -> Slave [Selection]
stb_m2s <= cpu_stb_i;
rs2_stb_o <= rs2_ss and stb_m2s;
ad_stb_o <= ad_ss and stb_m2s;
tmr_stb_o <= tmr_ss and stb_m2s;
t16_stb_o <= t16_ss and stb_m2s;
-- we Master -> Slave
we_m2s <= cpu_we_i;
rs2_we_o <= we_m2s;
ad_we_o <= we_m2s;
tmr_we_o <= we_m2s;
t16_we_o <= we_m2s;
-- ack Slave -> Master
ack_s2m <= rs2_ack_i or ad_ack_i or tmr_ack_i or t16_ack_i;
cpu_ack_o <= ack_s2m;
-- dat Master -> Slave
dat_m2s <= cpu_dat_i;
rs2_dat_o <= dat_m2s;
ad_dat_o <= dat_m2s;
tmr_dat_o <= dat_m2s;
t16_dat_o <= dat_m2s;
-- dat Slave -> Master [and/or]
dat_s2m <= (rs2_dat_i and rs2_ss) or (ad_dat_i and ad_ss) or (tmr_dat_i and tmr_ss) or (t16_dat_i and t16_ss);
cpu_dat_o <= dat_s2m;
end block mux;
end architecture RTL; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Ram2_N_Demo is
port( KEY : in std_logic_vector(0 downto 0);
SW : in std_logic_vector(17 downto 0);
LEDG : out std_logic_vector(3 downto 0));
end Ram2_N_demo;
architecture Structural of Ram2_N_Demo is
begin
ram: entity work.Ram2_n(Behavioral)
generic map(data => 4,
addr => 2)
port map(clk => KEY(0),
writeEnable => SW(0),
writeData => SW(17 downto 14),
writeAddress => SW(2 downto 1),
readAddress => SW(4 downto 3),
dataOut => LEDG(3 downto 0));
end Structural; |
-- Dynamic Partial Reconfiguration
constant CFG_PRC : integer := CONFIG_PARTIAL;
constant CFG_CRC_EN : integer := CONFIG_CRC;
constant CFG_EDAC_EN : integer := CONFIG_EDAC;
constant CFG_WORDS_BLOCK : integer := CONFIG_BLOCK;
constant CFG_DCM_FIFO : integer := CONFIG_DCM_FIFO;
constant CFG_DPR_FIFO : integer := CFG_DPRFIFO;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2608.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02608ent IS
END c13s03b01x00p02n01i02608ent;
ARCHITECTURE c13s03b01x00p02n01i02608arch OF c13s03b01x00p02n01i02608ent IS
BEGIN
TESTING: PROCESS
variable k\ : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02608 - Identifier can not end with '\'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02608arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2608.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02608ent IS
END c13s03b01x00p02n01i02608ent;
ARCHITECTURE c13s03b01x00p02n01i02608arch OF c13s03b01x00p02n01i02608ent IS
BEGIN
TESTING: PROCESS
variable k\ : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02608 - Identifier can not end with '\'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02608arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2608.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02608ent IS
END c13s03b01x00p02n01i02608ent;
ARCHITECTURE c13s03b01x00p02n01i02608arch OF c13s03b01x00p02n01i02608ent IS
BEGIN
TESTING: PROCESS
variable k\ : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02608 - Identifier can not end with '\'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02608arch;
|
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|
`protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/Complex3Multiply_block4.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block4
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block4 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din2_re_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
din2_im_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
di2_vld_dly3 : IN std_logic;
twdl_3_8_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_8_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_8_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_8_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin2_vld : OUT std_logic
);
END Complex3Multiply_block4;
ARCHITECTURE rtl OF Complex3Multiply_block4 IS
-- Signals
SIGNAL din2_re_dly3_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_im_dly3_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_sum : signed(20 DOWNTO 0); -- sfix21
SIGNAL twdl_3_8_re_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_re_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_8_im_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_im_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL adder_add_cast : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL adder_add_cast_1 : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL twdl_sum : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(20 DOWNTO 0); -- sfix21
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL prodOfRe : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL prodOfIm : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL prodOfSum : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Add_multRes_re_reg1 : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_multRes_re_reg2 : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_multRes_im_reg : signed(39 DOWNTO 0); -- sfix40
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Add_tmpResult_reg_next : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL Complex3Add_multRes_re_reg1_next : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL Complex3Add_multRes_re_reg2_next : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL Complex3Add_multRes_im_reg_next : signed(39 DOWNTO 0); -- sfix40_En15
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL multResFP_re : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL multResFP_im : signed(39 DOWNTO 0); -- sfix40_En15
SIGNAL twdlXdin_8_re_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_8_im_tmp : signed(19 DOWNTO 0); -- sfix20
BEGIN
din2_re_dly3_signed <= signed(din2_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#00000#, 20);
ELSE
din_re_reg <= din2_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din2_im_dly3_signed <= signed(din2_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#00000#, 20);
ELSE
din_im_reg <= din2_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
din_sum <= resize(din_re_reg, 21) + resize(din_im_reg, 21);
twdl_3_8_re_signed <= signed(twdl_3_8_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSE
twdl_re_reg <= twdl_3_8_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_8_im_signed <= signed(twdl_3_8_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSE
twdl_im_reg <= twdl_3_8_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast <= resize(twdl_re_reg, 18);
adder_add_cast_1 <= resize(twdl_im_reg, 18);
twdl_sum <= adder_add_cast + adder_add_cast_1;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly1 <= di2_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 39);
Complex3Add_tmpResult_reg <= to_signed(0, 39);
Complex3Add_multRes_re_reg1 <= to_signed(0, 38);
Complex3Add_multRes_re_reg2 <= to_signed(0, 38);
Complex3Add_multRes_im_reg <= to_signed(0, 40);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(37 DOWNTO 0);
VARIABLE sub_cast_0 : signed(37 DOWNTO 0);
VARIABLE sub_cast_1 : signed(39 DOWNTO 0);
VARIABLE sub_cast_2 : signed(39 DOWNTO 0);
VARIABLE add_cast : signed(37 DOWNTO 0);
VARIABLE add_cast_0 : signed(37 DOWNTO 0);
VARIABLE add_temp : signed(37 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 38);
sub_cast_0 := resize(prodOfIm, 38);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 40);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 40);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 38);
add_cast_0 := resize(prodOfIm, 38);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 39);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin2_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_8_re_tmp <= multResFP_re(34 DOWNTO 15);
twdlXdin_8_re <= std_logic_vector(twdlXdin_8_re_tmp);
twdlXdin_8_im_tmp <= multResFP_im(34 DOWNTO 15);
twdlXdin_8_im <= std_logic_vector(twdlXdin_8_im_tmp);
END rtl;
|
--**********************************************************************************
-- Copyright 2013, Ryan Henderson
-- CMOS digital camera controller and frame capture device
--
-- ram_control.vhd
--
--
-- Memory arbitrator. Handle access to memory. Control the FIFOs in other modules
-- Incorporates SDRAM controller.
--**********************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.common.all;
use work.comp_pckgs.all;
ENTITY ram_control IS
PORT
(
clk_50Mhz: in std_logic;
rst: in std_logic;
-- PP RAM access. Control provided by MCSG
pp_data_out : out std_logic_vector(15 downto 0);
start_upload : in std_logic;
abort_upload : in std_logic;
start_addr_upload : in std_logic_vector(22 downto 0);
end_addr_upload : in std_logic_vector(22 downto 0);
pp_fifo_wr_en : out std_logic;
pp_fifo_need_data : in std_logic;
-- KAC RAM access
rd_en_KAC : out std_logic;
dout_KAC : in std_logic_vector(15 downto 0);
dump_data_req_KAC : in std_logic;
start_new_frame : in std_logic;
-- SDRAM side
cke: out std_logic; -- clock-enable to SDRAM
cs_n: out std_logic; -- chip-select to SDRAM
ras_n: out std_logic; -- command input to SDRAM
cas_n: out std_logic; -- command input to SDRAM
we_n: out std_logic; -- command input to SDRAM
ba: out unsigned(1 downto 0); -- SDRAM bank address bits
sAddr: out unsigned(12-1 downto 0); -- SDRAM row/column address
sData: inout unsigned(16-1 downto 0); -- SDRAM in/out databus
dqmh: out std_logic; -- high databits I/O mask
dqml: out std_logic -- low databits I/O mask
);
END ram_control;
ARCHITECTURE ram_control_arch OF ram_control IS
-- Constants
constant HRES : natural := 1280;
constant VRES : natural := 1024;
--Flags pport, misc
signal uploading : std_logic;
signal pp_addr_pointer : unsigned(19 downto 0);
signal pp_ram_page : unsigned(2 downto 0); --Current readout page
signal ram_page_full : unsigned(2 downto 0); --Complete frame
signal ram_addr : unsigned(22 downto 0);
type semaphore is (NOBODY, KAC, PPORT);
signal SDRAM_used_by : semaphore;
--KAC signals
signal addr_ptr_KAC : unsigned(19 downto 0);
signal ram_page_KAC : unsigned(2 downto 0); --Current writeout page
--SDRAM Signals and constants
signal rd, rd_next : std_logic;
signal wr : std_logic;
signal done : std_logic;
signal hDOut : unsigned(16-1 downto 0); -- Type conversion
signal sdramCntl_state : std_logic_vector(3 downto 0);
BEGIN
pp_fifo_wr_en <= '1' when done = '1' and rd = '1' else '0';
rd_en_KAC <= '1' when done = '1' and wr = '1' else '0';
pp_data_out <= std_logic_vector(hDOut); --Conversions are fun!
-- The rd_en for the KAC_data fifo also can enable the write for the memory.
-- Data in: Enable KAC_data fifo read and RAM Write
-- Data out: Enable PP_Fifo write and RAM read
-- B5 : block_ram_2kx16
-- port map
-- (
-- addr => std_logic_vector(ram_addr(10 downto 0)),
-- clk => clk_50Mhz,
-- sinit => not_rst,
-- din => dout_KAC,
-- dout => pp_data_out,
-- we => rd_en_KAC_sig
-- );
-- SDRAM memory controller module
u1: sdramCntl
generic map(
FREQ => 50_000, -- 50 MHz operation
DATA_WIDTH => 16,
HADDR_WIDTH => 23,
SADDR_WIDTH => 12
)
port map(
clk => clk_50Mhz, -- master clock
rst => rst, -- active high reset
rd => rd, -- SDRAM read control
wr => wr, -- SDRAM write control
done => done, -- SDRAM memory read/write done indicator
hAddr => ram_addr, -- host-side address from memory tester
hDIn => unsigned(dout_KAC), -- Data into sdram controller
hDOut => hDOut, -- data from SDRAM
sdramCntl_state => sdramCntl_state, -- (for testing)
cke => cke, -- SDRAM clock enable
cs_n => cs_n, -- SDRAM chip-select
ras_n => ras_n, -- SDRAM RAS
cas_n => cas_n, -- SDRAM CAS
we_n => we_n, -- SDRAM write-enable
ba => ba, -- SDRAM bank address
sAddr => sAddr, -- SDRAM address
sData => sData, -- SDRAM databus
dqmh => dqmh, -- SDRAM DQMH
dqml => dqml -- SDRAM DQML
);
-- Determine which address to use for ram
ram_addr <= (others=>'0') when rst = '0' else
ram_page_KAC & addr_ptr_KAC when wr = '1' else
pp_ram_page & pp_addr_pointer;
-- Page the memory to prevent over writing
ram_page: process (rst, clk_50Mhz, start_new_frame, ram_page_full, pp_ram_page,
ram_page_KAC, start_upload ) is
--Do I need to make a temp variable for the swap? NOPE!
begin
if rst = '0' then
ram_page_KAC <= "000";
ram_page_full <= "001";
pp_ram_page <= "010";
elsif clk_50Mhz'event and clk_50Mhz = '1' then
-- They both could happen in the same 50Mhz clock. unlikely,
-- but possible
if start_new_frame = '1' and start_upload = '1' then
pp_ram_page <= ram_page_KAC;
elsif start_new_frame = '1' then
ram_page_full <= ram_page_KAC;
ram_page_KAC <= ram_page_full;
elsif start_upload = '1' then
pp_ram_page <= ram_page_full;
ram_page_full <= pp_ram_page;
end if;
end if;
end process ram_page;
-- Control access to the SDRAM with a semaphore. When a FIFO request action,
-- respond by locking control of the memory, or waiting. If memory is
-- available, signal the fifo to start transfering, and set SDRAM control
-- bits rd and wr.
sem_control: process(clk_50Mhz, rst, SDRAM_used_by, pp_fifo_need_data,
dump_data_req_KAC, uploading, addr_ptr_KAC) is
begin
if rst='0' then
rd_next <= '0';
rd <= '0';
SDRAM_used_by <= NOBODY;
wr <= '0';
else
--take semaphore
if pp_fifo_need_data = '1' and uploading = '1'
and (SDRAM_used_by = NOBODY or SDRAM_used_by = PPORT) then
SDRAM_used_by <= PPORT;
rd_next <= '1'; --SDRAM read
elsif dump_data_req_KAC = '1'
and (SDRAM_used_by = NOBODY or SDRAM_used_by = KAC) then
SDRAM_used_by <= KAC;
wr <= '1';
else
-- Default values if not specified below
-- Done with transfer, release control of memory
-- or it's not needed
rd_next <= '0';
wr <= '0';
SDRAM_used_by <= NOBODY;
end if;
-- Delay the pp_fifo_wr_en signal by one clock to account for delay
if clk_50Mhz'event and clk_50Mhz = '1' then
rd <= rd_next;
end if;
end if;
end process sem_control;
-- Control the KAC address pointer. Reset it when a new frame is signaled.
-- Only increment it once after a write is completed. Prevent writing into
-- next frame if there is no new frame signal
KAC_fifo_empty: process(clk_50Mhz, rst, start_new_frame, wr, done,
addr_ptr_KAC ) is
begin
if rst='0' then
addr_ptr_KAC <= (others=>'0');
elsif clk_50Mhz'event and clk_50Mhz='1' then
if start_new_frame = '1' then
addr_ptr_KAC <= (others=>'0');
elsif wr = '1' and done = '1' then
if addr_ptr_KAC < 655360 then -- Don't wrap around
addr_ptr_KAC <= addr_ptr_KAC + 1;
end if;
end if;
end if;
end process KAC_fifo_empty;
-- When the fifo needs data, check to see if memory is available, then set the
-- write flag and start clocking data at the fifo until it lowers need_data.
-- Update process to add new sdram stuff. Control how the address for the pport
-- is set
pp_fifo_fill: process(clk_50Mhz, rst, pp_fifo_need_data, start_upload,
abort_upload, start_addr_upload, end_addr_upload, pp_addr_pointer) is
begin
if rst='0' then
pp_addr_pointer <= (others=>'0');
uploading <= '0';
else
--clocked events
if clk_50Mhz'event and clk_50Mhz='1' then
if start_upload = '1' then
uploading <= '1';
pp_addr_pointer <= unsigned(start_addr_upload(19 downto 0));
elsif abort_upload = '1' or pp_addr_pointer >
unsigned(end_addr_upload(19 downto 0)) then
uploading <= '0';
pp_addr_pointer <= (others=>'0');
-- Inc on done signal generated by sdram
elsif rd = '1' and done = '1' then
pp_addr_pointer <= pp_addr_pointer + 1;
end if;
end if;
end if;
end process pp_fifo_fill;
END ram_control_arch;
|
--========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_sbi;
use bitvis_vip_sbi.vvc_cmd_pkg.all;
use bitvis_vip_sbi.vvc_methods_pkg.all;
use bitvis_vip_sbi.td_vvc_framework_common_methods_pkg.all;
end context; |
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: dlx-instrumented.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 18:36:01 $
--
--------------------------------------------------------------------------
--
-- Instrumented behavioural architecture for DLX, that generates
-- a files of instruction execution frequencies for a program.
--
use work.dlx_instr.all,
work.bv_arithmetic.all,
std.textio.all;
architecture instrumented of dlx is
begin -- instrumented
interpreter: process
type reg_array is array (reg_index) of dlx_word;
variable reg : reg_array;
variable fp_reg : reg_array;
variable PC : dlx_word;
variable user_mode : boolean;
variable overflow, div_by_zero : boolean;
constant PC_incr : dlx_word := X"0000_0004";
variable IR : dlx_word;
alias IR_opcode : dlx_opcode is IR(0 to 5);
alias IR_sp_func : dlx_sp_func is IR(26 to 31);
alias IR_fp_func : dlx_fp_func is IR(27 to 31);
alias IR_rs1 : dlx_reg_addr is IR(6 to 10);
alias IR_rs2 : dlx_reg_addr is IR(11 to 15);
alias IR_Itype_rd : dlx_reg_addr is IR(11 to 15);
alias IR_Rtype_rd : dlx_reg_addr is IR(16 to 20);
alias IR_immed16 : dlx_immed16 is IR(16 to 31);
alias IR_immed26 : dlx_immed26 is IR(6 to 31);
variable IR_opcode_num : dlx_opcode_num;
variable IR_sp_func_num : dlx_sp_func_num;
variable IR_fp_func_num : dlx_fp_func_num;
variable rs1, rs2, Itype_rd, Rtype_rd : reg_index;
variable mem_addr : dlx_address;
variable mem_data : dlx_word;
subtype ls_2_addr_bits is bit_vector(1 downto 0);
file data : text is out "dlx_instruction_counts";
variable L : line;
---------------------------------------------------------------------------
-- instrumentation: array of counters, one per instruction
---------------------------------------------------------------------------
type opcode_count_array is array (dlx_opcode_num) of natural;
type sp_func_count_array is array (dlx_sp_func_num) of natural;
type fp_func_count_array is array (dlx_fp_func_num) of natural;
variable op_count : opcode_count_array := (others => 0);
variable sp_func_count : sp_func_count_array := (others => 0);
variable fp_func_count : fp_func_count_array := (others => 0);
variable instr_count : natural := 0;
---------------------------------------------------------------------------
-- instrumentation: procedure to dump counter values
---------------------------------------------------------------------------
procedure instrumentation_dump is
variable L : line;
begin
for op in dlx_opcode_num loop
write(L, opcode_names(op));
write(L, ' ');
write(L, op_count(op));
writeline(data, L);
end loop;
for sp_func in dlx_sp_func_num loop
write(L, sp_func_names(sp_func));
write(L, ' ');
write(L, sp_func_count(sp_func));
writeline(data, L);
end loop;
for fp_func in dlx_fp_func_num loop
write(L, fp_func_names(fp_func));
write(L, ' ');
write(L, fp_func_count(fp_func));
writeline(data, L);
end loop;
end instrumentation_dump;
---------------------------------------------------------------------------
procedure write (address : in dlx_address;
data_width : in mem_width;
data : in dlx_word;
signal phi1, phi2 : in bit; -- 2-phase non-overlapping clks
signal reset : in bit; -- synchronous reset input
signal a : out dlx_address; -- address bus output
signal d : inout dlx_word_bus; -- bidirectional data bus
signal width : out mem_width; -- byte/halfword/word
signal write_enable : out bit; -- selects read/write cycle
signal mem_enable : out bit; -- starts memory cycle
signal ifetch : out bit; -- indicates instruction fetch
signal ready : in bit; -- status from memory system
Tpd_clk_out : in time -- clock to output delay
) is
begin
wait until phi1 = '1';
if reset = '1' then
return;
end if;
a <= address after Tpd_clk_out;
width <= data_width after Tpd_clk_out;
d <= data after Tpd_clk_out;
write_enable <= '1' after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
ifetch <= '0' after Tpd_clk_out;
loop
wait until phi2 = '0';
exit when ready = '1' or reset = '1';
end loop;
d <= null after Tpd_clk_out;
write_enable <= '0' after Tpd_clk_out;
mem_enable <= '0' after Tpd_clk_out;
end write;
procedure bus_read (address : in dlx_address;
data_width : in mem_width;
instr_fetch : in boolean;
data : out dlx_word;
signal phi1, phi2 : in bit; -- 2-phase non-overlapping clks
signal reset : in bit; -- synchronous reset input
signal a : out dlx_address; -- address bus output
signal d : inout dlx_word_bus; -- bidirectional data bus
signal width : out mem_width; -- byte/halfword/word
signal write_enable : out bit; -- selects read/write cycle
signal mem_enable : out bit; -- starts memory cycle
signal ifetch : out bit; -- indicates instruction eftch
signal ready : in bit; -- status from memory system
Tpd_clk_out : in time -- clock to output delay
) is
begin
wait until phi1 = '1';
if reset = '1' then
return;
end if;
a <= address after Tpd_clk_out;
width <= data_width after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
ifetch <= bit'val(boolean'pos(instr_fetch)) after Tpd_clk_out;
loop
wait until phi2 = '0';
exit when ready = '1' or reset = '1';
end loop;
data := d;
mem_enable <= '0' after Tpd_clk_out;
end bus_read;
begin -- interpreter
--
-- reset the processor
--
d <= null;
halt <= '0';
write_enable <= '0';
mem_enable <= '0';
reg(0) := X"0000_0000";
PC := X"0000_0000";
user_mode := false;
--
-- fetch-decode-execute loop
--
loop
--
-- fetch next instruction
--
if debug then
write(L, tag);
write(L, string'(": fetching instruction..."));
writeline(output, L);
end if;
--
bus_read(PC, width_word, true, IR,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
--
-- increment the PC to point to the following instruction
--
if debug then
write(L, tag);
write(L, string'(": incrementing PC..."));
writeline(output, L);
end if;
--
bv_add(PC, PC_incr, PC, overflow);
--
-- decode the instruction
--
if debug then
write(L, tag);
write(L, string'(": decoding instruction..."));
writeline(output, L);
end if;
--
IR_opcode_num := bv_to_natural(IR_opcode);
IR_sp_func_num := bv_to_natural(IR_sp_func);
IR_fp_func_num := bv_to_natural(IR_fp_func);
rs1 := bv_to_natural(IR_rs1);
rs2 := bv_to_natural(IR_rs2);
Itype_rd := bv_to_natural(IR_Itype_rd);
Rtype_rd := bv_to_natural(IR_Rtype_rd);
--
-------------------------------------------------------------------------
-- instrumentation: increment counter for decoded instruction
-------------------------------------------------------------------------
--
op_count(IR_opcode_num) := op_count(IR_opcode_num) + 1;
if IR_opcode = op_special then
sp_func_count(IR_sp_func_num) := sp_func_count(IR_sp_func_num) + 1;
elsif IR_opcode = op_fparith then
fp_func_count(IR_fp_func_num) := fp_func_count(IR_fp_func_num) + 1;
end if;
instr_count := instr_count + 1;
--
-------------------------------------------------------------------------
--
-- exectute
--
if debug then
write(L, tag);
write(L, string'(": executing instruction..."));
writeline(output, L);
end if;
--
case IR_opcode is
when op_special =>
case IR_sp_func is
WHEN sp_func_nop =>
null;
when sp_func_sll =>
reg(Rtype_rd) := bv_sll(reg(rs1), bv_to_natural(reg(rs2)(27 to 31)));
when sp_func_srl =>
reg(Rtype_rd) := bv_srl(reg(rs1), bv_to_natural(reg(rs2)(27 to 31)));
when sp_func_sra =>
reg(Rtype_rd) := bv_sra(reg(rs1), bv_to_natural(reg(rs2)(27 to 31)));
when sp_func_sequ =>
if reg(rs1) = reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sneu =>
if reg(rs1) /= reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sltu =>
if reg(rs1) < reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sgtu =>
if reg(rs1) > reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sleu =>
if reg(rs1) <= reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sgeu =>
if reg(rs1) >= reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_add =>
bv_add(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_addu =>
bv_addu(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_sub =>
bv_sub(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_subu =>
bv_subu(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_and =>
reg(Rtype_rd) := reg(rs1) and reg(rs2);
when sp_func_or =>
reg(Rtype_rd) := reg(rs1) or reg(rs2);
when sp_func_xor =>
reg(Rtype_rd) := reg(rs1) xor reg(rs2);
when sp_func_seq =>
if reg(rs1) = reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sne =>
if reg(rs1) /= reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_slt =>
if bv_lt(reg(rs1), reg(rs2)) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sgt =>
if bv_gt(reg(rs1), reg(rs2)) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sle =>
if bv_le(reg(rs1), reg(rs2)) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sge =>
if bv_ge(reg(rs1), reg(rs2)) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_movi2s =>
assert false
report "MOVI2S instruction not implemented" severity warning;
when sp_func_movs2i =>
assert false
report "MOVS2I instruction not implemented" severity warning;
when sp_func_movf =>
assert false
report "MOVF instruction not implemented" severity warning;
when sp_func_movd =>
assert false
report "MOVD instruction not implemented" severity warning;
when sp_func_movfp2i =>
reg(Rtype_rd) := fp_reg(rs1);
when sp_func_movi2fp =>
fp_reg(Rtype_rd) := reg(rs1);
when others =>
assert false
report "undefined special instruction function" severity error;
end case;
when op_fparith =>
case IR_fp_func is
when fp_func_mult =>
bv_mult(fp_reg(rs1), fp_reg(rs2), fp_reg(Rtype_rd), overflow);
when fp_func_multu =>
bv_multu(fp_reg(rs1), fp_reg(rs2), fp_reg(Rtype_rd), overflow);
when fp_func_div =>
bv_div(fp_reg(rs1), fp_reg(rs2), fp_reg(Rtype_rd), div_by_zero, overflow);
when fp_func_divu =>
bv_divu(fp_reg(rs1), fp_reg(rs2), fp_reg(Rtype_rd), div_by_zero);
when fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf |
fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd |
fp_func_cvtf2d | fp_func_cvtf2i | fp_func_cvtd2f |
fp_func_cvtd2i | fp_func_cvti2f | fp_func_cvti2d |
fp_func_eqf | fp_func_nef | fp_func_ltf | fp_func_gtf |
fp_func_lef | fp_func_gef | fp_func_eqd | fp_func_ned |
fp_func_ltd | fp_func_gtd | fp_func_led | fp_func_ged =>
assert false
report "floating point instructions not implemented" severity warning;
when others =>
assert false
report "undefined floating point instruction function" severity error;
end case;
when op_j =>
bv_add(PC, bv_sext(IR_immed26, 32), PC, overflow);
when op_jal =>
reg(link_reg) := PC;
bv_add(PC, bv_sext(IR_immed26, 32), PC, overflow);
when op_beqz =>
if reg(rs1) = X"0000_0000" then
bv_add(PC, bv_sext(IR_immed16, 32), PC, overflow);
end if;
when op_bnez =>
if reg(rs1) /= X"0000_0000" then
bv_add(PC, bv_sext(IR_immed16, 32), PC, overflow);
end if;
when op_bfpt =>
assert false
report "BFPT instruction not implemented" severity warning;
when op_bfpf =>
assert false
report "BFPF instruction not implemented" severity warning;
when op_addi =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_addui =>
bv_addu(reg(rs1), bv_zext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_subi =>
bv_sub(reg(rs1), bv_sext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_subui =>
bv_subu(reg(rs1), bv_zext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_slli =>
reg(Itype_rd) := bv_sll(reg(rs1), bv_to_natural(IR_immed16(11 to 15)));
when op_srli =>
reg(Itype_rd) := bv_srl(reg(rs1), bv_to_natural(IR_immed16(11 to 15)));
when op_srai =>
reg(Itype_rd) := bv_sra(reg(rs1), bv_to_natural(IR_immed16(11 to 15)));
when op_andi =>
reg(Itype_rd) := reg(rs1) and bv_zext(IR_immed16, 32);
when op_ori =>
reg(Itype_rd) := reg(rs1) or bv_zext(IR_immed16, 32);
when op_xori =>
reg(Itype_rd) := reg(rs1) xor bv_zext(IR_immed16, 32);
when op_lhi =>
reg(Itype_rd) := IR_immed16 & X"0000";
when op_rfe =>
assert false
report "RFE instruction not implemented" severity warning;
when op_trap =>
assert false
report "TRAP instruction encountered, execution halted"
severity note;
halt <= '1' after Tpd_clk_out;
---------------------------------------------------------------------
-- instrumentation: dump counters
---------------------------------------------------------------------
instrumentation_dump;
---------------------------------------------------------------------
wait until reset = '1';
exit;
when op_jr =>
PC := reg(rs1);
when op_jalr =>
reg(link_reg) := PC;
PC := reg(rs1);
when op_seqi =>
if reg(rs1) = bv_sext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_snei =>
if reg(rs1) /= bv_sext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_slti =>
if bv_lt(reg(rs1), bv_sext(IR_immed16, 32)) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sgti =>
if bv_gt(reg(rs1), bv_sext(IR_immed16, 32)) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_slei =>
if bv_le(reg(rs1), bv_sext(IR_immed16, 32)) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sgei =>
if bv_ge(reg(rs1), bv_sext(IR_immed16, 32)) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_lb =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_byte, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
case ls_2_addr_bits'(mem_addr(1 downto 0)) is
when B"00" =>
reg(Itype_rd) := bv_sext(mem_data(0 to 7), 32);
when B"01" =>
reg(Itype_rd) := bv_sext(mem_data(8 to 15), 32);
when B"10" =>
reg(Itype_rd) := bv_sext(mem_data(16 to 23), 32);
when B"11" =>
reg(Itype_rd) := bv_sext(mem_data(24 to 31), 32);
end case;
when op_lh =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_halfword, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
if mem_addr(1) = '0' then
reg(Itype_rd) := bv_sext(mem_data(0 to 15), 32);
else
reg(Itype_rd) := bv_sext(mem_data(16 to 31), 32);
end if;
when op_lw =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_word, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
reg(Itype_rd) := mem_data;
when op_lbu =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_byte, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
case ls_2_addr_bits'(mem_addr(1 downto 0)) is
when B"00" =>
reg(Itype_rd) := bv_zext(mem_data(0 to 7), 32);
when B"01" =>
reg(Itype_rd) := bv_zext(mem_data(8 to 15), 32);
when B"10" =>
reg(Itype_rd) := bv_zext(mem_data(16 to 23), 32);
when B"11" =>
reg(Itype_rd) := bv_zext(mem_data(24 to 31), 32);
end case;
when op_lhu =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_halfword, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
if mem_addr(1) = '0' then
reg(Itype_rd) := bv_zext(mem_data(0 to 15), 32);
else
reg(Itype_rd) := bv_zext(mem_data(16 to 31), 32);
end if;
when op_lf =>
assert false
report "LF instruction not implemented" severity warning;
when op_ld =>
assert false
report "LD instruction not implemented" severity warning;
when op_sb =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
mem_data := X"0000_0000";
case ls_2_addr_bits'(mem_addr(1 downto 0)) is
when B"00" =>
mem_data(0 to 7) := reg(Itype_rd)(0 to 7);
when B"01" =>
mem_data(8 to 15) := reg(Itype_rd)(0 to 7);
when B"10" =>
mem_data(16 to 23) := reg(Itype_rd)(0 to 7);
when B"11" =>
mem_data(24 to 31) := reg(Itype_rd)(0 to 7);
end case;
write(mem_addr, width_halfword, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
when op_sh =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
mem_data := X"0000_0000";
if mem_addr(1) = '0' then
mem_data(0 to 15) := reg(Itype_rd)(0 to 15);
else
mem_data(16 to 31) := reg(Itype_rd)(0 to 15);
end if;
write(mem_addr, width_halfword, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
when op_sw =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
mem_data := reg(Itype_rd);
write(mem_addr, width_word, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
when op_sf =>
assert false
report "SF instruction not implemented" severity warning;
when op_sd =>
assert false
report "SD instruction not implemented" severity warning;
when op_sequi =>
if reg(rs1) = bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sneui =>
if reg(rs1) /= bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sltui =>
if reg(rs1) < bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sgtui =>
if reg(rs1) > bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sleui =>
if reg(rs1) <= bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sgeui =>
if reg(rs1) >= bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when others =>
assert false
report "undefined instruction" severity error;
end case;
--
-- fix up R0 in case it was overwritten
--
reg(0) := X"0000_0000";
--
if debug then
write(L, tag);
write(L, string'(": end of execution"));
writeline(output, L);
end if;
if instr_count mod 100 = 0 then
write(L, tag);
write(L, string'(": executed "));
write(L, instr_count);
write(L, string'(" instructions"));
writeline(output, L);
end if;
--
end loop;
--
-- loop is only exited when reset active: wait until it goes inactive
--
assert reset = '1'
report "reset code reached with reset = '0'" severity error;
wait until phi2 = '0' and reset = '0';
--
-- process interpreter now starts again from beginning
--
end process interpreter;
end instrumented;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Description: Prefix AND computation: y(i) <= '1' when x(i downto 0) = (i downto 0 => '1') else '0'
-- This implementation uses carry chains for wider implementations.
--
-- Authors: Thomas B. Preusser
-- =============================================================================
-- Copyright 2007-2014 Technische Universität Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
entity arith_prefix_and is
generic (
N : positive
);
port (
x : in std_logic_vector(N-1 downto 0);
y : out std_logic_vector(N-1 downto 0)
);
end arith_prefix_and;
architecture rtl of arith_prefix_and is
type T_VENDOR is (VENDOR_XILINX, VENDOR_ALTERA);
constant VENDOR : T_VENDOR := VENDOR_XILINX;
begin
y(0) <= x(0);
gen1: if N > 1 generate
signal p : unsigned(N-1 downto 1);
begin
p(1) <= x(0) and x(1);
gen2: if N > 2 generate
p(N-1 downto 2) <= unsigned(x(N-1 downto 2));
-- Generic Carry Chain through Addition
genGeneric: if VENDOR /= VENDOR_XILINX generate
signal s : std_logic_vector(N downto 1);
begin
s <= std_logic_vector(('0' & p) + 1);
y(N-1 downto 2) <= s(N downto 3) xor ('0' & x(N-1 downto 3));
end generate genGeneric;
-- Direct Carry Chain by MUXCY Instantiation
genXilinx: if VENDOR = VENDOR_XILINX generate
-- component MUXCY
-- port (
-- S : in std_logic;
-- DI : in std_logic;
-- CI : in std_logic;
-- O : out std_logic
-- );
-- end component;
signal c : std_logic_vector(N-1 downto 0);
begin
c(0) <= '1';
genChain: for i in 1 to N-1 generate
mux : entity unisim.MUXCY
port map (
S => p(i),
DI => '0',
CI => c(i-1),
O => c(i)
);
end generate genChain;
y(N-1 downto 2) <= c(N-1 downto 2);
end generate genXilinx;
end generate gen2;
y(1) <= p(1);
end generate gen1;
end rtl;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Description: Prefix AND computation: y(i) <= '1' when x(i downto 0) = (i downto 0 => '1') else '0'
-- This implementation uses carry chains for wider implementations.
--
-- Authors: Thomas B. Preusser
-- =============================================================================
-- Copyright 2007-2014 Technische Universität Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
entity arith_prefix_and is
generic (
N : positive
);
port (
x : in std_logic_vector(N-1 downto 0);
y : out std_logic_vector(N-1 downto 0)
);
end arith_prefix_and;
architecture rtl of arith_prefix_and is
type T_VENDOR is (VENDOR_XILINX, VENDOR_ALTERA);
constant VENDOR : T_VENDOR := VENDOR_XILINX;
begin
y(0) <= x(0);
gen1: if N > 1 generate
signal p : unsigned(N-1 downto 1);
begin
p(1) <= x(0) and x(1);
gen2: if N > 2 generate
p(N-1 downto 2) <= unsigned(x(N-1 downto 2));
-- Generic Carry Chain through Addition
genGeneric: if VENDOR /= VENDOR_XILINX generate
signal s : std_logic_vector(N downto 1);
begin
s <= std_logic_vector(('0' & p) + 1);
y(N-1 downto 2) <= s(N downto 3) xor ('0' & x(N-1 downto 3));
end generate genGeneric;
-- Direct Carry Chain by MUXCY Instantiation
genXilinx: if VENDOR = VENDOR_XILINX generate
-- component MUXCY
-- port (
-- S : in std_logic;
-- DI : in std_logic;
-- CI : in std_logic;
-- O : out std_logic
-- );
-- end component;
signal c : std_logic_vector(N-1 downto 0);
begin
c(0) <= '1';
genChain: for i in 1 to N-1 generate
mux : entity unisim.MUXCY
port map (
S => p(i),
DI => '0',
CI => c(i-1),
O => c(i)
);
end generate genChain;
y(N-1 downto 2) <= c(N-1 downto 2);
end generate genXilinx;
end generate gen2;
y(1) <= p(1);
end generate gen1;
end rtl;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Description: Prefix AND computation: y(i) <= '1' when x(i downto 0) = (i downto 0 => '1') else '0'
-- This implementation uses carry chains for wider implementations.
--
-- Authors: Thomas B. Preusser
-- =============================================================================
-- Copyright 2007-2014 Technische Universität Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
entity arith_prefix_and is
generic (
N : positive
);
port (
x : in std_logic_vector(N-1 downto 0);
y : out std_logic_vector(N-1 downto 0)
);
end arith_prefix_and;
architecture rtl of arith_prefix_and is
type T_VENDOR is (VENDOR_XILINX, VENDOR_ALTERA);
constant VENDOR : T_VENDOR := VENDOR_XILINX;
begin
y(0) <= x(0);
gen1: if N > 1 generate
signal p : unsigned(N-1 downto 1);
begin
p(1) <= x(0) and x(1);
gen2: if N > 2 generate
p(N-1 downto 2) <= unsigned(x(N-1 downto 2));
-- Generic Carry Chain through Addition
genGeneric: if VENDOR /= VENDOR_XILINX generate
signal s : std_logic_vector(N downto 1);
begin
s <= std_logic_vector(('0' & p) + 1);
y(N-1 downto 2) <= s(N downto 3) xor ('0' & x(N-1 downto 3));
end generate genGeneric;
-- Direct Carry Chain by MUXCY Instantiation
genXilinx: if VENDOR = VENDOR_XILINX generate
-- component MUXCY
-- port (
-- S : in std_logic;
-- DI : in std_logic;
-- CI : in std_logic;
-- O : out std_logic
-- );
-- end component;
signal c : std_logic_vector(N-1 downto 0);
begin
c(0) <= '1';
genChain: for i in 1 to N-1 generate
mux : entity unisim.MUXCY
port map (
S => p(i),
DI => '0',
CI => c(i-1),
O => c(i)
);
end generate genChain;
y(N-1 downto 2) <= c(N-1 downto 2);
end generate genXilinx;
end generate gen2;
y(1) <= p(1);
end generate gen1;
end rtl;
|
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 28672)
`protect data_block
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bQ==
`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity bistableelement_tb is
end bistableelement_tb;
architecture TB_ARCHITECTURE of bistableelement_tb is
-- Component declaration of the tested unit
component bistableelement
port(
Q : out STD_LOGIC;
nQ : out STD_LOGIC );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
-- Observed signals - signals mapped to the output ports of tested entity
signal Q : STD_LOGIC;
signal nQ : STD_LOGIC;
-- Add your code here ...
begin
-- Unit Under Test port map
UUT : bistableelement
port map (
Q => Q,
nQ => nQ
);
-- Add your stimulus here ...
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_bistableelement of bistableelement_tb is
for TB_ARCHITECTURE
for UUT : bistableelement
use entity work.bistableelement(bistableelement);
end for;
end for;
end TESTBENCH_FOR_bistableelement;
|
entity FIFO is
port ( );
end entity FIFO;
entity FIFO is
port (
);
end entity FIFO;
entity FIFO is
port
(
)
;
end entity FIFO;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: uart
-- File: uart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UART types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package uart is
type uart_in_type is record
rxd : std_ulogic;
ctsn : std_ulogic;
extclk : std_ulogic;
end record;
type uart_in_vector_type is array (natural range <>) of uart_in_type;
type uart_out_type is record
rtsn : std_ulogic;
txd : std_ulogic;
scaler : std_logic_vector(31 downto 0);
txen : std_ulogic;
flow : std_ulogic;
rxen : std_ulogic;
end record;
type uart_out_vector_type is array (natural range <>) of uart_out_type;
component apbuart
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
parity : integer := 1;
flow : integer := 1;
fifosize : integer range 1 to 32 := 1;
abits : integer := 8;
sbits : integer range 12 to 32 := 12);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in uart_in_type;
uarto : out uart_out_type);
end component;
component ahbuart
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
uarti : in uart_in_type;
uarto : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type);
end component;
end;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr:user:uart_transceiver:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_uart_transceiver_0_0 IS
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END DemoInterconnect_uart_transceiver_0_0;
ARCHITECTURE DemoInterconnect_uart_transceiver_0_0_arch OF DemoInterconnect_uart_transceiver_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_uart_transceiver_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT uart_top IS
GENERIC (
CLK_FREQ : INTEGER;
BAUD_RATE : INTEGER
);
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END COMPONENT uart_top;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_uart_transceiver_0_0_arch: ARCHITECTURE IS "uart_top,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_uart_transceiver_0_0_arch : ARCHITECTURE IS "DemoInterconnect_uart_transceiver_0_0,uart_top,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF i_Clk: SIGNAL IS "XIL_INTERFACENAME i_Clk, FREQ_HZ 12000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF i_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_Clk CLK";
BEGIN
U0 : uart_top
GENERIC MAP (
CLK_FREQ => 12000000,
BAUD_RATE => 115200
)
PORT MAP (
i_Clk => i_Clk,
i_RX_Serial => i_RX_Serial,
o_RX_Done => o_RX_Done,
o_RX_Byte => o_RX_Byte,
i_TX_Load => i_TX_Load,
i_TX_Byte => i_TX_Byte,
o_TX_Active => o_TX_Active,
o_TX_Serial => o_TX_Serial,
o_TX_Done => o_TX_Done
);
END DemoInterconnect_uart_transceiver_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package utils_pkg is
-- Calculates the number of bits required to encode the given number
--
-- Note that this function is not intended to synthesize directly into
-- hardware, rather it is used to generate constants for synthesized
-- hardware.
--
-- Example:
-- entity foo is
-- generic(
-- ABC : positive);
-- port(
-- xzy : out std_logic_vector(required_bits(ABC) downto 0));
-- end foo;
function required_bits (value : natural) return natural;
-- Another function which does the same, up to 32 bits
function log2 (val : integer) return natural;
----------------------------------------------------------------------------
function max(L : integer;
R : integer)
return integer;
function minn(L : integer;
R : integer)
return integer;
----------------------------------------------------------------------------
-- replacement for std_logic_arith
-- works with unsigneds
-- see http://www.lothar-miller.de/s9y/archives/14-Numeric_Std.html
function conv_integer(
vec : std_logic_vector)
return integer;
function conv_std_logic_vector (
int : natural;
len : natural)
return std_logic_vector;
----------------------------------------------------------------------------
component clock_divider is
generic (
DIV : positive);
port (
clk_out_p : out std_logic;
clk : in std_logic);
end component;
-- Requires MUL <= DIV
component fractional_clock_divider is
generic (
DIV : positive;
MUL : positive;
WIDTH : positive := 16);
port (
clk_out_p : out std_logic;
clk : in std_logic);
end component fractional_clock_divider;
-- Requires mul <= div
component fractional_clock_divider_variable is
generic (
WIDTH : positive);
port (
div : in std_logic_vector(WIDTH-1 downto 0);
mul : in std_logic_vector(WIDTH-1 downto 0);
clk_out_p : out std_logic;
clk : in std_logic);
end component fractional_clock_divider_variable;
----------------------------------------------------------------------------
component event_hold_stage is
port (
dout_p : out std_logic;
din_p : in std_logic;
period_p : in std_logic;
clk : in std_logic);
end component event_hold_stage;
component edge_detect is
port (
async_sig : in std_logic;
clk : in std_logic;
rise : out std_logic;
fall : out std_logic);
end component edge_detect;
----------------------------------------------------------------------------
component dff is
port (
dout_p : out std_logic;
din_p : in std_logic;
set_p : in std_logic;
reset_p : in std_logic;
ce_p : in std_logic;
clk : in std_logic);
end component dff;
end package utils_pkg;
package body utils_pkg is
function required_bits (value : natural) return natural is
begin
if value <= 0 then
return 0;
elsif value = 1 then
return 1;
elsif value < 8 then
return integer(ceil(log2(real(value))));
else
-- FIXME: Why is this hack necessary?
-- Otherwise the values for 2**x (x >= 3) are calculated wrong.
-- E.g.:
-- required_bits(8) = 3 != 4
-- required_bits(16) = 4 != 5
-- see ../tb/utils_tb.vhd
return integer(ceil(log2(real(value) + 0.5)));
end if;
end function;
function log2 (val : integer) return natural is
variable res : positive;
begin -- log2
for i in 1 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop; -- i
return res;
end log2;
----------------------------------------------------------------------------
function max(L : integer;
R : integer)
return integer is
begin -- max
if L > R then
return L;
else
return R;
end if;
end max;
function minn(L : integer;
R : integer)
return integer is
begin -- min
if L < R then
return L;
else
return R;
end if;
end minn;
----------------------------------------------------------------------------
function conv_integer(
vec : std_logic_vector)
return integer is
begin
return to_integer(unsigned(vec));
end conv_integer;
function conv_std_logic_vector (
int : natural;
len : natural)
return std_logic_vector is
begin -- conv_std_logic_vector
return std_logic_vector(to_unsigned(int, len));
end conv_std_logic_vector;
end package body utils_pkg;
|
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