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--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: timer
-- Date:2015-02-19
-- Author: Gideon
-- Description: Generic timeout timer
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timer is
generic (
g_reset : std_logic := '0';
g_width : natural := 10 );
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
start_value : in unsigned(g_width-1 downto 0);
timeout : out std_logic );
end entity;
architecture arch of timer is
signal running : std_logic;
signal count : unsigned(g_width-1 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
if start = '1' then
count <= start_value;
running <= '1';
timeout <= '0';
elsif running = '1' then
count <= count - 1;
end if;
if count = 1 then
timeout <= '1';
running <= '0';
end if;
if reset='1' then
count <= (others => '0');
running <= '0';
timeout <= g_reset;
end if;
end if;
end process;
end arch;
|
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: timer
-- Date:2015-02-19
-- Author: Gideon
-- Description: Generic timeout timer
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timer is
generic (
g_reset : std_logic := '0';
g_width : natural := 10 );
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
start_value : in unsigned(g_width-1 downto 0);
timeout : out std_logic );
end entity;
architecture arch of timer is
signal running : std_logic;
signal count : unsigned(g_width-1 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
if start = '1' then
count <= start_value;
running <= '1';
timeout <= '0';
elsif running = '1' then
count <= count - 1;
end if;
if count = 1 then
timeout <= '1';
running <= '0';
end if;
if reset='1' then
count <= (others => '0');
running <= '0';
timeout <= g_reset;
end if;
end if;
end process;
end arch;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ea_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ea_e-rtl-a.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: inst_ea_e-rtl-a.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ea_e
--
architecture rtl of inst_ea_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_eaa_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_eaa_e
mbist_clut_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
mbist_fifo_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
c_addr_i : in std_ulogic_vector(12 downto 0);
c_bus_i : in std_ulogic_vector(31 downto 0); -- CBUSinterface
video_p_0 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_0 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_1 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_10 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_11 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_12 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_13 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_14 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_15 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_16 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_17 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_18 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_19 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_2 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_20 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_21 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_22 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_23 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_24 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_25 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_26 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_27 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_28 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_29 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_3 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_30 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_31 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_4 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_5 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_6 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_7 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_8 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_9 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p : in std_ulogic_vector(30 downto 0);
unsplice_a1_no3 : in std_ulogic_vector(127 downto 0); -- leaves 3 unconnected
unsplice_a2_all128 : in std_ulogic_vector(127 downto 0); -- full 128 bit port
unsplice_a3_up100 : in std_ulogic_vector(100 downto 0); -- connect 100 bits from 0
unsplice_a4_mid100 : in std_ulogic_vector(97 downto 0); -- connect mid 100 bits
unsplice_a5_midp100 : in std_ulogic_vector(99 downto 2); -- connect mid 100 bits
unsplice_bad_a : in std_ulogic_vector(1 downto 0);
unsplice_bad_b : in std_ulogic_vector(3 downto 0); -- # conflict
widemerge_a1_p : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_eaa_e
);
end component;
-- ---------
component inst_eab_e
-- No Generated Generics
-- Generated Generics for Entity inst_eab_e
-- End of Generated Generics for Entity inst_eab_e
port (
-- Generated Port for Entity inst_eab_e
v_select : in std_ulogic_vector(5 downto 0); -- VPUinterface
c_add : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0); -- CBUSinterface
video_p_1 : in std_ulogic
-- End of Generated Port for Entity inst_eab_e
);
end component;
-- ---------
component inst_eac_e
-- No Generated Generics
-- Generated Generics for Entity inst_eac_e
-- End of Generated Generics for Entity inst_eac_e
port (
-- Generated Port for Entity inst_eac_e
adp_bist_fail : out std_ulogic;
cpu_bist_fail : out std_ulogic;
ema_bist_fail : out std_ulogic;
ifu_bist_fail : out std_ulogic;
mcu_bist_fail : out std_ulogic;
pdu_bist_fail0 : out std_ulogic;
pdu_bist_fail1 : out std_ulogic;
tsd_bist_fail : out std_ulogic;
cp_lcmd : in std_ulogic_vector(6 downto 0); -- GuestBusLBC(memorymappedI/O)Interface
cp_lcmd_p : in std_ulogic_vector(6 downto 0); -- Signal name != port name
cp_lcmd_2 : in std_ulogic_vector(6 downto 0); -- Second way to wire to zero / GuestBusLBC(memorymappedI/O)Interface
c_addr : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0); -- CBUSinterface
cvi_sbist_fail0 : in std_ulogic;
cvi_sbist_fail1 : in std_ulogic;
ga_sbist_fail0 : in std_ulogic;
ga_sbist_fail1 : in std_ulogic;
video_p_2 : in std_ulogic
-- End of Generated Port for Entity inst_eac_e
);
end component;
-- ---------
component inst_ead_e
-- No Generated Generics
-- Generated Generics for Entity inst_ead_e
-- End of Generated Generics for Entity inst_ead_e
port (
-- Generated Port for Entity inst_ead_e
video_p_3 : in std_ulogic
-- End of Generated Port for Entity inst_ead_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic0_2 : std_ulogic;
signal mix_logic0_bus_0 : std_ulogic_vector(5 downto 0);
signal mix_logic0_bus_1 : std_ulogic_vector(5 downto 0);
signal c_addr : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal c_bus_in : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal cp_lcmd : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal cp_lcmd_2 : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
constant cp_lcmd_2_tolow_c : std_ulogic_vector(5 downto 0) := ( others => '0' );
signal cp_lcmd_2_tolow : std_ulogic_vector(5 downto 0);
signal cp_lcmd_3 : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal tmi_sbist_fail : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a1_no3 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a2_all128 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a3_up100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a4_mid100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a5_midp100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_bad_a : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_bad_b : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal v_select : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal widemerge_a1 : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal widesig : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_10 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_11 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_19 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_20 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_21 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_22 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_23 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_24 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_25 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_26 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_27 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_28 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_29 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_30 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_6 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_7 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_8 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_9 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic0_2 <= '0';
mix_logic0_bus_0 <= ( others => '0' );
mix_logic0_bus_1 <= ( others => '0' );
c_addr <= p_mix_c_addr_12_0_gi; -- __I_I_BUS_PORT
c_bus_in <= p_mix_c_bus_in_31_0_gi; -- __I_I_BUS_PORT
cp_lcmd(6) <= p_mix_cp_lcmd_6_6_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
cp_lcmd_2(6) <= p_mix_cp_lcmd_2_6_6_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
cp_lcmd_2_tolow <= cp_lcmd_2_tolow_c;
cp_lcmd_3(6) <= p_mix_cp_lcmd_3_6_6_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
tmi_sbist_fail(11 downto 10) <= p_mix_tmi_sbist_fail_11_10_gi(1 downto 0); -- __I_I_SLICE_PORT
p_mix_tmi_sbist_fail_9_0_go(9 downto 0) <= tmi_sbist_fail(9 downto 0); -- __I_O_SLICE_PORT
unsplice_a1_no3(125 downto 0) <= p_mix_unsplice_a1_no3_125_0_gi(125 downto 0); -- __I_I_SLICE_PORT
unsplice_a1_no3(127) <= p_mix_unsplice_a1_no3_127_127_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
unsplice_a2_all128 <= p_mix_unsplice_a2_all128_127_0_gi; -- __I_I_BUS_PORT
unsplice_a3_up100(100 downto 0) <= p_mix_unsplice_a3_up100_100_0_gi(100 downto 0); -- __I_I_SLICE_PORT
unsplice_a4_mid100(99 downto 2) <= p_mix_unsplice_a4_mid100_99_2_gi(97 downto 0); -- __I_I_SLICE_PORT
unsplice_a5_midp100(99 downto 2) <= p_mix_unsplice_a5_midp100_99_2_gi(97 downto 0); -- __I_I_SLICE_PORT
unsplice_bad_a(1) <= p_mix_unsplice_bad_a_1_1_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
unsplice_bad_b(1 downto 0) <= p_mix_unsplice_bad_b_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
v_select(5) <= p_mix_v_select_5_5_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
v_select(2) <= p_mix_v_select_2_2_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
widemerge_a1 <= p_mix_widemerge_a1_31_0_gi; -- __I_I_BUS_PORT
widesig <= p_mix_widesig_31_0_gi; -- __I_I_BUS_PORT
widesig_r_0 <= p_mix_widesig_r_0_gi; -- __I_I_BIT_PORT
widesig_r_1 <= p_mix_widesig_r_1_gi; -- __I_I_BIT_PORT
widesig_r_10 <= p_mix_widesig_r_10_gi; -- __I_I_BIT_PORT
widesig_r_11 <= p_mix_widesig_r_11_gi; -- __I_I_BIT_PORT
widesig_r_12 <= p_mix_widesig_r_12_gi; -- __I_I_BIT_PORT
widesig_r_13 <= p_mix_widesig_r_13_gi; -- __I_I_BIT_PORT
widesig_r_14 <= p_mix_widesig_r_14_gi; -- __I_I_BIT_PORT
widesig_r_15 <= p_mix_widesig_r_15_gi; -- __I_I_BIT_PORT
widesig_r_16 <= p_mix_widesig_r_16_gi; -- __I_I_BIT_PORT
widesig_r_17 <= p_mix_widesig_r_17_gi; -- __I_I_BIT_PORT
widesig_r_18 <= p_mix_widesig_r_18_gi; -- __I_I_BIT_PORT
widesig_r_19 <= p_mix_widesig_r_19_gi; -- __I_I_BIT_PORT
widesig_r_2 <= p_mix_widesig_r_2_gi; -- __I_I_BIT_PORT
widesig_r_20 <= p_mix_widesig_r_20_gi; -- __I_I_BIT_PORT
widesig_r_21 <= p_mix_widesig_r_21_gi; -- __I_I_BIT_PORT
widesig_r_22 <= p_mix_widesig_r_22_gi; -- __I_I_BIT_PORT
widesig_r_23 <= p_mix_widesig_r_23_gi; -- __I_I_BIT_PORT
widesig_r_24 <= p_mix_widesig_r_24_gi; -- __I_I_BIT_PORT
widesig_r_25 <= p_mix_widesig_r_25_gi; -- __I_I_BIT_PORT
widesig_r_26 <= p_mix_widesig_r_26_gi; -- __I_I_BIT_PORT
widesig_r_27 <= p_mix_widesig_r_27_gi; -- __I_I_BIT_PORT
widesig_r_28 <= p_mix_widesig_r_28_gi; -- __I_I_BIT_PORT
widesig_r_29 <= p_mix_widesig_r_29_gi; -- __I_I_BIT_PORT
widesig_r_3 <= p_mix_widesig_r_3_gi; -- __I_I_BIT_PORT
widesig_r_30 <= p_mix_widesig_r_30_gi; -- __I_I_BIT_PORT
widesig_r_4 <= p_mix_widesig_r_4_gi; -- __I_I_BIT_PORT
widesig_r_5 <= p_mix_widesig_r_5_gi; -- __I_I_BIT_PORT
widesig_r_6 <= p_mix_widesig_r_6_gi; -- __I_I_BIT_PORT
widesig_r_7 <= p_mix_widesig_r_7_gi; -- __I_I_BIT_PORT
widesig_r_8 <= p_mix_widesig_r_8_gi; -- __I_I_BIT_PORT
widesig_r_9 <= p_mix_widesig_r_9_gi; -- __I_I_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_eaa
inst_eaa: inst_eaa_e
port map (
-- __E_PRINTCONN unsplice_bad_a => unsplice_bad_a
c_addr_i => c_addr,
c_bus_i => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
mbist_clut_fail_o => tmi_sbist_fail(8),
mbist_fifo_fail_o => tmi_sbist_fail(9),
unsplice_a1_no3(1 downto 0) => unsplice_a1_no3(1 downto 0), -- leaves 3 unconnected
unsplice_a1_no3(127 downto 4) => unsplice_a1_no3(125 downto 2), -- leaves 3 unconnected
unsplice_a1_no3(2) => unsplice_a1_no3(127), -- leaves 3 unconnected
unsplice_a2_all128 => unsplice_a2_all128, -- full 128 bit port
unsplice_a3_up100 => unsplice_a3_up100(100 downto 0), -- connect 100 bits from 0
unsplice_a4_mid100 => unsplice_a4_mid100(99 downto 2), -- connect mid 100 bits
unsplice_a5_midp100 => unsplice_a5_midp100(99 downto 2), -- connect mid 100 bits
unsplice_bad_b(1 downto 0) => unsplice_bad_b(1 downto 0), -- # conflict
unsplice_bad_b(3 downto 2) => unsplice_bad_b(1 downto 0), -- # conflict
video_p_0 => video_i(0),
widemerge_a1_p => widemerge_a1,
widesig_p(0) => widesig_r_0, -- __I_BIT_TO_BUSPORT
widesig_p(1) => widesig_r_1, -- __I_BIT_TO_BUSPORT
widesig_p(10) => widesig_r_10, -- __I_BIT_TO_BUSPORT
widesig_p(11) => widesig_r_11, -- __I_BIT_TO_BUSPORT
widesig_p(12) => widesig_r_12, -- __I_BIT_TO_BUSPORT
widesig_p(13) => widesig_r_13, -- __I_BIT_TO_BUSPORT
widesig_p(14) => widesig_r_14, -- __I_BIT_TO_BUSPORT
widesig_p(15) => widesig_r_15, -- __I_BIT_TO_BUSPORT
widesig_p(16) => widesig_r_16, -- __I_BIT_TO_BUSPORT
widesig_p(17) => widesig_r_17, -- __I_BIT_TO_BUSPORT
widesig_p(18) => widesig_r_18, -- __I_BIT_TO_BUSPORT
widesig_p(19) => widesig_r_19, -- __I_BIT_TO_BUSPORT
widesig_p(2) => widesig_r_2, -- __I_BIT_TO_BUSPORT
widesig_p(20) => widesig_r_20, -- __I_BIT_TO_BUSPORT
widesig_p(21) => widesig_r_21, -- __I_BIT_TO_BUSPORT
widesig_p(22) => widesig_r_22, -- __I_BIT_TO_BUSPORT
widesig_p(23) => widesig_r_23, -- __I_BIT_TO_BUSPORT
widesig_p(24) => widesig_r_24, -- __I_BIT_TO_BUSPORT
widesig_p(25) => widesig_r_25, -- __I_BIT_TO_BUSPORT
widesig_p(26) => widesig_r_26, -- __I_BIT_TO_BUSPORT
widesig_p(27) => widesig_r_27, -- __I_BIT_TO_BUSPORT
widesig_p(28) => widesig_r_28, -- __I_BIT_TO_BUSPORT
widesig_p(29) => widesig_r_29, -- __I_BIT_TO_BUSPORT
widesig_p(3) => widesig_r_3, -- __I_BIT_TO_BUSPORT
widesig_p(30) => widesig_r_30, -- __I_BIT_TO_BUSPORT
widesig_p(4) => widesig_r_4, -- __I_BIT_TO_BUSPORT
widesig_p(5) => widesig_r_5, -- __I_BIT_TO_BUSPORT
widesig_p(6) => widesig_r_6, -- __I_BIT_TO_BUSPORT
widesig_p(7) => widesig_r_7, -- __I_BIT_TO_BUSPORT
widesig_p(8) => widesig_r_8, -- __I_BIT_TO_BUSPORT
widesig_p(9) => widesig_r_9, -- __I_BIT_TO_BUSPORT
widesig_p_0 => widesig(0),
widesig_p_1 => widesig(1),
widesig_p_10 => widesig(10),
widesig_p_11 => widesig(11),
widesig_p_12 => widesig(12),
widesig_p_13 => widesig(13),
widesig_p_14 => widesig(14),
widesig_p_15 => widesig(15),
widesig_p_16 => widesig(16),
widesig_p_17 => widesig(17),
widesig_p_18 => widesig(18),
widesig_p_19 => widesig(19),
widesig_p_2 => widesig(2),
widesig_p_20 => widesig(20),
widesig_p_21 => widesig(21),
widesig_p_22 => widesig(22),
widesig_p_23 => widesig(23),
widesig_p_24 => widesig(24),
widesig_p_25 => widesig(25),
widesig_p_26 => widesig(26),
widesig_p_27 => widesig(27),
widesig_p_28 => widesig(28),
widesig_p_29 => widesig(29),
widesig_p_3 => widesig(3),
widesig_p_30 => widesig(30),
widesig_p_31 => widesig(31),
widesig_p_4 => widesig(4),
widesig_p_5 => widesig(5),
widesig_p_6 => widesig(6),
widesig_p_7 => widesig(7),
widesig_p_8 => widesig(8),
widesig_p_9 => widesig(9)
);
-- End of Generated Instance Port Map for inst_eaa
-- Generated Instance Port Map for inst_eab
inst_eab: inst_eab_e
port map (
c_add => c_addr,
c_bus_in => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
v_select(0) => mix_logic0_2, -- __I_BIT_TO_BUSPORT
v_select(1) => mix_logic0_2, -- __I_BIT_TO_BUSPORT
v_select(2) => v_select(2), -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
v_select(3) => mix_logic0_2, -- __I_BIT_TO_BUSPORT
v_select(4) => mix_logic0_2, -- __I_BIT_TO_BUSPORT
v_select(5) => v_select(5), -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
video_p_1 => video_i(1)
);
-- End of Generated Instance Port Map for inst_eab
-- Generated Instance Port Map for inst_eac
inst_eac: inst_eac_e
port map (
adp_bist_fail => tmi_sbist_fail(0),
c_addr => c_addr,
c_bus_in => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
cp_lcmd(5 downto 0) => mix_logic0_bus_0, -- __W_PORT
cp_lcmd(6) => cp_lcmd(6), -- GuestBusLBC(memorymappedI/O)Interface
cp_lcmd_2(5 downto 0) => cp_lcmd_2_tolow, -- __W_PORT
cp_lcmd_2(6) => cp_lcmd_2(6), -- Second way to wire to zero / GuestBusLBC(memorymappedI/O)Interface
cp_lcmd_p(5 downto 0) => mix_logic0_bus_1, -- __W_PORT
cp_lcmd_p(6) => cp_lcmd_3(6), -- Signal name != port name
cpu_bist_fail => tmi_sbist_fail(1),
cvi_sbist_fail0 => tmi_sbist_fail(10),
cvi_sbist_fail1 => tmi_sbist_fail(11),
ema_bist_fail => tmi_sbist_fail(7),
ga_sbist_fail0 => tmi_sbist_fail(8),
ga_sbist_fail1 => tmi_sbist_fail(9),
ifu_bist_fail => tmi_sbist_fail(6),
mcu_bist_fail => tmi_sbist_fail(2),
pdu_bist_fail0 => tmi_sbist_fail(3),
pdu_bist_fail1 => tmi_sbist_fail(4),
tsd_bist_fail => tmi_sbist_fail(5),
video_p_2 => video_i(2)
);
-- End of Generated Instance Port Map for inst_eac
-- Generated Instance Port Map for inst_ead
inst_ead: inst_ead_e
port map (
video_p_3 => video_i(3)
);
-- End of Generated Instance Port Map for inst_ead
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_tb_03_05.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_03_05 is
end entity test_bench_03_05;
architecture test_counter_behavior of test_bench_03_05 is
signal clk, reset : bit := '0';
signal count : natural;
begin
dut : entity work.counter(behavior)
port map ( clk => clk, reset => reset, count => count );
stimulus : process is
begin
for cycle_count in 1 to 5 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
reset <= '1' after 15 ns;
for cycle_count in 1 to 5 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
reset <= '0' after 15 ns;
for cycle_count in 1 to 30 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
wait;
end process stimulus;
end architecture test_counter_behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_tb_03_05.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_03_05 is
end entity test_bench_03_05;
architecture test_counter_behavior of test_bench_03_05 is
signal clk, reset : bit := '0';
signal count : natural;
begin
dut : entity work.counter(behavior)
port map ( clk => clk, reset => reset, count => count );
stimulus : process is
begin
for cycle_count in 1 to 5 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
reset <= '1' after 15 ns;
for cycle_count in 1 to 5 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
reset <= '0' after 15 ns;
for cycle_count in 1 to 30 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
wait;
end process stimulus;
end architecture test_counter_behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_tb_03_05.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_03_05 is
end entity test_bench_03_05;
architecture test_counter_behavior of test_bench_03_05 is
signal clk, reset : bit := '0';
signal count : natural;
begin
dut : entity work.counter(behavior)
port map ( clk => clk, reset => reset, count => count );
stimulus : process is
begin
for cycle_count in 1 to 5 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
reset <= '1' after 15 ns;
for cycle_count in 1 to 5 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
reset <= '0' after 15 ns;
for cycle_count in 1 to 30 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
wait;
end process stimulus;
end architecture test_counter_behavior;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY snake_lib;
USE snake_lib.snake_pack.all;
ENTITY demo_make_map IS
GENERIC (N : INTEGER := 10;
M : INTEGER := 10;
INITIAL_SIZE : INTEGER := 2);
PORT (clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
eaten : STD_LOGIC;
snake_size : IN INTEGER RANGE 0 TO N*M;
dir : IN STD_LOGIC_VECTOR(1 DOWNTO 0));
END demo_make_map;
ARCHITECTURE Behavior OF demo_make_map IS
SIGNAL snake_body : int_array;
BEGIN
make_map1: make_map PORT MAP (clock, reset, eaten, snake_size, dir, snake_body);
END Behavior;
|
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Quad 2-input OR gate
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_7432 is
generic (
latency : integer := 1
);
port (
emuclk : in std_logic;
p1 : in ttl_t;
p2 : in ttl_t;
p3 : out ttl_t;
p4 : in ttl_t;
p5 : in ttl_t;
p6 : out ttl_t;
p8 : out ttl_t;
p9 : in ttl_t;
p10 : in ttl_t;
p11 : out ttl_t;
p12 : in ttl_t;
p13 : in ttl_t
);
end entity;
architecture rtl of ttl_7432 is
signal p3_loc : ttl_t;
signal p6_loc : ttl_t;
signal p8_loc : ttl_t;
signal p11_loc : ttl_t;
begin
p3_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p3_loc, q => p3);
p6_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p6_loc, q => p6);
p8_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p8_loc, q => p8);
p11_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p11_loc, q => p11);
p3_loc <= p1 or p2;
p6_loc <= p4 or p5;
p8_loc <= p9 or p10;
p11_loc <= p12 or p13;
end architecture;
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_poly_17_9 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC;
RAND_OUT : OUT std_logic_vector(7 downto 0)
);
END pokey_poly_17_9;
ARCHITECTURE vhdl OF pokey_poly_17_9 IS
signal shift_reg: std_logic_vector(16 downto 0);
signal shift_next: std_logic_vector(16 downto 0);
signal feedback : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
shift_reg <= "01010101010101010";
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- next state (as pokey decap)
feedback <= shift_reg(13) xnor shift_reg(8);
process(enable,shift_reg,feedback,select_9_17,init)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next(15 downto 8) <= shift_reg(16 downto 9);
shift_next(7) <= feedback;
shift_next(6 downto 0) <= shift_reg(7 downto 1);
shift_next(16) <= ((feedback and select_9_17) or (shift_reg(0) and not(select_9_17))) and not(init);
end if;
end process;
-- output
bit_out <= shift_reg(9);
RAND_OUT(7 downto 0) <= not(shift_reg(15 downto 8));
END vhdl;
|
--
-- LoopCheck
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016-2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity LoopCheck is
generic (
DWIDTH : positive:=8 -- Data width
);
port (
-- TX side
tx_clk_i : in std_logic;
tx_rst_i : in std_logic;
tx_stb_i : in std_logic;
tx_data_i : in std_logic_vector(DWIDTH-1 downto 0);
tx_data_o : out std_logic_vector(DWIDTH-1 downto 0);
-- RX side
rx_clk_i : in std_logic;
rx_rst_i : in std_logic;
rx_stb_i : in std_logic;
rx_data_i : in std_logic_vector(DWIDTH-1 downto 0);
rx_errors_o : out std_logic_vector(4 downto 0)
);
end entity LoopCheck;
architecture RTL of LoopCheck is
constant NOT_RECEIVED : natural:=0;
constant VAL_MISSMATCH : natural:=1;
constant QTY_MISSMATCH : natural:=2;
constant QTY_LESS : natural:=3;
constant QTY_MORE : natural:=4;
signal tx_qty, rx_qty : unsigned(DWIDTH downto 0);
signal errors : std_logic_vector(4 downto 0);
begin
tx_side: process(tx_clk_i)
begin
if rising_edge(tx_clk_i) then
if tx_rst_i='1' then
tx_data_o <= tx_data_i;
tx_qty <= '0' & unsigned(tx_data_i);
elsif tx_stb_i='1' then
tx_data_o <= std_logic_vector(tx_qty(DWIDTH-1 downto 0) + 1);
tx_qty <= tx_qty + 1;
end if;
end if;
end process;
rx_side: process(rx_clk_i)
begin
if rising_edge(rx_clk_i) then
if rx_rst_i='1' then
rx_qty <= '0' & unsigned(tx_data_i);
errors <= "00001";
elsif rx_stb_i='1' then
errors(NOT_RECEIVED) <= '0';
if rx_data_i /= std_logic_vector(rx_qty(DWIDTH-1 downto 0)) then
errors(VAL_MISSMATCH) <= '1';
end if;
if tx_qty=rx_qty+1 then
errors(QTY_MISSMATCH) <= '0';
errors(QTY_LESS) <= '0';
errors(QTY_MORE) <= '0';
elsif tx_qty>rx_qty+1 then
errors(QTY_MISSMATCH) <= '1';
errors(QTY_LESS) <= '1';
errors(QTY_MORE) <= '0';
else -- tx_qty<rx_qty+1
errors(QTY_MISSMATCH) <= '1';
errors(QTY_LESS) <= '0';
errors(QTY_MORE) <= '1';
end if;
rx_qty <= rx_qty + 1;
end if;
end if;
end process;
rx_errors_o <= errors;
end architecture RTL;
|
-- file: clocking.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____48.000______0.000______50.0______273.634____296.868
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clocking is
port
(-- Clock in ports
CLK_100 : in std_logic;
-- Clock out ports
CLK_48 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end clocking;
architecture xilinx of clocking is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clocking,clk_wiz_v3_6,{component_name=clocking,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_100);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 5,
CLKFBOUT_MULT_F => 49.500,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 20.625,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_48,
I => clkout0);
end xilinx;
|
-- file: clocking.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____48.000______0.000______50.0______273.634____296.868
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clocking is
port
(-- Clock in ports
CLK_100 : in std_logic;
-- Clock out ports
CLK_48 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end clocking;
architecture xilinx of clocking is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clocking,clk_wiz_v3_6,{component_name=clocking,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_100);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 5,
CLKFBOUT_MULT_F => 49.500,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 20.625,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_48,
I => clkout0);
end xilinx;
|
-- file: clocking.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____48.000______0.000______50.0______273.634____296.868
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clocking is
port
(-- Clock in ports
CLK_100 : in std_logic;
-- Clock out ports
CLK_48 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end clocking;
architecture xilinx of clocking is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clocking,clk_wiz_v3_6,{component_name=clocking,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_100);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 5,
CLKFBOUT_MULT_F => 49.500,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 20.625,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_48,
I => clkout0);
end xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
package OV76X0Pack is
constant SccbAddrW : positive := 8;
constant SccbDataW : positive := 8;
constant SramDataW : positive := 16;
constant SramAddrW : positive := 18;
constant PixelResW : positive := 3;
constant NoPixels : positive := SramDataW / PixelResW;
constant NoPixelsW : positive := bits(NoPixels);
constant NoBuffers : positive := 2;
constant NoBuffersW : positive := bits(NoBuffers);
constant BufferAddrOffs : positive := 16#10000#;
constant FrameW : positive := 640;
constant FrameWW : positive := bits(FrameW);
constant FrameH : positive := 480;
constant FrameHW : positive := bits(FrameH);
constant FrameRes : positive := FrameW * FrameH;
constant MemWordsPerLine : positive := FrameW / NoPixels;
constant MemWordsPerLineW : positive := bits(MemWordsPerLine);
constant InstPtrW : positive := 4;
constant tClk : positive := 1;
constant tP : positive := 2 * tClk;
constant tLine : positive := tP * 784;
constant tVsyncPeriod : positive := tLine * 510;
constant tVsyncHigh : positive := 4;
constant tHrefPreamble : positive := tVsyncHigh + 11;
constant tHrefPostamble : positive := 15;
constant noHrefs : positive := 480;
constant tHrefHigh : positive := 640 * tP;
constant tHrefLow : positive := 144 * tP;
constant tHrefPeriod : positive := tHrefHigh + tHrefLow;
constant PixelW : positive := 8;
type PixVec is array (3-1 downto 0) of word(PixelW-1 downto 0);
type PixVec2D is array (natural range <>) of PixVec;
constant NONE_MODE : natural := 0;
constant DITHER_MODE : natural := 1;
constant SOBEL_MODE : natural := 2;
constant GAUSSIAN_MODE : natural := 3;
constant MODES : natural := GAUSSIAN_MODE + 1;
constant MODESW : natural := bits(MODES);
type Cord is
record
X : word(FrameWW-1 downto 0);
Y : word(FrameHW-1 downto 0);
end record;
constant Z_Cord : Cord :=
(X => (others => '0'),
Y => (others => '0'));
constant MiddleXOfScreen : natural := FrameW/2;
constant MiddleYOfScreen : natural := FrameH/2;
constant MiddleOfScreen : Cord :=
(X => conv_word(MiddleXOfScreen, FrameWW),
Y => conv_word(MiddleYOfScreen, FrameHW));
constant ServoResW : positive := 8;
constant ServoRes : positive := 2**ServoResW;
constant MiddleServoPos : positive := ServoRes / 2;
--
constant ServoPitchMin : natural := 20;
constant ServoPitchMax : positive := 120;
constant ServoPitchStart : positive := 80;
constant ServoPitchRange : positive := ServoPitchMax - ServoPitchMin;
--
-- constant ServoYawMin : natural := 30;
constant ServoYawMin : natural := 40;
constant ServoYawMax : positive := 80;
-- constant ServoYawMax : positive := 120;
constant ServoYawStart : positive := 50;
constant ServoYawRange : positive := ServoYawMax - ServoYawMin;
--
constant TileXRes : positive := FrameW / ServoYawRange;
constant TileXResW : positive := bits(TileXRes);
constant TileYRes : positive := FrameH / ServoPitchRange;
constant TileYResW : positive := bits(TileYRes);
end package;
package body OV76X0Pack is
end package body;
|
-- Configurable FIR operating on 4 round robin multiplexed channels.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
entity quadfir is
generic(acc_width : integer;
out_width : integer;
differentiate : boolean;
index_sample_strobe : integer;
index_out_strobe : integer;
index_pc_reset : integer;
index_read_reset : integer;
index_mac_accum : integer;
program_size : integer;
program : program_t);
port(d : in signed18;
d_last : in std_logic;
q : out signed(out_width - 1 downto 0);
q_strobe : out std_logic; -- Asserted on the first cycle with new data.
q_last : out std_logic; -- Asserted when output is last channel (3).
clk : in std_logic);
end quadfir;
architecture behavioural of quadfir is
-- Layout of the command word:
-- 18 bits multiplier.
-- 1 bit in sample strobe.
-- 1 bit out strobe.
-- 1 bit pc reset.
-- 1 bit read reset.
-- 1 bit mac accumulate/reset control.
subtype program_counter_t is integer range 0 to program_size - 1;
signal command : command_t := (others => '0');
--type buff_t is array(0 to 1023) of signed18;
type buff_t is array(0 to 2047) of signed18;
signal buff : buff_t := (others => "00" & x"0000");
signal pc : program_counter_t;
constant pointer_size : integer := 11;
subtype pointer_t is unsigned(pointer_size-1 downto 0);
signal write_pointer : pointer_t := (others => '0');
signal read_pointer : pointer_t := (others=> '0');
-- Unpacked command.
signal coef_1 : signed18;
signal sample_strobe : std_logic;
signal out_strobe : std_logic;
signal pc_reset : std_logic := '0';
signal read_reset : std_logic;
signal mac_accum : std_logic;
signal mac_accum_1 : std_logic;
signal mac_accum_2 : std_logic;
signal accumulator : signed(acc_width-1 downto 0);
signal data_1 : signed18;
signal data_2 : signed18;
signal data_3 : signed18;
signal coef_2 : signed18;
signal diff : signed18;
signal product : signed36;
begin
process
variable acc_addend : signed(acc_width - 1 downto 0);
variable rp_addend : pointer_t;
variable rp_increment : integer;
variable write_pointer_corrected : pointer_t;
variable diff_out : signed18;
begin
wait until rising_edge(clk);
command <= program(pc);
if pc_reset = '1' then
pc <= 0;
else
pc <= pc + 1;
end if;
-- Unpack the command.
coef_1 <= signed(command(17 downto 0));
sample_strobe <= command(index_sample_strobe);
out_strobe <= command(index_out_strobe);
pc_reset <= command(index_pc_reset);
read_reset <= command(index_read_reset);
mac_accum <= command(index_mac_accum);
-- Input processing...
if sample_strobe = '1' then
buff(to_integer(write_pointer)) <= d;
write_pointer_corrected := write_pointer;
if d_last = '1' then
write_pointer_corrected(1 downto 0) := "11";
end if;
write_pointer <= write_pointer_corrected + 1;
end if;
-- DSP input buffering.
data_1 <= buff(to_integer(read_pointer));
data_2 <= data_1;
data_3 <= data_2;
coef_2 <= coef_1;
mac_accum_1 <= mac_accum;
if differentiate then
diff <= data_2 - data_3;
diff_out := diff;
else
diff_out := data_2;
end if;
-- dsp
product <= diff_out * coef_2;
if mac_accum_1 = '0' then
acc_addend := (others => '0');
else
acc_addend := accumulator;
end if;
accumulator <= acc_addend + product;
if out_strobe = '1' then
q <= accumulator(acc_width - 1 downto acc_width - out_width);
-- Channel will have already advanced on output.
q_last <= b2s(read_pointer(1 downto 0) = "00");
end if;
q_strobe <= out_strobe;
-- buff pointer update.
if read_reset = '1' then
rp_addend := write_pointer(pointer_size-1 downto 2) &
(read_pointer(1 downto 0) + 1);
rp_increment := 64;
else
rp_addend := read_pointer;
rp_increment := 4;
end if;
read_pointer <= rp_addend + rp_increment;
end process;
end behavioural;
|
--!
--! Copyright 2020 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! See "Wasserfall" implementation with the real L2-cache
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
library commonlib;
use commonlib.types_common.all;
library ambalib;
use ambalib.types_amba4.all;
library riverlib;
use riverlib.river_cfg.all;
use riverlib.types_river.all;
entity RiverL2Dummy is
generic (
async_reset : boolean := false
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
-- CPUs Workgroup
i_l1o : in axi4_l1_out_vector;
o_l1i : out axi4_l1_in_vector;
-- System bus
i_l2i : in axi4_l2_in_type;
o_l2o : out axi4_l2_out_type;
i_flush_valid : std_logic
);
end;
architecture arch_RiverL2Dummy of RiverL2Dummy is
type state_type is (
Idle,
state_ar,
state_r,
l1_r_resp,
state_aw,
state_w,
state_b,
l1_w_resp
);
type registers_type is record
state : state_type;
srcid : integer range 0 to CFG_SLOT_L1_TOTAL-1;
req_addr : std_logic_vector(CFG_SYSBUS_ADDR_BITS-1 downto 0);
req_size : std_logic_vector(2 downto 0);
req_prot : std_logic_vector(2 downto 0);
req_lock : std_logic;
req_id : std_logic_vector(CFG_CPU_ID_BITS-1 downto 0);
req_user : std_logic_vector(CFG_CPU_USER_BITS-1 downto 0);
req_wdata : std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
req_wstrb : std_logic_vector(L1CACHE_BYTES_PER_LINE-1 downto 0);
rdata : std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
resp : std_logic_vector(1 downto 0);
end record;
constant R_RESET : registers_type := (
Idle,
0,
(others => '0'), -- req_addr
"000", -- req_size
"000", -- req_prot
'0', -- req_lock
(others => '0'), -- req_id
(others => '0'), -- req_user
(others => '0'), -- req_wdata
(others => '0'), -- req_wstrb
(others => '0'), -- req_rdata
AXI_RESP_OKAY -- resp
);
signal rin, r : registers_type;
begin
comb : process(i_nrst, i_l1o, i_l2i, i_flush_valid, r)
variable v : registers_type;
variable vlxi : axi4_l1_in_vector;
variable vl2o : axi4_l2_out_type;
variable vb_src_aw : std_logic_vector(CFG_SLOT_L1_TOTAL-1 downto 0);
variable vb_src_ar : std_logic_vector(CFG_SLOT_L1_TOTAL-1 downto 0);
variable srcid : integer range 0 to CFG_SLOT_L1_TOTAL-1;
variable selected : std_logic;
begin
v := r;
for i in 0 to CFG_SLOT_L1_TOTAL-1 loop
vlxi(i) := axi4_l1_in_none;
vb_src_aw(i) := i_l1o(i).aw_valid;
vb_src_ar(i) := i_l1o(i).ar_valid;
end loop;
vl2o := axi4_l2_out_none;
-- select source (aw has higher priority):
srcid := 0;
selected := '0';
if or_reduce(vb_src_aw) = '0' then
for i in 0 to CFG_SLOT_L1_TOTAL-1 loop
if (selected = '0') and (vb_src_ar(i) = '1') then
srcid := i;
selected := '1';
end if;
end loop;
else
for i in 0 to CFG_SLOT_L1_TOTAL-1 loop
if (selected = '0') and (vb_src_aw(i) = '1') then
srcid := i;
selected := '1';
end if;
end loop;
end if;
case (r.state) is
when Idle =>
if or_reduce(vb_src_aw) = '1' then
v.state := state_aw;
vlxi(srcid).aw_ready := '1';
vlxi(srcid).w_ready := '1'; -- AXI-Lite-interface
v.srcid := srcid;
v.req_addr := i_l1o(srcid).aw_bits.addr;
v.req_size := i_l1o(srcid).aw_bits.size;
v.req_lock := i_l1o(srcid).aw_bits.lock;
v.req_prot := i_l1o(srcid).aw_bits.prot;
v.req_id := i_l1o(srcid).aw_id;
v.req_user := i_l1o(srcid).aw_user;
-- AXI-Lite-interface
v.req_wdata := i_l1o(srcid).w_data;
v.req_wstrb := i_l1o(srcid).w_strb;
elsif or_reduce(vb_src_ar) = '1' then
v.state := state_ar;
vlxi(srcid).ar_ready := '1';
v.srcid := srcid;
v.req_addr := i_l1o(srcid).ar_bits.addr;
v.req_size := i_l1o(srcid).ar_bits.size;
v.req_lock := i_l1o(srcid).ar_bits.lock;
v.req_prot := i_l1o(srcid).ar_bits.prot;
v.req_id := i_l1o(srcid).ar_id;
v.req_user := i_l1o(srcid).ar_user;
end if;
when state_ar =>
vl2o.ar_valid := '1';
vl2o.ar_bits.addr := r.req_addr;
vl2o.ar_bits.size := r.req_size;
vl2o.ar_bits.lock := r.req_lock;
vl2o.ar_bits.prot := r.req_prot;
vl2o.ar_id := r.req_id;
vl2o.ar_user := r.req_user;
if i_l2i.ar_ready = '1' then
v.state := state_r;
end if;
when state_r =>
vl2o.r_ready := '1';
if i_l2i.r_valid = '1' then
v.rdata := i_l2i.r_data;
v.resp := i_l2i.r_resp;
v.state := l1_r_resp;
end if;
when l1_r_resp =>
vlxi(r.srcid).r_valid := '1';
vlxi(r.srcid).r_last := '1';
vlxi(r.srcid).r_data := r.rdata;
vlxi(r.srcid).r_resp := "00" & r.resp;
vlxi(r.srcid).r_id := r.req_id;
vlxi(r.srcid).r_user := r.req_user;
if i_l1o(r.srcid).r_ready = '1' then
v.state := Idle;
end if;
when state_aw =>
vl2o.aw_valid := '1';
vl2o.aw_bits.addr := r.req_addr;
vl2o.aw_bits.size := r.req_size;
vl2o.aw_bits.lock := r.req_lock;
vl2o.aw_bits.prot := r.req_prot;
vl2o.aw_id := r.req_id;
vl2o.aw_user := r.req_user;
vl2o.w_valid := '1'; -- AXI-Lite request
vl2o.w_last := '1';
vl2o.w_data := r.req_wdata;
vl2o.w_strb := r.req_wstrb;
vl2o.w_user := r.req_user;
if i_l2i.aw_ready = '1' then
if i_l2i.w_ready = '1' then
v.state := state_b;
else
v.state := state_w;
end if;
end if;
when state_w =>
vl2o.w_valid := '1';
vl2o.w_last := '1';
vl2o.w_data := r.req_wdata;
vl2o.w_strb := r.req_wstrb;
vl2o.w_user := r.req_user;
if i_l2i.w_ready = '1' then
v.state := state_b;
end if;
when state_b =>
vl2o.b_ready := '1';
if i_l2i.b_valid = '1' then
v.resp := i_l2i.b_resp;
v.state := l1_w_resp;
end if;
when l1_w_resp =>
vlxi(r.srcid).b_valid := '1';
vlxi(r.srcid).b_resp := r.resp;
vlxi(r.srcid).b_id := r.req_id;
vlxi(r.srcid).b_user := r.req_user;
if i_l1o(r.srcid).b_ready = '1' then
v.state := Idle;
end if;
when others =>
end case;
rin <= v;
o_l1i <= vlxi;
o_l2o <= vl2o;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16560)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztlHgsA7XTu3se9+qgRV127brGn1J+SpZIMueDb+AV872JX
nOXB120GyVLNbjkhWTWXGQdsLOXfaXs2I36xZVRiwzpAgBzfQJrI9hG2kq7bh9WznJ3xEF5DLexY
Cq15Vdb5gm0qDaFFZVGzlV0qAsnNmU5TwLZdRsYlrsSd1i9jUQlzfmNsUENvXGN3CDlY8CFK3jai
INNNriIElfSpAetTkn9VmfppFFOF7wWkbrMeWuJ7l/thC50PzIkDIzK4x9CtfhJd3F2cp+VAeBKF
LrxUYaG5u5XXGRyoHikRUGoKOXXmqvmZIKvGnqo9OmemjsqjILGrPxP+3Dy+cG+LmqgRYTxy9X3z
oMfdSSQ6KvJIZvqKnopohLc6y0/oMFyP21GDeRYafr53M5KZ/f/dLwptOby/mIDvt7SkwnKGfvFl
EpHTWq8Qukwr6iDxqQsNxGo493Q+4LG/yKuSE0SND6bwyarofUfxPeW4laRQMKn7H0Tq/eaUvdP7
vXl1nkBrtRL2reVVADRjcpDm+3z/jYigRFz9ttrA1C+77PRjiowP1YG1fdzffqSmOJ2j2mFWYikv
ToyM9T8m18egCp2ghJoN4eI/VKWlDfluDP8ZTsWcngrJsn3e/GAOL8PDe92FDeVUKpkl+gr4V7Rp
2aPnAyyzEcBeVlaEkmCZITU7qdXWBM5BIqVU+5e2tVie09XfrzH5MIHwUfVaSuy2u55zP0BOF7Gu
CUEPlLKnR9X1WrHVcPnd6fkPfFulzaTs2HuDJi/KrTvbj7wCFie6P4/WolNX6kPWjcz9aQ+wnwhS
Cl7c1ftfyzJMNbweg5RPfaq3a88McLpzC6etEqO31+rgbz/dfhINoJkCiNixX7xIp4n8lci7GXoM
doKmP5XLBXmP/Ef1HlFhsKHBbwP+AsT/HJKsRbeMXUWPRtcZnkpB4dP4RxWecqcBPC+ggs2Wg9XD
flCvKjr6I9RAgAyAJYDKpapS2KNmOBVR6fSfSEbVOTjDKBU6mPvbIW0B1GrxujCVwXhYhzfa2n7s
pSvvjqm7xICaDI8wL4+o4znzeARXPT/oyN++/EZb2EHhIwgPpY5/j+VTdImaOHA9M1rXQQLS5YiQ
d8fE3ICl0Dc9YPx7Gi23TU1UqiV1wx1HdnYhTuzoxdEq6NpLA258Wh+rwSu8vP7hWDb4IQs7YCmU
6c1ehdkx/jvYYfcnI/kqhIpv07AlgCablcW/IVHSudlBYFvHKGNJQlgPw9VF3ckGkh8Nga9O9I9d
WGpkXkOB7qPMCwxtST5z9waEGTMzhngUhfVQG3HBNTQ2/Wat/S/5ryngqBFCJaIgUfrzw8VYPRpx
Ma8yghJP9QRD0sXR0VB21eJw+4iLEg1o1b5xf9NUkYGOZOEZKU4Stu4K+cfuS7iTeocaFB1jsdNn
ntMoV0FAqRuj1lOxDG+YJLiVc5qi1sBf6RQL2iPcSOOeEQ+PD/uFwCj6180hC84peYYWAyHN1Frg
05/zwXh2E591TYe4C0h0dT+Aos4yWciHzN20jWOxXMzIS3G1qwF0EGqAijrnXGLcGocwxkZPDg7O
+ZIkcpsjjhwsvUCRAmpdYb12MfN1aomq3wUg8VUEjLXBfDpGSJm6LmRFOyE95KmkhVn9RTJI7dRC
jwjcf+RbuNT2kw6BbtbyviR0PCqcqqTHTP/U7tvsE06ymyUlA0+8IJ3mEXtUVLHrlnKrg8hrwXl2
4THwUppB9JDYFgpLPAXCkF4P+9MlHt8xmiKzjjY/jg4X5Mak8s5L1GLzrK731k64QPGLnV7Y58fc
JJVHuV7cVknlClqd9DJbTGS2lpfnm3E5Xx2a9tbuW2oKicS7VLIMnVFCOqwczmsysYtdtNgGlee5
1fK25W2QAG1uuOeASXuQ2ZNt0bEInni+G7PBrvOi/pIjashgqTgNL3SHHmA/XFMZnHX6netOZm3e
BlfRhSx0HBjP/WZtK5NmOcyW9rMppg466DDbqoPfn9ht2ThmNdE55qlP9RBkGuq3LmORr9QPoP2r
Kez2IK03BRuNytY9tB9JWMXjpeNTFfev40Y2apCXKqghOHbvLqicXRe2RpvdFsDdFcAH3Zd2cOx1
is5sPhAMvaqwmdbkvhYB2IccISAzJCjDSLxf9u2Ohfbk1LkOVNmX/lsYcr4M5bchScDMMvbxps9A
/nKuGAdf59tzE0AtDeG/JB6q9/Xatq9vDckMhMnW79Nj2YM+eA4nboeZi2q2usxzOCsHZCPMfnmQ
JdiYT4tcLjLpV/MAsswTqI2YwYG7Wsr4TfTd62xl1K6gTKPFxD0Bxeh/7gMUL+s04w2ABMxYeOUS
soGkfyrtq/fWWpQisTLRSPV3UDe0a8xM5OL7koiF4kZg6J6vU2gRPDL6/9fq88Oi9w56f6BRRcy5
zn1CYRLMCbCuNo0bQ1ikRl2fwa6WE8OA23UlxdNZk2+rphNHNk/UloVCB5ZXiKdP89w0J0JyVcme
Cc0Eo26iADVldbzlUVXNikp8CU4tzrmC9jSh4NIpBU6d0qi+G69Y6KulyUxpENfSof5PXnrXrb0Q
89dsh1dr1Thsq5QZcNvSCknVagRzD5eUWy/u9tPEyziJvWGUJQOb/YSxz+I915Wlw3Gxem7EPsck
e1PONwATUS1zh0sOiUIChUN2ZysliabYb/tSsNGvzBtEp+DbZPlcoyqbJHSoP1TjXAnB/TDMobpY
yugtm5DdXSlGUrsKwBiBRcewN/Y7XznivnNsc3JPTo1vYK5Mc4DCRgFEZfIqde02lPpl2OUw54bh
699OiZk8Z8JHlBC/A3sqOSelp2MNG5GW1MrCAdQjpmlf7u1evUvOQyjx5tM4G0aaGiNS35xwXmvy
Z3hId27r4DbvS3CI56QsLSh4NsdzjHoirwkfFFUQco4kP6r6bBSb+qSdg5mYwvieiEwLTDYXGdFR
9H1KBQGXkHjNWieL8VYuheOudvT56+fW+kiYu45hauh62DQdKGeGikrGmLr6O7Cs5+vYXEzV1A+o
rsbHB+3w/DVKGDe6r51wO+1rKxqQ0Ly+zSKNFfswqm4qVO9OSIjiL8P+9WdX2WRpsnvOWOa9LUFo
NQi1p429r6FXqSXAxtJFZAgtNmAhrqBd28LyAHLvJsKdymxhpLsNGZqUP9VODIMT/jg9FeKzeDhN
K+mriXZRagg47TCbQ2xZG4/ay2CZfZ2sKH10qBP+sssi7JR0Ir2VywA0EPn9PnMhtTgQtvqypQKp
tC3vUX8ahzFNh3Rwo1+nu3wdy26gqFRexgdN/bJkXd15oB982kk1dlJgX/DPRLOnOtTMfIjnqRu7
2BJeaOK1r1bEPNmwXEsaqVzTfE4vFlLEBmqnmT4YWmW6Nicd9qmfnMC629+UyKOGD1E8xJcFqsai
KGe5AvZuNbA6toK3QaB3p/GBfA9yvQgi/U5HY2xKehgk1556cTgixJxIZpNI2uwglCpYejZIoyYw
6MJnv9EPF/8HnKQCdAU6BeocT+XCeiSTlDDbaeGtC2h/HJjGXOM6hrc7vAC/zpwnoyF7BrVFoaFr
gUbOuzQlFA7zzL7gukUB5wlipL4en88vw4fNqQVoEsXtOJt7+OwYxZGX2DVrbzXE/u+6qgVZrJE4
GQ7b/tFeHjN2MmA31MwbHpN90Bx3MkW/t/UnXttPwJLkHGqRWBEg+6k5qScLFuJU9yfxFL6Gl1Ts
wIRCystlJ0QiGF51P+e4bdezj3lGSLIsINtYaa972U88lqm3si79cpBX3PmtfG0LWfmvcwEQ5C3S
O8DvsGbXqhKhQI0hcp/q1GLivekWYvv0DUYQwl1D0pqHEU6HhXAmtkavBRzh+bBdmM4eq00j9/ey
KMDXJ/KGd1UHloG2GevD15YewMLbBrBiBbGCrKoG2MlVx4pS2l8Ed6uFi8sr8JvMm5BfOB4qMX3k
eLhMva3T55O4F6d1xJKytcNUWG3o/ioUCGqLOQbz5VEFJuO0yJNibwfl0L6Zq8nGoa1d7tAFKrf8
di+++XVql/0QR3Objt3pn44+I4/xFX0Fo/WAA4Gjx2qN2v+gBwp4PmFB8RFtRHZzYeho2dUEaoRS
iMRoCzeoLMqR3IpyV+4Ke+/YXueoKclTjREVWIZx+xOC2/8Mkzsn5exuL8xBytvXlZOlNThg1q/s
l+UTvKbilMmlpnfJWVQmVvY1ANEms1T7Fmi/iRqLt81K2quZBkn1yotrpJQoXWim5/1Xx+FbJtpc
Z5W0Lei80zbfWjkV6fJJh97rvbydPikIQMr9ggiVBXziaHiyz5znMYChR+noERf30uWQc3r6i969
l2DppBpsIOzfpUufIvlfQdviduKBkfPmBu7cwp8Z35r4PCO8d6/PVWhVy/1LrRH8cKz7XPVpdgs+
Po/s1l+Qq6117HHXkaG3erTJFyrL/cjeunpIxssncNIfUTlC0ZhoLm/orQiCQ1AUBv/z5KFlTyAo
VSYL6gRlt2mxsIMjxj76F72fc+8DYK+rp6lD4fpUG5VCVquHWtym4EXwat4n6LS25KP0AI3Pz6IV
tdpsgjz5Il7fHQ5P3NG3r4ovkDcCTh4LSwibzVal6hT0QgjhsTRTwtSyjwURaXESfpoyqtm08gS/
kHuni1hz1GYk9h00Z656w/xYEMFTzzA/nP4mvA8eqwo4IxrSOxhBURV5iLrnl7W5+6u/XyeGswma
UVjZu2CdWHnHs2DTL6MZA1dw8CcQJnRxDi0iJDV3Yw5QhBR3B6l+6opFKyHYGPchwT9kYF9WOnq+
sX6DCc7wxGppgxXmZQdKcHGDG99/GEBN3JzB1wVu9AE0+x2KFcTOKruRuetEFiZRugsWJk9CSMd/
Pqqy/1ZYooTmoIpm9FYrtCFnT9cZPY74f61YlKZkI7Exq+2450huOnNcq0DND0THHUpPYSkZ1Cqf
+l2kGlL1EFHj8yRGpSFjkx7gDHvCk1wtgb1ANbEPaBAOQZZx8hZGFPitdaELgSXqAwDmmmB04p0P
hCqQBvO7/RrfEphYFnJ+mjkm4HdtKH7uRiYv+QKjpCSofNUUiVufrzljkzStj8YWPOZx7uYZ3Pt9
6zoVxfaT0QlvhZBypPXB9AvcprFuQVdI0CbPafTMDyScVAKXK3gp/N2kou0/LjK1xxKRyNpMI5/J
s8ZUxEh3N6SaPUTMBtlbFt62nnGUR8BSPx6xNpjHft65N3D8MnyNwUoaxiF5jyZmli3Ye9euPJpk
tpr8tzkhm+mqOfWrnh6YC6wOo36VeNLL29tZhHPG+XzhbVqj1t1o6Lflpaef8P8e1nfLueBAXAos
hvJ+1/D8hFZis7N+I9kOsK/ts4QlDxXnwXUACHo6nS6+ediDinAvxlSRJVkBDnh9x2UupT/wmWpV
LOvKTfv4/9ccTpiF/6+Z4K7s16m58iG1nr5tayTHj9eq+xtq/XVgokWOI/AvlPHYa1M+GGLEPO4h
y0Ld4Ypo9LmENFgAY7KRnFxujX+grSfz+tJiiULvhK5xcL+H+pukbgvy7hF7sUZzC4mKlaaJgcja
dZXxPUVudBbevACchjTnaH838vqO7f6vn9N2WDAMjViYQcb2OjteHH0io1avNJO6LN0u5Z/BxGiJ
L6PDB3PPEi8+iFiIF6zYSU1kD1C6XQBPlzym0BztEtUx1Hvopmgz7F9Sg7qqTHkITBUH4aaMsXpR
qyrpvoTQYUKbQCZfpzL8DkJrw77hFAFw+Fa3ZCQ7PT2FWAkUzezubjPh40kzSjaKAFfkZbN2qm0U
Gr8IXg1PHQdLcesTh3D0uJbsj1GGdYHMlV6KNx+rNn5LpBafB4oB+0weRGlJwsm/lQmAiIK3GxBS
XR7FMD7djS36sPeCSDUIZAmb26Afq97fmRdVbftrJOiSwPiHkKp2jTS8cZK3LLO2Vuwx3RS6WJ0R
JsvHNqt1lkDqJdrFsDHWZHN3UH/jQJgkhCjAgvo/4bP1fgs3e+8Vww806JoJhsfT/89GDrydvY8A
fj2iFIprpUv1NoMDolCWe7AHLlaRFGsf5COLhW3qKDrSl5iAlYiUVbEYCERth1B68+Xx9aULxMe8
4GV8KTUJvI4s/mlTXrhrbkA8cQpPpg4ZHxIY1xrc47rdyP19k3MGsLLpSVxFY3i3J8Moq51yq1VG
IGp3+5ELe+7e3VWSgTu9ws1bLvjDItgxgbNEFG+yiv7cykZXb/3gSTi2bZOS8ywKS9qjwA8BHyHj
G0DULxEBtFuYIHFIh5Xk0jPSn9lbO7Xur07oGHzwXeBE9MoGBhnxN7Zhn+976V7BPpWuuSh8cfFE
Yr6DmL0pCduDPGNbDXTER1+leirJP9ZJp9j9DGkmcgI+NWueCs/cGj1Js2nt62xOyJEnGNmuKien
FojwXD4CFBPPrIozMwEFwv0eUV/lsvjQB8VrYEXwZVkHOLYGKyNntf+2mYgGPCIgliMaokIz7ELC
Kbh7Cu6yvOiPyh85SBt7XFf5IFzKkVRbFGayIF4BLb0hnIfZYXHfOU1RqGguCNRvXzDqmp3a3Yn3
2IN6Q3PgLKG7B/UBs6kVhIZJkNA1JeoiUCO/w3uKdR6tB3LDMP2aU1Pl4F8fGLovULMF2Qq3gG6o
tPQbnC9DMTc+fQDwWACPQoQwTXLAZzGcAvGtDgBNYQvCcnx0QIChoTDWszGFWZ2cQzXJvG/gw6wz
g8zGiEeDOrSGHNoitYW+k1lx7FrW8yRPfPdpz2vdKD6T9da0d3Gfy40tWeV3ZllxKAMEAhbJl1Y2
1vYJmWWU/nFz6JSA7Fq/IRYHe/9ANTyTOrAENui5qESRYZ1YYxOY7v1GH8c3kFqb1cflDhFdehHa
SPxCWJLMEmtoNRbICkuqMyYeXf6fE4oRp2GVvgJcXVyfbJvpcPLdJzNOWFxv4Ku5UhsELGBiTviq
OlPzz39UDDndJeyQdx2tSgkrVQ8cNV7iN2Zvvr8239TxwVEr1QCj+BwQ1l0HB4VCFyY1125db7s8
gc8lLMekkOpse62RVtMVHoaRcySsYqcb6FqPFxOPkkouDbgKnq2sK1neOh9LD+6LQ5r23ji/qyvW
HoiyQCwIr+8RfRRBu6dYdh3khE/ePDS2UnL+Xr9/zUMW/+QF/bs/saVJNs/Vj6oJxUlM/X/sbD8W
3GL/dQM/VahC/GkUbb2R47Bnq+8PdReb7cRecV3fE+ijFAKwt8ZWswVRSHbPSsdbwoCX7QWMSJCI
2dWJCTUtjAebp2jWLP3ZU9ZRkjpDemB51DOaVGz6NpjsBE+NQrxMQP0HZirpBKny3egZau/rijG3
rEVHGnb9FO7TIqMv81FsBJ+YW660fzOhVFBwT1emw0wNsDkFlBr52iNhovsUm3YNqGcrqjxB3S1Y
1g16hsPoEeOqAMzANwkTCT0/Xo8L852PVF4J99c9LQCSxqMLdndR7GcMMGFqCw/cgf8hgHZ4fC3F
8WmNzcdYZfuRJy0DXbQVHA1HJ/X9ejBmI95DeGlQqJcLKUYI1YL2H3wcey1XzY9uQgR+q1TVbI59
uyvUIcu+MHcqo9ejJRNuL/WnWv0bZ9ktwIQesdJTYX/KxkrzNZJRXp+x0A08D94pbcESeuoVbu7z
sm470JmLNx5n0IxyD5yfYQrGBA3ImSg29PMd7ghRArbCyHRupup8NqWHxvODbHby8dSpI1vT5JP6
AxGE/4qPMCSJtwaoVoJEmNXMN202RibkW6HJ88GFD0L0Saf4Il94KSAtPB8aU1RTZP3QJXQ1d6Dz
/fzYS12HtxvBjYcyclkndBWYaM2ZOxahUJe3uTG3DTKirg6QrQfY3NYFvXUrBV+4YHo1BF2/Q9oz
0z5wQe0Ad5Kc+s+mMResyrEV6GuYw0uDc1rUsTlx+0XpV4KL38sw9GPRQf4C8EWUmh2/tid5o31d
aSlkIL8hmDRqrI04xrF8yGkciS9NK8FlJYg+819vIchRu0ZxS0Xj1BY7SZG4swBUybfXh7HXOJLD
iT+IlvDn9GYGe8OooBBQZeb7p14Xlwyef70eJJBOnujKD9yRwbhUvaYM4EabGGQvr+qvOgBp0Zk8
SgxVfgK8tUKEBwE5di4+qLWEkFo7sazend8QDuUUOzGEovV3PRyPTPPdIQbtcNy92pb+2qlwWQH5
cOMo7jeJU3DdA9D7KYpT/F/lrXmJB0RWRUaFrTwKxoE35h8wcLcNQyawZjW6l6TUuDxHdhkGB/Fv
2aeaArVRU60iWJgFfVDlIZfrbxVIALYUTxBOBJOqCZEdPIA8Zq9lLx2ohLmGFkjLcriXnR1Dir4G
cTJXrAdhCAeqMhGDWJnOEZWoVMROcnkly4Kb2e0uJzFsf4egGRguI+vk11nXlVdR6ZlL0RxRER37
6j9TrMw12HYXNvHZ70qW+Vle6NKf+oBrY5Spz3lMw62kOfc+kfdjoPPMGDD9OLGGbC7nDEal8mzv
NJBrW8e5kqXJtv0RlH7j0l5MdcYQ6UVh+b6/z47d1pccps1RF0isRGpy8emcMp3eU0SwPISTO5Nj
Yy0IuMxqGsY/bsLN9sn63G3nSkjf1gmc/8rKucrxa/gJNCgSnluKD+EFGZOWFBeYVDbcrex8kn14
UHh0HjadbYJTf7JfQgqKAflO8YuNu2qW3R904gOd9FsbcHZsQA+RlJmTbBkrwjjAmwrHnTOpzp3M
5JIP87bN+qBJM51S4Kac0PoHJdnpnAL1xyMF/g15+0tG7CilYL7jQR664Hl4OYcBMtUc0EBbxK84
LTjy68XCy0HrfOPRTqb8+IjVMfo46X1babr6vNVRgxgfoD8oI+22NKABZdGxKYCDBe1emwMZgLwD
dGDARzEpWjsnn/RNc7bAQwts4E0t1MihNDxwP5Khs8APL+juIYTWrvPTQYMV9R/itb5IsZvxxWCv
/WbryWhvOG7FOn0EYnilTlQMFLy1QhWtI+5rmntR9LZUOlDBP+FhFeMOgICUP9t/Yt6vK6v/gp9n
yWmlqRYYr3g1OEDp1DwCTyzRmSALNHseyMkAcHu5hH5cqhiCVR2WKYBIKyWjjo9uvjIVR8oUHFMg
eUuy2hcWQe/+/GRBg0U15wB3rZggVEWkdZbo98NEUaCqQldFx3oHR6JnPDMXSM+ldYjtQesUOU7i
JMIPJkZNb6rdQG4ypJw9PLIL0XiRFL3UyuDkRg738Fcj8oq6YinWpaZFBvjSUloDY1P7FYXo3ds8
cYwipMu1aoDF3QY7I/FLJgHNhlnnLmRiZZs0yU26ikTTY638ZotZcl/yqjLDo71aCAUA8n7xPTGz
DilNhNALFTWNXmeE/FCHYktHn4mop3NrYe1nz1qUJAJpo8f4hCeKj+qB29OG0IroNtQMBirJpBcy
J/qDSiQ7gRTJXiZ8SkfaPSRVjxcMD9zf1ogPd3h4A5lyGK3UT3k63JISxwE+ivMvZLJ7h7ZbQtcE
UATW6roDXbBUbMYhJXZ5RGXhjIlVTHMQVufliMlvG1Lw2Rpi8ZUBoFvCywoHPljLHj86HFtNB5xg
c/Z/mQ8SXN3muIg63nkqkruWTgWMKqpvvnQcRwuXtpjKEAjYG7as/4KFFkrMR0iP8fqXWarAZLQ+
3QVcpooqFatuvDm5oFLGOtAqYjobHjd91KejD6jg8T+W1oTkNmAtPzwm/CgKaDMv1JIEz1LTzBhU
ELCM7YeiaxkCzVQ1QnZbPbbJ16zOh/c5G+HWa0Cg8ncWnxi/zMs9VXjMTsZga5+y4HeQSXd3jwyd
SqBqKpHkyIfavnx370xCiRq+Zszvod6wkPc2typPUWU2kxVjCYARqzB80Gi2QfDVa64BseI1U2tY
9gxXT2w3m4R83KCuxisQa7IwzODVEIEvAZEBjVGXDP7mqwDPoWuZkzb9WDTSUMkeGrPjW6eIJe+G
DhG97+JFtS9sNZ0HtKtEeIr4zPHOtlIwwohzOKeqUCS8YACWptfGXbWgy3joE+OyqH5kbrxkjfuI
ejN+pPSI1h4/zHayB+8tY0YII3t2F1Bn7pMirEONBAubL8hBGIG6HvKd8dBJqLiq1FmuEXhP7wjs
ShbKaCORmJ5n2RQOUvsPEuqQRHWdWLw1G5B1n3i8w1MowkHNQnebiEYhdFySYbzUU2a0BMTEZjjU
9GYieB8cX9Ki6dfvwnwwc14+PlY2kvzy3YorG9ArCxffSU8DwxPeE3PzpGd/ZjFtQIxB+BXcp9uu
HH6lH6cv2Wj2SbRsmkvUXDGDJ9qMk2Ad8whAXioG2D7UMYVmARmadBw673H/wV0UAMZd4n5Aqtsd
LVP2PjzLt+1uGCZm/A04JBBF1VSYCOWXXlYtq2qkwCP7GHF+nW4r8Gm6WqcMpd5ZS8oGtiY/xiD3
BVlDC/XGPmcrdhPz3AOo0PO5IgwoSWh0btpz6nJkyv9SEH/Ofr8g8Wxhs1y4O4IWmrNCmNOQ5WOT
NZecZGaZKfVz38JopmfRQEMAGCTy5OArPyE1JceLg80iEtbf5N6MkjeArw2E1ZTDOOV447Ar8zvE
nP6mXwVAZRVLorOAiX95z8OWMmmxI/3Yicub3N3Dwd6uXqpyoZX4HxHOGO5wpuBWiKVQYmEJZbKe
iR/UOU1AszGjLprttMdu7G7PZm2cQpkdXZ6SfJKyuk6fGtfBVfdK/72yzg9iKEpkRQq/NoAlMgHh
kT35LeZ4pPC8ak5g6rcLQK4bNXIDj/ApKqIqwqSjvtn/7p8ygDp12NbdZRuURvIG+IjG1ln/tP8L
WKmpydb1c7lxeAUEMGzIj1Npl3pGr1Wt8BOkxhm4hn7NKcBsVyO8amFo+qDreJ4Xgr/WyIlzelRr
Yjz11bHtyN3tABq4tk2gBcVwZjWKUMqg+Lnm+b/SGUTrUna4sMODP9lM1At3gp32IB5yUPfFZCHf
pXCoOgeWigFFp71feGukIWryAmSF3hl/JpFuWF3SB+AKERYitC8GzatRTXa1ac/qfG73W29O3KpD
FJ/pixQ9RjwLchlacGtOsxEV8HSfJpvJHgEch7JLEAlhWNPiNVWEfDiuC27TvoJs8b2r8kLJMLwR
UCWrH7MmZ7uziouIg6SbnHx63SrfKee+jTUlxNCjemj6CAMyIu+d1R8X+R9d8Zui7GW/RZY/QMbE
XjLcEpDEkiJt981rITsYEeFEyHMguM6Ju6nIHid8SzRuEWriZRmEIJTAlNIiNLwMJugzTB3crOQl
8IBfaMRzjfCoau+PZND8cAA4s7vNHF4D0OokRek2glXyoRMl1VJLVGmx8Bu37nyNdvu1AQFjSYLt
etkuXnpS0VKHm9ZgA4jv6FmgSt2eUmSa6qrnvPMC3oNUSWtDdl2AajaxIAbvwKZgY/beH1iIkNEv
TjmzzCSq8SktUmBG72Tjfxpu7Va8SzV7CEVoXthUQ2f2wog4l1z5+1Xj+lXv4PQkEAl2xwkSxJln
lEG391BLOkFz8ytRyunEeaf0qbRxQqkLIFbClTxHPYYVF5vUJ66KAE7CRsABWa9FDyp8XMtk5zAl
bNo9Ns/XQjmFKd4k92EtfeH+ZT9RuldWeM+9sVWxeKVSntXZAA6ppscYjsGfRgSp6dGksLyHzi/s
Bwy7i1P0DdbURQM8g+Bp9+W8ADwkj/Tw+QQUXogp7ZwL2NAJyvAOr/16eTgF5Qun4OykMrEfpcJn
4WkkWtbKyL46Afr7gObVr5ukGM5mMGxU8HmBHqGBjJmPyhjCCeTeHkbQxsZZKJUo2WowikWK8shF
CTK2xNy7A3kK54cBBGi8n1gBd/qRP5i/ISxSLP/FIC+/MtUe5aSGnI4+AeAqyw2/4eLsiNpj+tkO
Ogn1Ld4k9ivVN7f+7/htAQEDEDZBODHL8IwVVYvhNTsfsKPs8RpJMMUNun5AN+FM4xOC0OZy7IrD
bUBZLmUkm1x/CggFdLCedKFp1P7Nv/B3wrItPNaJ50/z7IRomLk8I8QSC9zJaLyI9PeAAHlZ3r/r
SZ6scDe1XGNUQQJVnoXM8ivLdua9OY19yh3fZhePtbKbxtsKdShqdFf1gXRJNrQh4L3GTOaJNOTp
DfowShHtYS5OS0FuDNItNDPlDrjb4yaBRNf9k1fUQSgjjTLtpaoEqkuWmAdTZU75T0gmQKeEdRmQ
d/REs26i04OWljHjoXBbg3gVUT+pAS/51KWVMIt6TKU3/oK5N2XAxM0GL9x5sHcle4+Totk0f1UM
pJSDJNAxBvl09xwAvNDkI3rv1If8srNnYf8woVDiL/GAl6aVBgk2Olh5A4fq7NvGkTnRjwBNoR67
76+HULUBRo7ZQOtL31pyt1W6DbOaRUwPMyLEfjjOh/f/4aP2Z0D5xLUz9h1nL4bk9tLuKvhWN2eC
v/VoOzh9knxV4XPU9k6FbNki+i5AoEoRUzkmy857Bo4gHOLS7/OQbbcOVu+42q2PJJSBPt8KF0Og
8O2QpP2/q6e7A7D2tzI/deUI8EwfzhAv5v4cYEK54AqR2yfNmaz54RNgcisOpXnoPzSAmi5Jiy4w
seUpvvUtUt3cF5xBmjd4H1njGi39sQyhQ5/xvuBY2HJMWMXIJTLYgpvKYSqMHJwhi/AxnP9Z3QLR
IliidA7EvSzogBR039dzo8cF0ksFtfGYV+3P/S1fvjP1mkOzPu3XR7pWZIup+YYQq7iK4SmuYhlL
EnmOJxtLHjEWIJ2IVg1C+5bkUVOfkHbXg4BEnClv4C/tHNZWJt6h+hsD/WWW+wNSHvfujeIyxJ1H
aGSCNa6hGHhrwyPdCEMym6iGLtMfytUCK4RcpDVx4uBJFjWnYl/OQ4a/2+zNbyv+pcXIkWLRe8oO
06fRGbxHxbcMiBKDtwfs3ftrHM2ao2hMCrnDOdnWpjoKq9BPYMlreZX8FnxhtVwaIqkJkQvm3WSG
a8OKtxnDF76zPPrInP3CfNyM29okOqqlHKpUaEFkzRlaInutn/9EbtmcunIPVSHv2wrPgK9EbXyq
vDFW4nPn2G8q0NKET+jEWcTOfZhlcSR3MVqAAc8Eyn315NtKWhy6C8cdBOi1PNJruNo/R6+crqw0
U2R5NmesHfliHs7RN/ixyEvnevb2pZvwg01GfKMB9salRlBuPM1gnvkXNXXUEG1N3QoyLDgQW9Uy
qFwWVVNwl4tSF1bm4asF/r3tMU9AAYIos9ioMRHi4aSxnBOUm+vznfIp+f972/MxZenx6R8J+S5t
jN3icf8ZUTPX+zVK+QvPTZT1Z4ykXOCk3VjtQyHx/3ba/vOuftcVJl7asj57uzOKZ+y6RLoGADkq
PZsPM9L0XluYwd6zYAWZDz+LHeZgo5+aTPuDQ0OrsZjMV9LfjsEnoHLQe1NFOf8jSq/RAthRjbEL
vlvJZOxaTM0B812GC1dvy70EC3ANFCa1p1i9qZZbsUl2DG2SF+Q0P8s9PU+Yg6TKXx+iBSFoiVc1
7aO1HcaJlBuWPsN4UfqiIxXfmss3KXOd1Ev+U+VxTIx0+SAV7QsFrNz1xcXgK3r/YYffvSTfwhbg
HiBD7FlLBC1/HndfD0yqpu40/OMyjCclh1KjlssFnip/U0AcO4aYcWgMr4yr9p/LXO2/PyaC6s4K
246JXCxMfl06I48Pj6ylR4AfEc6ypfhm2Wb5gu1Dyp/5yNJjWSA4hDog/vJdelIo0Wu0vGLLuwLs
HbXG4yph/T4B6KoB8muzBPRiqWHxixRXcsRJTgeJYjWyBCsZrPrl4LAWoYbVDVGvIK1ZnnxM3bYk
CgznsbVv8CeANMXSCperCepOFVg39YQ3gwIc+V3fdyhyzeVKqqyAXNwANyMuHPv8sIUKXGzZUN7Q
v55m9YKKN/lMd/CixzHkc8NBSjIsdk3YGcSPuZGMU6Vh0+6c5RSgjNeXr/Um/3oIpHHIePt6oLys
Z0+cVcM3BdNznioVMDL8uN2UNNCgL+KTMeVk+be4GSmos3o+c+gonMuxHwGLDxQQk6/eUhUVCgVv
JNepm1O87ulOjRPtSJpmTVOlxCj0FU5c5eb31dWiNUqbldnxjj95VywbKMb1ixDVFOtl+Jx0ciU6
QGO0OogJ9oGfSw7snkftcNPGciuyqkzZXzqjPWhVf/7exsUFK+sTCse/lV2qEOgpLkrZjFA8rFY7
pJ0p0KWR5f5EGq5KorIAuRhce1hTp4bHOTSwyYunl5fOArBLMZ+UEv4L/LJ8aouAZvyC2zXG0FMq
+wrWT2HG/AFuVLR6PzyW01kqKAIenBFqjgq27me0C0CoX93Yh8ZD6IE1fhdkfzPiUuw1DHnNpqEg
dospkG+6eYM/rqt/40hO0028egQ76/QNdv6qAl9FTTRTTArX1mHhm6sROHC4sJLZ0e3+wbqsLYe+
R2YY5uAcdBqJ9jEXpR0XJe7GNrUTzhWr0LCFJV2pfxgKxI1a/iwcbkplDaNO42tpp7RhexYW4wAV
mw5nVhOMKgK521XK5gLopBacJ8kt+wKKAIBPx0gkoUF2Xvczn7yRXrOOAM+PA6O7VBdPrSxJjklS
cTMbv4trZ9YCFsDEKa1NZ9JUpqVHOt4V6pTOEgJG/K9SyOBkvqOlYkwSSt3Phfjn7SAjrGZkswcl
0enWzIcPl1PUWmnesZZ7DZHJdDDGbgWPE5pw5DdypeUq0rC0RgTtd8CWE2QqLU8sK2CHLH0/sasK
riMsChZfTuYlZ/NxfNIL/OvK9RFlkBw7UZ/Ti7HWHnhDGKNAGMVkv+SAq3xlbV7CLVNIvugAVrLj
uFEOAIi3/n3xmhku197aprimHrJeOuwravlUi7x1jbNDgV8O3W7X33pMUM1DPvI2SwSYdEK/j1jb
bUWeZc77HLcw/AlV1UEe1wTD37N85KyT+rtCNcx/nh+VlyeXfY20bDM8kwbknIWO7OrbavBb+t4/
jq0rc7Z+MgNxDelbKOsyyuFfhdfXprg3GyU7VD7nDhvsdZSP/dgwvjOSnG9bRa/GXNOWyLjXjWgS
Pedybov+gsNkkLxSXezxlzfpPaijgzax7NqRcDXUBbTXmHoXVnRbi+y+E6rUVA4W2+x9pMMBSobP
AEsB5+HTgvOkNwEIWiuuMBDSHmKtQwiccjeCwG3nyrgWIqWcG+DG7rdLD/m4UoQWzRHHsGG3bhaM
mFGrIo528l/2zy9fk+PRsEspBn9eeEbzOWv9ig5GOXcMOLeqLM/Kat7Xsg7FwI84ZjSfDNuL25eB
RIpCdlJpeGdiOjFNFG9yojRX4eq3h88zaX28sRLQmByD3UPgLwE6dpvCcqX2Fdtxjo2/eJmWpzt4
4OXvVc2sfQ3awRozhcCL6Ixfc78SyBCCcDiNbRmZr2kHvf8Tms5bdyaxT7+cw7pjjkW1BRyqSy/Z
DInqnjnOkjTmP55NJ8yUE7fh3Ef7Xejws9fTIfKo34G4WYkqkleeLCSJ5LDwhXVrX0ZI6pIphBCf
ya0gMoSXcJCfgm3R07tyLDG2yfrrwvvFw7XyvUDZfean4tkK/DnKOci3ubcgvTku5wRyVH36RCi2
/qr/LKF0qHIYg76szxAcMBBrxKbAMuu1E/PEt0PgiQsYrTsInsWOQ6BkBru3FzbPV54m2jwMQse/
O/42zoPz19Xagk54mH1irmDCmPrvOrchD6RH4Jgt1iH9of+t1dtFl9x16Ib5W55ySo26X627QjHz
yWSVi+lQcQK/X3Z9L2qgv45VLr7OCn4nCsmGL9M/R0gFZcyod5Zx2mEV4MdjLJJ82I827eapPP/O
S0DrlrXkKKse7N1LrF0oQPODUbqCq5otDfp1vlyO/QkFjBRR9tqNHjJT8sIYx1IG66jkQK/RhY1u
j7w4TgFASabJRvBwwI/5iAyc2koBr6KckhZ7OUdasskAIWgUUr4DhqBbq4evRweAhHVVXDbLo7n6
Pmb4XrBLitPcLX230wlr8gXbBNPOpPT3Ud2zSyLFIKC5tGjT79AGmIpfqnjsgBNEiLCrLjvNklc+
qfUrE4zJ0khjRzr1kVnGjoBC/jqDcLl4V5yx+FO10hsshujdvnxJRBogQCvwybZlEbjDjmazHuz/
v4mN+W82KL+f/lRYXFJHc5IDxFQzVGhRsjmRiMdBRL+6SnacTIJ3/gUqxu17hPHqxB9kH/R4rxRo
924+PvEtLofz1hQZ5lZTklva/tExBkXUsFpjfTElCK+zskttzhPoPkUnQDcMSDXVeHQDx03GXPal
E8QMZzzS59Ej2vYEHI0yOra8eGzmGHq2tOiQYWvsHEpVmdoP1ELpsB/Mn+QxZ5St+V/CWbIEjSRN
bi3LgpynSwSc8PtuR0pNCyzA9gxllslN52feZJKR9aXADMBKLVIq6oAmMhJmXRuENPnOP4L1kTB0
+/7hco31aoZx5Xz2FRYrX5SqsvjPjDIwhsDVYoZvNIaN7vYyyRm8kje3ehPmfKgseGBx862zpvt9
BlblvRsCRSoMvKJv0C1tNYqMiSZYj7R9LuEx3xCKmeDv/YfBM20DQT1h05ot3fFdrFUivBv8GvnW
HSlq9CTrnErOLn51140xfjmqZiTcCL2Hfxs0HXFDzdmqgzZNVTeuJtxRUEBZOvx8BLtNHJqNINQH
sXOLvx7Mc3XBnJmR5Xtug18YAFSuNBJEqiooy7NLwDgL70/8HaQXeIJH0TLDr9aUqQLSeudO3wo9
GINngGxPEv7JPucjhkf+hpf7bX68Ebb+omVu2j+ash2ULjx9EFzH0SPh8YE6wbnc/kFwCZoxccDj
VEx82tPKgmZU5hkLEV8rS8eca3+QGw8BR/pmRZBoVuNwj5N72aIcvmqUYffD4VQ6E3+QEGeIB+wB
ynk9vA9WUExcAcR0Lm+OAAsDrwRpmZD83EXJPbllGe48BB5fVzziP78RINoZCfgBPltdHESgltI4
vTKLI30rnpyF0bLnO4xczINdy+JVd9P1ozOuRNYAUL9RZNX+SJ9JYrajMboKKK7d/SnhRkjV0rXg
uubO3UYSEIxPC5ZImki/19ALb2t5TkL3lC0fmihXH6GYaIHhhNeuOoXQO6tQCmVNWhC307ZZTXR9
7rYlYMd8djcIQC4W92VmKGc9c4DcK/RDusTKXtQjYHqwnEuaUGuUCdY9ED7A71215OsjNGxQ228G
jFcdcM0wqyr4GUcDOK8WrYbvrGqBZZwosgZJEtyKk7FYrb6zvdqHN0y5YPDtRgr/8CVfn6xGkOvg
k6TaPQYl4JBP2fOgF18J2y9RPDTR1DZj7xwAeGv3SjuKffYjV3hDwfQQktFuk60X3ewzoMN2x7vW
LdEQYN7MvHpG3745q8iEm1s9Zpj9AztiEC1qJPs3aftpDNNPipuC1hOkMs2fFrkiZin+03uxQYlh
OvgVFRCntkLKAibVQ2Tntyr9qcs6+zAjlnknSGkh5/0Iy15GhiRofwJhnKiaMbW6ZW5JRMoVRaot
fn0GBmSxOL10K13MIdq4Ny1WFHRPSMRgfZFqnmT35kJhCWflJV/lXVCShVcqO+Ge65Srl6j25Wqw
pBwbnS/g7pcSFVO2NaUYgp6zKblyGyCXZ51Hqcmv0cHQRBmEBDByH7S0wkpMk1vZFQLihl0gp1Kg
uKTZI0K5GFA+st/LJHbUn7Cso6tg64h1D3uhOqj4FdWPwDDZuO2hEcxSg1JLlhDnRUjRbGN405Jv
oPMU+MZgYrBXglKpbgAPQ/bC2AJOqCn8LCYhXJ2aBr4W1zrGCSfvSJpFFCztiVQjX5dhBccdy6Sm
ySFKHeOrUwMQiTtPNd5caxd3mKeMXKtGXifcZTvJ9hv0NuRr8QatcebprlIUUxt0dbXTx8yrTvRW
ALCKibrNV+BPIqtIv6AbUCx1jirvteBiYQ5K6kq6j2SK5RrfsEYorN0clIwNl9mBi6uejTEaRTvh
+4pFD4olrH5D7hZfuj0MUJ/2MMSWFOK+1pdUlkuUssGXBGX6S5KM4yjPoeqWwVePqinLIdvdyjsE
D0UAotFGjIZfZaE0de4BP1k91/v3cdwLMDoy8XmQ80fQqUPFIEGaB+yYeudxNo93VAD9SdUcMpNg
/if1cSjlXx0nsrKa4knDN+zxc51i/Gi0rtm+MwgoQplQyd2+WuOCp3BhdkJerQf8zQoFo8CDS7+K
YA2BUrW/fJxaQphmk/kS+0GbenbTtMm9eR8+eVzJJ4qyOgSryzkBXH/ZUpp8fjmuGrmrXoEJRREF
P7ZbmFzJBiPgBn040r0vIxOO1dbWbZxbmcdow/fhRIs8WN1u46aPh9z5zbQZhQEwDBp8JU11kuVN
QHvGCqDa8TA8AT8gByF3j0UVI1Eq7DNjJrTQMlpe966u92RkriRfXnbmLAvDdTeYmt2lm2Gjl1Rt
140NzzfyquW1akUJYDPhVrRyB9yxgJPhpQjBI5hd0AzfBO4y8IXVEvmHqmcPRgEsJhAEWHyqIUFz
fT6E1iITk9V1VBcrhwHRFLQM75v4dwiG9qFQeVqzuw6naU2L73XWvMcCDEcf1bEmblV1fVHevRGM
fmBWpkLMT45C+OBO+MhHbluBuWOVuRtJ2mHXghyK2xQfnn4GstkWlt55LnNuE4Wa2n/1ApzmoFci
JGEjRpw/sMvql0zvLSbEKVyDyWGT63BOYE9Aad0ReAgO74/UImUGTZ85yGKoYW91h+5UHNoydYqB
fuA8iBBK6hVXq+xCIs9sGyNtSStCb4Rp53k6UhgaHpF2imjgPiOKIlFV9/G6N89UDKVlUToVWDSG
YIpfmoqlEzpNus69p/NjWcmej7wbxso072bg4Zpg8YzktToOg9jiBOb8JKfZbj2dO89pqw/jftZR
Tup2jiAIo4JIA5J01Gkce4WLz17BrUdrbTEUQqFTqEmL4dhzwsfzZmuyQ0qjcK+T9zS+1BoPTF+T
eT3y/CgiBiygQjB34qVHb5AzDKifyEHdp3RanQq8fywxigVHOwnXhOvRZbKFisbo3wW6sAB/xXKW
dKxFg31Va0CzB8Qae3XoBt3oB6Hr34mqB0Ht+IPZqZitKje5pZr0F4JQDOyYfeUhVLFqBPREU5au
A0oBAb5BPRnHEdXW2T3eVJRPvL1qcPIMyyFg9fhi19q6U78+qPTDMtcmxamjld6Nu3/OzZBPb/bw
1kfD1GMJSAZea9xPuLmE00yPBglskXv0wc6ZttReBVKvfmsoyUkmVA/oC/mAK8I5QIJ5eX+XNfv5
COWuoHhSQXUSFNZLxgAd/cH2sALVMlJ7DQF6GfSERSzNFtsbOfOh7kMbP846nqYBk4ABzibGCeGU
0iouq41a0k750x/984lROTPlUCgRfpjxzte74Iw5F7Aye67imQZuysyjmtAfWk5K5kdzIFmUImY1
UQDGTVtS0gTr2zojxi1RcWlitfIiajvoc93/M10d+5/5LZ7VkskgxkttQE4nYY6lg3L+HhBDaFkH
pZqoX4ZlXKQ3j0OvsklDn4Eqavs2+AAMn2jtF828tlQJPm6ERgBd03xSoA8HzJTr/yjzni55fWyW
xYgp372PqVP9Eoz8loGOQske3ZBYRt+Cu4uZMwOSl1LyyZ9lHcVCDf9ryFWUBgELmG+LIim1RUSx
Etn4p0Ms7uwGswsVmMJx9sZOjCAqKzEbJm/RIcyosuOkNcn+BL9CWvS34zNB0qnZsYkpk1Ovv5Yl
MOYshJGX+II+Ae6jVA4O4NCJYletaPaCASobQCqE5eOWItRBMck4Ppp4L2mwXzWyt4NcfyeBna3u
9dWTG2VkZtTHyYJDMXOlxlIvBcDRAl5r0lP3RcxT9+Kp+L0U7gSA3GSBF9xHUYfean7j6wvKOHLx
nk2g5JA9oQQ5TPwI/xINqqLm2rP5RoiksJf2SugjHDPbiWlZM0j++nXRpmmZOxXu8ENYOoJR9kdk
WXjNNn+F/nMmPlyUOBKzc2a0PF53W1mrhpntfPUT7xcdcc8OpwJRK32H8S85kEZFYY/VtSWUqCQm
9pbQmagifTey0LL46v5M5faq7/A0dv/ZaOVPfDW1NGp6TomoSaHq5BRop/U0OQ8DBYFfI5L1uGYu
2I2aQrAmdAnShUs1f7QTOWqnyKmNHCYj2zqUBjxMDrPa2d5Oa8ac8tGXEmwiK1bbCSEJHVoAyuWA
OVASXh/tDtT2rAEW2RSTmgedPDppooWi7W0BB3xjzQgz5tZ2kQpDB5LL+bZ8m3qU/IRnQKXCjw1y
oQjk4ZoYJM5dUdMEhXaY/uGQhB50m2Y4vGICCMdlZ1jjRE29XgfviShgZ0ii23dP0+UmiTYkSdmW
+csObdxfbSVW+ZcVbdqmJKMRqAhxfbweoc1W75cGOXZzZO3PZcgiQvs8863PNinu4tXa+FHIl+sX
c8ut/kl4bZUCUpjT2aim2oVzrib9RYthSefZFRPncHoRxsakaxdQzI35jTiDrO1yqB9dnMR26f1E
7R46fLT+IU7gVuQebSsnm15h7CBE7GitTf7a2Wd4lfwFF96D2gxlJIS+K8EQGt0zAMsBe586A5FO
kr/oVhZB19yWgnwuvHS8E+VuXidoV+ged7CGaD8dB0BR/yfGTehMCrql2KqgyD/DDF0GOqTcsEG/
3wiO4j86SIAYVQC6D0Q9u56s8MNK4nUaM0qFRl8G6bP2Yf84gg0CQHtxjJmrPS5yJqEQXSLK/+RU
Y46+0Y9XsORLoghM3ZDnLkL7q0zWzLvOImM9LOuhVcHx+fl22Tw95Do3N1qJxFc3pY1HhfpbhkMv
HwgxMX3RSkbmTfMjHcDzFbVu5cymnUSfxpxINXTnBiErIXfGENwB235wgIfn7JQQy8u981Rg5f6w
SUeOpCtuq8QtaQ/B1x+ZN/pmninpCK+PZFIkZUgjoBfMvn3/EmdWIetcVU+CAayqsYnfeengCwkb
Q0yoPTgv9IpPPJpZDyhW1MhLIj2dcCut8LtKcoVoCfG1ADkvt6GLJu61HrXhoSv8EIHy0NXwfDDT
FlCHFTEh8jtZHx/TwyU/iMRauLZRxuHQvleSlfus6h/i7aPl7PsadjvTIVv7xCN6aXZAxTVDg8NJ
wHmTMNrf89yySt2vwR+bBZixL+lAp3EctrCMszwwGamZdvUahpzt2uWrqtPm75zRSPk+hbUOPZbl
EopqNiSoOybEsm0KyTe/xhsxOVZPN+ftFIhn114LTsjUZYDFoUBxRhFqLFjL26afoFK65iRUBE9n
Wgi7+iEzH7Ar8vn5X+MaoncF18Y67sk4E+NsY0tKwkHsJCIC7q8oDWrIpI+mpUGmhc6HL4gq+3A4
wMlTA1PtdDj9rhB2Dx5qHew/oU54BNIhOmEn9XU6xKuLahA+8aL4rpcWEKMj7eQUu9g27fV074Dv
9FlDO99z2gCMZK0XW1U4JQbeSdXDzSTE83EsA0jjLodkelx045vujrhcbfq3FLkzU0gRlLE7HGcK
n2XOwPkRvFRc/TWrlul15CB1NT64F7MDbhk+MytHzXxSZRnqaS6w1/kF4Pfd9ZDXmYl/2dzJBb6j
3nCh8B2WQIgD1SH/mYB0AcdotsVj+hsU8Gk9vMEDa4zAuoR+WWzf4xMALJRy6g8+jeDrlHWTV44v
/wi0RE5qrVy8LXsG9qWficyY2UFiZ74tsevA3g+71UIu3THm28X4yQcxW8I0J8YABxPebHs3MSx4
qsiSeT6NjznbFHy8sD9FJxx+tCk3b6DfXKYVb9JfOB+DFKH4HkDeN3A7pCYuNef0pJRJwa8aNbp8
Smi6ozWoRiuCiuxcfKxbcGMIfU2LLeooVkWZoyQ7NpIlzzscehfQwqqMuo01VnFRUugoja8UiWrM
LS97WERraUvgXYptaAaVGGPKdZ9Bqt0hSdjnPX9jnz/PpS1MMoidENaESTmaKceXLnj91YtqF3s6
xyEoemHoaKqEkgqKbKLTL2+zndcMaHiCnpJOFthU5vjbOJ9APAzE6SVQxvzyBvM6zahE2iTr2dVs
SDet7CPp9zM45/bYA8Th0NVcYMAGeAlf3KVf/a3xH/EIbpFSaZXY04QQlCmrHmAeA+AvimLBcFFR
2HdgSEcUk9x8g81XyUwQDPGAb2ydteHRwCM9oBidlm/oRgykZesT73limi5kwrMX22EuvIJ66D0b
X9OcuUCA1yE3UHZoIbPA30IUF7fx121l1eRCmTuh
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16560)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztlHgsA7XTu3se9+qgRV127brGn1J+SpZIMueDb+AV872JX
nOXB120GyVLNbjkhWTWXGQdsLOXfaXs2I36xZVRiwzpAgBzfQJrI9hG2kq7bh9WznJ3xEF5DLexY
Cq15Vdb5gm0qDaFFZVGzlV0qAsnNmU5TwLZdRsYlrsSd1i9jUQlzfmNsUENvXGN3CDlY8CFK3jai
INNNriIElfSpAetTkn9VmfppFFOF7wWkbrMeWuJ7l/thC50PzIkDIzK4x9CtfhJd3F2cp+VAeBKF
LrxUYaG5u5XXGRyoHikRUGoKOXXmqvmZIKvGnqo9OmemjsqjILGrPxP+3Dy+cG+LmqgRYTxy9X3z
oMfdSSQ6KvJIZvqKnopohLc6y0/oMFyP21GDeRYafr53M5KZ/f/dLwptOby/mIDvt7SkwnKGfvFl
EpHTWq8Qukwr6iDxqQsNxGo493Q+4LG/yKuSE0SND6bwyarofUfxPeW4laRQMKn7H0Tq/eaUvdP7
vXl1nkBrtRL2reVVADRjcpDm+3z/jYigRFz9ttrA1C+77PRjiowP1YG1fdzffqSmOJ2j2mFWYikv
ToyM9T8m18egCp2ghJoN4eI/VKWlDfluDP8ZTsWcngrJsn3e/GAOL8PDe92FDeVUKpkl+gr4V7Rp
2aPnAyyzEcBeVlaEkmCZITU7qdXWBM5BIqVU+5e2tVie09XfrzH5MIHwUfVaSuy2u55zP0BOF7Gu
CUEPlLKnR9X1WrHVcPnd6fkPfFulzaTs2HuDJi/KrTvbj7wCFie6P4/WolNX6kPWjcz9aQ+wnwhS
Cl7c1ftfyzJMNbweg5RPfaq3a88McLpzC6etEqO31+rgbz/dfhINoJkCiNixX7xIp4n8lci7GXoM
doKmP5XLBXmP/Ef1HlFhsKHBbwP+AsT/HJKsRbeMXUWPRtcZnkpB4dP4RxWecqcBPC+ggs2Wg9XD
flCvKjr6I9RAgAyAJYDKpapS2KNmOBVR6fSfSEbVOTjDKBU6mPvbIW0B1GrxujCVwXhYhzfa2n7s
pSvvjqm7xICaDI8wL4+o4znzeARXPT/oyN++/EZb2EHhIwgPpY5/j+VTdImaOHA9M1rXQQLS5YiQ
d8fE3ICl0Dc9YPx7Gi23TU1UqiV1wx1HdnYhTuzoxdEq6NpLA258Wh+rwSu8vP7hWDb4IQs7YCmU
6c1ehdkx/jvYYfcnI/kqhIpv07AlgCablcW/IVHSudlBYFvHKGNJQlgPw9VF3ckGkh8Nga9O9I9d
WGpkXkOB7qPMCwxtST5z9waEGTMzhngUhfVQG3HBNTQ2/Wat/S/5ryngqBFCJaIgUfrzw8VYPRpx
Ma8yghJP9QRD0sXR0VB21eJw+4iLEg1o1b5xf9NUkYGOZOEZKU4Stu4K+cfuS7iTeocaFB1jsdNn
ntMoV0FAqRuj1lOxDG+YJLiVc5qi1sBf6RQL2iPcSOOeEQ+PD/uFwCj6180hC84peYYWAyHN1Frg
05/zwXh2E591TYe4C0h0dT+Aos4yWciHzN20jWOxXMzIS3G1qwF0EGqAijrnXGLcGocwxkZPDg7O
+ZIkcpsjjhwsvUCRAmpdYb12MfN1aomq3wUg8VUEjLXBfDpGSJm6LmRFOyE95KmkhVn9RTJI7dRC
jwjcf+RbuNT2kw6BbtbyviR0PCqcqqTHTP/U7tvsE06ymyUlA0+8IJ3mEXtUVLHrlnKrg8hrwXl2
4THwUppB9JDYFgpLPAXCkF4P+9MlHt8xmiKzjjY/jg4X5Mak8s5L1GLzrK731k64QPGLnV7Y58fc
JJVHuV7cVknlClqd9DJbTGS2lpfnm3E5Xx2a9tbuW2oKicS7VLIMnVFCOqwczmsysYtdtNgGlee5
1fK25W2QAG1uuOeASXuQ2ZNt0bEInni+G7PBrvOi/pIjashgqTgNL3SHHmA/XFMZnHX6netOZm3e
BlfRhSx0HBjP/WZtK5NmOcyW9rMppg466DDbqoPfn9ht2ThmNdE55qlP9RBkGuq3LmORr9QPoP2r
Kez2IK03BRuNytY9tB9JWMXjpeNTFfev40Y2apCXKqghOHbvLqicXRe2RpvdFsDdFcAH3Zd2cOx1
is5sPhAMvaqwmdbkvhYB2IccISAzJCjDSLxf9u2Ohfbk1LkOVNmX/lsYcr4M5bchScDMMvbxps9A
/nKuGAdf59tzE0AtDeG/JB6q9/Xatq9vDckMhMnW79Nj2YM+eA4nboeZi2q2usxzOCsHZCPMfnmQ
JdiYT4tcLjLpV/MAsswTqI2YwYG7Wsr4TfTd62xl1K6gTKPFxD0Bxeh/7gMUL+s04w2ABMxYeOUS
soGkfyrtq/fWWpQisTLRSPV3UDe0a8xM5OL7koiF4kZg6J6vU2gRPDL6/9fq88Oi9w56f6BRRcy5
zn1CYRLMCbCuNo0bQ1ikRl2fwa6WE8OA23UlxdNZk2+rphNHNk/UloVCB5ZXiKdP89w0J0JyVcme
Cc0Eo26iADVldbzlUVXNikp8CU4tzrmC9jSh4NIpBU6d0qi+G69Y6KulyUxpENfSof5PXnrXrb0Q
89dsh1dr1Thsq5QZcNvSCknVagRzD5eUWy/u9tPEyziJvWGUJQOb/YSxz+I915Wlw3Gxem7EPsck
e1PONwATUS1zh0sOiUIChUN2ZysliabYb/tSsNGvzBtEp+DbZPlcoyqbJHSoP1TjXAnB/TDMobpY
yugtm5DdXSlGUrsKwBiBRcewN/Y7XznivnNsc3JPTo1vYK5Mc4DCRgFEZfIqde02lPpl2OUw54bh
699OiZk8Z8JHlBC/A3sqOSelp2MNG5GW1MrCAdQjpmlf7u1evUvOQyjx5tM4G0aaGiNS35xwXmvy
Z3hId27r4DbvS3CI56QsLSh4NsdzjHoirwkfFFUQco4kP6r6bBSb+qSdg5mYwvieiEwLTDYXGdFR
9H1KBQGXkHjNWieL8VYuheOudvT56+fW+kiYu45hauh62DQdKGeGikrGmLr6O7Cs5+vYXEzV1A+o
rsbHB+3w/DVKGDe6r51wO+1rKxqQ0Ly+zSKNFfswqm4qVO9OSIjiL8P+9WdX2WRpsnvOWOa9LUFo
NQi1p429r6FXqSXAxtJFZAgtNmAhrqBd28LyAHLvJsKdymxhpLsNGZqUP9VODIMT/jg9FeKzeDhN
K+mriXZRagg47TCbQ2xZG4/ay2CZfZ2sKH10qBP+sssi7JR0Ir2VywA0EPn9PnMhtTgQtvqypQKp
tC3vUX8ahzFNh3Rwo1+nu3wdy26gqFRexgdN/bJkXd15oB982kk1dlJgX/DPRLOnOtTMfIjnqRu7
2BJeaOK1r1bEPNmwXEsaqVzTfE4vFlLEBmqnmT4YWmW6Nicd9qmfnMC629+UyKOGD1E8xJcFqsai
KGe5AvZuNbA6toK3QaB3p/GBfA9yvQgi/U5HY2xKehgk1556cTgixJxIZpNI2uwglCpYejZIoyYw
6MJnv9EPF/8HnKQCdAU6BeocT+XCeiSTlDDbaeGtC2h/HJjGXOM6hrc7vAC/zpwnoyF7BrVFoaFr
gUbOuzQlFA7zzL7gukUB5wlipL4en88vw4fNqQVoEsXtOJt7+OwYxZGX2DVrbzXE/u+6qgVZrJE4
GQ7b/tFeHjN2MmA31MwbHpN90Bx3MkW/t/UnXttPwJLkHGqRWBEg+6k5qScLFuJU9yfxFL6Gl1Ts
wIRCystlJ0QiGF51P+e4bdezj3lGSLIsINtYaa972U88lqm3si79cpBX3PmtfG0LWfmvcwEQ5C3S
O8DvsGbXqhKhQI0hcp/q1GLivekWYvv0DUYQwl1D0pqHEU6HhXAmtkavBRzh+bBdmM4eq00j9/ey
KMDXJ/KGd1UHloG2GevD15YewMLbBrBiBbGCrKoG2MlVx4pS2l8Ed6uFi8sr8JvMm5BfOB4qMX3k
eLhMva3T55O4F6d1xJKytcNUWG3o/ioUCGqLOQbz5VEFJuO0yJNibwfl0L6Zq8nGoa1d7tAFKrf8
di+++XVql/0QR3Objt3pn44+I4/xFX0Fo/WAA4Gjx2qN2v+gBwp4PmFB8RFtRHZzYeho2dUEaoRS
iMRoCzeoLMqR3IpyV+4Ke+/YXueoKclTjREVWIZx+xOC2/8Mkzsn5exuL8xBytvXlZOlNThg1q/s
l+UTvKbilMmlpnfJWVQmVvY1ANEms1T7Fmi/iRqLt81K2quZBkn1yotrpJQoXWim5/1Xx+FbJtpc
Z5W0Lei80zbfWjkV6fJJh97rvbydPikIQMr9ggiVBXziaHiyz5znMYChR+noERf30uWQc3r6i969
l2DppBpsIOzfpUufIvlfQdviduKBkfPmBu7cwp8Z35r4PCO8d6/PVWhVy/1LrRH8cKz7XPVpdgs+
Po/s1l+Qq6117HHXkaG3erTJFyrL/cjeunpIxssncNIfUTlC0ZhoLm/orQiCQ1AUBv/z5KFlTyAo
VSYL6gRlt2mxsIMjxj76F72fc+8DYK+rp6lD4fpUG5VCVquHWtym4EXwat4n6LS25KP0AI3Pz6IV
tdpsgjz5Il7fHQ5P3NG3r4ovkDcCTh4LSwibzVal6hT0QgjhsTRTwtSyjwURaXESfpoyqtm08gS/
kHuni1hz1GYk9h00Z656w/xYEMFTzzA/nP4mvA8eqwo4IxrSOxhBURV5iLrnl7W5+6u/XyeGswma
UVjZu2CdWHnHs2DTL6MZA1dw8CcQJnRxDi0iJDV3Yw5QhBR3B6l+6opFKyHYGPchwT9kYF9WOnq+
sX6DCc7wxGppgxXmZQdKcHGDG99/GEBN3JzB1wVu9AE0+x2KFcTOKruRuetEFiZRugsWJk9CSMd/
Pqqy/1ZYooTmoIpm9FYrtCFnT9cZPY74f61YlKZkI7Exq+2450huOnNcq0DND0THHUpPYSkZ1Cqf
+l2kGlL1EFHj8yRGpSFjkx7gDHvCk1wtgb1ANbEPaBAOQZZx8hZGFPitdaELgSXqAwDmmmB04p0P
hCqQBvO7/RrfEphYFnJ+mjkm4HdtKH7uRiYv+QKjpCSofNUUiVufrzljkzStj8YWPOZx7uYZ3Pt9
6zoVxfaT0QlvhZBypPXB9AvcprFuQVdI0CbPafTMDyScVAKXK3gp/N2kou0/LjK1xxKRyNpMI5/J
s8ZUxEh3N6SaPUTMBtlbFt62nnGUR8BSPx6xNpjHft65N3D8MnyNwUoaxiF5jyZmli3Ye9euPJpk
tpr8tzkhm+mqOfWrnh6YC6wOo36VeNLL29tZhHPG+XzhbVqj1t1o6Lflpaef8P8e1nfLueBAXAos
hvJ+1/D8hFZis7N+I9kOsK/ts4QlDxXnwXUACHo6nS6+ediDinAvxlSRJVkBDnh9x2UupT/wmWpV
LOvKTfv4/9ccTpiF/6+Z4K7s16m58iG1nr5tayTHj9eq+xtq/XVgokWOI/AvlPHYa1M+GGLEPO4h
y0Ld4Ypo9LmENFgAY7KRnFxujX+grSfz+tJiiULvhK5xcL+H+pukbgvy7hF7sUZzC4mKlaaJgcja
dZXxPUVudBbevACchjTnaH838vqO7f6vn9N2WDAMjViYQcb2OjteHH0io1avNJO6LN0u5Z/BxGiJ
L6PDB3PPEi8+iFiIF6zYSU1kD1C6XQBPlzym0BztEtUx1Hvopmgz7F9Sg7qqTHkITBUH4aaMsXpR
qyrpvoTQYUKbQCZfpzL8DkJrw77hFAFw+Fa3ZCQ7PT2FWAkUzezubjPh40kzSjaKAFfkZbN2qm0U
Gr8IXg1PHQdLcesTh3D0uJbsj1GGdYHMlV6KNx+rNn5LpBafB4oB+0weRGlJwsm/lQmAiIK3GxBS
XR7FMD7djS36sPeCSDUIZAmb26Afq97fmRdVbftrJOiSwPiHkKp2jTS8cZK3LLO2Vuwx3RS6WJ0R
JsvHNqt1lkDqJdrFsDHWZHN3UH/jQJgkhCjAgvo/4bP1fgs3e+8Vww806JoJhsfT/89GDrydvY8A
fj2iFIprpUv1NoMDolCWe7AHLlaRFGsf5COLhW3qKDrSl5iAlYiUVbEYCERth1B68+Xx9aULxMe8
4GV8KTUJvI4s/mlTXrhrbkA8cQpPpg4ZHxIY1xrc47rdyP19k3MGsLLpSVxFY3i3J8Moq51yq1VG
IGp3+5ELe+7e3VWSgTu9ws1bLvjDItgxgbNEFG+yiv7cykZXb/3gSTi2bZOS8ywKS9qjwA8BHyHj
G0DULxEBtFuYIHFIh5Xk0jPSn9lbO7Xur07oGHzwXeBE9MoGBhnxN7Zhn+976V7BPpWuuSh8cfFE
Yr6DmL0pCduDPGNbDXTER1+leirJP9ZJp9j9DGkmcgI+NWueCs/cGj1Js2nt62xOyJEnGNmuKien
FojwXD4CFBPPrIozMwEFwv0eUV/lsvjQB8VrYEXwZVkHOLYGKyNntf+2mYgGPCIgliMaokIz7ELC
Kbh7Cu6yvOiPyh85SBt7XFf5IFzKkVRbFGayIF4BLb0hnIfZYXHfOU1RqGguCNRvXzDqmp3a3Yn3
2IN6Q3PgLKG7B/UBs6kVhIZJkNA1JeoiUCO/w3uKdR6tB3LDMP2aU1Pl4F8fGLovULMF2Qq3gG6o
tPQbnC9DMTc+fQDwWACPQoQwTXLAZzGcAvGtDgBNYQvCcnx0QIChoTDWszGFWZ2cQzXJvG/gw6wz
g8zGiEeDOrSGHNoitYW+k1lx7FrW8yRPfPdpz2vdKD6T9da0d3Gfy40tWeV3ZllxKAMEAhbJl1Y2
1vYJmWWU/nFz6JSA7Fq/IRYHe/9ANTyTOrAENui5qESRYZ1YYxOY7v1GH8c3kFqb1cflDhFdehHa
SPxCWJLMEmtoNRbICkuqMyYeXf6fE4oRp2GVvgJcXVyfbJvpcPLdJzNOWFxv4Ku5UhsELGBiTviq
OlPzz39UDDndJeyQdx2tSgkrVQ8cNV7iN2Zvvr8239TxwVEr1QCj+BwQ1l0HB4VCFyY1125db7s8
gc8lLMekkOpse62RVtMVHoaRcySsYqcb6FqPFxOPkkouDbgKnq2sK1neOh9LD+6LQ5r23ji/qyvW
HoiyQCwIr+8RfRRBu6dYdh3khE/ePDS2UnL+Xr9/zUMW/+QF/bs/saVJNs/Vj6oJxUlM/X/sbD8W
3GL/dQM/VahC/GkUbb2R47Bnq+8PdReb7cRecV3fE+ijFAKwt8ZWswVRSHbPSsdbwoCX7QWMSJCI
2dWJCTUtjAebp2jWLP3ZU9ZRkjpDemB51DOaVGz6NpjsBE+NQrxMQP0HZirpBKny3egZau/rijG3
rEVHGnb9FO7TIqMv81FsBJ+YW660fzOhVFBwT1emw0wNsDkFlBr52iNhovsUm3YNqGcrqjxB3S1Y
1g16hsPoEeOqAMzANwkTCT0/Xo8L852PVF4J99c9LQCSxqMLdndR7GcMMGFqCw/cgf8hgHZ4fC3F
8WmNzcdYZfuRJy0DXbQVHA1HJ/X9ejBmI95DeGlQqJcLKUYI1YL2H3wcey1XzY9uQgR+q1TVbI59
uyvUIcu+MHcqo9ejJRNuL/WnWv0bZ9ktwIQesdJTYX/KxkrzNZJRXp+x0A08D94pbcESeuoVbu7z
sm470JmLNx5n0IxyD5yfYQrGBA3ImSg29PMd7ghRArbCyHRupup8NqWHxvODbHby8dSpI1vT5JP6
AxGE/4qPMCSJtwaoVoJEmNXMN202RibkW6HJ88GFD0L0Saf4Il94KSAtPB8aU1RTZP3QJXQ1d6Dz
/fzYS12HtxvBjYcyclkndBWYaM2ZOxahUJe3uTG3DTKirg6QrQfY3NYFvXUrBV+4YHo1BF2/Q9oz
0z5wQe0Ad5Kc+s+mMResyrEV6GuYw0uDc1rUsTlx+0XpV4KL38sw9GPRQf4C8EWUmh2/tid5o31d
aSlkIL8hmDRqrI04xrF8yGkciS9NK8FlJYg+819vIchRu0ZxS0Xj1BY7SZG4swBUybfXh7HXOJLD
iT+IlvDn9GYGe8OooBBQZeb7p14Xlwyef70eJJBOnujKD9yRwbhUvaYM4EabGGQvr+qvOgBp0Zk8
SgxVfgK8tUKEBwE5di4+qLWEkFo7sazend8QDuUUOzGEovV3PRyPTPPdIQbtcNy92pb+2qlwWQH5
cOMo7jeJU3DdA9D7KYpT/F/lrXmJB0RWRUaFrTwKxoE35h8wcLcNQyawZjW6l6TUuDxHdhkGB/Fv
2aeaArVRU60iWJgFfVDlIZfrbxVIALYUTxBOBJOqCZEdPIA8Zq9lLx2ohLmGFkjLcriXnR1Dir4G
cTJXrAdhCAeqMhGDWJnOEZWoVMROcnkly4Kb2e0uJzFsf4egGRguI+vk11nXlVdR6ZlL0RxRER37
6j9TrMw12HYXNvHZ70qW+Vle6NKf+oBrY5Spz3lMw62kOfc+kfdjoPPMGDD9OLGGbC7nDEal8mzv
NJBrW8e5kqXJtv0RlH7j0l5MdcYQ6UVh+b6/z47d1pccps1RF0isRGpy8emcMp3eU0SwPISTO5Nj
Yy0IuMxqGsY/bsLN9sn63G3nSkjf1gmc/8rKucrxa/gJNCgSnluKD+EFGZOWFBeYVDbcrex8kn14
UHh0HjadbYJTf7JfQgqKAflO8YuNu2qW3R904gOd9FsbcHZsQA+RlJmTbBkrwjjAmwrHnTOpzp3M
5JIP87bN+qBJM51S4Kac0PoHJdnpnAL1xyMF/g15+0tG7CilYL7jQR664Hl4OYcBMtUc0EBbxK84
LTjy68XCy0HrfOPRTqb8+IjVMfo46X1babr6vNVRgxgfoD8oI+22NKABZdGxKYCDBe1emwMZgLwD
dGDARzEpWjsnn/RNc7bAQwts4E0t1MihNDxwP5Khs8APL+juIYTWrvPTQYMV9R/itb5IsZvxxWCv
/WbryWhvOG7FOn0EYnilTlQMFLy1QhWtI+5rmntR9LZUOlDBP+FhFeMOgICUP9t/Yt6vK6v/gp9n
yWmlqRYYr3g1OEDp1DwCTyzRmSALNHseyMkAcHu5hH5cqhiCVR2WKYBIKyWjjo9uvjIVR8oUHFMg
eUuy2hcWQe/+/GRBg0U15wB3rZggVEWkdZbo98NEUaCqQldFx3oHR6JnPDMXSM+ldYjtQesUOU7i
JMIPJkZNb6rdQG4ypJw9PLIL0XiRFL3UyuDkRg738Fcj8oq6YinWpaZFBvjSUloDY1P7FYXo3ds8
cYwipMu1aoDF3QY7I/FLJgHNhlnnLmRiZZs0yU26ikTTY638ZotZcl/yqjLDo71aCAUA8n7xPTGz
DilNhNALFTWNXmeE/FCHYktHn4mop3NrYe1nz1qUJAJpo8f4hCeKj+qB29OG0IroNtQMBirJpBcy
J/qDSiQ7gRTJXiZ8SkfaPSRVjxcMD9zf1ogPd3h4A5lyGK3UT3k63JISxwE+ivMvZLJ7h7ZbQtcE
UATW6roDXbBUbMYhJXZ5RGXhjIlVTHMQVufliMlvG1Lw2Rpi8ZUBoFvCywoHPljLHj86HFtNB5xg
c/Z/mQ8SXN3muIg63nkqkruWTgWMKqpvvnQcRwuXtpjKEAjYG7as/4KFFkrMR0iP8fqXWarAZLQ+
3QVcpooqFatuvDm5oFLGOtAqYjobHjd91KejD6jg8T+W1oTkNmAtPzwm/CgKaDMv1JIEz1LTzBhU
ELCM7YeiaxkCzVQ1QnZbPbbJ16zOh/c5G+HWa0Cg8ncWnxi/zMs9VXjMTsZga5+y4HeQSXd3jwyd
SqBqKpHkyIfavnx370xCiRq+Zszvod6wkPc2typPUWU2kxVjCYARqzB80Gi2QfDVa64BseI1U2tY
9gxXT2w3m4R83KCuxisQa7IwzODVEIEvAZEBjVGXDP7mqwDPoWuZkzb9WDTSUMkeGrPjW6eIJe+G
DhG97+JFtS9sNZ0HtKtEeIr4zPHOtlIwwohzOKeqUCS8YACWptfGXbWgy3joE+OyqH5kbrxkjfuI
ejN+pPSI1h4/zHayB+8tY0YII3t2F1Bn7pMirEONBAubL8hBGIG6HvKd8dBJqLiq1FmuEXhP7wjs
ShbKaCORmJ5n2RQOUvsPEuqQRHWdWLw1G5B1n3i8w1MowkHNQnebiEYhdFySYbzUU2a0BMTEZjjU
9GYieB8cX9Ki6dfvwnwwc14+PlY2kvzy3YorG9ArCxffSU8DwxPeE3PzpGd/ZjFtQIxB+BXcp9uu
HH6lH6cv2Wj2SbRsmkvUXDGDJ9qMk2Ad8whAXioG2D7UMYVmARmadBw673H/wV0UAMZd4n5Aqtsd
LVP2PjzLt+1uGCZm/A04JBBF1VSYCOWXXlYtq2qkwCP7GHF+nW4r8Gm6WqcMpd5ZS8oGtiY/xiD3
BVlDC/XGPmcrdhPz3AOo0PO5IgwoSWh0btpz6nJkyv9SEH/Ofr8g8Wxhs1y4O4IWmrNCmNOQ5WOT
NZecZGaZKfVz38JopmfRQEMAGCTy5OArPyE1JceLg80iEtbf5N6MkjeArw2E1ZTDOOV447Ar8zvE
nP6mXwVAZRVLorOAiX95z8OWMmmxI/3Yicub3N3Dwd6uXqpyoZX4HxHOGO5wpuBWiKVQYmEJZbKe
iR/UOU1AszGjLprttMdu7G7PZm2cQpkdXZ6SfJKyuk6fGtfBVfdK/72yzg9iKEpkRQq/NoAlMgHh
kT35LeZ4pPC8ak5g6rcLQK4bNXIDj/ApKqIqwqSjvtn/7p8ygDp12NbdZRuURvIG+IjG1ln/tP8L
WKmpydb1c7lxeAUEMGzIj1Npl3pGr1Wt8BOkxhm4hn7NKcBsVyO8amFo+qDreJ4Xgr/WyIlzelRr
Yjz11bHtyN3tABq4tk2gBcVwZjWKUMqg+Lnm+b/SGUTrUna4sMODP9lM1At3gp32IB5yUPfFZCHf
pXCoOgeWigFFp71feGukIWryAmSF3hl/JpFuWF3SB+AKERYitC8GzatRTXa1ac/qfG73W29O3KpD
FJ/pixQ9RjwLchlacGtOsxEV8HSfJpvJHgEch7JLEAlhWNPiNVWEfDiuC27TvoJs8b2r8kLJMLwR
UCWrH7MmZ7uziouIg6SbnHx63SrfKee+jTUlxNCjemj6CAMyIu+d1R8X+R9d8Zui7GW/RZY/QMbE
XjLcEpDEkiJt981rITsYEeFEyHMguM6Ju6nIHid8SzRuEWriZRmEIJTAlNIiNLwMJugzTB3crOQl
8IBfaMRzjfCoau+PZND8cAA4s7vNHF4D0OokRek2glXyoRMl1VJLVGmx8Bu37nyNdvu1AQFjSYLt
etkuXnpS0VKHm9ZgA4jv6FmgSt2eUmSa6qrnvPMC3oNUSWtDdl2AajaxIAbvwKZgY/beH1iIkNEv
TjmzzCSq8SktUmBG72Tjfxpu7Va8SzV7CEVoXthUQ2f2wog4l1z5+1Xj+lXv4PQkEAl2xwkSxJln
lEG391BLOkFz8ytRyunEeaf0qbRxQqkLIFbClTxHPYYVF5vUJ66KAE7CRsABWa9FDyp8XMtk5zAl
bNo9Ns/XQjmFKd4k92EtfeH+ZT9RuldWeM+9sVWxeKVSntXZAA6ppscYjsGfRgSp6dGksLyHzi/s
Bwy7i1P0DdbURQM8g+Bp9+W8ADwkj/Tw+QQUXogp7ZwL2NAJyvAOr/16eTgF5Qun4OykMrEfpcJn
4WkkWtbKyL46Afr7gObVr5ukGM5mMGxU8HmBHqGBjJmPyhjCCeTeHkbQxsZZKJUo2WowikWK8shF
CTK2xNy7A3kK54cBBGi8n1gBd/qRP5i/ISxSLP/FIC+/MtUe5aSGnI4+AeAqyw2/4eLsiNpj+tkO
Ogn1Ld4k9ivVN7f+7/htAQEDEDZBODHL8IwVVYvhNTsfsKPs8RpJMMUNun5AN+FM4xOC0OZy7IrD
bUBZLmUkm1x/CggFdLCedKFp1P7Nv/B3wrItPNaJ50/z7IRomLk8I8QSC9zJaLyI9PeAAHlZ3r/r
SZ6scDe1XGNUQQJVnoXM8ivLdua9OY19yh3fZhePtbKbxtsKdShqdFf1gXRJNrQh4L3GTOaJNOTp
DfowShHtYS5OS0FuDNItNDPlDrjb4yaBRNf9k1fUQSgjjTLtpaoEqkuWmAdTZU75T0gmQKeEdRmQ
d/REs26i04OWljHjoXBbg3gVUT+pAS/51KWVMIt6TKU3/oK5N2XAxM0GL9x5sHcle4+Totk0f1UM
pJSDJNAxBvl09xwAvNDkI3rv1If8srNnYf8woVDiL/GAl6aVBgk2Olh5A4fq7NvGkTnRjwBNoR67
76+HULUBRo7ZQOtL31pyt1W6DbOaRUwPMyLEfjjOh/f/4aP2Z0D5xLUz9h1nL4bk9tLuKvhWN2eC
v/VoOzh9knxV4XPU9k6FbNki+i5AoEoRUzkmy857Bo4gHOLS7/OQbbcOVu+42q2PJJSBPt8KF0Og
8O2QpP2/q6e7A7D2tzI/deUI8EwfzhAv5v4cYEK54AqR2yfNmaz54RNgcisOpXnoPzSAmi5Jiy4w
seUpvvUtUt3cF5xBmjd4H1njGi39sQyhQ5/xvuBY2HJMWMXIJTLYgpvKYSqMHJwhi/AxnP9Z3QLR
IliidA7EvSzogBR039dzo8cF0ksFtfGYV+3P/S1fvjP1mkOzPu3XR7pWZIup+YYQq7iK4SmuYhlL
EnmOJxtLHjEWIJ2IVg1C+5bkUVOfkHbXg4BEnClv4C/tHNZWJt6h+hsD/WWW+wNSHvfujeIyxJ1H
aGSCNa6hGHhrwyPdCEMym6iGLtMfytUCK4RcpDVx4uBJFjWnYl/OQ4a/2+zNbyv+pcXIkWLRe8oO
06fRGbxHxbcMiBKDtwfs3ftrHM2ao2hMCrnDOdnWpjoKq9BPYMlreZX8FnxhtVwaIqkJkQvm3WSG
a8OKtxnDF76zPPrInP3CfNyM29okOqqlHKpUaEFkzRlaInutn/9EbtmcunIPVSHv2wrPgK9EbXyq
vDFW4nPn2G8q0NKET+jEWcTOfZhlcSR3MVqAAc8Eyn315NtKWhy6C8cdBOi1PNJruNo/R6+crqw0
U2R5NmesHfliHs7RN/ixyEvnevb2pZvwg01GfKMB9salRlBuPM1gnvkXNXXUEG1N3QoyLDgQW9Uy
qFwWVVNwl4tSF1bm4asF/r3tMU9AAYIos9ioMRHi4aSxnBOUm+vznfIp+f972/MxZenx6R8J+S5t
jN3icf8ZUTPX+zVK+QvPTZT1Z4ykXOCk3VjtQyHx/3ba/vOuftcVJl7asj57uzOKZ+y6RLoGADkq
PZsPM9L0XluYwd6zYAWZDz+LHeZgo5+aTPuDQ0OrsZjMV9LfjsEnoHLQe1NFOf8jSq/RAthRjbEL
vlvJZOxaTM0B812GC1dvy70EC3ANFCa1p1i9qZZbsUl2DG2SF+Q0P8s9PU+Yg6TKXx+iBSFoiVc1
7aO1HcaJlBuWPsN4UfqiIxXfmss3KXOd1Ev+U+VxTIx0+SAV7QsFrNz1xcXgK3r/YYffvSTfwhbg
HiBD7FlLBC1/HndfD0yqpu40/OMyjCclh1KjlssFnip/U0AcO4aYcWgMr4yr9p/LXO2/PyaC6s4K
246JXCxMfl06I48Pj6ylR4AfEc6ypfhm2Wb5gu1Dyp/5yNJjWSA4hDog/vJdelIo0Wu0vGLLuwLs
HbXG4yph/T4B6KoB8muzBPRiqWHxixRXcsRJTgeJYjWyBCsZrPrl4LAWoYbVDVGvIK1ZnnxM3bYk
CgznsbVv8CeANMXSCperCepOFVg39YQ3gwIc+V3fdyhyzeVKqqyAXNwANyMuHPv8sIUKXGzZUN7Q
v55m9YKKN/lMd/CixzHkc8NBSjIsdk3YGcSPuZGMU6Vh0+6c5RSgjNeXr/Um/3oIpHHIePt6oLys
Z0+cVcM3BdNznioVMDL8uN2UNNCgL+KTMeVk+be4GSmos3o+c+gonMuxHwGLDxQQk6/eUhUVCgVv
JNepm1O87ulOjRPtSJpmTVOlxCj0FU5c5eb31dWiNUqbldnxjj95VywbKMb1ixDVFOtl+Jx0ciU6
QGO0OogJ9oGfSw7snkftcNPGciuyqkzZXzqjPWhVf/7exsUFK+sTCse/lV2qEOgpLkrZjFA8rFY7
pJ0p0KWR5f5EGq5KorIAuRhce1hTp4bHOTSwyYunl5fOArBLMZ+UEv4L/LJ8aouAZvyC2zXG0FMq
+wrWT2HG/AFuVLR6PzyW01kqKAIenBFqjgq27me0C0CoX93Yh8ZD6IE1fhdkfzPiUuw1DHnNpqEg
dospkG+6eYM/rqt/40hO0028egQ76/QNdv6qAl9FTTRTTArX1mHhm6sROHC4sJLZ0e3+wbqsLYe+
R2YY5uAcdBqJ9jEXpR0XJe7GNrUTzhWr0LCFJV2pfxgKxI1a/iwcbkplDaNO42tpp7RhexYW4wAV
mw5nVhOMKgK521XK5gLopBacJ8kt+wKKAIBPx0gkoUF2Xvczn7yRXrOOAM+PA6O7VBdPrSxJjklS
cTMbv4trZ9YCFsDEKa1NZ9JUpqVHOt4V6pTOEgJG/K9SyOBkvqOlYkwSSt3Phfjn7SAjrGZkswcl
0enWzIcPl1PUWmnesZZ7DZHJdDDGbgWPE5pw5DdypeUq0rC0RgTtd8CWE2QqLU8sK2CHLH0/sasK
riMsChZfTuYlZ/NxfNIL/OvK9RFlkBw7UZ/Ti7HWHnhDGKNAGMVkv+SAq3xlbV7CLVNIvugAVrLj
uFEOAIi3/n3xmhku197aprimHrJeOuwravlUi7x1jbNDgV8O3W7X33pMUM1DPvI2SwSYdEK/j1jb
bUWeZc77HLcw/AlV1UEe1wTD37N85KyT+rtCNcx/nh+VlyeXfY20bDM8kwbknIWO7OrbavBb+t4/
jq0rc7Z+MgNxDelbKOsyyuFfhdfXprg3GyU7VD7nDhvsdZSP/dgwvjOSnG9bRa/GXNOWyLjXjWgS
Pedybov+gsNkkLxSXezxlzfpPaijgzax7NqRcDXUBbTXmHoXVnRbi+y+E6rUVA4W2+x9pMMBSobP
AEsB5+HTgvOkNwEIWiuuMBDSHmKtQwiccjeCwG3nyrgWIqWcG+DG7rdLD/m4UoQWzRHHsGG3bhaM
mFGrIo528l/2zy9fk+PRsEspBn9eeEbzOWv9ig5GOXcMOLeqLM/Kat7Xsg7FwI84ZjSfDNuL25eB
RIpCdlJpeGdiOjFNFG9yojRX4eq3h88zaX28sRLQmByD3UPgLwE6dpvCcqX2Fdtxjo2/eJmWpzt4
4OXvVc2sfQ3awRozhcCL6Ixfc78SyBCCcDiNbRmZr2kHvf8Tms5bdyaxT7+cw7pjjkW1BRyqSy/Z
DInqnjnOkjTmP55NJ8yUE7fh3Ef7Xejws9fTIfKo34G4WYkqkleeLCSJ5LDwhXVrX0ZI6pIphBCf
ya0gMoSXcJCfgm3R07tyLDG2yfrrwvvFw7XyvUDZfean4tkK/DnKOci3ubcgvTku5wRyVH36RCi2
/qr/LKF0qHIYg76szxAcMBBrxKbAMuu1E/PEt0PgiQsYrTsInsWOQ6BkBru3FzbPV54m2jwMQse/
O/42zoPz19Xagk54mH1irmDCmPrvOrchD6RH4Jgt1iH9of+t1dtFl9x16Ib5W55ySo26X627QjHz
yWSVi+lQcQK/X3Z9L2qgv45VLr7OCn4nCsmGL9M/R0gFZcyod5Zx2mEV4MdjLJJ82I827eapPP/O
S0DrlrXkKKse7N1LrF0oQPODUbqCq5otDfp1vlyO/QkFjBRR9tqNHjJT8sIYx1IG66jkQK/RhY1u
j7w4TgFASabJRvBwwI/5iAyc2koBr6KckhZ7OUdasskAIWgUUr4DhqBbq4evRweAhHVVXDbLo7n6
Pmb4XrBLitPcLX230wlr8gXbBNPOpPT3Ud2zSyLFIKC5tGjT79AGmIpfqnjsgBNEiLCrLjvNklc+
qfUrE4zJ0khjRzr1kVnGjoBC/jqDcLl4V5yx+FO10hsshujdvnxJRBogQCvwybZlEbjDjmazHuz/
v4mN+W82KL+f/lRYXFJHc5IDxFQzVGhRsjmRiMdBRL+6SnacTIJ3/gUqxu17hPHqxB9kH/R4rxRo
924+PvEtLofz1hQZ5lZTklva/tExBkXUsFpjfTElCK+zskttzhPoPkUnQDcMSDXVeHQDx03GXPal
E8QMZzzS59Ej2vYEHI0yOra8eGzmGHq2tOiQYWvsHEpVmdoP1ELpsB/Mn+QxZ5St+V/CWbIEjSRN
bi3LgpynSwSc8PtuR0pNCyzA9gxllslN52feZJKR9aXADMBKLVIq6oAmMhJmXRuENPnOP4L1kTB0
+/7hco31aoZx5Xz2FRYrX5SqsvjPjDIwhsDVYoZvNIaN7vYyyRm8kje3ehPmfKgseGBx862zpvt9
BlblvRsCRSoMvKJv0C1tNYqMiSZYj7R9LuEx3xCKmeDv/YfBM20DQT1h05ot3fFdrFUivBv8GvnW
HSlq9CTrnErOLn51140xfjmqZiTcCL2Hfxs0HXFDzdmqgzZNVTeuJtxRUEBZOvx8BLtNHJqNINQH
sXOLvx7Mc3XBnJmR5Xtug18YAFSuNBJEqiooy7NLwDgL70/8HaQXeIJH0TLDr9aUqQLSeudO3wo9
GINngGxPEv7JPucjhkf+hpf7bX68Ebb+omVu2j+ash2ULjx9EFzH0SPh8YE6wbnc/kFwCZoxccDj
VEx82tPKgmZU5hkLEV8rS8eca3+QGw8BR/pmRZBoVuNwj5N72aIcvmqUYffD4VQ6E3+QEGeIB+wB
ynk9vA9WUExcAcR0Lm+OAAsDrwRpmZD83EXJPbllGe48BB5fVzziP78RINoZCfgBPltdHESgltI4
vTKLI30rnpyF0bLnO4xczINdy+JVd9P1ozOuRNYAUL9RZNX+SJ9JYrajMboKKK7d/SnhRkjV0rXg
uubO3UYSEIxPC5ZImki/19ALb2t5TkL3lC0fmihXH6GYaIHhhNeuOoXQO6tQCmVNWhC307ZZTXR9
7rYlYMd8djcIQC4W92VmKGc9c4DcK/RDusTKXtQjYHqwnEuaUGuUCdY9ED7A71215OsjNGxQ228G
jFcdcM0wqyr4GUcDOK8WrYbvrGqBZZwosgZJEtyKk7FYrb6zvdqHN0y5YPDtRgr/8CVfn6xGkOvg
k6TaPQYl4JBP2fOgF18J2y9RPDTR1DZj7xwAeGv3SjuKffYjV3hDwfQQktFuk60X3ewzoMN2x7vW
LdEQYN7MvHpG3745q8iEm1s9Zpj9AztiEC1qJPs3aftpDNNPipuC1hOkMs2fFrkiZin+03uxQYlh
OvgVFRCntkLKAibVQ2Tntyr9qcs6+zAjlnknSGkh5/0Iy15GhiRofwJhnKiaMbW6ZW5JRMoVRaot
fn0GBmSxOL10K13MIdq4Ny1WFHRPSMRgfZFqnmT35kJhCWflJV/lXVCShVcqO+Ge65Srl6j25Wqw
pBwbnS/g7pcSFVO2NaUYgp6zKblyGyCXZ51Hqcmv0cHQRBmEBDByH7S0wkpMk1vZFQLihl0gp1Kg
uKTZI0K5GFA+st/LJHbUn7Cso6tg64h1D3uhOqj4FdWPwDDZuO2hEcxSg1JLlhDnRUjRbGN405Jv
oPMU+MZgYrBXglKpbgAPQ/bC2AJOqCn8LCYhXJ2aBr4W1zrGCSfvSJpFFCztiVQjX5dhBccdy6Sm
ySFKHeOrUwMQiTtPNd5caxd3mKeMXKtGXifcZTvJ9hv0NuRr8QatcebprlIUUxt0dbXTx8yrTvRW
ALCKibrNV+BPIqtIv6AbUCx1jirvteBiYQ5K6kq6j2SK5RrfsEYorN0clIwNl9mBi6uejTEaRTvh
+4pFD4olrH5D7hZfuj0MUJ/2MMSWFOK+1pdUlkuUssGXBGX6S5KM4yjPoeqWwVePqinLIdvdyjsE
D0UAotFGjIZfZaE0de4BP1k91/v3cdwLMDoy8XmQ80fQqUPFIEGaB+yYeudxNo93VAD9SdUcMpNg
/if1cSjlXx0nsrKa4knDN+zxc51i/Gi0rtm+MwgoQplQyd2+WuOCp3BhdkJerQf8zQoFo8CDS7+K
YA2BUrW/fJxaQphmk/kS+0GbenbTtMm9eR8+eVzJJ4qyOgSryzkBXH/ZUpp8fjmuGrmrXoEJRREF
P7ZbmFzJBiPgBn040r0vIxOO1dbWbZxbmcdow/fhRIs8WN1u46aPh9z5zbQZhQEwDBp8JU11kuVN
QHvGCqDa8TA8AT8gByF3j0UVI1Eq7DNjJrTQMlpe966u92RkriRfXnbmLAvDdTeYmt2lm2Gjl1Rt
140NzzfyquW1akUJYDPhVrRyB9yxgJPhpQjBI5hd0AzfBO4y8IXVEvmHqmcPRgEsJhAEWHyqIUFz
fT6E1iITk9V1VBcrhwHRFLQM75v4dwiG9qFQeVqzuw6naU2L73XWvMcCDEcf1bEmblV1fVHevRGM
fmBWpkLMT45C+OBO+MhHbluBuWOVuRtJ2mHXghyK2xQfnn4GstkWlt55LnNuE4Wa2n/1ApzmoFci
JGEjRpw/sMvql0zvLSbEKVyDyWGT63BOYE9Aad0ReAgO74/UImUGTZ85yGKoYW91h+5UHNoydYqB
fuA8iBBK6hVXq+xCIs9sGyNtSStCb4Rp53k6UhgaHpF2imjgPiOKIlFV9/G6N89UDKVlUToVWDSG
YIpfmoqlEzpNus69p/NjWcmej7wbxso072bg4Zpg8YzktToOg9jiBOb8JKfZbj2dO89pqw/jftZR
Tup2jiAIo4JIA5J01Gkce4WLz17BrUdrbTEUQqFTqEmL4dhzwsfzZmuyQ0qjcK+T9zS+1BoPTF+T
eT3y/CgiBiygQjB34qVHb5AzDKifyEHdp3RanQq8fywxigVHOwnXhOvRZbKFisbo3wW6sAB/xXKW
dKxFg31Va0CzB8Qae3XoBt3oB6Hr34mqB0Ht+IPZqZitKje5pZr0F4JQDOyYfeUhVLFqBPREU5au
A0oBAb5BPRnHEdXW2T3eVJRPvL1qcPIMyyFg9fhi19q6U78+qPTDMtcmxamjld6Nu3/OzZBPb/bw
1kfD1GMJSAZea9xPuLmE00yPBglskXv0wc6ZttReBVKvfmsoyUkmVA/oC/mAK8I5QIJ5eX+XNfv5
COWuoHhSQXUSFNZLxgAd/cH2sALVMlJ7DQF6GfSERSzNFtsbOfOh7kMbP846nqYBk4ABzibGCeGU
0iouq41a0k750x/984lROTPlUCgRfpjxzte74Iw5F7Aye67imQZuysyjmtAfWk5K5kdzIFmUImY1
UQDGTVtS0gTr2zojxi1RcWlitfIiajvoc93/M10d+5/5LZ7VkskgxkttQE4nYY6lg3L+HhBDaFkH
pZqoX4ZlXKQ3j0OvsklDn4Eqavs2+AAMn2jtF828tlQJPm6ERgBd03xSoA8HzJTr/yjzni55fWyW
xYgp372PqVP9Eoz8loGOQske3ZBYRt+Cu4uZMwOSl1LyyZ9lHcVCDf9ryFWUBgELmG+LIim1RUSx
Etn4p0Ms7uwGswsVmMJx9sZOjCAqKzEbJm/RIcyosuOkNcn+BL9CWvS34zNB0qnZsYkpk1Ovv5Yl
MOYshJGX+II+Ae6jVA4O4NCJYletaPaCASobQCqE5eOWItRBMck4Ppp4L2mwXzWyt4NcfyeBna3u
9dWTG2VkZtTHyYJDMXOlxlIvBcDRAl5r0lP3RcxT9+Kp+L0U7gSA3GSBF9xHUYfean7j6wvKOHLx
nk2g5JA9oQQ5TPwI/xINqqLm2rP5RoiksJf2SugjHDPbiWlZM0j++nXRpmmZOxXu8ENYOoJR9kdk
WXjNNn+F/nMmPlyUOBKzc2a0PF53W1mrhpntfPUT7xcdcc8OpwJRK32H8S85kEZFYY/VtSWUqCQm
9pbQmagifTey0LL46v5M5faq7/A0dv/ZaOVPfDW1NGp6TomoSaHq5BRop/U0OQ8DBYFfI5L1uGYu
2I2aQrAmdAnShUs1f7QTOWqnyKmNHCYj2zqUBjxMDrPa2d5Oa8ac8tGXEmwiK1bbCSEJHVoAyuWA
OVASXh/tDtT2rAEW2RSTmgedPDppooWi7W0BB3xjzQgz5tZ2kQpDB5LL+bZ8m3qU/IRnQKXCjw1y
oQjk4ZoYJM5dUdMEhXaY/uGQhB50m2Y4vGICCMdlZ1jjRE29XgfviShgZ0ii23dP0+UmiTYkSdmW
+csObdxfbSVW+ZcVbdqmJKMRqAhxfbweoc1W75cGOXZzZO3PZcgiQvs8863PNinu4tXa+FHIl+sX
c8ut/kl4bZUCUpjT2aim2oVzrib9RYthSefZFRPncHoRxsakaxdQzI35jTiDrO1yqB9dnMR26f1E
7R46fLT+IU7gVuQebSsnm15h7CBE7GitTf7a2Wd4lfwFF96D2gxlJIS+K8EQGt0zAMsBe586A5FO
kr/oVhZB19yWgnwuvHS8E+VuXidoV+ged7CGaD8dB0BR/yfGTehMCrql2KqgyD/DDF0GOqTcsEG/
3wiO4j86SIAYVQC6D0Q9u56s8MNK4nUaM0qFRl8G6bP2Yf84gg0CQHtxjJmrPS5yJqEQXSLK/+RU
Y46+0Y9XsORLoghM3ZDnLkL7q0zWzLvOImM9LOuhVcHx+fl22Tw95Do3N1qJxFc3pY1HhfpbhkMv
HwgxMX3RSkbmTfMjHcDzFbVu5cymnUSfxpxINXTnBiErIXfGENwB235wgIfn7JQQy8u981Rg5f6w
SUeOpCtuq8QtaQ/B1x+ZN/pmninpCK+PZFIkZUgjoBfMvn3/EmdWIetcVU+CAayqsYnfeengCwkb
Q0yoPTgv9IpPPJpZDyhW1MhLIj2dcCut8LtKcoVoCfG1ADkvt6GLJu61HrXhoSv8EIHy0NXwfDDT
FlCHFTEh8jtZHx/TwyU/iMRauLZRxuHQvleSlfus6h/i7aPl7PsadjvTIVv7xCN6aXZAxTVDg8NJ
wHmTMNrf89yySt2vwR+bBZixL+lAp3EctrCMszwwGamZdvUahpzt2uWrqtPm75zRSPk+hbUOPZbl
EopqNiSoOybEsm0KyTe/xhsxOVZPN+ftFIhn114LTsjUZYDFoUBxRhFqLFjL26afoFK65iRUBE9n
Wgi7+iEzH7Ar8vn5X+MaoncF18Y67sk4E+NsY0tKwkHsJCIC7q8oDWrIpI+mpUGmhc6HL4gq+3A4
wMlTA1PtdDj9rhB2Dx5qHew/oU54BNIhOmEn9XU6xKuLahA+8aL4rpcWEKMj7eQUu9g27fV074Dv
9FlDO99z2gCMZK0XW1U4JQbeSdXDzSTE83EsA0jjLodkelx045vujrhcbfq3FLkzU0gRlLE7HGcK
n2XOwPkRvFRc/TWrlul15CB1NT64F7MDbhk+MytHzXxSZRnqaS6w1/kF4Pfd9ZDXmYl/2dzJBb6j
3nCh8B2WQIgD1SH/mYB0AcdotsVj+hsU8Gk9vMEDa4zAuoR+WWzf4xMALJRy6g8+jeDrlHWTV44v
/wi0RE5qrVy8LXsG9qWficyY2UFiZ74tsevA3g+71UIu3THm28X4yQcxW8I0J8YABxPebHs3MSx4
qsiSeT6NjznbFHy8sD9FJxx+tCk3b6DfXKYVb9JfOB+DFKH4HkDeN3A7pCYuNef0pJRJwa8aNbp8
Smi6ozWoRiuCiuxcfKxbcGMIfU2LLeooVkWZoyQ7NpIlzzscehfQwqqMuo01VnFRUugoja8UiWrM
LS97WERraUvgXYptaAaVGGPKdZ9Bqt0hSdjnPX9jnz/PpS1MMoidENaESTmaKceXLnj91YtqF3s6
xyEoemHoaKqEkgqKbKLTL2+zndcMaHiCnpJOFthU5vjbOJ9APAzE6SVQxvzyBvM6zahE2iTr2dVs
SDet7CPp9zM45/bYA8Th0NVcYMAGeAlf3KVf/a3xH/EIbpFSaZXY04QQlCmrHmAeA+AvimLBcFFR
2HdgSEcUk9x8g81XyUwQDPGAb2ydteHRwCM9oBidlm/oRgykZesT73limi5kwrMX22EuvIJ66D0b
X9OcuUCA1yE3UHZoIbPA30IUF7fx121l1eRCmTuh
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16560)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztlHgsA7XTu3se9+qgRV127brGn1J+SpZIMueDb+AV872JX
nOXB120GyVLNbjkhWTWXGQdsLOXfaXs2I36xZVRiwzpAgBzfQJrI9hG2kq7bh9WznJ3xEF5DLexY
Cq15Vdb5gm0qDaFFZVGzlV0qAsnNmU5TwLZdRsYlrsSd1i9jUQlzfmNsUENvXGN3CDlY8CFK3jai
INNNriIElfSpAetTkn9VmfppFFOF7wWkbrMeWuJ7l/thC50PzIkDIzK4x9CtfhJd3F2cp+VAeBKF
LrxUYaG5u5XXGRyoHikRUGoKOXXmqvmZIKvGnqo9OmemjsqjILGrPxP+3Dy+cG+LmqgRYTxy9X3z
oMfdSSQ6KvJIZvqKnopohLc6y0/oMFyP21GDeRYafr53M5KZ/f/dLwptOby/mIDvt7SkwnKGfvFl
EpHTWq8Qukwr6iDxqQsNxGo493Q+4LG/yKuSE0SND6bwyarofUfxPeW4laRQMKn7H0Tq/eaUvdP7
vXl1nkBrtRL2reVVADRjcpDm+3z/jYigRFz9ttrA1C+77PRjiowP1YG1fdzffqSmOJ2j2mFWYikv
ToyM9T8m18egCp2ghJoN4eI/VKWlDfluDP8ZTsWcngrJsn3e/GAOL8PDe92FDeVUKpkl+gr4V7Rp
2aPnAyyzEcBeVlaEkmCZITU7qdXWBM5BIqVU+5e2tVie09XfrzH5MIHwUfVaSuy2u55zP0BOF7Gu
CUEPlLKnR9X1WrHVcPnd6fkPfFulzaTs2HuDJi/KrTvbj7wCFie6P4/WolNX6kPWjcz9aQ+wnwhS
Cl7c1ftfyzJMNbweg5RPfaq3a88McLpzC6etEqO31+rgbz/dfhINoJkCiNixX7xIp4n8lci7GXoM
doKmP5XLBXmP/Ef1HlFhsKHBbwP+AsT/HJKsRbeMXUWPRtcZnkpB4dP4RxWecqcBPC+ggs2Wg9XD
flCvKjr6I9RAgAyAJYDKpapS2KNmOBVR6fSfSEbVOTjDKBU6mPvbIW0B1GrxujCVwXhYhzfa2n7s
pSvvjqm7xICaDI8wL4+o4znzeARXPT/oyN++/EZb2EHhIwgPpY5/j+VTdImaOHA9M1rXQQLS5YiQ
d8fE3ICl0Dc9YPx7Gi23TU1UqiV1wx1HdnYhTuzoxdEq6NpLA258Wh+rwSu8vP7hWDb4IQs7YCmU
6c1ehdkx/jvYYfcnI/kqhIpv07AlgCablcW/IVHSudlBYFvHKGNJQlgPw9VF3ckGkh8Nga9O9I9d
WGpkXkOB7qPMCwxtST5z9waEGTMzhngUhfVQG3HBNTQ2/Wat/S/5ryngqBFCJaIgUfrzw8VYPRpx
Ma8yghJP9QRD0sXR0VB21eJw+4iLEg1o1b5xf9NUkYGOZOEZKU4Stu4K+cfuS7iTeocaFB1jsdNn
ntMoV0FAqRuj1lOxDG+YJLiVc5qi1sBf6RQL2iPcSOOeEQ+PD/uFwCj6180hC84peYYWAyHN1Frg
05/zwXh2E591TYe4C0h0dT+Aos4yWciHzN20jWOxXMzIS3G1qwF0EGqAijrnXGLcGocwxkZPDg7O
+ZIkcpsjjhwsvUCRAmpdYb12MfN1aomq3wUg8VUEjLXBfDpGSJm6LmRFOyE95KmkhVn9RTJI7dRC
jwjcf+RbuNT2kw6BbtbyviR0PCqcqqTHTP/U7tvsE06ymyUlA0+8IJ3mEXtUVLHrlnKrg8hrwXl2
4THwUppB9JDYFgpLPAXCkF4P+9MlHt8xmiKzjjY/jg4X5Mak8s5L1GLzrK731k64QPGLnV7Y58fc
JJVHuV7cVknlClqd9DJbTGS2lpfnm3E5Xx2a9tbuW2oKicS7VLIMnVFCOqwczmsysYtdtNgGlee5
1fK25W2QAG1uuOeASXuQ2ZNt0bEInni+G7PBrvOi/pIjashgqTgNL3SHHmA/XFMZnHX6netOZm3e
BlfRhSx0HBjP/WZtK5NmOcyW9rMppg466DDbqoPfn9ht2ThmNdE55qlP9RBkGuq3LmORr9QPoP2r
Kez2IK03BRuNytY9tB9JWMXjpeNTFfev40Y2apCXKqghOHbvLqicXRe2RpvdFsDdFcAH3Zd2cOx1
is5sPhAMvaqwmdbkvhYB2IccISAzJCjDSLxf9u2Ohfbk1LkOVNmX/lsYcr4M5bchScDMMvbxps9A
/nKuGAdf59tzE0AtDeG/JB6q9/Xatq9vDckMhMnW79Nj2YM+eA4nboeZi2q2usxzOCsHZCPMfnmQ
JdiYT4tcLjLpV/MAsswTqI2YwYG7Wsr4TfTd62xl1K6gTKPFxD0Bxeh/7gMUL+s04w2ABMxYeOUS
soGkfyrtq/fWWpQisTLRSPV3UDe0a8xM5OL7koiF4kZg6J6vU2gRPDL6/9fq88Oi9w56f6BRRcy5
zn1CYRLMCbCuNo0bQ1ikRl2fwa6WE8OA23UlxdNZk2+rphNHNk/UloVCB5ZXiKdP89w0J0JyVcme
Cc0Eo26iADVldbzlUVXNikp8CU4tzrmC9jSh4NIpBU6d0qi+G69Y6KulyUxpENfSof5PXnrXrb0Q
89dsh1dr1Thsq5QZcNvSCknVagRzD5eUWy/u9tPEyziJvWGUJQOb/YSxz+I915Wlw3Gxem7EPsck
e1PONwATUS1zh0sOiUIChUN2ZysliabYb/tSsNGvzBtEp+DbZPlcoyqbJHSoP1TjXAnB/TDMobpY
yugtm5DdXSlGUrsKwBiBRcewN/Y7XznivnNsc3JPTo1vYK5Mc4DCRgFEZfIqde02lPpl2OUw54bh
699OiZk8Z8JHlBC/A3sqOSelp2MNG5GW1MrCAdQjpmlf7u1evUvOQyjx5tM4G0aaGiNS35xwXmvy
Z3hId27r4DbvS3CI56QsLSh4NsdzjHoirwkfFFUQco4kP6r6bBSb+qSdg5mYwvieiEwLTDYXGdFR
9H1KBQGXkHjNWieL8VYuheOudvT56+fW+kiYu45hauh62DQdKGeGikrGmLr6O7Cs5+vYXEzV1A+o
rsbHB+3w/DVKGDe6r51wO+1rKxqQ0Ly+zSKNFfswqm4qVO9OSIjiL8P+9WdX2WRpsnvOWOa9LUFo
NQi1p429r6FXqSXAxtJFZAgtNmAhrqBd28LyAHLvJsKdymxhpLsNGZqUP9VODIMT/jg9FeKzeDhN
K+mriXZRagg47TCbQ2xZG4/ay2CZfZ2sKH10qBP+sssi7JR0Ir2VywA0EPn9PnMhtTgQtvqypQKp
tC3vUX8ahzFNh3Rwo1+nu3wdy26gqFRexgdN/bJkXd15oB982kk1dlJgX/DPRLOnOtTMfIjnqRu7
2BJeaOK1r1bEPNmwXEsaqVzTfE4vFlLEBmqnmT4YWmW6Nicd9qmfnMC629+UyKOGD1E8xJcFqsai
KGe5AvZuNbA6toK3QaB3p/GBfA9yvQgi/U5HY2xKehgk1556cTgixJxIZpNI2uwglCpYejZIoyYw
6MJnv9EPF/8HnKQCdAU6BeocT+XCeiSTlDDbaeGtC2h/HJjGXOM6hrc7vAC/zpwnoyF7BrVFoaFr
gUbOuzQlFA7zzL7gukUB5wlipL4en88vw4fNqQVoEsXtOJt7+OwYxZGX2DVrbzXE/u+6qgVZrJE4
GQ7b/tFeHjN2MmA31MwbHpN90Bx3MkW/t/UnXttPwJLkHGqRWBEg+6k5qScLFuJU9yfxFL6Gl1Ts
wIRCystlJ0QiGF51P+e4bdezj3lGSLIsINtYaa972U88lqm3si79cpBX3PmtfG0LWfmvcwEQ5C3S
O8DvsGbXqhKhQI0hcp/q1GLivekWYvv0DUYQwl1D0pqHEU6HhXAmtkavBRzh+bBdmM4eq00j9/ey
KMDXJ/KGd1UHloG2GevD15YewMLbBrBiBbGCrKoG2MlVx4pS2l8Ed6uFi8sr8JvMm5BfOB4qMX3k
eLhMva3T55O4F6d1xJKytcNUWG3o/ioUCGqLOQbz5VEFJuO0yJNibwfl0L6Zq8nGoa1d7tAFKrf8
di+++XVql/0QR3Objt3pn44+I4/xFX0Fo/WAA4Gjx2qN2v+gBwp4PmFB8RFtRHZzYeho2dUEaoRS
iMRoCzeoLMqR3IpyV+4Ke+/YXueoKclTjREVWIZx+xOC2/8Mkzsn5exuL8xBytvXlZOlNThg1q/s
l+UTvKbilMmlpnfJWVQmVvY1ANEms1T7Fmi/iRqLt81K2quZBkn1yotrpJQoXWim5/1Xx+FbJtpc
Z5W0Lei80zbfWjkV6fJJh97rvbydPikIQMr9ggiVBXziaHiyz5znMYChR+noERf30uWQc3r6i969
l2DppBpsIOzfpUufIvlfQdviduKBkfPmBu7cwp8Z35r4PCO8d6/PVWhVy/1LrRH8cKz7XPVpdgs+
Po/s1l+Qq6117HHXkaG3erTJFyrL/cjeunpIxssncNIfUTlC0ZhoLm/orQiCQ1AUBv/z5KFlTyAo
VSYL6gRlt2mxsIMjxj76F72fc+8DYK+rp6lD4fpUG5VCVquHWtym4EXwat4n6LS25KP0AI3Pz6IV
tdpsgjz5Il7fHQ5P3NG3r4ovkDcCTh4LSwibzVal6hT0QgjhsTRTwtSyjwURaXESfpoyqtm08gS/
kHuni1hz1GYk9h00Z656w/xYEMFTzzA/nP4mvA8eqwo4IxrSOxhBURV5iLrnl7W5+6u/XyeGswma
UVjZu2CdWHnHs2DTL6MZA1dw8CcQJnRxDi0iJDV3Yw5QhBR3B6l+6opFKyHYGPchwT9kYF9WOnq+
sX6DCc7wxGppgxXmZQdKcHGDG99/GEBN3JzB1wVu9AE0+x2KFcTOKruRuetEFiZRugsWJk9CSMd/
Pqqy/1ZYooTmoIpm9FYrtCFnT9cZPY74f61YlKZkI7Exq+2450huOnNcq0DND0THHUpPYSkZ1Cqf
+l2kGlL1EFHj8yRGpSFjkx7gDHvCk1wtgb1ANbEPaBAOQZZx8hZGFPitdaELgSXqAwDmmmB04p0P
hCqQBvO7/RrfEphYFnJ+mjkm4HdtKH7uRiYv+QKjpCSofNUUiVufrzljkzStj8YWPOZx7uYZ3Pt9
6zoVxfaT0QlvhZBypPXB9AvcprFuQVdI0CbPafTMDyScVAKXK3gp/N2kou0/LjK1xxKRyNpMI5/J
s8ZUxEh3N6SaPUTMBtlbFt62nnGUR8BSPx6xNpjHft65N3D8MnyNwUoaxiF5jyZmli3Ye9euPJpk
tpr8tzkhm+mqOfWrnh6YC6wOo36VeNLL29tZhHPG+XzhbVqj1t1o6Lflpaef8P8e1nfLueBAXAos
hvJ+1/D8hFZis7N+I9kOsK/ts4QlDxXnwXUACHo6nS6+ediDinAvxlSRJVkBDnh9x2UupT/wmWpV
LOvKTfv4/9ccTpiF/6+Z4K7s16m58iG1nr5tayTHj9eq+xtq/XVgokWOI/AvlPHYa1M+GGLEPO4h
y0Ld4Ypo9LmENFgAY7KRnFxujX+grSfz+tJiiULvhK5xcL+H+pukbgvy7hF7sUZzC4mKlaaJgcja
dZXxPUVudBbevACchjTnaH838vqO7f6vn9N2WDAMjViYQcb2OjteHH0io1avNJO6LN0u5Z/BxGiJ
L6PDB3PPEi8+iFiIF6zYSU1kD1C6XQBPlzym0BztEtUx1Hvopmgz7F9Sg7qqTHkITBUH4aaMsXpR
qyrpvoTQYUKbQCZfpzL8DkJrw77hFAFw+Fa3ZCQ7PT2FWAkUzezubjPh40kzSjaKAFfkZbN2qm0U
Gr8IXg1PHQdLcesTh3D0uJbsj1GGdYHMlV6KNx+rNn5LpBafB4oB+0weRGlJwsm/lQmAiIK3GxBS
XR7FMD7djS36sPeCSDUIZAmb26Afq97fmRdVbftrJOiSwPiHkKp2jTS8cZK3LLO2Vuwx3RS6WJ0R
JsvHNqt1lkDqJdrFsDHWZHN3UH/jQJgkhCjAgvo/4bP1fgs3e+8Vww806JoJhsfT/89GDrydvY8A
fj2iFIprpUv1NoMDolCWe7AHLlaRFGsf5COLhW3qKDrSl5iAlYiUVbEYCERth1B68+Xx9aULxMe8
4GV8KTUJvI4s/mlTXrhrbkA8cQpPpg4ZHxIY1xrc47rdyP19k3MGsLLpSVxFY3i3J8Moq51yq1VG
IGp3+5ELe+7e3VWSgTu9ws1bLvjDItgxgbNEFG+yiv7cykZXb/3gSTi2bZOS8ywKS9qjwA8BHyHj
G0DULxEBtFuYIHFIh5Xk0jPSn9lbO7Xur07oGHzwXeBE9MoGBhnxN7Zhn+976V7BPpWuuSh8cfFE
Yr6DmL0pCduDPGNbDXTER1+leirJP9ZJp9j9DGkmcgI+NWueCs/cGj1Js2nt62xOyJEnGNmuKien
FojwXD4CFBPPrIozMwEFwv0eUV/lsvjQB8VrYEXwZVkHOLYGKyNntf+2mYgGPCIgliMaokIz7ELC
Kbh7Cu6yvOiPyh85SBt7XFf5IFzKkVRbFGayIF4BLb0hnIfZYXHfOU1RqGguCNRvXzDqmp3a3Yn3
2IN6Q3PgLKG7B/UBs6kVhIZJkNA1JeoiUCO/w3uKdR6tB3LDMP2aU1Pl4F8fGLovULMF2Qq3gG6o
tPQbnC9DMTc+fQDwWACPQoQwTXLAZzGcAvGtDgBNYQvCcnx0QIChoTDWszGFWZ2cQzXJvG/gw6wz
g8zGiEeDOrSGHNoitYW+k1lx7FrW8yRPfPdpz2vdKD6T9da0d3Gfy40tWeV3ZllxKAMEAhbJl1Y2
1vYJmWWU/nFz6JSA7Fq/IRYHe/9ANTyTOrAENui5qESRYZ1YYxOY7v1GH8c3kFqb1cflDhFdehHa
SPxCWJLMEmtoNRbICkuqMyYeXf6fE4oRp2GVvgJcXVyfbJvpcPLdJzNOWFxv4Ku5UhsELGBiTviq
OlPzz39UDDndJeyQdx2tSgkrVQ8cNV7iN2Zvvr8239TxwVEr1QCj+BwQ1l0HB4VCFyY1125db7s8
gc8lLMekkOpse62RVtMVHoaRcySsYqcb6FqPFxOPkkouDbgKnq2sK1neOh9LD+6LQ5r23ji/qyvW
HoiyQCwIr+8RfRRBu6dYdh3khE/ePDS2UnL+Xr9/zUMW/+QF/bs/saVJNs/Vj6oJxUlM/X/sbD8W
3GL/dQM/VahC/GkUbb2R47Bnq+8PdReb7cRecV3fE+ijFAKwt8ZWswVRSHbPSsdbwoCX7QWMSJCI
2dWJCTUtjAebp2jWLP3ZU9ZRkjpDemB51DOaVGz6NpjsBE+NQrxMQP0HZirpBKny3egZau/rijG3
rEVHGnb9FO7TIqMv81FsBJ+YW660fzOhVFBwT1emw0wNsDkFlBr52iNhovsUm3YNqGcrqjxB3S1Y
1g16hsPoEeOqAMzANwkTCT0/Xo8L852PVF4J99c9LQCSxqMLdndR7GcMMGFqCw/cgf8hgHZ4fC3F
8WmNzcdYZfuRJy0DXbQVHA1HJ/X9ejBmI95DeGlQqJcLKUYI1YL2H3wcey1XzY9uQgR+q1TVbI59
uyvUIcu+MHcqo9ejJRNuL/WnWv0bZ9ktwIQesdJTYX/KxkrzNZJRXp+x0A08D94pbcESeuoVbu7z
sm470JmLNx5n0IxyD5yfYQrGBA3ImSg29PMd7ghRArbCyHRupup8NqWHxvODbHby8dSpI1vT5JP6
AxGE/4qPMCSJtwaoVoJEmNXMN202RibkW6HJ88GFD0L0Saf4Il94KSAtPB8aU1RTZP3QJXQ1d6Dz
/fzYS12HtxvBjYcyclkndBWYaM2ZOxahUJe3uTG3DTKirg6QrQfY3NYFvXUrBV+4YHo1BF2/Q9oz
0z5wQe0Ad5Kc+s+mMResyrEV6GuYw0uDc1rUsTlx+0XpV4KL38sw9GPRQf4C8EWUmh2/tid5o31d
aSlkIL8hmDRqrI04xrF8yGkciS9NK8FlJYg+819vIchRu0ZxS0Xj1BY7SZG4swBUybfXh7HXOJLD
iT+IlvDn9GYGe8OooBBQZeb7p14Xlwyef70eJJBOnujKD9yRwbhUvaYM4EabGGQvr+qvOgBp0Zk8
SgxVfgK8tUKEBwE5di4+qLWEkFo7sazend8QDuUUOzGEovV3PRyPTPPdIQbtcNy92pb+2qlwWQH5
cOMo7jeJU3DdA9D7KYpT/F/lrXmJB0RWRUaFrTwKxoE35h8wcLcNQyawZjW6l6TUuDxHdhkGB/Fv
2aeaArVRU60iWJgFfVDlIZfrbxVIALYUTxBOBJOqCZEdPIA8Zq9lLx2ohLmGFkjLcriXnR1Dir4G
cTJXrAdhCAeqMhGDWJnOEZWoVMROcnkly4Kb2e0uJzFsf4egGRguI+vk11nXlVdR6ZlL0RxRER37
6j9TrMw12HYXNvHZ70qW+Vle6NKf+oBrY5Spz3lMw62kOfc+kfdjoPPMGDD9OLGGbC7nDEal8mzv
NJBrW8e5kqXJtv0RlH7j0l5MdcYQ6UVh+b6/z47d1pccps1RF0isRGpy8emcMp3eU0SwPISTO5Nj
Yy0IuMxqGsY/bsLN9sn63G3nSkjf1gmc/8rKucrxa/gJNCgSnluKD+EFGZOWFBeYVDbcrex8kn14
UHh0HjadbYJTf7JfQgqKAflO8YuNu2qW3R904gOd9FsbcHZsQA+RlJmTbBkrwjjAmwrHnTOpzp3M
5JIP87bN+qBJM51S4Kac0PoHJdnpnAL1xyMF/g15+0tG7CilYL7jQR664Hl4OYcBMtUc0EBbxK84
LTjy68XCy0HrfOPRTqb8+IjVMfo46X1babr6vNVRgxgfoD8oI+22NKABZdGxKYCDBe1emwMZgLwD
dGDARzEpWjsnn/RNc7bAQwts4E0t1MihNDxwP5Khs8APL+juIYTWrvPTQYMV9R/itb5IsZvxxWCv
/WbryWhvOG7FOn0EYnilTlQMFLy1QhWtI+5rmntR9LZUOlDBP+FhFeMOgICUP9t/Yt6vK6v/gp9n
yWmlqRYYr3g1OEDp1DwCTyzRmSALNHseyMkAcHu5hH5cqhiCVR2WKYBIKyWjjo9uvjIVR8oUHFMg
eUuy2hcWQe/+/GRBg0U15wB3rZggVEWkdZbo98NEUaCqQldFx3oHR6JnPDMXSM+ldYjtQesUOU7i
JMIPJkZNb6rdQG4ypJw9PLIL0XiRFL3UyuDkRg738Fcj8oq6YinWpaZFBvjSUloDY1P7FYXo3ds8
cYwipMu1aoDF3QY7I/FLJgHNhlnnLmRiZZs0yU26ikTTY638ZotZcl/yqjLDo71aCAUA8n7xPTGz
DilNhNALFTWNXmeE/FCHYktHn4mop3NrYe1nz1qUJAJpo8f4hCeKj+qB29OG0IroNtQMBirJpBcy
J/qDSiQ7gRTJXiZ8SkfaPSRVjxcMD9zf1ogPd3h4A5lyGK3UT3k63JISxwE+ivMvZLJ7h7ZbQtcE
UATW6roDXbBUbMYhJXZ5RGXhjIlVTHMQVufliMlvG1Lw2Rpi8ZUBoFvCywoHPljLHj86HFtNB5xg
c/Z/mQ8SXN3muIg63nkqkruWTgWMKqpvvnQcRwuXtpjKEAjYG7as/4KFFkrMR0iP8fqXWarAZLQ+
3QVcpooqFatuvDm5oFLGOtAqYjobHjd91KejD6jg8T+W1oTkNmAtPzwm/CgKaDMv1JIEz1LTzBhU
ELCM7YeiaxkCzVQ1QnZbPbbJ16zOh/c5G+HWa0Cg8ncWnxi/zMs9VXjMTsZga5+y4HeQSXd3jwyd
SqBqKpHkyIfavnx370xCiRq+Zszvod6wkPc2typPUWU2kxVjCYARqzB80Gi2QfDVa64BseI1U2tY
9gxXT2w3m4R83KCuxisQa7IwzODVEIEvAZEBjVGXDP7mqwDPoWuZkzb9WDTSUMkeGrPjW6eIJe+G
DhG97+JFtS9sNZ0HtKtEeIr4zPHOtlIwwohzOKeqUCS8YACWptfGXbWgy3joE+OyqH5kbrxkjfuI
ejN+pPSI1h4/zHayB+8tY0YII3t2F1Bn7pMirEONBAubL8hBGIG6HvKd8dBJqLiq1FmuEXhP7wjs
ShbKaCORmJ5n2RQOUvsPEuqQRHWdWLw1G5B1n3i8w1MowkHNQnebiEYhdFySYbzUU2a0BMTEZjjU
9GYieB8cX9Ki6dfvwnwwc14+PlY2kvzy3YorG9ArCxffSU8DwxPeE3PzpGd/ZjFtQIxB+BXcp9uu
HH6lH6cv2Wj2SbRsmkvUXDGDJ9qMk2Ad8whAXioG2D7UMYVmARmadBw673H/wV0UAMZd4n5Aqtsd
LVP2PjzLt+1uGCZm/A04JBBF1VSYCOWXXlYtq2qkwCP7GHF+nW4r8Gm6WqcMpd5ZS8oGtiY/xiD3
BVlDC/XGPmcrdhPz3AOo0PO5IgwoSWh0btpz6nJkyv9SEH/Ofr8g8Wxhs1y4O4IWmrNCmNOQ5WOT
NZecZGaZKfVz38JopmfRQEMAGCTy5OArPyE1JceLg80iEtbf5N6MkjeArw2E1ZTDOOV447Ar8zvE
nP6mXwVAZRVLorOAiX95z8OWMmmxI/3Yicub3N3Dwd6uXqpyoZX4HxHOGO5wpuBWiKVQYmEJZbKe
iR/UOU1AszGjLprttMdu7G7PZm2cQpkdXZ6SfJKyuk6fGtfBVfdK/72yzg9iKEpkRQq/NoAlMgHh
kT35LeZ4pPC8ak5g6rcLQK4bNXIDj/ApKqIqwqSjvtn/7p8ygDp12NbdZRuURvIG+IjG1ln/tP8L
WKmpydb1c7lxeAUEMGzIj1Npl3pGr1Wt8BOkxhm4hn7NKcBsVyO8amFo+qDreJ4Xgr/WyIlzelRr
Yjz11bHtyN3tABq4tk2gBcVwZjWKUMqg+Lnm+b/SGUTrUna4sMODP9lM1At3gp32IB5yUPfFZCHf
pXCoOgeWigFFp71feGukIWryAmSF3hl/JpFuWF3SB+AKERYitC8GzatRTXa1ac/qfG73W29O3KpD
FJ/pixQ9RjwLchlacGtOsxEV8HSfJpvJHgEch7JLEAlhWNPiNVWEfDiuC27TvoJs8b2r8kLJMLwR
UCWrH7MmZ7uziouIg6SbnHx63SrfKee+jTUlxNCjemj6CAMyIu+d1R8X+R9d8Zui7GW/RZY/QMbE
XjLcEpDEkiJt981rITsYEeFEyHMguM6Ju6nIHid8SzRuEWriZRmEIJTAlNIiNLwMJugzTB3crOQl
8IBfaMRzjfCoau+PZND8cAA4s7vNHF4D0OokRek2glXyoRMl1VJLVGmx8Bu37nyNdvu1AQFjSYLt
etkuXnpS0VKHm9ZgA4jv6FmgSt2eUmSa6qrnvPMC3oNUSWtDdl2AajaxIAbvwKZgY/beH1iIkNEv
TjmzzCSq8SktUmBG72Tjfxpu7Va8SzV7CEVoXthUQ2f2wog4l1z5+1Xj+lXv4PQkEAl2xwkSxJln
lEG391BLOkFz8ytRyunEeaf0qbRxQqkLIFbClTxHPYYVF5vUJ66KAE7CRsABWa9FDyp8XMtk5zAl
bNo9Ns/XQjmFKd4k92EtfeH+ZT9RuldWeM+9sVWxeKVSntXZAA6ppscYjsGfRgSp6dGksLyHzi/s
Bwy7i1P0DdbURQM8g+Bp9+W8ADwkj/Tw+QQUXogp7ZwL2NAJyvAOr/16eTgF5Qun4OykMrEfpcJn
4WkkWtbKyL46Afr7gObVr5ukGM5mMGxU8HmBHqGBjJmPyhjCCeTeHkbQxsZZKJUo2WowikWK8shF
CTK2xNy7A3kK54cBBGi8n1gBd/qRP5i/ISxSLP/FIC+/MtUe5aSGnI4+AeAqyw2/4eLsiNpj+tkO
Ogn1Ld4k9ivVN7f+7/htAQEDEDZBODHL8IwVVYvhNTsfsKPs8RpJMMUNun5AN+FM4xOC0OZy7IrD
bUBZLmUkm1x/CggFdLCedKFp1P7Nv/B3wrItPNaJ50/z7IRomLk8I8QSC9zJaLyI9PeAAHlZ3r/r
SZ6scDe1XGNUQQJVnoXM8ivLdua9OY19yh3fZhePtbKbxtsKdShqdFf1gXRJNrQh4L3GTOaJNOTp
DfowShHtYS5OS0FuDNItNDPlDrjb4yaBRNf9k1fUQSgjjTLtpaoEqkuWmAdTZU75T0gmQKeEdRmQ
d/REs26i04OWljHjoXBbg3gVUT+pAS/51KWVMIt6TKU3/oK5N2XAxM0GL9x5sHcle4+Totk0f1UM
pJSDJNAxBvl09xwAvNDkI3rv1If8srNnYf8woVDiL/GAl6aVBgk2Olh5A4fq7NvGkTnRjwBNoR67
76+HULUBRo7ZQOtL31pyt1W6DbOaRUwPMyLEfjjOh/f/4aP2Z0D5xLUz9h1nL4bk9tLuKvhWN2eC
v/VoOzh9knxV4XPU9k6FbNki+i5AoEoRUzkmy857Bo4gHOLS7/OQbbcOVu+42q2PJJSBPt8KF0Og
8O2QpP2/q6e7A7D2tzI/deUI8EwfzhAv5v4cYEK54AqR2yfNmaz54RNgcisOpXnoPzSAmi5Jiy4w
seUpvvUtUt3cF5xBmjd4H1njGi39sQyhQ5/xvuBY2HJMWMXIJTLYgpvKYSqMHJwhi/AxnP9Z3QLR
IliidA7EvSzogBR039dzo8cF0ksFtfGYV+3P/S1fvjP1mkOzPu3XR7pWZIup+YYQq7iK4SmuYhlL
EnmOJxtLHjEWIJ2IVg1C+5bkUVOfkHbXg4BEnClv4C/tHNZWJt6h+hsD/WWW+wNSHvfujeIyxJ1H
aGSCNa6hGHhrwyPdCEMym6iGLtMfytUCK4RcpDVx4uBJFjWnYl/OQ4a/2+zNbyv+pcXIkWLRe8oO
06fRGbxHxbcMiBKDtwfs3ftrHM2ao2hMCrnDOdnWpjoKq9BPYMlreZX8FnxhtVwaIqkJkQvm3WSG
a8OKtxnDF76zPPrInP3CfNyM29okOqqlHKpUaEFkzRlaInutn/9EbtmcunIPVSHv2wrPgK9EbXyq
vDFW4nPn2G8q0NKET+jEWcTOfZhlcSR3MVqAAc8Eyn315NtKWhy6C8cdBOi1PNJruNo/R6+crqw0
U2R5NmesHfliHs7RN/ixyEvnevb2pZvwg01GfKMB9salRlBuPM1gnvkXNXXUEG1N3QoyLDgQW9Uy
qFwWVVNwl4tSF1bm4asF/r3tMU9AAYIos9ioMRHi4aSxnBOUm+vznfIp+f972/MxZenx6R8J+S5t
jN3icf8ZUTPX+zVK+QvPTZT1Z4ykXOCk3VjtQyHx/3ba/vOuftcVJl7asj57uzOKZ+y6RLoGADkq
PZsPM9L0XluYwd6zYAWZDz+LHeZgo5+aTPuDQ0OrsZjMV9LfjsEnoHLQe1NFOf8jSq/RAthRjbEL
vlvJZOxaTM0B812GC1dvy70EC3ANFCa1p1i9qZZbsUl2DG2SF+Q0P8s9PU+Yg6TKXx+iBSFoiVc1
7aO1HcaJlBuWPsN4UfqiIxXfmss3KXOd1Ev+U+VxTIx0+SAV7QsFrNz1xcXgK3r/YYffvSTfwhbg
HiBD7FlLBC1/HndfD0yqpu40/OMyjCclh1KjlssFnip/U0AcO4aYcWgMr4yr9p/LXO2/PyaC6s4K
246JXCxMfl06I48Pj6ylR4AfEc6ypfhm2Wb5gu1Dyp/5yNJjWSA4hDog/vJdelIo0Wu0vGLLuwLs
HbXG4yph/T4B6KoB8muzBPRiqWHxixRXcsRJTgeJYjWyBCsZrPrl4LAWoYbVDVGvIK1ZnnxM3bYk
CgznsbVv8CeANMXSCperCepOFVg39YQ3gwIc+V3fdyhyzeVKqqyAXNwANyMuHPv8sIUKXGzZUN7Q
v55m9YKKN/lMd/CixzHkc8NBSjIsdk3YGcSPuZGMU6Vh0+6c5RSgjNeXr/Um/3oIpHHIePt6oLys
Z0+cVcM3BdNznioVMDL8uN2UNNCgL+KTMeVk+be4GSmos3o+c+gonMuxHwGLDxQQk6/eUhUVCgVv
JNepm1O87ulOjRPtSJpmTVOlxCj0FU5c5eb31dWiNUqbldnxjj95VywbKMb1ixDVFOtl+Jx0ciU6
QGO0OogJ9oGfSw7snkftcNPGciuyqkzZXzqjPWhVf/7exsUFK+sTCse/lV2qEOgpLkrZjFA8rFY7
pJ0p0KWR5f5EGq5KorIAuRhce1hTp4bHOTSwyYunl5fOArBLMZ+UEv4L/LJ8aouAZvyC2zXG0FMq
+wrWT2HG/AFuVLR6PzyW01kqKAIenBFqjgq27me0C0CoX93Yh8ZD6IE1fhdkfzPiUuw1DHnNpqEg
dospkG+6eYM/rqt/40hO0028egQ76/QNdv6qAl9FTTRTTArX1mHhm6sROHC4sJLZ0e3+wbqsLYe+
R2YY5uAcdBqJ9jEXpR0XJe7GNrUTzhWr0LCFJV2pfxgKxI1a/iwcbkplDaNO42tpp7RhexYW4wAV
mw5nVhOMKgK521XK5gLopBacJ8kt+wKKAIBPx0gkoUF2Xvczn7yRXrOOAM+PA6O7VBdPrSxJjklS
cTMbv4trZ9YCFsDEKa1NZ9JUpqVHOt4V6pTOEgJG/K9SyOBkvqOlYkwSSt3Phfjn7SAjrGZkswcl
0enWzIcPl1PUWmnesZZ7DZHJdDDGbgWPE5pw5DdypeUq0rC0RgTtd8CWE2QqLU8sK2CHLH0/sasK
riMsChZfTuYlZ/NxfNIL/OvK9RFlkBw7UZ/Ti7HWHnhDGKNAGMVkv+SAq3xlbV7CLVNIvugAVrLj
uFEOAIi3/n3xmhku197aprimHrJeOuwravlUi7x1jbNDgV8O3W7X33pMUM1DPvI2SwSYdEK/j1jb
bUWeZc77HLcw/AlV1UEe1wTD37N85KyT+rtCNcx/nh+VlyeXfY20bDM8kwbknIWO7OrbavBb+t4/
jq0rc7Z+MgNxDelbKOsyyuFfhdfXprg3GyU7VD7nDhvsdZSP/dgwvjOSnG9bRa/GXNOWyLjXjWgS
Pedybov+gsNkkLxSXezxlzfpPaijgzax7NqRcDXUBbTXmHoXVnRbi+y+E6rUVA4W2+x9pMMBSobP
AEsB5+HTgvOkNwEIWiuuMBDSHmKtQwiccjeCwG3nyrgWIqWcG+DG7rdLD/m4UoQWzRHHsGG3bhaM
mFGrIo528l/2zy9fk+PRsEspBn9eeEbzOWv9ig5GOXcMOLeqLM/Kat7Xsg7FwI84ZjSfDNuL25eB
RIpCdlJpeGdiOjFNFG9yojRX4eq3h88zaX28sRLQmByD3UPgLwE6dpvCcqX2Fdtxjo2/eJmWpzt4
4OXvVc2sfQ3awRozhcCL6Ixfc78SyBCCcDiNbRmZr2kHvf8Tms5bdyaxT7+cw7pjjkW1BRyqSy/Z
DInqnjnOkjTmP55NJ8yUE7fh3Ef7Xejws9fTIfKo34G4WYkqkleeLCSJ5LDwhXVrX0ZI6pIphBCf
ya0gMoSXcJCfgm3R07tyLDG2yfrrwvvFw7XyvUDZfean4tkK/DnKOci3ubcgvTku5wRyVH36RCi2
/qr/LKF0qHIYg76szxAcMBBrxKbAMuu1E/PEt0PgiQsYrTsInsWOQ6BkBru3FzbPV54m2jwMQse/
O/42zoPz19Xagk54mH1irmDCmPrvOrchD6RH4Jgt1iH9of+t1dtFl9x16Ib5W55ySo26X627QjHz
yWSVi+lQcQK/X3Z9L2qgv45VLr7OCn4nCsmGL9M/R0gFZcyod5Zx2mEV4MdjLJJ82I827eapPP/O
S0DrlrXkKKse7N1LrF0oQPODUbqCq5otDfp1vlyO/QkFjBRR9tqNHjJT8sIYx1IG66jkQK/RhY1u
j7w4TgFASabJRvBwwI/5iAyc2koBr6KckhZ7OUdasskAIWgUUr4DhqBbq4evRweAhHVVXDbLo7n6
Pmb4XrBLitPcLX230wlr8gXbBNPOpPT3Ud2zSyLFIKC5tGjT79AGmIpfqnjsgBNEiLCrLjvNklc+
qfUrE4zJ0khjRzr1kVnGjoBC/jqDcLl4V5yx+FO10hsshujdvnxJRBogQCvwybZlEbjDjmazHuz/
v4mN+W82KL+f/lRYXFJHc5IDxFQzVGhRsjmRiMdBRL+6SnacTIJ3/gUqxu17hPHqxB9kH/R4rxRo
924+PvEtLofz1hQZ5lZTklva/tExBkXUsFpjfTElCK+zskttzhPoPkUnQDcMSDXVeHQDx03GXPal
E8QMZzzS59Ej2vYEHI0yOra8eGzmGHq2tOiQYWvsHEpVmdoP1ELpsB/Mn+QxZ5St+V/CWbIEjSRN
bi3LgpynSwSc8PtuR0pNCyzA9gxllslN52feZJKR9aXADMBKLVIq6oAmMhJmXRuENPnOP4L1kTB0
+/7hco31aoZx5Xz2FRYrX5SqsvjPjDIwhsDVYoZvNIaN7vYyyRm8kje3ehPmfKgseGBx862zpvt9
BlblvRsCRSoMvKJv0C1tNYqMiSZYj7R9LuEx3xCKmeDv/YfBM20DQT1h05ot3fFdrFUivBv8GvnW
HSlq9CTrnErOLn51140xfjmqZiTcCL2Hfxs0HXFDzdmqgzZNVTeuJtxRUEBZOvx8BLtNHJqNINQH
sXOLvx7Mc3XBnJmR5Xtug18YAFSuNBJEqiooy7NLwDgL70/8HaQXeIJH0TLDr9aUqQLSeudO3wo9
GINngGxPEv7JPucjhkf+hpf7bX68Ebb+omVu2j+ash2ULjx9EFzH0SPh8YE6wbnc/kFwCZoxccDj
VEx82tPKgmZU5hkLEV8rS8eca3+QGw8BR/pmRZBoVuNwj5N72aIcvmqUYffD4VQ6E3+QEGeIB+wB
ynk9vA9WUExcAcR0Lm+OAAsDrwRpmZD83EXJPbllGe48BB5fVzziP78RINoZCfgBPltdHESgltI4
vTKLI30rnpyF0bLnO4xczINdy+JVd9P1ozOuRNYAUL9RZNX+SJ9JYrajMboKKK7d/SnhRkjV0rXg
uubO3UYSEIxPC5ZImki/19ALb2t5TkL3lC0fmihXH6GYaIHhhNeuOoXQO6tQCmVNWhC307ZZTXR9
7rYlYMd8djcIQC4W92VmKGc9c4DcK/RDusTKXtQjYHqwnEuaUGuUCdY9ED7A71215OsjNGxQ228G
jFcdcM0wqyr4GUcDOK8WrYbvrGqBZZwosgZJEtyKk7FYrb6zvdqHN0y5YPDtRgr/8CVfn6xGkOvg
k6TaPQYl4JBP2fOgF18J2y9RPDTR1DZj7xwAeGv3SjuKffYjV3hDwfQQktFuk60X3ewzoMN2x7vW
LdEQYN7MvHpG3745q8iEm1s9Zpj9AztiEC1qJPs3aftpDNNPipuC1hOkMs2fFrkiZin+03uxQYlh
OvgVFRCntkLKAibVQ2Tntyr9qcs6+zAjlnknSGkh5/0Iy15GhiRofwJhnKiaMbW6ZW5JRMoVRaot
fn0GBmSxOL10K13MIdq4Ny1WFHRPSMRgfZFqnmT35kJhCWflJV/lXVCShVcqO+Ge65Srl6j25Wqw
pBwbnS/g7pcSFVO2NaUYgp6zKblyGyCXZ51Hqcmv0cHQRBmEBDByH7S0wkpMk1vZFQLihl0gp1Kg
uKTZI0K5GFA+st/LJHbUn7Cso6tg64h1D3uhOqj4FdWPwDDZuO2hEcxSg1JLlhDnRUjRbGN405Jv
oPMU+MZgYrBXglKpbgAPQ/bC2AJOqCn8LCYhXJ2aBr4W1zrGCSfvSJpFFCztiVQjX5dhBccdy6Sm
ySFKHeOrUwMQiTtPNd5caxd3mKeMXKtGXifcZTvJ9hv0NuRr8QatcebprlIUUxt0dbXTx8yrTvRW
ALCKibrNV+BPIqtIv6AbUCx1jirvteBiYQ5K6kq6j2SK5RrfsEYorN0clIwNl9mBi6uejTEaRTvh
+4pFD4olrH5D7hZfuj0MUJ/2MMSWFOK+1pdUlkuUssGXBGX6S5KM4yjPoeqWwVePqinLIdvdyjsE
D0UAotFGjIZfZaE0de4BP1k91/v3cdwLMDoy8XmQ80fQqUPFIEGaB+yYeudxNo93VAD9SdUcMpNg
/if1cSjlXx0nsrKa4knDN+zxc51i/Gi0rtm+MwgoQplQyd2+WuOCp3BhdkJerQf8zQoFo8CDS7+K
YA2BUrW/fJxaQphmk/kS+0GbenbTtMm9eR8+eVzJJ4qyOgSryzkBXH/ZUpp8fjmuGrmrXoEJRREF
P7ZbmFzJBiPgBn040r0vIxOO1dbWbZxbmcdow/fhRIs8WN1u46aPh9z5zbQZhQEwDBp8JU11kuVN
QHvGCqDa8TA8AT8gByF3j0UVI1Eq7DNjJrTQMlpe966u92RkriRfXnbmLAvDdTeYmt2lm2Gjl1Rt
140NzzfyquW1akUJYDPhVrRyB9yxgJPhpQjBI5hd0AzfBO4y8IXVEvmHqmcPRgEsJhAEWHyqIUFz
fT6E1iITk9V1VBcrhwHRFLQM75v4dwiG9qFQeVqzuw6naU2L73XWvMcCDEcf1bEmblV1fVHevRGM
fmBWpkLMT45C+OBO+MhHbluBuWOVuRtJ2mHXghyK2xQfnn4GstkWlt55LnNuE4Wa2n/1ApzmoFci
JGEjRpw/sMvql0zvLSbEKVyDyWGT63BOYE9Aad0ReAgO74/UImUGTZ85yGKoYW91h+5UHNoydYqB
fuA8iBBK6hVXq+xCIs9sGyNtSStCb4Rp53k6UhgaHpF2imjgPiOKIlFV9/G6N89UDKVlUToVWDSG
YIpfmoqlEzpNus69p/NjWcmej7wbxso072bg4Zpg8YzktToOg9jiBOb8JKfZbj2dO89pqw/jftZR
Tup2jiAIo4JIA5J01Gkce4WLz17BrUdrbTEUQqFTqEmL4dhzwsfzZmuyQ0qjcK+T9zS+1BoPTF+T
eT3y/CgiBiygQjB34qVHb5AzDKifyEHdp3RanQq8fywxigVHOwnXhOvRZbKFisbo3wW6sAB/xXKW
dKxFg31Va0CzB8Qae3XoBt3oB6Hr34mqB0Ht+IPZqZitKje5pZr0F4JQDOyYfeUhVLFqBPREU5au
A0oBAb5BPRnHEdXW2T3eVJRPvL1qcPIMyyFg9fhi19q6U78+qPTDMtcmxamjld6Nu3/OzZBPb/bw
1kfD1GMJSAZea9xPuLmE00yPBglskXv0wc6ZttReBVKvfmsoyUkmVA/oC/mAK8I5QIJ5eX+XNfv5
COWuoHhSQXUSFNZLxgAd/cH2sALVMlJ7DQF6GfSERSzNFtsbOfOh7kMbP846nqYBk4ABzibGCeGU
0iouq41a0k750x/984lROTPlUCgRfpjxzte74Iw5F7Aye67imQZuysyjmtAfWk5K5kdzIFmUImY1
UQDGTVtS0gTr2zojxi1RcWlitfIiajvoc93/M10d+5/5LZ7VkskgxkttQE4nYY6lg3L+HhBDaFkH
pZqoX4ZlXKQ3j0OvsklDn4Eqavs2+AAMn2jtF828tlQJPm6ERgBd03xSoA8HzJTr/yjzni55fWyW
xYgp372PqVP9Eoz8loGOQske3ZBYRt+Cu4uZMwOSl1LyyZ9lHcVCDf9ryFWUBgELmG+LIim1RUSx
Etn4p0Ms7uwGswsVmMJx9sZOjCAqKzEbJm/RIcyosuOkNcn+BL9CWvS34zNB0qnZsYkpk1Ovv5Yl
MOYshJGX+II+Ae6jVA4O4NCJYletaPaCASobQCqE5eOWItRBMck4Ppp4L2mwXzWyt4NcfyeBna3u
9dWTG2VkZtTHyYJDMXOlxlIvBcDRAl5r0lP3RcxT9+Kp+L0U7gSA3GSBF9xHUYfean7j6wvKOHLx
nk2g5JA9oQQ5TPwI/xINqqLm2rP5RoiksJf2SugjHDPbiWlZM0j++nXRpmmZOxXu8ENYOoJR9kdk
WXjNNn+F/nMmPlyUOBKzc2a0PF53W1mrhpntfPUT7xcdcc8OpwJRK32H8S85kEZFYY/VtSWUqCQm
9pbQmagifTey0LL46v5M5faq7/A0dv/ZaOVPfDW1NGp6TomoSaHq5BRop/U0OQ8DBYFfI5L1uGYu
2I2aQrAmdAnShUs1f7QTOWqnyKmNHCYj2zqUBjxMDrPa2d5Oa8ac8tGXEmwiK1bbCSEJHVoAyuWA
OVASXh/tDtT2rAEW2RSTmgedPDppooWi7W0BB3xjzQgz5tZ2kQpDB5LL+bZ8m3qU/IRnQKXCjw1y
oQjk4ZoYJM5dUdMEhXaY/uGQhB50m2Y4vGICCMdlZ1jjRE29XgfviShgZ0ii23dP0+UmiTYkSdmW
+csObdxfbSVW+ZcVbdqmJKMRqAhxfbweoc1W75cGOXZzZO3PZcgiQvs8863PNinu4tXa+FHIl+sX
c8ut/kl4bZUCUpjT2aim2oVzrib9RYthSefZFRPncHoRxsakaxdQzI35jTiDrO1yqB9dnMR26f1E
7R46fLT+IU7gVuQebSsnm15h7CBE7GitTf7a2Wd4lfwFF96D2gxlJIS+K8EQGt0zAMsBe586A5FO
kr/oVhZB19yWgnwuvHS8E+VuXidoV+ged7CGaD8dB0BR/yfGTehMCrql2KqgyD/DDF0GOqTcsEG/
3wiO4j86SIAYVQC6D0Q9u56s8MNK4nUaM0qFRl8G6bP2Yf84gg0CQHtxjJmrPS5yJqEQXSLK/+RU
Y46+0Y9XsORLoghM3ZDnLkL7q0zWzLvOImM9LOuhVcHx+fl22Tw95Do3N1qJxFc3pY1HhfpbhkMv
HwgxMX3RSkbmTfMjHcDzFbVu5cymnUSfxpxINXTnBiErIXfGENwB235wgIfn7JQQy8u981Rg5f6w
SUeOpCtuq8QtaQ/B1x+ZN/pmninpCK+PZFIkZUgjoBfMvn3/EmdWIetcVU+CAayqsYnfeengCwkb
Q0yoPTgv9IpPPJpZDyhW1MhLIj2dcCut8LtKcoVoCfG1ADkvt6GLJu61HrXhoSv8EIHy0NXwfDDT
FlCHFTEh8jtZHx/TwyU/iMRauLZRxuHQvleSlfus6h/i7aPl7PsadjvTIVv7xCN6aXZAxTVDg8NJ
wHmTMNrf89yySt2vwR+bBZixL+lAp3EctrCMszwwGamZdvUahpzt2uWrqtPm75zRSPk+hbUOPZbl
EopqNiSoOybEsm0KyTe/xhsxOVZPN+ftFIhn114LTsjUZYDFoUBxRhFqLFjL26afoFK65iRUBE9n
Wgi7+iEzH7Ar8vn5X+MaoncF18Y67sk4E+NsY0tKwkHsJCIC7q8oDWrIpI+mpUGmhc6HL4gq+3A4
wMlTA1PtdDj9rhB2Dx5qHew/oU54BNIhOmEn9XU6xKuLahA+8aL4rpcWEKMj7eQUu9g27fV074Dv
9FlDO99z2gCMZK0XW1U4JQbeSdXDzSTE83EsA0jjLodkelx045vujrhcbfq3FLkzU0gRlLE7HGcK
n2XOwPkRvFRc/TWrlul15CB1NT64F7MDbhk+MytHzXxSZRnqaS6w1/kF4Pfd9ZDXmYl/2dzJBb6j
3nCh8B2WQIgD1SH/mYB0AcdotsVj+hsU8Gk9vMEDa4zAuoR+WWzf4xMALJRy6g8+jeDrlHWTV44v
/wi0RE5qrVy8LXsG9qWficyY2UFiZ74tsevA3g+71UIu3THm28X4yQcxW8I0J8YABxPebHs3MSx4
qsiSeT6NjznbFHy8sD9FJxx+tCk3b6DfXKYVb9JfOB+DFKH4HkDeN3A7pCYuNef0pJRJwa8aNbp8
Smi6ozWoRiuCiuxcfKxbcGMIfU2LLeooVkWZoyQ7NpIlzzscehfQwqqMuo01VnFRUugoja8UiWrM
LS97WERraUvgXYptaAaVGGPKdZ9Bqt0hSdjnPX9jnz/PpS1MMoidENaESTmaKceXLnj91YtqF3s6
xyEoemHoaKqEkgqKbKLTL2+zndcMaHiCnpJOFthU5vjbOJ9APAzE6SVQxvzyBvM6zahE2iTr2dVs
SDet7CPp9zM45/bYA8Th0NVcYMAGeAlf3KVf/a3xH/EIbpFSaZXY04QQlCmrHmAeA+AvimLBcFFR
2HdgSEcUk9x8g81XyUwQDPGAb2ydteHRwCM9oBidlm/oRgykZesT73limi5kwrMX22EuvIJ66D0b
X9OcuUCA1yE3UHZoIbPA30IUF7fx121l1eRCmTuh
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16560)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztlHgsA7XTu3se9+qgRV127brGn1J+SpZIMueDb+AV872JX
nOXB120GyVLNbjkhWTWXGQdsLOXfaXs2I36xZVRiwzpAgBzfQJrI9hG2kq7bh9WznJ3xEF5DLexY
Cq15Vdb5gm0qDaFFZVGzlV0qAsnNmU5TwLZdRsYlrsSd1i9jUQlzfmNsUENvXGN3CDlY8CFK3jai
INNNriIElfSpAetTkn9VmfppFFOF7wWkbrMeWuJ7l/thC50PzIkDIzK4x9CtfhJd3F2cp+VAeBKF
LrxUYaG5u5XXGRyoHikRUGoKOXXmqvmZIKvGnqo9OmemjsqjILGrPxP+3Dy+cG+LmqgRYTxy9X3z
oMfdSSQ6KvJIZvqKnopohLc6y0/oMFyP21GDeRYafr53M5KZ/f/dLwptOby/mIDvt7SkwnKGfvFl
EpHTWq8Qukwr6iDxqQsNxGo493Q+4LG/yKuSE0SND6bwyarofUfxPeW4laRQMKn7H0Tq/eaUvdP7
vXl1nkBrtRL2reVVADRjcpDm+3z/jYigRFz9ttrA1C+77PRjiowP1YG1fdzffqSmOJ2j2mFWYikv
ToyM9T8m18egCp2ghJoN4eI/VKWlDfluDP8ZTsWcngrJsn3e/GAOL8PDe92FDeVUKpkl+gr4V7Rp
2aPnAyyzEcBeVlaEkmCZITU7qdXWBM5BIqVU+5e2tVie09XfrzH5MIHwUfVaSuy2u55zP0BOF7Gu
CUEPlLKnR9X1WrHVcPnd6fkPfFulzaTs2HuDJi/KrTvbj7wCFie6P4/WolNX6kPWjcz9aQ+wnwhS
Cl7c1ftfyzJMNbweg5RPfaq3a88McLpzC6etEqO31+rgbz/dfhINoJkCiNixX7xIp4n8lci7GXoM
doKmP5XLBXmP/Ef1HlFhsKHBbwP+AsT/HJKsRbeMXUWPRtcZnkpB4dP4RxWecqcBPC+ggs2Wg9XD
flCvKjr6I9RAgAyAJYDKpapS2KNmOBVR6fSfSEbVOTjDKBU6mPvbIW0B1GrxujCVwXhYhzfa2n7s
pSvvjqm7xICaDI8wL4+o4znzeARXPT/oyN++/EZb2EHhIwgPpY5/j+VTdImaOHA9M1rXQQLS5YiQ
d8fE3ICl0Dc9YPx7Gi23TU1UqiV1wx1HdnYhTuzoxdEq6NpLA258Wh+rwSu8vP7hWDb4IQs7YCmU
6c1ehdkx/jvYYfcnI/kqhIpv07AlgCablcW/IVHSudlBYFvHKGNJQlgPw9VF3ckGkh8Nga9O9I9d
WGpkXkOB7qPMCwxtST5z9waEGTMzhngUhfVQG3HBNTQ2/Wat/S/5ryngqBFCJaIgUfrzw8VYPRpx
Ma8yghJP9QRD0sXR0VB21eJw+4iLEg1o1b5xf9NUkYGOZOEZKU4Stu4K+cfuS7iTeocaFB1jsdNn
ntMoV0FAqRuj1lOxDG+YJLiVc5qi1sBf6RQL2iPcSOOeEQ+PD/uFwCj6180hC84peYYWAyHN1Frg
05/zwXh2E591TYe4C0h0dT+Aos4yWciHzN20jWOxXMzIS3G1qwF0EGqAijrnXGLcGocwxkZPDg7O
+ZIkcpsjjhwsvUCRAmpdYb12MfN1aomq3wUg8VUEjLXBfDpGSJm6LmRFOyE95KmkhVn9RTJI7dRC
jwjcf+RbuNT2kw6BbtbyviR0PCqcqqTHTP/U7tvsE06ymyUlA0+8IJ3mEXtUVLHrlnKrg8hrwXl2
4THwUppB9JDYFgpLPAXCkF4P+9MlHt8xmiKzjjY/jg4X5Mak8s5L1GLzrK731k64QPGLnV7Y58fc
JJVHuV7cVknlClqd9DJbTGS2lpfnm3E5Xx2a9tbuW2oKicS7VLIMnVFCOqwczmsysYtdtNgGlee5
1fK25W2QAG1uuOeASXuQ2ZNt0bEInni+G7PBrvOi/pIjashgqTgNL3SHHmA/XFMZnHX6netOZm3e
BlfRhSx0HBjP/WZtK5NmOcyW9rMppg466DDbqoPfn9ht2ThmNdE55qlP9RBkGuq3LmORr9QPoP2r
Kez2IK03BRuNytY9tB9JWMXjpeNTFfev40Y2apCXKqghOHbvLqicXRe2RpvdFsDdFcAH3Zd2cOx1
is5sPhAMvaqwmdbkvhYB2IccISAzJCjDSLxf9u2Ohfbk1LkOVNmX/lsYcr4M5bchScDMMvbxps9A
/nKuGAdf59tzE0AtDeG/JB6q9/Xatq9vDckMhMnW79Nj2YM+eA4nboeZi2q2usxzOCsHZCPMfnmQ
JdiYT4tcLjLpV/MAsswTqI2YwYG7Wsr4TfTd62xl1K6gTKPFxD0Bxeh/7gMUL+s04w2ABMxYeOUS
soGkfyrtq/fWWpQisTLRSPV3UDe0a8xM5OL7koiF4kZg6J6vU2gRPDL6/9fq88Oi9w56f6BRRcy5
zn1CYRLMCbCuNo0bQ1ikRl2fwa6WE8OA23UlxdNZk2+rphNHNk/UloVCB5ZXiKdP89w0J0JyVcme
Cc0Eo26iADVldbzlUVXNikp8CU4tzrmC9jSh4NIpBU6d0qi+G69Y6KulyUxpENfSof5PXnrXrb0Q
89dsh1dr1Thsq5QZcNvSCknVagRzD5eUWy/u9tPEyziJvWGUJQOb/YSxz+I915Wlw3Gxem7EPsck
e1PONwATUS1zh0sOiUIChUN2ZysliabYb/tSsNGvzBtEp+DbZPlcoyqbJHSoP1TjXAnB/TDMobpY
yugtm5DdXSlGUrsKwBiBRcewN/Y7XznivnNsc3JPTo1vYK5Mc4DCRgFEZfIqde02lPpl2OUw54bh
699OiZk8Z8JHlBC/A3sqOSelp2MNG5GW1MrCAdQjpmlf7u1evUvOQyjx5tM4G0aaGiNS35xwXmvy
Z3hId27r4DbvS3CI56QsLSh4NsdzjHoirwkfFFUQco4kP6r6bBSb+qSdg5mYwvieiEwLTDYXGdFR
9H1KBQGXkHjNWieL8VYuheOudvT56+fW+kiYu45hauh62DQdKGeGikrGmLr6O7Cs5+vYXEzV1A+o
rsbHB+3w/DVKGDe6r51wO+1rKxqQ0Ly+zSKNFfswqm4qVO9OSIjiL8P+9WdX2WRpsnvOWOa9LUFo
NQi1p429r6FXqSXAxtJFZAgtNmAhrqBd28LyAHLvJsKdymxhpLsNGZqUP9VODIMT/jg9FeKzeDhN
K+mriXZRagg47TCbQ2xZG4/ay2CZfZ2sKH10qBP+sssi7JR0Ir2VywA0EPn9PnMhtTgQtvqypQKp
tC3vUX8ahzFNh3Rwo1+nu3wdy26gqFRexgdN/bJkXd15oB982kk1dlJgX/DPRLOnOtTMfIjnqRu7
2BJeaOK1r1bEPNmwXEsaqVzTfE4vFlLEBmqnmT4YWmW6Nicd9qmfnMC629+UyKOGD1E8xJcFqsai
KGe5AvZuNbA6toK3QaB3p/GBfA9yvQgi/U5HY2xKehgk1556cTgixJxIZpNI2uwglCpYejZIoyYw
6MJnv9EPF/8HnKQCdAU6BeocT+XCeiSTlDDbaeGtC2h/HJjGXOM6hrc7vAC/zpwnoyF7BrVFoaFr
gUbOuzQlFA7zzL7gukUB5wlipL4en88vw4fNqQVoEsXtOJt7+OwYxZGX2DVrbzXE/u+6qgVZrJE4
GQ7b/tFeHjN2MmA31MwbHpN90Bx3MkW/t/UnXttPwJLkHGqRWBEg+6k5qScLFuJU9yfxFL6Gl1Ts
wIRCystlJ0QiGF51P+e4bdezj3lGSLIsINtYaa972U88lqm3si79cpBX3PmtfG0LWfmvcwEQ5C3S
O8DvsGbXqhKhQI0hcp/q1GLivekWYvv0DUYQwl1D0pqHEU6HhXAmtkavBRzh+bBdmM4eq00j9/ey
KMDXJ/KGd1UHloG2GevD15YewMLbBrBiBbGCrKoG2MlVx4pS2l8Ed6uFi8sr8JvMm5BfOB4qMX3k
eLhMva3T55O4F6d1xJKytcNUWG3o/ioUCGqLOQbz5VEFJuO0yJNibwfl0L6Zq8nGoa1d7tAFKrf8
di+++XVql/0QR3Objt3pn44+I4/xFX0Fo/WAA4Gjx2qN2v+gBwp4PmFB8RFtRHZzYeho2dUEaoRS
iMRoCzeoLMqR3IpyV+4Ke+/YXueoKclTjREVWIZx+xOC2/8Mkzsn5exuL8xBytvXlZOlNThg1q/s
l+UTvKbilMmlpnfJWVQmVvY1ANEms1T7Fmi/iRqLt81K2quZBkn1yotrpJQoXWim5/1Xx+FbJtpc
Z5W0Lei80zbfWjkV6fJJh97rvbydPikIQMr9ggiVBXziaHiyz5znMYChR+noERf30uWQc3r6i969
l2DppBpsIOzfpUufIvlfQdviduKBkfPmBu7cwp8Z35r4PCO8d6/PVWhVy/1LrRH8cKz7XPVpdgs+
Po/s1l+Qq6117HHXkaG3erTJFyrL/cjeunpIxssncNIfUTlC0ZhoLm/orQiCQ1AUBv/z5KFlTyAo
VSYL6gRlt2mxsIMjxj76F72fc+8DYK+rp6lD4fpUG5VCVquHWtym4EXwat4n6LS25KP0AI3Pz6IV
tdpsgjz5Il7fHQ5P3NG3r4ovkDcCTh4LSwibzVal6hT0QgjhsTRTwtSyjwURaXESfpoyqtm08gS/
kHuni1hz1GYk9h00Z656w/xYEMFTzzA/nP4mvA8eqwo4IxrSOxhBURV5iLrnl7W5+6u/XyeGswma
UVjZu2CdWHnHs2DTL6MZA1dw8CcQJnRxDi0iJDV3Yw5QhBR3B6l+6opFKyHYGPchwT9kYF9WOnq+
sX6DCc7wxGppgxXmZQdKcHGDG99/GEBN3JzB1wVu9AE0+x2KFcTOKruRuetEFiZRugsWJk9CSMd/
Pqqy/1ZYooTmoIpm9FYrtCFnT9cZPY74f61YlKZkI7Exq+2450huOnNcq0DND0THHUpPYSkZ1Cqf
+l2kGlL1EFHj8yRGpSFjkx7gDHvCk1wtgb1ANbEPaBAOQZZx8hZGFPitdaELgSXqAwDmmmB04p0P
hCqQBvO7/RrfEphYFnJ+mjkm4HdtKH7uRiYv+QKjpCSofNUUiVufrzljkzStj8YWPOZx7uYZ3Pt9
6zoVxfaT0QlvhZBypPXB9AvcprFuQVdI0CbPafTMDyScVAKXK3gp/N2kou0/LjK1xxKRyNpMI5/J
s8ZUxEh3N6SaPUTMBtlbFt62nnGUR8BSPx6xNpjHft65N3D8MnyNwUoaxiF5jyZmli3Ye9euPJpk
tpr8tzkhm+mqOfWrnh6YC6wOo36VeNLL29tZhHPG+XzhbVqj1t1o6Lflpaef8P8e1nfLueBAXAos
hvJ+1/D8hFZis7N+I9kOsK/ts4QlDxXnwXUACHo6nS6+ediDinAvxlSRJVkBDnh9x2UupT/wmWpV
LOvKTfv4/9ccTpiF/6+Z4K7s16m58iG1nr5tayTHj9eq+xtq/XVgokWOI/AvlPHYa1M+GGLEPO4h
y0Ld4Ypo9LmENFgAY7KRnFxujX+grSfz+tJiiULvhK5xcL+H+pukbgvy7hF7sUZzC4mKlaaJgcja
dZXxPUVudBbevACchjTnaH838vqO7f6vn9N2WDAMjViYQcb2OjteHH0io1avNJO6LN0u5Z/BxGiJ
L6PDB3PPEi8+iFiIF6zYSU1kD1C6XQBPlzym0BztEtUx1Hvopmgz7F9Sg7qqTHkITBUH4aaMsXpR
qyrpvoTQYUKbQCZfpzL8DkJrw77hFAFw+Fa3ZCQ7PT2FWAkUzezubjPh40kzSjaKAFfkZbN2qm0U
Gr8IXg1PHQdLcesTh3D0uJbsj1GGdYHMlV6KNx+rNn5LpBafB4oB+0weRGlJwsm/lQmAiIK3GxBS
XR7FMD7djS36sPeCSDUIZAmb26Afq97fmRdVbftrJOiSwPiHkKp2jTS8cZK3LLO2Vuwx3RS6WJ0R
JsvHNqt1lkDqJdrFsDHWZHN3UH/jQJgkhCjAgvo/4bP1fgs3e+8Vww806JoJhsfT/89GDrydvY8A
fj2iFIprpUv1NoMDolCWe7AHLlaRFGsf5COLhW3qKDrSl5iAlYiUVbEYCERth1B68+Xx9aULxMe8
4GV8KTUJvI4s/mlTXrhrbkA8cQpPpg4ZHxIY1xrc47rdyP19k3MGsLLpSVxFY3i3J8Moq51yq1VG
IGp3+5ELe+7e3VWSgTu9ws1bLvjDItgxgbNEFG+yiv7cykZXb/3gSTi2bZOS8ywKS9qjwA8BHyHj
G0DULxEBtFuYIHFIh5Xk0jPSn9lbO7Xur07oGHzwXeBE9MoGBhnxN7Zhn+976V7BPpWuuSh8cfFE
Yr6DmL0pCduDPGNbDXTER1+leirJP9ZJp9j9DGkmcgI+NWueCs/cGj1Js2nt62xOyJEnGNmuKien
FojwXD4CFBPPrIozMwEFwv0eUV/lsvjQB8VrYEXwZVkHOLYGKyNntf+2mYgGPCIgliMaokIz7ELC
Kbh7Cu6yvOiPyh85SBt7XFf5IFzKkVRbFGayIF4BLb0hnIfZYXHfOU1RqGguCNRvXzDqmp3a3Yn3
2IN6Q3PgLKG7B/UBs6kVhIZJkNA1JeoiUCO/w3uKdR6tB3LDMP2aU1Pl4F8fGLovULMF2Qq3gG6o
tPQbnC9DMTc+fQDwWACPQoQwTXLAZzGcAvGtDgBNYQvCcnx0QIChoTDWszGFWZ2cQzXJvG/gw6wz
g8zGiEeDOrSGHNoitYW+k1lx7FrW8yRPfPdpz2vdKD6T9da0d3Gfy40tWeV3ZllxKAMEAhbJl1Y2
1vYJmWWU/nFz6JSA7Fq/IRYHe/9ANTyTOrAENui5qESRYZ1YYxOY7v1GH8c3kFqb1cflDhFdehHa
SPxCWJLMEmtoNRbICkuqMyYeXf6fE4oRp2GVvgJcXVyfbJvpcPLdJzNOWFxv4Ku5UhsELGBiTviq
OlPzz39UDDndJeyQdx2tSgkrVQ8cNV7iN2Zvvr8239TxwVEr1QCj+BwQ1l0HB4VCFyY1125db7s8
gc8lLMekkOpse62RVtMVHoaRcySsYqcb6FqPFxOPkkouDbgKnq2sK1neOh9LD+6LQ5r23ji/qyvW
HoiyQCwIr+8RfRRBu6dYdh3khE/ePDS2UnL+Xr9/zUMW/+QF/bs/saVJNs/Vj6oJxUlM/X/sbD8W
3GL/dQM/VahC/GkUbb2R47Bnq+8PdReb7cRecV3fE+ijFAKwt8ZWswVRSHbPSsdbwoCX7QWMSJCI
2dWJCTUtjAebp2jWLP3ZU9ZRkjpDemB51DOaVGz6NpjsBE+NQrxMQP0HZirpBKny3egZau/rijG3
rEVHGnb9FO7TIqMv81FsBJ+YW660fzOhVFBwT1emw0wNsDkFlBr52iNhovsUm3YNqGcrqjxB3S1Y
1g16hsPoEeOqAMzANwkTCT0/Xo8L852PVF4J99c9LQCSxqMLdndR7GcMMGFqCw/cgf8hgHZ4fC3F
8WmNzcdYZfuRJy0DXbQVHA1HJ/X9ejBmI95DeGlQqJcLKUYI1YL2H3wcey1XzY9uQgR+q1TVbI59
uyvUIcu+MHcqo9ejJRNuL/WnWv0bZ9ktwIQesdJTYX/KxkrzNZJRXp+x0A08D94pbcESeuoVbu7z
sm470JmLNx5n0IxyD5yfYQrGBA3ImSg29PMd7ghRArbCyHRupup8NqWHxvODbHby8dSpI1vT5JP6
AxGE/4qPMCSJtwaoVoJEmNXMN202RibkW6HJ88GFD0L0Saf4Il94KSAtPB8aU1RTZP3QJXQ1d6Dz
/fzYS12HtxvBjYcyclkndBWYaM2ZOxahUJe3uTG3DTKirg6QrQfY3NYFvXUrBV+4YHo1BF2/Q9oz
0z5wQe0Ad5Kc+s+mMResyrEV6GuYw0uDc1rUsTlx+0XpV4KL38sw9GPRQf4C8EWUmh2/tid5o31d
aSlkIL8hmDRqrI04xrF8yGkciS9NK8FlJYg+819vIchRu0ZxS0Xj1BY7SZG4swBUybfXh7HXOJLD
iT+IlvDn9GYGe8OooBBQZeb7p14Xlwyef70eJJBOnujKD9yRwbhUvaYM4EabGGQvr+qvOgBp0Zk8
SgxVfgK8tUKEBwE5di4+qLWEkFo7sazend8QDuUUOzGEovV3PRyPTPPdIQbtcNy92pb+2qlwWQH5
cOMo7jeJU3DdA9D7KYpT/F/lrXmJB0RWRUaFrTwKxoE35h8wcLcNQyawZjW6l6TUuDxHdhkGB/Fv
2aeaArVRU60iWJgFfVDlIZfrbxVIALYUTxBOBJOqCZEdPIA8Zq9lLx2ohLmGFkjLcriXnR1Dir4G
cTJXrAdhCAeqMhGDWJnOEZWoVMROcnkly4Kb2e0uJzFsf4egGRguI+vk11nXlVdR6ZlL0RxRER37
6j9TrMw12HYXNvHZ70qW+Vle6NKf+oBrY5Spz3lMw62kOfc+kfdjoPPMGDD9OLGGbC7nDEal8mzv
NJBrW8e5kqXJtv0RlH7j0l5MdcYQ6UVh+b6/z47d1pccps1RF0isRGpy8emcMp3eU0SwPISTO5Nj
Yy0IuMxqGsY/bsLN9sn63G3nSkjf1gmc/8rKucrxa/gJNCgSnluKD+EFGZOWFBeYVDbcrex8kn14
UHh0HjadbYJTf7JfQgqKAflO8YuNu2qW3R904gOd9FsbcHZsQA+RlJmTbBkrwjjAmwrHnTOpzp3M
5JIP87bN+qBJM51S4Kac0PoHJdnpnAL1xyMF/g15+0tG7CilYL7jQR664Hl4OYcBMtUc0EBbxK84
LTjy68XCy0HrfOPRTqb8+IjVMfo46X1babr6vNVRgxgfoD8oI+22NKABZdGxKYCDBe1emwMZgLwD
dGDARzEpWjsnn/RNc7bAQwts4E0t1MihNDxwP5Khs8APL+juIYTWrvPTQYMV9R/itb5IsZvxxWCv
/WbryWhvOG7FOn0EYnilTlQMFLy1QhWtI+5rmntR9LZUOlDBP+FhFeMOgICUP9t/Yt6vK6v/gp9n
yWmlqRYYr3g1OEDp1DwCTyzRmSALNHseyMkAcHu5hH5cqhiCVR2WKYBIKyWjjo9uvjIVR8oUHFMg
eUuy2hcWQe/+/GRBg0U15wB3rZggVEWkdZbo98NEUaCqQldFx3oHR6JnPDMXSM+ldYjtQesUOU7i
JMIPJkZNb6rdQG4ypJw9PLIL0XiRFL3UyuDkRg738Fcj8oq6YinWpaZFBvjSUloDY1P7FYXo3ds8
cYwipMu1aoDF3QY7I/FLJgHNhlnnLmRiZZs0yU26ikTTY638ZotZcl/yqjLDo71aCAUA8n7xPTGz
DilNhNALFTWNXmeE/FCHYktHn4mop3NrYe1nz1qUJAJpo8f4hCeKj+qB29OG0IroNtQMBirJpBcy
J/qDSiQ7gRTJXiZ8SkfaPSRVjxcMD9zf1ogPd3h4A5lyGK3UT3k63JISxwE+ivMvZLJ7h7ZbQtcE
UATW6roDXbBUbMYhJXZ5RGXhjIlVTHMQVufliMlvG1Lw2Rpi8ZUBoFvCywoHPljLHj86HFtNB5xg
c/Z/mQ8SXN3muIg63nkqkruWTgWMKqpvvnQcRwuXtpjKEAjYG7as/4KFFkrMR0iP8fqXWarAZLQ+
3QVcpooqFatuvDm5oFLGOtAqYjobHjd91KejD6jg8T+W1oTkNmAtPzwm/CgKaDMv1JIEz1LTzBhU
ELCM7YeiaxkCzVQ1QnZbPbbJ16zOh/c5G+HWa0Cg8ncWnxi/zMs9VXjMTsZga5+y4HeQSXd3jwyd
SqBqKpHkyIfavnx370xCiRq+Zszvod6wkPc2typPUWU2kxVjCYARqzB80Gi2QfDVa64BseI1U2tY
9gxXT2w3m4R83KCuxisQa7IwzODVEIEvAZEBjVGXDP7mqwDPoWuZkzb9WDTSUMkeGrPjW6eIJe+G
DhG97+JFtS9sNZ0HtKtEeIr4zPHOtlIwwohzOKeqUCS8YACWptfGXbWgy3joE+OyqH5kbrxkjfuI
ejN+pPSI1h4/zHayB+8tY0YII3t2F1Bn7pMirEONBAubL8hBGIG6HvKd8dBJqLiq1FmuEXhP7wjs
ShbKaCORmJ5n2RQOUvsPEuqQRHWdWLw1G5B1n3i8w1MowkHNQnebiEYhdFySYbzUU2a0BMTEZjjU
9GYieB8cX9Ki6dfvwnwwc14+PlY2kvzy3YorG9ArCxffSU8DwxPeE3PzpGd/ZjFtQIxB+BXcp9uu
HH6lH6cv2Wj2SbRsmkvUXDGDJ9qMk2Ad8whAXioG2D7UMYVmARmadBw673H/wV0UAMZd4n5Aqtsd
LVP2PjzLt+1uGCZm/A04JBBF1VSYCOWXXlYtq2qkwCP7GHF+nW4r8Gm6WqcMpd5ZS8oGtiY/xiD3
BVlDC/XGPmcrdhPz3AOo0PO5IgwoSWh0btpz6nJkyv9SEH/Ofr8g8Wxhs1y4O4IWmrNCmNOQ5WOT
NZecZGaZKfVz38JopmfRQEMAGCTy5OArPyE1JceLg80iEtbf5N6MkjeArw2E1ZTDOOV447Ar8zvE
nP6mXwVAZRVLorOAiX95z8OWMmmxI/3Yicub3N3Dwd6uXqpyoZX4HxHOGO5wpuBWiKVQYmEJZbKe
iR/UOU1AszGjLprttMdu7G7PZm2cQpkdXZ6SfJKyuk6fGtfBVfdK/72yzg9iKEpkRQq/NoAlMgHh
kT35LeZ4pPC8ak5g6rcLQK4bNXIDj/ApKqIqwqSjvtn/7p8ygDp12NbdZRuURvIG+IjG1ln/tP8L
WKmpydb1c7lxeAUEMGzIj1Npl3pGr1Wt8BOkxhm4hn7NKcBsVyO8amFo+qDreJ4Xgr/WyIlzelRr
Yjz11bHtyN3tABq4tk2gBcVwZjWKUMqg+Lnm+b/SGUTrUna4sMODP9lM1At3gp32IB5yUPfFZCHf
pXCoOgeWigFFp71feGukIWryAmSF3hl/JpFuWF3SB+AKERYitC8GzatRTXa1ac/qfG73W29O3KpD
FJ/pixQ9RjwLchlacGtOsxEV8HSfJpvJHgEch7JLEAlhWNPiNVWEfDiuC27TvoJs8b2r8kLJMLwR
UCWrH7MmZ7uziouIg6SbnHx63SrfKee+jTUlxNCjemj6CAMyIu+d1R8X+R9d8Zui7GW/RZY/QMbE
XjLcEpDEkiJt981rITsYEeFEyHMguM6Ju6nIHid8SzRuEWriZRmEIJTAlNIiNLwMJugzTB3crOQl
8IBfaMRzjfCoau+PZND8cAA4s7vNHF4D0OokRek2glXyoRMl1VJLVGmx8Bu37nyNdvu1AQFjSYLt
etkuXnpS0VKHm9ZgA4jv6FmgSt2eUmSa6qrnvPMC3oNUSWtDdl2AajaxIAbvwKZgY/beH1iIkNEv
TjmzzCSq8SktUmBG72Tjfxpu7Va8SzV7CEVoXthUQ2f2wog4l1z5+1Xj+lXv4PQkEAl2xwkSxJln
lEG391BLOkFz8ytRyunEeaf0qbRxQqkLIFbClTxHPYYVF5vUJ66KAE7CRsABWa9FDyp8XMtk5zAl
bNo9Ns/XQjmFKd4k92EtfeH+ZT9RuldWeM+9sVWxeKVSntXZAA6ppscYjsGfRgSp6dGksLyHzi/s
Bwy7i1P0DdbURQM8g+Bp9+W8ADwkj/Tw+QQUXogp7ZwL2NAJyvAOr/16eTgF5Qun4OykMrEfpcJn
4WkkWtbKyL46Afr7gObVr5ukGM5mMGxU8HmBHqGBjJmPyhjCCeTeHkbQxsZZKJUo2WowikWK8shF
CTK2xNy7A3kK54cBBGi8n1gBd/qRP5i/ISxSLP/FIC+/MtUe5aSGnI4+AeAqyw2/4eLsiNpj+tkO
Ogn1Ld4k9ivVN7f+7/htAQEDEDZBODHL8IwVVYvhNTsfsKPs8RpJMMUNun5AN+FM4xOC0OZy7IrD
bUBZLmUkm1x/CggFdLCedKFp1P7Nv/B3wrItPNaJ50/z7IRomLk8I8QSC9zJaLyI9PeAAHlZ3r/r
SZ6scDe1XGNUQQJVnoXM8ivLdua9OY19yh3fZhePtbKbxtsKdShqdFf1gXRJNrQh4L3GTOaJNOTp
DfowShHtYS5OS0FuDNItNDPlDrjb4yaBRNf9k1fUQSgjjTLtpaoEqkuWmAdTZU75T0gmQKeEdRmQ
d/REs26i04OWljHjoXBbg3gVUT+pAS/51KWVMIt6TKU3/oK5N2XAxM0GL9x5sHcle4+Totk0f1UM
pJSDJNAxBvl09xwAvNDkI3rv1If8srNnYf8woVDiL/GAl6aVBgk2Olh5A4fq7NvGkTnRjwBNoR67
76+HULUBRo7ZQOtL31pyt1W6DbOaRUwPMyLEfjjOh/f/4aP2Z0D5xLUz9h1nL4bk9tLuKvhWN2eC
v/VoOzh9knxV4XPU9k6FbNki+i5AoEoRUzkmy857Bo4gHOLS7/OQbbcOVu+42q2PJJSBPt8KF0Og
8O2QpP2/q6e7A7D2tzI/deUI8EwfzhAv5v4cYEK54AqR2yfNmaz54RNgcisOpXnoPzSAmi5Jiy4w
seUpvvUtUt3cF5xBmjd4H1njGi39sQyhQ5/xvuBY2HJMWMXIJTLYgpvKYSqMHJwhi/AxnP9Z3QLR
IliidA7EvSzogBR039dzo8cF0ksFtfGYV+3P/S1fvjP1mkOzPu3XR7pWZIup+YYQq7iK4SmuYhlL
EnmOJxtLHjEWIJ2IVg1C+5bkUVOfkHbXg4BEnClv4C/tHNZWJt6h+hsD/WWW+wNSHvfujeIyxJ1H
aGSCNa6hGHhrwyPdCEMym6iGLtMfytUCK4RcpDVx4uBJFjWnYl/OQ4a/2+zNbyv+pcXIkWLRe8oO
06fRGbxHxbcMiBKDtwfs3ftrHM2ao2hMCrnDOdnWpjoKq9BPYMlreZX8FnxhtVwaIqkJkQvm3WSG
a8OKtxnDF76zPPrInP3CfNyM29okOqqlHKpUaEFkzRlaInutn/9EbtmcunIPVSHv2wrPgK9EbXyq
vDFW4nPn2G8q0NKET+jEWcTOfZhlcSR3MVqAAc8Eyn315NtKWhy6C8cdBOi1PNJruNo/R6+crqw0
U2R5NmesHfliHs7RN/ixyEvnevb2pZvwg01GfKMB9salRlBuPM1gnvkXNXXUEG1N3QoyLDgQW9Uy
qFwWVVNwl4tSF1bm4asF/r3tMU9AAYIos9ioMRHi4aSxnBOUm+vznfIp+f972/MxZenx6R8J+S5t
jN3icf8ZUTPX+zVK+QvPTZT1Z4ykXOCk3VjtQyHx/3ba/vOuftcVJl7asj57uzOKZ+y6RLoGADkq
PZsPM9L0XluYwd6zYAWZDz+LHeZgo5+aTPuDQ0OrsZjMV9LfjsEnoHLQe1NFOf8jSq/RAthRjbEL
vlvJZOxaTM0B812GC1dvy70EC3ANFCa1p1i9qZZbsUl2DG2SF+Q0P8s9PU+Yg6TKXx+iBSFoiVc1
7aO1HcaJlBuWPsN4UfqiIxXfmss3KXOd1Ev+U+VxTIx0+SAV7QsFrNz1xcXgK3r/YYffvSTfwhbg
HiBD7FlLBC1/HndfD0yqpu40/OMyjCclh1KjlssFnip/U0AcO4aYcWgMr4yr9p/LXO2/PyaC6s4K
246JXCxMfl06I48Pj6ylR4AfEc6ypfhm2Wb5gu1Dyp/5yNJjWSA4hDog/vJdelIo0Wu0vGLLuwLs
HbXG4yph/T4B6KoB8muzBPRiqWHxixRXcsRJTgeJYjWyBCsZrPrl4LAWoYbVDVGvIK1ZnnxM3bYk
CgznsbVv8CeANMXSCperCepOFVg39YQ3gwIc+V3fdyhyzeVKqqyAXNwANyMuHPv8sIUKXGzZUN7Q
v55m9YKKN/lMd/CixzHkc8NBSjIsdk3YGcSPuZGMU6Vh0+6c5RSgjNeXr/Um/3oIpHHIePt6oLys
Z0+cVcM3BdNznioVMDL8uN2UNNCgL+KTMeVk+be4GSmos3o+c+gonMuxHwGLDxQQk6/eUhUVCgVv
JNepm1O87ulOjRPtSJpmTVOlxCj0FU5c5eb31dWiNUqbldnxjj95VywbKMb1ixDVFOtl+Jx0ciU6
QGO0OogJ9oGfSw7snkftcNPGciuyqkzZXzqjPWhVf/7exsUFK+sTCse/lV2qEOgpLkrZjFA8rFY7
pJ0p0KWR5f5EGq5KorIAuRhce1hTp4bHOTSwyYunl5fOArBLMZ+UEv4L/LJ8aouAZvyC2zXG0FMq
+wrWT2HG/AFuVLR6PzyW01kqKAIenBFqjgq27me0C0CoX93Yh8ZD6IE1fhdkfzPiUuw1DHnNpqEg
dospkG+6eYM/rqt/40hO0028egQ76/QNdv6qAl9FTTRTTArX1mHhm6sROHC4sJLZ0e3+wbqsLYe+
R2YY5uAcdBqJ9jEXpR0XJe7GNrUTzhWr0LCFJV2pfxgKxI1a/iwcbkplDaNO42tpp7RhexYW4wAV
mw5nVhOMKgK521XK5gLopBacJ8kt+wKKAIBPx0gkoUF2Xvczn7yRXrOOAM+PA6O7VBdPrSxJjklS
cTMbv4trZ9YCFsDEKa1NZ9JUpqVHOt4V6pTOEgJG/K9SyOBkvqOlYkwSSt3Phfjn7SAjrGZkswcl
0enWzIcPl1PUWmnesZZ7DZHJdDDGbgWPE5pw5DdypeUq0rC0RgTtd8CWE2QqLU8sK2CHLH0/sasK
riMsChZfTuYlZ/NxfNIL/OvK9RFlkBw7UZ/Ti7HWHnhDGKNAGMVkv+SAq3xlbV7CLVNIvugAVrLj
uFEOAIi3/n3xmhku197aprimHrJeOuwravlUi7x1jbNDgV8O3W7X33pMUM1DPvI2SwSYdEK/j1jb
bUWeZc77HLcw/AlV1UEe1wTD37N85KyT+rtCNcx/nh+VlyeXfY20bDM8kwbknIWO7OrbavBb+t4/
jq0rc7Z+MgNxDelbKOsyyuFfhdfXprg3GyU7VD7nDhvsdZSP/dgwvjOSnG9bRa/GXNOWyLjXjWgS
Pedybov+gsNkkLxSXezxlzfpPaijgzax7NqRcDXUBbTXmHoXVnRbi+y+E6rUVA4W2+x9pMMBSobP
AEsB5+HTgvOkNwEIWiuuMBDSHmKtQwiccjeCwG3nyrgWIqWcG+DG7rdLD/m4UoQWzRHHsGG3bhaM
mFGrIo528l/2zy9fk+PRsEspBn9eeEbzOWv9ig5GOXcMOLeqLM/Kat7Xsg7FwI84ZjSfDNuL25eB
RIpCdlJpeGdiOjFNFG9yojRX4eq3h88zaX28sRLQmByD3UPgLwE6dpvCcqX2Fdtxjo2/eJmWpzt4
4OXvVc2sfQ3awRozhcCL6Ixfc78SyBCCcDiNbRmZr2kHvf8Tms5bdyaxT7+cw7pjjkW1BRyqSy/Z
DInqnjnOkjTmP55NJ8yUE7fh3Ef7Xejws9fTIfKo34G4WYkqkleeLCSJ5LDwhXVrX0ZI6pIphBCf
ya0gMoSXcJCfgm3R07tyLDG2yfrrwvvFw7XyvUDZfean4tkK/DnKOci3ubcgvTku5wRyVH36RCi2
/qr/LKF0qHIYg76szxAcMBBrxKbAMuu1E/PEt0PgiQsYrTsInsWOQ6BkBru3FzbPV54m2jwMQse/
O/42zoPz19Xagk54mH1irmDCmPrvOrchD6RH4Jgt1iH9of+t1dtFl9x16Ib5W55ySo26X627QjHz
yWSVi+lQcQK/X3Z9L2qgv45VLr7OCn4nCsmGL9M/R0gFZcyod5Zx2mEV4MdjLJJ82I827eapPP/O
S0DrlrXkKKse7N1LrF0oQPODUbqCq5otDfp1vlyO/QkFjBRR9tqNHjJT8sIYx1IG66jkQK/RhY1u
j7w4TgFASabJRvBwwI/5iAyc2koBr6KckhZ7OUdasskAIWgUUr4DhqBbq4evRweAhHVVXDbLo7n6
Pmb4XrBLitPcLX230wlr8gXbBNPOpPT3Ud2zSyLFIKC5tGjT79AGmIpfqnjsgBNEiLCrLjvNklc+
qfUrE4zJ0khjRzr1kVnGjoBC/jqDcLl4V5yx+FO10hsshujdvnxJRBogQCvwybZlEbjDjmazHuz/
v4mN+W82KL+f/lRYXFJHc5IDxFQzVGhRsjmRiMdBRL+6SnacTIJ3/gUqxu17hPHqxB9kH/R4rxRo
924+PvEtLofz1hQZ5lZTklva/tExBkXUsFpjfTElCK+zskttzhPoPkUnQDcMSDXVeHQDx03GXPal
E8QMZzzS59Ej2vYEHI0yOra8eGzmGHq2tOiQYWvsHEpVmdoP1ELpsB/Mn+QxZ5St+V/CWbIEjSRN
bi3LgpynSwSc8PtuR0pNCyzA9gxllslN52feZJKR9aXADMBKLVIq6oAmMhJmXRuENPnOP4L1kTB0
+/7hco31aoZx5Xz2FRYrX5SqsvjPjDIwhsDVYoZvNIaN7vYyyRm8kje3ehPmfKgseGBx862zpvt9
BlblvRsCRSoMvKJv0C1tNYqMiSZYj7R9LuEx3xCKmeDv/YfBM20DQT1h05ot3fFdrFUivBv8GvnW
HSlq9CTrnErOLn51140xfjmqZiTcCL2Hfxs0HXFDzdmqgzZNVTeuJtxRUEBZOvx8BLtNHJqNINQH
sXOLvx7Mc3XBnJmR5Xtug18YAFSuNBJEqiooy7NLwDgL70/8HaQXeIJH0TLDr9aUqQLSeudO3wo9
GINngGxPEv7JPucjhkf+hpf7bX68Ebb+omVu2j+ash2ULjx9EFzH0SPh8YE6wbnc/kFwCZoxccDj
VEx82tPKgmZU5hkLEV8rS8eca3+QGw8BR/pmRZBoVuNwj5N72aIcvmqUYffD4VQ6E3+QEGeIB+wB
ynk9vA9WUExcAcR0Lm+OAAsDrwRpmZD83EXJPbllGe48BB5fVzziP78RINoZCfgBPltdHESgltI4
vTKLI30rnpyF0bLnO4xczINdy+JVd9P1ozOuRNYAUL9RZNX+SJ9JYrajMboKKK7d/SnhRkjV0rXg
uubO3UYSEIxPC5ZImki/19ALb2t5TkL3lC0fmihXH6GYaIHhhNeuOoXQO6tQCmVNWhC307ZZTXR9
7rYlYMd8djcIQC4W92VmKGc9c4DcK/RDusTKXtQjYHqwnEuaUGuUCdY9ED7A71215OsjNGxQ228G
jFcdcM0wqyr4GUcDOK8WrYbvrGqBZZwosgZJEtyKk7FYrb6zvdqHN0y5YPDtRgr/8CVfn6xGkOvg
k6TaPQYl4JBP2fOgF18J2y9RPDTR1DZj7xwAeGv3SjuKffYjV3hDwfQQktFuk60X3ewzoMN2x7vW
LdEQYN7MvHpG3745q8iEm1s9Zpj9AztiEC1qJPs3aftpDNNPipuC1hOkMs2fFrkiZin+03uxQYlh
OvgVFRCntkLKAibVQ2Tntyr9qcs6+zAjlnknSGkh5/0Iy15GhiRofwJhnKiaMbW6ZW5JRMoVRaot
fn0GBmSxOL10K13MIdq4Ny1WFHRPSMRgfZFqnmT35kJhCWflJV/lXVCShVcqO+Ge65Srl6j25Wqw
pBwbnS/g7pcSFVO2NaUYgp6zKblyGyCXZ51Hqcmv0cHQRBmEBDByH7S0wkpMk1vZFQLihl0gp1Kg
uKTZI0K5GFA+st/LJHbUn7Cso6tg64h1D3uhOqj4FdWPwDDZuO2hEcxSg1JLlhDnRUjRbGN405Jv
oPMU+MZgYrBXglKpbgAPQ/bC2AJOqCn8LCYhXJ2aBr4W1zrGCSfvSJpFFCztiVQjX5dhBccdy6Sm
ySFKHeOrUwMQiTtPNd5caxd3mKeMXKtGXifcZTvJ9hv0NuRr8QatcebprlIUUxt0dbXTx8yrTvRW
ALCKibrNV+BPIqtIv6AbUCx1jirvteBiYQ5K6kq6j2SK5RrfsEYorN0clIwNl9mBi6uejTEaRTvh
+4pFD4olrH5D7hZfuj0MUJ/2MMSWFOK+1pdUlkuUssGXBGX6S5KM4yjPoeqWwVePqinLIdvdyjsE
D0UAotFGjIZfZaE0de4BP1k91/v3cdwLMDoy8XmQ80fQqUPFIEGaB+yYeudxNo93VAD9SdUcMpNg
/if1cSjlXx0nsrKa4knDN+zxc51i/Gi0rtm+MwgoQplQyd2+WuOCp3BhdkJerQf8zQoFo8CDS7+K
YA2BUrW/fJxaQphmk/kS+0GbenbTtMm9eR8+eVzJJ4qyOgSryzkBXH/ZUpp8fjmuGrmrXoEJRREF
P7ZbmFzJBiPgBn040r0vIxOO1dbWbZxbmcdow/fhRIs8WN1u46aPh9z5zbQZhQEwDBp8JU11kuVN
QHvGCqDa8TA8AT8gByF3j0UVI1Eq7DNjJrTQMlpe966u92RkriRfXnbmLAvDdTeYmt2lm2Gjl1Rt
140NzzfyquW1akUJYDPhVrRyB9yxgJPhpQjBI5hd0AzfBO4y8IXVEvmHqmcPRgEsJhAEWHyqIUFz
fT6E1iITk9V1VBcrhwHRFLQM75v4dwiG9qFQeVqzuw6naU2L73XWvMcCDEcf1bEmblV1fVHevRGM
fmBWpkLMT45C+OBO+MhHbluBuWOVuRtJ2mHXghyK2xQfnn4GstkWlt55LnNuE4Wa2n/1ApzmoFci
JGEjRpw/sMvql0zvLSbEKVyDyWGT63BOYE9Aad0ReAgO74/UImUGTZ85yGKoYW91h+5UHNoydYqB
fuA8iBBK6hVXq+xCIs9sGyNtSStCb4Rp53k6UhgaHpF2imjgPiOKIlFV9/G6N89UDKVlUToVWDSG
YIpfmoqlEzpNus69p/NjWcmej7wbxso072bg4Zpg8YzktToOg9jiBOb8JKfZbj2dO89pqw/jftZR
Tup2jiAIo4JIA5J01Gkce4WLz17BrUdrbTEUQqFTqEmL4dhzwsfzZmuyQ0qjcK+T9zS+1BoPTF+T
eT3y/CgiBiygQjB34qVHb5AzDKifyEHdp3RanQq8fywxigVHOwnXhOvRZbKFisbo3wW6sAB/xXKW
dKxFg31Va0CzB8Qae3XoBt3oB6Hr34mqB0Ht+IPZqZitKje5pZr0F4JQDOyYfeUhVLFqBPREU5au
A0oBAb5BPRnHEdXW2T3eVJRPvL1qcPIMyyFg9fhi19q6U78+qPTDMtcmxamjld6Nu3/OzZBPb/bw
1kfD1GMJSAZea9xPuLmE00yPBglskXv0wc6ZttReBVKvfmsoyUkmVA/oC/mAK8I5QIJ5eX+XNfv5
COWuoHhSQXUSFNZLxgAd/cH2sALVMlJ7DQF6GfSERSzNFtsbOfOh7kMbP846nqYBk4ABzibGCeGU
0iouq41a0k750x/984lROTPlUCgRfpjxzte74Iw5F7Aye67imQZuysyjmtAfWk5K5kdzIFmUImY1
UQDGTVtS0gTr2zojxi1RcWlitfIiajvoc93/M10d+5/5LZ7VkskgxkttQE4nYY6lg3L+HhBDaFkH
pZqoX4ZlXKQ3j0OvsklDn4Eqavs2+AAMn2jtF828tlQJPm6ERgBd03xSoA8HzJTr/yjzni55fWyW
xYgp372PqVP9Eoz8loGOQske3ZBYRt+Cu4uZMwOSl1LyyZ9lHcVCDf9ryFWUBgELmG+LIim1RUSx
Etn4p0Ms7uwGswsVmMJx9sZOjCAqKzEbJm/RIcyosuOkNcn+BL9CWvS34zNB0qnZsYkpk1Ovv5Yl
MOYshJGX+II+Ae6jVA4O4NCJYletaPaCASobQCqE5eOWItRBMck4Ppp4L2mwXzWyt4NcfyeBna3u
9dWTG2VkZtTHyYJDMXOlxlIvBcDRAl5r0lP3RcxT9+Kp+L0U7gSA3GSBF9xHUYfean7j6wvKOHLx
nk2g5JA9oQQ5TPwI/xINqqLm2rP5RoiksJf2SugjHDPbiWlZM0j++nXRpmmZOxXu8ENYOoJR9kdk
WXjNNn+F/nMmPlyUOBKzc2a0PF53W1mrhpntfPUT7xcdcc8OpwJRK32H8S85kEZFYY/VtSWUqCQm
9pbQmagifTey0LL46v5M5faq7/A0dv/ZaOVPfDW1NGp6TomoSaHq5BRop/U0OQ8DBYFfI5L1uGYu
2I2aQrAmdAnShUs1f7QTOWqnyKmNHCYj2zqUBjxMDrPa2d5Oa8ac8tGXEmwiK1bbCSEJHVoAyuWA
OVASXh/tDtT2rAEW2RSTmgedPDppooWi7W0BB3xjzQgz5tZ2kQpDB5LL+bZ8m3qU/IRnQKXCjw1y
oQjk4ZoYJM5dUdMEhXaY/uGQhB50m2Y4vGICCMdlZ1jjRE29XgfviShgZ0ii23dP0+UmiTYkSdmW
+csObdxfbSVW+ZcVbdqmJKMRqAhxfbweoc1W75cGOXZzZO3PZcgiQvs8863PNinu4tXa+FHIl+sX
c8ut/kl4bZUCUpjT2aim2oVzrib9RYthSefZFRPncHoRxsakaxdQzI35jTiDrO1yqB9dnMR26f1E
7R46fLT+IU7gVuQebSsnm15h7CBE7GitTf7a2Wd4lfwFF96D2gxlJIS+K8EQGt0zAMsBe586A5FO
kr/oVhZB19yWgnwuvHS8E+VuXidoV+ged7CGaD8dB0BR/yfGTehMCrql2KqgyD/DDF0GOqTcsEG/
3wiO4j86SIAYVQC6D0Q9u56s8MNK4nUaM0qFRl8G6bP2Yf84gg0CQHtxjJmrPS5yJqEQXSLK/+RU
Y46+0Y9XsORLoghM3ZDnLkL7q0zWzLvOImM9LOuhVcHx+fl22Tw95Do3N1qJxFc3pY1HhfpbhkMv
HwgxMX3RSkbmTfMjHcDzFbVu5cymnUSfxpxINXTnBiErIXfGENwB235wgIfn7JQQy8u981Rg5f6w
SUeOpCtuq8QtaQ/B1x+ZN/pmninpCK+PZFIkZUgjoBfMvn3/EmdWIetcVU+CAayqsYnfeengCwkb
Q0yoPTgv9IpPPJpZDyhW1MhLIj2dcCut8LtKcoVoCfG1ADkvt6GLJu61HrXhoSv8EIHy0NXwfDDT
FlCHFTEh8jtZHx/TwyU/iMRauLZRxuHQvleSlfus6h/i7aPl7PsadjvTIVv7xCN6aXZAxTVDg8NJ
wHmTMNrf89yySt2vwR+bBZixL+lAp3EctrCMszwwGamZdvUahpzt2uWrqtPm75zRSPk+hbUOPZbl
EopqNiSoOybEsm0KyTe/xhsxOVZPN+ftFIhn114LTsjUZYDFoUBxRhFqLFjL26afoFK65iRUBE9n
Wgi7+iEzH7Ar8vn5X+MaoncF18Y67sk4E+NsY0tKwkHsJCIC7q8oDWrIpI+mpUGmhc6HL4gq+3A4
wMlTA1PtdDj9rhB2Dx5qHew/oU54BNIhOmEn9XU6xKuLahA+8aL4rpcWEKMj7eQUu9g27fV074Dv
9FlDO99z2gCMZK0XW1U4JQbeSdXDzSTE83EsA0jjLodkelx045vujrhcbfq3FLkzU0gRlLE7HGcK
n2XOwPkRvFRc/TWrlul15CB1NT64F7MDbhk+MytHzXxSZRnqaS6w1/kF4Pfd9ZDXmYl/2dzJBb6j
3nCh8B2WQIgD1SH/mYB0AcdotsVj+hsU8Gk9vMEDa4zAuoR+WWzf4xMALJRy6g8+jeDrlHWTV44v
/wi0RE5qrVy8LXsG9qWficyY2UFiZ74tsevA3g+71UIu3THm28X4yQcxW8I0J8YABxPebHs3MSx4
qsiSeT6NjznbFHy8sD9FJxx+tCk3b6DfXKYVb9JfOB+DFKH4HkDeN3A7pCYuNef0pJRJwa8aNbp8
Smi6ozWoRiuCiuxcfKxbcGMIfU2LLeooVkWZoyQ7NpIlzzscehfQwqqMuo01VnFRUugoja8UiWrM
LS97WERraUvgXYptaAaVGGPKdZ9Bqt0hSdjnPX9jnz/PpS1MMoidENaESTmaKceXLnj91YtqF3s6
xyEoemHoaKqEkgqKbKLTL2+zndcMaHiCnpJOFthU5vjbOJ9APAzE6SVQxvzyBvM6zahE2iTr2dVs
SDet7CPp9zM45/bYA8Th0NVcYMAGeAlf3KVf/a3xH/EIbpFSaZXY04QQlCmrHmAeA+AvimLBcFFR
2HdgSEcUk9x8g81XyUwQDPGAb2ydteHRwCM9oBidlm/oRgykZesT73limi5kwrMX22EuvIJ66D0b
X9OcuUCA1yE3UHZoIbPA30IUF7fx121l1eRCmTuh
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16560)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztlHgsA7XTu3se9+qgRV127brGn1J+SpZIMueDb+AV872JX
nOXB120GyVLNbjkhWTWXGQdsLOXfaXs2I36xZVRiwzpAgBzfQJrI9hG2kq7bh9WznJ3xEF5DLexY
Cq15Vdb5gm0qDaFFZVGzlV0qAsnNmU5TwLZdRsYlrsSd1i9jUQlzfmNsUENvXGN3CDlY8CFK3jai
INNNriIElfSpAetTkn9VmfppFFOF7wWkbrMeWuJ7l/thC50PzIkDIzK4x9CtfhJd3F2cp+VAeBKF
LrxUYaG5u5XXGRyoHikRUGoKOXXmqvmZIKvGnqo9OmemjsqjILGrPxP+3Dy+cG+LmqgRYTxy9X3z
oMfdSSQ6KvJIZvqKnopohLc6y0/oMFyP21GDeRYafr53M5KZ/f/dLwptOby/mIDvt7SkwnKGfvFl
EpHTWq8Qukwr6iDxqQsNxGo493Q+4LG/yKuSE0SND6bwyarofUfxPeW4laRQMKn7H0Tq/eaUvdP7
vXl1nkBrtRL2reVVADRjcpDm+3z/jYigRFz9ttrA1C+77PRjiowP1YG1fdzffqSmOJ2j2mFWYikv
ToyM9T8m18egCp2ghJoN4eI/VKWlDfluDP8ZTsWcngrJsn3e/GAOL8PDe92FDeVUKpkl+gr4V7Rp
2aPnAyyzEcBeVlaEkmCZITU7qdXWBM5BIqVU+5e2tVie09XfrzH5MIHwUfVaSuy2u55zP0BOF7Gu
CUEPlLKnR9X1WrHVcPnd6fkPfFulzaTs2HuDJi/KrTvbj7wCFie6P4/WolNX6kPWjcz9aQ+wnwhS
Cl7c1ftfyzJMNbweg5RPfaq3a88McLpzC6etEqO31+rgbz/dfhINoJkCiNixX7xIp4n8lci7GXoM
doKmP5XLBXmP/Ef1HlFhsKHBbwP+AsT/HJKsRbeMXUWPRtcZnkpB4dP4RxWecqcBPC+ggs2Wg9XD
flCvKjr6I9RAgAyAJYDKpapS2KNmOBVR6fSfSEbVOTjDKBU6mPvbIW0B1GrxujCVwXhYhzfa2n7s
pSvvjqm7xICaDI8wL4+o4znzeARXPT/oyN++/EZb2EHhIwgPpY5/j+VTdImaOHA9M1rXQQLS5YiQ
d8fE3ICl0Dc9YPx7Gi23TU1UqiV1wx1HdnYhTuzoxdEq6NpLA258Wh+rwSu8vP7hWDb4IQs7YCmU
6c1ehdkx/jvYYfcnI/kqhIpv07AlgCablcW/IVHSudlBYFvHKGNJQlgPw9VF3ckGkh8Nga9O9I9d
WGpkXkOB7qPMCwxtST5z9waEGTMzhngUhfVQG3HBNTQ2/Wat/S/5ryngqBFCJaIgUfrzw8VYPRpx
Ma8yghJP9QRD0sXR0VB21eJw+4iLEg1o1b5xf9NUkYGOZOEZKU4Stu4K+cfuS7iTeocaFB1jsdNn
ntMoV0FAqRuj1lOxDG+YJLiVc5qi1sBf6RQL2iPcSOOeEQ+PD/uFwCj6180hC84peYYWAyHN1Frg
05/zwXh2E591TYe4C0h0dT+Aos4yWciHzN20jWOxXMzIS3G1qwF0EGqAijrnXGLcGocwxkZPDg7O
+ZIkcpsjjhwsvUCRAmpdYb12MfN1aomq3wUg8VUEjLXBfDpGSJm6LmRFOyE95KmkhVn9RTJI7dRC
jwjcf+RbuNT2kw6BbtbyviR0PCqcqqTHTP/U7tvsE06ymyUlA0+8IJ3mEXtUVLHrlnKrg8hrwXl2
4THwUppB9JDYFgpLPAXCkF4P+9MlHt8xmiKzjjY/jg4X5Mak8s5L1GLzrK731k64QPGLnV7Y58fc
JJVHuV7cVknlClqd9DJbTGS2lpfnm3E5Xx2a9tbuW2oKicS7VLIMnVFCOqwczmsysYtdtNgGlee5
1fK25W2QAG1uuOeASXuQ2ZNt0bEInni+G7PBrvOi/pIjashgqTgNL3SHHmA/XFMZnHX6netOZm3e
BlfRhSx0HBjP/WZtK5NmOcyW9rMppg466DDbqoPfn9ht2ThmNdE55qlP9RBkGuq3LmORr9QPoP2r
Kez2IK03BRuNytY9tB9JWMXjpeNTFfev40Y2apCXKqghOHbvLqicXRe2RpvdFsDdFcAH3Zd2cOx1
is5sPhAMvaqwmdbkvhYB2IccISAzJCjDSLxf9u2Ohfbk1LkOVNmX/lsYcr4M5bchScDMMvbxps9A
/nKuGAdf59tzE0AtDeG/JB6q9/Xatq9vDckMhMnW79Nj2YM+eA4nboeZi2q2usxzOCsHZCPMfnmQ
JdiYT4tcLjLpV/MAsswTqI2YwYG7Wsr4TfTd62xl1K6gTKPFxD0Bxeh/7gMUL+s04w2ABMxYeOUS
soGkfyrtq/fWWpQisTLRSPV3UDe0a8xM5OL7koiF4kZg6J6vU2gRPDL6/9fq88Oi9w56f6BRRcy5
zn1CYRLMCbCuNo0bQ1ikRl2fwa6WE8OA23UlxdNZk2+rphNHNk/UloVCB5ZXiKdP89w0J0JyVcme
Cc0Eo26iADVldbzlUVXNikp8CU4tzrmC9jSh4NIpBU6d0qi+G69Y6KulyUxpENfSof5PXnrXrb0Q
89dsh1dr1Thsq5QZcNvSCknVagRzD5eUWy/u9tPEyziJvWGUJQOb/YSxz+I915Wlw3Gxem7EPsck
e1PONwATUS1zh0sOiUIChUN2ZysliabYb/tSsNGvzBtEp+DbZPlcoyqbJHSoP1TjXAnB/TDMobpY
yugtm5DdXSlGUrsKwBiBRcewN/Y7XznivnNsc3JPTo1vYK5Mc4DCRgFEZfIqde02lPpl2OUw54bh
699OiZk8Z8JHlBC/A3sqOSelp2MNG5GW1MrCAdQjpmlf7u1evUvOQyjx5tM4G0aaGiNS35xwXmvy
Z3hId27r4DbvS3CI56QsLSh4NsdzjHoirwkfFFUQco4kP6r6bBSb+qSdg5mYwvieiEwLTDYXGdFR
9H1KBQGXkHjNWieL8VYuheOudvT56+fW+kiYu45hauh62DQdKGeGikrGmLr6O7Cs5+vYXEzV1A+o
rsbHB+3w/DVKGDe6r51wO+1rKxqQ0Ly+zSKNFfswqm4qVO9OSIjiL8P+9WdX2WRpsnvOWOa9LUFo
NQi1p429r6FXqSXAxtJFZAgtNmAhrqBd28LyAHLvJsKdymxhpLsNGZqUP9VODIMT/jg9FeKzeDhN
K+mriXZRagg47TCbQ2xZG4/ay2CZfZ2sKH10qBP+sssi7JR0Ir2VywA0EPn9PnMhtTgQtvqypQKp
tC3vUX8ahzFNh3Rwo1+nu3wdy26gqFRexgdN/bJkXd15oB982kk1dlJgX/DPRLOnOtTMfIjnqRu7
2BJeaOK1r1bEPNmwXEsaqVzTfE4vFlLEBmqnmT4YWmW6Nicd9qmfnMC629+UyKOGD1E8xJcFqsai
KGe5AvZuNbA6toK3QaB3p/GBfA9yvQgi/U5HY2xKehgk1556cTgixJxIZpNI2uwglCpYejZIoyYw
6MJnv9EPF/8HnKQCdAU6BeocT+XCeiSTlDDbaeGtC2h/HJjGXOM6hrc7vAC/zpwnoyF7BrVFoaFr
gUbOuzQlFA7zzL7gukUB5wlipL4en88vw4fNqQVoEsXtOJt7+OwYxZGX2DVrbzXE/u+6qgVZrJE4
GQ7b/tFeHjN2MmA31MwbHpN90Bx3MkW/t/UnXttPwJLkHGqRWBEg+6k5qScLFuJU9yfxFL6Gl1Ts
wIRCystlJ0QiGF51P+e4bdezj3lGSLIsINtYaa972U88lqm3si79cpBX3PmtfG0LWfmvcwEQ5C3S
O8DvsGbXqhKhQI0hcp/q1GLivekWYvv0DUYQwl1D0pqHEU6HhXAmtkavBRzh+bBdmM4eq00j9/ey
KMDXJ/KGd1UHloG2GevD15YewMLbBrBiBbGCrKoG2MlVx4pS2l8Ed6uFi8sr8JvMm5BfOB4qMX3k
eLhMva3T55O4F6d1xJKytcNUWG3o/ioUCGqLOQbz5VEFJuO0yJNibwfl0L6Zq8nGoa1d7tAFKrf8
di+++XVql/0QR3Objt3pn44+I4/xFX0Fo/WAA4Gjx2qN2v+gBwp4PmFB8RFtRHZzYeho2dUEaoRS
iMRoCzeoLMqR3IpyV+4Ke+/YXueoKclTjREVWIZx+xOC2/8Mkzsn5exuL8xBytvXlZOlNThg1q/s
l+UTvKbilMmlpnfJWVQmVvY1ANEms1T7Fmi/iRqLt81K2quZBkn1yotrpJQoXWim5/1Xx+FbJtpc
Z5W0Lei80zbfWjkV6fJJh97rvbydPikIQMr9ggiVBXziaHiyz5znMYChR+noERf30uWQc3r6i969
l2DppBpsIOzfpUufIvlfQdviduKBkfPmBu7cwp8Z35r4PCO8d6/PVWhVy/1LrRH8cKz7XPVpdgs+
Po/s1l+Qq6117HHXkaG3erTJFyrL/cjeunpIxssncNIfUTlC0ZhoLm/orQiCQ1AUBv/z5KFlTyAo
VSYL6gRlt2mxsIMjxj76F72fc+8DYK+rp6lD4fpUG5VCVquHWtym4EXwat4n6LS25KP0AI3Pz6IV
tdpsgjz5Il7fHQ5P3NG3r4ovkDcCTh4LSwibzVal6hT0QgjhsTRTwtSyjwURaXESfpoyqtm08gS/
kHuni1hz1GYk9h00Z656w/xYEMFTzzA/nP4mvA8eqwo4IxrSOxhBURV5iLrnl7W5+6u/XyeGswma
UVjZu2CdWHnHs2DTL6MZA1dw8CcQJnRxDi0iJDV3Yw5QhBR3B6l+6opFKyHYGPchwT9kYF9WOnq+
sX6DCc7wxGppgxXmZQdKcHGDG99/GEBN3JzB1wVu9AE0+x2KFcTOKruRuetEFiZRugsWJk9CSMd/
Pqqy/1ZYooTmoIpm9FYrtCFnT9cZPY74f61YlKZkI7Exq+2450huOnNcq0DND0THHUpPYSkZ1Cqf
+l2kGlL1EFHj8yRGpSFjkx7gDHvCk1wtgb1ANbEPaBAOQZZx8hZGFPitdaELgSXqAwDmmmB04p0P
hCqQBvO7/RrfEphYFnJ+mjkm4HdtKH7uRiYv+QKjpCSofNUUiVufrzljkzStj8YWPOZx7uYZ3Pt9
6zoVxfaT0QlvhZBypPXB9AvcprFuQVdI0CbPafTMDyScVAKXK3gp/N2kou0/LjK1xxKRyNpMI5/J
s8ZUxEh3N6SaPUTMBtlbFt62nnGUR8BSPx6xNpjHft65N3D8MnyNwUoaxiF5jyZmli3Ye9euPJpk
tpr8tzkhm+mqOfWrnh6YC6wOo36VeNLL29tZhHPG+XzhbVqj1t1o6Lflpaef8P8e1nfLueBAXAos
hvJ+1/D8hFZis7N+I9kOsK/ts4QlDxXnwXUACHo6nS6+ediDinAvxlSRJVkBDnh9x2UupT/wmWpV
LOvKTfv4/9ccTpiF/6+Z4K7s16m58iG1nr5tayTHj9eq+xtq/XVgokWOI/AvlPHYa1M+GGLEPO4h
y0Ld4Ypo9LmENFgAY7KRnFxujX+grSfz+tJiiULvhK5xcL+H+pukbgvy7hF7sUZzC4mKlaaJgcja
dZXxPUVudBbevACchjTnaH838vqO7f6vn9N2WDAMjViYQcb2OjteHH0io1avNJO6LN0u5Z/BxGiJ
L6PDB3PPEi8+iFiIF6zYSU1kD1C6XQBPlzym0BztEtUx1Hvopmgz7F9Sg7qqTHkITBUH4aaMsXpR
qyrpvoTQYUKbQCZfpzL8DkJrw77hFAFw+Fa3ZCQ7PT2FWAkUzezubjPh40kzSjaKAFfkZbN2qm0U
Gr8IXg1PHQdLcesTh3D0uJbsj1GGdYHMlV6KNx+rNn5LpBafB4oB+0weRGlJwsm/lQmAiIK3GxBS
XR7FMD7djS36sPeCSDUIZAmb26Afq97fmRdVbftrJOiSwPiHkKp2jTS8cZK3LLO2Vuwx3RS6WJ0R
JsvHNqt1lkDqJdrFsDHWZHN3UH/jQJgkhCjAgvo/4bP1fgs3e+8Vww806JoJhsfT/89GDrydvY8A
fj2iFIprpUv1NoMDolCWe7AHLlaRFGsf5COLhW3qKDrSl5iAlYiUVbEYCERth1B68+Xx9aULxMe8
4GV8KTUJvI4s/mlTXrhrbkA8cQpPpg4ZHxIY1xrc47rdyP19k3MGsLLpSVxFY3i3J8Moq51yq1VG
IGp3+5ELe+7e3VWSgTu9ws1bLvjDItgxgbNEFG+yiv7cykZXb/3gSTi2bZOS8ywKS9qjwA8BHyHj
G0DULxEBtFuYIHFIh5Xk0jPSn9lbO7Xur07oGHzwXeBE9MoGBhnxN7Zhn+976V7BPpWuuSh8cfFE
Yr6DmL0pCduDPGNbDXTER1+leirJP9ZJp9j9DGkmcgI+NWueCs/cGj1Js2nt62xOyJEnGNmuKien
FojwXD4CFBPPrIozMwEFwv0eUV/lsvjQB8VrYEXwZVkHOLYGKyNntf+2mYgGPCIgliMaokIz7ELC
Kbh7Cu6yvOiPyh85SBt7XFf5IFzKkVRbFGayIF4BLb0hnIfZYXHfOU1RqGguCNRvXzDqmp3a3Yn3
2IN6Q3PgLKG7B/UBs6kVhIZJkNA1JeoiUCO/w3uKdR6tB3LDMP2aU1Pl4F8fGLovULMF2Qq3gG6o
tPQbnC9DMTc+fQDwWACPQoQwTXLAZzGcAvGtDgBNYQvCcnx0QIChoTDWszGFWZ2cQzXJvG/gw6wz
g8zGiEeDOrSGHNoitYW+k1lx7FrW8yRPfPdpz2vdKD6T9da0d3Gfy40tWeV3ZllxKAMEAhbJl1Y2
1vYJmWWU/nFz6JSA7Fq/IRYHe/9ANTyTOrAENui5qESRYZ1YYxOY7v1GH8c3kFqb1cflDhFdehHa
SPxCWJLMEmtoNRbICkuqMyYeXf6fE4oRp2GVvgJcXVyfbJvpcPLdJzNOWFxv4Ku5UhsELGBiTviq
OlPzz39UDDndJeyQdx2tSgkrVQ8cNV7iN2Zvvr8239TxwVEr1QCj+BwQ1l0HB4VCFyY1125db7s8
gc8lLMekkOpse62RVtMVHoaRcySsYqcb6FqPFxOPkkouDbgKnq2sK1neOh9LD+6LQ5r23ji/qyvW
HoiyQCwIr+8RfRRBu6dYdh3khE/ePDS2UnL+Xr9/zUMW/+QF/bs/saVJNs/Vj6oJxUlM/X/sbD8W
3GL/dQM/VahC/GkUbb2R47Bnq+8PdReb7cRecV3fE+ijFAKwt8ZWswVRSHbPSsdbwoCX7QWMSJCI
2dWJCTUtjAebp2jWLP3ZU9ZRkjpDemB51DOaVGz6NpjsBE+NQrxMQP0HZirpBKny3egZau/rijG3
rEVHGnb9FO7TIqMv81FsBJ+YW660fzOhVFBwT1emw0wNsDkFlBr52iNhovsUm3YNqGcrqjxB3S1Y
1g16hsPoEeOqAMzANwkTCT0/Xo8L852PVF4J99c9LQCSxqMLdndR7GcMMGFqCw/cgf8hgHZ4fC3F
8WmNzcdYZfuRJy0DXbQVHA1HJ/X9ejBmI95DeGlQqJcLKUYI1YL2H3wcey1XzY9uQgR+q1TVbI59
uyvUIcu+MHcqo9ejJRNuL/WnWv0bZ9ktwIQesdJTYX/KxkrzNZJRXp+x0A08D94pbcESeuoVbu7z
sm470JmLNx5n0IxyD5yfYQrGBA3ImSg29PMd7ghRArbCyHRupup8NqWHxvODbHby8dSpI1vT5JP6
AxGE/4qPMCSJtwaoVoJEmNXMN202RibkW6HJ88GFD0L0Saf4Il94KSAtPB8aU1RTZP3QJXQ1d6Dz
/fzYS12HtxvBjYcyclkndBWYaM2ZOxahUJe3uTG3DTKirg6QrQfY3NYFvXUrBV+4YHo1BF2/Q9oz
0z5wQe0Ad5Kc+s+mMResyrEV6GuYw0uDc1rUsTlx+0XpV4KL38sw9GPRQf4C8EWUmh2/tid5o31d
aSlkIL8hmDRqrI04xrF8yGkciS9NK8FlJYg+819vIchRu0ZxS0Xj1BY7SZG4swBUybfXh7HXOJLD
iT+IlvDn9GYGe8OooBBQZeb7p14Xlwyef70eJJBOnujKD9yRwbhUvaYM4EabGGQvr+qvOgBp0Zk8
SgxVfgK8tUKEBwE5di4+qLWEkFo7sazend8QDuUUOzGEovV3PRyPTPPdIQbtcNy92pb+2qlwWQH5
cOMo7jeJU3DdA9D7KYpT/F/lrXmJB0RWRUaFrTwKxoE35h8wcLcNQyawZjW6l6TUuDxHdhkGB/Fv
2aeaArVRU60iWJgFfVDlIZfrbxVIALYUTxBOBJOqCZEdPIA8Zq9lLx2ohLmGFkjLcriXnR1Dir4G
cTJXrAdhCAeqMhGDWJnOEZWoVMROcnkly4Kb2e0uJzFsf4egGRguI+vk11nXlVdR6ZlL0RxRER37
6j9TrMw12HYXNvHZ70qW+Vle6NKf+oBrY5Spz3lMw62kOfc+kfdjoPPMGDD9OLGGbC7nDEal8mzv
NJBrW8e5kqXJtv0RlH7j0l5MdcYQ6UVh+b6/z47d1pccps1RF0isRGpy8emcMp3eU0SwPISTO5Nj
Yy0IuMxqGsY/bsLN9sn63G3nSkjf1gmc/8rKucrxa/gJNCgSnluKD+EFGZOWFBeYVDbcrex8kn14
UHh0HjadbYJTf7JfQgqKAflO8YuNu2qW3R904gOd9FsbcHZsQA+RlJmTbBkrwjjAmwrHnTOpzp3M
5JIP87bN+qBJM51S4Kac0PoHJdnpnAL1xyMF/g15+0tG7CilYL7jQR664Hl4OYcBMtUc0EBbxK84
LTjy68XCy0HrfOPRTqb8+IjVMfo46X1babr6vNVRgxgfoD8oI+22NKABZdGxKYCDBe1emwMZgLwD
dGDARzEpWjsnn/RNc7bAQwts4E0t1MihNDxwP5Khs8APL+juIYTWrvPTQYMV9R/itb5IsZvxxWCv
/WbryWhvOG7FOn0EYnilTlQMFLy1QhWtI+5rmntR9LZUOlDBP+FhFeMOgICUP9t/Yt6vK6v/gp9n
yWmlqRYYr3g1OEDp1DwCTyzRmSALNHseyMkAcHu5hH5cqhiCVR2WKYBIKyWjjo9uvjIVR8oUHFMg
eUuy2hcWQe/+/GRBg0U15wB3rZggVEWkdZbo98NEUaCqQldFx3oHR6JnPDMXSM+ldYjtQesUOU7i
JMIPJkZNb6rdQG4ypJw9PLIL0XiRFL3UyuDkRg738Fcj8oq6YinWpaZFBvjSUloDY1P7FYXo3ds8
cYwipMu1aoDF3QY7I/FLJgHNhlnnLmRiZZs0yU26ikTTY638ZotZcl/yqjLDo71aCAUA8n7xPTGz
DilNhNALFTWNXmeE/FCHYktHn4mop3NrYe1nz1qUJAJpo8f4hCeKj+qB29OG0IroNtQMBirJpBcy
J/qDSiQ7gRTJXiZ8SkfaPSRVjxcMD9zf1ogPd3h4A5lyGK3UT3k63JISxwE+ivMvZLJ7h7ZbQtcE
UATW6roDXbBUbMYhJXZ5RGXhjIlVTHMQVufliMlvG1Lw2Rpi8ZUBoFvCywoHPljLHj86HFtNB5xg
c/Z/mQ8SXN3muIg63nkqkruWTgWMKqpvvnQcRwuXtpjKEAjYG7as/4KFFkrMR0iP8fqXWarAZLQ+
3QVcpooqFatuvDm5oFLGOtAqYjobHjd91KejD6jg8T+W1oTkNmAtPzwm/CgKaDMv1JIEz1LTzBhU
ELCM7YeiaxkCzVQ1QnZbPbbJ16zOh/c5G+HWa0Cg8ncWnxi/zMs9VXjMTsZga5+y4HeQSXd3jwyd
SqBqKpHkyIfavnx370xCiRq+Zszvod6wkPc2typPUWU2kxVjCYARqzB80Gi2QfDVa64BseI1U2tY
9gxXT2w3m4R83KCuxisQa7IwzODVEIEvAZEBjVGXDP7mqwDPoWuZkzb9WDTSUMkeGrPjW6eIJe+G
DhG97+JFtS9sNZ0HtKtEeIr4zPHOtlIwwohzOKeqUCS8YACWptfGXbWgy3joE+OyqH5kbrxkjfuI
ejN+pPSI1h4/zHayB+8tY0YII3t2F1Bn7pMirEONBAubL8hBGIG6HvKd8dBJqLiq1FmuEXhP7wjs
ShbKaCORmJ5n2RQOUvsPEuqQRHWdWLw1G5B1n3i8w1MowkHNQnebiEYhdFySYbzUU2a0BMTEZjjU
9GYieB8cX9Ki6dfvwnwwc14+PlY2kvzy3YorG9ArCxffSU8DwxPeE3PzpGd/ZjFtQIxB+BXcp9uu
HH6lH6cv2Wj2SbRsmkvUXDGDJ9qMk2Ad8whAXioG2D7UMYVmARmadBw673H/wV0UAMZd4n5Aqtsd
LVP2PjzLt+1uGCZm/A04JBBF1VSYCOWXXlYtq2qkwCP7GHF+nW4r8Gm6WqcMpd5ZS8oGtiY/xiD3
BVlDC/XGPmcrdhPz3AOo0PO5IgwoSWh0btpz6nJkyv9SEH/Ofr8g8Wxhs1y4O4IWmrNCmNOQ5WOT
NZecZGaZKfVz38JopmfRQEMAGCTy5OArPyE1JceLg80iEtbf5N6MkjeArw2E1ZTDOOV447Ar8zvE
nP6mXwVAZRVLorOAiX95z8OWMmmxI/3Yicub3N3Dwd6uXqpyoZX4HxHOGO5wpuBWiKVQYmEJZbKe
iR/UOU1AszGjLprttMdu7G7PZm2cQpkdXZ6SfJKyuk6fGtfBVfdK/72yzg9iKEpkRQq/NoAlMgHh
kT35LeZ4pPC8ak5g6rcLQK4bNXIDj/ApKqIqwqSjvtn/7p8ygDp12NbdZRuURvIG+IjG1ln/tP8L
WKmpydb1c7lxeAUEMGzIj1Npl3pGr1Wt8BOkxhm4hn7NKcBsVyO8amFo+qDreJ4Xgr/WyIlzelRr
Yjz11bHtyN3tABq4tk2gBcVwZjWKUMqg+Lnm+b/SGUTrUna4sMODP9lM1At3gp32IB5yUPfFZCHf
pXCoOgeWigFFp71feGukIWryAmSF3hl/JpFuWF3SB+AKERYitC8GzatRTXa1ac/qfG73W29O3KpD
FJ/pixQ9RjwLchlacGtOsxEV8HSfJpvJHgEch7JLEAlhWNPiNVWEfDiuC27TvoJs8b2r8kLJMLwR
UCWrH7MmZ7uziouIg6SbnHx63SrfKee+jTUlxNCjemj6CAMyIu+d1R8X+R9d8Zui7GW/RZY/QMbE
XjLcEpDEkiJt981rITsYEeFEyHMguM6Ju6nIHid8SzRuEWriZRmEIJTAlNIiNLwMJugzTB3crOQl
8IBfaMRzjfCoau+PZND8cAA4s7vNHF4D0OokRek2glXyoRMl1VJLVGmx8Bu37nyNdvu1AQFjSYLt
etkuXnpS0VKHm9ZgA4jv6FmgSt2eUmSa6qrnvPMC3oNUSWtDdl2AajaxIAbvwKZgY/beH1iIkNEv
TjmzzCSq8SktUmBG72Tjfxpu7Va8SzV7CEVoXthUQ2f2wog4l1z5+1Xj+lXv4PQkEAl2xwkSxJln
lEG391BLOkFz8ytRyunEeaf0qbRxQqkLIFbClTxHPYYVF5vUJ66KAE7CRsABWa9FDyp8XMtk5zAl
bNo9Ns/XQjmFKd4k92EtfeH+ZT9RuldWeM+9sVWxeKVSntXZAA6ppscYjsGfRgSp6dGksLyHzi/s
Bwy7i1P0DdbURQM8g+Bp9+W8ADwkj/Tw+QQUXogp7ZwL2NAJyvAOr/16eTgF5Qun4OykMrEfpcJn
4WkkWtbKyL46Afr7gObVr5ukGM5mMGxU8HmBHqGBjJmPyhjCCeTeHkbQxsZZKJUo2WowikWK8shF
CTK2xNy7A3kK54cBBGi8n1gBd/qRP5i/ISxSLP/FIC+/MtUe5aSGnI4+AeAqyw2/4eLsiNpj+tkO
Ogn1Ld4k9ivVN7f+7/htAQEDEDZBODHL8IwVVYvhNTsfsKPs8RpJMMUNun5AN+FM4xOC0OZy7IrD
bUBZLmUkm1x/CggFdLCedKFp1P7Nv/B3wrItPNaJ50/z7IRomLk8I8QSC9zJaLyI9PeAAHlZ3r/r
SZ6scDe1XGNUQQJVnoXM8ivLdua9OY19yh3fZhePtbKbxtsKdShqdFf1gXRJNrQh4L3GTOaJNOTp
DfowShHtYS5OS0FuDNItNDPlDrjb4yaBRNf9k1fUQSgjjTLtpaoEqkuWmAdTZU75T0gmQKeEdRmQ
d/REs26i04OWljHjoXBbg3gVUT+pAS/51KWVMIt6TKU3/oK5N2XAxM0GL9x5sHcle4+Totk0f1UM
pJSDJNAxBvl09xwAvNDkI3rv1If8srNnYf8woVDiL/GAl6aVBgk2Olh5A4fq7NvGkTnRjwBNoR67
76+HULUBRo7ZQOtL31pyt1W6DbOaRUwPMyLEfjjOh/f/4aP2Z0D5xLUz9h1nL4bk9tLuKvhWN2eC
v/VoOzh9knxV4XPU9k6FbNki+i5AoEoRUzkmy857Bo4gHOLS7/OQbbcOVu+42q2PJJSBPt8KF0Og
8O2QpP2/q6e7A7D2tzI/deUI8EwfzhAv5v4cYEK54AqR2yfNmaz54RNgcisOpXnoPzSAmi5Jiy4w
seUpvvUtUt3cF5xBmjd4H1njGi39sQyhQ5/xvuBY2HJMWMXIJTLYgpvKYSqMHJwhi/AxnP9Z3QLR
IliidA7EvSzogBR039dzo8cF0ksFtfGYV+3P/S1fvjP1mkOzPu3XR7pWZIup+YYQq7iK4SmuYhlL
EnmOJxtLHjEWIJ2IVg1C+5bkUVOfkHbXg4BEnClv4C/tHNZWJt6h+hsD/WWW+wNSHvfujeIyxJ1H
aGSCNa6hGHhrwyPdCEMym6iGLtMfytUCK4RcpDVx4uBJFjWnYl/OQ4a/2+zNbyv+pcXIkWLRe8oO
06fRGbxHxbcMiBKDtwfs3ftrHM2ao2hMCrnDOdnWpjoKq9BPYMlreZX8FnxhtVwaIqkJkQvm3WSG
a8OKtxnDF76zPPrInP3CfNyM29okOqqlHKpUaEFkzRlaInutn/9EbtmcunIPVSHv2wrPgK9EbXyq
vDFW4nPn2G8q0NKET+jEWcTOfZhlcSR3MVqAAc8Eyn315NtKWhy6C8cdBOi1PNJruNo/R6+crqw0
U2R5NmesHfliHs7RN/ixyEvnevb2pZvwg01GfKMB9salRlBuPM1gnvkXNXXUEG1N3QoyLDgQW9Uy
qFwWVVNwl4tSF1bm4asF/r3tMU9AAYIos9ioMRHi4aSxnBOUm+vznfIp+f972/MxZenx6R8J+S5t
jN3icf8ZUTPX+zVK+QvPTZT1Z4ykXOCk3VjtQyHx/3ba/vOuftcVJl7asj57uzOKZ+y6RLoGADkq
PZsPM9L0XluYwd6zYAWZDz+LHeZgo5+aTPuDQ0OrsZjMV9LfjsEnoHLQe1NFOf8jSq/RAthRjbEL
vlvJZOxaTM0B812GC1dvy70EC3ANFCa1p1i9qZZbsUl2DG2SF+Q0P8s9PU+Yg6TKXx+iBSFoiVc1
7aO1HcaJlBuWPsN4UfqiIxXfmss3KXOd1Ev+U+VxTIx0+SAV7QsFrNz1xcXgK3r/YYffvSTfwhbg
HiBD7FlLBC1/HndfD0yqpu40/OMyjCclh1KjlssFnip/U0AcO4aYcWgMr4yr9p/LXO2/PyaC6s4K
246JXCxMfl06I48Pj6ylR4AfEc6ypfhm2Wb5gu1Dyp/5yNJjWSA4hDog/vJdelIo0Wu0vGLLuwLs
HbXG4yph/T4B6KoB8muzBPRiqWHxixRXcsRJTgeJYjWyBCsZrPrl4LAWoYbVDVGvIK1ZnnxM3bYk
CgznsbVv8CeANMXSCperCepOFVg39YQ3gwIc+V3fdyhyzeVKqqyAXNwANyMuHPv8sIUKXGzZUN7Q
v55m9YKKN/lMd/CixzHkc8NBSjIsdk3YGcSPuZGMU6Vh0+6c5RSgjNeXr/Um/3oIpHHIePt6oLys
Z0+cVcM3BdNznioVMDL8uN2UNNCgL+KTMeVk+be4GSmos3o+c+gonMuxHwGLDxQQk6/eUhUVCgVv
JNepm1O87ulOjRPtSJpmTVOlxCj0FU5c5eb31dWiNUqbldnxjj95VywbKMb1ixDVFOtl+Jx0ciU6
QGO0OogJ9oGfSw7snkftcNPGciuyqkzZXzqjPWhVf/7exsUFK+sTCse/lV2qEOgpLkrZjFA8rFY7
pJ0p0KWR5f5EGq5KorIAuRhce1hTp4bHOTSwyYunl5fOArBLMZ+UEv4L/LJ8aouAZvyC2zXG0FMq
+wrWT2HG/AFuVLR6PzyW01kqKAIenBFqjgq27me0C0CoX93Yh8ZD6IE1fhdkfzPiUuw1DHnNpqEg
dospkG+6eYM/rqt/40hO0028egQ76/QNdv6qAl9FTTRTTArX1mHhm6sROHC4sJLZ0e3+wbqsLYe+
R2YY5uAcdBqJ9jEXpR0XJe7GNrUTzhWr0LCFJV2pfxgKxI1a/iwcbkplDaNO42tpp7RhexYW4wAV
mw5nVhOMKgK521XK5gLopBacJ8kt+wKKAIBPx0gkoUF2Xvczn7yRXrOOAM+PA6O7VBdPrSxJjklS
cTMbv4trZ9YCFsDEKa1NZ9JUpqVHOt4V6pTOEgJG/K9SyOBkvqOlYkwSSt3Phfjn7SAjrGZkswcl
0enWzIcPl1PUWmnesZZ7DZHJdDDGbgWPE5pw5DdypeUq0rC0RgTtd8CWE2QqLU8sK2CHLH0/sasK
riMsChZfTuYlZ/NxfNIL/OvK9RFlkBw7UZ/Ti7HWHnhDGKNAGMVkv+SAq3xlbV7CLVNIvugAVrLj
uFEOAIi3/n3xmhku197aprimHrJeOuwravlUi7x1jbNDgV8O3W7X33pMUM1DPvI2SwSYdEK/j1jb
bUWeZc77HLcw/AlV1UEe1wTD37N85KyT+rtCNcx/nh+VlyeXfY20bDM8kwbknIWO7OrbavBb+t4/
jq0rc7Z+MgNxDelbKOsyyuFfhdfXprg3GyU7VD7nDhvsdZSP/dgwvjOSnG9bRa/GXNOWyLjXjWgS
Pedybov+gsNkkLxSXezxlzfpPaijgzax7NqRcDXUBbTXmHoXVnRbi+y+E6rUVA4W2+x9pMMBSobP
AEsB5+HTgvOkNwEIWiuuMBDSHmKtQwiccjeCwG3nyrgWIqWcG+DG7rdLD/m4UoQWzRHHsGG3bhaM
mFGrIo528l/2zy9fk+PRsEspBn9eeEbzOWv9ig5GOXcMOLeqLM/Kat7Xsg7FwI84ZjSfDNuL25eB
RIpCdlJpeGdiOjFNFG9yojRX4eq3h88zaX28sRLQmByD3UPgLwE6dpvCcqX2Fdtxjo2/eJmWpzt4
4OXvVc2sfQ3awRozhcCL6Ixfc78SyBCCcDiNbRmZr2kHvf8Tms5bdyaxT7+cw7pjjkW1BRyqSy/Z
DInqnjnOkjTmP55NJ8yUE7fh3Ef7Xejws9fTIfKo34G4WYkqkleeLCSJ5LDwhXVrX0ZI6pIphBCf
ya0gMoSXcJCfgm3R07tyLDG2yfrrwvvFw7XyvUDZfean4tkK/DnKOci3ubcgvTku5wRyVH36RCi2
/qr/LKF0qHIYg76szxAcMBBrxKbAMuu1E/PEt0PgiQsYrTsInsWOQ6BkBru3FzbPV54m2jwMQse/
O/42zoPz19Xagk54mH1irmDCmPrvOrchD6RH4Jgt1iH9of+t1dtFl9x16Ib5W55ySo26X627QjHz
yWSVi+lQcQK/X3Z9L2qgv45VLr7OCn4nCsmGL9M/R0gFZcyod5Zx2mEV4MdjLJJ82I827eapPP/O
S0DrlrXkKKse7N1LrF0oQPODUbqCq5otDfp1vlyO/QkFjBRR9tqNHjJT8sIYx1IG66jkQK/RhY1u
j7w4TgFASabJRvBwwI/5iAyc2koBr6KckhZ7OUdasskAIWgUUr4DhqBbq4evRweAhHVVXDbLo7n6
Pmb4XrBLitPcLX230wlr8gXbBNPOpPT3Ud2zSyLFIKC5tGjT79AGmIpfqnjsgBNEiLCrLjvNklc+
qfUrE4zJ0khjRzr1kVnGjoBC/jqDcLl4V5yx+FO10hsshujdvnxJRBogQCvwybZlEbjDjmazHuz/
v4mN+W82KL+f/lRYXFJHc5IDxFQzVGhRsjmRiMdBRL+6SnacTIJ3/gUqxu17hPHqxB9kH/R4rxRo
924+PvEtLofz1hQZ5lZTklva/tExBkXUsFpjfTElCK+zskttzhPoPkUnQDcMSDXVeHQDx03GXPal
E8QMZzzS59Ej2vYEHI0yOra8eGzmGHq2tOiQYWvsHEpVmdoP1ELpsB/Mn+QxZ5St+V/CWbIEjSRN
bi3LgpynSwSc8PtuR0pNCyzA9gxllslN52feZJKR9aXADMBKLVIq6oAmMhJmXRuENPnOP4L1kTB0
+/7hco31aoZx5Xz2FRYrX5SqsvjPjDIwhsDVYoZvNIaN7vYyyRm8kje3ehPmfKgseGBx862zpvt9
BlblvRsCRSoMvKJv0C1tNYqMiSZYj7R9LuEx3xCKmeDv/YfBM20DQT1h05ot3fFdrFUivBv8GvnW
HSlq9CTrnErOLn51140xfjmqZiTcCL2Hfxs0HXFDzdmqgzZNVTeuJtxRUEBZOvx8BLtNHJqNINQH
sXOLvx7Mc3XBnJmR5Xtug18YAFSuNBJEqiooy7NLwDgL70/8HaQXeIJH0TLDr9aUqQLSeudO3wo9
GINngGxPEv7JPucjhkf+hpf7bX68Ebb+omVu2j+ash2ULjx9EFzH0SPh8YE6wbnc/kFwCZoxccDj
VEx82tPKgmZU5hkLEV8rS8eca3+QGw8BR/pmRZBoVuNwj5N72aIcvmqUYffD4VQ6E3+QEGeIB+wB
ynk9vA9WUExcAcR0Lm+OAAsDrwRpmZD83EXJPbllGe48BB5fVzziP78RINoZCfgBPltdHESgltI4
vTKLI30rnpyF0bLnO4xczINdy+JVd9P1ozOuRNYAUL9RZNX+SJ9JYrajMboKKK7d/SnhRkjV0rXg
uubO3UYSEIxPC5ZImki/19ALb2t5TkL3lC0fmihXH6GYaIHhhNeuOoXQO6tQCmVNWhC307ZZTXR9
7rYlYMd8djcIQC4W92VmKGc9c4DcK/RDusTKXtQjYHqwnEuaUGuUCdY9ED7A71215OsjNGxQ228G
jFcdcM0wqyr4GUcDOK8WrYbvrGqBZZwosgZJEtyKk7FYrb6zvdqHN0y5YPDtRgr/8CVfn6xGkOvg
k6TaPQYl4JBP2fOgF18J2y9RPDTR1DZj7xwAeGv3SjuKffYjV3hDwfQQktFuk60X3ewzoMN2x7vW
LdEQYN7MvHpG3745q8iEm1s9Zpj9AztiEC1qJPs3aftpDNNPipuC1hOkMs2fFrkiZin+03uxQYlh
OvgVFRCntkLKAibVQ2Tntyr9qcs6+zAjlnknSGkh5/0Iy15GhiRofwJhnKiaMbW6ZW5JRMoVRaot
fn0GBmSxOL10K13MIdq4Ny1WFHRPSMRgfZFqnmT35kJhCWflJV/lXVCShVcqO+Ge65Srl6j25Wqw
pBwbnS/g7pcSFVO2NaUYgp6zKblyGyCXZ51Hqcmv0cHQRBmEBDByH7S0wkpMk1vZFQLihl0gp1Kg
uKTZI0K5GFA+st/LJHbUn7Cso6tg64h1D3uhOqj4FdWPwDDZuO2hEcxSg1JLlhDnRUjRbGN405Jv
oPMU+MZgYrBXglKpbgAPQ/bC2AJOqCn8LCYhXJ2aBr4W1zrGCSfvSJpFFCztiVQjX5dhBccdy6Sm
ySFKHeOrUwMQiTtPNd5caxd3mKeMXKtGXifcZTvJ9hv0NuRr8QatcebprlIUUxt0dbXTx8yrTvRW
ALCKibrNV+BPIqtIv6AbUCx1jirvteBiYQ5K6kq6j2SK5RrfsEYorN0clIwNl9mBi6uejTEaRTvh
+4pFD4olrH5D7hZfuj0MUJ/2MMSWFOK+1pdUlkuUssGXBGX6S5KM4yjPoeqWwVePqinLIdvdyjsE
D0UAotFGjIZfZaE0de4BP1k91/v3cdwLMDoy8XmQ80fQqUPFIEGaB+yYeudxNo93VAD9SdUcMpNg
/if1cSjlXx0nsrKa4knDN+zxc51i/Gi0rtm+MwgoQplQyd2+WuOCp3BhdkJerQf8zQoFo8CDS7+K
YA2BUrW/fJxaQphmk/kS+0GbenbTtMm9eR8+eVzJJ4qyOgSryzkBXH/ZUpp8fjmuGrmrXoEJRREF
P7ZbmFzJBiPgBn040r0vIxOO1dbWbZxbmcdow/fhRIs8WN1u46aPh9z5zbQZhQEwDBp8JU11kuVN
QHvGCqDa8TA8AT8gByF3j0UVI1Eq7DNjJrTQMlpe966u92RkriRfXnbmLAvDdTeYmt2lm2Gjl1Rt
140NzzfyquW1akUJYDPhVrRyB9yxgJPhpQjBI5hd0AzfBO4y8IXVEvmHqmcPRgEsJhAEWHyqIUFz
fT6E1iITk9V1VBcrhwHRFLQM75v4dwiG9qFQeVqzuw6naU2L73XWvMcCDEcf1bEmblV1fVHevRGM
fmBWpkLMT45C+OBO+MhHbluBuWOVuRtJ2mHXghyK2xQfnn4GstkWlt55LnNuE4Wa2n/1ApzmoFci
JGEjRpw/sMvql0zvLSbEKVyDyWGT63BOYE9Aad0ReAgO74/UImUGTZ85yGKoYW91h+5UHNoydYqB
fuA8iBBK6hVXq+xCIs9sGyNtSStCb4Rp53k6UhgaHpF2imjgPiOKIlFV9/G6N89UDKVlUToVWDSG
YIpfmoqlEzpNus69p/NjWcmej7wbxso072bg4Zpg8YzktToOg9jiBOb8JKfZbj2dO89pqw/jftZR
Tup2jiAIo4JIA5J01Gkce4WLz17BrUdrbTEUQqFTqEmL4dhzwsfzZmuyQ0qjcK+T9zS+1BoPTF+T
eT3y/CgiBiygQjB34qVHb5AzDKifyEHdp3RanQq8fywxigVHOwnXhOvRZbKFisbo3wW6sAB/xXKW
dKxFg31Va0CzB8Qae3XoBt3oB6Hr34mqB0Ht+IPZqZitKje5pZr0F4JQDOyYfeUhVLFqBPREU5au
A0oBAb5BPRnHEdXW2T3eVJRPvL1qcPIMyyFg9fhi19q6U78+qPTDMtcmxamjld6Nu3/OzZBPb/bw
1kfD1GMJSAZea9xPuLmE00yPBglskXv0wc6ZttReBVKvfmsoyUkmVA/oC/mAK8I5QIJ5eX+XNfv5
COWuoHhSQXUSFNZLxgAd/cH2sALVMlJ7DQF6GfSERSzNFtsbOfOh7kMbP846nqYBk4ABzibGCeGU
0iouq41a0k750x/984lROTPlUCgRfpjxzte74Iw5F7Aye67imQZuysyjmtAfWk5K5kdzIFmUImY1
UQDGTVtS0gTr2zojxi1RcWlitfIiajvoc93/M10d+5/5LZ7VkskgxkttQE4nYY6lg3L+HhBDaFkH
pZqoX4ZlXKQ3j0OvsklDn4Eqavs2+AAMn2jtF828tlQJPm6ERgBd03xSoA8HzJTr/yjzni55fWyW
xYgp372PqVP9Eoz8loGOQske3ZBYRt+Cu4uZMwOSl1LyyZ9lHcVCDf9ryFWUBgELmG+LIim1RUSx
Etn4p0Ms7uwGswsVmMJx9sZOjCAqKzEbJm/RIcyosuOkNcn+BL9CWvS34zNB0qnZsYkpk1Ovv5Yl
MOYshJGX+II+Ae6jVA4O4NCJYletaPaCASobQCqE5eOWItRBMck4Ppp4L2mwXzWyt4NcfyeBna3u
9dWTG2VkZtTHyYJDMXOlxlIvBcDRAl5r0lP3RcxT9+Kp+L0U7gSA3GSBF9xHUYfean7j6wvKOHLx
nk2g5JA9oQQ5TPwI/xINqqLm2rP5RoiksJf2SugjHDPbiWlZM0j++nXRpmmZOxXu8ENYOoJR9kdk
WXjNNn+F/nMmPlyUOBKzc2a0PF53W1mrhpntfPUT7xcdcc8OpwJRK32H8S85kEZFYY/VtSWUqCQm
9pbQmagifTey0LL46v5M5faq7/A0dv/ZaOVPfDW1NGp6TomoSaHq5BRop/U0OQ8DBYFfI5L1uGYu
2I2aQrAmdAnShUs1f7QTOWqnyKmNHCYj2zqUBjxMDrPa2d5Oa8ac8tGXEmwiK1bbCSEJHVoAyuWA
OVASXh/tDtT2rAEW2RSTmgedPDppooWi7W0BB3xjzQgz5tZ2kQpDB5LL+bZ8m3qU/IRnQKXCjw1y
oQjk4ZoYJM5dUdMEhXaY/uGQhB50m2Y4vGICCMdlZ1jjRE29XgfviShgZ0ii23dP0+UmiTYkSdmW
+csObdxfbSVW+ZcVbdqmJKMRqAhxfbweoc1W75cGOXZzZO3PZcgiQvs8863PNinu4tXa+FHIl+sX
c8ut/kl4bZUCUpjT2aim2oVzrib9RYthSefZFRPncHoRxsakaxdQzI35jTiDrO1yqB9dnMR26f1E
7R46fLT+IU7gVuQebSsnm15h7CBE7GitTf7a2Wd4lfwFF96D2gxlJIS+K8EQGt0zAMsBe586A5FO
kr/oVhZB19yWgnwuvHS8E+VuXidoV+ged7CGaD8dB0BR/yfGTehMCrql2KqgyD/DDF0GOqTcsEG/
3wiO4j86SIAYVQC6D0Q9u56s8MNK4nUaM0qFRl8G6bP2Yf84gg0CQHtxjJmrPS5yJqEQXSLK/+RU
Y46+0Y9XsORLoghM3ZDnLkL7q0zWzLvOImM9LOuhVcHx+fl22Tw95Do3N1qJxFc3pY1HhfpbhkMv
HwgxMX3RSkbmTfMjHcDzFbVu5cymnUSfxpxINXTnBiErIXfGENwB235wgIfn7JQQy8u981Rg5f6w
SUeOpCtuq8QtaQ/B1x+ZN/pmninpCK+PZFIkZUgjoBfMvn3/EmdWIetcVU+CAayqsYnfeengCwkb
Q0yoPTgv9IpPPJpZDyhW1MhLIj2dcCut8LtKcoVoCfG1ADkvt6GLJu61HrXhoSv8EIHy0NXwfDDT
FlCHFTEh8jtZHx/TwyU/iMRauLZRxuHQvleSlfus6h/i7aPl7PsadjvTIVv7xCN6aXZAxTVDg8NJ
wHmTMNrf89yySt2vwR+bBZixL+lAp3EctrCMszwwGamZdvUahpzt2uWrqtPm75zRSPk+hbUOPZbl
EopqNiSoOybEsm0KyTe/xhsxOVZPN+ftFIhn114LTsjUZYDFoUBxRhFqLFjL26afoFK65iRUBE9n
Wgi7+iEzH7Ar8vn5X+MaoncF18Y67sk4E+NsY0tKwkHsJCIC7q8oDWrIpI+mpUGmhc6HL4gq+3A4
wMlTA1PtdDj9rhB2Dx5qHew/oU54BNIhOmEn9XU6xKuLahA+8aL4rpcWEKMj7eQUu9g27fV074Dv
9FlDO99z2gCMZK0XW1U4JQbeSdXDzSTE83EsA0jjLodkelx045vujrhcbfq3FLkzU0gRlLE7HGcK
n2XOwPkRvFRc/TWrlul15CB1NT64F7MDbhk+MytHzXxSZRnqaS6w1/kF4Pfd9ZDXmYl/2dzJBb6j
3nCh8B2WQIgD1SH/mYB0AcdotsVj+hsU8Gk9vMEDa4zAuoR+WWzf4xMALJRy6g8+jeDrlHWTV44v
/wi0RE5qrVy8LXsG9qWficyY2UFiZ74tsevA3g+71UIu3THm28X4yQcxW8I0J8YABxPebHs3MSx4
qsiSeT6NjznbFHy8sD9FJxx+tCk3b6DfXKYVb9JfOB+DFKH4HkDeN3A7pCYuNef0pJRJwa8aNbp8
Smi6ozWoRiuCiuxcfKxbcGMIfU2LLeooVkWZoyQ7NpIlzzscehfQwqqMuo01VnFRUugoja8UiWrM
LS97WERraUvgXYptaAaVGGPKdZ9Bqt0hSdjnPX9jnz/PpS1MMoidENaESTmaKceXLnj91YtqF3s6
xyEoemHoaKqEkgqKbKLTL2+zndcMaHiCnpJOFthU5vjbOJ9APAzE6SVQxvzyBvM6zahE2iTr2dVs
SDet7CPp9zM45/bYA8Th0NVcYMAGeAlf3KVf/a3xH/EIbpFSaZXY04QQlCmrHmAeA+AvimLBcFFR
2HdgSEcUk9x8g81XyUwQDPGAb2ydteHRwCM9oBidlm/oRgykZesT73limi5kwrMX22EuvIJ66D0b
X9OcuUCA1yE3UHZoIbPA30IUF7fx121l1eRCmTuh
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16560)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztlHgsA7XTu3se9+qgRV127brGn1J+SpZIMueDb+AV872JX
nOXB120GyVLNbjkhWTWXGQdsLOXfaXs2I36xZVRiwzpAgBzfQJrI9hG2kq7bh9WznJ3xEF5DLexY
Cq15Vdb5gm0qDaFFZVGzlV0qAsnNmU5TwLZdRsYlrsSd1i9jUQlzfmNsUENvXGN3CDlY8CFK3jai
INNNriIElfSpAetTkn9VmfppFFOF7wWkbrMeWuJ7l/thC50PzIkDIzK4x9CtfhJd3F2cp+VAeBKF
LrxUYaG5u5XXGRyoHikRUGoKOXXmqvmZIKvGnqo9OmemjsqjILGrPxP+3Dy+cG+LmqgRYTxy9X3z
oMfdSSQ6KvJIZvqKnopohLc6y0/oMFyP21GDeRYafr53M5KZ/f/dLwptOby/mIDvt7SkwnKGfvFl
EpHTWq8Qukwr6iDxqQsNxGo493Q+4LG/yKuSE0SND6bwyarofUfxPeW4laRQMKn7H0Tq/eaUvdP7
vXl1nkBrtRL2reVVADRjcpDm+3z/jYigRFz9ttrA1C+77PRjiowP1YG1fdzffqSmOJ2j2mFWYikv
ToyM9T8m18egCp2ghJoN4eI/VKWlDfluDP8ZTsWcngrJsn3e/GAOL8PDe92FDeVUKpkl+gr4V7Rp
2aPnAyyzEcBeVlaEkmCZITU7qdXWBM5BIqVU+5e2tVie09XfrzH5MIHwUfVaSuy2u55zP0BOF7Gu
CUEPlLKnR9X1WrHVcPnd6fkPfFulzaTs2HuDJi/KrTvbj7wCFie6P4/WolNX6kPWjcz9aQ+wnwhS
Cl7c1ftfyzJMNbweg5RPfaq3a88McLpzC6etEqO31+rgbz/dfhINoJkCiNixX7xIp4n8lci7GXoM
doKmP5XLBXmP/Ef1HlFhsKHBbwP+AsT/HJKsRbeMXUWPRtcZnkpB4dP4RxWecqcBPC+ggs2Wg9XD
flCvKjr6I9RAgAyAJYDKpapS2KNmOBVR6fSfSEbVOTjDKBU6mPvbIW0B1GrxujCVwXhYhzfa2n7s
pSvvjqm7xICaDI8wL4+o4znzeARXPT/oyN++/EZb2EHhIwgPpY5/j+VTdImaOHA9M1rXQQLS5YiQ
d8fE3ICl0Dc9YPx7Gi23TU1UqiV1wx1HdnYhTuzoxdEq6NpLA258Wh+rwSu8vP7hWDb4IQs7YCmU
6c1ehdkx/jvYYfcnI/kqhIpv07AlgCablcW/IVHSudlBYFvHKGNJQlgPw9VF3ckGkh8Nga9O9I9d
WGpkXkOB7qPMCwxtST5z9waEGTMzhngUhfVQG3HBNTQ2/Wat/S/5ryngqBFCJaIgUfrzw8VYPRpx
Ma8yghJP9QRD0sXR0VB21eJw+4iLEg1o1b5xf9NUkYGOZOEZKU4Stu4K+cfuS7iTeocaFB1jsdNn
ntMoV0FAqRuj1lOxDG+YJLiVc5qi1sBf6RQL2iPcSOOeEQ+PD/uFwCj6180hC84peYYWAyHN1Frg
05/zwXh2E591TYe4C0h0dT+Aos4yWciHzN20jWOxXMzIS3G1qwF0EGqAijrnXGLcGocwxkZPDg7O
+ZIkcpsjjhwsvUCRAmpdYb12MfN1aomq3wUg8VUEjLXBfDpGSJm6LmRFOyE95KmkhVn9RTJI7dRC
jwjcf+RbuNT2kw6BbtbyviR0PCqcqqTHTP/U7tvsE06ymyUlA0+8IJ3mEXtUVLHrlnKrg8hrwXl2
4THwUppB9JDYFgpLPAXCkF4P+9MlHt8xmiKzjjY/jg4X5Mak8s5L1GLzrK731k64QPGLnV7Y58fc
JJVHuV7cVknlClqd9DJbTGS2lpfnm3E5Xx2a9tbuW2oKicS7VLIMnVFCOqwczmsysYtdtNgGlee5
1fK25W2QAG1uuOeASXuQ2ZNt0bEInni+G7PBrvOi/pIjashgqTgNL3SHHmA/XFMZnHX6netOZm3e
BlfRhSx0HBjP/WZtK5NmOcyW9rMppg466DDbqoPfn9ht2ThmNdE55qlP9RBkGuq3LmORr9QPoP2r
Kez2IK03BRuNytY9tB9JWMXjpeNTFfev40Y2apCXKqghOHbvLqicXRe2RpvdFsDdFcAH3Zd2cOx1
is5sPhAMvaqwmdbkvhYB2IccISAzJCjDSLxf9u2Ohfbk1LkOVNmX/lsYcr4M5bchScDMMvbxps9A
/nKuGAdf59tzE0AtDeG/JB6q9/Xatq9vDckMhMnW79Nj2YM+eA4nboeZi2q2usxzOCsHZCPMfnmQ
JdiYT4tcLjLpV/MAsswTqI2YwYG7Wsr4TfTd62xl1K6gTKPFxD0Bxeh/7gMUL+s04w2ABMxYeOUS
soGkfyrtq/fWWpQisTLRSPV3UDe0a8xM5OL7koiF4kZg6J6vU2gRPDL6/9fq88Oi9w56f6BRRcy5
zn1CYRLMCbCuNo0bQ1ikRl2fwa6WE8OA23UlxdNZk2+rphNHNk/UloVCB5ZXiKdP89w0J0JyVcme
Cc0Eo26iADVldbzlUVXNikp8CU4tzrmC9jSh4NIpBU6d0qi+G69Y6KulyUxpENfSof5PXnrXrb0Q
89dsh1dr1Thsq5QZcNvSCknVagRzD5eUWy/u9tPEyziJvWGUJQOb/YSxz+I915Wlw3Gxem7EPsck
e1PONwATUS1zh0sOiUIChUN2ZysliabYb/tSsNGvzBtEp+DbZPlcoyqbJHSoP1TjXAnB/TDMobpY
yugtm5DdXSlGUrsKwBiBRcewN/Y7XznivnNsc3JPTo1vYK5Mc4DCRgFEZfIqde02lPpl2OUw54bh
699OiZk8Z8JHlBC/A3sqOSelp2MNG5GW1MrCAdQjpmlf7u1evUvOQyjx5tM4G0aaGiNS35xwXmvy
Z3hId27r4DbvS3CI56QsLSh4NsdzjHoirwkfFFUQco4kP6r6bBSb+qSdg5mYwvieiEwLTDYXGdFR
9H1KBQGXkHjNWieL8VYuheOudvT56+fW+kiYu45hauh62DQdKGeGikrGmLr6O7Cs5+vYXEzV1A+o
rsbHB+3w/DVKGDe6r51wO+1rKxqQ0Ly+zSKNFfswqm4qVO9OSIjiL8P+9WdX2WRpsnvOWOa9LUFo
NQi1p429r6FXqSXAxtJFZAgtNmAhrqBd28LyAHLvJsKdymxhpLsNGZqUP9VODIMT/jg9FeKzeDhN
K+mriXZRagg47TCbQ2xZG4/ay2CZfZ2sKH10qBP+sssi7JR0Ir2VywA0EPn9PnMhtTgQtvqypQKp
tC3vUX8ahzFNh3Rwo1+nu3wdy26gqFRexgdN/bJkXd15oB982kk1dlJgX/DPRLOnOtTMfIjnqRu7
2BJeaOK1r1bEPNmwXEsaqVzTfE4vFlLEBmqnmT4YWmW6Nicd9qmfnMC629+UyKOGD1E8xJcFqsai
KGe5AvZuNbA6toK3QaB3p/GBfA9yvQgi/U5HY2xKehgk1556cTgixJxIZpNI2uwglCpYejZIoyYw
6MJnv9EPF/8HnKQCdAU6BeocT+XCeiSTlDDbaeGtC2h/HJjGXOM6hrc7vAC/zpwnoyF7BrVFoaFr
gUbOuzQlFA7zzL7gukUB5wlipL4en88vw4fNqQVoEsXtOJt7+OwYxZGX2DVrbzXE/u+6qgVZrJE4
GQ7b/tFeHjN2MmA31MwbHpN90Bx3MkW/t/UnXttPwJLkHGqRWBEg+6k5qScLFuJU9yfxFL6Gl1Ts
wIRCystlJ0QiGF51P+e4bdezj3lGSLIsINtYaa972U88lqm3si79cpBX3PmtfG0LWfmvcwEQ5C3S
O8DvsGbXqhKhQI0hcp/q1GLivekWYvv0DUYQwl1D0pqHEU6HhXAmtkavBRzh+bBdmM4eq00j9/ey
KMDXJ/KGd1UHloG2GevD15YewMLbBrBiBbGCrKoG2MlVx4pS2l8Ed6uFi8sr8JvMm5BfOB4qMX3k
eLhMva3T55O4F6d1xJKytcNUWG3o/ioUCGqLOQbz5VEFJuO0yJNibwfl0L6Zq8nGoa1d7tAFKrf8
di+++XVql/0QR3Objt3pn44+I4/xFX0Fo/WAA4Gjx2qN2v+gBwp4PmFB8RFtRHZzYeho2dUEaoRS
iMRoCzeoLMqR3IpyV+4Ke+/YXueoKclTjREVWIZx+xOC2/8Mkzsn5exuL8xBytvXlZOlNThg1q/s
l+UTvKbilMmlpnfJWVQmVvY1ANEms1T7Fmi/iRqLt81K2quZBkn1yotrpJQoXWim5/1Xx+FbJtpc
Z5W0Lei80zbfWjkV6fJJh97rvbydPikIQMr9ggiVBXziaHiyz5znMYChR+noERf30uWQc3r6i969
l2DppBpsIOzfpUufIvlfQdviduKBkfPmBu7cwp8Z35r4PCO8d6/PVWhVy/1LrRH8cKz7XPVpdgs+
Po/s1l+Qq6117HHXkaG3erTJFyrL/cjeunpIxssncNIfUTlC0ZhoLm/orQiCQ1AUBv/z5KFlTyAo
VSYL6gRlt2mxsIMjxj76F72fc+8DYK+rp6lD4fpUG5VCVquHWtym4EXwat4n6LS25KP0AI3Pz6IV
tdpsgjz5Il7fHQ5P3NG3r4ovkDcCTh4LSwibzVal6hT0QgjhsTRTwtSyjwURaXESfpoyqtm08gS/
kHuni1hz1GYk9h00Z656w/xYEMFTzzA/nP4mvA8eqwo4IxrSOxhBURV5iLrnl7W5+6u/XyeGswma
UVjZu2CdWHnHs2DTL6MZA1dw8CcQJnRxDi0iJDV3Yw5QhBR3B6l+6opFKyHYGPchwT9kYF9WOnq+
sX6DCc7wxGppgxXmZQdKcHGDG99/GEBN3JzB1wVu9AE0+x2KFcTOKruRuetEFiZRugsWJk9CSMd/
Pqqy/1ZYooTmoIpm9FYrtCFnT9cZPY74f61YlKZkI7Exq+2450huOnNcq0DND0THHUpPYSkZ1Cqf
+l2kGlL1EFHj8yRGpSFjkx7gDHvCk1wtgb1ANbEPaBAOQZZx8hZGFPitdaELgSXqAwDmmmB04p0P
hCqQBvO7/RrfEphYFnJ+mjkm4HdtKH7uRiYv+QKjpCSofNUUiVufrzljkzStj8YWPOZx7uYZ3Pt9
6zoVxfaT0QlvhZBypPXB9AvcprFuQVdI0CbPafTMDyScVAKXK3gp/N2kou0/LjK1xxKRyNpMI5/J
s8ZUxEh3N6SaPUTMBtlbFt62nnGUR8BSPx6xNpjHft65N3D8MnyNwUoaxiF5jyZmli3Ye9euPJpk
tpr8tzkhm+mqOfWrnh6YC6wOo36VeNLL29tZhHPG+XzhbVqj1t1o6Lflpaef8P8e1nfLueBAXAos
hvJ+1/D8hFZis7N+I9kOsK/ts4QlDxXnwXUACHo6nS6+ediDinAvxlSRJVkBDnh9x2UupT/wmWpV
LOvKTfv4/9ccTpiF/6+Z4K7s16m58iG1nr5tayTHj9eq+xtq/XVgokWOI/AvlPHYa1M+GGLEPO4h
y0Ld4Ypo9LmENFgAY7KRnFxujX+grSfz+tJiiULvhK5xcL+H+pukbgvy7hF7sUZzC4mKlaaJgcja
dZXxPUVudBbevACchjTnaH838vqO7f6vn9N2WDAMjViYQcb2OjteHH0io1avNJO6LN0u5Z/BxGiJ
L6PDB3PPEi8+iFiIF6zYSU1kD1C6XQBPlzym0BztEtUx1Hvopmgz7F9Sg7qqTHkITBUH4aaMsXpR
qyrpvoTQYUKbQCZfpzL8DkJrw77hFAFw+Fa3ZCQ7PT2FWAkUzezubjPh40kzSjaKAFfkZbN2qm0U
Gr8IXg1PHQdLcesTh3D0uJbsj1GGdYHMlV6KNx+rNn5LpBafB4oB+0weRGlJwsm/lQmAiIK3GxBS
XR7FMD7djS36sPeCSDUIZAmb26Afq97fmRdVbftrJOiSwPiHkKp2jTS8cZK3LLO2Vuwx3RS6WJ0R
JsvHNqt1lkDqJdrFsDHWZHN3UH/jQJgkhCjAgvo/4bP1fgs3e+8Vww806JoJhsfT/89GDrydvY8A
fj2iFIprpUv1NoMDolCWe7AHLlaRFGsf5COLhW3qKDrSl5iAlYiUVbEYCERth1B68+Xx9aULxMe8
4GV8KTUJvI4s/mlTXrhrbkA8cQpPpg4ZHxIY1xrc47rdyP19k3MGsLLpSVxFY3i3J8Moq51yq1VG
IGp3+5ELe+7e3VWSgTu9ws1bLvjDItgxgbNEFG+yiv7cykZXb/3gSTi2bZOS8ywKS9qjwA8BHyHj
G0DULxEBtFuYIHFIh5Xk0jPSn9lbO7Xur07oGHzwXeBE9MoGBhnxN7Zhn+976V7BPpWuuSh8cfFE
Yr6DmL0pCduDPGNbDXTER1+leirJP9ZJp9j9DGkmcgI+NWueCs/cGj1Js2nt62xOyJEnGNmuKien
FojwXD4CFBPPrIozMwEFwv0eUV/lsvjQB8VrYEXwZVkHOLYGKyNntf+2mYgGPCIgliMaokIz7ELC
Kbh7Cu6yvOiPyh85SBt7XFf5IFzKkVRbFGayIF4BLb0hnIfZYXHfOU1RqGguCNRvXzDqmp3a3Yn3
2IN6Q3PgLKG7B/UBs6kVhIZJkNA1JeoiUCO/w3uKdR6tB3LDMP2aU1Pl4F8fGLovULMF2Qq3gG6o
tPQbnC9DMTc+fQDwWACPQoQwTXLAZzGcAvGtDgBNYQvCcnx0QIChoTDWszGFWZ2cQzXJvG/gw6wz
g8zGiEeDOrSGHNoitYW+k1lx7FrW8yRPfPdpz2vdKD6T9da0d3Gfy40tWeV3ZllxKAMEAhbJl1Y2
1vYJmWWU/nFz6JSA7Fq/IRYHe/9ANTyTOrAENui5qESRYZ1YYxOY7v1GH8c3kFqb1cflDhFdehHa
SPxCWJLMEmtoNRbICkuqMyYeXf6fE4oRp2GVvgJcXVyfbJvpcPLdJzNOWFxv4Ku5UhsELGBiTviq
OlPzz39UDDndJeyQdx2tSgkrVQ8cNV7iN2Zvvr8239TxwVEr1QCj+BwQ1l0HB4VCFyY1125db7s8
gc8lLMekkOpse62RVtMVHoaRcySsYqcb6FqPFxOPkkouDbgKnq2sK1neOh9LD+6LQ5r23ji/qyvW
HoiyQCwIr+8RfRRBu6dYdh3khE/ePDS2UnL+Xr9/zUMW/+QF/bs/saVJNs/Vj6oJxUlM/X/sbD8W
3GL/dQM/VahC/GkUbb2R47Bnq+8PdReb7cRecV3fE+ijFAKwt8ZWswVRSHbPSsdbwoCX7QWMSJCI
2dWJCTUtjAebp2jWLP3ZU9ZRkjpDemB51DOaVGz6NpjsBE+NQrxMQP0HZirpBKny3egZau/rijG3
rEVHGnb9FO7TIqMv81FsBJ+YW660fzOhVFBwT1emw0wNsDkFlBr52iNhovsUm3YNqGcrqjxB3S1Y
1g16hsPoEeOqAMzANwkTCT0/Xo8L852PVF4J99c9LQCSxqMLdndR7GcMMGFqCw/cgf8hgHZ4fC3F
8WmNzcdYZfuRJy0DXbQVHA1HJ/X9ejBmI95DeGlQqJcLKUYI1YL2H3wcey1XzY9uQgR+q1TVbI59
uyvUIcu+MHcqo9ejJRNuL/WnWv0bZ9ktwIQesdJTYX/KxkrzNZJRXp+x0A08D94pbcESeuoVbu7z
sm470JmLNx5n0IxyD5yfYQrGBA3ImSg29PMd7ghRArbCyHRupup8NqWHxvODbHby8dSpI1vT5JP6
AxGE/4qPMCSJtwaoVoJEmNXMN202RibkW6HJ88GFD0L0Saf4Il94KSAtPB8aU1RTZP3QJXQ1d6Dz
/fzYS12HtxvBjYcyclkndBWYaM2ZOxahUJe3uTG3DTKirg6QrQfY3NYFvXUrBV+4YHo1BF2/Q9oz
0z5wQe0Ad5Kc+s+mMResyrEV6GuYw0uDc1rUsTlx+0XpV4KL38sw9GPRQf4C8EWUmh2/tid5o31d
aSlkIL8hmDRqrI04xrF8yGkciS9NK8FlJYg+819vIchRu0ZxS0Xj1BY7SZG4swBUybfXh7HXOJLD
iT+IlvDn9GYGe8OooBBQZeb7p14Xlwyef70eJJBOnujKD9yRwbhUvaYM4EabGGQvr+qvOgBp0Zk8
SgxVfgK8tUKEBwE5di4+qLWEkFo7sazend8QDuUUOzGEovV3PRyPTPPdIQbtcNy92pb+2qlwWQH5
cOMo7jeJU3DdA9D7KYpT/F/lrXmJB0RWRUaFrTwKxoE35h8wcLcNQyawZjW6l6TUuDxHdhkGB/Fv
2aeaArVRU60iWJgFfVDlIZfrbxVIALYUTxBOBJOqCZEdPIA8Zq9lLx2ohLmGFkjLcriXnR1Dir4G
cTJXrAdhCAeqMhGDWJnOEZWoVMROcnkly4Kb2e0uJzFsf4egGRguI+vk11nXlVdR6ZlL0RxRER37
6j9TrMw12HYXNvHZ70qW+Vle6NKf+oBrY5Spz3lMw62kOfc+kfdjoPPMGDD9OLGGbC7nDEal8mzv
NJBrW8e5kqXJtv0RlH7j0l5MdcYQ6UVh+b6/z47d1pccps1RF0isRGpy8emcMp3eU0SwPISTO5Nj
Yy0IuMxqGsY/bsLN9sn63G3nSkjf1gmc/8rKucrxa/gJNCgSnluKD+EFGZOWFBeYVDbcrex8kn14
UHh0HjadbYJTf7JfQgqKAflO8YuNu2qW3R904gOd9FsbcHZsQA+RlJmTbBkrwjjAmwrHnTOpzp3M
5JIP87bN+qBJM51S4Kac0PoHJdnpnAL1xyMF/g15+0tG7CilYL7jQR664Hl4OYcBMtUc0EBbxK84
LTjy68XCy0HrfOPRTqb8+IjVMfo46X1babr6vNVRgxgfoD8oI+22NKABZdGxKYCDBe1emwMZgLwD
dGDARzEpWjsnn/RNc7bAQwts4E0t1MihNDxwP5Khs8APL+juIYTWrvPTQYMV9R/itb5IsZvxxWCv
/WbryWhvOG7FOn0EYnilTlQMFLy1QhWtI+5rmntR9LZUOlDBP+FhFeMOgICUP9t/Yt6vK6v/gp9n
yWmlqRYYr3g1OEDp1DwCTyzRmSALNHseyMkAcHu5hH5cqhiCVR2WKYBIKyWjjo9uvjIVR8oUHFMg
eUuy2hcWQe/+/GRBg0U15wB3rZggVEWkdZbo98NEUaCqQldFx3oHR6JnPDMXSM+ldYjtQesUOU7i
JMIPJkZNb6rdQG4ypJw9PLIL0XiRFL3UyuDkRg738Fcj8oq6YinWpaZFBvjSUloDY1P7FYXo3ds8
cYwipMu1aoDF3QY7I/FLJgHNhlnnLmRiZZs0yU26ikTTY638ZotZcl/yqjLDo71aCAUA8n7xPTGz
DilNhNALFTWNXmeE/FCHYktHn4mop3NrYe1nz1qUJAJpo8f4hCeKj+qB29OG0IroNtQMBirJpBcy
J/qDSiQ7gRTJXiZ8SkfaPSRVjxcMD9zf1ogPd3h4A5lyGK3UT3k63JISxwE+ivMvZLJ7h7ZbQtcE
UATW6roDXbBUbMYhJXZ5RGXhjIlVTHMQVufliMlvG1Lw2Rpi8ZUBoFvCywoHPljLHj86HFtNB5xg
c/Z/mQ8SXN3muIg63nkqkruWTgWMKqpvvnQcRwuXtpjKEAjYG7as/4KFFkrMR0iP8fqXWarAZLQ+
3QVcpooqFatuvDm5oFLGOtAqYjobHjd91KejD6jg8T+W1oTkNmAtPzwm/CgKaDMv1JIEz1LTzBhU
ELCM7YeiaxkCzVQ1QnZbPbbJ16zOh/c5G+HWa0Cg8ncWnxi/zMs9VXjMTsZga5+y4HeQSXd3jwyd
SqBqKpHkyIfavnx370xCiRq+Zszvod6wkPc2typPUWU2kxVjCYARqzB80Gi2QfDVa64BseI1U2tY
9gxXT2w3m4R83KCuxisQa7IwzODVEIEvAZEBjVGXDP7mqwDPoWuZkzb9WDTSUMkeGrPjW6eIJe+G
DhG97+JFtS9sNZ0HtKtEeIr4zPHOtlIwwohzOKeqUCS8YACWptfGXbWgy3joE+OyqH5kbrxkjfuI
ejN+pPSI1h4/zHayB+8tY0YII3t2F1Bn7pMirEONBAubL8hBGIG6HvKd8dBJqLiq1FmuEXhP7wjs
ShbKaCORmJ5n2RQOUvsPEuqQRHWdWLw1G5B1n3i8w1MowkHNQnebiEYhdFySYbzUU2a0BMTEZjjU
9GYieB8cX9Ki6dfvwnwwc14+PlY2kvzy3YorG9ArCxffSU8DwxPeE3PzpGd/ZjFtQIxB+BXcp9uu
HH6lH6cv2Wj2SbRsmkvUXDGDJ9qMk2Ad8whAXioG2D7UMYVmARmadBw673H/wV0UAMZd4n5Aqtsd
LVP2PjzLt+1uGCZm/A04JBBF1VSYCOWXXlYtq2qkwCP7GHF+nW4r8Gm6WqcMpd5ZS8oGtiY/xiD3
BVlDC/XGPmcrdhPz3AOo0PO5IgwoSWh0btpz6nJkyv9SEH/Ofr8g8Wxhs1y4O4IWmrNCmNOQ5WOT
NZecZGaZKfVz38JopmfRQEMAGCTy5OArPyE1JceLg80iEtbf5N6MkjeArw2E1ZTDOOV447Ar8zvE
nP6mXwVAZRVLorOAiX95z8OWMmmxI/3Yicub3N3Dwd6uXqpyoZX4HxHOGO5wpuBWiKVQYmEJZbKe
iR/UOU1AszGjLprttMdu7G7PZm2cQpkdXZ6SfJKyuk6fGtfBVfdK/72yzg9iKEpkRQq/NoAlMgHh
kT35LeZ4pPC8ak5g6rcLQK4bNXIDj/ApKqIqwqSjvtn/7p8ygDp12NbdZRuURvIG+IjG1ln/tP8L
WKmpydb1c7lxeAUEMGzIj1Npl3pGr1Wt8BOkxhm4hn7NKcBsVyO8amFo+qDreJ4Xgr/WyIlzelRr
Yjz11bHtyN3tABq4tk2gBcVwZjWKUMqg+Lnm+b/SGUTrUna4sMODP9lM1At3gp32IB5yUPfFZCHf
pXCoOgeWigFFp71feGukIWryAmSF3hl/JpFuWF3SB+AKERYitC8GzatRTXa1ac/qfG73W29O3KpD
FJ/pixQ9RjwLchlacGtOsxEV8HSfJpvJHgEch7JLEAlhWNPiNVWEfDiuC27TvoJs8b2r8kLJMLwR
UCWrH7MmZ7uziouIg6SbnHx63SrfKee+jTUlxNCjemj6CAMyIu+d1R8X+R9d8Zui7GW/RZY/QMbE
XjLcEpDEkiJt981rITsYEeFEyHMguM6Ju6nIHid8SzRuEWriZRmEIJTAlNIiNLwMJugzTB3crOQl
8IBfaMRzjfCoau+PZND8cAA4s7vNHF4D0OokRek2glXyoRMl1VJLVGmx8Bu37nyNdvu1AQFjSYLt
etkuXnpS0VKHm9ZgA4jv6FmgSt2eUmSa6qrnvPMC3oNUSWtDdl2AajaxIAbvwKZgY/beH1iIkNEv
TjmzzCSq8SktUmBG72Tjfxpu7Va8SzV7CEVoXthUQ2f2wog4l1z5+1Xj+lXv4PQkEAl2xwkSxJln
lEG391BLOkFz8ytRyunEeaf0qbRxQqkLIFbClTxHPYYVF5vUJ66KAE7CRsABWa9FDyp8XMtk5zAl
bNo9Ns/XQjmFKd4k92EtfeH+ZT9RuldWeM+9sVWxeKVSntXZAA6ppscYjsGfRgSp6dGksLyHzi/s
Bwy7i1P0DdbURQM8g+Bp9+W8ADwkj/Tw+QQUXogp7ZwL2NAJyvAOr/16eTgF5Qun4OykMrEfpcJn
4WkkWtbKyL46Afr7gObVr5ukGM5mMGxU8HmBHqGBjJmPyhjCCeTeHkbQxsZZKJUo2WowikWK8shF
CTK2xNy7A3kK54cBBGi8n1gBd/qRP5i/ISxSLP/FIC+/MtUe5aSGnI4+AeAqyw2/4eLsiNpj+tkO
Ogn1Ld4k9ivVN7f+7/htAQEDEDZBODHL8IwVVYvhNTsfsKPs8RpJMMUNun5AN+FM4xOC0OZy7IrD
bUBZLmUkm1x/CggFdLCedKFp1P7Nv/B3wrItPNaJ50/z7IRomLk8I8QSC9zJaLyI9PeAAHlZ3r/r
SZ6scDe1XGNUQQJVnoXM8ivLdua9OY19yh3fZhePtbKbxtsKdShqdFf1gXRJNrQh4L3GTOaJNOTp
DfowShHtYS5OS0FuDNItNDPlDrjb4yaBRNf9k1fUQSgjjTLtpaoEqkuWmAdTZU75T0gmQKeEdRmQ
d/REs26i04OWljHjoXBbg3gVUT+pAS/51KWVMIt6TKU3/oK5N2XAxM0GL9x5sHcle4+Totk0f1UM
pJSDJNAxBvl09xwAvNDkI3rv1If8srNnYf8woVDiL/GAl6aVBgk2Olh5A4fq7NvGkTnRjwBNoR67
76+HULUBRo7ZQOtL31pyt1W6DbOaRUwPMyLEfjjOh/f/4aP2Z0D5xLUz9h1nL4bk9tLuKvhWN2eC
v/VoOzh9knxV4XPU9k6FbNki+i5AoEoRUzkmy857Bo4gHOLS7/OQbbcOVu+42q2PJJSBPt8KF0Og
8O2QpP2/q6e7A7D2tzI/deUI8EwfzhAv5v4cYEK54AqR2yfNmaz54RNgcisOpXnoPzSAmi5Jiy4w
seUpvvUtUt3cF5xBmjd4H1njGi39sQyhQ5/xvuBY2HJMWMXIJTLYgpvKYSqMHJwhi/AxnP9Z3QLR
IliidA7EvSzogBR039dzo8cF0ksFtfGYV+3P/S1fvjP1mkOzPu3XR7pWZIup+YYQq7iK4SmuYhlL
EnmOJxtLHjEWIJ2IVg1C+5bkUVOfkHbXg4BEnClv4C/tHNZWJt6h+hsD/WWW+wNSHvfujeIyxJ1H
aGSCNa6hGHhrwyPdCEMym6iGLtMfytUCK4RcpDVx4uBJFjWnYl/OQ4a/2+zNbyv+pcXIkWLRe8oO
06fRGbxHxbcMiBKDtwfs3ftrHM2ao2hMCrnDOdnWpjoKq9BPYMlreZX8FnxhtVwaIqkJkQvm3WSG
a8OKtxnDF76zPPrInP3CfNyM29okOqqlHKpUaEFkzRlaInutn/9EbtmcunIPVSHv2wrPgK9EbXyq
vDFW4nPn2G8q0NKET+jEWcTOfZhlcSR3MVqAAc8Eyn315NtKWhy6C8cdBOi1PNJruNo/R6+crqw0
U2R5NmesHfliHs7RN/ixyEvnevb2pZvwg01GfKMB9salRlBuPM1gnvkXNXXUEG1N3QoyLDgQW9Uy
qFwWVVNwl4tSF1bm4asF/r3tMU9AAYIos9ioMRHi4aSxnBOUm+vznfIp+f972/MxZenx6R8J+S5t
jN3icf8ZUTPX+zVK+QvPTZT1Z4ykXOCk3VjtQyHx/3ba/vOuftcVJl7asj57uzOKZ+y6RLoGADkq
PZsPM9L0XluYwd6zYAWZDz+LHeZgo5+aTPuDQ0OrsZjMV9LfjsEnoHLQe1NFOf8jSq/RAthRjbEL
vlvJZOxaTM0B812GC1dvy70EC3ANFCa1p1i9qZZbsUl2DG2SF+Q0P8s9PU+Yg6TKXx+iBSFoiVc1
7aO1HcaJlBuWPsN4UfqiIxXfmss3KXOd1Ev+U+VxTIx0+SAV7QsFrNz1xcXgK3r/YYffvSTfwhbg
HiBD7FlLBC1/HndfD0yqpu40/OMyjCclh1KjlssFnip/U0AcO4aYcWgMr4yr9p/LXO2/PyaC6s4K
246JXCxMfl06I48Pj6ylR4AfEc6ypfhm2Wb5gu1Dyp/5yNJjWSA4hDog/vJdelIo0Wu0vGLLuwLs
HbXG4yph/T4B6KoB8muzBPRiqWHxixRXcsRJTgeJYjWyBCsZrPrl4LAWoYbVDVGvIK1ZnnxM3bYk
CgznsbVv8CeANMXSCperCepOFVg39YQ3gwIc+V3fdyhyzeVKqqyAXNwANyMuHPv8sIUKXGzZUN7Q
v55m9YKKN/lMd/CixzHkc8NBSjIsdk3YGcSPuZGMU6Vh0+6c5RSgjNeXr/Um/3oIpHHIePt6oLys
Z0+cVcM3BdNznioVMDL8uN2UNNCgL+KTMeVk+be4GSmos3o+c+gonMuxHwGLDxQQk6/eUhUVCgVv
JNepm1O87ulOjRPtSJpmTVOlxCj0FU5c5eb31dWiNUqbldnxjj95VywbKMb1ixDVFOtl+Jx0ciU6
QGO0OogJ9oGfSw7snkftcNPGciuyqkzZXzqjPWhVf/7exsUFK+sTCse/lV2qEOgpLkrZjFA8rFY7
pJ0p0KWR5f5EGq5KorIAuRhce1hTp4bHOTSwyYunl5fOArBLMZ+UEv4L/LJ8aouAZvyC2zXG0FMq
+wrWT2HG/AFuVLR6PzyW01kqKAIenBFqjgq27me0C0CoX93Yh8ZD6IE1fhdkfzPiUuw1DHnNpqEg
dospkG+6eYM/rqt/40hO0028egQ76/QNdv6qAl9FTTRTTArX1mHhm6sROHC4sJLZ0e3+wbqsLYe+
R2YY5uAcdBqJ9jEXpR0XJe7GNrUTzhWr0LCFJV2pfxgKxI1a/iwcbkplDaNO42tpp7RhexYW4wAV
mw5nVhOMKgK521XK5gLopBacJ8kt+wKKAIBPx0gkoUF2Xvczn7yRXrOOAM+PA6O7VBdPrSxJjklS
cTMbv4trZ9YCFsDEKa1NZ9JUpqVHOt4V6pTOEgJG/K9SyOBkvqOlYkwSSt3Phfjn7SAjrGZkswcl
0enWzIcPl1PUWmnesZZ7DZHJdDDGbgWPE5pw5DdypeUq0rC0RgTtd8CWE2QqLU8sK2CHLH0/sasK
riMsChZfTuYlZ/NxfNIL/OvK9RFlkBw7UZ/Ti7HWHnhDGKNAGMVkv+SAq3xlbV7CLVNIvugAVrLj
uFEOAIi3/n3xmhku197aprimHrJeOuwravlUi7x1jbNDgV8O3W7X33pMUM1DPvI2SwSYdEK/j1jb
bUWeZc77HLcw/AlV1UEe1wTD37N85KyT+rtCNcx/nh+VlyeXfY20bDM8kwbknIWO7OrbavBb+t4/
jq0rc7Z+MgNxDelbKOsyyuFfhdfXprg3GyU7VD7nDhvsdZSP/dgwvjOSnG9bRa/GXNOWyLjXjWgS
Pedybov+gsNkkLxSXezxlzfpPaijgzax7NqRcDXUBbTXmHoXVnRbi+y+E6rUVA4W2+x9pMMBSobP
AEsB5+HTgvOkNwEIWiuuMBDSHmKtQwiccjeCwG3nyrgWIqWcG+DG7rdLD/m4UoQWzRHHsGG3bhaM
mFGrIo528l/2zy9fk+PRsEspBn9eeEbzOWv9ig5GOXcMOLeqLM/Kat7Xsg7FwI84ZjSfDNuL25eB
RIpCdlJpeGdiOjFNFG9yojRX4eq3h88zaX28sRLQmByD3UPgLwE6dpvCcqX2Fdtxjo2/eJmWpzt4
4OXvVc2sfQ3awRozhcCL6Ixfc78SyBCCcDiNbRmZr2kHvf8Tms5bdyaxT7+cw7pjjkW1BRyqSy/Z
DInqnjnOkjTmP55NJ8yUE7fh3Ef7Xejws9fTIfKo34G4WYkqkleeLCSJ5LDwhXVrX0ZI6pIphBCf
ya0gMoSXcJCfgm3R07tyLDG2yfrrwvvFw7XyvUDZfean4tkK/DnKOci3ubcgvTku5wRyVH36RCi2
/qr/LKF0qHIYg76szxAcMBBrxKbAMuu1E/PEt0PgiQsYrTsInsWOQ6BkBru3FzbPV54m2jwMQse/
O/42zoPz19Xagk54mH1irmDCmPrvOrchD6RH4Jgt1iH9of+t1dtFl9x16Ib5W55ySo26X627QjHz
yWSVi+lQcQK/X3Z9L2qgv45VLr7OCn4nCsmGL9M/R0gFZcyod5Zx2mEV4MdjLJJ82I827eapPP/O
S0DrlrXkKKse7N1LrF0oQPODUbqCq5otDfp1vlyO/QkFjBRR9tqNHjJT8sIYx1IG66jkQK/RhY1u
j7w4TgFASabJRvBwwI/5iAyc2koBr6KckhZ7OUdasskAIWgUUr4DhqBbq4evRweAhHVVXDbLo7n6
Pmb4XrBLitPcLX230wlr8gXbBNPOpPT3Ud2zSyLFIKC5tGjT79AGmIpfqnjsgBNEiLCrLjvNklc+
qfUrE4zJ0khjRzr1kVnGjoBC/jqDcLl4V5yx+FO10hsshujdvnxJRBogQCvwybZlEbjDjmazHuz/
v4mN+W82KL+f/lRYXFJHc5IDxFQzVGhRsjmRiMdBRL+6SnacTIJ3/gUqxu17hPHqxB9kH/R4rxRo
924+PvEtLofz1hQZ5lZTklva/tExBkXUsFpjfTElCK+zskttzhPoPkUnQDcMSDXVeHQDx03GXPal
E8QMZzzS59Ej2vYEHI0yOra8eGzmGHq2tOiQYWvsHEpVmdoP1ELpsB/Mn+QxZ5St+V/CWbIEjSRN
bi3LgpynSwSc8PtuR0pNCyzA9gxllslN52feZJKR9aXADMBKLVIq6oAmMhJmXRuENPnOP4L1kTB0
+/7hco31aoZx5Xz2FRYrX5SqsvjPjDIwhsDVYoZvNIaN7vYyyRm8kje3ehPmfKgseGBx862zpvt9
BlblvRsCRSoMvKJv0C1tNYqMiSZYj7R9LuEx3xCKmeDv/YfBM20DQT1h05ot3fFdrFUivBv8GvnW
HSlq9CTrnErOLn51140xfjmqZiTcCL2Hfxs0HXFDzdmqgzZNVTeuJtxRUEBZOvx8BLtNHJqNINQH
sXOLvx7Mc3XBnJmR5Xtug18YAFSuNBJEqiooy7NLwDgL70/8HaQXeIJH0TLDr9aUqQLSeudO3wo9
GINngGxPEv7JPucjhkf+hpf7bX68Ebb+omVu2j+ash2ULjx9EFzH0SPh8YE6wbnc/kFwCZoxccDj
VEx82tPKgmZU5hkLEV8rS8eca3+QGw8BR/pmRZBoVuNwj5N72aIcvmqUYffD4VQ6E3+QEGeIB+wB
ynk9vA9WUExcAcR0Lm+OAAsDrwRpmZD83EXJPbllGe48BB5fVzziP78RINoZCfgBPltdHESgltI4
vTKLI30rnpyF0bLnO4xczINdy+JVd9P1ozOuRNYAUL9RZNX+SJ9JYrajMboKKK7d/SnhRkjV0rXg
uubO3UYSEIxPC5ZImki/19ALb2t5TkL3lC0fmihXH6GYaIHhhNeuOoXQO6tQCmVNWhC307ZZTXR9
7rYlYMd8djcIQC4W92VmKGc9c4DcK/RDusTKXtQjYHqwnEuaUGuUCdY9ED7A71215OsjNGxQ228G
jFcdcM0wqyr4GUcDOK8WrYbvrGqBZZwosgZJEtyKk7FYrb6zvdqHN0y5YPDtRgr/8CVfn6xGkOvg
k6TaPQYl4JBP2fOgF18J2y9RPDTR1DZj7xwAeGv3SjuKffYjV3hDwfQQktFuk60X3ewzoMN2x7vW
LdEQYN7MvHpG3745q8iEm1s9Zpj9AztiEC1qJPs3aftpDNNPipuC1hOkMs2fFrkiZin+03uxQYlh
OvgVFRCntkLKAibVQ2Tntyr9qcs6+zAjlnknSGkh5/0Iy15GhiRofwJhnKiaMbW6ZW5JRMoVRaot
fn0GBmSxOL10K13MIdq4Ny1WFHRPSMRgfZFqnmT35kJhCWflJV/lXVCShVcqO+Ge65Srl6j25Wqw
pBwbnS/g7pcSFVO2NaUYgp6zKblyGyCXZ51Hqcmv0cHQRBmEBDByH7S0wkpMk1vZFQLihl0gp1Kg
uKTZI0K5GFA+st/LJHbUn7Cso6tg64h1D3uhOqj4FdWPwDDZuO2hEcxSg1JLlhDnRUjRbGN405Jv
oPMU+MZgYrBXglKpbgAPQ/bC2AJOqCn8LCYhXJ2aBr4W1zrGCSfvSJpFFCztiVQjX5dhBccdy6Sm
ySFKHeOrUwMQiTtPNd5caxd3mKeMXKtGXifcZTvJ9hv0NuRr8QatcebprlIUUxt0dbXTx8yrTvRW
ALCKibrNV+BPIqtIv6AbUCx1jirvteBiYQ5K6kq6j2SK5RrfsEYorN0clIwNl9mBi6uejTEaRTvh
+4pFD4olrH5D7hZfuj0MUJ/2MMSWFOK+1pdUlkuUssGXBGX6S5KM4yjPoeqWwVePqinLIdvdyjsE
D0UAotFGjIZfZaE0de4BP1k91/v3cdwLMDoy8XmQ80fQqUPFIEGaB+yYeudxNo93VAD9SdUcMpNg
/if1cSjlXx0nsrKa4knDN+zxc51i/Gi0rtm+MwgoQplQyd2+WuOCp3BhdkJerQf8zQoFo8CDS7+K
YA2BUrW/fJxaQphmk/kS+0GbenbTtMm9eR8+eVzJJ4qyOgSryzkBXH/ZUpp8fjmuGrmrXoEJRREF
P7ZbmFzJBiPgBn040r0vIxOO1dbWbZxbmcdow/fhRIs8WN1u46aPh9z5zbQZhQEwDBp8JU11kuVN
QHvGCqDa8TA8AT8gByF3j0UVI1Eq7DNjJrTQMlpe966u92RkriRfXnbmLAvDdTeYmt2lm2Gjl1Rt
140NzzfyquW1akUJYDPhVrRyB9yxgJPhpQjBI5hd0AzfBO4y8IXVEvmHqmcPRgEsJhAEWHyqIUFz
fT6E1iITk9V1VBcrhwHRFLQM75v4dwiG9qFQeVqzuw6naU2L73XWvMcCDEcf1bEmblV1fVHevRGM
fmBWpkLMT45C+OBO+MhHbluBuWOVuRtJ2mHXghyK2xQfnn4GstkWlt55LnNuE4Wa2n/1ApzmoFci
JGEjRpw/sMvql0zvLSbEKVyDyWGT63BOYE9Aad0ReAgO74/UImUGTZ85yGKoYW91h+5UHNoydYqB
fuA8iBBK6hVXq+xCIs9sGyNtSStCb4Rp53k6UhgaHpF2imjgPiOKIlFV9/G6N89UDKVlUToVWDSG
YIpfmoqlEzpNus69p/NjWcmej7wbxso072bg4Zpg8YzktToOg9jiBOb8JKfZbj2dO89pqw/jftZR
Tup2jiAIo4JIA5J01Gkce4WLz17BrUdrbTEUQqFTqEmL4dhzwsfzZmuyQ0qjcK+T9zS+1BoPTF+T
eT3y/CgiBiygQjB34qVHb5AzDKifyEHdp3RanQq8fywxigVHOwnXhOvRZbKFisbo3wW6sAB/xXKW
dKxFg31Va0CzB8Qae3XoBt3oB6Hr34mqB0Ht+IPZqZitKje5pZr0F4JQDOyYfeUhVLFqBPREU5au
A0oBAb5BPRnHEdXW2T3eVJRPvL1qcPIMyyFg9fhi19q6U78+qPTDMtcmxamjld6Nu3/OzZBPb/bw
1kfD1GMJSAZea9xPuLmE00yPBglskXv0wc6ZttReBVKvfmsoyUkmVA/oC/mAK8I5QIJ5eX+XNfv5
COWuoHhSQXUSFNZLxgAd/cH2sALVMlJ7DQF6GfSERSzNFtsbOfOh7kMbP846nqYBk4ABzibGCeGU
0iouq41a0k750x/984lROTPlUCgRfpjxzte74Iw5F7Aye67imQZuysyjmtAfWk5K5kdzIFmUImY1
UQDGTVtS0gTr2zojxi1RcWlitfIiajvoc93/M10d+5/5LZ7VkskgxkttQE4nYY6lg3L+HhBDaFkH
pZqoX4ZlXKQ3j0OvsklDn4Eqavs2+AAMn2jtF828tlQJPm6ERgBd03xSoA8HzJTr/yjzni55fWyW
xYgp372PqVP9Eoz8loGOQske3ZBYRt+Cu4uZMwOSl1LyyZ9lHcVCDf9ryFWUBgELmG+LIim1RUSx
Etn4p0Ms7uwGswsVmMJx9sZOjCAqKzEbJm/RIcyosuOkNcn+BL9CWvS34zNB0qnZsYkpk1Ovv5Yl
MOYshJGX+II+Ae6jVA4O4NCJYletaPaCASobQCqE5eOWItRBMck4Ppp4L2mwXzWyt4NcfyeBna3u
9dWTG2VkZtTHyYJDMXOlxlIvBcDRAl5r0lP3RcxT9+Kp+L0U7gSA3GSBF9xHUYfean7j6wvKOHLx
nk2g5JA9oQQ5TPwI/xINqqLm2rP5RoiksJf2SugjHDPbiWlZM0j++nXRpmmZOxXu8ENYOoJR9kdk
WXjNNn+F/nMmPlyUOBKzc2a0PF53W1mrhpntfPUT7xcdcc8OpwJRK32H8S85kEZFYY/VtSWUqCQm
9pbQmagifTey0LL46v5M5faq7/A0dv/ZaOVPfDW1NGp6TomoSaHq5BRop/U0OQ8DBYFfI5L1uGYu
2I2aQrAmdAnShUs1f7QTOWqnyKmNHCYj2zqUBjxMDrPa2d5Oa8ac8tGXEmwiK1bbCSEJHVoAyuWA
OVASXh/tDtT2rAEW2RSTmgedPDppooWi7W0BB3xjzQgz5tZ2kQpDB5LL+bZ8m3qU/IRnQKXCjw1y
oQjk4ZoYJM5dUdMEhXaY/uGQhB50m2Y4vGICCMdlZ1jjRE29XgfviShgZ0ii23dP0+UmiTYkSdmW
+csObdxfbSVW+ZcVbdqmJKMRqAhxfbweoc1W75cGOXZzZO3PZcgiQvs8863PNinu4tXa+FHIl+sX
c8ut/kl4bZUCUpjT2aim2oVzrib9RYthSefZFRPncHoRxsakaxdQzI35jTiDrO1yqB9dnMR26f1E
7R46fLT+IU7gVuQebSsnm15h7CBE7GitTf7a2Wd4lfwFF96D2gxlJIS+K8EQGt0zAMsBe586A5FO
kr/oVhZB19yWgnwuvHS8E+VuXidoV+ged7CGaD8dB0BR/yfGTehMCrql2KqgyD/DDF0GOqTcsEG/
3wiO4j86SIAYVQC6D0Q9u56s8MNK4nUaM0qFRl8G6bP2Yf84gg0CQHtxjJmrPS5yJqEQXSLK/+RU
Y46+0Y9XsORLoghM3ZDnLkL7q0zWzLvOImM9LOuhVcHx+fl22Tw95Do3N1qJxFc3pY1HhfpbhkMv
HwgxMX3RSkbmTfMjHcDzFbVu5cymnUSfxpxINXTnBiErIXfGENwB235wgIfn7JQQy8u981Rg5f6w
SUeOpCtuq8QtaQ/B1x+ZN/pmninpCK+PZFIkZUgjoBfMvn3/EmdWIetcVU+CAayqsYnfeengCwkb
Q0yoPTgv9IpPPJpZDyhW1MhLIj2dcCut8LtKcoVoCfG1ADkvt6GLJu61HrXhoSv8EIHy0NXwfDDT
FlCHFTEh8jtZHx/TwyU/iMRauLZRxuHQvleSlfus6h/i7aPl7PsadjvTIVv7xCN6aXZAxTVDg8NJ
wHmTMNrf89yySt2vwR+bBZixL+lAp3EctrCMszwwGamZdvUahpzt2uWrqtPm75zRSPk+hbUOPZbl
EopqNiSoOybEsm0KyTe/xhsxOVZPN+ftFIhn114LTsjUZYDFoUBxRhFqLFjL26afoFK65iRUBE9n
Wgi7+iEzH7Ar8vn5X+MaoncF18Y67sk4E+NsY0tKwkHsJCIC7q8oDWrIpI+mpUGmhc6HL4gq+3A4
wMlTA1PtdDj9rhB2Dx5qHew/oU54BNIhOmEn9XU6xKuLahA+8aL4rpcWEKMj7eQUu9g27fV074Dv
9FlDO99z2gCMZK0XW1U4JQbeSdXDzSTE83EsA0jjLodkelx045vujrhcbfq3FLkzU0gRlLE7HGcK
n2XOwPkRvFRc/TWrlul15CB1NT64F7MDbhk+MytHzXxSZRnqaS6w1/kF4Pfd9ZDXmYl/2dzJBb6j
3nCh8B2WQIgD1SH/mYB0AcdotsVj+hsU8Gk9vMEDa4zAuoR+WWzf4xMALJRy6g8+jeDrlHWTV44v
/wi0RE5qrVy8LXsG9qWficyY2UFiZ74tsevA3g+71UIu3THm28X4yQcxW8I0J8YABxPebHs3MSx4
qsiSeT6NjznbFHy8sD9FJxx+tCk3b6DfXKYVb9JfOB+DFKH4HkDeN3A7pCYuNef0pJRJwa8aNbp8
Smi6ozWoRiuCiuxcfKxbcGMIfU2LLeooVkWZoyQ7NpIlzzscehfQwqqMuo01VnFRUugoja8UiWrM
LS97WERraUvgXYptaAaVGGPKdZ9Bqt0hSdjnPX9jnz/PpS1MMoidENaESTmaKceXLnj91YtqF3s6
xyEoemHoaKqEkgqKbKLTL2+zndcMaHiCnpJOFthU5vjbOJ9APAzE6SVQxvzyBvM6zahE2iTr2dVs
SDet7CPp9zM45/bYA8Th0NVcYMAGeAlf3KVf/a3xH/EIbpFSaZXY04QQlCmrHmAeA+AvimLBcFFR
2HdgSEcUk9x8g81XyUwQDPGAb2ydteHRwCM9oBidlm/oRgykZesT73limi5kwrMX22EuvIJ66D0b
X9OcuUCA1yE3UHZoIbPA30IUF7fx121l1eRCmTuh
`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity busgate4 is
port(
in_bus: in std_logic_vector(3 downto 0);
is_enabled: in std_logic;
out_bus: out std_logic_vector(3 downto 0)
);
end;
architecture logic of busgate4 is
signal tmp_enabled: std_logic_vector(3 downto 0);
begin
tmp_enabled <= (others => is_enabled);
out_bus <= in_bus and tmp_enabled;
end;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity busmux4x4 is
port (
in_bus: in std_logic_vector(15 downto 0);
sel: in std_logic_vector(3 downto 0);
out_bus: out std_logic_vector(3 downto 0)
);
end;
architecture logic of busmux4x4 is
component busgate4
port(
in_bus: in std_logic_vector(3 downto 0);
is_enabled: in std_logic;
out_bus: out std_logic_vector(3 downto 0)
);
end component;
signal internal_bus: std_logic_vector(15 downto 0);
begin
cell1: busgate4 port map (in_bus=>in_bus(3 downto 0), is_enabled=>sel(0), out_bus=>internal_bus(3 downto 0));
cell2: busgate4 port map (in_bus=>in_bus(7 downto 4), is_enabled=>sel(1), out_bus=>internal_bus(7 downto 4));
cell3: busgate4 port map (in_bus=>in_bus(11 downto 8), is_enabled=>sel(2), out_bus=>internal_bus(11 downto 8));
cell4: busgate4 port map (in_bus=>in_bus(15 downto 12), is_enabled=>sel(3), out_bus=>internal_bus(15 downto 12));
out_bus <= internal_bus(3 downto 0) or internal_bus(7 downto 4) or internal_bus(11 downto 8) or internal_bus(15 downto 12);
end logic; |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity w_split0 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end w_split0;
architecture augh of w_split0 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (
"00000111", "00000111"
);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity w_split0 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end w_split0;
architecture augh of w_split0 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (
"00000111", "00000111"
);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
entity tb_iassoc01 is
end tb_iassoc01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_iassoc01 is
signal a : natural;
signal b : natural;
signal res : natural;
begin
dut: entity work.iassoc01
port map (a, b, res);
process
begin
a <= 1;
b <= 5;
wait for 1 ns;
assert res = 6 severity failure;
a <= 197;
b <= 203;
wait for 1 ns;
assert res = 400 severity failure;
wait;
end process;
end behav;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:32:49 11/21/2015
-- Design Name:
-- Module Name: FSM_robot - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 1.1.0 - Main Robot Implementation
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.PKG_ROBOT_SUMO.all;
entity FSM_robot is
port (
in_pres_state : in robot_state_values;
in_color_1 : in STD_LOGIC;
in_sonic_1 : in STD_LOGIC;
out_next_state_fsmr : out robot_state_values);
end FSM_robot;
architecture Behavioral of FSM_robot is
begin
fsm: process (in_pres_state, in_color_1, in_sonic_1)
begin
case in_pres_state is
when ROBOT_DETECT =>
out_next_state_fsmr <= ROBOT_FOWARD;
when ROBOT_FOWARD =>
if(in_color_1 = '1')then
out_next_state_fsmr <= ROBOT_REVERSE;
elsif(in_sonic_1 = '0')then
out_next_state_fsmr <= ROBOT_STOP;
else
out_next_state_fsmr <= ROBOT_FOWARD;
end if;
when ROBOT_REVERSE =>
if(in_color_1 = '0') then
out_next_state_fsmr <= ROBOT_STOP;
else
out_next_state_fsmr <= ROBOT_REVERSE;
end if;
when ROBOT_STOP =>
out_next_state_fsmr <= ROBOT_DETECT;
when others =>
out_next_state_fsmr <= ROBOT_DETECT;
end case;
end process fsm;
end Behavioral;
|
-- NEED RESULT: ARCH00697: Positional and named associations in same association list passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00697
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.3.2 (3)
-- 4.3.3.2 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00697(ARCH00697)
-- ENT00697_Test_Bench(ARCH00697_Test_Bench)
--
-- REVISION HISTORY:
--
-- 09-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00697 is
generic (
g_integer : integer ;
g_boolean : boolean ;
g_st_arr3 : st_arr3
) ;
port (
p_integer : integer ;
p_boolean : boolean ;
p_st_arr3 : st_arr3
) ;
end ENT00697 ;
--
architecture ARCH00697 of ENT00697 is
procedure p1 (
pc_integer : integer ;
pc_boolean : boolean ;
pc_st_arr3 : st_arr3 ;
pv_integer : inout integer ;
pv_boolean : inout boolean ;
pv_st_arr3 : inout st_arr3 ;
signal ps_integer : integer ;
signal ps_boolean : boolean ;
signal ps_st_arr3 : st_arr3
) is
variable correct : boolean := true ;
begin
correct := correct and pc_integer = -4 ;
correct := correct and not pc_boolean ;
correct := correct and pc_st_arr3 = c_st_arr3_2 ;
correct := correct and pv_integer = 0 ;
correct := correct and pv_boolean ;
correct := correct and pv_st_arr3 = c_st_arr3_1 ;
correct := correct and ps_integer = 5 ;
correct := correct and ps_boolean ;
correct := correct and ps_st_arr3 = c_st_arr3_1 ;
test_report ( "ARCH00697" ,
"Positional and named associations in same association"
& " list" ,
correct ) ;
end p1 ;
begin
process
variable v_integer : integer := 0 ;
variable v_boolean : boolean := true ;
variable v_st_arr3 : st_arr3 := c_st_arr3_1 ;
begin
p1 (
g_integer + p_integer ,
boolean'val(boolean'pos(g_boolean and v_boolean) - 3 mod 2) ,
st_arr3 ' (g_st_arr3) ,
v_integer ,
v_boolean ,
v_st_arr3 ,
ps_integer => p_integer ,
ps_boolean => p_boolean ,
ps_st_arr3 => p_st_arr3
) ;
wait ;
end process ;
end ARCH00697 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00697_Test_Bench is
end ENT00697_Test_Bench ;
--
architecture ARCH00697_Test_Bench of ENT00697_Test_Bench is
begin
L1:
block
signal s_integer : integer := 5 ;
signal s_boolean : boolean := true ;
signal s_st_arr3 : st_arr3 := c_st_arr3_1 ;
constant c_integer : integer := -6 ;
constant c_boolean : boolean := false ;
constant c_st_arr3 : st_arr3 := c_st_arr3_2 ;
component UUT
generic (
lg_integer : integer ;
lg_boolean : boolean ;
lg_st_arr3 : st_arr3
) ;
port (
lp_integer : integer ;
lp_boolean : boolean ;
lp_st_arr3 : st_arr3
) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00697 ( ARCH00697 )
generic map (
lg_integer ,
g_boolean => lg_boolean ,
g_st_arr3 => lg_st_arr3
)
port map (
lp_integer ,
p_boolean => lp_boolean ,
p_st_arr3 => lp_st_arr3
) ;
begin
CIS1 : UUT
generic map (
c_integer - 3 ,
lg_boolean => boolean'succ(c_boolean) ,
lg_st_arr3 => c_st_arr3
)
port map (
s_integer ,
lp_boolean => s_boolean ,
lp_st_arr3 => s_st_arr3
) ;
end block L1 ;
end ARCH00697_Test_Bench ;
--
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (burst of 2), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_timing.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_32_tb is
end ext_mem_test_32_tb;
architecture tb of ext_mem_test_32_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req_16 : t_mem_burst_16_req := c_mem_burst_16_req_init;
signal resp_16 : t_mem_burst_16_resp;
signal req_32 : t_mem_burst_32_req := c_mem_burst_32_req_init;
signal resp_32 : t_mem_burst_32_resp;
signal okay : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal MEM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(12 downto 0);
signal logic_BA : std_logic_vector(1 downto 0);
signal dummy_data : std_logic_vector(15 downto 0) := (others => 'H');
signal dummy_dqm : std_logic_vector(1 downto 0) := (others => 'H');
constant c_wire_delay : VitalDelayType01 := ( 2 ns, 3 ns );
begin
clock <= not clock after 10.2 ns;
clk_2x <= not clk_2x after 5.1 ns;
reset <= '1', '0' after 100 ns;
i_checker: entity work.ext_mem_test_32
port map (
clock => clock,
reset => reset,
req => req_32,
resp => resp_32,
okay => okay );
i_convert: entity work.mem_16to32
port map (
clock => clock,
reset => reset,
req_16 => req_16,
resp_16 => resp_16,
req_32 => req_32,
resp_32 => resp_32 );
i_mut: entity work.ext_mem_ctrl_v6
generic map (
q_tcko_data => 5 ns,
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req_16,
resp => resp_16,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
SDRAM_BA => logic_BA,
SDRAM_A => logic_A,
SDRAM_DQ => MEM_D );
i_sdram : entity work.mt48lc16m16a2
generic map(
tipd_BA0 => c_wire_delay,
tipd_BA1 => c_wire_delay,
tipd_DQMH => c_wire_delay,
tipd_DQML => c_wire_delay,
tipd_DQ0 => c_wire_delay,
tipd_DQ1 => c_wire_delay,
tipd_DQ2 => c_wire_delay,
tipd_DQ3 => c_wire_delay,
tipd_DQ4 => c_wire_delay,
tipd_DQ5 => c_wire_delay,
tipd_DQ6 => c_wire_delay,
tipd_DQ7 => c_wire_delay,
tipd_DQ8 => c_wire_delay,
tipd_DQ9 => c_wire_delay,
tipd_DQ10 => c_wire_delay,
tipd_DQ11 => c_wire_delay,
tipd_DQ12 => c_wire_delay,
tipd_DQ13 => c_wire_delay,
tipd_DQ14 => c_wire_delay,
tipd_DQ15 => c_wire_delay,
tipd_CLK => c_wire_delay,
tipd_CKE => c_wire_delay,
tipd_A0 => c_wire_delay,
tipd_A1 => c_wire_delay,
tipd_A2 => c_wire_delay,
tipd_A3 => c_wire_delay,
tipd_A4 => c_wire_delay,
tipd_A5 => c_wire_delay,
tipd_A6 => c_wire_delay,
tipd_A7 => c_wire_delay,
tipd_A8 => c_wire_delay,
tipd_A9 => c_wire_delay,
tipd_A10 => c_wire_delay,
tipd_A11 => c_wire_delay,
tipd_A12 => c_wire_delay,
tipd_WENeg => c_wire_delay,
tipd_RASNeg => c_wire_delay,
tipd_CSNeg => c_wire_delay,
tipd_CASNeg => c_wire_delay,
-- tpd delays
tpd_CLK_DQ2 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
tpd_CLK_DQ3 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
-- -- tpw values: pulse widths
-- tpw_CLK_posedge : VitalDelayType := UnitDelay;
-- tpw_CLK_negedge : VitalDelayType := UnitDelay;
-- -- tsetup values: setup times
-- tsetup_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- thold values: hold times
-- thold_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- tperiod_min: minimum clock period = 1/max freq
-- tperiod_CLK_posedge : VitalDelayType := UnitDelay;
--
mem_file_name => "none",
tpowerup => 100 ns )
port map(
BA0 => logic_BA(0),
BA1 => logic_BA(1),
DQMH => dummy_dqm(1),
DQML => logic_DQM,
DQ0 => MEM_D(0),
DQ1 => MEM_D(1),
DQ2 => MEM_D(2),
DQ3 => MEM_D(3),
DQ4 => MEM_D(4),
DQ5 => MEM_D(5),
DQ6 => MEM_D(6),
DQ7 => MEM_D(7),
DQ8 => dummy_data(8),
DQ9 => dummy_data(9),
DQ10 => dummy_data(10),
DQ11 => dummy_data(11),
DQ12 => dummy_data(12),
DQ13 => dummy_data(13),
DQ14 => dummy_data(14),
DQ15 => dummy_data(15),
CLK => logic_CLK,
CKE => logic_CKE,
A0 => logic_A(0),
A1 => logic_A(1),
A2 => logic_A(2),
A3 => logic_A(3),
A4 => logic_A(4),
A5 => logic_A(5),
A6 => logic_A(6),
A7 => logic_A(7),
A8 => logic_A(8),
A9 => logic_A(9),
A10 => logic_A(10),
A11 => logic_A(11),
A12 => logic_A(12),
WENeg => logic_WEn,
RASNeg => logic_RASn,
CSNeg => logic_CSn,
CASNeg => logic_CASn );
end;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (burst of 2), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_timing.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_32_tb is
end ext_mem_test_32_tb;
architecture tb of ext_mem_test_32_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req_16 : t_mem_burst_16_req := c_mem_burst_16_req_init;
signal resp_16 : t_mem_burst_16_resp;
signal req_32 : t_mem_burst_32_req := c_mem_burst_32_req_init;
signal resp_32 : t_mem_burst_32_resp;
signal okay : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal MEM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(12 downto 0);
signal logic_BA : std_logic_vector(1 downto 0);
signal dummy_data : std_logic_vector(15 downto 0) := (others => 'H');
signal dummy_dqm : std_logic_vector(1 downto 0) := (others => 'H');
constant c_wire_delay : VitalDelayType01 := ( 2 ns, 3 ns );
begin
clock <= not clock after 10.2 ns;
clk_2x <= not clk_2x after 5.1 ns;
reset <= '1', '0' after 100 ns;
i_checker: entity work.ext_mem_test_32
port map (
clock => clock,
reset => reset,
req => req_32,
resp => resp_32,
okay => okay );
i_convert: entity work.mem_16to32
port map (
clock => clock,
reset => reset,
req_16 => req_16,
resp_16 => resp_16,
req_32 => req_32,
resp_32 => resp_32 );
i_mut: entity work.ext_mem_ctrl_v6
generic map (
q_tcko_data => 5 ns,
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req_16,
resp => resp_16,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
SDRAM_BA => logic_BA,
SDRAM_A => logic_A,
SDRAM_DQ => MEM_D );
i_sdram : entity work.mt48lc16m16a2
generic map(
tipd_BA0 => c_wire_delay,
tipd_BA1 => c_wire_delay,
tipd_DQMH => c_wire_delay,
tipd_DQML => c_wire_delay,
tipd_DQ0 => c_wire_delay,
tipd_DQ1 => c_wire_delay,
tipd_DQ2 => c_wire_delay,
tipd_DQ3 => c_wire_delay,
tipd_DQ4 => c_wire_delay,
tipd_DQ5 => c_wire_delay,
tipd_DQ6 => c_wire_delay,
tipd_DQ7 => c_wire_delay,
tipd_DQ8 => c_wire_delay,
tipd_DQ9 => c_wire_delay,
tipd_DQ10 => c_wire_delay,
tipd_DQ11 => c_wire_delay,
tipd_DQ12 => c_wire_delay,
tipd_DQ13 => c_wire_delay,
tipd_DQ14 => c_wire_delay,
tipd_DQ15 => c_wire_delay,
tipd_CLK => c_wire_delay,
tipd_CKE => c_wire_delay,
tipd_A0 => c_wire_delay,
tipd_A1 => c_wire_delay,
tipd_A2 => c_wire_delay,
tipd_A3 => c_wire_delay,
tipd_A4 => c_wire_delay,
tipd_A5 => c_wire_delay,
tipd_A6 => c_wire_delay,
tipd_A7 => c_wire_delay,
tipd_A8 => c_wire_delay,
tipd_A9 => c_wire_delay,
tipd_A10 => c_wire_delay,
tipd_A11 => c_wire_delay,
tipd_A12 => c_wire_delay,
tipd_WENeg => c_wire_delay,
tipd_RASNeg => c_wire_delay,
tipd_CSNeg => c_wire_delay,
tipd_CASNeg => c_wire_delay,
-- tpd delays
tpd_CLK_DQ2 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
tpd_CLK_DQ3 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
-- -- tpw values: pulse widths
-- tpw_CLK_posedge : VitalDelayType := UnitDelay;
-- tpw_CLK_negedge : VitalDelayType := UnitDelay;
-- -- tsetup values: setup times
-- tsetup_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- thold values: hold times
-- thold_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- tperiod_min: minimum clock period = 1/max freq
-- tperiod_CLK_posedge : VitalDelayType := UnitDelay;
--
mem_file_name => "none",
tpowerup => 100 ns )
port map(
BA0 => logic_BA(0),
BA1 => logic_BA(1),
DQMH => dummy_dqm(1),
DQML => logic_DQM,
DQ0 => MEM_D(0),
DQ1 => MEM_D(1),
DQ2 => MEM_D(2),
DQ3 => MEM_D(3),
DQ4 => MEM_D(4),
DQ5 => MEM_D(5),
DQ6 => MEM_D(6),
DQ7 => MEM_D(7),
DQ8 => dummy_data(8),
DQ9 => dummy_data(9),
DQ10 => dummy_data(10),
DQ11 => dummy_data(11),
DQ12 => dummy_data(12),
DQ13 => dummy_data(13),
DQ14 => dummy_data(14),
DQ15 => dummy_data(15),
CLK => logic_CLK,
CKE => logic_CKE,
A0 => logic_A(0),
A1 => logic_A(1),
A2 => logic_A(2),
A3 => logic_A(3),
A4 => logic_A(4),
A5 => logic_A(5),
A6 => logic_A(6),
A7 => logic_A(7),
A8 => logic_A(8),
A9 => logic_A(9),
A10 => logic_A(10),
A11 => logic_A(11),
A12 => logic_A(12),
WENeg => logic_WEn,
RASNeg => logic_RASn,
CSNeg => logic_CSn,
CASNeg => logic_CASn );
end;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (burst of 2), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_timing.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_32_tb is
end ext_mem_test_32_tb;
architecture tb of ext_mem_test_32_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req_16 : t_mem_burst_16_req := c_mem_burst_16_req_init;
signal resp_16 : t_mem_burst_16_resp;
signal req_32 : t_mem_burst_32_req := c_mem_burst_32_req_init;
signal resp_32 : t_mem_burst_32_resp;
signal okay : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal MEM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(12 downto 0);
signal logic_BA : std_logic_vector(1 downto 0);
signal dummy_data : std_logic_vector(15 downto 0) := (others => 'H');
signal dummy_dqm : std_logic_vector(1 downto 0) := (others => 'H');
constant c_wire_delay : VitalDelayType01 := ( 2 ns, 3 ns );
begin
clock <= not clock after 10.2 ns;
clk_2x <= not clk_2x after 5.1 ns;
reset <= '1', '0' after 100 ns;
i_checker: entity work.ext_mem_test_32
port map (
clock => clock,
reset => reset,
req => req_32,
resp => resp_32,
okay => okay );
i_convert: entity work.mem_16to32
port map (
clock => clock,
reset => reset,
req_16 => req_16,
resp_16 => resp_16,
req_32 => req_32,
resp_32 => resp_32 );
i_mut: entity work.ext_mem_ctrl_v6
generic map (
q_tcko_data => 5 ns,
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req_16,
resp => resp_16,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
SDRAM_BA => logic_BA,
SDRAM_A => logic_A,
SDRAM_DQ => MEM_D );
i_sdram : entity work.mt48lc16m16a2
generic map(
tipd_BA0 => c_wire_delay,
tipd_BA1 => c_wire_delay,
tipd_DQMH => c_wire_delay,
tipd_DQML => c_wire_delay,
tipd_DQ0 => c_wire_delay,
tipd_DQ1 => c_wire_delay,
tipd_DQ2 => c_wire_delay,
tipd_DQ3 => c_wire_delay,
tipd_DQ4 => c_wire_delay,
tipd_DQ5 => c_wire_delay,
tipd_DQ6 => c_wire_delay,
tipd_DQ7 => c_wire_delay,
tipd_DQ8 => c_wire_delay,
tipd_DQ9 => c_wire_delay,
tipd_DQ10 => c_wire_delay,
tipd_DQ11 => c_wire_delay,
tipd_DQ12 => c_wire_delay,
tipd_DQ13 => c_wire_delay,
tipd_DQ14 => c_wire_delay,
tipd_DQ15 => c_wire_delay,
tipd_CLK => c_wire_delay,
tipd_CKE => c_wire_delay,
tipd_A0 => c_wire_delay,
tipd_A1 => c_wire_delay,
tipd_A2 => c_wire_delay,
tipd_A3 => c_wire_delay,
tipd_A4 => c_wire_delay,
tipd_A5 => c_wire_delay,
tipd_A6 => c_wire_delay,
tipd_A7 => c_wire_delay,
tipd_A8 => c_wire_delay,
tipd_A9 => c_wire_delay,
tipd_A10 => c_wire_delay,
tipd_A11 => c_wire_delay,
tipd_A12 => c_wire_delay,
tipd_WENeg => c_wire_delay,
tipd_RASNeg => c_wire_delay,
tipd_CSNeg => c_wire_delay,
tipd_CASNeg => c_wire_delay,
-- tpd delays
tpd_CLK_DQ2 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
tpd_CLK_DQ3 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
-- -- tpw values: pulse widths
-- tpw_CLK_posedge : VitalDelayType := UnitDelay;
-- tpw_CLK_negedge : VitalDelayType := UnitDelay;
-- -- tsetup values: setup times
-- tsetup_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- thold values: hold times
-- thold_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- tperiod_min: minimum clock period = 1/max freq
-- tperiod_CLK_posedge : VitalDelayType := UnitDelay;
--
mem_file_name => "none",
tpowerup => 100 ns )
port map(
BA0 => logic_BA(0),
BA1 => logic_BA(1),
DQMH => dummy_dqm(1),
DQML => logic_DQM,
DQ0 => MEM_D(0),
DQ1 => MEM_D(1),
DQ2 => MEM_D(2),
DQ3 => MEM_D(3),
DQ4 => MEM_D(4),
DQ5 => MEM_D(5),
DQ6 => MEM_D(6),
DQ7 => MEM_D(7),
DQ8 => dummy_data(8),
DQ9 => dummy_data(9),
DQ10 => dummy_data(10),
DQ11 => dummy_data(11),
DQ12 => dummy_data(12),
DQ13 => dummy_data(13),
DQ14 => dummy_data(14),
DQ15 => dummy_data(15),
CLK => logic_CLK,
CKE => logic_CKE,
A0 => logic_A(0),
A1 => logic_A(1),
A2 => logic_A(2),
A3 => logic_A(3),
A4 => logic_A(4),
A5 => logic_A(5),
A6 => logic_A(6),
A7 => logic_A(7),
A8 => logic_A(8),
A9 => logic_A(9),
A10 => logic_A(10),
A11 => logic_A(11),
A12 => logic_A(12),
WENeg => logic_WEn,
RASNeg => logic_RASn,
CSNeg => logic_CSn,
CASNeg => logic_CASn );
end;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (burst of 2), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_timing.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_32_tb is
end ext_mem_test_32_tb;
architecture tb of ext_mem_test_32_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req_16 : t_mem_burst_16_req := c_mem_burst_16_req_init;
signal resp_16 : t_mem_burst_16_resp;
signal req_32 : t_mem_burst_32_req := c_mem_burst_32_req_init;
signal resp_32 : t_mem_burst_32_resp;
signal okay : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal MEM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(12 downto 0);
signal logic_BA : std_logic_vector(1 downto 0);
signal dummy_data : std_logic_vector(15 downto 0) := (others => 'H');
signal dummy_dqm : std_logic_vector(1 downto 0) := (others => 'H');
constant c_wire_delay : VitalDelayType01 := ( 2 ns, 3 ns );
begin
clock <= not clock after 10.2 ns;
clk_2x <= not clk_2x after 5.1 ns;
reset <= '1', '0' after 100 ns;
i_checker: entity work.ext_mem_test_32
port map (
clock => clock,
reset => reset,
req => req_32,
resp => resp_32,
okay => okay );
i_convert: entity work.mem_16to32
port map (
clock => clock,
reset => reset,
req_16 => req_16,
resp_16 => resp_16,
req_32 => req_32,
resp_32 => resp_32 );
i_mut: entity work.ext_mem_ctrl_v6
generic map (
q_tcko_data => 5 ns,
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req_16,
resp => resp_16,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
SDRAM_BA => logic_BA,
SDRAM_A => logic_A,
SDRAM_DQ => MEM_D );
i_sdram : entity work.mt48lc16m16a2
generic map(
tipd_BA0 => c_wire_delay,
tipd_BA1 => c_wire_delay,
tipd_DQMH => c_wire_delay,
tipd_DQML => c_wire_delay,
tipd_DQ0 => c_wire_delay,
tipd_DQ1 => c_wire_delay,
tipd_DQ2 => c_wire_delay,
tipd_DQ3 => c_wire_delay,
tipd_DQ4 => c_wire_delay,
tipd_DQ5 => c_wire_delay,
tipd_DQ6 => c_wire_delay,
tipd_DQ7 => c_wire_delay,
tipd_DQ8 => c_wire_delay,
tipd_DQ9 => c_wire_delay,
tipd_DQ10 => c_wire_delay,
tipd_DQ11 => c_wire_delay,
tipd_DQ12 => c_wire_delay,
tipd_DQ13 => c_wire_delay,
tipd_DQ14 => c_wire_delay,
tipd_DQ15 => c_wire_delay,
tipd_CLK => c_wire_delay,
tipd_CKE => c_wire_delay,
tipd_A0 => c_wire_delay,
tipd_A1 => c_wire_delay,
tipd_A2 => c_wire_delay,
tipd_A3 => c_wire_delay,
tipd_A4 => c_wire_delay,
tipd_A5 => c_wire_delay,
tipd_A6 => c_wire_delay,
tipd_A7 => c_wire_delay,
tipd_A8 => c_wire_delay,
tipd_A9 => c_wire_delay,
tipd_A10 => c_wire_delay,
tipd_A11 => c_wire_delay,
tipd_A12 => c_wire_delay,
tipd_WENeg => c_wire_delay,
tipd_RASNeg => c_wire_delay,
tipd_CSNeg => c_wire_delay,
tipd_CASNeg => c_wire_delay,
-- tpd delays
tpd_CLK_DQ2 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
tpd_CLK_DQ3 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
-- -- tpw values: pulse widths
-- tpw_CLK_posedge : VitalDelayType := UnitDelay;
-- tpw_CLK_negedge : VitalDelayType := UnitDelay;
-- -- tsetup values: setup times
-- tsetup_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- thold values: hold times
-- thold_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- tperiod_min: minimum clock period = 1/max freq
-- tperiod_CLK_posedge : VitalDelayType := UnitDelay;
--
mem_file_name => "none",
tpowerup => 100 ns )
port map(
BA0 => logic_BA(0),
BA1 => logic_BA(1),
DQMH => dummy_dqm(1),
DQML => logic_DQM,
DQ0 => MEM_D(0),
DQ1 => MEM_D(1),
DQ2 => MEM_D(2),
DQ3 => MEM_D(3),
DQ4 => MEM_D(4),
DQ5 => MEM_D(5),
DQ6 => MEM_D(6),
DQ7 => MEM_D(7),
DQ8 => dummy_data(8),
DQ9 => dummy_data(9),
DQ10 => dummy_data(10),
DQ11 => dummy_data(11),
DQ12 => dummy_data(12),
DQ13 => dummy_data(13),
DQ14 => dummy_data(14),
DQ15 => dummy_data(15),
CLK => logic_CLK,
CKE => logic_CKE,
A0 => logic_A(0),
A1 => logic_A(1),
A2 => logic_A(2),
A3 => logic_A(3),
A4 => logic_A(4),
A5 => logic_A(5),
A6 => logic_A(6),
A7 => logic_A(7),
A8 => logic_A(8),
A9 => logic_A(9),
A10 => logic_A(10),
A11 => logic_A(11),
A12 => logic_A(12),
WENeg => logic_WEn,
RASNeg => logic_RASn,
CSNeg => logic_CSn,
CASNeg => logic_CASn );
end;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (burst of 2), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_timing.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_32_tb is
end ext_mem_test_32_tb;
architecture tb of ext_mem_test_32_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req_16 : t_mem_burst_16_req := c_mem_burst_16_req_init;
signal resp_16 : t_mem_burst_16_resp;
signal req_32 : t_mem_burst_32_req := c_mem_burst_32_req_init;
signal resp_32 : t_mem_burst_32_resp;
signal okay : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal MEM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(12 downto 0);
signal logic_BA : std_logic_vector(1 downto 0);
signal dummy_data : std_logic_vector(15 downto 0) := (others => 'H');
signal dummy_dqm : std_logic_vector(1 downto 0) := (others => 'H');
constant c_wire_delay : VitalDelayType01 := ( 2 ns, 3 ns );
begin
clock <= not clock after 10.2 ns;
clk_2x <= not clk_2x after 5.1 ns;
reset <= '1', '0' after 100 ns;
i_checker: entity work.ext_mem_test_32
port map (
clock => clock,
reset => reset,
req => req_32,
resp => resp_32,
okay => okay );
i_convert: entity work.mem_16to32
port map (
clock => clock,
reset => reset,
req_16 => req_16,
resp_16 => resp_16,
req_32 => req_32,
resp_32 => resp_32 );
i_mut: entity work.ext_mem_ctrl_v6
generic map (
q_tcko_data => 5 ns,
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req_16,
resp => resp_16,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
SDRAM_BA => logic_BA,
SDRAM_A => logic_A,
SDRAM_DQ => MEM_D );
i_sdram : entity work.mt48lc16m16a2
generic map(
tipd_BA0 => c_wire_delay,
tipd_BA1 => c_wire_delay,
tipd_DQMH => c_wire_delay,
tipd_DQML => c_wire_delay,
tipd_DQ0 => c_wire_delay,
tipd_DQ1 => c_wire_delay,
tipd_DQ2 => c_wire_delay,
tipd_DQ3 => c_wire_delay,
tipd_DQ4 => c_wire_delay,
tipd_DQ5 => c_wire_delay,
tipd_DQ6 => c_wire_delay,
tipd_DQ7 => c_wire_delay,
tipd_DQ8 => c_wire_delay,
tipd_DQ9 => c_wire_delay,
tipd_DQ10 => c_wire_delay,
tipd_DQ11 => c_wire_delay,
tipd_DQ12 => c_wire_delay,
tipd_DQ13 => c_wire_delay,
tipd_DQ14 => c_wire_delay,
tipd_DQ15 => c_wire_delay,
tipd_CLK => c_wire_delay,
tipd_CKE => c_wire_delay,
tipd_A0 => c_wire_delay,
tipd_A1 => c_wire_delay,
tipd_A2 => c_wire_delay,
tipd_A3 => c_wire_delay,
tipd_A4 => c_wire_delay,
tipd_A5 => c_wire_delay,
tipd_A6 => c_wire_delay,
tipd_A7 => c_wire_delay,
tipd_A8 => c_wire_delay,
tipd_A9 => c_wire_delay,
tipd_A10 => c_wire_delay,
tipd_A11 => c_wire_delay,
tipd_A12 => c_wire_delay,
tipd_WENeg => c_wire_delay,
tipd_RASNeg => c_wire_delay,
tipd_CSNeg => c_wire_delay,
tipd_CASNeg => c_wire_delay,
-- tpd delays
tpd_CLK_DQ2 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
tpd_CLK_DQ3 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
-- -- tpw values: pulse widths
-- tpw_CLK_posedge : VitalDelayType := UnitDelay;
-- tpw_CLK_negedge : VitalDelayType := UnitDelay;
-- -- tsetup values: setup times
-- tsetup_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- thold values: hold times
-- thold_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- tperiod_min: minimum clock period = 1/max freq
-- tperiod_CLK_posedge : VitalDelayType := UnitDelay;
--
mem_file_name => "none",
tpowerup => 100 ns )
port map(
BA0 => logic_BA(0),
BA1 => logic_BA(1),
DQMH => dummy_dqm(1),
DQML => logic_DQM,
DQ0 => MEM_D(0),
DQ1 => MEM_D(1),
DQ2 => MEM_D(2),
DQ3 => MEM_D(3),
DQ4 => MEM_D(4),
DQ5 => MEM_D(5),
DQ6 => MEM_D(6),
DQ7 => MEM_D(7),
DQ8 => dummy_data(8),
DQ9 => dummy_data(9),
DQ10 => dummy_data(10),
DQ11 => dummy_data(11),
DQ12 => dummy_data(12),
DQ13 => dummy_data(13),
DQ14 => dummy_data(14),
DQ15 => dummy_data(15),
CLK => logic_CLK,
CKE => logic_CKE,
A0 => logic_A(0),
A1 => logic_A(1),
A2 => logic_A(2),
A3 => logic_A(3),
A4 => logic_A(4),
A5 => logic_A(5),
A6 => logic_A(6),
A7 => logic_A(7),
A8 => logic_A(8),
A9 => logic_A(9),
A10 => logic_A(10),
A11 => logic_A(11),
A12 => logic_A(12),
WENeg => logic_WEn,
RASNeg => logic_RASn,
CSNeg => logic_CSn,
CASNeg => logic_CASn );
end;
|
-- $Id: ib_sel.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ib_sel - syn
-- Description: ibus: address select logic
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 12.1-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.0 Initial version (derived from rritb_sres_or_mon)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_sel is -- ibus address select logic
generic (
IB_ADDR : slv16; -- ibus address base
SAWIDTH : natural := 0); -- device subaddress space width
port (
CLK : in slbit; -- clock
IB_MREQ : in ib_mreq_type; -- ibus request
SEL : out slbit -- select state bit
);
end ib_sel;
architecture syn of ib_sel is
signal R_SEL : slbit := '0';
begin
assert SAWIDTH<=10 -- at most 1k words devices
report "assert(SAWIDTH<=10)" severity failure;
proc_regs: process (CLK)
variable isel : slbit := '0';
begin
if rising_edge(CLK) then
isel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto SAWIDTH+1)=IB_ADDR(12 downto SAWIDTH+1) then
isel := '1';
end if;
R_SEL <= isel;
end if;
end process proc_regs;
SEL <= R_SEL;
end syn;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
-- NOTE: This BFM is only intended as a simplified UART BFM to be used as a test
-- vehicle for presenting UVVM functionality.
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library STD;
use std.textio.all;
--=================================================================================================
package uart_bfm_pkg is
--===============================================================================================
-- Types and constants for UART BFMs
--===============================================================================================
constant C_SCOPE : string := "UART BFM";
-- Configuration record to be assigned in the test harness.
type t_parity is (
PARITY_NONE,
PARITY_ODD,
PARITY_EVEN
);
type t_stop_bits is (
STOP_BITS_ONE,
STOP_BITS_ONE_AND_HALF,
STOP_BITS_TWO
);
constant C_MAX_BITS_IN_RECEIVED_DATA : natural := 8;
constant C_EXPECT_RECEIVED_DATA_STRING_SEPARATOR : string := "; ";
type uart_expect_received_data_array is array (natural range<>) of std_logic_vector(C_MAX_BITS_IN_RECEIVED_DATA-1 downto 0);
type t_uart_bfm_config is
record
bit_time : time; -- The time it takes to transfer one bit
num_data_bits : natural range 7 to 8; -- Number of data bits to send per transmission
idle_state : std_logic; -- Bit value when line is idle
num_stop_bits : t_stop_bits; -- Number of stop-bits to use per transmission {STOP_BITS_ONE, STOP_BITS_ONE_AND_HALF, STOP_BITS_TWO}
parity : t_parity; -- Transmission parity bit {PARITY_NONE, PARITY_ODD, PARITY_EVEN}
timeout : time; -- The maximum time to pass before the expected data must be received. Exceeding this limit results in an alert with severity ‘alert_level’.
timeout_severity : t_alert_level; -- The above timeout will have this severity
num_bytes_to_log_before_expected_data : natural; -- Maximum number of bytes to save ahead of the expected data in the receive buffer. The bytes in the receive buffer will be logged.
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the UART BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the UART BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the UART BFM
id_for_bfm_poll_summary : t_msg_id; -- The message ID used for logging polling summary in the UART BFM
end record;
constant C_UART_BFM_CONFIG_DEFAULT : t_uart_bfm_config := (
bit_time => -1 ns,
num_data_bits => 8,
idle_state => '1',
num_stop_bits => STOP_BITS_ONE,
parity => PARITY_ODD,
timeout => 0 ns, -- will default never time out
timeout_severity => error,
num_bytes_to_log_before_expected_data => 10,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL,
id_for_bfm_poll_summary => ID_BFM_POLL_SUMMARY
);
----------------------------------------------------
-- BFM procedures
----------------------------------------------------
------------------------------------------
-- uart_transmit
------------------------------------------
-- - This procedure transmits data 'data_value' to the UART DUT
-- - The TX configuration can be set in the config parameter
procedure uart_transmit (
constant data_value : in std_logic_vector;
constant msg : in string;
signal tx : inout std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
);
------------------------------------------
-- uart_receive
------------------------------------------
-- - This procedure reads data from the UART DUT and returns it in 'data_value'
-- - The RX configuration can be set in the config parameter
procedure uart_receive (
variable data_value : out std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call: in string := "" -- External proc_call; used if called from other BFM procedure like uart_expect
);
------------------------------------------
-- uart_expect
------------------------------------------
-- - This procedure reads data from the UART DUT and compares it to the data in
-- 'data_exp'.
-- - If the read data is inconsistent with the 'data_exp' data, a new read will
-- be performed, and the new read data will be compared with 'data_exp'.
-- This process will continue untill one of the following conditions are met:
-- a) The read data is equal to the expected data
-- b) The number of reads equal 'max_receptions'
-- c) The time spent reading is equal to the 'timeout'
-- - If 'timeout' is set to 0, it will be interpreted as no timeout
-- - If 'max_receptions' is set to 0, it will be interpreted as no limitation on number of reads
-- - The RX configuration can be set in the config parameter
procedure uart_expect (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant max_receptions : in natural := 1;
constant timeout : in time := -1 ns;
constant alert_level : in t_alert_level := ERROR;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
);
------------------------------------------
-- odd_parity
------------------------------------------
-- - This function checks if the data parity is odd or even
-- - If the number of '1' in the 'data' input is odd, '1' will be returned
-- - If the number of '1' in the 'data' input is even, '0' will be returned
function odd_parity (
constant data : std_logic_vector(7 downto 0))
return std_logic;
end package uart_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body uart_bfm_pkg is
function odd_parity (
constant data : std_logic_vector(7 downto 0))
return std_logic is
begin
return xnor(data);
end odd_parity;
---------------------------------------------------------------------------------
-- uart_transmit
---------------------------------------------------------------------------------
procedure uart_transmit (
constant data_value : in std_logic_vector;
constant msg : in string;
signal tx : inout std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) is
constant proc_name : string := "uart_transmit";
constant proc_call : string := proc_name & "(" & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";
begin
-- check whether config.bit_time was set probably
check_value(config.bit_time /= -1 ns, TB_ERROR, "UART Bit time was not set in config. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
check_value(data_value'length = config.num_data_bits, FAILURE, "length of data_value does not match config.num_data_bits. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- check if tx line was idle when trying to transmit data
check_value(tx, config.idle_state, FAILURE, proc_call & " Bus was active when trying to send data. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
tx <= not config.idle_state;
wait for config.bit_time;
for j in data_value'low to data_value'high loop
tx <= data_value(j);
wait for config.bit_time;
end loop;
-- parity?
if (config.parity = PARITY_ODD) then
tx <= odd_parity(data_value);
wait for config.bit_time;
elsif(config.parity = PARITY_EVEN) then
tx <= not odd_parity(data_value);
wait for config.bit_time;
end if;
-- stop bits
tx <= config.idle_state;
wait for config.bit_time;
if (config.num_stop_bits = STOP_BITS_ONE_AND_HALF) then
wait for config.bit_time/2;
elsif(config.num_stop_bits = STOP_BITS_TWO) then
wait for config.bit_time;
end if;
log(config.id_for_bfm, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure;
---------------------------------------------------------------------------------
-- uart_receive
---------------------------------------------------------------------------------
-- Perform a receive operation
procedure uart_receive (
variable data_value : out std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call: in string := "" -- External proc_call; used if called from other BFM procedure like uart_expect
) is
constant start_time : time := now;
-- local_proc_* used if uart_receive is called directly from sequencer or VVC
constant local_proc_name : string := "uart_receive";
constant local_proc_call : string := local_proc_name & "()";
-- Helper variables
variable v_transfer_time : time;
variable v_proc_call : line; -- Current proc_call, external or internal
variable v_remaining_time : time; -- temp variable to calculate the remaining time before timeout
variable v_data_value : std_logic_vector(config.num_data_bits-1 downto 0);
variable v_terminated : boolean := false;
variable v_timeout : boolean := false;
begin
-- check whether config.bit_time was set properly
check_value(config.bit_time /= -1 ns, TB_ERROR, "UART Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
data_value := (data_value'range => 'X');
check_value(data_value'length = config.num_data_bits, FAILURE, "length of data_value does not match config.num_data_bits. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- If timeout enabled, check that timeout is longer than transfer time
if config.timeout /= 0 ns then
v_transfer_time := (config.num_data_bits + 2) * config.bit_time;
if config.parity = PARITY_ODD or config.parity = PARITY_EVEN then
v_transfer_time := v_transfer_time + config.bit_time;
end if;
if config.num_stop_bits = STOP_BITS_ONE_AND_HALF then
v_transfer_time := v_transfer_time + config.bit_time/2;
elsif config.num_stop_bits = STOP_BITS_TWO then
v_transfer_time := v_transfer_time + config.bit_time;
end if;
check_value(v_transfer_time < config.timeout, TB_ERROR, "Length of timeout is shorter than or equal length of transfer time.", C_SCOPE, ID_NEVER, msg_id_panel);
end if;
if ext_proc_call = "" then
-- called from sequencer/VVC, show 'uart_receive()...' in log
write(v_proc_call, local_proc_call);
else
-- called from other BFM procedure like uart_expect, log 'uart_expect() while executing uart_receive()...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name & ". ");
end if;
-- check if bus is in idle state
check_value(rx, config.idle_state, FAILURE, v_proc_call.all & "Bus was active when trying to receive data. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
-- wait until the start bit is sent on the bus, configured timeout occures or procedure get terminate signal
if config.timeout = 0 ns then
wait until (rx /= config.idle_state) or (terminate_loop = '1');
else
wait until (rx /= config.idle_state) or (terminate_loop = '1') for config.timeout;
end if;
if terminate_loop = '1' then
if ext_proc_call = "" then
log(ID_TERMINATE_CMD, v_proc_call.all & "=> terminated." & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- termination handled in calling procedure
end if;
v_terminated := true;
end if;
-- if configured timeout, check if there is enough time remaining to receive the byte
if config.timeout /= 0 ns and not v_terminated then
v_remaining_time := (config.num_data_bits + 2) * config.bit_time;
if config.parity = PARITY_ODD or config.parity = PARITY_EVEN then
v_remaining_time := v_remaining_time + config.bit_time;
end if;
if config.num_stop_bits = STOP_BITS_ONE_AND_HALF then
v_remaining_time := v_remaining_time + config.bit_time/2;
elsif config.num_stop_bits = STOP_BITS_TWO then
v_remaining_time := v_remaining_time + config.bit_time;
end if;
if now + v_remaining_time > start_time + config.timeout then
-- wait until timeout
wait for ((start_time + config.timeout) - now);
if ext_proc_call = "" then
alert(config.timeout_severity, v_proc_call.all & "=> timeout. " & add_msg_delimiter(msg),scope);
else
-- timeout handled in upper module
end if;
v_timeout := true;
end if;
end if;
if not v_terminated and not v_timeout then
-- enter the middle of the bit period
wait for config.bit_time/2;
check_value(rx , not config.idle_state, FAILURE, v_proc_call.all & " Start bit was not stable during receiving. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
-- wait for data bit
wait for config.bit_time;
-- sample the data bits
for i in 0 to config.num_data_bits-1 loop
v_data_value(i) := rx;
-- wait for middle of the next bit
wait for config.bit_time;
end loop;
-- check parity, if enabled
if config.parity = PARITY_ODD then
if rx /= odd_parity(v_data_value) then
alert(error, v_proc_call.all & "=> Failed. Incorrect parity received. " & add_msg_delimiter(msg),scope);
end if;
wait for config.bit_time;
elsif config.parity = PARITY_EVEN then
if rx /= not odd_parity(v_data_value) then
alert(error, v_proc_call.all & "=> Failed. Incorrect parity received. " & add_msg_delimiter(msg),scope);
end if;
wait for config.bit_time;
end if;
-- check the stop bit
if rx /= config.idle_state then
alert(error, v_proc_call.all & "=> Failed. Incorrect stop bit received. " & add_msg_delimiter(msg),scope);
end if;
if config.num_stop_bits = STOP_BITS_ONE_AND_HALF then
wait for config.bit_time/2 + config.bit_time/4; -- middle of the last half. Last half of previous stop bit + first half of current stop bit
if rx /= config.idle_state then
alert(error, v_proc_call.all & "=> Failed. Incorrect second half stop bit received. " & add_msg_delimiter(msg),scope);
end if;
elsif config.num_stop_bits = STOP_BITS_TWO then
wait for config.bit_time; -- middle of the last bit. Last half of previous stop bit + first half of current stop bit
if rx /= config.idle_state then
alert(error, v_proc_call.all & "=> Failed. Incorrect second stop bit received. " & add_msg_delimiter(msg),scope);
end if;
end if;
-- return the received data
data_value := v_data_value;
if ext_proc_call = "" then
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. uart_expect)
end if;
end if;
end procedure;
----------------------------------------------------------------------------------------
-- uart_expect
----------------------------------------------------------------------------------------
-- Perform a receive operation, then compare the received value to the expected value.
procedure uart_expect (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal rx : in std_logic;
signal terminate_loop : in std_logic;
constant max_receptions : in natural := 1; -- 0 = any occurrence before timeout
constant timeout : in time := -1 ns;
constant alert_level : in t_alert_level := ERROR;
constant config : in t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) is
constant proc_name : string := "uart_expect";
constant proc_call : string := proc_name & "(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
constant start_time : time := now;
variable v_data_value : std_logic_vector(config.num_data_bits-1 downto 0);
variable v_num_of_occurrences : natural := 0;
variable v_check_ok : boolean;
variable v_num_of_occurrences_ok : boolean;
variable v_timeout_ok : boolean;
variable v_config : t_uart_bfm_config := config;
variable v_received_data_fifo : uart_expect_received_data_array(0 to v_config.num_bytes_to_log_before_expected_data-1) := (others => (others =>'0'));
variable v_received_data_fifo_write_idx : natural := 0;
variable v_received_output_line : line;
variable v_internal_timeout : time;
begin
-- check whether config.bit_time was set probably
check_value(config.bit_time /= -1 ns, TB_ERROR, "UART Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- if timeout = -1 function was called without parameter
if timeout = -1 ns then
v_internal_timeout := config.timeout;
else
v_internal_timeout := timeout;
end if;
assert (v_internal_timeout >= 0 ns) report "configured negative timeout(not allowed). " & add_msg_delimiter(msg) severity failure;
-- Check for v_internal_timeout = 0 and max_receptions = 0. This combination can result in an infinite loop.
if v_internal_timeout = 0 ns and max_receptions = 0 then
alert(ERROR, proc_name & " called with timeout=0 and max_receptions = 0. This combination can result in an infinite loop. " & add_msg_delimiter(msg),scope);
end if;
if v_internal_timeout = 0 ns then
log(v_config.id_for_bfm_wait, "Expecting data " & to_string(data_exp, HEX, SKIP_LEADING_0, INCL_RADIX) & " within " & to_string(max_receptions) & " occurrences. " & msg, scope, msg_id_panel);
elsif max_receptions = 0 then
log(v_config.id_for_bfm_wait, "Expecting data " & to_string(data_exp, HEX, SKIP_LEADING_0, INCL_RADIX) & " within " & to_string(v_internal_timeout,ns) & ". " & msg, scope, msg_id_panel);
else
log(v_config.id_for_bfm_wait, "Expecting data " & to_string(data_exp, HEX, SKIP_LEADING_0, INCL_RADIX) & " within " & to_string(max_receptions) & " occurrences and " & to_string(v_internal_timeout,ns) & ". " & msg, scope, msg_id_panel);
end if;
-- Initial status of check variables
v_check_ok := false;
v_timeout_ok := true;
if max_receptions < 1 then
v_num_of_occurrences_ok := true;
else
v_num_of_occurrences_ok := v_num_of_occurrences < max_receptions;
end if;
-- Setup of v_config with correct timeout
v_config.timeout := v_internal_timeout;
-- Check operation
while not v_check_ok and v_timeout_ok and v_num_of_occurrences_ok and (terminate_loop = '0') loop
-- Receive and check data
uart_receive(v_data_value, msg, rx, terminate_loop, v_config, scope, msg_id_panel, proc_call);
for i in 0 to v_config.num_data_bits-1 loop
if (data_exp(i) = '-' or
v_data_value(i) = data_exp(i)) then
v_check_ok := true;
else
v_check_ok := false;
exit;
end if;
end loop;
-- Place the received data in the received data buffer for debugging
-- If the FIFO is not full, fill it up
if v_received_data_fifo_write_idx < v_config.num_bytes_to_log_before_expected_data then
v_received_data_fifo(v_received_data_fifo_write_idx)(v_data_value'length-1 downto 0) := v_data_value;
v_received_data_fifo_write_idx := v_received_data_fifo_write_idx + 1;
else
-- If the FIFO is full, left shift all input and append new data
for i in 1 to v_config.num_bytes_to_log_before_expected_data-1 loop
v_received_data_fifo(i-1) := v_received_data_fifo(i);
end loop;
v_received_data_fifo(v_received_data_fifo_write_idx-1)(v_data_value'length-1 downto 0) := v_data_value;
end if;
-- Evaluate number of occurrences, if limited by user
if max_receptions > 0 then
v_num_of_occurrences := v_num_of_occurrences + 1;
v_num_of_occurrences_ok := v_num_of_occurrences < max_receptions;
end if;
-- Evaluate timeout if specified by user
if v_internal_timeout = 0 ns then
v_timeout_ok := true;
else
v_timeout_ok := now < start_time + v_internal_timeout;
end if;
end loop;
-- Concatenate the string FIFO into a single string with given separators
for i in 0 to v_received_data_fifo_write_idx-1 loop
write(v_received_output_line, to_string(v_received_data_fifo(i), HEX, SKIP_LEADING_0, INCL_RADIX));
if i /= v_received_data_fifo_write_idx-1 then
write(v_received_output_line, C_EXPECT_RECEIVED_DATA_STRING_SEPARATOR);
end if;
end loop;
if max_receptions > 1 then
-- Print the received string of bytes
log(v_config.id_for_bfm_poll_summary, "Last "& to_string(v_received_data_fifo_write_idx) & " received data bytes while waiting for expected data: " & v_received_output_line.all, scope, msg_id_panel);
end if;
if v_check_ok then
log(v_config.id_for_bfm, proc_call & "=> OK, received data = " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & " after " & to_string(v_num_of_occurrences) & " occurrences and " & to_string((now - start_time),ns) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
elsif not v_timeout_ok then
alert(config.timeout_severity, proc_call & "=> Failed due to timeout. Did not get expected value " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & " before time " & to_string(v_internal_timeout,ns) & ". " & add_msg_delimiter(msg), scope);
elsif not v_num_of_occurrences_ok then
if max_receptions = 1 then
alert(alert_level, proc_call & "=> Failed. Expected value " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & " did not appear within " & to_string(max_receptions) & " occurrences, received value " & to_string(v_data_value, HEX, AS_IS, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope);
else
alert(alert_level, proc_call & "=> Failed. Expected value " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & " did not appear within " & to_string(max_receptions) & " occurrences. " & add_msg_delimiter(msg), scope);
end if;
else
alert(warning, proc_call & "=> Failed. Terminate loop received. " & add_msg_delimiter(msg), scope);
end if;
end procedure;
end package body uart_bfm_pkg;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity phase_acc is
generic(
sine_length_bits: integer := 10
);
port(
x_out: out std_logic_vector(sine_length_bits - 1 downto 0);
freq_mult: in std_logic_vector(9 downto 0);
phase_in: in std_logic_vector(7 downto 0);
new_signal: out std_logic;
clk: in std_logic
);
end phase_acc;
architecture Behavioral of phase_acc is
signal big_ol_counter: unsigned(20 downto 0) := (others => '0');
begin
process(clk)
begin
if(rising_edge(clk)) then
big_ol_counter <= big_ol_counter + unsigned(freq_mult);
if(big_ol_counter < "10000") then
new_signal <= '1';
else
new_signal <= '0';
end if;
end if;
end process;
x_out <= std_logic_vector(big_ol_counter(20 downto 11) + unsigned(phase_in & "00"));
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_3_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_3_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_3_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_3_e
--
architecture rtl of inst_3_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (single beat), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v5 is
generic (
g_simulation : boolean := false;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_2x : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic;
is_idle : out std_logic;
req : in t_mem_req_32;
resp : out t_mem_resp_32;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_A : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v5;
-- ADDR: 25 24 23 ...
-- 0 X X ... SDRAM (32MB)
architecture Gideon of ext_mem_ctrl_v5 is
constant c_cmd_inactive : std_logic_vector(3 downto 0) := "1111";
constant c_cmd_nop : std_logic_vector(3 downto 0) := "0111";
constant c_cmd_active : std_logic_vector(3 downto 0) := "0011";
constant c_cmd_read : std_logic_vector(3 downto 0) := "0101";
constant c_cmd_write : std_logic_vector(3 downto 0) := "0100";
constant c_cmd_bterm : std_logic_vector(3 downto 0) := "0110";
constant c_cmd_precharge : std_logic_vector(3 downto 0) := "0010";
constant c_cmd_refresh : std_logic_vector(3 downto 0) := "0001";
constant c_cmd_mode_reg : std_logic_vector(3 downto 0) := "0000";
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(3 downto 0);
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", c_cmd_precharge ),
( X"0032", c_cmd_mode_reg ), -- mode register, burstlen=4, writelen=4, CAS lat = 3
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ) );
signal not_clock_2x : std_logic;
signal not_clock : std_logic;
type t_state is (boot, init, idle, sd_read, sd_read_2, sd_read_3, sd_write, sd_write_2, sd_write_3);
signal sdram_d_o : std_logic_vector(7 downto 0);
signal sdram_t_o : std_logic_vector(7 downto 0);
signal rdata : std_logic_vector(15 downto 0);
signal rdata_lo : std_logic_vector(7 downto 0);
signal rdata_hi : std_logic_vector(7 downto 0);
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of SDRAM_RASn : signal is "true";
attribute iob of SDRAM_CASn : signal is "true";
attribute iob of SDRAM_WEn : signal is "true";
attribute iob of SDRAM_BA : signal is "true";
attribute iob of SDRAM_A : signal is "true";
attribute iob of SDRAM_CKE : signal is "false";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of SDRAM_DQ : signal is "1";
type t_output is record
sdram_cmd : std_logic_vector(3 downto 0);
sdram_cke : std_logic;
sdram_a : std_logic_vector(12 downto 0);
sdram_ba : std_logic_vector(1 downto 0);
tri : std_logic_vector(1 downto 0);
wmask_16 : std_logic_vector(1 downto 0);
wdata_16 : std_logic_vector(15 downto 0);
end record;
type t_internal_state is record
state : t_state;
enable_sdram : std_logic;
col_addr : std_logic_vector(9 downto 0);
bank_addr : std_logic_vector(1 downto 0);
refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
refr_delay : integer range 0 to 3;
delay : integer range 0 to 7;
do_refresh : std_logic;
refresh_inhibit : std_logic;
tag : std_logic_vector(req.tag'range);
rack : std_logic;
rack_tag : std_logic_vector(req.tag'range);
dack : std_logic;
dack_tag : std_logic_vector(req.tag'range);
dack_pre : std_logic;
dack_tag_pre : std_logic_vector(req.tag'range);
boot_cnt : integer range 0 to SDRAM_WakeupTime-1;
init_cnt : integer range 0 to c_init_array'high;
wdata : std_logic_vector(31 downto 0);
wmask : std_logic_vector(3 downto 0);
end record;
constant c_internal_state_init : t_internal_state := (
state => boot,
enable_sdram => '0',
col_addr => (others => '0'),
bank_addr => (others => '0'),
refresh_cnt => SDRAM_Refr_period-1,
refr_delay => 3,
delay => 7,
do_refresh => '0',
refresh_inhibit => '0',
tag => (others => '0'),
rack => '0',
rack_tag => (others => '0'),
dack => '0',
dack_tag => (others => '0'),
dack_pre => '0',
dack_tag_pre => (others => '0'),
boot_cnt => SDRAM_WakeupTime-1,
init_cnt => c_init_array'high,
wdata => (others => '0'),
wmask => (others => '0')
);
signal outp : t_output;
signal cur : t_internal_state := c_internal_state_init;
signal nxt : t_internal_state;
begin
is_idle <= '1' when cur.state = idle else '0';
resp.data <= rdata & rdata_hi & rdata_lo;
resp.rack <= cur.rack;
resp.rack_tag <= cur.rack_tag;
resp.dack_tag <= cur.dack_tag;
process(req, inhibit, cur)
procedure send_refresh_cmd is
begin
outp.sdram_cmd <= c_cmd_refresh;
nxt.do_refresh <= '0';
nxt.refr_delay <= 3;
end procedure;
procedure accept_req is
begin
nxt.rack <= '1';
nxt.rack_tag <= req.tag;
nxt.tag <= req.tag;
nxt.wdata <= req.data;
nxt.wmask <= not req.byte_en;
nxt.col_addr <= std_logic_vector(req.address( 9 downto 0)); -- 10 column bits
nxt.bank_addr <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits
outp.sdram_ba <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits
outp.sdram_a <= std_logic_vector(req.address(24 downto 12)); -- 13 row bits
outp.sdram_cmd <= c_cmd_active;
end procedure;
begin
nxt <= cur; -- default no change
nxt.rack <= '0';
nxt.rack_tag <= (others => '0');
nxt.dack_pre <= '0';
nxt.dack_tag_pre <= (others => '0');
nxt.dack <= cur.dack_pre;
nxt.dack_tag <= cur.dack_tag_pre;
outp.sdram_cmd <= c_cmd_inactive;
outp.sdram_cke <= cur.enable_sdram;
outp.sdram_ba <= (others => 'X');
outp.sdram_a <= (others => 'X');
outp.tri <= "11";
outp.wmask_16 <= "00";
outp.wdata_16 <= (others => 'X');
if cur.refr_delay /= 0 then
nxt.refr_delay <= cur.refr_delay - 1;
end if;
if cur.delay /= 0 then
nxt.delay <= cur.delay - 1;
end if;
if inhibit='1' then
nxt.refresh_inhibit <= '1';
end if;
case cur.state is
when boot =>
nxt.refresh_inhibit <= '0';
nxt.enable_sdram <= '1';
if cur.refresh_cnt = 0 then
nxt.boot_cnt <= cur.boot_cnt - 1;
if cur.boot_cnt = 1 then
nxt.state <= init;
end if;
elsif g_simulation then
nxt.state <= idle;
end if;
when init =>
nxt.do_refresh <= '0';
outp.sdram_a <= c_init_array(cur.init_cnt).addr(12 downto 0);
outp.sdram_ba <= c_init_array(cur.init_cnt).addr(14 downto 13);
outp.sdram_cmd(3) <= '1';
outp.sdram_cmd(2 downto 0) <= c_init_array(cur.init_cnt).cmd(2 downto 0);
if cur.delay = 0 then
nxt.delay <= 7;
if cur.init_cnt = c_init_array'high then
nxt.state <= idle;
else
outp.sdram_cmd(3) <= '0';
nxt.init_cnt <= cur.init_cnt + 1;
end if;
end if;
when idle =>
-- first cycle after inhibit goes 1, should not be a refresh
-- this enables putting cartridge images in sdram, because we guarantee the first access after inhibit to be a cart cycle
if cur.do_refresh='1' and cur.refresh_inhibit='0' then
send_refresh_cmd;
elsif inhibit='0' then -- make sure we are allowed to start a new cycle
if req.request='1' and cur.refr_delay = 0 then
accept_req;
nxt.refresh_inhibit <= '0';
if req.read_writen = '1' then
nxt.state <= sd_read;
else
nxt.state <= sd_write;
end if;
end if;
end if;
when sd_read =>
outp.sdram_ba <= cur.bank_addr;
outp.sdram_a(12 downto 11) <= "00";
outp.sdram_a(10) <= '1'; -- auto precharge
outp.sdram_a(9 downto 0) <= cur.col_addr;
outp.sdram_cmd <= c_cmd_read;
nxt.state <= sd_read_2;
when sd_read_2 =>
nxt.state <= sd_read_3;
when sd_read_3 =>
nxt.dack_pre <= '1';
nxt.dack_tag_pre <= cur.tag;
nxt.state <= idle;
when sd_write =>
outp.sdram_ba <= cur.bank_addr;
outp.sdram_a(12 downto 11) <= "00";
outp.sdram_a(10) <= '1'; -- auto precharge
outp.sdram_a(9 downto 0) <= cur.col_addr;
outp.sdram_cmd <= c_cmd_write;
outp.wdata_16 <= cur.wdata(31 downto 24) & "XXXXXXXX";
outp.wmask_16 <= cur.wmask(3) & "0";
outp.tri <= "01";
nxt.state <= sd_write_2;
when sd_write_2 =>
outp.tri <= "00";
outp.wdata_16 <= cur.wdata(15 downto 8) & cur.wdata(23 downto 16);
outp.wmask_16 <= cur.wmask(1) & cur.wmask(2);
nxt.state <= sd_write_3;
when sd_write_3 =>
outp.tri <= "10";
outp.wdata_16 <= "XXXXXXXX" & cur.wdata(7 downto 0);
outp.wmask_16 <= "0" & cur.wmask(0);
nxt.state <= idle;
when others =>
null;
end case;
if cur.refresh_cnt = SDRAM_Refr_period-1 then
nxt.do_refresh <= '1';
nxt.refresh_cnt <= 0;
else
nxt.refresh_cnt <= cur.refresh_cnt + 1;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
cur <= nxt;
SDRAM_A <= outp.sdram_a;
SDRAM_BA <= outp.sdram_ba;
SDRAM_RASn <= outp.sdram_cmd(2);
SDRAM_CASn <= outp.sdram_cmd(1);
SDRAM_WEn <= outp.sdram_cmd(0);
SDRAM_CKE <= cur.enable_sdram;
rdata <= rdata_hi & rdata_lo;
if reset='1' then
cur.state <= boot;
cur.delay <= 0;
cur.tag <= (others => '0');
cur.do_refresh <= '0';
cur.boot_cnt <= SDRAM_WakeupTime-1;
cur.init_cnt <= 0;
cur.enable_sdram <= '1';
cur.refresh_inhibit <= '0';
end if;
end if;
end process;
not_clock_2x <= not clk_2x;
not_clock <= not clock;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_2x,
C1 => not_clock_2x,
D0 => '0',
D1 => cur.enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
select_out: FDDRRSE
port map (
CE => '1',
C0 => clock,
C1 => not_clock,
D0 => outp.sdram_cmd(3),
D1 => '1',
Q => SDRAM_CSn,
R => '0',
S => '0' );
r_data: for i in 0 to 7 generate
i_in: IDDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q0 => rdata_hi(i),
Q1 => rdata_lo(i),
C0 => clock,
C1 => not_clock,
CE => '1',
D => SDRAM_DQ(i),
R => reset,
S => '0');
i_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => sdram_d_o(i),
C0 => clock,
C1 => not_clock,
CE => '1',
D0 => outp.wdata_16(8+i),
D1 => outp.wdata_16(i),
R => reset,
S => '0' );
i_out_t: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => sdram_t_o(i),
C0 => clock,
C1 => not_clock,
CE => '1',
D0 => outp.tri(1),
D1 => outp.tri(0),
R => reset,
S => '0' );
SDRAM_DQ(i) <= sdram_d_o(i) when sdram_t_o(i)='0' else 'Z';
end generate;
mask_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => SDRAM_DQM,
C0 => clock,
C1 => not_clock,
CE => '1',
D0 => outp.wmask_16(1),
D1 => outp.wmask_16(0),
R => reset,
S => '0' );
end Gideon;
-- 100 MHz
-- ACT to READ: tRCD = 20 ns ( = 2 CLKs)
-- ACT to PRCH: tRAS = 44 ns ( = 5 CLKs)
-- ACT to ACT: tRC = 66 ns ( = 7 CLKs)
-- ACT to ACTb: tRRD = 15 ns ( = 2 CLKs)
-- PRCH time; tRP = 20 ns ( = 2 CLKs)
-- wr. recov. tWR=8ns+1clk ( = 2 CLKs) (starting from last data word)
-- CL=2
-- 0 1 2 3 4 5 6 7 8 9
-- BL1 A - R - - P + - precharge on odd clock
-- - - - - D d d -
-- +: ONLY if same bank, a new ACT command can be given here. Otherwise we don't meet tRC.
-- BL4 A - r - - - p -
-- - - - - D D D D
-- BL1W A - W - - P + - (precharge on odd clock)
-- - - D - - - - -
-- BL4W A - W - - - p -
-- - - D D D D - -
-- Conclusion: In order to meet tRC, without checking for the bank, we always need 80 ns.
-- In order to optimize to 60 ns (using 20 ns logic ticks), we need to add both bank
-- number checking, as well as differentiate between 1 byte and 4 bytes. I think that
-- it is not worthwhile at this point to implement this, so we will use a very rigid
-- 4-tick schedule: one fits all
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (single beat), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v5 is
generic (
g_simulation : boolean := false;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_2x : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic;
is_idle : out std_logic;
req : in t_mem_req_32;
resp : out t_mem_resp_32;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_A : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v5;
-- ADDR: 25 24 23 ...
-- 0 X X ... SDRAM (32MB)
architecture Gideon of ext_mem_ctrl_v5 is
constant c_cmd_inactive : std_logic_vector(3 downto 0) := "1111";
constant c_cmd_nop : std_logic_vector(3 downto 0) := "0111";
constant c_cmd_active : std_logic_vector(3 downto 0) := "0011";
constant c_cmd_read : std_logic_vector(3 downto 0) := "0101";
constant c_cmd_write : std_logic_vector(3 downto 0) := "0100";
constant c_cmd_bterm : std_logic_vector(3 downto 0) := "0110";
constant c_cmd_precharge : std_logic_vector(3 downto 0) := "0010";
constant c_cmd_refresh : std_logic_vector(3 downto 0) := "0001";
constant c_cmd_mode_reg : std_logic_vector(3 downto 0) := "0000";
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(3 downto 0);
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", c_cmd_precharge ),
( X"0032", c_cmd_mode_reg ), -- mode register, burstlen=4, writelen=4, CAS lat = 3
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ) );
signal not_clock_2x : std_logic;
signal not_clock : std_logic;
type t_state is (boot, init, idle, sd_read, sd_read_2, sd_read_3, sd_write, sd_write_2, sd_write_3);
signal sdram_d_o : std_logic_vector(7 downto 0);
signal sdram_t_o : std_logic_vector(7 downto 0);
signal rdata : std_logic_vector(15 downto 0);
signal rdata_lo : std_logic_vector(7 downto 0);
signal rdata_hi : std_logic_vector(7 downto 0);
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of SDRAM_RASn : signal is "true";
attribute iob of SDRAM_CASn : signal is "true";
attribute iob of SDRAM_WEn : signal is "true";
attribute iob of SDRAM_BA : signal is "true";
attribute iob of SDRAM_A : signal is "true";
attribute iob of SDRAM_CKE : signal is "false";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of SDRAM_DQ : signal is "1";
type t_output is record
sdram_cmd : std_logic_vector(3 downto 0);
sdram_cke : std_logic;
sdram_a : std_logic_vector(12 downto 0);
sdram_ba : std_logic_vector(1 downto 0);
tri : std_logic_vector(1 downto 0);
wmask_16 : std_logic_vector(1 downto 0);
wdata_16 : std_logic_vector(15 downto 0);
end record;
type t_internal_state is record
state : t_state;
enable_sdram : std_logic;
col_addr : std_logic_vector(9 downto 0);
bank_addr : std_logic_vector(1 downto 0);
refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
refr_delay : integer range 0 to 3;
delay : integer range 0 to 7;
do_refresh : std_logic;
refresh_inhibit : std_logic;
tag : std_logic_vector(req.tag'range);
rack : std_logic;
rack_tag : std_logic_vector(req.tag'range);
dack : std_logic;
dack_tag : std_logic_vector(req.tag'range);
dack_pre : std_logic;
dack_tag_pre : std_logic_vector(req.tag'range);
boot_cnt : integer range 0 to SDRAM_WakeupTime-1;
init_cnt : integer range 0 to c_init_array'high;
wdata : std_logic_vector(31 downto 0);
wmask : std_logic_vector(3 downto 0);
end record;
constant c_internal_state_init : t_internal_state := (
state => boot,
enable_sdram => '0',
col_addr => (others => '0'),
bank_addr => (others => '0'),
refresh_cnt => SDRAM_Refr_period-1,
refr_delay => 3,
delay => 7,
do_refresh => '0',
refresh_inhibit => '0',
tag => (others => '0'),
rack => '0',
rack_tag => (others => '0'),
dack => '0',
dack_tag => (others => '0'),
dack_pre => '0',
dack_tag_pre => (others => '0'),
boot_cnt => SDRAM_WakeupTime-1,
init_cnt => c_init_array'high,
wdata => (others => '0'),
wmask => (others => '0')
);
signal outp : t_output;
signal cur : t_internal_state := c_internal_state_init;
signal nxt : t_internal_state;
begin
is_idle <= '1' when cur.state = idle else '0';
resp.data <= rdata & rdata_hi & rdata_lo;
resp.rack <= cur.rack;
resp.rack_tag <= cur.rack_tag;
resp.dack_tag <= cur.dack_tag;
process(req, inhibit, cur)
procedure send_refresh_cmd is
begin
outp.sdram_cmd <= c_cmd_refresh;
nxt.do_refresh <= '0';
nxt.refr_delay <= 3;
end procedure;
procedure accept_req is
begin
nxt.rack <= '1';
nxt.rack_tag <= req.tag;
nxt.tag <= req.tag;
nxt.wdata <= req.data;
nxt.wmask <= not req.byte_en;
nxt.col_addr <= std_logic_vector(req.address( 9 downto 0)); -- 10 column bits
nxt.bank_addr <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits
outp.sdram_ba <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits
outp.sdram_a <= std_logic_vector(req.address(24 downto 12)); -- 13 row bits
outp.sdram_cmd <= c_cmd_active;
end procedure;
begin
nxt <= cur; -- default no change
nxt.rack <= '0';
nxt.rack_tag <= (others => '0');
nxt.dack_pre <= '0';
nxt.dack_tag_pre <= (others => '0');
nxt.dack <= cur.dack_pre;
nxt.dack_tag <= cur.dack_tag_pre;
outp.sdram_cmd <= c_cmd_inactive;
outp.sdram_cke <= cur.enable_sdram;
outp.sdram_ba <= (others => 'X');
outp.sdram_a <= (others => 'X');
outp.tri <= "11";
outp.wmask_16 <= "00";
outp.wdata_16 <= (others => 'X');
if cur.refr_delay /= 0 then
nxt.refr_delay <= cur.refr_delay - 1;
end if;
if cur.delay /= 0 then
nxt.delay <= cur.delay - 1;
end if;
if inhibit='1' then
nxt.refresh_inhibit <= '1';
end if;
case cur.state is
when boot =>
nxt.refresh_inhibit <= '0';
nxt.enable_sdram <= '1';
if cur.refresh_cnt = 0 then
nxt.boot_cnt <= cur.boot_cnt - 1;
if cur.boot_cnt = 1 then
nxt.state <= init;
end if;
elsif g_simulation then
nxt.state <= idle;
end if;
when init =>
nxt.do_refresh <= '0';
outp.sdram_a <= c_init_array(cur.init_cnt).addr(12 downto 0);
outp.sdram_ba <= c_init_array(cur.init_cnt).addr(14 downto 13);
outp.sdram_cmd(3) <= '1';
outp.sdram_cmd(2 downto 0) <= c_init_array(cur.init_cnt).cmd(2 downto 0);
if cur.delay = 0 then
nxt.delay <= 7;
if cur.init_cnt = c_init_array'high then
nxt.state <= idle;
else
outp.sdram_cmd(3) <= '0';
nxt.init_cnt <= cur.init_cnt + 1;
end if;
end if;
when idle =>
-- first cycle after inhibit goes 1, should not be a refresh
-- this enables putting cartridge images in sdram, because we guarantee the first access after inhibit to be a cart cycle
if cur.do_refresh='1' and cur.refresh_inhibit='0' then
send_refresh_cmd;
elsif inhibit='0' then -- make sure we are allowed to start a new cycle
if req.request='1' and cur.refr_delay = 0 then
accept_req;
nxt.refresh_inhibit <= '0';
if req.read_writen = '1' then
nxt.state <= sd_read;
else
nxt.state <= sd_write;
end if;
end if;
end if;
when sd_read =>
outp.sdram_ba <= cur.bank_addr;
outp.sdram_a(12 downto 11) <= "00";
outp.sdram_a(10) <= '1'; -- auto precharge
outp.sdram_a(9 downto 0) <= cur.col_addr;
outp.sdram_cmd <= c_cmd_read;
nxt.state <= sd_read_2;
when sd_read_2 =>
nxt.state <= sd_read_3;
when sd_read_3 =>
nxt.dack_pre <= '1';
nxt.dack_tag_pre <= cur.tag;
nxt.state <= idle;
when sd_write =>
outp.sdram_ba <= cur.bank_addr;
outp.sdram_a(12 downto 11) <= "00";
outp.sdram_a(10) <= '1'; -- auto precharge
outp.sdram_a(9 downto 0) <= cur.col_addr;
outp.sdram_cmd <= c_cmd_write;
outp.wdata_16 <= cur.wdata(31 downto 24) & "XXXXXXXX";
outp.wmask_16 <= cur.wmask(3) & "0";
outp.tri <= "01";
nxt.state <= sd_write_2;
when sd_write_2 =>
outp.tri <= "00";
outp.wdata_16 <= cur.wdata(15 downto 8) & cur.wdata(23 downto 16);
outp.wmask_16 <= cur.wmask(1) & cur.wmask(2);
nxt.state <= sd_write_3;
when sd_write_3 =>
outp.tri <= "10";
outp.wdata_16 <= "XXXXXXXX" & cur.wdata(7 downto 0);
outp.wmask_16 <= "0" & cur.wmask(0);
nxt.state <= idle;
when others =>
null;
end case;
if cur.refresh_cnt = SDRAM_Refr_period-1 then
nxt.do_refresh <= '1';
nxt.refresh_cnt <= 0;
else
nxt.refresh_cnt <= cur.refresh_cnt + 1;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
cur <= nxt;
SDRAM_A <= outp.sdram_a;
SDRAM_BA <= outp.sdram_ba;
SDRAM_RASn <= outp.sdram_cmd(2);
SDRAM_CASn <= outp.sdram_cmd(1);
SDRAM_WEn <= outp.sdram_cmd(0);
SDRAM_CKE <= cur.enable_sdram;
rdata <= rdata_hi & rdata_lo;
if reset='1' then
cur.state <= boot;
cur.delay <= 0;
cur.tag <= (others => '0');
cur.do_refresh <= '0';
cur.boot_cnt <= SDRAM_WakeupTime-1;
cur.init_cnt <= 0;
cur.enable_sdram <= '1';
cur.refresh_inhibit <= '0';
end if;
end if;
end process;
not_clock_2x <= not clk_2x;
not_clock <= not clock;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_2x,
C1 => not_clock_2x,
D0 => '0',
D1 => cur.enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
select_out: FDDRRSE
port map (
CE => '1',
C0 => clock,
C1 => not_clock,
D0 => outp.sdram_cmd(3),
D1 => '1',
Q => SDRAM_CSn,
R => '0',
S => '0' );
r_data: for i in 0 to 7 generate
i_in: IDDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q0 => rdata_hi(i),
Q1 => rdata_lo(i),
C0 => clock,
C1 => not_clock,
CE => '1',
D => SDRAM_DQ(i),
R => reset,
S => '0');
i_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => sdram_d_o(i),
C0 => clock,
C1 => not_clock,
CE => '1',
D0 => outp.wdata_16(8+i),
D1 => outp.wdata_16(i),
R => reset,
S => '0' );
i_out_t: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => sdram_t_o(i),
C0 => clock,
C1 => not_clock,
CE => '1',
D0 => outp.tri(1),
D1 => outp.tri(0),
R => reset,
S => '0' );
SDRAM_DQ(i) <= sdram_d_o(i) when sdram_t_o(i)='0' else 'Z';
end generate;
mask_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => SDRAM_DQM,
C0 => clock,
C1 => not_clock,
CE => '1',
D0 => outp.wmask_16(1),
D1 => outp.wmask_16(0),
R => reset,
S => '0' );
end Gideon;
-- 100 MHz
-- ACT to READ: tRCD = 20 ns ( = 2 CLKs)
-- ACT to PRCH: tRAS = 44 ns ( = 5 CLKs)
-- ACT to ACT: tRC = 66 ns ( = 7 CLKs)
-- ACT to ACTb: tRRD = 15 ns ( = 2 CLKs)
-- PRCH time; tRP = 20 ns ( = 2 CLKs)
-- wr. recov. tWR=8ns+1clk ( = 2 CLKs) (starting from last data word)
-- CL=2
-- 0 1 2 3 4 5 6 7 8 9
-- BL1 A - R - - P + - precharge on odd clock
-- - - - - D d d -
-- +: ONLY if same bank, a new ACT command can be given here. Otherwise we don't meet tRC.
-- BL4 A - r - - - p -
-- - - - - D D D D
-- BL1W A - W - - P + - (precharge on odd clock)
-- - - D - - - - -
-- BL4W A - W - - - p -
-- - - D D D D - -
-- Conclusion: In order to meet tRC, without checking for the bank, we always need 80 ns.
-- In order to optimize to 60 ns (using 20 ns logic ticks), we need to add both bank
-- number checking, as well as differentiate between 1 byte and 4 bytes. I think that
-- it is not worthwhile at this point to implement this, so we will use a very rigid
-- 4-tick schedule: one fits all
|
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
END package body fifo_pkg;
|
-- NEED RESULT: ARCH00184.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00184.P2: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00184.P3: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00184.P4: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00184.P5: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00184.P6: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00184
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00184
-- PKG00184/BODY
-- ENT00184(ARCH00184)
-- ENT00184_Test_Bench(ARCH00184_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00184 is
type r_st_arr1_vector is record
f1 : integer ;
f2 : st_arr1_vector ;
end record ;
function c_r_st_arr1_vector_1 return r_st_arr1_vector ;
-- (c_integer_1, c_st_arr1_vector_1) ;
function c_r_st_arr1_vector_2 return r_st_arr1_vector ;
-- (c_integer_2, c_st_arr1_vector_2) ;
--
type r_st_arr2_vector is record
f1 : integer ;
f2 : st_arr2_vector ;
end record ;
function c_r_st_arr2_vector_1 return r_st_arr2_vector ;
-- (c_integer_1, c_st_arr2_vector_1) ;
function c_r_st_arr2_vector_2 return r_st_arr2_vector ;
-- (c_integer_2, c_st_arr2_vector_2) ;
--
type r_st_arr3_vector is record
f1 : integer ;
f2 : st_arr3_vector ;
end record ;
function c_r_st_arr3_vector_1 return r_st_arr3_vector ;
-- (c_integer_1, c_st_arr3_vector_1) ;
function c_r_st_arr3_vector_2 return r_st_arr3_vector ;
-- (c_integer_2, c_st_arr3_vector_2) ;
--
type r_st_rec1_vector is record
f1 : integer ;
f2 : st_rec1_vector ;
end record ;
function c_r_st_rec1_vector_1 return r_st_rec1_vector ;
-- (c_integer_1, c_st_rec1_vector_1) ;
function c_r_st_rec1_vector_2 return r_st_rec1_vector ;
-- (c_integer_2, c_st_rec1_vector_2) ;
--
type r_st_rec2_vector is record
f1 : integer ;
f2 : st_rec2_vector ;
end record ;
function c_r_st_rec2_vector_1 return r_st_rec2_vector ;
-- (c_integer_1, c_st_rec2_vector_1) ;
function c_r_st_rec2_vector_2 return r_st_rec2_vector ;
-- (c_integer_2, c_st_rec2_vector_2) ;
--
type r_st_rec3_vector is record
f1 : integer ;
f2 : st_rec3_vector ;
end record ;
function c_r_st_rec3_vector_1 return r_st_rec3_vector ;
-- (c_integer_1, c_st_rec3_vector_1) ;
function c_r_st_rec3_vector_2 return r_st_rec3_vector ;
-- (c_integer_2, c_st_rec3_vector_2) ;
--
--
end PKG00184 ;
--
package body PKG00184 is
function c_r_st_arr1_vector_1 return r_st_arr1_vector
is begin
return (c_integer_1, c_st_arr1_vector_1) ;
end c_r_st_arr1_vector_1 ;
--
function c_r_st_arr1_vector_2 return r_st_arr1_vector
is begin
return (c_integer_2, c_st_arr1_vector_2) ;
end c_r_st_arr1_vector_2 ;
--
--
function c_r_st_arr2_vector_1 return r_st_arr2_vector
is begin
return (c_integer_1, c_st_arr2_vector_1) ;
end c_r_st_arr2_vector_1 ;
--
function c_r_st_arr2_vector_2 return r_st_arr2_vector
is begin
return (c_integer_2, c_st_arr2_vector_2) ;
end c_r_st_arr2_vector_2 ;
--
--
function c_r_st_arr3_vector_1 return r_st_arr3_vector
is begin
return (c_integer_1, c_st_arr3_vector_1) ;
end c_r_st_arr3_vector_1 ;
--
function c_r_st_arr3_vector_2 return r_st_arr3_vector
is begin
return (c_integer_2, c_st_arr3_vector_2) ;
end c_r_st_arr3_vector_2 ;
--
--
function c_r_st_rec1_vector_1 return r_st_rec1_vector
is begin
return (c_integer_1, c_st_rec1_vector_1) ;
end c_r_st_rec1_vector_1 ;
--
function c_r_st_rec1_vector_2 return r_st_rec1_vector
is begin
return (c_integer_2, c_st_rec1_vector_2) ;
end c_r_st_rec1_vector_2 ;
--
--
function c_r_st_rec2_vector_1 return r_st_rec2_vector
is begin
return (c_integer_1, c_st_rec2_vector_1) ;
end c_r_st_rec2_vector_1 ;
--
function c_r_st_rec2_vector_2 return r_st_rec2_vector
is begin
return (c_integer_2, c_st_rec2_vector_2) ;
end c_r_st_rec2_vector_2 ;
--
--
function c_r_st_rec3_vector_1 return r_st_rec3_vector
is begin
return (c_integer_1, c_st_rec3_vector_1) ;
end c_r_st_rec3_vector_1 ;
--
function c_r_st_rec3_vector_2 return r_st_rec3_vector
is begin
return (c_integer_2, c_st_rec3_vector_2) ;
end c_r_st_rec3_vector_2 ;
--
--
--
end PKG00184 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00184.all ;
entity ENT00184 is
port (
s_r_st_arr1_vector : inout r_st_arr1_vector
; s_r_st_arr2_vector : inout r_st_arr2_vector
; s_r_st_arr3_vector : inout r_st_arr3_vector
; s_r_st_rec1_vector : inout r_st_rec1_vector
; s_r_st_rec2_vector : inout r_st_rec2_vector
; s_r_st_rec3_vector : inout r_st_rec3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_arr1_vector : chk_sig_type := -1 ;
signal chk_r_st_arr2_vector : chk_sig_type := -1 ;
signal chk_r_st_arr3_vector : chk_sig_type := -1 ;
signal chk_r_st_rec1_vector : chk_sig_type := -1 ;
signal chk_r_st_rec2_vector : chk_sig_type := -1 ;
signal chk_r_st_rec3_vector : chk_sig_type := -1 ;
--
--
procedure Proc1 (
signal s_r_st_arr1_vector : inout r_st_arr1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_r_st_arr2_vector : inout r_st_arr2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_arr2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_r_st_arr3_vector : inout r_st_arr3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_arr3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
procedure Proc4 (
signal s_r_st_rec1_vector : inout r_st_rec1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc4 ;
--
procedure Proc5 (
signal s_r_st_rec2_vector : inout r_st_rec2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc5 ;
--
procedure Proc6 (
signal s_r_st_rec3_vector : inout r_st_rec3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc6 ;
--
--
end ENT00184 ;
--
architecture ARCH00184 of ENT00184 is
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_r_st_arr1_vector,
counter,
correct,
savtime,
chk_r_st_arr1_vector
) ;
wait until (not s_r_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_r_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_r_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_r_st_arr2_vector,
counter,
correct,
savtime,
chk_r_st_arr2_vector
) ;
wait until (not s_r_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_r_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_r_st_arr3_vector,
counter,
correct,
savtime,
chk_r_st_arr3_vector
) ;
wait until (not s_r_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_r_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
P4 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc4 (
s_r_st_rec1_vector,
counter,
correct,
savtime,
chk_r_st_rec1_vector
) ;
wait until (not s_r_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_r_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_r_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
P5 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc5 (
s_r_st_rec2_vector,
counter,
correct,
savtime,
chk_r_st_rec2_vector
) ;
wait until (not s_r_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_r_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_r_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
P6 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc6 (
s_r_st_rec3_vector,
counter,
correct,
savtime,
chk_r_st_rec3_vector
) ;
wait until (not s_r_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_r_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_r_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
--
end ARCH00184 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00184.all ;
entity ENT00184_Test_Bench is
signal s_r_st_arr1_vector : r_st_arr1_vector
:= c_r_st_arr1_vector_1 ;
signal s_r_st_arr2_vector : r_st_arr2_vector
:= c_r_st_arr2_vector_1 ;
signal s_r_st_arr3_vector : r_st_arr3_vector
:= c_r_st_arr3_vector_1 ;
signal s_r_st_rec1_vector : r_st_rec1_vector
:= c_r_st_rec1_vector_1 ;
signal s_r_st_rec2_vector : r_st_rec2_vector
:= c_r_st_rec2_vector_1 ;
signal s_r_st_rec3_vector : r_st_rec3_vector
:= c_r_st_rec3_vector_1 ;
--
end ENT00184_Test_Bench ;
--
architecture ARCH00184_Test_Bench of ENT00184_Test_Bench is
begin
L1:
block
component UUT
port (
s_r_st_arr1_vector : inout r_st_arr1_vector
; s_r_st_arr2_vector : inout r_st_arr2_vector
; s_r_st_arr3_vector : inout r_st_arr3_vector
; s_r_st_rec1_vector : inout r_st_rec1_vector
; s_r_st_rec2_vector : inout r_st_rec2_vector
; s_r_st_rec3_vector : inout r_st_rec3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00184 ( ARCH00184 ) ;
begin
CIS1 : UUT
port map (
s_r_st_arr1_vector
, s_r_st_arr2_vector
, s_r_st_arr3_vector
, s_r_st_rec1_vector
, s_r_st_rec2_vector
, s_r_st_rec3_vector
) ;
end block L1 ;
end ARCH00184_Test_Bench ;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- Generated by IP Compiler for PCI Express 11.1 [Altera, IP Toolbench 1.3.0 Build 259]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2014 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY pcie_compiler_0_core IS
PORT (
AvlClk_i : IN STD_LOGIC;
CraAddress_i : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
CraByteEnable_i : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
CraChipSelect_i : IN STD_LOGIC;
CraRead : IN STD_LOGIC;
CraWrite : IN STD_LOGIC;
CraWriteData_i : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
Rstn_i : IN STD_LOGIC;
RxmIrqNum_i : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
RxmIrq_i : IN STD_LOGIC;
RxmReadDataValid_i : IN STD_LOGIC;
RxmReadData_i : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
RxmWaitRequest_i : IN STD_LOGIC;
TxsAddress_i : IN STD_LOGIC_VECTOR (27 DOWNTO 0);
TxsBurstCount_i : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
TxsByteEnable_i : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
TxsChipSelect_i : IN STD_LOGIC;
TxsRead_i : IN STD_LOGIC;
TxsWriteData_i : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
TxsWrite_i : IN STD_LOGIC;
aer_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
app_int_sts : IN STD_LOGIC;
app_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
app_msi_req : IN STD_LOGIC;
app_msi_tc : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
core_clk_in : IN STD_LOGIC;
cpl_err : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
cpl_pending : IN STD_LOGIC;
crst : IN STD_LOGIC;
hpg_ctrler : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
lmi_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
lmi_din : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
lmi_rden : IN STD_LOGIC;
lmi_wren : IN STD_LOGIC;
npor : IN STD_LOGIC;
pclk_central : IN STD_LOGIC;
pclk_ch0 : IN STD_LOGIC;
pex_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
pld_clk : IN STD_LOGIC;
pll_fixed_clk : IN STD_LOGIC;
pm_auxpwr : IN STD_LOGIC;
pm_data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
pm_event : IN STD_LOGIC;
pme_to_cr : IN STD_LOGIC;
rc_areset : IN STD_LOGIC;
rc_inclk_eq_125mhz : IN STD_LOGIC;
rc_pll_locked : IN STD_LOGIC;
rc_rx_pll_locked_one : IN STD_LOGIC;
rx_st_mask0 : IN STD_LOGIC;
rx_st_ready0 : IN STD_LOGIC;
srst : IN STD_LOGIC;
test_in : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
tx_st_data0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
tx_st_data0_p1 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
tx_st_eop0 : IN STD_LOGIC;
tx_st_eop0_p1 : IN STD_LOGIC;
tx_st_err0 : IN STD_LOGIC;
tx_st_sop0 : IN STD_LOGIC;
tx_st_sop0_p1 : IN STD_LOGIC;
tx_st_valid0 : IN STD_LOGIC;
phystatus0_ext : IN STD_LOGIC;
rxdata0_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak0_ext : IN STD_LOGIC;
rxelecidle0_ext : IN STD_LOGIC;
rxstatus0_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid0_ext : IN STD_LOGIC;
CraIrq_o : OUT STD_LOGIC;
CraReadData_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
CraWaitRequest_o : OUT STD_LOGIC;
RxmAddress_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
RxmBurstCount_o : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
RxmByteEnable_o : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
RxmRead_o : OUT STD_LOGIC;
RxmWriteData_o : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
RxmWrite_o : OUT STD_LOGIC;
TxsReadDataValid_o : OUT STD_LOGIC;
TxsReadData_o : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
TxsWaitRequest_o : OUT STD_LOGIC;
app_int_ack : OUT STD_LOGIC;
app_msi_ack : OUT STD_LOGIC;
avs_pcie_reconfig_readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
avs_pcie_reconfig_readdatavalid : OUT STD_LOGIC;
avs_pcie_reconfig_waitrequest : OUT STD_LOGIC;
core_clk_out : OUT STD_LOGIC;
derr_cor_ext_rcv0 : OUT STD_LOGIC;
derr_cor_ext_rpl : OUT STD_LOGIC;
derr_rpl : OUT STD_LOGIC;
dl_ltssm : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
dlup_exit : OUT STD_LOGIC;
eidle_infer_sel : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
ev_128ns : OUT STD_LOGIC;
ev_1us : OUT STD_LOGIC;
hip_extraclkout : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
hotrst_exit : OUT STD_LOGIC;
int_status : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
l2_exit : OUT STD_LOGIC;
lane_act : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
lmi_ack : OUT STD_LOGIC;
lmi_dout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
npd_alloc_1cred_vc0 : OUT STD_LOGIC;
npd_cred_vio_vc0 : OUT STD_LOGIC;
nph_alloc_1cred_vc0 : OUT STD_LOGIC;
nph_cred_vio_vc0 : OUT STD_LOGIC;
pme_to_sr : OUT STD_LOGIC;
r2c_err0 : OUT STD_LOGIC;
rate_ext : OUT STD_LOGIC;
rc_gxb_powerdown : OUT STD_LOGIC;
rc_rx_analogreset : OUT STD_LOGIC;
rc_rx_digitalreset : OUT STD_LOGIC;
rc_tx_digitalreset : OUT STD_LOGIC;
reset_status : OUT STD_LOGIC;
rx_fifo_empty0 : OUT STD_LOGIC;
rx_fifo_full0 : OUT STD_LOGIC;
rx_st_bardec0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_be0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_be0_p1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_data0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
rx_st_data0_p1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
rx_st_eop0 : OUT STD_LOGIC;
rx_st_eop0_p1 : OUT STD_LOGIC;
rx_st_err0 : OUT STD_LOGIC;
rx_st_sop0 : OUT STD_LOGIC;
rx_st_sop0_p1 : OUT STD_LOGIC;
rx_st_valid0 : OUT STD_LOGIC;
serr_out : OUT STD_LOGIC;
suc_spd_neg : OUT STD_LOGIC;
swdn_wake : OUT STD_LOGIC;
swup_hotrst : OUT STD_LOGIC;
test_out : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
tl_cfg_ctl_wr : OUT STD_LOGIC;
tl_cfg_sts : OUT STD_LOGIC_VECTOR (52 DOWNTO 0);
tl_cfg_sts_wr : OUT STD_LOGIC;
tx_cred0 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
tx_deemph : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
tx_fifo_empty0 : OUT STD_LOGIC;
tx_fifo_full0 : OUT STD_LOGIC;
tx_fifo_rdptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
tx_fifo_wrptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
tx_margin : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
tx_st_ready0 : OUT STD_LOGIC;
use_pcie_reconfig : OUT STD_LOGIC;
wake_oen : OUT STD_LOGIC;
powerdown0_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity0_ext : OUT STD_LOGIC;
txcompl0_ext : OUT STD_LOGIC;
txdata0_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak0_ext : OUT STD_LOGIC;
txdetectrx0_ext : OUT STD_LOGIC;
txelecidle0_ext : OUT STD_LOGIC
);
END pcie_compiler_0_core;
ARCHITECTURE SYN OF pcie_compiler_0_core IS
SIGNAL signal_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire1 : STD_LOGIC;
SIGNAL signal_wire2 : STD_LOGIC;
SIGNAL signal_wire3 : STD_LOGIC;
SIGNAL signal_wire4 : STD_LOGIC;
SIGNAL signal_wire5 : STD_LOGIC;
SIGNAL signal_wire6 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL signal_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL signal_wire8 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire9 : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL signal_wire10 : STD_LOGIC;
SIGNAL signal_wire11 : STD_LOGIC;
SIGNAL signal_wire12 : STD_LOGIC;
SIGNAL signal_wire13 : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL signal_wire14 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL signal_wire15 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire16 : STD_LOGIC;
SIGNAL signal_wire17 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire18 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL signal_wire19 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL signal_wire20 : STD_LOGIC;
SIGNAL signal_wire21 : STD_LOGIC;
SIGNAL signal_wire22 : STD_LOGIC;
SIGNAL signal_wire23 : STD_LOGIC;
SIGNAL signal_wire24 : STD_LOGIC;
SIGNAL signal_wire25 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire26 : STD_LOGIC;
SIGNAL signal_wire27 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL signal_wire28 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire29 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL signal_wire30 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire31 : STD_LOGIC;
SIGNAL signal_wire32 : STD_LOGIC;
SIGNAL signal_wire33 : STD_LOGIC_VECTOR (63 DOWNTO 0);
SIGNAL signal_wire34 : STD_LOGIC_VECTOR (63 DOWNTO 0);
SIGNAL signal_wire35 : STD_LOGIC;
SIGNAL signal_wire36 : STD_LOGIC;
SIGNAL signal_wire37 : STD_LOGIC;
SIGNAL signal_wire38 : STD_LOGIC;
SIGNAL signal_wire39 : STD_LOGIC;
SIGNAL signal_wire40 : STD_LOGIC;
SIGNAL signal_wire41 : STD_LOGIC;
SIGNAL signal_wire42 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire43 : STD_LOGIC;
SIGNAL signal_wire44 : STD_LOGIC;
SIGNAL signal_wire45 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire46 : STD_LOGIC;
SIGNAL signal_wire47 : STD_LOGIC;
SIGNAL signal_wire48 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire49 : STD_LOGIC;
SIGNAL signal_wire50 : STD_LOGIC;
SIGNAL signal_wire51 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire52 : STD_LOGIC;
SIGNAL signal_wire53 : STD_LOGIC;
SIGNAL signal_wire54 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire55 : STD_LOGIC;
SIGNAL signal_wire56 : STD_LOGIC;
SIGNAL signal_wire57 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire58 : STD_LOGIC;
SIGNAL signal_wire59 : STD_LOGIC;
SIGNAL signal_wire60 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire61 : STD_LOGIC;
SIGNAL signal_wire62 : STD_LOGIC;
SIGNAL signal_wire63 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire64 : STD_LOGIC;
SIGNAL signal_wire65 : STD_LOGIC;
SIGNAL signal_wire66 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire67 : STD_LOGIC;
SIGNAL signal_wire68 : STD_LOGIC;
SIGNAL signal_wire69 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire70 : STD_LOGIC;
SIGNAL signal_wire71 : STD_LOGIC;
SIGNAL signal_wire72 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire73 : STD_LOGIC;
SIGNAL signal_wire74 : STD_LOGIC;
SIGNAL signal_wire75 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire76 : STD_LOGIC;
SIGNAL signal_wire77 : STD_LOGIC;
SIGNAL signal_wire78 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire79 : STD_LOGIC;
SIGNAL signal_wire80 : STD_LOGIC;
SIGNAL signal_wire81 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire82 : STD_LOGIC;
COMPONENT altpcie_hip_pipen1b
GENERIC (
tx_cdc_full_value : NATURAL;
CB_PCIE_MODE : NATURAL;
CG_AVALON_S_ADDR_WIDTH : NATURAL;
CG_COMMON_CLOCK_MODE : NATURAL;
CG_IMPL_CRA_AV_SLAVE_PORT : NATURAL;
INTENDED_DEVICE_FAMILY : STRING;
CB_A2P_ADDR_MAP_NUM_ENTRIES : NATURAL;
CB_A2P_ADDR_MAP_PASS_THRU_BITS : NATURAL;
CB_A2P_ADDR_MAP_IS_FIXED : NATURAL;
CB_A2P_ADDR_MAP_FIXED_TABLE : STD_LOGIC_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000";
CB_P2A_AVALON_ADDR_B0 : STD_LOGIC_VECTOR := X"00000000";
CB_P2A_AVALON_ADDR_B1 : STD_LOGIC_VECTOR := X"00040000";
CB_P2A_AVALON_ADDR_B2 : STD_LOGIC_VECTOR := X"00000000";
CB_P2A_AVALON_ADDR_B3 : STD_LOGIC_VECTOR := X"00000000";
CB_P2A_AVALON_ADDR_B4 : STD_LOGIC_VECTOR := X"00000000";
CB_P2A_AVALON_ADDR_B5 : STD_LOGIC_VECTOR := X"00000000";
TL_SELECTION : NATURAL;
bypass_tl : STRING;
AST_LITE : NATURAL;
p_pcie_hip_type : STRING;
retry_buffer_last_active_address : STRING;
advanced_errors : STRING;
bar0_io_space : STRING;
bar0_64bit_mem_space : STRING;
bar0_prefetchable : STRING;
bar0_size_mask : NATURAL;
bar1_io_space : STRING;
bar1_64bit_mem_space : STRING;
bar1_prefetchable : STRING;
bar1_size_mask : NATURAL;
enable_ecrc_check : STRING;
enable_ecrc_gen : STRING;
enable_l1_aspm : STRING;
l01_entry_latency : NATURAL;
core_clk_source : STRING;
pcie_mode : STRING;
expansion_base_address_register : NATURAL;
extend_tag_field : STRING;
bypass_cdc : STRING;
vc_arbitration : NATURAL;
no_soft_reset : STRING;
enable_ch0_pclk_out : STRING;
core_clk_divider : NATURAL;
millisecond_cycle_count : NATURAL;
single_rx_detect : NATURAL;
enable_coreclk_out_half_rate : STRING;
enable_gen2_core : STRING;
gen2_lane_rate_mode : STRING;
lane_mask : STD_LOGIC_VECTOR := B"11111110";
max_link_width : NATURAL;
vendor_id : NATURAL;
device_id : NATURAL;
revision_id : NATURAL;
class_code : NATURAL;
subsystem_vendor_id : NATURAL;
subsystem_device_id : NATURAL;
port_link_number : NATURAL;
vc_enable : STD_LOGIC_VECTOR := B"0000000";
vc1_clk_enable : STRING;
low_priority_vc : NATURAL;
max_payload_size : NATURAL;
msi_function_count : NATURAL;
endpoint_l0_latency : NATURAL;
endpoint_l1_latency : NATURAL;
diffclock_nfts_count : NATURAL;
sameclock_nfts_count : NATURAL;
l1_exit_latency_sameclock : NATURAL;
l1_exit_latency_diffclock : NATURAL;
l0_exit_latency_sameclock : NATURAL;
l0_exit_latency_diffclock : NATURAL;
enable_msi_64bit_addressing : STRING;
gen2_diffclock_nfts_count : NATURAL;
gen2_sameclock_nfts_count : NATURAL;
enable_function_msix_support : STRING;
credit_buffer_allocation_aux : STRING;
eie_before_nfts_count : NATURAL;
enable_completion_timeout_disable : STRING;
completion_timeout : STRING;
enable_adapter_half_rate_mode : STRING;
msix_pba_bir : NATURAL;
msix_pba_offset : NATURAL;
msix_table_bir : NATURAL;
msix_table_offset : NATURAL;
msix_table_size : NATURAL;
use_crc_forwarding : STRING;
surprise_down_error_support : STRING;
dll_active_report_support : STRING;
bar_io_window_size : STRING;
bar_prefetchable : NATURAL;
hot_plug_support : STD_LOGIC_VECTOR := B"0000000";
no_command_completed : STRING;
slot_power_limit : NATURAL;
slot_power_scale : NATURAL;
slot_number : NATURAL;
enable_slot_register : STRING;
vc0_rx_flow_ctrl_posted_header : NATURAL;
vc0_rx_flow_ctrl_posted_data : NATURAL;
vc0_rx_flow_ctrl_nonposted_header : NATURAL;
vc0_rx_flow_ctrl_nonposted_data : NATURAL;
vc0_rx_flow_ctrl_compl_header : NATURAL;
vc0_rx_flow_ctrl_compl_data : NATURAL;
RX_BUF : NATURAL;
RH_NUM : NATURAL;
G_TAG_NUM0 : NATURAL
);
PORT (
AvlClk_i : IN STD_LOGIC;
CraAddress_i : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
CraByteEnable_i : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
CraChipSelect_i : IN STD_LOGIC;
CraRead : IN STD_LOGIC;
CraWrite : IN STD_LOGIC;
CraWriteData_i : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
Rstn_i : IN STD_LOGIC;
RxmIrqNum_i : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
RxmIrq_i : IN STD_LOGIC;
RxmReadDataValid_i : IN STD_LOGIC;
RxmReadData_i : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
RxmWaitRequest_i : IN STD_LOGIC;
TxsAddress_i : IN STD_LOGIC_VECTOR (27 DOWNTO 0);
TxsBurstCount_i : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
TxsByteEnable_i : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
TxsChipSelect_i : IN STD_LOGIC;
TxsRead_i : IN STD_LOGIC;
TxsWriteData_i : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
TxsWrite_i : IN STD_LOGIC;
aer_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
app_int_sts : IN STD_LOGIC;
app_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
app_msi_req : IN STD_LOGIC;
app_msi_tc : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
avs_pcie_reconfig_address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
avs_pcie_reconfig_chipselect : IN STD_LOGIC;
avs_pcie_reconfig_clk : IN STD_LOGIC;
avs_pcie_reconfig_read : IN STD_LOGIC;
avs_pcie_reconfig_rstn : IN STD_LOGIC;
avs_pcie_reconfig_write : IN STD_LOGIC;
avs_pcie_reconfig_writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
core_clk_in : IN STD_LOGIC;
cpl_err : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
cpl_pending : IN STD_LOGIC;
crst : IN STD_LOGIC;
hpg_ctrler : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
lmi_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
lmi_din : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
lmi_rden : IN STD_LOGIC;
lmi_wren : IN STD_LOGIC;
mode : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
npor : IN STD_LOGIC;
pclk_central : IN STD_LOGIC;
pclk_ch0 : IN STD_LOGIC;
pex_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
pld_clk : IN STD_LOGIC;
pll_fixed_clk : IN STD_LOGIC;
pm_auxpwr : IN STD_LOGIC;
pm_data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
pm_event : IN STD_LOGIC;
pme_to_cr : IN STD_LOGIC;
rc_areset : IN STD_LOGIC;
rc_inclk_eq_125mhz : IN STD_LOGIC;
rc_pll_locked : IN STD_LOGIC;
rc_rx_pll_locked_one : IN STD_LOGIC;
rx_st_mask0 : IN STD_LOGIC;
rx_st_ready0 : IN STD_LOGIC;
srst : IN STD_LOGIC;
swdn_in : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
swup_in : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
test_in : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
tl_slotclk_cfg : IN STD_LOGIC;
tlbp_dl_aspm_cr0 : IN STD_LOGIC;
tlbp_dl_comclk_reg : IN STD_LOGIC;
tlbp_dl_ctrl_link2 : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
tlbp_dl_data_upfc : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
tlbp_dl_hdr_upfc : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
tlbp_dl_inh_dllp : IN STD_LOGIC;
tlbp_dl_maxpload_dcr : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
tlbp_dl_req_phycfg : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
tlbp_dl_req_phypm : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
tlbp_dl_req_upfc : IN STD_LOGIC;
tlbp_dl_req_wake : IN STD_LOGIC;
tlbp_dl_rx_ecrcchk : IN STD_LOGIC;
tlbp_dl_snd_upfc : IN STD_LOGIC;
tlbp_dl_tx_reqpm : IN STD_LOGIC;
tlbp_dl_tx_typpm : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
tlbp_dl_txcfg_extsy : IN STD_LOGIC;
tlbp_dl_typ_upfc : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
tlbp_dl_vc_ctrl : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
tlbp_dl_vcid_map : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
tlbp_dl_vcid_upfc : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
tx_st_data0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
tx_st_data0_p1 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
tx_st_eop0 : IN STD_LOGIC;
tx_st_eop0_p1 : IN STD_LOGIC;
tx_st_err0 : IN STD_LOGIC;
tx_st_sop0 : IN STD_LOGIC;
tx_st_sop0_p1 : IN STD_LOGIC;
tx_st_valid0 : IN STD_LOGIC;
rx_st_mask1 : IN STD_LOGIC;
rx_st_ready1 : IN STD_LOGIC;
tx_st_data1 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
tx_st_data1_p1 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
tx_st_eop1 : IN STD_LOGIC;
tx_st_eop1_p1 : IN STD_LOGIC;
tx_st_err1 : IN STD_LOGIC;
tx_st_sop1 : IN STD_LOGIC;
tx_st_sop1_p1 : IN STD_LOGIC;
tx_st_valid1 : IN STD_LOGIC;
phystatus0_ext : IN STD_LOGIC;
rxdata0_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak0_ext : IN STD_LOGIC;
rxelecidle0_ext : IN STD_LOGIC;
rxstatus0_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid0_ext : IN STD_LOGIC;
phystatus1_ext : IN STD_LOGIC;
rxdata1_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak1_ext : IN STD_LOGIC;
rxelecidle1_ext : IN STD_LOGIC;
rxstatus1_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid1_ext : IN STD_LOGIC;
phystatus2_ext : IN STD_LOGIC;
rxdata2_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak2_ext : IN STD_LOGIC;
rxelecidle2_ext : IN STD_LOGIC;
rxstatus2_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid2_ext : IN STD_LOGIC;
phystatus3_ext : IN STD_LOGIC;
rxdata3_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak3_ext : IN STD_LOGIC;
rxelecidle3_ext : IN STD_LOGIC;
rxstatus3_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid3_ext : IN STD_LOGIC;
phystatus4_ext : IN STD_LOGIC;
rxdata4_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak4_ext : IN STD_LOGIC;
rxelecidle4_ext : IN STD_LOGIC;
rxstatus4_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid4_ext : IN STD_LOGIC;
phystatus5_ext : IN STD_LOGIC;
rxdata5_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak5_ext : IN STD_LOGIC;
rxelecidle5_ext : IN STD_LOGIC;
rxstatus5_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid5_ext : IN STD_LOGIC;
phystatus6_ext : IN STD_LOGIC;
rxdata6_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak6_ext : IN STD_LOGIC;
rxelecidle6_ext : IN STD_LOGIC;
rxstatus6_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid6_ext : IN STD_LOGIC;
phystatus7_ext : IN STD_LOGIC;
rxdata7_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak7_ext : IN STD_LOGIC;
rxelecidle7_ext : IN STD_LOGIC;
rxstatus7_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid7_ext : IN STD_LOGIC;
CraIrq_o : OUT STD_LOGIC;
CraReadData_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
CraWaitRequest_o : OUT STD_LOGIC;
RxmAddress_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
RxmBurstCount_o : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
RxmByteEnable_o : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
RxmRead_o : OUT STD_LOGIC;
RxmWriteData_o : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
RxmWrite_o : OUT STD_LOGIC;
TxsReadDataValid_o : OUT STD_LOGIC;
TxsReadData_o : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
TxsWaitRequest_o : OUT STD_LOGIC;
app_int_ack : OUT STD_LOGIC;
app_msi_ack : OUT STD_LOGIC;
avs_pcie_reconfig_readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
avs_pcie_reconfig_readdatavalid : OUT STD_LOGIC;
avs_pcie_reconfig_waitrequest : OUT STD_LOGIC;
core_clk_out : OUT STD_LOGIC;
derr_cor_ext_rcv0 : OUT STD_LOGIC;
derr_cor_ext_rpl : OUT STD_LOGIC;
derr_rpl : OUT STD_LOGIC;
dl_ltssm : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
dlup_exit : OUT STD_LOGIC;
eidle_infer_sel : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
ev_128ns : OUT STD_LOGIC;
ev_1us : OUT STD_LOGIC;
hip_extraclkout : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
hotrst_exit : OUT STD_LOGIC;
int_status : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
l2_exit : OUT STD_LOGIC;
lane_act : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
lmi_ack : OUT STD_LOGIC;
lmi_dout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
npd_alloc_1cred_vc0 : OUT STD_LOGIC;
npd_cred_vio_vc0 : OUT STD_LOGIC;
nph_alloc_1cred_vc0 : OUT STD_LOGIC;
nph_cred_vio_vc0 : OUT STD_LOGIC;
pme_to_sr : OUT STD_LOGIC;
r2c_err0 : OUT STD_LOGIC;
rate_ext : OUT STD_LOGIC;
rc_gxb_powerdown : OUT STD_LOGIC;
rc_rx_analogreset : OUT STD_LOGIC;
rc_rx_digitalreset : OUT STD_LOGIC;
rc_tx_digitalreset : OUT STD_LOGIC;
reset_status : OUT STD_LOGIC;
rx_fifo_empty0 : OUT STD_LOGIC;
rx_fifo_full0 : OUT STD_LOGIC;
rx_st_bardec0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_be0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_be0_p1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_data0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
rx_st_data0_p1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
rx_st_eop0 : OUT STD_LOGIC;
rx_st_eop0_p1 : OUT STD_LOGIC;
rx_st_err0 : OUT STD_LOGIC;
rx_st_sop0 : OUT STD_LOGIC;
rx_st_sop0_p1 : OUT STD_LOGIC;
rx_st_valid0 : OUT STD_LOGIC;
serr_out : OUT STD_LOGIC;
suc_spd_neg : OUT STD_LOGIC;
swdn_wake : OUT STD_LOGIC;
swup_hotrst : OUT STD_LOGIC;
test_out : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
tl_cfg_ctl_wr : OUT STD_LOGIC;
tl_cfg_sts : OUT STD_LOGIC_VECTOR (52 DOWNTO 0);
tl_cfg_sts_wr : OUT STD_LOGIC;
tlbp_dl_ack_phypm : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
tlbp_dl_ack_requpfc : OUT STD_LOGIC;
tlbp_dl_ack_sndupfc : OUT STD_LOGIC;
tlbp_dl_current_deemp : OUT STD_LOGIC;
tlbp_dl_currentspeed : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
tlbp_dl_dll_req : OUT STD_LOGIC;
tlbp_dl_err_dll : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
tlbp_dl_errphy : OUT STD_LOGIC;
tlbp_dl_link_autobdw_status : OUT STD_LOGIC;
tlbp_dl_link_bdwmng_status : OUT STD_LOGIC;
tlbp_dl_rpbuf_emp : OUT STD_LOGIC;
tlbp_dl_rst_enter_comp_bit : OUT STD_LOGIC;
tlbp_dl_rst_tx_margin_field : OUT STD_LOGIC;
tlbp_dl_rx_typ_pm : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
tlbp_dl_rx_valpm : OUT STD_LOGIC;
tlbp_dl_tx_ackpm : OUT STD_LOGIC;
tlbp_dl_up : OUT STD_LOGIC;
tlbp_dl_vc_status : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
tlbp_link_up : OUT STD_LOGIC;
tx_cred0 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
tx_deemph : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
tx_fifo_empty0 : OUT STD_LOGIC;
tx_fifo_full0 : OUT STD_LOGIC;
tx_fifo_rdptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
tx_fifo_wrptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
tx_margin : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
tx_st_ready0 : OUT STD_LOGIC;
use_pcie_reconfig : OUT STD_LOGIC;
wake_oen : OUT STD_LOGIC;
derr_cor_ext_rcv1 : OUT STD_LOGIC;
npd_alloc_1cred_vc1 : OUT STD_LOGIC;
npd_cred_vio_vc1 : OUT STD_LOGIC;
nph_alloc_1cred_vc1 : OUT STD_LOGIC;
nph_cred_vio_vc1 : OUT STD_LOGIC;
r2c_err1 : OUT STD_LOGIC;
rx_fifo_empty1 : OUT STD_LOGIC;
rx_fifo_full1 : OUT STD_LOGIC;
rx_st_bardec1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_be1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_be1_p1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_data1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
rx_st_data1_p1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
rx_st_eop1 : OUT STD_LOGIC;
rx_st_eop1_p1 : OUT STD_LOGIC;
rx_st_err1 : OUT STD_LOGIC;
rx_st_sop1 : OUT STD_LOGIC;
rx_st_sop1_p1 : OUT STD_LOGIC;
rx_st_valid1 : OUT STD_LOGIC;
tx_cred1 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
tx_fifo_empty1 : OUT STD_LOGIC;
tx_fifo_full1 : OUT STD_LOGIC;
tx_fifo_rdptr1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
tx_fifo_wrptr1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
tx_st_ready1 : OUT STD_LOGIC;
powerdown0_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity0_ext : OUT STD_LOGIC;
txcompl0_ext : OUT STD_LOGIC;
txdata0_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak0_ext : OUT STD_LOGIC;
txdetectrx0_ext : OUT STD_LOGIC;
txelecidle0_ext : OUT STD_LOGIC;
powerdown1_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity1_ext : OUT STD_LOGIC;
txcompl1_ext : OUT STD_LOGIC;
txdata1_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak1_ext : OUT STD_LOGIC;
txdetectrx1_ext : OUT STD_LOGIC;
txelecidle1_ext : OUT STD_LOGIC;
powerdown2_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity2_ext : OUT STD_LOGIC;
txcompl2_ext : OUT STD_LOGIC;
txdata2_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak2_ext : OUT STD_LOGIC;
txdetectrx2_ext : OUT STD_LOGIC;
txelecidle2_ext : OUT STD_LOGIC;
powerdown3_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity3_ext : OUT STD_LOGIC;
txcompl3_ext : OUT STD_LOGIC;
txdata3_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak3_ext : OUT STD_LOGIC;
txdetectrx3_ext : OUT STD_LOGIC;
txelecidle3_ext : OUT STD_LOGIC;
powerdown4_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity4_ext : OUT STD_LOGIC;
txcompl4_ext : OUT STD_LOGIC;
txdata4_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak4_ext : OUT STD_LOGIC;
txdetectrx4_ext : OUT STD_LOGIC;
txelecidle4_ext : OUT STD_LOGIC;
powerdown5_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity5_ext : OUT STD_LOGIC;
txcompl5_ext : OUT STD_LOGIC;
txdata5_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak5_ext : OUT STD_LOGIC;
txdetectrx5_ext : OUT STD_LOGIC;
txelecidle5_ext : OUT STD_LOGIC;
powerdown6_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity6_ext : OUT STD_LOGIC;
txcompl6_ext : OUT STD_LOGIC;
txdata6_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak6_ext : OUT STD_LOGIC;
txdetectrx6_ext : OUT STD_LOGIC;
txelecidle6_ext : OUT STD_LOGIC;
powerdown7_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity7_ext : OUT STD_LOGIC;
txcompl7_ext : OUT STD_LOGIC;
txdata7_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak7_ext : OUT STD_LOGIC;
txdetectrx7_ext : OUT STD_LOGIC;
txelecidle7_ext : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
signal_wire0 <= (others => '0');
signal_wire1 <= '0';
signal_wire2 <= '0';
signal_wire3 <= '0';
signal_wire4 <= '0';
signal_wire5 <= '0';
signal_wire6 <= (others => '0');
signal_wire7 <= (others => '0');
signal_wire8 <= (others => '0');
signal_wire9 <= (others => '0');
signal_wire10 <= '1';
signal_wire11 <= '0';
signal_wire12 <= '0';
signal_wire13 <= (others => '0');
signal_wire14 <= (others => '0');
signal_wire15 <= (others => '0');
signal_wire16 <= '0';
signal_wire17 <= (others => '0');
signal_wire18 <= (others => '0');
signal_wire19 <= (others => '0');
signal_wire20 <= '0';
signal_wire21 <= '0';
signal_wire22 <= '0';
signal_wire23 <= '0';
signal_wire24 <= '0';
signal_wire25 <= (others => '0');
signal_wire26 <= '0';
signal_wire27 <= (others => '0');
signal_wire28 <= (others => '0');
signal_wire29 <= (others => '0');
signal_wire30 <= (others => '0');
signal_wire31 <= '0';
signal_wire32 <= '0';
signal_wire33 <= (others => '0');
signal_wire34 <= (others => '0');
signal_wire35 <= '0';
signal_wire36 <= '0';
signal_wire37 <= '0';
signal_wire38 <= '0';
signal_wire39 <= '0';
signal_wire40 <= '0';
signal_wire41 <= '0';
signal_wire42 <= (others => '0');
signal_wire43 <= '0';
signal_wire44 <= '0';
signal_wire45 <= (others => '0');
signal_wire46 <= '0';
signal_wire47 <= '0';
signal_wire48 <= (others => '0');
signal_wire49 <= '0';
signal_wire50 <= '0';
signal_wire51 <= (others => '0');
signal_wire52 <= '0';
signal_wire53 <= '0';
signal_wire54 <= (others => '0');
signal_wire55 <= '0';
signal_wire56 <= '0';
signal_wire57 <= (others => '0');
signal_wire58 <= '0';
signal_wire59 <= '0';
signal_wire60 <= (others => '0');
signal_wire61 <= '0';
signal_wire62 <= '0';
signal_wire63 <= (others => '0');
signal_wire64 <= '0';
signal_wire65 <= '0';
signal_wire66 <= (others => '0');
signal_wire67 <= '0';
signal_wire68 <= '0';
signal_wire69 <= (others => '0');
signal_wire70 <= '0';
signal_wire71 <= '0';
signal_wire72 <= (others => '0');
signal_wire73 <= '0';
signal_wire74 <= '0';
signal_wire75 <= (others => '0');
signal_wire76 <= '0';
signal_wire77 <= '0';
signal_wire78 <= (others => '0');
signal_wire79 <= '0';
signal_wire80 <= '0';
signal_wire81 <= (others => '0');
signal_wire82 <= '0';
altpcie_hip_pipen1b_inst : altpcie_hip_pipen1b
GENERIC MAP (
tx_cdc_full_value => 12,
CB_PCIE_MODE => 0,
CG_AVALON_S_ADDR_WIDTH => 31,
CG_COMMON_CLOCK_MODE => 1,
CG_IMPL_CRA_AV_SLAVE_PORT => 1,
INTENDED_DEVICE_FAMILY => "Cyclone IV GX",
CB_A2P_ADDR_MAP_NUM_ENTRIES => 2,
CB_A2P_ADDR_MAP_PASS_THRU_BITS => 30,
CB_A2P_ADDR_MAP_IS_FIXED => 0,
CB_A2P_ADDR_MAP_FIXED_TABLE => X"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000",
CB_P2A_AVALON_ADDR_B0 => X"00000000",
CB_P2A_AVALON_ADDR_B1 => X"00040000",
CB_P2A_AVALON_ADDR_B2 => X"00000000",
CB_P2A_AVALON_ADDR_B3 => X"00000000",
CB_P2A_AVALON_ADDR_B4 => X"00000000",
CB_P2A_AVALON_ADDR_B5 => X"00000000",
TL_SELECTION => 1,
bypass_tl => "true",
AST_LITE => 0,
p_pcie_hip_type => "2",
retry_buffer_last_active_address => "255",
advanced_errors => "false",
bar0_io_space => "false",
bar0_64bit_mem_space => "false",
bar0_prefetchable => "false",
bar0_size_mask => 15,
bar1_io_space => "false",
bar1_64bit_mem_space => "false",
bar1_prefetchable => "false",
bar1_size_mask => 18,
enable_ecrc_check => "false",
enable_ecrc_gen => "false",
enable_l1_aspm => "false",
l01_entry_latency => 31,
core_clk_source => "pclk",
pcie_mode => "SHARED_MODE",
expansion_base_address_register => 0,
extend_tag_field => "false",
bypass_cdc => "false",
vc_arbitration => 0,
no_soft_reset => "false",
enable_ch0_pclk_out => "true",
core_clk_divider => 4,
millisecond_cycle_count => 125000,
single_rx_detect => 1,
enable_coreclk_out_half_rate => "false",
enable_gen2_core => "false",
gen2_lane_rate_mode => "false",
lane_mask => B"11111110",
max_link_width => 1,
vendor_id => 6997,
device_id => 6390,
revision_id => 2,
class_code => 294912,
subsystem_vendor_id => 6997,
subsystem_device_id => 6390,
port_link_number => 1,
vc_enable => B"0000000",
vc1_clk_enable => "false",
low_priority_vc => 0,
max_payload_size => 1,
msi_function_count => 0,
endpoint_l0_latency => 0,
endpoint_l1_latency => 0,
diffclock_nfts_count => 255,
sameclock_nfts_count => 255,
l1_exit_latency_sameclock => 7,
l1_exit_latency_diffclock => 7,
l0_exit_latency_sameclock => 7,
l0_exit_latency_diffclock => 7,
enable_msi_64bit_addressing => "true",
gen2_diffclock_nfts_count => 255,
gen2_sameclock_nfts_count => 255,
enable_function_msix_support => "false",
credit_buffer_allocation_aux => "ABSOLUTE",
eie_before_nfts_count => 4,
enable_completion_timeout_disable => "false",
completion_timeout => "NONE",
enable_adapter_half_rate_mode => "false",
msix_pba_bir => 0,
msix_pba_offset => 0,
msix_table_bir => 0,
msix_table_offset => 0,
msix_table_size => 0,
use_crc_forwarding => "false",
surprise_down_error_support => "false",
dll_active_report_support => "false",
bar_io_window_size => "32BIT",
bar_prefetchable => 32,
hot_plug_support => B"0000000",
no_command_completed => "true",
slot_power_limit => 0,
slot_power_scale => 0,
slot_number => 0,
enable_slot_register => "false",
vc0_rx_flow_ctrl_posted_header => 28,
vc0_rx_flow_ctrl_posted_data => 198,
vc0_rx_flow_ctrl_nonposted_header => 30,
vc0_rx_flow_ctrl_nonposted_data => 0,
vc0_rx_flow_ctrl_compl_header => 0,
vc0_rx_flow_ctrl_compl_data => 0,
RX_BUF => 10,
RH_NUM => 7,
G_TAG_NUM0 => 32
)
PORT MAP (
AvlClk_i => AvlClk_i,
CraAddress_i => CraAddress_i,
CraByteEnable_i => CraByteEnable_i,
CraChipSelect_i => CraChipSelect_i,
CraRead => CraRead,
CraWrite => CraWrite,
CraWriteData_i => CraWriteData_i,
Rstn_i => Rstn_i,
RxmIrqNum_i => RxmIrqNum_i,
RxmIrq_i => RxmIrq_i,
RxmReadDataValid_i => RxmReadDataValid_i,
RxmReadData_i => RxmReadData_i,
RxmWaitRequest_i => RxmWaitRequest_i,
TxsAddress_i => TxsAddress_i,
TxsBurstCount_i => TxsBurstCount_i,
TxsByteEnable_i => TxsByteEnable_i,
TxsChipSelect_i => TxsChipSelect_i,
TxsRead_i => TxsRead_i,
TxsWriteData_i => TxsWriteData_i,
TxsWrite_i => TxsWrite_i,
aer_msi_num => aer_msi_num,
app_int_sts => app_int_sts,
app_msi_num => app_msi_num,
app_msi_req => app_msi_req,
app_msi_tc => app_msi_tc,
avs_pcie_reconfig_address => signal_wire0,
avs_pcie_reconfig_chipselect => signal_wire1,
avs_pcie_reconfig_clk => signal_wire2,
avs_pcie_reconfig_read => signal_wire3,
avs_pcie_reconfig_rstn => signal_wire4,
avs_pcie_reconfig_write => signal_wire5,
avs_pcie_reconfig_writedata => signal_wire6,
core_clk_in => core_clk_in,
cpl_err => cpl_err,
cpl_pending => cpl_pending,
crst => crst,
hpg_ctrler => hpg_ctrler,
lmi_addr => lmi_addr,
lmi_din => lmi_din,
lmi_rden => lmi_rden,
lmi_wren => lmi_wren,
mode => signal_wire7,
npor => npor,
pclk_central => pclk_central,
pclk_ch0 => pclk_ch0,
pex_msi_num => pex_msi_num,
pld_clk => pld_clk,
pll_fixed_clk => pll_fixed_clk,
pm_auxpwr => pm_auxpwr,
pm_data => pm_data,
pm_event => pm_event,
pme_to_cr => pme_to_cr,
rc_areset => rc_areset,
rc_inclk_eq_125mhz => rc_inclk_eq_125mhz,
rc_pll_locked => rc_pll_locked,
rc_rx_pll_locked_one => rc_rx_pll_locked_one,
rx_st_mask0 => rx_st_mask0,
rx_st_ready0 => rx_st_ready0,
srst => srst,
swdn_in => signal_wire8,
swup_in => signal_wire9,
test_in => test_in,
tl_slotclk_cfg => signal_wire10,
tlbp_dl_aspm_cr0 => signal_wire11,
tlbp_dl_comclk_reg => signal_wire12,
tlbp_dl_ctrl_link2 => signal_wire13,
tlbp_dl_data_upfc => signal_wire14,
tlbp_dl_hdr_upfc => signal_wire15,
tlbp_dl_inh_dllp => signal_wire16,
tlbp_dl_maxpload_dcr => signal_wire17,
tlbp_dl_req_phycfg => signal_wire18,
tlbp_dl_req_phypm => signal_wire19,
tlbp_dl_req_upfc => signal_wire20,
tlbp_dl_req_wake => signal_wire21,
tlbp_dl_rx_ecrcchk => signal_wire22,
tlbp_dl_snd_upfc => signal_wire23,
tlbp_dl_tx_reqpm => signal_wire24,
tlbp_dl_tx_typpm => signal_wire25,
tlbp_dl_txcfg_extsy => signal_wire26,
tlbp_dl_typ_upfc => signal_wire27,
tlbp_dl_vc_ctrl => signal_wire28,
tlbp_dl_vcid_map => signal_wire29,
tlbp_dl_vcid_upfc => signal_wire30,
tx_st_data0 => tx_st_data0,
tx_st_data0_p1 => tx_st_data0_p1,
tx_st_eop0 => tx_st_eop0,
tx_st_eop0_p1 => tx_st_eop0_p1,
tx_st_err0 => tx_st_err0,
tx_st_sop0 => tx_st_sop0,
tx_st_sop0_p1 => tx_st_sop0_p1,
tx_st_valid0 => tx_st_valid0,
rx_st_mask1 => signal_wire31,
rx_st_ready1 => signal_wire32,
tx_st_data1 => signal_wire33,
tx_st_data1_p1 => signal_wire34,
tx_st_eop1 => signal_wire35,
tx_st_eop1_p1 => signal_wire36,
tx_st_err1 => signal_wire37,
tx_st_sop1 => signal_wire38,
tx_st_sop1_p1 => signal_wire39,
tx_st_valid1 => signal_wire40,
phystatus0_ext => phystatus0_ext,
rxdata0_ext => rxdata0_ext,
rxdatak0_ext => rxdatak0_ext,
rxelecidle0_ext => rxelecidle0_ext,
rxstatus0_ext => rxstatus0_ext,
rxvalid0_ext => rxvalid0_ext,
phystatus1_ext => signal_wire41,
rxdata1_ext => signal_wire42,
rxdatak1_ext => signal_wire43,
rxelecidle1_ext => signal_wire44,
rxstatus1_ext => signal_wire45,
rxvalid1_ext => signal_wire46,
phystatus2_ext => signal_wire47,
rxdata2_ext => signal_wire48,
rxdatak2_ext => signal_wire49,
rxelecidle2_ext => signal_wire50,
rxstatus2_ext => signal_wire51,
rxvalid2_ext => signal_wire52,
phystatus3_ext => signal_wire53,
rxdata3_ext => signal_wire54,
rxdatak3_ext => signal_wire55,
rxelecidle3_ext => signal_wire56,
rxstatus3_ext => signal_wire57,
rxvalid3_ext => signal_wire58,
phystatus4_ext => signal_wire59,
rxdata4_ext => signal_wire60,
rxdatak4_ext => signal_wire61,
rxelecidle4_ext => signal_wire62,
rxstatus4_ext => signal_wire63,
rxvalid4_ext => signal_wire64,
phystatus5_ext => signal_wire65,
rxdata5_ext => signal_wire66,
rxdatak5_ext => signal_wire67,
rxelecidle5_ext => signal_wire68,
rxstatus5_ext => signal_wire69,
rxvalid5_ext => signal_wire70,
phystatus6_ext => signal_wire71,
rxdata6_ext => signal_wire72,
rxdatak6_ext => signal_wire73,
rxelecidle6_ext => signal_wire74,
rxstatus6_ext => signal_wire75,
rxvalid6_ext => signal_wire76,
phystatus7_ext => signal_wire77,
rxdata7_ext => signal_wire78,
rxdatak7_ext => signal_wire79,
rxelecidle7_ext => signal_wire80,
rxstatus7_ext => signal_wire81,
rxvalid7_ext => signal_wire82,
CraIrq_o => CraIrq_o,
CraReadData_o => CraReadData_o,
CraWaitRequest_o => CraWaitRequest_o,
RxmAddress_o => RxmAddress_o,
RxmBurstCount_o => RxmBurstCount_o,
RxmByteEnable_o => RxmByteEnable_o,
RxmRead_o => RxmRead_o,
RxmWriteData_o => RxmWriteData_o,
RxmWrite_o => RxmWrite_o,
TxsReadDataValid_o => TxsReadDataValid_o,
TxsReadData_o => TxsReadData_o,
TxsWaitRequest_o => TxsWaitRequest_o,
app_int_ack => app_int_ack,
app_msi_ack => app_msi_ack,
avs_pcie_reconfig_readdata => avs_pcie_reconfig_readdata,
avs_pcie_reconfig_readdatavalid => avs_pcie_reconfig_readdatavalid,
avs_pcie_reconfig_waitrequest => avs_pcie_reconfig_waitrequest,
core_clk_out => core_clk_out,
derr_cor_ext_rcv0 => derr_cor_ext_rcv0,
derr_cor_ext_rpl => derr_cor_ext_rpl,
derr_rpl => derr_rpl,
dl_ltssm => dl_ltssm,
dlup_exit => dlup_exit,
eidle_infer_sel => eidle_infer_sel,
ev_128ns => ev_128ns,
ev_1us => ev_1us,
hip_extraclkout => hip_extraclkout,
hotrst_exit => hotrst_exit,
int_status => int_status,
l2_exit => l2_exit,
lane_act => lane_act,
lmi_ack => lmi_ack,
lmi_dout => lmi_dout,
npd_alloc_1cred_vc0 => npd_alloc_1cred_vc0,
npd_cred_vio_vc0 => npd_cred_vio_vc0,
nph_alloc_1cred_vc0 => nph_alloc_1cred_vc0,
nph_cred_vio_vc0 => nph_cred_vio_vc0,
pme_to_sr => pme_to_sr,
r2c_err0 => r2c_err0,
rate_ext => rate_ext,
rc_gxb_powerdown => rc_gxb_powerdown,
rc_rx_analogreset => rc_rx_analogreset,
rc_rx_digitalreset => rc_rx_digitalreset,
rc_tx_digitalreset => rc_tx_digitalreset,
reset_status => reset_status,
rx_fifo_empty0 => rx_fifo_empty0,
rx_fifo_full0 => rx_fifo_full0,
rx_st_bardec0 => rx_st_bardec0,
rx_st_be0 => rx_st_be0,
rx_st_be0_p1 => rx_st_be0_p1,
rx_st_data0 => rx_st_data0,
rx_st_data0_p1 => rx_st_data0_p1,
rx_st_eop0 => rx_st_eop0,
rx_st_eop0_p1 => rx_st_eop0_p1,
rx_st_err0 => rx_st_err0,
rx_st_sop0 => rx_st_sop0,
rx_st_sop0_p1 => rx_st_sop0_p1,
rx_st_valid0 => rx_st_valid0,
serr_out => serr_out,
suc_spd_neg => suc_spd_neg,
swdn_wake => swdn_wake,
swup_hotrst => swup_hotrst,
test_out => test_out,
tl_cfg_add => tl_cfg_add,
tl_cfg_ctl => tl_cfg_ctl,
tl_cfg_ctl_wr => tl_cfg_ctl_wr,
tl_cfg_sts => tl_cfg_sts,
tl_cfg_sts_wr => tl_cfg_sts_wr,
tlbp_dl_ack_phypm => open,
tlbp_dl_ack_requpfc => open,
tlbp_dl_ack_sndupfc => open,
tlbp_dl_current_deemp => open,
tlbp_dl_currentspeed => open,
tlbp_dl_dll_req => open,
tlbp_dl_err_dll => open,
tlbp_dl_errphy => open,
tlbp_dl_link_autobdw_status => open,
tlbp_dl_link_bdwmng_status => open,
tlbp_dl_rpbuf_emp => open,
tlbp_dl_rst_enter_comp_bit => open,
tlbp_dl_rst_tx_margin_field => open,
tlbp_dl_rx_typ_pm => open,
tlbp_dl_rx_valpm => open,
tlbp_dl_tx_ackpm => open,
tlbp_dl_up => open,
tlbp_dl_vc_status => open,
tlbp_link_up => open,
tx_cred0 => tx_cred0,
tx_deemph => tx_deemph,
tx_fifo_empty0 => tx_fifo_empty0,
tx_fifo_full0 => tx_fifo_full0,
tx_fifo_rdptr0 => tx_fifo_rdptr0,
tx_fifo_wrptr0 => tx_fifo_wrptr0,
tx_margin => tx_margin,
tx_st_ready0 => tx_st_ready0,
use_pcie_reconfig => use_pcie_reconfig,
wake_oen => wake_oen,
derr_cor_ext_rcv1 => open,
npd_alloc_1cred_vc1 => open,
npd_cred_vio_vc1 => open,
nph_alloc_1cred_vc1 => open,
nph_cred_vio_vc1 => open,
r2c_err1 => open,
rx_fifo_empty1 => open,
rx_fifo_full1 => open,
rx_st_bardec1 => open,
rx_st_be1 => open,
rx_st_be1_p1 => open,
rx_st_data1 => open,
rx_st_data1_p1 => open,
rx_st_eop1 => open,
rx_st_eop1_p1 => open,
rx_st_err1 => open,
rx_st_sop1 => open,
rx_st_sop1_p1 => open,
rx_st_valid1 => open,
tx_cred1 => open,
tx_fifo_empty1 => open,
tx_fifo_full1 => open,
tx_fifo_rdptr1 => open,
tx_fifo_wrptr1 => open,
tx_st_ready1 => open,
powerdown0_ext => powerdown0_ext,
rxpolarity0_ext => rxpolarity0_ext,
txcompl0_ext => txcompl0_ext,
txdata0_ext => txdata0_ext,
txdatak0_ext => txdatak0_ext,
txdetectrx0_ext => txdetectrx0_ext,
txelecidle0_ext => txelecidle0_ext,
powerdown1_ext => open,
rxpolarity1_ext => open,
txcompl1_ext => open,
txdata1_ext => open,
txdatak1_ext => open,
txdetectrx1_ext => open,
txelecidle1_ext => open,
powerdown2_ext => open,
rxpolarity2_ext => open,
txcompl2_ext => open,
txdata2_ext => open,
txdatak2_ext => open,
txdetectrx2_ext => open,
txelecidle2_ext => open,
powerdown3_ext => open,
rxpolarity3_ext => open,
txcompl3_ext => open,
txdata3_ext => open,
txdatak3_ext => open,
txdetectrx3_ext => open,
txelecidle3_ext => open,
powerdown4_ext => open,
rxpolarity4_ext => open,
txcompl4_ext => open,
txdata4_ext => open,
txdatak4_ext => open,
txdetectrx4_ext => open,
txelecidle4_ext => open,
powerdown5_ext => open,
rxpolarity5_ext => open,
txcompl5_ext => open,
txdata5_ext => open,
txdatak5_ext => open,
txdetectrx5_ext => open,
txelecidle5_ext => open,
powerdown6_ext => open,
rxpolarity6_ext => open,
txcompl6_ext => open,
txdata6_ext => open,
txdatak6_ext => open,
txdetectrx6_ext => open,
txelecidle6_ext => open,
powerdown7_ext => open,
rxpolarity7_ext => open,
txcompl7_ext => open,
txdata7_ext => open,
txdatak7_ext => open,
txdetectrx7_ext => open,
txelecidle7_ext => open
);
END SYN;
|
-- 16 Bit Adder --
--
-- A Full 16 bit adder
-- Requires: bitadder_1.VHDL
--
-- Author: Colton Schmidt
-- Last Edited: 18/10/2015
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
-- library UNISIM;
-- use UNISIM.VComponents.all;
entity bitadder_16 is
Port ( x : in std_logic_vector(15 downto 0);
y : in std_logic_vector(15 downto 0);
s0 : out std_logic_vector(15 downto 0));
end bitadder_16;
architecture Behavioral of bitadder_16 is
-- Internal Signals --
signal c : std_logic_vector (15 downto 0):= "0000000000000000";
component bitadder_1
port( a,b,cin:in std_logic;
s,cout:out std_logic);
end component;
begin
bit1: bitadder_1 port map (a=>x(0), b=>y(0), s=>s0(0), cin=>c(0), cout=>c(1));
bit2: bitadder_1 port map (a=>x(1), b=>y(1), s=>s0(1), cin=>c(1), cout=>c(2));
bit3: bitadder_1 port map (a=>x(2), b=>y(2), s=>s0(2), cin=>c(2), cout=>c(3));
bit4: bitadder_1 port map (a=>x(3), b=>y(3), s=>s0(3), cin=>c(3), cout=>c(4));
bit5: bitadder_1 port map (a=>x(4), b=>y(4), s=>s0(4), cin=>c(4), cout=>c(5));
bit6: bitadder_1 port map (a=>x(5), b=>y(5), s=>s0(5), cin=>c(5), cout=>c(6));
bit7: bitadder_1 port map (a=>x(6), b=>y(6), s=>s0(6), cin=>c(6), cout=>c(7));
bit8: bitadder_1 port map (a=>x(7), b=>y(7), s=>s0(7), cin=>c(7), cout=>c(8));
bit9: bitadder_1 port map (a=>x(8), b=>y(8), s=>s0(8), cin=>c(8), cout=>c(9));
bit10: bitadder_1 port map (a=>x(9), b=>y(9), s=>s0(9), cin=>c(9), cout=>c(10));
bit11: bitadder_1 port map (a=>x(10), b=>y(10), s=>s0(10), cin=>c(10), cout=>c(11));
bit12: bitadder_1 port map (a=>x(11), b=>y(11), s=>s0(11), cin=>c(11), cout=>c(12));
bit13: bitadder_1 port map (a=>x(12), b=>y(12), s=>s0(12), cin=>c(12), cout=>c(13));
bit14: bitadder_1 port map (a=>x(13), b=>y(13), s=>s0(13), cin=>c(13), cout=>c(14));
bit15: bitadder_1 port map (a=>x(14), b=>y(14), s=>s0(14), cin=>c(14), cout=>c(15));
bit16: bitadder_1 port map (a=>x(15), b=>y(15), s=>s0(15), cin=>c(15), cout=>c(0));
end Behavioral; |
library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_pulse_generator is
port(
clk : in vl_logic;
ena : in vl_logic;
pulse : out vl_logic;
cycle : out vl_logic
);
end common_28nm_mlab_cell_pulse_generator;
|
library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_pulse_generator is
port(
clk : in vl_logic;
ena : in vl_logic;
pulse : out vl_logic;
cycle : out vl_logic
);
end common_28nm_mlab_cell_pulse_generator;
|
library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_pulse_generator is
port(
clk : in vl_logic;
ena : in vl_logic;
pulse : out vl_logic;
cycle : out vl_logic
);
end common_28nm_mlab_cell_pulse_generator;
|
library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_pulse_generator is
port(
clk : in vl_logic;
ena : in vl_logic;
pulse : out vl_logic;
cycle : out vl_logic
);
end common_28nm_mlab_cell_pulse_generator;
|
library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_pulse_generator is
port(
clk : in vl_logic;
ena : in vl_logic;
pulse : out vl_logic;
cycle : out vl_logic
);
end common_28nm_mlab_cell_pulse_generator;
|
component add
generic (
WIDTH : integer := 3;
HEIGHT : integer := 2
);
port (
clk : in std_logic;
in : in std_logic_vector(WIDTH-1 downto 0);
output : out std_logic_vector(WIDTH-1 downto 0)
);
end component add;
|
-------------------------------------------------------------------------------
-- Title : Generic clock divider
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description:
-- Generates a clock enable signal.
--
-- MUL must be smaller than DIV.
--
-- Example:
-- @code
-- process (clk)
-- begin
-- if rising_edge(clk) then
-- if enable = '1' then
-- ... do something with the period of the divided frequency ...
-- end if;
-- end if;
-- end process;
-- @endcode
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fractional_clock_divider is
generic (
DIV : positive;
MUL : positive := 1
);
port (
clk_out_p : out std_logic;
clk : in std_logic
);
end fractional_clock_divider;
-- ----------------------------------------------------------------------------
architecture behavior of fractional_clock_divider is
begin
process
variable cnt : integer range 0 to (MUL + DIV - 1) := 0;
begin
wait until rising_edge(clk);
cnt := cnt + MUL;
if cnt >= DIV then
cnt := cnt - DIV;
clk_out_p <= '1';
else
clk_out_p <= '0';
end if;
end process;
end behavior;
|
------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) <2013> <Shimafuji Electric Inc., Osaka University, JAXA>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity SpaceWireCODECIPReceiverSynchronize is
generic (
gDisconnectCountValue : integer := 141
);
port (
spaceWireStrobeIn : in std_logic;
spaceWireDataIn : in std_logic;
receiveDataOut : out std_logic_vector (8 downto 0);
receiveDataValidOut : out std_logic;
receiveTimeCodeOut : out std_logic_vector (7 downto 0);
receiveTimeCodeValidOut : out std_logic;
receiveNCharacterOut : out std_logic;
receiveFCTOut : out std_logic;
receiveNullOut : out std_logic;
receiveEEPOut : out std_logic;
receiveEOPOut : out std_logic;
receiveOffOut : out std_logic;
receiverErrorOut : out std_logic;
parityErrorOut : out std_logic;
escapeErrorOut : out std_logic;
disconnectErrorOut : out std_logic;
spaceWireReset : in std_logic;
receiveFIFOWriteEnable : out std_logic;
enableReceive : in std_logic;
receiveClock : in std_logic
);
end SpaceWireCODECIPReceiverSynchronize;
architecture RTL of SpaceWireCODECIPReceiverSynchronize is
signal iDataRegister : std_logic_vector(7 downto 0);
signal iParity : std_logic;
signal iESCFlag : std_logic;
signal iSpaceWireSynchronize : std_logic_vector(1 downto 0);
signal iBitCount : std_logic_vector(3 downto 0);
signal iLinkTimeOutCounter : std_logic_vector (7 downto 0);
signal iDisconnectErrorOut : std_logic;
signal iParityErrorOut : std_logic;
signal iEscapeErrorOut : std_logic;
signal iCommandFlag, iDataFlag : std_logic;
type spaceWireStateMachine is (
spaceWireIdel,
spaceWireOff,
spaceWireEven0,
spaceWireEven1,
spaceWireWaitEven,
spaceWireOdd0,
spaceWireOdd1,
spaceWireWaitOdd
);
signal spaceWireState : spaceWireStateMachine;
signal iReceiverEOPOut : std_logic;
signal iReceiverEEPOut : std_logic;
signal iReceiverDataValidOut : std_logic;
signal iReceiveDataOut : std_logic_vector (8 downto 0) := (others => '0');
signal iReceiveTimeCodeOut : std_logic_vector (7 downto 0);
signal iReceiveTimeCodeValidOut : std_logic;
signal iReceiveNCharacterOut : std_logic;
signal iReceiveFCTOut : std_logic;
signal iReceiveNullOut : std_logic;
signal iReceiveOffOut : std_logic;
signal iReceiverErrorOut : std_logic;
signal iReceiveFIFOWriteEnable : std_logic;
begin
receiveDataOut <= iReceiveDataOut;
receiveTimeCodeOut <= iReceiveTimeCodeOut;
receiveTimeCodeValidOut <= iReceiveTimeCodeValidOut;
receiveNCharacterOut <= iReceiveNCharacterOut;
receiveFCTOut <= iReceiveFCTOut;
receiveNullOut <= iReceiveNullOut;
receiveOffOut <= iReceiveOffOut;
receiverErrorOut <= iReceiverErrorOut;
receiveFIFOWriteEnable <= iReceiveFIFOWriteEnable;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.4.4 Receiver.
----------------------------------------------------------------------
----------------------------------------------------------------------
-- synchronize DS signal to the receiveClock.
----------------------------------------------------------------------
process (receiveClock)
begin
if (receiveClock'event and receiveClock = '1') then
iSpaceWireSynchronize <= spaceWireStrobeIn & spaceWireDataIn;
end if;
end process;
----------------------------------------------------------------------
-- Detect a change of the DS signal.
----------------------------------------------------------------------
process (receiveClock, spaceWireReset, iDisconnectErrorOut)
begin
if (spaceWireReset = '1' or iDisconnectErrorOut = '1') then
spaceWireState <= spaceWireIdel;
elsif (receiveClock'event and receiveClock = '1') then
if(enableReceive = '1')then
if (spaceWireState = spaceWireIdel) then
if (iSpaceWireSynchronize = "00") then
spaceWireState <= spaceWireOff;
end if;
elsif (spaceWireState = spaceWireOff) then
if (iSpaceWireSynchronize = "10") then
spaceWireState <= spaceWireOdd0;
end if;
elsif (spaceWireState = spaceWireEven1 or spaceWireState = spaceWireEven0 or spaceWireState = spaceWireWaitOdd) then
if (iSpaceWireSynchronize = "10") then
spaceWireState <= spaceWireOdd0;
elsif (iSpaceWireSynchronize = "01") then
spaceWireState <= spaceWireOdd1;
else
spaceWireState <= spaceWireWaitOdd;
end if;
elsif (spaceWireState = spaceWireOdd1 or spaceWireState = spaceWireOdd0 or spaceWireState = spaceWireWaitEven) then
if (iSpaceWireSynchronize = "00") then
spaceWireState <= spaceWireEven0;
elsif (iSpaceWireSynchronize = "11") then
spaceWireState <= spaceWireEven1;
else
spaceWireState <= spaceWireWaitEven;
end if;
else
spaceWireState <= spaceWireIdel;
end if;
end if;
end if;
end process;
process (receiveClock)
begin
if (receiveClock'event and receiveClock = '1') then
----------------------------------------------------------------------
-- Take the data into the shift register on the State transition of spaceWireState.
----------------------------------------------------------------------
if(enableReceive = '1')then
if (spaceWireState = spaceWireOff) then
iDataRegister <= (others => '0');
elsif (spaceWireState = spaceWireOdd1 or spaceWireState = spaceWireEven1) then
iDataRegister <= '1' & iDataRegister(7 downto 1);
elsif (spaceWireState = spaceWireOdd0 or spaceWireState = spaceWireEven0) then
iDataRegister <= '0' & iDataRegister(7 downto 1);
end if;
else
iDataRegister <= (others => '0');
end if;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 7.4 Parity for error detection.
-- Odd Parity.
----------------------------------------------------------------------
if(enableReceive = '1' and iEscapeErrorOut = '0' and iDisconnectErrorOut = '0')then
if (spaceWireState = spaceWireOff) then
iParity <= '0';
elsif (iBitCount = 0 and spaceWireState = spaceWireEven1) then
if (iParity = '1') then
iParityErrorOut <= '1';
iParity <= '0';
end if;
elsif (iBitCount = 0 and spaceWireState = spaceWireEven0) then
if iParity = '0' then
iParityErrorOut <= '1';
else
iParity <= '0';
end if;
elsif (spaceWireState = spaceWireOdd1 or spaceWireState = spaceWireEven1) then
iParity <= not iParity;
end if;
else
iParityErrorOut <= '0';
end if;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.5.3.7.2 Disconnect error.
-- Disconnect error is an error condition asserted
-- when the length of time since the last transition on
-- the D or S lines was longer than 850 ns nominal.
----------------------------------------------------------------------
if(enableReceive = '1' and iEscapeErrorOut = '0' and iParityErrorOut = '0')then
if (spaceWireState = spaceWireWaitOdd or spaceWireState = spaceWireWaitEven) then
if (iLinkTimeOutCounter < gDisconnectCountValue) then
iLinkTimeOutCounter <= iLinkTimeOutCounter + 1;
else
iDisconnectErrorOut <= '1';
end if;
elsif (spaceWireState = spaceWireIdel) then
iLinkTimeOutCounter <= X"00";
elsif (spaceWireState = spaceWireOdd1 or spaceWireState = spaceWireEven1 or spaceWireState = spaceWireOdd0 or spaceWireState = spaceWireEven0) then
iLinkTimeOutCounter <= X"00";
end if;
else
iDisconnectErrorOut <= '0';
iLinkTimeOutCounter <= X"00";
end if;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 4.4 Character level
-- ECSS-E-ST-50-12C 7.2 Data characters
-- Discriminate the data character or the the control character by the Data
-- Control Flag.
----------------------------------------------------------------------
if(enableReceive = '1')then
if (spaceWireState = spaceWireIdel) then
iCommandFlag <= '0'; iDataFlag <= '0';
elsif (iBitCount = 0 and spaceWireState = spaceWireEven0) then
iCommandFlag <= '0'; iDataFlag <= '1';
elsif (iBitCount = 0 and spaceWireState = spaceWireEven1) then
iCommandFlag <= '1'; iDataFlag <= '0';
end if;
else
iCommandFlag <= '0'; iDataFlag <= '0';
end if;
----------------------------------------------------------------------
-- Increment bit of character corresponding by state transition of
-- spaceWireState.
----------------------------------------------------------------------
if(enableReceive = '1' and iEscapeErrorOut = '0' and iDisconnectErrorOut = '0')then
if (spaceWireState = spaceWireIdel or spaceWireState = spaceWireOff) then
iBitCount <= X"0";
elsif (spaceWireState = spaceWireEven1 or spaceWireState = spaceWireEven0) then
if (iBitCount = 1 and iCommandFlag = '1') then
iBitCount <= X"0";
elsif (iBitCount = 4 and iCommandFlag = '0') then
iBitCount <= X"0";
else
iBitCount <= iBitCount + 1;
end if;
end if;
else
iBitCount <= X"0";
end if;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 7.3 Control characters and control codes.
-- Discriminate Data character, Control code and Time corde, and write to
-- Receive buffer
----------------------------------------------------------------------
if(enableReceive = '1')then
if (iBitCount = 0 and (spaceWireState = spaceWireOdd0 or spaceWireState = spaceWireOdd1)) then
if (iDataFlag = '1') then
if (iESCFlag = '1') then
--Time Code Receive.
iReceiveTimeCodeOut <= iDataRegister;
else
--Data Receive.
iReceiveDataOut <= '0' & iDataRegister;
iReceiveFIFOWriteEnable <= '1';
end if;
elsif (iCommandFlag = '1') then
if (iDataRegister (7 downto 6) = "10") then --EOP
iReceiveDataOut <= '1' & "00000000";
elsif (iDataRegister (7 downto 6) = "01") then --EEP
iReceiveDataOut <= '1' & "00000001";
end if;
if ((iESCFlag /= '1') and (iDataRegister (7 downto 6) = "10" or iDataRegister (7 downto 6) = "01")) then
--EOP EEP Receive.
iReceiveFIFOWriteEnable <= '1';
end if;
end if;
else
iReceiveFIFOWriteEnable <= '0';
end if;
end if;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 7.3 Control characters and control codes.
-- ECSS-E-ST-50-12C 8.5.3.7.4 Escape error.
-- Receive DataCharacter, ControlCode and TimeCode.
----------------------------------------------------------------------
if(enableReceive = '1' and iDisconnectErrorOut = '0' and iParityErrorOut = '0')then
if (iBitCount = 0 and (spaceWireState = spaceWireOdd0 or spaceWireState = spaceWireOdd1)) then
if (iCommandFlag = '1') then
case iDataRegister(7 downto 6) is
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.5.3.2 gotNULL.
-- ECSS-E-ST-50-12C 8.5.3.3 gotFCT.
----------------------------------------------------------------------
when "00" => -- FCT Receive or Null Receive.
if (iESCFlag = '1') then
iReceiveNullOut <= '1';
iESCFlag <= '0';
else
iReceiveFCTOut <= '1';
end if;
when "11" => -- ESC Receive.
if (iESCFlag = '1') then
iEscapeErrorOut <= '1';
else
iESCFlag <= '1';
end if;
when "10" => -- EOP Receive.
if (iESCFlag = '1') then
iEscapeErrorOut <= '1';
else
iReceiverEOPOut <= '1';
end if;
when "01" => -- EEP Receive.
if (iESCFlag = '1') then
iEscapeErrorOut <= '1';
else
iReceiverEEPOut <= '1';
end if;
when others => null;
end case;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.5.3.5 gotTime-Code.
-- ECSS-E-ST-50-12C 8.5.3.4 gotN-Char.
----------------------------------------------------------------------
elsif (iDataFlag = '1') then
if (iESCFlag = '1') then --TimeCode_Receive.
iReceiveTimeCodeValidOut <= '1';
iESCFlag <= '0';
else --N-Char_Receive.
iReceiverDataValidOut <= '1';
end if;
end if;
----------------------------------------------------------------------
-- Clear the previous Receive flag before receiving data.
----------------------------------------------------------------------
elsif (iBitCount = 1 and (spaceWireState = spaceWireOdd0 or spaceWireState = spaceWireOdd1)) then
iReceiverDataValidOut <= '0';
iReceiveTimeCodeValidOut <= '0';
iReceiveNullOut <= '0';
iReceiveFCTOut <= '0';
iReceiverEOPOut <= '0';
iReceiverEEPOut <= '0';
elsif spaceWireState = spaceWireIdel then
iReceiverDataValidOut <= '0';
iReceiveTimeCodeValidOut <= '0';
iReceiveNullOut <= '0';
iReceiveFCTOut <= '0';
iReceiverEOPOut <= '0';
iReceiverEEPOut <= '0';
iEscapeErrorOut <= '0';
iESCFlag <= '0';
end if;
else
iReceiverDataValidOut <= '0';
iReceiveTimeCodeValidOut <= '0';
iReceiveNullOut <= '0';
iReceiveFCTOut <= '0';
iReceiverEOPOut <= '0';
iReceiverEEPOut <= '0';
iEscapeErrorOut <= '0';
iESCFlag <= '0';
end if;
end if;
end process;
iReceiveOffOut <= '1' when spaceWireState = spaceWireOff else '0';
iReceiverErrorOut <= '1' when iDisconnectErrorOut = '1' or iParityErrorOut = '1' or iEscapeErrorOut = '1' else '0';
iReceiveNCharacterOut <= '1' when iReceiverEOPOut = '1' or iReceiverEEPOut = '1' or iReceiverDataValidOut = '1' else '0';
receiveDataValidOut <= iReceiverDataValidOut;
receiveEOPOut <= iReceiverEOPOut;
receiveEEPOut <= iReceiverEEPOut;
parityErrorOut <= iParityErrorOut;
escapeErrorOut <= iEscapeErrorOut;
disconnectErrorOut <= iDisconnectErrorOut;
end RTL;
|
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/21 23:26:37 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: aurora_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.3 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- aurora_16b
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: Brian Woodard
-- Xilinx - Garden Valley Design Team
--
-- Description: This is the top level module for a 1 2-byte lane Aurora
-- reference design module. This module supports the following features:
--
-- * Immediate Mode Native Flow Control
-- * Supports Virtex 2 Pro
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synthesis translate_off
library UNISIM;
use UNISIM.all;
-- synthesis translate_on
entity aurora_16b is
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- LocalLink TX Interface
TX_D : in std_logic_vector(0 to 15);
TX_REM : in std_logic;
TX_SRC_RDY_N : in std_logic;
TX_SOF_N : in std_logic;
TX_EOF_N : in std_logic;
TX_DST_RDY_N : out std_logic;
-- LocalLink RX Interface
RX_D : out std_logic_vector(0 to 15);
RX_REM : out std_logic;
RX_SRC_RDY_N : out std_logic;
RX_SOF_N : out std_logic;
RX_EOF_N : out std_logic;
-- Native Flow Control Interface
NFC_REQ_N : in std_logic;
NFC_NB : in std_logic_vector(0 to 3);
NFC_ACK_N : out std_logic;
-- MGT Serial I/O
RXP : in std_logic;
RXN : in std_logic;
TXP : out std_logic;
TXN : out std_logic;
-- MGT Reference Clock Interface
TOP_BREF_CLK : in std_logic;
-- Error Detection Interface
HARD_ERROR : out std_logic;
SOFT_ERROR : out std_logic;
FRAME_ERROR : out std_logic;
-- Status
CHANNEL_UP : out std_logic;
LANE_UP : out std_logic;
-- Clock Compensation Control Interface
WARN_CC : in std_logic;
DO_CC : in std_logic;
-- System Interface
DCM_NOT_LOCKED : in std_logic;
USER_CLK : in std_logic;
RESET : in std_logic;
POWER_DOWN : in std_logic;
LOOPBACK : in std_logic_vector(1 downto 0)
);
end aurora_16b;
architecture MAPPED of aurora_16b is
-- External Register Declarations --
signal TX_DST_RDY_N_Buffer : std_logic;
signal RX_D_Buffer : std_logic_vector(0 to 15);
signal RX_REM_Buffer : std_logic;
signal RX_SRC_RDY_N_Buffer : std_logic;
signal RX_SOF_N_Buffer : std_logic;
signal RX_EOF_N_Buffer : std_logic;
signal NFC_ACK_N_Buffer : std_logic;
signal TXP_Buffer : std_logic;
signal TXN_Buffer : std_logic;
signal HARD_ERROR_Buffer : std_logic;
signal SOFT_ERROR_Buffer : std_logic;
signal FRAME_ERROR_Buffer : std_logic;
signal CHANNEL_UP_Buffer : std_logic;
signal LANE_UP_Buffer : std_logic;
-- Wire Declarations --
signal rx_data_i : std_logic_vector(15 downto 0);
signal rx_not_in_table_i : std_logic_vector(1 downto 0);
signal rx_disp_err_i : std_logic_vector(1 downto 0);
signal rx_char_is_k_i : std_logic_vector(1 downto 0);
signal rx_char_is_comma_i : std_logic_vector(1 downto 0);
signal rx_buf_status_i : std_logic;
signal tx_buf_err_i : std_logic;
signal tx_k_err_i : std_logic_vector(1 downto 0);
signal rx_clk_cor_cnt_i : std_logic_vector(2 downto 0);
signal rx_realign_i : std_logic;
signal rx_polarity_i : std_logic;
signal rx_reset_i : std_logic;
signal tx_char_is_k_i : std_logic_vector(1 downto 0);
signal tx_data_i : std_logic_vector(15 downto 0);
signal tx_reset_i : std_logic;
signal ena_comma_align_i : std_logic;
signal gen_scp_i : std_logic;
signal gen_snf_i : std_logic;
signal fc_nb_i : std_logic_vector(0 to 3);
signal gen_ecp_i : std_logic;
signal gen_pad_i : std_logic;
signal tx_pe_data_i : std_logic_vector(0 to 15);
signal tx_pe_data_v_i : std_logic;
signal gen_cc_i : std_logic;
signal rx_pad_i : std_logic;
signal rx_pe_data_i : std_logic_vector(0 to 15);
signal rx_pe_data_v_i : std_logic;
signal rx_scp_i : std_logic;
signal rx_ecp_i : std_logic;
signal rx_snf_i : std_logic;
signal rx_fc_nb_i : std_logic_vector(0 to 3);
signal gen_a_i : std_logic;
signal gen_k_i : std_logic_vector(0 to 1);
signal gen_r_i : std_logic_vector(0 to 1);
signal gen_v_i : std_logic_vector(0 to 1);
signal lane_up_i : std_logic;
signal soft_error_i : std_logic;
signal hard_error_i : std_logic;
signal channel_bond_load_i : std_logic;
signal got_a_i : std_logic_vector(0 to 1);
signal got_v_i : std_logic;
signal reset_lanes_i : std_logic;
signal rx_rec_clk_i : std_logic;
signal ena_calign_rec_i : std_logic;
signal txcharisk_lane_0_i : std_logic_vector(3 downto 0);
signal txdata_lane_0_i : std_logic_vector(31 downto 0);
signal refclksel_lane_0_i : std_logic;
signal txbypass8b10b_lane_0_i : std_logic_vector(3 downto 0);
signal txchardispmode_lane_0_i : std_logic_vector(3 downto 0);
signal txchardispval_lane_0_i : std_logic_vector(3 downto 0);
signal configenable_lane_0_i : std_logic;
signal configin_lane_0_i : std_logic;
signal txforcecrcerr_lane_0_i : std_logic;
signal txinhibit_lane_0_i : std_logic;
signal txpolarity_lane_0_i : std_logic;
signal rxdata_lane_0_i : std_logic_vector(31 downto 0);
signal rxnotintable_lane_0_i : std_logic_vector(3 downto 0);
signal rxdisperr_lane_0_i : std_logic_vector(3 downto 0);
signal rxcharisk_lane_0_i : std_logic_vector(3 downto 0);
signal rxchariscomma_lane_0_i : std_logic_vector(3 downto 0);
signal rxbufstatus_lane_0_i : std_logic_vector(1 downto 0);
signal txkerr_lane_0_i : std_logic_vector(3 downto 0);
signal ch_bond_done_i : std_logic;
signal en_chan_sync_i : std_logic;
signal channel_up_i : std_logic;
signal start_rx_i : std_logic;
signal tx_wait_i : std_logic;
signal decrement_nfc_i : std_logic;
signal chbondi_not_used_i : std_logic_vector(3 downto 0);
signal chbondo_not_used_i : std_logic_vector(3 downto 0);
signal tied_to_ground_i : std_logic;
signal tied_to_vcc_i : std_logic;
signal system_reset_c : std_logic;
signal fc_nb_not_used_i : std_logic_vector(0 to 3);
-- Component Declarations --
component FD
generic (INIT : bit := '0');
port (
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic
);
end component;
component AURORA_LANE
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- MGT Interface
RX_DATA : in std_logic_vector(15 downto 0); -- 2-byte data bus from the MGT.
RX_NOT_IN_TABLE : in std_logic_vector(1 downto 0); -- Invalid 10-bit code was recieved.
RX_DISP_ERR : in std_logic_vector(1 downto 0); -- Disparity error detected on RX interface.
RX_CHAR_IS_K : in std_logic_vector(1 downto 0); -- Indicates which bytes of RX_DATA are control.
RX_CHAR_IS_COMMA : in std_logic_vector(1 downto 0); -- Comma received on given byte.
RX_BUF_STATUS : in std_logic; -- Overflow/Underflow of RX buffer detected.
TX_BUF_ERR : in std_logic; -- Overflow/Underflow of TX buffer detected.
TX_K_ERR : in std_logic_vector(1 downto 0); -- Attempt to send bad control byte detected.
RX_CLK_COR_CNT : in std_logic_vector(2 downto 0); -- Value used to determine channel bonding status.
RX_REALIGN : in std_logic; -- SERDES was realigned because of a new comma.
RX_POLARITY : out std_logic; -- Controls interpreted polarity of serial data inputs.
RX_RESET : out std_logic; -- Reset RX side of MGT logic.
TX_CHAR_IS_K : out std_logic_vector(1 downto 0); -- TX_DATA byte is a control character.
TX_DATA : out std_logic_vector(15 downto 0); -- 2-byte data bus to the MGT.
TX_RESET : out std_logic; -- Reset TX side of MGT logic.
-- Comma Detect Phase Align Interface
ENA_COMMA_ALIGN : out std_logic; -- Request comma alignment.
-- TX_LL Interface
GEN_SCP : in std_logic; -- SCP generation request from TX_LL.
GEN_ECP : in std_logic; -- ECP generation request from TX_LL.
GEN_SNF : in std_logic; -- SNF generation request from TX_LL.
GEN_PAD : in std_logic; -- PAD generation request from TX_LL.
FC_NB : in std_logic_vector(0 to 3); -- Size code for SUF and SNF messages.
TX_PE_DATA : in std_logic_vector(0 to 15); -- Data from TX_LL to send over lane.
TX_PE_DATA_V : in std_logic; -- Indicates TX_PE_DATA is Valid.
GEN_CC : in std_logic; -- CC generation request from TX_LL.
-- RX_LL Interface
RX_PAD : out std_logic; -- Indicates lane received PAD.
RX_PE_DATA : out std_logic_vector(0 to 15); -- RX data from lane to RX_LL.
RX_PE_DATA_V : out std_logic; -- RX_PE_DATA is data, not control symbol.
RX_SCP : out std_logic; -- Indicates lane received SCP.
RX_ECP : out std_logic; -- Indicates lane received ECP.
RX_SNF : out std_logic; -- Indicates lane received SNF.
RX_FC_NB : out std_logic_vector(0 to 3); -- Size code for SNF or SUF.
-- Global Logic Interface
GEN_A : in std_logic; -- 'A character' generation request from Global Logic.
GEN_K : in std_logic_vector(0 to 1); -- 'K character' generation request from Global Logic.
GEN_R : in std_logic_vector(0 to 1); -- 'R character' generation request from Global Logic.
GEN_V : in std_logic_vector(0 to 1); -- Verification data generation request.
LANE_UP : out std_logic; -- Lane is ready for bonding and verification.
SOFT_ERROR : out std_logic; -- Soft error detected.
HARD_ERROR : out std_logic; -- Hard error detected.
CHANNEL_BOND_LOAD : out std_logic; -- Channel Bonding done code received.
GOT_A : out std_logic_vector(0 to 1); -- Indicates lane recieved 'A character' bytes.
GOT_V : out std_logic; -- Verification symbols received.
-- System Interface
USER_CLK : in std_logic; -- System clock for all non-MGT Aurora Logic.
RESET : in std_logic -- Reset the lane.
);
end component;
component PHASE_ALIGN
port (
-- Aurora Lane Interface
ENA_COMMA_ALIGN : in std_logic;
-- MGT Interface
RX_REC_CLK : in std_logic;
ENA_CALIGN_REC : out std_logic
);
end component;
component GT_CUSTOM
generic (ALIGN_COMMA_MSB : boolean;
CHAN_BOND_MODE : string;
CHAN_BOND_ONE_SHOT : boolean;
CHAN_BOND_SEQ_1_1 : bit_vector;
REF_CLK_V_SEL : integer;
CLK_COR_INSERT_IDLE_FLAG : boolean;
CLK_COR_KEEP_IDLE : boolean;
CLK_COR_REPEAT_WAIT : integer;
CLK_COR_SEQ_1_1 : bit_vector;
CLK_COR_SEQ_1_2 : bit_vector;
CLK_COR_SEQ_2_USE : boolean;
CLK_COR_SEQ_LEN : integer;
CLK_CORRECT_USE : boolean;
COMMA_10B_MASK : bit_vector;
MCOMMA_10B_VALUE : bit_vector;
PCOMMA_10B_VALUE : bit_vector;
RX_CRC_USE : boolean;
RX_DATA_WIDTH : integer;
RX_LOSS_OF_SYNC_FSM : boolean;
RX_LOS_INVALID_INCR : integer;
RX_LOS_THRESHOLD : integer;
SERDES_10B : boolean;
TERMINATION_IMP : integer;
TX_CRC_USE : boolean;
TX_DATA_WIDTH : integer;
TX_DIFF_CTRL : integer;
TX_PREEMPHASIS : integer);
port (
CHBONDDONE : out std_logic;
CHBONDO : out std_logic_vector(3 downto 0);
CONFIGOUT : out std_logic;
RXBUFSTATUS : out std_logic_vector(1 downto 0);
RXCHARISCOMMA : out std_logic_vector(3 downto 0);
RXCHARISK : out std_logic_vector(3 downto 0);
RXCHECKINGCRC : out std_logic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_logic;
RXCRCERR : out std_logic;
RXDATA : out std_logic_vector(31 downto 0);
RXDISPERR : out std_logic_vector(3 downto 0);
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector(3 downto 0);
RXREALIGN : out std_logic;
RXRECCLK : out std_logic;
RXRUNDISP : out std_logic_vector(3 downto 0);
TXBUFERR : out std_logic;
TXKERR : out std_logic_vector(3 downto 0);
TXN : out std_logic;
TXP : out std_logic;
TXRUNDISP : out std_logic_vector(3 downto 0);
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector(3 downto 0);
CONFIGENABLE : in std_logic;
CONFIGIN : in std_logic;
ENCHANSYNC : in std_logic;
ENMCOMMAALIGN : in std_logic;
ENPCOMMAALIGN : in std_logic;
LOOPBACK : in std_logic_vector(1 downto 0);
POWERDOWN : in std_logic;
REFCLK : in std_logic;
REFCLK2 : in std_logic;
REFCLKSEL : in std_logic;
RXN : in std_logic;
RXP : in std_logic;
RXPOLARITY : in std_logic;
RXRESET : in std_logic;
RXUSRCLK : in std_logic;
RXUSRCLK2 : in std_logic;
TXBYPASS8B10B : in std_logic_vector(3 downto 0);
TXCHARDISPMODE : in std_logic_vector(3 downto 0);
TXCHARDISPVAL : in std_logic_vector(3 downto 0);
TXCHARISK : in std_logic_vector(3 downto 0);
TXDATA : in std_logic_vector(31 downto 0);
TXFORCECRCERR : in std_logic;
TXINHIBIT : in std_logic;
TXPOLARITY : in std_logic;
TXRESET : in std_logic;
TXUSRCLK : in std_logic;
TXUSRCLK2 : in std_logic
);
end component;
-- attribute syn_black_box of GT_CUSTOM : component is true;
component GLOBAL_LOGIC
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- MGT Interface
CH_BOND_DONE : in std_logic;
EN_CHAN_SYNC : out std_logic;
-- Aurora Lane Interface
LANE_UP : in std_logic;
SOFT_ERROR : in std_logic;
HARD_ERROR : in std_logic;
CHANNEL_BOND_LOAD : in std_logic;
GOT_A : in std_logic_vector(0 to 1);
GOT_V : in std_logic;
GEN_A : out std_logic;
GEN_K : out std_logic_vector(0 to 1);
GEN_R : out std_logic_vector(0 to 1);
GEN_V : out std_logic_vector(0 to 1);
RESET_LANES : out std_logic;
-- System Interface
USER_CLK : in std_logic;
RESET : in std_logic;
POWER_DOWN : in std_logic;
CHANNEL_UP : out std_logic;
START_RX : out std_logic;
CHANNEL_SOFT_ERROR : out std_logic;
CHANNEL_HARD_ERROR : out std_logic
);
end component;
component TX_LL
port (
-- LocalLink PDU Interface
TX_D : in std_logic_vector(0 to 15);
TX_REM : in std_logic;
TX_SRC_RDY_N : in std_logic;
TX_SOF_N : in std_logic;
TX_EOF_N : in std_logic;
TX_DST_RDY_N : out std_logic;
-- NFC Interface
NFC_REQ_N : in std_logic;
NFC_NB : in std_logic_vector(0 to 3);
NFC_ACK_N : out std_logic;
-- Clock Compensation Interface
WARN_CC : in std_logic;
DO_CC : in std_logic;
-- Global Logic Interface
CHANNEL_UP : in std_logic;
-- Aurora Lane Interface
GEN_SCP : out std_logic;
GEN_ECP : out std_logic;
GEN_SNF : out std_logic;
FC_NB : out std_logic_vector(0 to 3);
TX_PE_DATA_V : out std_logic;
GEN_PAD : out std_logic;
TX_PE_DATA : out std_logic_vector(0 to 15);
GEN_CC : out std_logic;
-- RX_LL Interface
TX_WAIT : in std_logic;
DECREMENT_NFC : out std_logic;
-- System Interface
USER_CLK : in std_logic
);
end component;
component RX_LL
port (
-- LocalLink PDU Interface
RX_D : out std_logic_vector(0 to 15);
RX_REM : out std_logic;
RX_SRC_RDY_N : out std_logic;
RX_SOF_N : out std_logic;
RX_EOF_N : out std_logic;
-- Global Logic Interface
START_RX : in std_logic;
-- Aurora Lane Interface
RX_PAD : in std_logic;
RX_PE_DATA : in std_logic_vector(0 to 15);
RX_PE_DATA_V : in std_logic;
RX_SCP : in std_logic;
RX_ECP : in std_logic;
RX_SNF : in std_logic;
RX_FC_NB : in std_logic_vector(0 to 3);
-- TX_LL Interface
DECREMENT_NFC : in std_logic;
TX_WAIT : out std_logic;
-- Error Interface
FRAME_ERROR : out std_logic;
-- System Interface
USER_CLK : in std_logic
);
end component;
begin
TX_DST_RDY_N <= TX_DST_RDY_N_Buffer;
RX_D <= RX_D_Buffer;
RX_REM <= RX_REM_Buffer;
RX_SRC_RDY_N <= RX_SRC_RDY_N_Buffer;
RX_SOF_N <= RX_SOF_N_Buffer;
RX_EOF_N <= RX_EOF_N_Buffer;
NFC_ACK_N <= NFC_ACK_N_Buffer;
TXP <= TXP_Buffer;
TXN <= TXN_Buffer;
HARD_ERROR <= HARD_ERROR_Buffer;
SOFT_ERROR <= SOFT_ERROR_Buffer;
FRAME_ERROR <= FRAME_ERROR_Buffer;
CHANNEL_UP <= CHANNEL_UP_Buffer;
LANE_UP <= LANE_UP_Buffer;
-- Main Body of Code --
tied_to_ground_i <= '0';
tied_to_vcc_i <= '1';
chbondi_not_used_i <= "0000";
fc_nb_not_used_i <= "0000";
CHANNEL_UP_Buffer <= channel_up_i;
system_reset_c <= RESET or DCM_NOT_LOCKED;
-- Instantiate Lane 0 --
LANE_UP_Buffer <= lane_up_i;
aurora_lane_0_i : AURORA_LANE
generic map (
EXTEND_WATCHDOGS => EXTEND_WATCHDOGS
)
port map (
-- MGT Interface
RX_DATA => rx_data_i(15 downto 0),
RX_NOT_IN_TABLE => rx_not_in_table_i(1 downto 0),
RX_DISP_ERR => rx_disp_err_i(1 downto 0),
RX_CHAR_IS_K => rx_char_is_k_i(1 downto 0),
RX_CHAR_IS_COMMA => rx_char_is_comma_i(1 downto 0),
RX_BUF_STATUS => rx_buf_status_i,
TX_BUF_ERR => tx_buf_err_i,
TX_K_ERR => tx_k_err_i(1 downto 0),
RX_CLK_COR_CNT => rx_clk_cor_cnt_i(2 downto 0),
RX_REALIGN => rx_realign_i,
RX_POLARITY => rx_polarity_i,
RX_RESET => rx_reset_i,
TX_CHAR_IS_K => tx_char_is_k_i(1 downto 0),
TX_DATA => tx_data_i(15 downto 0),
TX_RESET => tx_reset_i,
-- Comma Detect Phase Align Interface
ENA_COMMA_ALIGN => ena_comma_align_i,
-- TX_LL Interface
GEN_SCP => gen_scp_i,
GEN_SNF => gen_snf_i,
FC_NB => fc_nb_i,
GEN_ECP => gen_ecp_i,
GEN_PAD => gen_pad_i,
TX_PE_DATA => tx_pe_data_i(0 to 15),
TX_PE_DATA_V => tx_pe_data_v_i,
GEN_CC => gen_cc_i,
-- RX_LL Interface
RX_PAD => rx_pad_i,
RX_PE_DATA => rx_pe_data_i(0 to 15),
RX_PE_DATA_V => rx_pe_data_v_i,
RX_SCP => rx_scp_i,
RX_ECP => rx_ecp_i,
RX_SNF => rx_snf_i,
RX_FC_NB => rx_fc_nb_i(0 to 3),
-- Global Logic Interface
GEN_A => gen_a_i,
GEN_K => gen_k_i(0 to 1),
GEN_R => gen_r_i(0 to 1),
GEN_V => gen_v_i(0 to 1),
LANE_UP => lane_up_i,
SOFT_ERROR => soft_error_i,
HARD_ERROR => hard_error_i,
CHANNEL_BOND_LOAD => channel_bond_load_i,
GOT_A => got_a_i(0 to 1),
GOT_V => got_v_i,
-- System Interface
USER_CLK => USER_CLK,
RESET => reset_lanes_i
);
lane_0_phase_align_i : PHASE_ALIGN
port map (
-- Aurora Lane Interface
ENA_COMMA_ALIGN => ena_comma_align_i,
-- MGT Interface
RX_REC_CLK => rx_rec_clk_i,
ENA_CALIGN_REC => ena_calign_rec_i
);
txcharisk_lane_0_i <= "00" & tx_char_is_k_i(1 downto 0);
txdata_lane_0_i <= "0000000000000000" & tx_data_i(15 downto 0);
refclksel_lane_0_i <= '0';
txbypass8b10b_lane_0_i <= "0000";
txchardispmode_lane_0_i <= "0000";
txchardispval_lane_0_i <= "0000";
configenable_lane_0_i <= '0';
configin_lane_0_i <= '0';
txforcecrcerr_lane_0_i <= '0';
txinhibit_lane_0_i <= '0';
txpolarity_lane_0_i <= '0';
rx_data_i(15 downto 0) <= rxdata_lane_0_i(15 downto 0);
rx_not_in_table_i(1 downto 0) <= rxnotintable_lane_0_i(1 downto 0);
rx_disp_err_i(1 downto 0) <= rxdisperr_lane_0_i(1 downto 0);
rx_char_is_k_i(1 downto 0) <= rxcharisk_lane_0_i(1 downto 0);
rx_char_is_comma_i(1 downto 0) <= rxchariscomma_lane_0_i(1 downto 0);
rx_buf_status_i <= rxbufstatus_lane_0_i(1);
tx_k_err_i(1 downto 0) <= txkerr_lane_0_i(1 downto 0);
lane_0_mgt_i : GT_CUSTOM
-- Lane 0 MGT attributes
generic map (
ALIGN_COMMA_MSB => TRUE,
CHAN_BOND_MODE => "OFF",
CHAN_BOND_ONE_SHOT => FALSE,
CHAN_BOND_SEQ_1_1 => "00101111100",
REF_CLK_V_SEL => 1,
CLK_COR_INSERT_IDLE_FLAG => FALSE,
CLK_COR_KEEP_IDLE => FALSE,
CLK_COR_REPEAT_WAIT => 8,
CLK_COR_SEQ_1_1 => "00111110111",
CLK_COR_SEQ_1_2 => "00111110111",
CLK_COR_SEQ_2_USE => FALSE,
CLK_COR_SEQ_LEN => 2,
CLK_CORRECT_USE => TRUE,
COMMA_10B_MASK => "1111111111",
MCOMMA_10B_VALUE => "1100000101",
PCOMMA_10B_VALUE => "0011111010",
RX_CRC_USE => FALSE,
RX_DATA_WIDTH => 2,
RX_LOSS_OF_SYNC_FSM => FALSE,
RX_LOS_INVALID_INCR => 1,
RX_LOS_THRESHOLD => 4,
SERDES_10B => FALSE,
TERMINATION_IMP => 50,
TX_CRC_USE => FALSE,
TX_DATA_WIDTH => 2,
TX_DIFF_CTRL => 600,
TX_PREEMPHASIS => 1
)
port map (
-- Aurora Lane Interface
RXPOLARITY => rx_polarity_i,
RXRESET => rx_reset_i,
TXCHARISK => txcharisk_lane_0_i,
TXDATA => txdata_lane_0_i,
TXRESET => tx_reset_i,
RXDATA => rxdata_lane_0_i,
RXNOTINTABLE => rxnotintable_lane_0_i,
RXDISPERR => rxdisperr_lane_0_i,
RXCHARISK => rxcharisk_lane_0_i,
RXCHARISCOMMA => rxchariscomma_lane_0_i,
RXBUFSTATUS => rxbufstatus_lane_0_i,
TXBUFERR => tx_buf_err_i,
TXKERR => txkerr_lane_0_i,
RXCLKCORCNT => rx_clk_cor_cnt_i(2 downto 0),
RXREALIGN => rx_realign_i,
-- Phase Align Interface
ENMCOMMAALIGN => ena_calign_rec_i,
ENPCOMMAALIGN => ena_calign_rec_i,
RXRECCLK => rx_rec_clk_i,
-- Global Logic Interface
ENCHANSYNC => tied_to_ground_i,
CHBONDDONE => ch_bond_done_i,
-- Peer Channel Bonding Interface
CHBONDI => chbondi_not_used_i,
CHBONDO => chbondo_not_used_i(3 downto 0),
-- Unused MGT Ports
CONFIGOUT => open,
RXCHECKINGCRC => open,
RXCOMMADET => open,
RXCRCERR => open,
RXLOSSOFSYNC => open,
RXRUNDISP => open,
TXRUNDISP => open,
-- Fixed MGT settings for Aurora
TXBYPASS8B10B => txbypass8b10b_lane_0_i,
TXCHARDISPMODE => txchardispmode_lane_0_i,
TXCHARDISPVAL => txchardispval_lane_0_i,
CONFIGENABLE => configenable_lane_0_i,
CONFIGIN => configin_lane_0_i,
TXFORCECRCERR => txforcecrcerr_lane_0_i,
TXINHIBIT => txinhibit_lane_0_i,
TXPOLARITY => txpolarity_lane_0_i,
-- Serial IO
RXN => RXN,
RXP => RXP,
TXN => TXN_Buffer,
TXP => TXP_Buffer,
-- Reference Clocks and User Clock
RXUSRCLK => USER_CLK,
RXUSRCLK2 => USER_CLK,
TXUSRCLK => USER_CLK,
TXUSRCLK2 => USER_CLK,
BREFCLK => TOP_BREF_CLK,
BREFCLK2 => tied_to_ground_i,
REFCLK => tied_to_ground_i,
REFCLK2 => tied_to_ground_i,
REFCLKSEL => refclksel_lane_0_i,
-- System Interface
LOOPBACK => LOOPBACK,
POWERDOWN => POWER_DOWN
);
-- Instantiate Global Logic to combine Lanes into a Channel --
global_logic_i : GLOBAL_LOGIC
generic map (
EXTEND_WATCHDOGS => EXTEND_WATCHDOGS
)
port map (
-- MGT Interface
CH_BOND_DONE => ch_bond_done_i,
EN_CHAN_SYNC => en_chan_sync_i,
-- Aurora Lane Interface
LANE_UP => lane_up_i,
SOFT_ERROR => soft_error_i,
HARD_ERROR => hard_error_i,
CHANNEL_BOND_LOAD => channel_bond_load_i,
GOT_A => got_a_i,
GOT_V => got_v_i,
GEN_A => gen_a_i,
GEN_K => gen_k_i,
GEN_R => gen_r_i,
GEN_V => gen_v_i,
RESET_LANES => reset_lanes_i,
-- System Interface
USER_CLK => USER_CLK,
RESET => system_reset_c,
POWER_DOWN => POWER_DOWN,
CHANNEL_UP => channel_up_i,
START_RX => start_rx_i,
CHANNEL_SOFT_ERROR => SOFT_ERROR_Buffer,
CHANNEL_HARD_ERROR => HARD_ERROR_Buffer
);
-- Instantiate TX_LL --
tx_ll_i : TX_LL
port map (
-- LocalLink PDU Interface
TX_D => TX_D,
TX_REM => TX_REM,
TX_SRC_RDY_N => TX_SRC_RDY_N,
TX_SOF_N => TX_SOF_N,
TX_EOF_N => TX_EOF_N,
TX_DST_RDY_N => TX_DST_RDY_N_Buffer,
-- NFC Interface
NFC_REQ_N => NFC_REQ_N,
NFC_NB => NFC_NB,
NFC_ACK_N => NFC_ACK_N_Buffer,
-- Clock Compenstaion Interface
WARN_CC => WARN_CC,
DO_CC => DO_CC,
-- Global Logic Interface
CHANNEL_UP => channel_up_i,
-- Aurora Lane Interface
GEN_SCP => gen_scp_i,
GEN_ECP => gen_ecp_i,
GEN_SNF => gen_snf_i,
FC_NB => fc_nb_i,
TX_PE_DATA_V => tx_pe_data_v_i,
GEN_PAD => gen_pad_i,
TX_PE_DATA => tx_pe_data_i,
GEN_CC => gen_cc_i,
-- RX_LL Interface
TX_WAIT => tx_wait_i,
DECREMENT_NFC => decrement_nfc_i,
-- System Interface
USER_CLK => USER_CLK
);
-- Instantiate RX_LL --
rx_ll_i : RX_LL
port map (
-- LocalLink PDU Interface
RX_D => RX_D_Buffer,
RX_REM => RX_REM_Buffer,
RX_SRC_RDY_N => RX_SRC_RDY_N_Buffer,
RX_SOF_N => RX_SOF_N_Buffer,
RX_EOF_N => RX_EOF_N_Buffer,
-- Global Logic Interface
START_RX => start_rx_i,
-- Aurora Lane Interface
RX_PAD => rx_pad_i,
RX_PE_DATA => rx_pe_data_i,
RX_PE_DATA_V => rx_pe_data_v_i,
RX_SCP => rx_scp_i,
RX_ECP => rx_ecp_i,
RX_SNF => rx_snf_i,
RX_FC_NB => rx_fc_nb_i,
-- TX_LL Interface
DECREMENT_NFC => decrement_nfc_i,
TX_WAIT => tx_wait_i,
-- Error Interface
FRAME_ERROR => FRAME_ERROR_Buffer,
-- System Interface
USER_CLK => USER_CLK
);
end MAPPED;
|
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/21 23:26:37 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: aurora_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.3 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- aurora_16b
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: Brian Woodard
-- Xilinx - Garden Valley Design Team
--
-- Description: This is the top level module for a 1 2-byte lane Aurora
-- reference design module. This module supports the following features:
--
-- * Immediate Mode Native Flow Control
-- * Supports Virtex 2 Pro
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synthesis translate_off
library UNISIM;
use UNISIM.all;
-- synthesis translate_on
entity aurora_16b is
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- LocalLink TX Interface
TX_D : in std_logic_vector(0 to 15);
TX_REM : in std_logic;
TX_SRC_RDY_N : in std_logic;
TX_SOF_N : in std_logic;
TX_EOF_N : in std_logic;
TX_DST_RDY_N : out std_logic;
-- LocalLink RX Interface
RX_D : out std_logic_vector(0 to 15);
RX_REM : out std_logic;
RX_SRC_RDY_N : out std_logic;
RX_SOF_N : out std_logic;
RX_EOF_N : out std_logic;
-- Native Flow Control Interface
NFC_REQ_N : in std_logic;
NFC_NB : in std_logic_vector(0 to 3);
NFC_ACK_N : out std_logic;
-- MGT Serial I/O
RXP : in std_logic;
RXN : in std_logic;
TXP : out std_logic;
TXN : out std_logic;
-- MGT Reference Clock Interface
TOP_BREF_CLK : in std_logic;
-- Error Detection Interface
HARD_ERROR : out std_logic;
SOFT_ERROR : out std_logic;
FRAME_ERROR : out std_logic;
-- Status
CHANNEL_UP : out std_logic;
LANE_UP : out std_logic;
-- Clock Compensation Control Interface
WARN_CC : in std_logic;
DO_CC : in std_logic;
-- System Interface
DCM_NOT_LOCKED : in std_logic;
USER_CLK : in std_logic;
RESET : in std_logic;
POWER_DOWN : in std_logic;
LOOPBACK : in std_logic_vector(1 downto 0)
);
end aurora_16b;
architecture MAPPED of aurora_16b is
-- External Register Declarations --
signal TX_DST_RDY_N_Buffer : std_logic;
signal RX_D_Buffer : std_logic_vector(0 to 15);
signal RX_REM_Buffer : std_logic;
signal RX_SRC_RDY_N_Buffer : std_logic;
signal RX_SOF_N_Buffer : std_logic;
signal RX_EOF_N_Buffer : std_logic;
signal NFC_ACK_N_Buffer : std_logic;
signal TXP_Buffer : std_logic;
signal TXN_Buffer : std_logic;
signal HARD_ERROR_Buffer : std_logic;
signal SOFT_ERROR_Buffer : std_logic;
signal FRAME_ERROR_Buffer : std_logic;
signal CHANNEL_UP_Buffer : std_logic;
signal LANE_UP_Buffer : std_logic;
-- Wire Declarations --
signal rx_data_i : std_logic_vector(15 downto 0);
signal rx_not_in_table_i : std_logic_vector(1 downto 0);
signal rx_disp_err_i : std_logic_vector(1 downto 0);
signal rx_char_is_k_i : std_logic_vector(1 downto 0);
signal rx_char_is_comma_i : std_logic_vector(1 downto 0);
signal rx_buf_status_i : std_logic;
signal tx_buf_err_i : std_logic;
signal tx_k_err_i : std_logic_vector(1 downto 0);
signal rx_clk_cor_cnt_i : std_logic_vector(2 downto 0);
signal rx_realign_i : std_logic;
signal rx_polarity_i : std_logic;
signal rx_reset_i : std_logic;
signal tx_char_is_k_i : std_logic_vector(1 downto 0);
signal tx_data_i : std_logic_vector(15 downto 0);
signal tx_reset_i : std_logic;
signal ena_comma_align_i : std_logic;
signal gen_scp_i : std_logic;
signal gen_snf_i : std_logic;
signal fc_nb_i : std_logic_vector(0 to 3);
signal gen_ecp_i : std_logic;
signal gen_pad_i : std_logic;
signal tx_pe_data_i : std_logic_vector(0 to 15);
signal tx_pe_data_v_i : std_logic;
signal gen_cc_i : std_logic;
signal rx_pad_i : std_logic;
signal rx_pe_data_i : std_logic_vector(0 to 15);
signal rx_pe_data_v_i : std_logic;
signal rx_scp_i : std_logic;
signal rx_ecp_i : std_logic;
signal rx_snf_i : std_logic;
signal rx_fc_nb_i : std_logic_vector(0 to 3);
signal gen_a_i : std_logic;
signal gen_k_i : std_logic_vector(0 to 1);
signal gen_r_i : std_logic_vector(0 to 1);
signal gen_v_i : std_logic_vector(0 to 1);
signal lane_up_i : std_logic;
signal soft_error_i : std_logic;
signal hard_error_i : std_logic;
signal channel_bond_load_i : std_logic;
signal got_a_i : std_logic_vector(0 to 1);
signal got_v_i : std_logic;
signal reset_lanes_i : std_logic;
signal rx_rec_clk_i : std_logic;
signal ena_calign_rec_i : std_logic;
signal txcharisk_lane_0_i : std_logic_vector(3 downto 0);
signal txdata_lane_0_i : std_logic_vector(31 downto 0);
signal refclksel_lane_0_i : std_logic;
signal txbypass8b10b_lane_0_i : std_logic_vector(3 downto 0);
signal txchardispmode_lane_0_i : std_logic_vector(3 downto 0);
signal txchardispval_lane_0_i : std_logic_vector(3 downto 0);
signal configenable_lane_0_i : std_logic;
signal configin_lane_0_i : std_logic;
signal txforcecrcerr_lane_0_i : std_logic;
signal txinhibit_lane_0_i : std_logic;
signal txpolarity_lane_0_i : std_logic;
signal rxdata_lane_0_i : std_logic_vector(31 downto 0);
signal rxnotintable_lane_0_i : std_logic_vector(3 downto 0);
signal rxdisperr_lane_0_i : std_logic_vector(3 downto 0);
signal rxcharisk_lane_0_i : std_logic_vector(3 downto 0);
signal rxchariscomma_lane_0_i : std_logic_vector(3 downto 0);
signal rxbufstatus_lane_0_i : std_logic_vector(1 downto 0);
signal txkerr_lane_0_i : std_logic_vector(3 downto 0);
signal ch_bond_done_i : std_logic;
signal en_chan_sync_i : std_logic;
signal channel_up_i : std_logic;
signal start_rx_i : std_logic;
signal tx_wait_i : std_logic;
signal decrement_nfc_i : std_logic;
signal chbondi_not_used_i : std_logic_vector(3 downto 0);
signal chbondo_not_used_i : std_logic_vector(3 downto 0);
signal tied_to_ground_i : std_logic;
signal tied_to_vcc_i : std_logic;
signal system_reset_c : std_logic;
signal fc_nb_not_used_i : std_logic_vector(0 to 3);
-- Component Declarations --
component FD
generic (INIT : bit := '0');
port (
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic
);
end component;
component AURORA_LANE
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- MGT Interface
RX_DATA : in std_logic_vector(15 downto 0); -- 2-byte data bus from the MGT.
RX_NOT_IN_TABLE : in std_logic_vector(1 downto 0); -- Invalid 10-bit code was recieved.
RX_DISP_ERR : in std_logic_vector(1 downto 0); -- Disparity error detected on RX interface.
RX_CHAR_IS_K : in std_logic_vector(1 downto 0); -- Indicates which bytes of RX_DATA are control.
RX_CHAR_IS_COMMA : in std_logic_vector(1 downto 0); -- Comma received on given byte.
RX_BUF_STATUS : in std_logic; -- Overflow/Underflow of RX buffer detected.
TX_BUF_ERR : in std_logic; -- Overflow/Underflow of TX buffer detected.
TX_K_ERR : in std_logic_vector(1 downto 0); -- Attempt to send bad control byte detected.
RX_CLK_COR_CNT : in std_logic_vector(2 downto 0); -- Value used to determine channel bonding status.
RX_REALIGN : in std_logic; -- SERDES was realigned because of a new comma.
RX_POLARITY : out std_logic; -- Controls interpreted polarity of serial data inputs.
RX_RESET : out std_logic; -- Reset RX side of MGT logic.
TX_CHAR_IS_K : out std_logic_vector(1 downto 0); -- TX_DATA byte is a control character.
TX_DATA : out std_logic_vector(15 downto 0); -- 2-byte data bus to the MGT.
TX_RESET : out std_logic; -- Reset TX side of MGT logic.
-- Comma Detect Phase Align Interface
ENA_COMMA_ALIGN : out std_logic; -- Request comma alignment.
-- TX_LL Interface
GEN_SCP : in std_logic; -- SCP generation request from TX_LL.
GEN_ECP : in std_logic; -- ECP generation request from TX_LL.
GEN_SNF : in std_logic; -- SNF generation request from TX_LL.
GEN_PAD : in std_logic; -- PAD generation request from TX_LL.
FC_NB : in std_logic_vector(0 to 3); -- Size code for SUF and SNF messages.
TX_PE_DATA : in std_logic_vector(0 to 15); -- Data from TX_LL to send over lane.
TX_PE_DATA_V : in std_logic; -- Indicates TX_PE_DATA is Valid.
GEN_CC : in std_logic; -- CC generation request from TX_LL.
-- RX_LL Interface
RX_PAD : out std_logic; -- Indicates lane received PAD.
RX_PE_DATA : out std_logic_vector(0 to 15); -- RX data from lane to RX_LL.
RX_PE_DATA_V : out std_logic; -- RX_PE_DATA is data, not control symbol.
RX_SCP : out std_logic; -- Indicates lane received SCP.
RX_ECP : out std_logic; -- Indicates lane received ECP.
RX_SNF : out std_logic; -- Indicates lane received SNF.
RX_FC_NB : out std_logic_vector(0 to 3); -- Size code for SNF or SUF.
-- Global Logic Interface
GEN_A : in std_logic; -- 'A character' generation request from Global Logic.
GEN_K : in std_logic_vector(0 to 1); -- 'K character' generation request from Global Logic.
GEN_R : in std_logic_vector(0 to 1); -- 'R character' generation request from Global Logic.
GEN_V : in std_logic_vector(0 to 1); -- Verification data generation request.
LANE_UP : out std_logic; -- Lane is ready for bonding and verification.
SOFT_ERROR : out std_logic; -- Soft error detected.
HARD_ERROR : out std_logic; -- Hard error detected.
CHANNEL_BOND_LOAD : out std_logic; -- Channel Bonding done code received.
GOT_A : out std_logic_vector(0 to 1); -- Indicates lane recieved 'A character' bytes.
GOT_V : out std_logic; -- Verification symbols received.
-- System Interface
USER_CLK : in std_logic; -- System clock for all non-MGT Aurora Logic.
RESET : in std_logic -- Reset the lane.
);
end component;
component PHASE_ALIGN
port (
-- Aurora Lane Interface
ENA_COMMA_ALIGN : in std_logic;
-- MGT Interface
RX_REC_CLK : in std_logic;
ENA_CALIGN_REC : out std_logic
);
end component;
component GT_CUSTOM
generic (ALIGN_COMMA_MSB : boolean;
CHAN_BOND_MODE : string;
CHAN_BOND_ONE_SHOT : boolean;
CHAN_BOND_SEQ_1_1 : bit_vector;
REF_CLK_V_SEL : integer;
CLK_COR_INSERT_IDLE_FLAG : boolean;
CLK_COR_KEEP_IDLE : boolean;
CLK_COR_REPEAT_WAIT : integer;
CLK_COR_SEQ_1_1 : bit_vector;
CLK_COR_SEQ_1_2 : bit_vector;
CLK_COR_SEQ_2_USE : boolean;
CLK_COR_SEQ_LEN : integer;
CLK_CORRECT_USE : boolean;
COMMA_10B_MASK : bit_vector;
MCOMMA_10B_VALUE : bit_vector;
PCOMMA_10B_VALUE : bit_vector;
RX_CRC_USE : boolean;
RX_DATA_WIDTH : integer;
RX_LOSS_OF_SYNC_FSM : boolean;
RX_LOS_INVALID_INCR : integer;
RX_LOS_THRESHOLD : integer;
SERDES_10B : boolean;
TERMINATION_IMP : integer;
TX_CRC_USE : boolean;
TX_DATA_WIDTH : integer;
TX_DIFF_CTRL : integer;
TX_PREEMPHASIS : integer);
port (
CHBONDDONE : out std_logic;
CHBONDO : out std_logic_vector(3 downto 0);
CONFIGOUT : out std_logic;
RXBUFSTATUS : out std_logic_vector(1 downto 0);
RXCHARISCOMMA : out std_logic_vector(3 downto 0);
RXCHARISK : out std_logic_vector(3 downto 0);
RXCHECKINGCRC : out std_logic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_logic;
RXCRCERR : out std_logic;
RXDATA : out std_logic_vector(31 downto 0);
RXDISPERR : out std_logic_vector(3 downto 0);
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector(3 downto 0);
RXREALIGN : out std_logic;
RXRECCLK : out std_logic;
RXRUNDISP : out std_logic_vector(3 downto 0);
TXBUFERR : out std_logic;
TXKERR : out std_logic_vector(3 downto 0);
TXN : out std_logic;
TXP : out std_logic;
TXRUNDISP : out std_logic_vector(3 downto 0);
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector(3 downto 0);
CONFIGENABLE : in std_logic;
CONFIGIN : in std_logic;
ENCHANSYNC : in std_logic;
ENMCOMMAALIGN : in std_logic;
ENPCOMMAALIGN : in std_logic;
LOOPBACK : in std_logic_vector(1 downto 0);
POWERDOWN : in std_logic;
REFCLK : in std_logic;
REFCLK2 : in std_logic;
REFCLKSEL : in std_logic;
RXN : in std_logic;
RXP : in std_logic;
RXPOLARITY : in std_logic;
RXRESET : in std_logic;
RXUSRCLK : in std_logic;
RXUSRCLK2 : in std_logic;
TXBYPASS8B10B : in std_logic_vector(3 downto 0);
TXCHARDISPMODE : in std_logic_vector(3 downto 0);
TXCHARDISPVAL : in std_logic_vector(3 downto 0);
TXCHARISK : in std_logic_vector(3 downto 0);
TXDATA : in std_logic_vector(31 downto 0);
TXFORCECRCERR : in std_logic;
TXINHIBIT : in std_logic;
TXPOLARITY : in std_logic;
TXRESET : in std_logic;
TXUSRCLK : in std_logic;
TXUSRCLK2 : in std_logic
);
end component;
-- attribute syn_black_box of GT_CUSTOM : component is true;
component GLOBAL_LOGIC
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- MGT Interface
CH_BOND_DONE : in std_logic;
EN_CHAN_SYNC : out std_logic;
-- Aurora Lane Interface
LANE_UP : in std_logic;
SOFT_ERROR : in std_logic;
HARD_ERROR : in std_logic;
CHANNEL_BOND_LOAD : in std_logic;
GOT_A : in std_logic_vector(0 to 1);
GOT_V : in std_logic;
GEN_A : out std_logic;
GEN_K : out std_logic_vector(0 to 1);
GEN_R : out std_logic_vector(0 to 1);
GEN_V : out std_logic_vector(0 to 1);
RESET_LANES : out std_logic;
-- System Interface
USER_CLK : in std_logic;
RESET : in std_logic;
POWER_DOWN : in std_logic;
CHANNEL_UP : out std_logic;
START_RX : out std_logic;
CHANNEL_SOFT_ERROR : out std_logic;
CHANNEL_HARD_ERROR : out std_logic
);
end component;
component TX_LL
port (
-- LocalLink PDU Interface
TX_D : in std_logic_vector(0 to 15);
TX_REM : in std_logic;
TX_SRC_RDY_N : in std_logic;
TX_SOF_N : in std_logic;
TX_EOF_N : in std_logic;
TX_DST_RDY_N : out std_logic;
-- NFC Interface
NFC_REQ_N : in std_logic;
NFC_NB : in std_logic_vector(0 to 3);
NFC_ACK_N : out std_logic;
-- Clock Compensation Interface
WARN_CC : in std_logic;
DO_CC : in std_logic;
-- Global Logic Interface
CHANNEL_UP : in std_logic;
-- Aurora Lane Interface
GEN_SCP : out std_logic;
GEN_ECP : out std_logic;
GEN_SNF : out std_logic;
FC_NB : out std_logic_vector(0 to 3);
TX_PE_DATA_V : out std_logic;
GEN_PAD : out std_logic;
TX_PE_DATA : out std_logic_vector(0 to 15);
GEN_CC : out std_logic;
-- RX_LL Interface
TX_WAIT : in std_logic;
DECREMENT_NFC : out std_logic;
-- System Interface
USER_CLK : in std_logic
);
end component;
component RX_LL
port (
-- LocalLink PDU Interface
RX_D : out std_logic_vector(0 to 15);
RX_REM : out std_logic;
RX_SRC_RDY_N : out std_logic;
RX_SOF_N : out std_logic;
RX_EOF_N : out std_logic;
-- Global Logic Interface
START_RX : in std_logic;
-- Aurora Lane Interface
RX_PAD : in std_logic;
RX_PE_DATA : in std_logic_vector(0 to 15);
RX_PE_DATA_V : in std_logic;
RX_SCP : in std_logic;
RX_ECP : in std_logic;
RX_SNF : in std_logic;
RX_FC_NB : in std_logic_vector(0 to 3);
-- TX_LL Interface
DECREMENT_NFC : in std_logic;
TX_WAIT : out std_logic;
-- Error Interface
FRAME_ERROR : out std_logic;
-- System Interface
USER_CLK : in std_logic
);
end component;
begin
TX_DST_RDY_N <= TX_DST_RDY_N_Buffer;
RX_D <= RX_D_Buffer;
RX_REM <= RX_REM_Buffer;
RX_SRC_RDY_N <= RX_SRC_RDY_N_Buffer;
RX_SOF_N <= RX_SOF_N_Buffer;
RX_EOF_N <= RX_EOF_N_Buffer;
NFC_ACK_N <= NFC_ACK_N_Buffer;
TXP <= TXP_Buffer;
TXN <= TXN_Buffer;
HARD_ERROR <= HARD_ERROR_Buffer;
SOFT_ERROR <= SOFT_ERROR_Buffer;
FRAME_ERROR <= FRAME_ERROR_Buffer;
CHANNEL_UP <= CHANNEL_UP_Buffer;
LANE_UP <= LANE_UP_Buffer;
-- Main Body of Code --
tied_to_ground_i <= '0';
tied_to_vcc_i <= '1';
chbondi_not_used_i <= "0000";
fc_nb_not_used_i <= "0000";
CHANNEL_UP_Buffer <= channel_up_i;
system_reset_c <= RESET or DCM_NOT_LOCKED;
-- Instantiate Lane 0 --
LANE_UP_Buffer <= lane_up_i;
aurora_lane_0_i : AURORA_LANE
generic map (
EXTEND_WATCHDOGS => EXTEND_WATCHDOGS
)
port map (
-- MGT Interface
RX_DATA => rx_data_i(15 downto 0),
RX_NOT_IN_TABLE => rx_not_in_table_i(1 downto 0),
RX_DISP_ERR => rx_disp_err_i(1 downto 0),
RX_CHAR_IS_K => rx_char_is_k_i(1 downto 0),
RX_CHAR_IS_COMMA => rx_char_is_comma_i(1 downto 0),
RX_BUF_STATUS => rx_buf_status_i,
TX_BUF_ERR => tx_buf_err_i,
TX_K_ERR => tx_k_err_i(1 downto 0),
RX_CLK_COR_CNT => rx_clk_cor_cnt_i(2 downto 0),
RX_REALIGN => rx_realign_i,
RX_POLARITY => rx_polarity_i,
RX_RESET => rx_reset_i,
TX_CHAR_IS_K => tx_char_is_k_i(1 downto 0),
TX_DATA => tx_data_i(15 downto 0),
TX_RESET => tx_reset_i,
-- Comma Detect Phase Align Interface
ENA_COMMA_ALIGN => ena_comma_align_i,
-- TX_LL Interface
GEN_SCP => gen_scp_i,
GEN_SNF => gen_snf_i,
FC_NB => fc_nb_i,
GEN_ECP => gen_ecp_i,
GEN_PAD => gen_pad_i,
TX_PE_DATA => tx_pe_data_i(0 to 15),
TX_PE_DATA_V => tx_pe_data_v_i,
GEN_CC => gen_cc_i,
-- RX_LL Interface
RX_PAD => rx_pad_i,
RX_PE_DATA => rx_pe_data_i(0 to 15),
RX_PE_DATA_V => rx_pe_data_v_i,
RX_SCP => rx_scp_i,
RX_ECP => rx_ecp_i,
RX_SNF => rx_snf_i,
RX_FC_NB => rx_fc_nb_i(0 to 3),
-- Global Logic Interface
GEN_A => gen_a_i,
GEN_K => gen_k_i(0 to 1),
GEN_R => gen_r_i(0 to 1),
GEN_V => gen_v_i(0 to 1),
LANE_UP => lane_up_i,
SOFT_ERROR => soft_error_i,
HARD_ERROR => hard_error_i,
CHANNEL_BOND_LOAD => channel_bond_load_i,
GOT_A => got_a_i(0 to 1),
GOT_V => got_v_i,
-- System Interface
USER_CLK => USER_CLK,
RESET => reset_lanes_i
);
lane_0_phase_align_i : PHASE_ALIGN
port map (
-- Aurora Lane Interface
ENA_COMMA_ALIGN => ena_comma_align_i,
-- MGT Interface
RX_REC_CLK => rx_rec_clk_i,
ENA_CALIGN_REC => ena_calign_rec_i
);
txcharisk_lane_0_i <= "00" & tx_char_is_k_i(1 downto 0);
txdata_lane_0_i <= "0000000000000000" & tx_data_i(15 downto 0);
refclksel_lane_0_i <= '0';
txbypass8b10b_lane_0_i <= "0000";
txchardispmode_lane_0_i <= "0000";
txchardispval_lane_0_i <= "0000";
configenable_lane_0_i <= '0';
configin_lane_0_i <= '0';
txforcecrcerr_lane_0_i <= '0';
txinhibit_lane_0_i <= '0';
txpolarity_lane_0_i <= '0';
rx_data_i(15 downto 0) <= rxdata_lane_0_i(15 downto 0);
rx_not_in_table_i(1 downto 0) <= rxnotintable_lane_0_i(1 downto 0);
rx_disp_err_i(1 downto 0) <= rxdisperr_lane_0_i(1 downto 0);
rx_char_is_k_i(1 downto 0) <= rxcharisk_lane_0_i(1 downto 0);
rx_char_is_comma_i(1 downto 0) <= rxchariscomma_lane_0_i(1 downto 0);
rx_buf_status_i <= rxbufstatus_lane_0_i(1);
tx_k_err_i(1 downto 0) <= txkerr_lane_0_i(1 downto 0);
lane_0_mgt_i : GT_CUSTOM
-- Lane 0 MGT attributes
generic map (
ALIGN_COMMA_MSB => TRUE,
CHAN_BOND_MODE => "OFF",
CHAN_BOND_ONE_SHOT => FALSE,
CHAN_BOND_SEQ_1_1 => "00101111100",
REF_CLK_V_SEL => 1,
CLK_COR_INSERT_IDLE_FLAG => FALSE,
CLK_COR_KEEP_IDLE => FALSE,
CLK_COR_REPEAT_WAIT => 8,
CLK_COR_SEQ_1_1 => "00111110111",
CLK_COR_SEQ_1_2 => "00111110111",
CLK_COR_SEQ_2_USE => FALSE,
CLK_COR_SEQ_LEN => 2,
CLK_CORRECT_USE => TRUE,
COMMA_10B_MASK => "1111111111",
MCOMMA_10B_VALUE => "1100000101",
PCOMMA_10B_VALUE => "0011111010",
RX_CRC_USE => FALSE,
RX_DATA_WIDTH => 2,
RX_LOSS_OF_SYNC_FSM => FALSE,
RX_LOS_INVALID_INCR => 1,
RX_LOS_THRESHOLD => 4,
SERDES_10B => FALSE,
TERMINATION_IMP => 50,
TX_CRC_USE => FALSE,
TX_DATA_WIDTH => 2,
TX_DIFF_CTRL => 600,
TX_PREEMPHASIS => 1
)
port map (
-- Aurora Lane Interface
RXPOLARITY => rx_polarity_i,
RXRESET => rx_reset_i,
TXCHARISK => txcharisk_lane_0_i,
TXDATA => txdata_lane_0_i,
TXRESET => tx_reset_i,
RXDATA => rxdata_lane_0_i,
RXNOTINTABLE => rxnotintable_lane_0_i,
RXDISPERR => rxdisperr_lane_0_i,
RXCHARISK => rxcharisk_lane_0_i,
RXCHARISCOMMA => rxchariscomma_lane_0_i,
RXBUFSTATUS => rxbufstatus_lane_0_i,
TXBUFERR => tx_buf_err_i,
TXKERR => txkerr_lane_0_i,
RXCLKCORCNT => rx_clk_cor_cnt_i(2 downto 0),
RXREALIGN => rx_realign_i,
-- Phase Align Interface
ENMCOMMAALIGN => ena_calign_rec_i,
ENPCOMMAALIGN => ena_calign_rec_i,
RXRECCLK => rx_rec_clk_i,
-- Global Logic Interface
ENCHANSYNC => tied_to_ground_i,
CHBONDDONE => ch_bond_done_i,
-- Peer Channel Bonding Interface
CHBONDI => chbondi_not_used_i,
CHBONDO => chbondo_not_used_i(3 downto 0),
-- Unused MGT Ports
CONFIGOUT => open,
RXCHECKINGCRC => open,
RXCOMMADET => open,
RXCRCERR => open,
RXLOSSOFSYNC => open,
RXRUNDISP => open,
TXRUNDISP => open,
-- Fixed MGT settings for Aurora
TXBYPASS8B10B => txbypass8b10b_lane_0_i,
TXCHARDISPMODE => txchardispmode_lane_0_i,
TXCHARDISPVAL => txchardispval_lane_0_i,
CONFIGENABLE => configenable_lane_0_i,
CONFIGIN => configin_lane_0_i,
TXFORCECRCERR => txforcecrcerr_lane_0_i,
TXINHIBIT => txinhibit_lane_0_i,
TXPOLARITY => txpolarity_lane_0_i,
-- Serial IO
RXN => RXN,
RXP => RXP,
TXN => TXN_Buffer,
TXP => TXP_Buffer,
-- Reference Clocks and User Clock
RXUSRCLK => USER_CLK,
RXUSRCLK2 => USER_CLK,
TXUSRCLK => USER_CLK,
TXUSRCLK2 => USER_CLK,
BREFCLK => TOP_BREF_CLK,
BREFCLK2 => tied_to_ground_i,
REFCLK => tied_to_ground_i,
REFCLK2 => tied_to_ground_i,
REFCLKSEL => refclksel_lane_0_i,
-- System Interface
LOOPBACK => LOOPBACK,
POWERDOWN => POWER_DOWN
);
-- Instantiate Global Logic to combine Lanes into a Channel --
global_logic_i : GLOBAL_LOGIC
generic map (
EXTEND_WATCHDOGS => EXTEND_WATCHDOGS
)
port map (
-- MGT Interface
CH_BOND_DONE => ch_bond_done_i,
EN_CHAN_SYNC => en_chan_sync_i,
-- Aurora Lane Interface
LANE_UP => lane_up_i,
SOFT_ERROR => soft_error_i,
HARD_ERROR => hard_error_i,
CHANNEL_BOND_LOAD => channel_bond_load_i,
GOT_A => got_a_i,
GOT_V => got_v_i,
GEN_A => gen_a_i,
GEN_K => gen_k_i,
GEN_R => gen_r_i,
GEN_V => gen_v_i,
RESET_LANES => reset_lanes_i,
-- System Interface
USER_CLK => USER_CLK,
RESET => system_reset_c,
POWER_DOWN => POWER_DOWN,
CHANNEL_UP => channel_up_i,
START_RX => start_rx_i,
CHANNEL_SOFT_ERROR => SOFT_ERROR_Buffer,
CHANNEL_HARD_ERROR => HARD_ERROR_Buffer
);
-- Instantiate TX_LL --
tx_ll_i : TX_LL
port map (
-- LocalLink PDU Interface
TX_D => TX_D,
TX_REM => TX_REM,
TX_SRC_RDY_N => TX_SRC_RDY_N,
TX_SOF_N => TX_SOF_N,
TX_EOF_N => TX_EOF_N,
TX_DST_RDY_N => TX_DST_RDY_N_Buffer,
-- NFC Interface
NFC_REQ_N => NFC_REQ_N,
NFC_NB => NFC_NB,
NFC_ACK_N => NFC_ACK_N_Buffer,
-- Clock Compenstaion Interface
WARN_CC => WARN_CC,
DO_CC => DO_CC,
-- Global Logic Interface
CHANNEL_UP => channel_up_i,
-- Aurora Lane Interface
GEN_SCP => gen_scp_i,
GEN_ECP => gen_ecp_i,
GEN_SNF => gen_snf_i,
FC_NB => fc_nb_i,
TX_PE_DATA_V => tx_pe_data_v_i,
GEN_PAD => gen_pad_i,
TX_PE_DATA => tx_pe_data_i,
GEN_CC => gen_cc_i,
-- RX_LL Interface
TX_WAIT => tx_wait_i,
DECREMENT_NFC => decrement_nfc_i,
-- System Interface
USER_CLK => USER_CLK
);
-- Instantiate RX_LL --
rx_ll_i : RX_LL
port map (
-- LocalLink PDU Interface
RX_D => RX_D_Buffer,
RX_REM => RX_REM_Buffer,
RX_SRC_RDY_N => RX_SRC_RDY_N_Buffer,
RX_SOF_N => RX_SOF_N_Buffer,
RX_EOF_N => RX_EOF_N_Buffer,
-- Global Logic Interface
START_RX => start_rx_i,
-- Aurora Lane Interface
RX_PAD => rx_pad_i,
RX_PE_DATA => rx_pe_data_i,
RX_PE_DATA_V => rx_pe_data_v_i,
RX_SCP => rx_scp_i,
RX_ECP => rx_ecp_i,
RX_SNF => rx_snf_i,
RX_FC_NB => rx_fc_nb_i,
-- TX_LL Interface
DECREMENT_NFC => decrement_nfc_i,
TX_WAIT => tx_wait_i,
-- Error Interface
FRAME_ERROR => FRAME_ERROR_Buffer,
-- System Interface
USER_CLK => USER_CLK
);
end MAPPED;
|
-- nios_rst_controller_001.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity nios_rst_controller_001;
architecture rtl of nios_rst_controller_001 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller_001 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of nios_rst_controller_001
|
-- nios_rst_controller_001.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity nios_rst_controller_001;
architecture rtl of nios_rst_controller_001 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller_001 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of nios_rst_controller_001
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_640x480 is
Port ( clk, clr : in STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
hc : out STD_LOGIC_VECTOR(9 downto 0);
vc : out STD_LOGIC_VECTOR(9 downto 0);
vidon : out STD_LOGIC);
end vga_640x480;
architecture Behavioral of vga_640x480 is
constant hpixels: STD_LOGIC_VECTOR(9 downto 0) := "1100100000";
--Pixels in a horizontal line = 800
constant vlines : STD_LOGIC_VECTOR(9 downto 0) := "1000001001";
--Lines in the image = 521
constant hbp : STD_LOGIC_VECTOR(9 downto 0) := "0010010000";
--Horizontal back porch = 144
constant hfp : STD_LOGIC_VECTOR(9 downto 0) := "1100010000";
--Horiztonal front porch = 748
constant vbp : STD_LOGIC_VECTOR(9 downto 0) := "0000011111";
--Vertical back porch = 31
constant vfp : STD_LOGIC_VECTOR(9 downto 0) := "0111111111";
--Vertical front porch = 511
signal hcs, vcs: STD_LOGIC_VECTOR(9 downto 0);
--Horiztonal and vertical counters
signal vsenable : STD_LOGIC;
--Enable for the vertical counter
signal hsync_s, vsync_s : STD_LOGIC;
begin
--Counter for the horizontal sync signal
process(clk, clr)
begin
if clr = '1' then
hcs <= "0000000000";
elsif(clk'event and clk = '1') then
if hcs = hpixels - 1 then
--The counter has reached the end of pixel count, reset
hcs <= "0000000000";
--Enable the vertical counter
vsenable <= '1';
else
--Increment the horizontal counter
hcs <= hcs + 1;
--Leave vsenable off
vsenable <= '0';
end if;
end if;
end process;
--Horizontal sync pulse is low when hc is 0-127
hsync_s <= '0' when hcs < 128 else '1';
--Counter for the vertical sync signal
process(clk, clr)
begin
if clr = '1' then
vcs <= "0000000000";
elsif(clk'event and clk = '1' and vsenable = '1') then
--Increment when enabled
if vcs = vlines - 1 then
--Reset when the number of lines is reached
vcs <= "0000000000";
else
--Increment vertical counter
vcs <= vcs + 1;
end if;
end if;
end process;
--Vertical sync pulse is low when vc is 0 or 1
vsync_s <= '0' when vcs < 2 else '1';
--Enable video out when within the porches
--vidon <= '1' when (((hcs < hfp) and (hcs >= hbp)) and ((vcs < vfp) and (vcs >= vbp))) else '0';
vidon <= (vsync_s and hsync_s);
--Output horizontal and vertical counters
hc <= hcs;
vc <= vcs;
hsync <= hsync_s;
vsync <= vsync_s;
end Behavioral;
|
-------------------------------------------------------------------------------
--! @file lutFileRtl.vhd
--
--! @brief Look-up table file implementation
--
--! @details This look-up table file stores initialization values (generics)
--! in LUT resources.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity lutFile is
generic (
gLutCount : natural := 4;
gLutWidth : natural := 32;
gLutInitValue : std_logic_vector :=
x"1111_1111" & x"2222_2222" & x"3333_3333" & x"4444_4444"
);
port (
iAddrRead : in std_logic_vector(LogDualis(gLutCount)-1 downto 0);
oData : out std_logic_vector
);
end lutFile;
architecture Rtl of lutFile is
constant cLutFile : std_logic_vector(gLutCount*gLutWidth-1 downto 0) :=
gLutInitValue;
signal lutOutput : std_logic_vector(gLutWidth-1 downto 0);
begin
--Lut File is a bitstream that is blockwise (gLutWidth) read with
--respect to iAddrRead.
bitSelect : process(iAddrRead)
begin
--default
lutOutput <= (others => '0');
for i in gLutWidth-1 downto 0 loop
--assign selected bits in Lut File to output
lutOutput(i) <= cLutFile
( (gLutCount-1-to_integer(unsigned(iAddrRead)))*gLutWidth + i );
end loop;
end process;
--! downscale lut width to output
oData <= lutOutput(oData'range);
end Rtl;
|
-- clkgen_tb.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clkgen_tb is
end entity;
architecture testbench of clkgen_tb is
signal clk_0 : std_logic;
signal rst_0 : std_logic;
signal clk_10 : std_logic;
signal rst_10 : std_logic;
signal clk_45 : std_logic;
signal rst_45 : std_logic;
signal clk_90 : std_logic;
signal rst_90 : std_logic;
signal clk_180 : std_logic;
signal rst_180 : std_logic;
signal clk_360 : std_logic;
signal rst_360 : std_logic;
begin
clkgen_0 : entity work.clkgen
generic map (
FREQ => 200.0,
RST_CYCLES => 200,
PHASE => 0
)
port map (
CLK => clk_0,
RST => rst_0
);
clkgen_10 : entity work.clkgen
generic map (
FREQ => 200.0,
RST_CYCLES => 200,
PHASE => 10
)
port map (
CLK => clk_10,
RST => rst_10
);
clkgen_45 : entity work.clkgen
generic map (
FREQ => 200.0,
RST_CYCLES => 200,
PHASE => 45
)
port map (
CLK => clk_45,
RST => rst_45
);
clkgen_90 : entity work.clkgen
generic map (
FREQ => 200.0,
RST_CYCLES => 200,
PHASE => 90
)
port map (
CLK => clk_90,
RST => rst_90
);
clkgen_180 : entity work.clkgen
generic map (
FREQ => 200.0,
RST_CYCLES => 200,
PHASE => 180
)
port map (
CLK => clk_180,
RST => rst_180
);
clkgen_360 : entity work.clkgen
generic map (
FREQ => 200.0,
RST_CYCLES => 200,
PHASE => 360
)
port map (
CLK => clk_360,
RST => rst_360
);
end architecture;
|
use Std.Textio.all;
library IEEE;
library worklib;
use ieee.std_logic_1164.ALL;
entity test_c_subtractor
is end;
architecture test_c_subtractor of test_c_subtractor is
component c_subtractor
generic(width: integer := 4);
port(input1, input2: in std_logic_vector((width-1) downto 0);
output : out std_logic_vector(width downto 0));
end component;
for all : c_subtractor use entity work.c_subtractor(behavior);
signal input1 : std_logic_vector(3 downto 0);
signal input2 : std_logic_vector(3 downto 0);
signal out1 : std_logic_vector(4 downto 0);
begin
subtractor4 : c_subtractor generic map(4)
port map( input1, input2, out1);
test_process : process
begin
-- 0 - 1 = -1
input1 <= "0000" ;
input2 <= "0001" ;
wait for 10 ns;
-- +7 - 5 = +2
input1 <= "0111" ;
input2 <= "0101" ;
wait for 10 ns;
-- +5 - 7 = -2
input1 <= "0101" ;
input2 <= "0111" ;
wait for 10 ns;
-- -8 -8 = -16
input1 <= "1000" ;
input2 <= "1000" ;
wait for 10 ns;
-- -7 +7 = 0
input1 <= "1001" ;
input2 <= "0111" ;
wait for 10 ns;
wait;
end process test_process ;
end test_c_subtractor;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer: Gabbe
--
-- Create Date: 12:04:52 09/17/2014
-- Design Name:
-- Module Name: H:/embedded_labs/comp/tb_comp.vhd
-- Project Name: comp
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: comp
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_comp IS
END tb_comp;
ARCHITECTURE behavior OF tb_comp IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT comp
PORT(
clk : IN std_logic;
rstn : IN std_logic;
i_hash_0 : IN unsigned(31 downto 0);
i_hash_1 : IN unsigned(31 downto 0);
i_hash_2 : IN unsigned(31 downto 0);
i_hash_3 : IN unsigned(31 downto 0);
i_cmp_hash : IN std_logic_vector(127 downto 0);
i_start : IN std_logic;
o_equal : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rstn : std_logic := '1';
signal i_hash_0 : unsigned(31 downto 0) := (others => '0');
signal i_hash_1 : unsigned(31 downto 0) := (others => '0');
signal i_hash_2 : unsigned(31 downto 0) := (others => '0');
signal i_hash_3 : unsigned(31 downto 0) := (others => '0');
signal i_cmp_hash : std_logic_vector(127 downto 0) := (others => '0');
signal i_start : std_logic := '0';
--Outputs
signal o_equal : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: comp PORT MAP (
clk => clk,
rstn => rstn,
i_hash_0 => i_hash_0,
i_hash_1 => i_hash_1,
i_hash_2 => i_hash_2,
i_hash_3 => i_hash_3,
i_cmp_hash => i_cmp_hash,
i_start => i_start,
o_equal => o_res
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2;
rstn <= '0';
wait for clk_period;
rstn <= '1';
i_cmp_hash <= x"13121110232221203332313043424140";
i_start <= '1';
wait for clk_period;
i_start <= '0';
i_hash_0 <= x"10111213";
i_hash_1 <= x"20212223";
i_hash_2 <= x"30313233";
i_hash_3 <= x"40414243";
assert o_equal = '1' report "correct hash compared wrong";
wait for clk_period*4;
i_hash_0 <= x"11111111";
i_hash_1 <= x"11111111";
i_hash_2 <= x"11111111";
i_hash_3 <= x"11111111";
wait for clk_period;
assert o_equal = '0' report "false hash compared wrong";
wait;
end process;
END;
|
-- Testbench for com5402_wrapper
--
-- * ARP requests
-- * broadcast udp rx
-- * unicast udp rx
-- * unicast udp rx filtering
-- * udp tx with NACK from ComBlock
-- * tcp conneciton establish
-- * tcp tx with tready deasserting
--
-- Original author: Colm Ryan
-- Copyright 2015,2016 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_frame_pkg.all;
use work.IPv4_packet_pkg.all;
entity com5402_wrapper_tb is
end;
architecture bench of com5402_wrapper_tb is
constant APS2_UDP_PORT : std_logic_vector(15 downto 0) := x"bb4f";
constant UUT_MAC_ADDR : MACAddr_t := (x"46", x"1d", x"db", x"11", x"22", x"33");
constant UUT_IP_ADDR : IPv4_addr_t := (x"c0", x"a8", x"02", x"03");
constant HOST_MAC_ADDR : MACAddr_t := (x"ba", x"ad", x"0d", x"db", x"a1", x"11");
constant HOST_IP_ADDR : IPv4_addr_t := (x"c0", x"a8", x"02", x"01");
constant HOST2_MAC_ADDR : MACAddr_t := (x"ba", x"ad", x"0d", x"db", x"a1", x"12");
constant HOST2_IP_ADDR : IPv4_addr_t := (x"c0", x"a8", x"02", x"51");
constant BROADCAST_IP_ADDR : IPv4_addr_t := (x"c0", x"a8", x"02", x"ff");
constant WRONG_IP_ADDR : IPv4_addr_t := (x"c0", x"a8", x"02", x"04");
constant BROADCAST_MAC_ADDR : MACAddr_t := (x"ff", x"ff", x"ff", x"ff", x"ff", x"ff");
-- "I am an APS2"
constant ENUMERATE_RESPONSE : byte_array :=
(x"49", x"20", x"61", x"6d", x"20", x"61", x"6e", x"20", x"41", x"50", x"53", x"32");
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal mac_addr : std_logic_vector(47 downto 0) := UUT_MAC_ADDR(0) & UUT_MAC_ADDR(1) & UUT_MAC_ADDR(2) & UUT_MAC_ADDR(3) & UUT_MAC_ADDR(4) & UUT_MAC_ADDR(5);
signal IPv4_addr : std_logic_vector(31 downto 0) := UUT_IP_ADDR(0) & UUT_IP_ADDR(1) & UUT_IP_ADDR(2) & UUT_IP_ADDR(3);
signal subnet_mask : std_logic_vector(31 downto 0) := x"ffffff00";
signal gateway_ip_addr : std_logic_vector(31 downto 0) := x"c0a80201";
signal tcp_rst : std_logic := '0';
signal dhcp_enable : std_logic := '0';
signal mac_tx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal mac_tx_tvalid : std_logic := '0';
signal mac_tx_tlast : std_logic := '0';
signal mac_tx_tuser : std_logic := '0';
signal mac_tx_tready : std_logic := '1';
signal mac_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal mac_rx_tvalid : std_logic := '0';
signal mac_rx_tlast : std_logic := '0';
signal mac_rx_tuser : std_logic := '0';
signal mac_rx_tready : std_logic := '0';
signal udp_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal udp_rx_tvalid : std_logic := '0';
signal udp_rx_tlast : std_logic := '0';
signal udp_rx_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal rx_src_ip_addr : std_logic_vector(31 downto 0);
signal udp_tx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal udp_tx_tvalid : std_logic := '0';
signal udp_tx_tlast : std_logic := '0';
signal udp_tx_tready : std_logic := '0';
signal udp_tx_src_port : std_logic_vector(15 downto 0) := APS2_UDP_PORT;
signal udp_tx_dest_port : std_logic_vector(15 downto 0) := APS2_UDP_PORT;
signal udp_tx_dest_ip_addr : std_logic_vector(31 downto 0) := HOST2_IP_ADDR(0) & HOST2_IP_ADDR(1) & HOST2_IP_ADDR(2) & HOST2_IP_ADDR(3);
signal udp_tx_ack : std_logic;
signal udp_tx_nack : std_logic;
signal tcp_port : std_logic_vector(15 downto 0) := x"bb4e";
signal tcp_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal tcp_rx_tvalid : std_logic := '0';
signal tcp_rx_tready : std_logic := '1';
signal tcp_tx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal tcp_tx_tvalid : std_logic := '0';
signal tcp_tx_tready : std_logic := '0';
constant clock_period: time := 8 ns;
signal stop_the_clock: boolean := false;
type TestBenchState_t is (RESET, ARP_REQUEST, UDP_BROADCAST_RX, UDP_UNICAST_RX,
NO_INTERFRAME_GAP, UDP_UNICAST_IP_FILTER, UDP_TX,
ARP_RESPONSE, UDP_TX_RETRY, TCP_ESTABLISH, TCP_RX, DHCP);
signal testBench_state : TestBenchState_t;
signal checking_finished : boolean := false;
shared variable tcp_test_payload : byte_array(0 to 1023);
begin
uut: entity work.com5402_wrapper
generic map ( SIMULATION => '1')
port map (
clk => clk,
rst => rst,
tcp_rst => tcp_rst,
mac_addr => mac_addr,
IPv4_addr => IPv4_addr,
subnet_mask => subnet_mask,
gateway_ip_addr => gateway_ip_addr,
dhcp_enable => dhcp_enable,
mac_tx_tdata => mac_tx_tdata,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tlast => mac_tx_tlast,
mac_tx_tuser => mac_tx_tuser,
mac_tx_tready => mac_tx_tready,
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tlast => mac_rx_tlast,
mac_rx_tuser => mac_rx_tuser,
mac_rx_tready => mac_rx_tready,
udp_rx_tdata => udp_rx_tdata,
udp_rx_tvalid => udp_rx_tvalid,
udp_rx_tlast => udp_rx_tlast,
udp_rx_dest_port => APS2_UDP_PORT,
udp_rx_src_port => udp_rx_src_port,
rx_src_ip_addr => rx_src_ip_addr,
udp_tx_tdata => udp_tx_tdata,
udp_tx_tvalid => udp_tx_tvalid,
udp_tx_tlast => udp_tx_tlast,
udp_tx_tready => udp_tx_tready,
udp_tx_src_port => udp_tx_src_port,
udp_tx_dest_port => udp_tx_dest_port,
udp_tx_dest_ip_addr => udp_tx_dest_ip_addr,
udp_tx_ack => udp_tx_ack,
udp_tx_nack => udp_tx_nack,
tcp_port => tcp_port,
tcp_rx_tdata => tcp_rx_tdata,
tcp_rx_tvalid => tcp_rx_tvalid,
tcp_rx_tready => tcp_rx_tready,
tcp_tx_tdata => tcp_tx_tdata,
tcp_tx_tvalid => tcp_tx_tvalid,
tcp_tx_tready => tcp_tx_tready
);
clk <= not clk after clock_period / 2 when not stop_the_clock;
stimulus: process
constant ARP_req : byte_array := (
x"00", x"01", -- hardware type
x"08", x"00", -- protocol type
x"06", --hardware length (MAC address is 6 bytes)
x"04", --protocol size
x"00", x"01", -- request operation
HOST_MAC_ADDR(0), HOST_MAC_ADDR(1), HOST_MAC_ADDR(2),
HOST_MAC_ADDR(3), HOST_MAC_ADDR(4), HOST_MAC_ADDR(5), --sender MAC address
HOST_IP_ADDR(0), HOST_IP_ADDR(1), HOST_IP_ADDR(2), HOST_IP_ADDR(3), --sender IPv4 address
x"00", x"00", x"00", x"00", x"00", x"00", --target MAC address; empty for request
UUT_IP_ADDR(0), UUT_IP_ADDR(1), UUT_IP_ADDR(2), UUT_IP_ADDR(3) -- target IP address
);
constant ARP_resp : byte_array := (
x"00", x"01", -- hardware type
x"08", x"00", -- protocol type
x"06", --hardware length (MAC address is 6 bytes)
x"04", --protocol size
x"00", x"02", -- response operation
HOST2_MAC_ADDR(0), HOST2_MAC_ADDR(1), HOST2_MAC_ADDR(2),
HOST2_MAC_ADDR(3), HOST2_MAC_ADDR(4), HOST2_MAC_ADDR(5), --sender MAC address
HOST2_IP_ADDR(0), HOST2_IP_ADDR(1), HOST2_IP_ADDR(2), HOST2_IP_ADDR(3), -- sender IP address
UUT_MAC_ADDR(0), UUT_MAC_ADDR(1), UUT_MAC_ADDR(2),
UUT_MAC_ADDR(3), UUT_MAC_ADDR(4), UUT_MAC_ADDR(5), --target MAC address
UUT_IP_ADDR(0), UUT_IP_ADDR(1), UUT_IP_ADDR(2), UUT_IP_ADDR(3) --target IPv4 address
);
constant empty_payload : byte_array(0 to -1) := (others => (others => '0'));
constant UDP_test_payload : byte_array := (x"01", x"02", x"03", x"04");
variable tcp_response_packet : byte_array(0 to 1521);
variable ct : natural;
variable seq_num, ack_num, recv_seq_num, recv_ack_num : natural;
variable tmp : std_logic_vector(31 downto 0);
variable src_MAC, dest_MAC : MACAddr_t := (others => (others => '0'));
variable timeout : time;
begin
wait until rising_edge(clk);
--------------------------------------------------------------------------------
testBench_state <= RESET;
rst <= '1';
wait for 100ns;
wait until rising_edge(clk);
rst <= '0';
wait for 100ns;
wait until rising_edge(clk);
--------------------------------------------------------------------------------
testBench_state <= ARP_REQUEST;
--ARP request who has 192.168.2.3? Tell 192.168.2.1";
src_MAC := (x"ba", x"ad", x"0d", x"db", x"a1", x"11");
dest_MAC := (x"FF", x"FF", x"FF", x"FF", x"FF", x"FF");
write_ethernet_frame(dest_MAC, src_MAC, x"0806", ARP_req, clk, mac_rx_tdata,
mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
mac_rx_tlast <= '1';
--wait for the response to come back
wait until rising_edge(clk) and mac_tx_tvalid = '1' and mac_tx_tlast = '1' for 1us;
--Make sure nothing else comes back
--coverage for issue #26
timeout := now + 5 us;
while now < timeout loop
wait until rising_edge(clk);
assert mac_tx_tvalid = '0' report "mac_tx traffic when there shouldn't be";
assert mac_tx_tlast = '0' report "mac_tx traffic when there shouldn't be";
end loop;
--------------------------------------------------------------------------------
--Clock in a broadcast UDP packet
testBench_state <= UDP_BROADCAST_RX;
dest_MAC := UUT_MAC_ADDR;
write_ethernet_frame(BROADCAST_MAC_ADDR, src_MAC, x"0800",
udp_packet(HOST_IP_ADDR, BROADCAST_IP_ADDR, x"abcd", APS2_UDP_PORT, UDP_test_payload),
clk, mac_rx_tdata, mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
--interframe gap
for ct in 1 to 12 loop
wait until rising_edge(clk);
end loop;
--Clock in an unicast UDP packet to the correct IP
testBench_state <= UDP_UNICAST_RX;
dest_MAC := UUT_MAC_ADDR;
write_ethernet_frame(dest_MAC, src_MAC, x"0800",
udp_packet(HOST_IP_ADDR, UUT_IP_ADDR, APS2_UDP_PORT, APS2_UDP_PORT, UDP_test_payload),
clk, mac_rx_tdata, mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
--repeat with no interframe gap to test gap adder
testBench_state <= NO_INTERFRAME_GAP;
dest_MAC := UUT_MAC_ADDR;
write_ethernet_frame(dest_MAC, src_MAC, x"0800",
udp_packet(HOST_IP_ADDR, UUT_IP_ADDR, APS2_UDP_PORT, APS2_UDP_PORT, UDP_test_payload),
clk, mac_rx_tdata, mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
--interframe gap
for ct in 1 to 12 loop
wait until rising_edge(clk);
end loop;
--Clock in a unicast UDP packet to the wrong IP
testBench_state <= UDP_UNICAST_IP_FILTER;
dest_MAC := UUT_MAC_ADDR;
write_ethernet_frame(dest_MAC, src_MAC, x"0800",
udp_packet(HOST_IP_ADDR, WRONG_IP_ADDR, APS2_UDP_PORT, APS2_UDP_PORT, UDP_test_payload),
clk, mac_rx_tdata, mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
--------------------------------------------------------------------------------
--Try to send a response to UDP
--Send to different host to trigger ARP request and NACK
testBench_state <= UDP_TX;
wait until rising_edge(clk);
for ct in 0 to ENUMERATE_RESPONSE'high loop
udp_tx_tdata <= ENUMERATE_RESPONSE(ct);
udp_tx_tvalid <= '1';
if ct = ENUMERATE_RESPONSE'high then
udp_tx_tlast <= '1';
else
udp_tx_tlast <= '0';
end if;
wait until rising_edge(clk) and udp_tx_tready = '1';
end loop;
udp_tx_tvalid <= '0';
udp_tx_tlast <= '0';
wait until mac_tx_tvalid = '1' and mac_tx_tlast = '1' for 5 us;
--Send back the ARP response
testBench_state <= ARP_RESPONSE;
src_MAC := (x"ba", x"ad", x"0d", x"db", x"a1", x"12");
write_ethernet_frame(dest_MAC, src_MAC, x"0806", ARP_resp, clk, mac_rx_tdata,
mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
wait for 5 us;
--Try again the UDP_TX
testBench_state <= UDP_TX_RETRY;
wait until rising_edge(clk);
for ct in 0 to ENUMERATE_RESPONSE'high loop
udp_tx_tdata <= ENUMERATE_RESPONSE(ct);
udp_tx_tvalid <= '1';
if ct = ENUMERATE_RESPONSE'high then
udp_tx_tlast <= '1';
else
udp_tx_tlast <= '0';
end if;
wait until rising_edge(clk) and udp_tx_tready = '1';
end loop;
udp_tx_tvalid <= '0';
udp_tx_tlast <= '0';
wait until mac_tx_tvalid = '1' and mac_tx_tlast = '1' for 5 us;
--------------------------------------------------------------------------------
--Try to establish TCP connection
seq_num := 0;
ack_num := 0;
testBench_state <= TCP_ESTABLISH;
wait until rising_edge(clk);
write_ethernet_frame(dest_MAC, src_MAC, x"0800",
tcp_packet(HOST_IP_ADDR, UUT_IP_ADDR, x"bb4f", x"bb4e", seq_num, ack_num, '1', '0', empty_payload),
clk, mac_rx_tdata, mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
--extract the sequence and ack number returned
ct := 0;
loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
tcp_response_packet(ct) := mac_tx_tdata;
ct := ct + 1;
exit when mac_tx_tlast = '1';
end loop;
--sequence number starts at byte 14 (ethernet frame header) + 20 (IPv4 header) + 4 (tcp src/dest port)= 38
--For some reason Vivado can't infer this as one line
-- recv_seq_num := to_integer(unsigned( tcp_response_packet(38) & tcp_response_packet(39) & tcp_response_packet(40) & tcp_response_packet(41) ) );
-- recv_ack_num := to_integer(unsigned( tcp_response_packet(42) & tcp_response_packet(43) & tcp_response_packet(44) & tcp_response_packet(45) ) );
tmp := tcp_response_packet(38) & tcp_response_packet(39) & tcp_response_packet(40) & tcp_response_packet(41);
recv_seq_num := to_integer(unsigned(tmp));
tmp := tcp_response_packet(42) & tcp_response_packet(43) & tcp_response_packet(44) & tcp_response_packet(45);
recv_ack_num := to_integer(unsigned(tmp));
ack_num := recv_seq_num + 1;
seq_num := recv_ack_num;
--send ack back to finish connection established
wait until rising_edge(clk);
write_ethernet_frame(dest_MAC, src_MAC, x"0800",
tcp_packet(HOST_IP_ADDR, UUT_IP_ADDR, x"bb4f", x"bb4e", seq_num, ack_num, '0', '1', empty_payload),
clk, mac_rx_tdata, mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
--interframe gap
for ct in 1 to 12 loop
wait until rising_edge(clk);
end loop;
--send data
testBench_state <= TCP_RX;
for k in 0 to 1023 loop
tcp_test_payload(k) := std_logic_vector(to_unsigned(k, 8));
end loop;
wait until rising_edge(clk);
write_ethernet_frame(dest_MAC, src_MAC, x"0800",
tcp_packet(HOST_IP_ADDR, UUT_IP_ADDR, x"bb4f", x"bb4e", seq_num, ack_num, '0', '1', tcp_test_payload),
clk, mac_rx_tdata, mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
ct := 0;
loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
tcp_response_packet(ct) := mac_tx_tdata;
ct := ct + 1;
exit when mac_tx_tlast = '1';
end loop;
--wait for the data to show up
wait until tcp_rx_tvalid = '1' for 100 ns;
-- let the first half go by then start dropping ready periodically
ct := 0;
loop
if ct < 512 then
tcp_rx_tready <= '1';
wait until rising_edge(clk);
else
if (ct mod 16) = 0 then
tcp_rx_tready <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
else
tcp_rx_tready <= '1';
wait until rising_edge(clk);
end if;
end if;
ct := ct + 1;
exit when ct = 1024;
end loop;
tcp_rx_tready <= '1';
wait for 500 ns;
--------------------------------------------------------------------------------
testBench_state <= DHCP;
dhcp_enable <= '1';
wait until mac_tx_tvalid = '1' and mac_tx_tlast = '1' for 250us;
assert checking_finished report "Checking process failed to finish";
wait for 1 us;
stop_the_clock <= true;
end process;
checking : process
constant ARP_resp : byte_array := (
x"00", x"01", -- hardware type
x"08", x"00", -- protocol type
x"06", --hardware length (MAC address is 6 bytes)
x"04", --protocol size
x"00", x"02", -- response operation
UUT_MAC_ADDR(0), UUT_MAC_ADDR(1), UUT_MAC_ADDR(2),
UUT_MAC_ADDR(3), UUT_MAC_ADDR(4), UUT_MAC_ADDR(5), --sender MAC address
UUT_IP_ADDR(0), UUT_IP_ADDR(1), UUT_IP_ADDR(2), UUT_IP_ADDR(3), --sender IPv4 address
HOST_MAC_ADDR(0), HOST_MAC_ADDR(1), HOST_MAC_ADDR(2),
HOST_MAC_ADDR(3), HOST_MAC_ADDR(4), HOST_MAC_ADDR(5), --target MAC address
HOST_IP_ADDR(0), HOST_IP_ADDR(1), HOST_IP_ADDR(2), HOST_IP_ADDR(3) -- target IP address
);
constant ARP_req : byte_array := (
x"00", x"01", -- hardware type
x"08", x"00", -- protocol type
x"06", --hardware length (MAC address is 6 bytes)
x"04", --protocol size
x"00", x"01", -- request operation
UUT_MAC_ADDR(0), UUT_MAC_ADDR(1), UUT_MAC_ADDR(2),
UUT_MAC_ADDR(3), UUT_MAC_ADDR(4), UUT_MAC_ADDR(5), --sender MAC address
UUT_IP_ADDR(0), UUT_IP_ADDR(1), UUT_IP_ADDR(2), UUT_IP_ADDR(3), --sender IPv4 address
x"00", x"00", x"00", x"00", x"00", x"00", --target MAC address; empty for request
HOST2_IP_ADDR(0), HOST2_IP_ADDR(1), HOST2_IP_ADDR(2), HOST2_IP_ADDR(3) -- target IP address
);
begin
--------------------------------------------------------------------------------
--First thing back is the ARP response
--Ethernet frame header
for ct in 0 to 5 loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = HOST_MAC_ADDR(ct) report "ARP response ethernet frame MAC header incorrect";
end loop;
for ct in 0 to 5 loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = UUT_MAC_ADDR(ct) report "ARP response ethernet frame MAC header incorrect";
end loop;
--Ethernet type
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = x"08" report "ARP response ethernet frame MAC header incorrect";
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = x"06" report "ARP response ethernet frame MAC header incorrect";
for ct in 0 to ARP_resp'high loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = ARP_resp(ct) report "ARP response payload incorrect";
if ct = ARP_resp'high then
assert mac_tx_tlast = '1' report "tlast failed to assert end of ARP response";
else
assert mac_tx_tlast = '0' report "tlast asserted early in ARP response";
end if;
end loop;
--------------------------------------------------------------------------------
-- broadcast UDP packet at udp_rx should come through
wait until rising_edge(clk) and mac_rx_tvalid = '1';
-- wait for header (14 Ethernet + 20 IP + 8 UDP) and latency (4)
for ct in 1 to 46 loop
wait until rising_edge(clk);
end loop;
assert udp_rx_src_port = x"abcd" report "UDP source port incorrect";
assert rx_src_ip_addr = HOST_IP_ADDR(0) & HOST_IP_ADDR(1) & HOST_IP_ADDR(2) & HOST_IP_ADDR(3) report "RX source IP address incorrect";
for ct in 0 to 3 loop
assert udp_rx_tdata = std_logic_vector(to_unsigned(ct+1,8));
assert udp_rx_tvalid = '1' report "udp_rx_tvalid failed to assert";
if ct = 3 then
assert udp_rx_tlast = '1' report "udp_rx_tlast failed to assert";
else
assert udp_rx_tlast = '0' report "udp_rx_tlast asserted incorrectly";
wait until rising_edge(clk);
end if;
end loop;
--wait for end of packet
wait until rising_edge(clk) and mac_rx_tlast = '1' for 1 us;
---unicast UDP packet at udp_rx
wait until rising_edge(clk) and mac_rx_tvalid = '1';
-- wait for header (14 Ethernet + 20 IP + 8 UDP) and latency (4)
for ct in 1 to 46 loop
wait until rising_edge(clk);
end loop;
assert udp_rx_src_port = APS2_UDP_PORT report "UDP source port incorrect";
assert rx_src_ip_addr = HOST_IP_ADDR(0) & HOST_IP_ADDR(1) & HOST_IP_ADDR(2) & HOST_IP_ADDR(3) report "RX source IP address incorrect";
for ct in 0 to 3 loop
assert udp_rx_tdata = std_logic_vector(to_unsigned(ct+1,8));
assert udp_rx_tvalid = '1' report "udp_rx_tvalid failed to assert";
if ct = 3 then
assert udp_rx_tlast = '1' report "udp_rx_tlast failed to assert";
else
assert udp_rx_tlast = '0' report "udp_rx_tlast asserted incorrectly";
wait until rising_edge(clk);
end if;
end loop;
--wait for end of packet
wait until rising_edge(clk) and mac_rx_tlast = '1' for 1 us;
---second unicast UDP packet at udp_rx should be delayed by added interframe gap
wait until rising_edge(clk) and mac_rx_tvalid = '1';
for ct in 1 to 8 loop
assert mac_rx_tready = '0' report "mac_rx_tready failed to deassert for interframe gap";
wait until rising_edge(clk);
end loop;
-- wait for header (14 Ethernet + 20 IP + 8 UDP) and latency (4)
for ct in 1 to 46 loop
wait until rising_edge(clk);
end loop;
assert udp_rx_src_port = APS2_UDP_PORT report "UDP source port incorrect";
assert rx_src_ip_addr = HOST_IP_ADDR(0) & HOST_IP_ADDR(1) & HOST_IP_ADDR(2) & HOST_IP_ADDR(3) report "RX source IP address incorrect";
for ct in 0 to 3 loop
assert udp_rx_tdata = std_logic_vector(to_unsigned(ct+1,8));
assert udp_rx_tvalid = '1' report "udp_rx_tvalid failed to assert";
if ct = 3 then
assert udp_rx_tlast = '1' report "udp_rx_tlast failed to assert";
else
assert udp_rx_tlast = '0' report "udp_rx_tlast asserted incorrectly";
wait until rising_edge(clk);
end if;
end loop;
--wait for end of packet
wait until rising_edge(clk) and mac_rx_tlast = '1' for 1 us;
---unicast UDP packet to different IP address should not come through at udp_rx
wait until rising_edge(clk) and mac_rx_tvalid = '1';
-- wait for header (14 Ethernet + 20 IP + 8 UDP) and latency (4)
for ct in 1 to 46 loop
wait until rising_edge(clk);
end loop;
for ct in 0 to 3 loop
assert udp_rx_tvalid = '0' report "udp_rx_tvalid asserted incorrectly";
wait until rising_edge(clk);
end loop;
--wait for end of packet
wait until rising_edge(clk) and mac_rx_tlast = '1' for 1 us;
--------------------------------------------------------------------------------
--Next is a ARP request at mac_tx
--Ethernet frame header
for ct in 0 to 5 loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = x"ff" report "ARP request ethernet frame MAC header incorrect";
end loop;
for ct in 0 to 5 loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = UUT_MAC_ADDR(ct) report "ARP request ethernet frame MAC header incorrect";
end loop;
--Ethernet type
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = x"08" report "ARP request ethernet frame MAC header incorrect";
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = x"06" report "ARP request ethernet frame MAC header incorrect";
for ct in 0 to ARP_req'high loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = ARP_req(ct) report "ARP request payload incorrect";
if ct = ARP_resp'high then
assert mac_tx_tlast = '1' report "tlast failed to assert end of ARP request";
else
assert mac_tx_tlast = '0' report "tlast asserted early in ARP request";
end if;
end loop;
--Next is UDP tx appearing at mac_tx
--count off header (should be checking) 14 bytes ethernet frame header; 20 bytes IpV4 header; 8 byte UDP header
for ct in 1 to 42 loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
end loop;
--Now check ennumerate response
for ct in 0 to ENUMERATE_RESPONSE'high loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = ENUMERATE_RESPONSE(ct) report "udp_tx data incorrect";
end loop;
--Next is TCP stream at tcp_rx
for ct in 0 to 1023 loop
wait until rising_edge(clk) and tcp_rx_tvalid = '1' and tcp_rx_tready = '1';
assert tcp_rx_tdata = tcp_test_payload(ct) report "tcp data incorrect";
end loop;
--Next is DHCP request
--TODO: checking
checking_finished <= true;
wait;
end process;
end;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v1.01.a
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.proc_common_pkg.max2;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.family_support.all;
use proc_common_v3_00_a.counter_f;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v1_01_a.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
package test_pkg is
type t_test is (ONE, TWO);
end package;
package test2_pkg is
alias t_test is work.test_pkg.t_test;
end package;
use work.test_pkg.all;
use work.test2_pkg.all;
entity test is
generic(
test_type : t_test := ONE
);
end entity test;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (single beat), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v5_tb is
end ext_mem_ctrl_v5_tb;
architecture tb of ext_mem_ctrl_v5_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic;
signal req : t_mem_req_32;
signal resp : t_mem_resp_32;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(12 downto 0);
signal logic_BA : std_logic_vector(1 downto 0);
signal Q : std_logic_vector(7 downto 0);
signal Qd : std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
clk_2x <= not clk_2x after 5 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
SDRAM_A => logic_A,
SDRAM_BA => logic_BA,
SDRAM_DQ => SDRAM_DQ );
SDRAM_A <= transport logic_A after 6 ns;
SDRAM_CLK <= transport logic_CLK after 6 ns;
SDRAM_CKE <= transport logic_CKE after 6 ns;
SDRAM_CSn <= transport logic_CSn after 6 ns;
SDRAM_RASn <= transport logic_RASn after 6 ns;
SDRAM_CASn <= transport logic_CASn after 6 ns;
SDRAM_WEn <= transport logic_WEn after 6 ns;
SDRAM_DQM <= transport logic_DQM after 6 ns;
p_test: process
begin
req <= c_mem_req_32_init;
wait until reset='0';
wait until clock='1';
req.read_writen <= '1'; -- read
req.read_writen <= '0'; -- write
req.request <= '1';
req.size <= '1';
req.data <= X"44332211";
req.byte_en <= "0111";
req.tag <= X"34";
while true loop
wait until clock='1';
if resp.rack='1' then
if req.read_writen = '0' then
req.address <= req.address + 4;
end if;
req.read_writen <= not req.read_writen;
end if;
end loop;
wait;
end process;
p_read: process(SDRAM_CLK)
variable count : integer := 10;
begin
if rising_edge(SDRAM_CLK) then
if SDRAM_CSn='0' and SDRAM_RASn='1' and SDRAM_CASn='0' and SDRAM_WEn='1' then -- start read
count := 0;
end if;
case count is
when 0 =>
Q <= X"01";
when 1 =>
Q <= X"02";
when 2 =>
Q <= X"03";
when 3 =>
Q <= X"04";
when others =>
Q <= (others => 'Z');
end case;
Qd <= Q;
if Qd(0)='Z' then
SDRAM_DQ <= Qd after 3.6 ns;
else
SDRAM_DQ <= Qd after 5.6 ns;
end if;
count := count + 1;
end if;
end process;
end;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (single beat), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v5_tb is
end ext_mem_ctrl_v5_tb;
architecture tb of ext_mem_ctrl_v5_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic;
signal req : t_mem_req_32;
signal resp : t_mem_resp_32;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(12 downto 0);
signal logic_BA : std_logic_vector(1 downto 0);
signal Q : std_logic_vector(7 downto 0);
signal Qd : std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
clk_2x <= not clk_2x after 5 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
SDRAM_A => logic_A,
SDRAM_BA => logic_BA,
SDRAM_DQ => SDRAM_DQ );
SDRAM_A <= transport logic_A after 6 ns;
SDRAM_CLK <= transport logic_CLK after 6 ns;
SDRAM_CKE <= transport logic_CKE after 6 ns;
SDRAM_CSn <= transport logic_CSn after 6 ns;
SDRAM_RASn <= transport logic_RASn after 6 ns;
SDRAM_CASn <= transport logic_CASn after 6 ns;
SDRAM_WEn <= transport logic_WEn after 6 ns;
SDRAM_DQM <= transport logic_DQM after 6 ns;
p_test: process
begin
req <= c_mem_req_32_init;
wait until reset='0';
wait until clock='1';
req.read_writen <= '1'; -- read
req.read_writen <= '0'; -- write
req.request <= '1';
req.size <= '1';
req.data <= X"44332211";
req.byte_en <= "0111";
req.tag <= X"34";
while true loop
wait until clock='1';
if resp.rack='1' then
if req.read_writen = '0' then
req.address <= req.address + 4;
end if;
req.read_writen <= not req.read_writen;
end if;
end loop;
wait;
end process;
p_read: process(SDRAM_CLK)
variable count : integer := 10;
begin
if rising_edge(SDRAM_CLK) then
if SDRAM_CSn='0' and SDRAM_RASn='1' and SDRAM_CASn='0' and SDRAM_WEn='1' then -- start read
count := 0;
end if;
case count is
when 0 =>
Q <= X"01";
when 1 =>
Q <= X"02";
when 2 =>
Q <= X"03";
when 3 =>
Q <= X"04";
when others =>
Q <= (others => 'Z');
end case;
Qd <= Q;
if Qd(0)='Z' then
SDRAM_DQ <= Qd after 3.6 ns;
else
SDRAM_DQ <= Qd after 5.6 ns;
end if;
count := count + 1;
end if;
end process;
end;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (single beat), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v5_tb is
end ext_mem_ctrl_v5_tb;
architecture tb of ext_mem_ctrl_v5_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic;
signal req : t_mem_req_32;
signal resp : t_mem_resp_32;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(12 downto 0);
signal logic_BA : std_logic_vector(1 downto 0);
signal Q : std_logic_vector(7 downto 0);
signal Qd : std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
clk_2x <= not clk_2x after 5 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
SDRAM_A => logic_A,
SDRAM_BA => logic_BA,
SDRAM_DQ => SDRAM_DQ );
SDRAM_A <= transport logic_A after 6 ns;
SDRAM_CLK <= transport logic_CLK after 6 ns;
SDRAM_CKE <= transport logic_CKE after 6 ns;
SDRAM_CSn <= transport logic_CSn after 6 ns;
SDRAM_RASn <= transport logic_RASn after 6 ns;
SDRAM_CASn <= transport logic_CASn after 6 ns;
SDRAM_WEn <= transport logic_WEn after 6 ns;
SDRAM_DQM <= transport logic_DQM after 6 ns;
p_test: process
begin
req <= c_mem_req_32_init;
wait until reset='0';
wait until clock='1';
req.read_writen <= '1'; -- read
req.read_writen <= '0'; -- write
req.request <= '1';
req.size <= '1';
req.data <= X"44332211";
req.byte_en <= "0111";
req.tag <= X"34";
while true loop
wait until clock='1';
if resp.rack='1' then
if req.read_writen = '0' then
req.address <= req.address + 4;
end if;
req.read_writen <= not req.read_writen;
end if;
end loop;
wait;
end process;
p_read: process(SDRAM_CLK)
variable count : integer := 10;
begin
if rising_edge(SDRAM_CLK) then
if SDRAM_CSn='0' and SDRAM_RASn='1' and SDRAM_CASn='0' and SDRAM_WEn='1' then -- start read
count := 0;
end if;
case count is
when 0 =>
Q <= X"01";
when 1 =>
Q <= X"02";
when 2 =>
Q <= X"03";
when 3 =>
Q <= X"04";
when others =>
Q <= (others => 'Z');
end case;
Qd <= Q;
if Qd(0)='Z' then
SDRAM_DQ <= Qd after 3.6 ns;
else
SDRAM_DQ <= Qd after 5.6 ns;
end if;
count := count + 1;
end if;
end process;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iodpad
-- File: iodpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Open-drain I/O pad with technology wrapper
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iodpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iodpad is
signal gnd, oen : std_ulogic;
begin
oen <= not i when oepol /= padoen_polarity(tech) else i;
gnd <= '0';
gen0 : if has_pads(tech) = 0 generate
pad <= '0'
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(i)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
o <= to_X01(pad)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
pa : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
igl2 : if (tech = igloo2) generate
x0 : igloo2_iopad port map (pad, gnd, oen, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
um : if (tech = umc) generate
x0 : umc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_iopad generic map (strength) port map (pad, gnd, oen, o);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (level, slew, voltage, strength)
port map(pad, gnd, oen, o);
end generate;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iodpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iodpadv is
begin
v : for j in width-1 downto 0 generate
x0 : iodpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), o(j));
end generate;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1800.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p03n01i01800ent IS
END c07s01b00x00p03n01i01800ent;
ARCHITECTURE c07s01b00x00p03n01i01800arch OF c07s01b00x00p03n01i01800ent IS
BEGIN
TESTING: PROCESS
variable x : real := 4;
variable y : real := 6.7;
variable z : real := 4.8;
variable p : real;
BEGIN
if y = x = z then -- Failure_here
-- only a single relational operator allowed.
p := y + z + x;
end if;
assert FALSE
report "***FAILED TEST: c07s01b00x00p03n01i01800 - Only a single relational operator is used to combine expressions and form realtions."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p03n01i01800arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1800.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p03n01i01800ent IS
END c07s01b00x00p03n01i01800ent;
ARCHITECTURE c07s01b00x00p03n01i01800arch OF c07s01b00x00p03n01i01800ent IS
BEGIN
TESTING: PROCESS
variable x : real := 4;
variable y : real := 6.7;
variable z : real := 4.8;
variable p : real;
BEGIN
if y = x = z then -- Failure_here
-- only a single relational operator allowed.
p := y + z + x;
end if;
assert FALSE
report "***FAILED TEST: c07s01b00x00p03n01i01800 - Only a single relational operator is used to combine expressions and form realtions."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p03n01i01800arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1800.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p03n01i01800ent IS
END c07s01b00x00p03n01i01800ent;
ARCHITECTURE c07s01b00x00p03n01i01800arch OF c07s01b00x00p03n01i01800ent IS
BEGIN
TESTING: PROCESS
variable x : real := 4;
variable y : real := 6.7;
variable z : real := 4.8;
variable p : real;
BEGIN
if y = x = z then -- Failure_here
-- only a single relational operator allowed.
p := y + z + x;
end if;
assert FALSE
report "***FAILED TEST: c07s01b00x00p03n01i01800 - Only a single relational operator is used to combine expressions and form realtions."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p03n01i01800arch;
|
package poly is
generic (a, b : integer);
function apply (x : integer) return integer;
end package;
package body poly is
function apply (x : integer) return integer is
begin
return x * a + b;
end function;
end package body;
-------------------------------------------------------------------------------
package wrapper is
generic ( package p is new work.poly generic map ( <> ) );
function wrapped_apply (n : integer) return integer;
procedure check_params (xa, xb : integer);
end package;
package body wrapper is
use p.all;
function wrapped_apply (n : integer) return integer is
begin
return apply(n);
end function;
procedure check_params (xa, xb : integer) is
begin
report "a=" & to_string(a) & " b=" & to_string(b);
assert a = xa;
assert b = xb;
end procedure;
end package body;
-------------------------------------------------------------------------------
entity genpack3 is
end entity;
architecture test of genpack3 is
package my_poly1 is new work.poly generic map (a => 2, b => 3);
package my_wrap1 is new work.wrapper generic map (p => my_poly1);
package my_poly2 is new work.poly generic map (a => 5, b => 1);
package my_wrap2 is new work.wrapper generic map (p => my_poly2);
begin
main: process is
variable v : integer := 5;
begin
assert my_wrap1.wrapped_apply(2) = 7;
wait for 1 ns;
assert my_wrap1.wrapped_apply(v) = 13;
my_wrap1.check_params(2, 3);
assert my_wrap2.wrapped_apply(2) = 11;
assert my_wrap2.wrapped_apply(v) = 26;
my_wrap2.check_params(v, 1);
wait;
end process;
end architecture;
|
library ieee;
package body fifo_pkg is
end package body;
-- Violation below
package body fifo_pkg is
end package body;
-- Comments could be allowed
library ieee;
package body fifo_pkg is
end package body;
entity fifo is
end entity fifo;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2135.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02135ent IS
END c07s02b04x00p21n01i02135ent;
ARCHITECTURE c07s02b04x00p21n01i02135arch OF c07s02b04x00p21n01i02135ent IS
TYPE simple_record is record
data_1 : integer;
data_2 : integer;
end record;
TYPE record_v is array (integer range <>) of simple_record;
SUBTYPE record_null is record_v (1 to 0);
SUBTYPE record_1 is record_v (1 to 1);
BEGIN
TESTING: PROCESS
variable result : record_1;
variable l_operand : record_null;
variable r_operand : simple_record := (12,34);
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result(1) = (12,34) )
report "***PASSED TEST: c07s02b04x00p21n01i02135"
severity NOTE;
assert ( result(1) = (12,34) )
report "***FAILED TEST: c07s02b04x00p21n01i02135 - Concatenation of null and RECORD element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02135arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2135.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02135ent IS
END c07s02b04x00p21n01i02135ent;
ARCHITECTURE c07s02b04x00p21n01i02135arch OF c07s02b04x00p21n01i02135ent IS
TYPE simple_record is record
data_1 : integer;
data_2 : integer;
end record;
TYPE record_v is array (integer range <>) of simple_record;
SUBTYPE record_null is record_v (1 to 0);
SUBTYPE record_1 is record_v (1 to 1);
BEGIN
TESTING: PROCESS
variable result : record_1;
variable l_operand : record_null;
variable r_operand : simple_record := (12,34);
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result(1) = (12,34) )
report "***PASSED TEST: c07s02b04x00p21n01i02135"
severity NOTE;
assert ( result(1) = (12,34) )
report "***FAILED TEST: c07s02b04x00p21n01i02135 - Concatenation of null and RECORD element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02135arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2135.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02135ent IS
END c07s02b04x00p21n01i02135ent;
ARCHITECTURE c07s02b04x00p21n01i02135arch OF c07s02b04x00p21n01i02135ent IS
TYPE simple_record is record
data_1 : integer;
data_2 : integer;
end record;
TYPE record_v is array (integer range <>) of simple_record;
SUBTYPE record_null is record_v (1 to 0);
SUBTYPE record_1 is record_v (1 to 1);
BEGIN
TESTING: PROCESS
variable result : record_1;
variable l_operand : record_null;
variable r_operand : simple_record := (12,34);
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result(1) = (12,34) )
report "***PASSED TEST: c07s02b04x00p21n01i02135"
severity NOTE;
assert ( result(1) = (12,34) )
report "***FAILED TEST: c07s02b04x00p21n01i02135 - Concatenation of null and RECORD element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02135arch;
|
-------------------------------------------------------------------------------------------------------------
-- Extender
-- This unit recieves as input the immediate filed in the instruction(15-0). Depending on the value of the
-- control signal Unsigned_value it performs and unsigned sing-extension or a signed sign-extension(in two's
-- complement. The block is fully combinational.
-------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
-------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
entity extender is
port (
-- INPUTS
immediate : in std_logic_vector(15 downto 0); -- immediate filed (instruction 15 -0)
unsigned_value : in std_logic; -- control signal generated by the CU
-- OUTPUTS
extended : out std_logic_vector(31 downto 0) -- extended value
);
end extender;
-------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
architecture behavioral of extender is
begin
--------------------------------------------------
-- Extend Process
-- Type: Combinational
-- Implemnents the
-- sign-extensionl
-- logic
-----------------------i--------------------------
extend_process:process(immediate, unsigned_value)
begin
if (unsigned_value = '1') then
extended <= "0000000000000000" & immediate;
else
if (immediate(15) = '1') then
extended(31 downto 16) <= (others => '1');
extended(15 downto 0) <= immediate;
else
extended(31 downto 16) <= (others => '0');
extended(15 downto 0) <= immediate;
end if;
end if;
end process;
end behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2584.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02584ent IS
END c13s03b01x00p02n01i02584ent;
ARCHITECTURE c13s03b01x00p02n01i02584arch OF c13s03b01x00p02n01i02584ent IS
BEGIN
TESTING: PROCESS
variable k^ : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02584 - Identifier can not end with '^'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02584arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2584.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02584ent IS
END c13s03b01x00p02n01i02584ent;
ARCHITECTURE c13s03b01x00p02n01i02584arch OF c13s03b01x00p02n01i02584ent IS
BEGIN
TESTING: PROCESS
variable k^ : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02584 - Identifier can not end with '^'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02584arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2584.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02584ent IS
END c13s03b01x00p02n01i02584ent;
ARCHITECTURE c13s03b01x00p02n01i02584arch OF c13s03b01x00p02n01i02584ent IS
BEGIN
TESTING: PROCESS
variable k^ : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02584 - Identifier can not end with '^'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02584arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D4_C1 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D4_C1;
architecture D4_C1 of D4_C1 is
type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal s:state;
begin
next_state:process(rst,clk)
begin
if (rst='1') then s<=s0;
else
if (rising_edge(clk)) then
case s is
when s0 => s <=s1;
when s1 => s <=s2;
when s2 => s <=s3;
when s3 => s <=s4;
when s4 => s <=s5;
when s5 => s <=s6;
when s6 => s <=s7;
when s7 => s <=s8;
when s8 => s <=s9;
when s9 => s <=s0;
end case;
end if;
end if;
end process;
output_state:process(s)
begin
case s is
when s0 => seg<= x"C0";
when s1 => seg<= x"F9";
when s2 => seg<= x"A4";
when s3 => seg<= x"B0";
when s4 => seg<= x"99";
when s5 => seg<= x"92";
when s6 => seg<= x"82";
when s7 => seg<= x"F8";
when s8 => seg<= x"80";
when s9 => seg<= x"90";
end case;
end process;
end D4_C1;
-- rst=0.5Mhz; clk=20Mhz; |
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity mixed_clock_fifo_regbased_tb is
end mixed_clock_fifo_regbased_tb;
architecture TB_ARCHITECTURE of mixed_clock_fifo_regbased_tb is
-- Component declaration of the tested unit
component mixed_clock_fifo_regbased
generic(
N : INTEGER;
L : INTEGER );
port(
reset : in STD_LOGIC;
read_clk : in STD_LOGIC;
read : in STD_LOGIC;
valid : out STD_LOGIC;
empty : out STD_LOGIC;
read_data : out STD_LOGIC_VECTOR(N-1 downto 0);
write_clk : in STD_LOGIC;
write : in STD_LOGIC;
full : out STD_LOGIC;
write_data : in STD_LOGIC_VECTOR(N-1 downto 0) );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal reset : STD_LOGIC := '0';
signal read_clk : STD_LOGIC := '0';
signal read : STD_LOGIC := '0';
signal write_clk : STD_LOGIC := '0';
signal write : STD_LOGIC := '0';
signal write_data : STD_LOGIC_VECTOR(15 downto 0) := X"0000";
-- Observed signals - signals mapped to the output ports of tested entity
signal valid : STD_LOGIC := '0';
signal empty : STD_LOGIC := '0';
signal read_data : STD_LOGIC_VECTOR(15 downto 0) := X"0000";
signal full : STD_LOGIC := '0';
-- Add your code here ...
constant clk1_period : time := 8 ns;
constant clk2_period : time := 15 ns;
begin
-- Unit Under Test port map
UUT : mixed_clock_fifo_regbased
generic map (
N => 16,
L => 8
)
port map (
reset => reset,
read_clk => read_clk,
read => read,
valid => valid,
empty => empty,
read_data => read_data,
write_clk => write_clk,
write => write,
full => full,
write_data => write_data
);
--Set read clock to 125 MHz
process
begin
clk1: loop
read_clk <= '1';
wait for clk1_period/2;
read_clk <= '0';
wait for clk1_period/2;
end loop;
end process;
--Set write clock to 66 MHz
process
begin
clk2: loop
write_clk <= '1';
wait for clk2_period/2;
write_clk <= '0';
wait for clk2_period/2;
end loop;
end process;
-- Add your stimulus here ...
process
--procedure to write a data word into the FIFO
procedure put_data(word : in std_logic_vector(15 downto 0)) is
begin
wait until write_clk = '1';
write_data <= word;
write <= '1';
wait until write_clk = '1';
write <= '0';
end procedure;
begin
reset <= '1';
wait for 40 ns;
reset <= '0';
put_data(X"0001");
put_data(X"0002");
put_data(X"0003");
put_data(X"0004");
put_data(X"0005");
put_data(X"0006");
put_data(X"0007");
put_data(X"0008");
wait for 1 ms;
end process;
process
--procedure to read a data word from the FIFO
procedure get_data is
begin
wait until read_clk = '1';
read <= '1';
wait for 8 ns;
read <= '0';
end procedure;
begin
wait for 300 ns;
get_data;
get_data;
wait for 16 ns;
get_data;
get_data;
get_data;
wait for 24 ns;
get_data;
get_data;
get_data;
wait for 1 ms;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_mixed_clock_fifo_regbased of mixed_clock_fifo_regbased_tb is
for TB_ARCHITECTURE
for UUT : mixed_clock_fifo_regbased
use entity work.mixed_clock_fifo_regbased(behavioral);
end for;
end for;
end TESTBENCH_FOR_mixed_clock_fifo_regbased;
|
-- $Id: rlink_mon_sb.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_mon_sb - sim
-- Description: simbus wrapper for rlink monitor
--
-- Dependencies: simbus
-- Test bench: -
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.0 renamed rritb_cpmon_sb -> rlink_mon_sb
-- 2010-05-02 287 1.0.1 use sbcntl_sbf_cpmon def
-- 2007-08-25 75 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.rlinklib.all;
entity rlink_mon_sb is -- simbus wrap for rlink monitor
generic (
DWIDTH : positive := 9; -- data port width (8 or 9)
ENAPIN : integer := sbcntl_sbf_rlmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : in slbit -- rlink: data hold
);
end rlink_mon_sb;
architecture sim of rlink_mon_sb is
signal ENA : slbit := '0';
begin
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
report "assert(ENAPIN in SB_CNTL'range)" severity failure;
ENA <= to_x01(SB_CNTL(ENAPIN));
CPMON : rlink_mon
generic map (
DWIDTH => DWIDTH)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
ENA => ENA,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD
);
end sim;
|
-------------------------------------------------------------------------------
--
-- The Arithmetic Logic Unit (ALU).
-- It contains the ALU core plus the Accumulator and the Temp Reg.
--
-- $Id: alu-c.vhd,v 1.2 2005-06-11 10:08:43 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t48_alu_rtl_c0 of t48_alu is
for rtl
end for;
end t48_alu_rtl_c0;
|
architecture RTL of FIFO is
begin
process
begin
end process;
-- Violations below
process
begin
end process;
process
begin
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (reset_in, clk_in, clock)
begin
if reset_in = '1' then
clock <= '0';
else
if clk_in'event and clk_in='1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, reset_in)
begin
if (reset_in = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
ext_irq <= "0000000" & periph_irq;
gpioa_in(3) <= uart_read;
uart_write <= gpioa_out(2);
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s;
data_write_periph <= data_write;
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (reset_in, clk_in, clock)
begin
if reset_in = '1' then
clock <= '0';
else
if clk_in'event and clk_in='1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, reset_in)
begin
if (reset_in = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
ext_irq <= "0000000" & periph_irq;
gpioa_in(3) <= uart_read;
uart_write <= gpioa_out(2);
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s;
data_write_periph <= data_write;
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2799.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity FOR is
end FOR;
ENTITY c13s09b00x00p99n01i02799ent IS
END c13s09b00x00p99n01i02799ent;
ARCHITECTURE c13s09b00x00p99n01i02799arch OF c13s09b00x00p99n01i02799ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02799 - Reserved word FOR can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02799arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2799.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity FOR is
end FOR;
ENTITY c13s09b00x00p99n01i02799ent IS
END c13s09b00x00p99n01i02799ent;
ARCHITECTURE c13s09b00x00p99n01i02799arch OF c13s09b00x00p99n01i02799ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02799 - Reserved word FOR can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02799arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2799.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity FOR is
end FOR;
ENTITY c13s09b00x00p99n01i02799ent IS
END c13s09b00x00p99n01i02799ent;
ARCHITECTURE c13s09b00x00p99n01i02799arch OF c13s09b00x00p99n01i02799ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02799 - Reserved word FOR can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02799arch;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design HDLC Busmaster
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Some Testbench
-------------------------------------------------------------------------------
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.hdlc_pkg.all;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use std.textio.all;
-------------------------------------------------------------------------------
entity hdlc_busmaster_tb is
end entity hdlc_busmaster_tb;
-------------------------------------------------------------------------------
architecture behavourial of hdlc_busmaster_tb is
-- component ports
signal tb_to_enc : hdlc_enc_in_type := (data => (others => '1'), enable => '0');
signal enc_to_dec : hdlc_enc_out_type := (data => (others => '0'), enable => '0');
signal dec_to_busmaster : hdlc_dec_out_type := (data => (others => '0'), enable => '0');
signal bus_to_master : busmaster_in_type := (data => (others => '0'));
signal master_to_bus : busmaster_out_type := (addr => (others => '0'), data => (others => '0'), re => '0', we => '0');
signal busmaster_to_enc2 : hdlc_enc_in_type := (data => (others => '0'), enable => '0');
signal enc_busy : std_logic := '0';
-- clock
signal Clk : std_logic := '1';
begin -- architecture behavourial
-- component instantiation
DUT_enc : work.hdlc_pkg.hdlc_enc
port map(
din_p => tb_to_enc,
dout_p => enc_to_dec,
busy_p => enc_busy,
clk => clk);
DUT_dec : work.hdlc_pkg.hdlc_dec
port map(
din_p => enc_to_dec,
dout_p => dec_to_busmaster,
clk => clk);
DUT_bus_mst : work.hdlc_pkg.hdlc_busmaster
port map(
din_p => dec_to_busmaster,
dout_p => busmaster_to_enc2,
bus_o => master_to_bus,
bus_i => bus_to_master,
clk => clk);
DUT_reg : work.reg_file_pkg.peripheral_register
generic map(
BASE_ADDRESS => 16#0080#)
port map(
dout_p => open,
din_p => x"1234",
bus_o => bus_to_master,
bus_i => master_to_bus,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
wait until rising_edge(Clk);
wait until rising_edge(Clk);
-- read with good crc
tb_to_enc.data <= "1" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"10";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"80";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"2B"; -- crc correct
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- read with bad crc
tb_to_enc.data <= "1" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"10";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"80";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"2c"; -- crc incorrect
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- write with good crc
tb_to_enc.data <= "1" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"20";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"80";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"0f";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"0f";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"81"; -- good crc
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- write with bad crc
tb_to_enc.data <= "1" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"20";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"80";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"0f";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"0f";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"80"; -- good crc
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait for 10 ms;
end process WaveGen_Proc;
end architecture behavourial;
|
-- Twofish_ecb_tbl_testbench_256bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the TABLES KAT of the twofish cipher with 192 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity tbl_testbench256 is
end tbl_testbench256;
architecture tbl_encryption256_testbench_arch of tbl_testbench256 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched256
port (
odd_in_tk256,
even_in_tk256 : in std_logic_vector(7 downto 0);
in_key_tk256 : in std_logic_vector(255 downto 0);
out_key_up_tk256,
out_key_down_tk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched256
port (
in_key_twk256 : in std_logic_vector(255 downto 0);
out_K0_twk256,
out_K1_twk256,
out_K2_twk256,
out_K3_twk256,
out_K4_twk256,
out_K5_twk256,
out_K6_twk256,
out_K7_twk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_encryption_round256
port (
in1_ter256,
in2_ter256,
in3_ter256,
in4_ter256,
in_Sfirst_ter256,
in_Ssecond_ter256,
in_Sthird_ter256,
in_Sfourth_ter256,
in_key_up_ter256,
in_key_down_ter256 : in std_logic_vector(31 downto 0);
out1_ter256,
out2_ter256,
out3_ter256,
out4_ter256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S256
port (
in_key_ts256 : in std_logic_vector(255 downto 0);
out_Sfirst_ts256,
out_Ssecond_ts256,
out_Sthird_ts256,
out_Sfourth_ts256 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_tbl_testvalues_256bits.txt";
FILE output_file : text is out "twofish_ecb_tbl_256bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 1 to 50) return string is
variable our_text : string (1 to 3) := (others => ' ');
variable hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := (int_number - (int_number mod 100)) / 100;
our_text(1) := digit_to_char(hundreds);
our_text(2) := digit_to_char(tens);
our_text(3) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(255 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
Sfourth,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched256
port map (
in_key_twk256 => twofish_key,
out_K0_twk256 => K0,
out_K1_twk256 => K1,
out_K2_twk256 => K2,
out_K3_twk256 => K3,
out_K4_twk256 => K4,
out_K5_twk256 => K5,
out_K6_twk256 => K6,
out_K7_twk256 => K7
);
-- performing the input whitening XORs
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched256
port map (
odd_in_tk256 => odd_number,
even_in_tk256 => even_number,
in_key_tk256 => twofish_key,
out_key_up_tk256 => key_up,
out_key_down_tk256 => key_down
);
producing_the_Skeys: twofish_S256
port map (
in_key_ts256 => twofish_key,
out_Sfirst_ts256 => Sfirst,
out_Ssecond_ts256 => Ssecond,
out_Sthird_ts256 => Sthird,
out_Sfourth_ts256 => Sfourth
);
the_encryption_circuit: twofish_encryption_round256
port map (
in1_ter256 => to_round(127 downto 96),
in2_ter256 => to_round(95 downto 64),
in3_ter256 => to_round(63 downto 32),
in4_ter256 => to_round(31 downto 0),
in_Sfirst_ter256 => Sfirst,
in_Ssecond_ter256 => Ssecond,
in_Sthird_ter256 => Sthird,
in_Sfourth_ter256 => Sfourth,
in_key_up_ter256 => key_up,
in_key_down_ter256 => key_down,
out1_ter256 => to_encr_reg128(127 downto 96),
out2_ter256 => to_encr_reg128(95 downto 64),
out3_ter256 => to_encr_reg128(63 downto 32),
out4_ter256 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
tbl_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f : line; -- ciphertext from file
variable pt_v , -- plaintext vector
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable key_v : std_logic_vector(255 downto 0); -- key vector input
variable counter : integer range 1 to 50 := 1;
variable round : integer range 0 to 16 := 0;
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
input_data <= pt_v;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00001000"; -- 8
odd_number <= "00001001"; -- 9
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector(((round*2)+8), 8);
odd_number <= conv_std_logic_vector(((round*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note;
counter := counter+1;
hwrite(pt_f,input_data);
hwrite(ct_f,output_data);
hwrite(key_f,key_v);
writeline(output_file,key_f);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
end loop;
assert false report "***** Tables Known Answer Test with 256 bits key size ended succesfully! :) *****" severity failure;
end process tbl_proc;
end tbl_encryption256_testbench_arch;
|
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) ap irq generator
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-14 V0.01 zelenkaj extract from pdi.vhd
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity apIrqGen is
generic (
genOnePdiClkDomain_g : boolean := false
);
port (
--CLOCK DOMAIN PCP
clkA : in std_logic;
rstA : in std_logic;
irqA : in std_logic; --toggle from MAC
enableA : in std_logic; --APIRQ_CONTROL / IRQ_En
modeA : in std_logic; --APIRQ_CONTROL / IRQ_MODE
setA : in std_logic; --APIRQ_CONTROL / IRQ_SET
--CLOCK DOMAIN AP
clkB : in std_logic;
rstB : in std_logic;
ackB : in std_logic; --APIRQ_CONTROL / IRQ_ACK
irqB : out std_logic
);
end entity apIrqGen;
architecture rtl of apIrqGen is
type fsm_t is (wait4event, setIrq, wait4ack);
signal fsm : fsm_t;
signal enable, mode, irq, toggle, set : std_logic;
begin
--everything is done in clkB domain!
theFsm : process(clkB, rstB)
begin
if rstB = '1' then
irqB <= '0';
fsm <= wait4event;
elsif clkB = '1' and clkB'event then
if enable = '1' then
case fsm is
when wait4event =>
if mode = '0' and set = '1' then
fsm <= setIrq;
elsif mode = '1' and irq = '1' then
fsm <= setIrq;
else
fsm <= wait4event;
end if;
when setIrq =>
irqB <= '1';
fsm <= wait4ack;
when wait4ack =>
if ackB = '1' then
irqB <= '0';
fsm <= wait4event;
else
fsm <= wait4ack;
end if;
end case;
else
irqB <= '0';
fsm <= wait4event;
end if;
end if;
end process;
syncEnable : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => enableA,
dout => enable,
clk => clkB,
rst => rstB
);
syncSet : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
dataSrc => setA,
dataDst => set,
clkSrc => clkA,
rstSrc => rstA,
clkDst => clkB,
rstDst => rstB
);
syncMode : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => modeA,
dout => mode,
clk => clkB,
rst => rstB
);
syncToggle : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => irqA,
dout => toggle,
clk => clkB,
rst => rstB
);
toggleEdgeDet : entity work.edgeDet
port map (
din => toggle,
rising => open,
falling => open,
any => irq,
clk => clkB,
rst => rstB
);
end architecture rtl; |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) ap irq generator
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-14 V0.01 zelenkaj extract from pdi.vhd
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity apIrqGen is
generic (
genOnePdiClkDomain_g : boolean := false
);
port (
--CLOCK DOMAIN PCP
clkA : in std_logic;
rstA : in std_logic;
irqA : in std_logic; --toggle from MAC
enableA : in std_logic; --APIRQ_CONTROL / IRQ_En
modeA : in std_logic; --APIRQ_CONTROL / IRQ_MODE
setA : in std_logic; --APIRQ_CONTROL / IRQ_SET
--CLOCK DOMAIN AP
clkB : in std_logic;
rstB : in std_logic;
ackB : in std_logic; --APIRQ_CONTROL / IRQ_ACK
irqB : out std_logic
);
end entity apIrqGen;
architecture rtl of apIrqGen is
type fsm_t is (wait4event, setIrq, wait4ack);
signal fsm : fsm_t;
signal enable, mode, irq, toggle, set : std_logic;
begin
--everything is done in clkB domain!
theFsm : process(clkB, rstB)
begin
if rstB = '1' then
irqB <= '0';
fsm <= wait4event;
elsif clkB = '1' and clkB'event then
if enable = '1' then
case fsm is
when wait4event =>
if mode = '0' and set = '1' then
fsm <= setIrq;
elsif mode = '1' and irq = '1' then
fsm <= setIrq;
else
fsm <= wait4event;
end if;
when setIrq =>
irqB <= '1';
fsm <= wait4ack;
when wait4ack =>
if ackB = '1' then
irqB <= '0';
fsm <= wait4event;
else
fsm <= wait4ack;
end if;
end case;
else
irqB <= '0';
fsm <= wait4event;
end if;
end if;
end process;
syncEnable : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => enableA,
dout => enable,
clk => clkB,
rst => rstB
);
syncSet : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
dataSrc => setA,
dataDst => set,
clkSrc => clkA,
rstSrc => rstA,
clkDst => clkB,
rstDst => rstB
);
syncMode : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => modeA,
dout => mode,
clk => clkB,
rst => rstB
);
syncToggle : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => irqA,
dout => toggle,
clk => clkB,
rst => rstB
);
toggleEdgeDet : entity work.edgeDet
port map (
din => toggle,
rising => open,
falling => open,
any => irq,
clk => clkB,
rst => rstB
);
end architecture rtl; |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) ap irq generator
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-14 V0.01 zelenkaj extract from pdi.vhd
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity apIrqGen is
generic (
genOnePdiClkDomain_g : boolean := false
);
port (
--CLOCK DOMAIN PCP
clkA : in std_logic;
rstA : in std_logic;
irqA : in std_logic; --toggle from MAC
enableA : in std_logic; --APIRQ_CONTROL / IRQ_En
modeA : in std_logic; --APIRQ_CONTROL / IRQ_MODE
setA : in std_logic; --APIRQ_CONTROL / IRQ_SET
--CLOCK DOMAIN AP
clkB : in std_logic;
rstB : in std_logic;
ackB : in std_logic; --APIRQ_CONTROL / IRQ_ACK
irqB : out std_logic
);
end entity apIrqGen;
architecture rtl of apIrqGen is
type fsm_t is (wait4event, setIrq, wait4ack);
signal fsm : fsm_t;
signal enable, mode, irq, toggle, set : std_logic;
begin
--everything is done in clkB domain!
theFsm : process(clkB, rstB)
begin
if rstB = '1' then
irqB <= '0';
fsm <= wait4event;
elsif clkB = '1' and clkB'event then
if enable = '1' then
case fsm is
when wait4event =>
if mode = '0' and set = '1' then
fsm <= setIrq;
elsif mode = '1' and irq = '1' then
fsm <= setIrq;
else
fsm <= wait4event;
end if;
when setIrq =>
irqB <= '1';
fsm <= wait4ack;
when wait4ack =>
if ackB = '1' then
irqB <= '0';
fsm <= wait4event;
else
fsm <= wait4ack;
end if;
end case;
else
irqB <= '0';
fsm <= wait4event;
end if;
end if;
end process;
syncEnable : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => enableA,
dout => enable,
clk => clkB,
rst => rstB
);
syncSet : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
dataSrc => setA,
dataDst => set,
clkSrc => clkA,
rstSrc => rstA,
clkDst => clkB,
rstDst => rstB
);
syncMode : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => modeA,
dout => mode,
clk => clkB,
rst => rstB
);
syncToggle : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => irqA,
dout => toggle,
clk => clkB,
rst => rstB
);
toggleEdgeDet : entity work.edgeDet
port map (
din => toggle,
rising => open,
falling => open,
any => irq,
clk => clkB,
rst => rstB
);
end architecture rtl; |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) ap irq generator
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-14 V0.01 zelenkaj extract from pdi.vhd
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity apIrqGen is
generic (
genOnePdiClkDomain_g : boolean := false
);
port (
--CLOCK DOMAIN PCP
clkA : in std_logic;
rstA : in std_logic;
irqA : in std_logic; --toggle from MAC
enableA : in std_logic; --APIRQ_CONTROL / IRQ_En
modeA : in std_logic; --APIRQ_CONTROL / IRQ_MODE
setA : in std_logic; --APIRQ_CONTROL / IRQ_SET
--CLOCK DOMAIN AP
clkB : in std_logic;
rstB : in std_logic;
ackB : in std_logic; --APIRQ_CONTROL / IRQ_ACK
irqB : out std_logic
);
end entity apIrqGen;
architecture rtl of apIrqGen is
type fsm_t is (wait4event, setIrq, wait4ack);
signal fsm : fsm_t;
signal enable, mode, irq, toggle, set : std_logic;
begin
--everything is done in clkB domain!
theFsm : process(clkB, rstB)
begin
if rstB = '1' then
irqB <= '0';
fsm <= wait4event;
elsif clkB = '1' and clkB'event then
if enable = '1' then
case fsm is
when wait4event =>
if mode = '0' and set = '1' then
fsm <= setIrq;
elsif mode = '1' and irq = '1' then
fsm <= setIrq;
else
fsm <= wait4event;
end if;
when setIrq =>
irqB <= '1';
fsm <= wait4ack;
when wait4ack =>
if ackB = '1' then
irqB <= '0';
fsm <= wait4event;
else
fsm <= wait4ack;
end if;
end case;
else
irqB <= '0';
fsm <= wait4event;
end if;
end if;
end process;
syncEnable : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => enableA,
dout => enable,
clk => clkB,
rst => rstB
);
syncSet : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
dataSrc => setA,
dataDst => set,
clkSrc => clkA,
rstSrc => rstA,
clkDst => clkB,
rstDst => rstB
);
syncMode : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => modeA,
dout => mode,
clk => clkB,
rst => rstB
);
syncToggle : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => irqA,
dout => toggle,
clk => clkB,
rst => rstB
);
toggleEdgeDet : entity work.edgeDet
port map (
din => toggle,
rising => open,
falling => open,
any => irq,
clk => clkB,
rst => rstB
);
end architecture rtl; |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) ap irq generator
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-14 V0.01 zelenkaj extract from pdi.vhd
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity apIrqGen is
generic (
genOnePdiClkDomain_g : boolean := false
);
port (
--CLOCK DOMAIN PCP
clkA : in std_logic;
rstA : in std_logic;
irqA : in std_logic; --toggle from MAC
enableA : in std_logic; --APIRQ_CONTROL / IRQ_En
modeA : in std_logic; --APIRQ_CONTROL / IRQ_MODE
setA : in std_logic; --APIRQ_CONTROL / IRQ_SET
--CLOCK DOMAIN AP
clkB : in std_logic;
rstB : in std_logic;
ackB : in std_logic; --APIRQ_CONTROL / IRQ_ACK
irqB : out std_logic
);
end entity apIrqGen;
architecture rtl of apIrqGen is
type fsm_t is (wait4event, setIrq, wait4ack);
signal fsm : fsm_t;
signal enable, mode, irq, toggle, set : std_logic;
begin
--everything is done in clkB domain!
theFsm : process(clkB, rstB)
begin
if rstB = '1' then
irqB <= '0';
fsm <= wait4event;
elsif clkB = '1' and clkB'event then
if enable = '1' then
case fsm is
when wait4event =>
if mode = '0' and set = '1' then
fsm <= setIrq;
elsif mode = '1' and irq = '1' then
fsm <= setIrq;
else
fsm <= wait4event;
end if;
when setIrq =>
irqB <= '1';
fsm <= wait4ack;
when wait4ack =>
if ackB = '1' then
irqB <= '0';
fsm <= wait4event;
else
fsm <= wait4ack;
end if;
end case;
else
irqB <= '0';
fsm <= wait4event;
end if;
end if;
end process;
syncEnable : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => enableA,
dout => enable,
clk => clkB,
rst => rstB
);
syncSet : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
dataSrc => setA,
dataDst => set,
clkSrc => clkA,
rstSrc => rstA,
clkDst => clkB,
rstDst => rstB
);
syncMode : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => modeA,
dout => mode,
clk => clkB,
rst => rstB
);
syncToggle : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => irqA,
dout => toggle,
clk => clkB,
rst => rstB
);
toggleEdgeDet : entity work.edgeDet
port map (
din => toggle,
rising => open,
falling => open,
any => irq,
clk => clkB,
rst => rstB
);
end architecture rtl; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testbench is
end testbench;
architecture test of testbench is
constant clkPeriod : time := 100 ns;
signal simulationFinished : std_logic := '0';
component Function_Z3fooi is
port
(
clk : in std_logic;
reset : in std_logic;
input1 : in signed(31 downto 0);
output : out signed(31 downto 0);
ready : out std_logic
);
end component;
signal clk : std_logic;
signal reset : std_logic;
signal input1 : signed(31 downto 0);
signal output : signed(31 downto 0);
signal ready : std_logic;
begin
uut : Function_Z3fooi port map
(
clk => clk,
reset => reset,
input1 => input1,
output => output,
ready => ready
);
clkGeneration : process
begin
if not simulationFinished
then
clk <= '1';
wait for clkPeriod / 2;
clk <= '0';
wait for clkPeriod / 2;
else
wait;
end if;
end process clkGeneration;
simulation : process
procedure check
(
constant in1 : in integer;
constant outputExpected : in integer
) is
variable result : integer;
begin
input1 <= to_signed(in1, input1'length);
reset <= '1';
wait until rising_edge(clk);
reset <= '0';
wait until rising_edge(clk) and ready = '1';
result := to_integer(output);
assert result = outputExpected
report
"Unexpected result: " &
"intput1 = " & integer'image(in1) & "; " &
"output = " & integer'image(result) & "; " &
"outputExpected = " & integer'image(outputExpected)
severity failure;
end procedure check;
begin
check(10, 59);
check(0, 49);
simulationFinished <= '1';
wait;
end process simulation;
end architecture test;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FSM is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PC_override : in vl_logic;
PPE_CTRL : in vl_logic_vector(31 downto 0);
PPE_PC_ETC : in vl_logic_vector(31 downto 0);
PPE_FPTR : in vl_logic_vector(31 downto 0);
RAM_DO_A : in vl_logic_vector(31 downto 0);
RAM_ADDRESSES_EQUAL: in vl_logic;
RAM_RD_A : out vl_logic;
RAM_RD_B : out vl_logic;
RAM_RD_B_hold_en: out vl_logic;
RAM_WR_B : out vl_logic;
RAM_ADDR_A : out vl_logic_vector(8 downto 0);
RAM_ADDR_B : out vl_logic_vector(8 downto 0);
PPE_BUSY : out vl_logic;
PPE2SSE_PREADY : in vl_logic;
PPE2SSE_wr : out vl_logic;
PPE2SSE_rd_hold_en: out vl_logic;
PPE2SSE_sel : out vl_logic;
PPE2SSE_en : out vl_logic;
st_filt_curr_st : in vl_logic;
st_filt_next_qual: in vl_logic;
st_filt_0to1_eq : in vl_logic;
st_filt_1to0_eq : in vl_logic;
C_reg_31 : in vl_logic;
CURRENT_ADC_CHAN: in vl_logic_vector(5 downto 0);
ADC_FIFO_EMPTY : in vl_logic;
OTHER_ADC_FIFOS_NOT_EMPTY: in vl_logic;
RR_DISABLE : in vl_logic;
ADC_FIFO_PTR_inc: out vl_logic;
ADC_FIFO_PTR_clr: out vl_logic;
ADC_FIFO_rd : out vl_logic;
ADC0_FIFO_CTRL_reg_move_target: out vl_logic;
ADC1_FIFO_CTRL_reg_move_target: out vl_logic;
ADC2_FIFO_CTRL_reg_move_target: out vl_logic;
st_filt_cnt_clr : out vl_logic;
st_filt_cnt_inc : out vl_logic;
st_filt_st_one : out vl_logic;
st_filt_st_zero : out vl_logic;
PC_init_addr_ld : out vl_logic;
PC_inc : out vl_logic;
PC_ETC_busy : out vl_logic;
SF_busy : out vl_logic;
THR_busy : out vl_logic;
SCRATCH_busy : out vl_logic;
ALU_CTRL_busy : out vl_logic;
A_busy : out vl_logic;
B_busy : out vl_logic;
C_busy : out vl_logic;
D_busy : out vl_logic;
E_busy : out vl_logic;
Ci_busy : out vl_logic;
NegA_busy : out vl_logic;
C2a_busy : out vl_logic;
s2B_busy : out vl_logic;
C2d_busy : out vl_logic;
PPE_FPTR_busy : out vl_logic;
PPE_FLAGS0_busy : out vl_logic;
PPE_FLAGS1_busy : out vl_logic;
PPE_FLAGS2_busy : out vl_logic;
PPE_FLAGS3_busy : out vl_logic;
PPE_SFFLAGS_busy: out vl_logic;
xfer_load_special_active: out vl_logic;
xfer_move_active: out vl_logic;
PPE_CTRL_reg_move_target: out vl_logic;
PC_ETC_reg_move_target: out vl_logic;
SCRATCH_reg_move_target: out vl_logic;
SF_reg_move_target: out vl_logic;
ALU_CTRL_reg_move_target: out vl_logic;
A_reg_move_target: out vl_logic;
B_reg_move_target: out vl_logic;
C_reg_move_target: out vl_logic;
D_reg_move_target: out vl_logic;
E_reg_move_target: out vl_logic;
PPE_FPTR_reg_move_target: out vl_logic;
PPE_FLAGS0_reg_move_target: out vl_logic;
PPE_FLAGS1_reg_move_target: out vl_logic;
PPE_FLAGS2_reg_move_target: out vl_logic;
PPE_FLAGS3_reg_move_target: out vl_logic;
PPE_SFFLAGS_reg_move_target: out vl_logic;
PPE2SSE_PADDR_reg_move_target: out vl_logic;
PPE2SSE_PWDATA_LSB_reg_move_target: out vl_logic;
PPE2SSE_PWDATA_MSB_reg_move_target: out vl_logic;
PPE_PDMA_DATAOUT_reg_move_target: out vl_logic;
PPE_PDMA_DATAOUT_chan_en: out vl_logic;
PPE_PDMA_DATAOUT_raw_en: out vl_logic;
PPE_PDMA_DATAOUT_tag_en: out vl_logic;
PPE_PDMA_CTRL_reg_move_target: out vl_logic;
PPE_FLAG_bit : out vl_logic;
PPE_FLAG_bit_update: out vl_logic;
PPE_thresh_op_load: out vl_logic;
move_from_PPE_CTRL: out vl_logic;
move_from_PC_ETC: out vl_logic;
move_from_SF : out vl_logic;
move_from_SCRATCH: out vl_logic;
move_from_ALU_CTRL: out vl_logic;
move_from_ALU_STATUS: out vl_logic;
move_from_A : out vl_logic;
move_from_B : out vl_logic;
move_from_C : out vl_logic;
move_from_PPE_FPTR: out vl_logic;
move_from_PPE_FLAGS0: out vl_logic;
move_from_PPE_FLAGS1: out vl_logic;
move_from_PPE_FLAGS2: out vl_logic;
move_from_PPE_FLAGS3: out vl_logic;
move_from_PPE_SFFLAGS: out vl_logic;
move_from_ADC0_FIFO_CTRL: out vl_logic;
move_from_ADC0_FIFO_STATUS: out vl_logic;
move_from_ADC0_FIFO_DATA: out vl_logic;
move_from_ADC1_FIFO_CTRL: out vl_logic;
move_from_ADC1_FIFO_STATUS: out vl_logic;
move_from_ADC1_FIFO_DATA: out vl_logic;
move_from_ADC2_FIFO_CTRL: out vl_logic;
move_from_ADC2_FIFO_STATUS: out vl_logic;
move_from_ADC2_FIFO_DATA: out vl_logic;
move_from_ADC_RESULT_LSB: out vl_logic;
move_from_ADC_RESULT_MSB: out vl_logic;
move_from_PPE2SSE_PRDATA: out vl_logic;
move_from_RAM_DO_A_31_0: out vl_logic;
move_from_RAM_DO_A_23_0_LSB: out vl_logic;
move_from_RAM_DO_A_23_0_MSB: out vl_logic;
move_from_RAM_DO_A_15_0_MSB: out vl_logic;
move_from_RAM_DO_B_31_0: out vl_logic;
RAM_DI_B_31_0_move_target: out vl_logic;
RAM_DI_B_23_0_move_target: out vl_logic;
RAM_DI_B_15_0_move_target: out vl_logic;
keep_bits_31_24 : out vl_logic;
keep_bits_7_0 : out vl_logic;
Ci_reg_set : out vl_logic;
NegA_reg_set : out vl_logic;
A_reg_hi_set : out vl_logic;
A_reg_lo_set : out vl_logic;
B_reg_hi_set : out vl_logic;
B_reg_lo_set : out vl_logic;
C_reg_hi_set : out vl_logic;
C_reg_lo_set : out vl_logic;
A_reg_hi_clr : out vl_logic;
A_reg_lo_clr : out vl_logic;
B_reg_hi_clr : out vl_logic;
B_reg_lo_clr : out vl_logic;
C_reg_hi_clr : out vl_logic;
C_reg_lo_clr : out vl_logic
);
end F2DSS_ACE_PPE_FSM;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FSM is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PC_override : in vl_logic;
PPE_CTRL : in vl_logic_vector(31 downto 0);
PPE_PC_ETC : in vl_logic_vector(31 downto 0);
PPE_FPTR : in vl_logic_vector(31 downto 0);
RAM_DO_A : in vl_logic_vector(31 downto 0);
RAM_ADDRESSES_EQUAL: in vl_logic;
RAM_RD_A : out vl_logic;
RAM_RD_B : out vl_logic;
RAM_RD_B_hold_en: out vl_logic;
RAM_WR_B : out vl_logic;
RAM_ADDR_A : out vl_logic_vector(8 downto 0);
RAM_ADDR_B : out vl_logic_vector(8 downto 0);
PPE_BUSY : out vl_logic;
PPE2SSE_PREADY : in vl_logic;
PPE2SSE_wr : out vl_logic;
PPE2SSE_rd_hold_en: out vl_logic;
PPE2SSE_sel : out vl_logic;
PPE2SSE_en : out vl_logic;
st_filt_curr_st : in vl_logic;
st_filt_next_qual: in vl_logic;
st_filt_0to1_eq : in vl_logic;
st_filt_1to0_eq : in vl_logic;
C_reg_31 : in vl_logic;
CURRENT_ADC_CHAN: in vl_logic_vector(5 downto 0);
ADC_FIFO_EMPTY : in vl_logic;
OTHER_ADC_FIFOS_NOT_EMPTY: in vl_logic;
RR_DISABLE : in vl_logic;
ADC_FIFO_PTR_inc: out vl_logic;
ADC_FIFO_PTR_clr: out vl_logic;
ADC_FIFO_rd : out vl_logic;
ADC0_FIFO_CTRL_reg_move_target: out vl_logic;
ADC1_FIFO_CTRL_reg_move_target: out vl_logic;
ADC2_FIFO_CTRL_reg_move_target: out vl_logic;
st_filt_cnt_clr : out vl_logic;
st_filt_cnt_inc : out vl_logic;
st_filt_st_one : out vl_logic;
st_filt_st_zero : out vl_logic;
PC_init_addr_ld : out vl_logic;
PC_inc : out vl_logic;
PC_ETC_busy : out vl_logic;
SF_busy : out vl_logic;
THR_busy : out vl_logic;
SCRATCH_busy : out vl_logic;
ALU_CTRL_busy : out vl_logic;
A_busy : out vl_logic;
B_busy : out vl_logic;
C_busy : out vl_logic;
D_busy : out vl_logic;
E_busy : out vl_logic;
Ci_busy : out vl_logic;
NegA_busy : out vl_logic;
C2a_busy : out vl_logic;
s2B_busy : out vl_logic;
C2d_busy : out vl_logic;
PPE_FPTR_busy : out vl_logic;
PPE_FLAGS0_busy : out vl_logic;
PPE_FLAGS1_busy : out vl_logic;
PPE_FLAGS2_busy : out vl_logic;
PPE_FLAGS3_busy : out vl_logic;
PPE_SFFLAGS_busy: out vl_logic;
xfer_load_special_active: out vl_logic;
xfer_move_active: out vl_logic;
PPE_CTRL_reg_move_target: out vl_logic;
PC_ETC_reg_move_target: out vl_logic;
SCRATCH_reg_move_target: out vl_logic;
SF_reg_move_target: out vl_logic;
ALU_CTRL_reg_move_target: out vl_logic;
A_reg_move_target: out vl_logic;
B_reg_move_target: out vl_logic;
C_reg_move_target: out vl_logic;
D_reg_move_target: out vl_logic;
E_reg_move_target: out vl_logic;
PPE_FPTR_reg_move_target: out vl_logic;
PPE_FLAGS0_reg_move_target: out vl_logic;
PPE_FLAGS1_reg_move_target: out vl_logic;
PPE_FLAGS2_reg_move_target: out vl_logic;
PPE_FLAGS3_reg_move_target: out vl_logic;
PPE_SFFLAGS_reg_move_target: out vl_logic;
PPE2SSE_PADDR_reg_move_target: out vl_logic;
PPE2SSE_PWDATA_LSB_reg_move_target: out vl_logic;
PPE2SSE_PWDATA_MSB_reg_move_target: out vl_logic;
PPE_PDMA_DATAOUT_reg_move_target: out vl_logic;
PPE_PDMA_DATAOUT_chan_en: out vl_logic;
PPE_PDMA_DATAOUT_raw_en: out vl_logic;
PPE_PDMA_DATAOUT_tag_en: out vl_logic;
PPE_PDMA_CTRL_reg_move_target: out vl_logic;
PPE_FLAG_bit : out vl_logic;
PPE_FLAG_bit_update: out vl_logic;
PPE_thresh_op_load: out vl_logic;
move_from_PPE_CTRL: out vl_logic;
move_from_PC_ETC: out vl_logic;
move_from_SF : out vl_logic;
move_from_SCRATCH: out vl_logic;
move_from_ALU_CTRL: out vl_logic;
move_from_ALU_STATUS: out vl_logic;
move_from_A : out vl_logic;
move_from_B : out vl_logic;
move_from_C : out vl_logic;
move_from_PPE_FPTR: out vl_logic;
move_from_PPE_FLAGS0: out vl_logic;
move_from_PPE_FLAGS1: out vl_logic;
move_from_PPE_FLAGS2: out vl_logic;
move_from_PPE_FLAGS3: out vl_logic;
move_from_PPE_SFFLAGS: out vl_logic;
move_from_ADC0_FIFO_CTRL: out vl_logic;
move_from_ADC0_FIFO_STATUS: out vl_logic;
move_from_ADC0_FIFO_DATA: out vl_logic;
move_from_ADC1_FIFO_CTRL: out vl_logic;
move_from_ADC1_FIFO_STATUS: out vl_logic;
move_from_ADC1_FIFO_DATA: out vl_logic;
move_from_ADC2_FIFO_CTRL: out vl_logic;
move_from_ADC2_FIFO_STATUS: out vl_logic;
move_from_ADC2_FIFO_DATA: out vl_logic;
move_from_ADC_RESULT_LSB: out vl_logic;
move_from_ADC_RESULT_MSB: out vl_logic;
move_from_PPE2SSE_PRDATA: out vl_logic;
move_from_RAM_DO_A_31_0: out vl_logic;
move_from_RAM_DO_A_23_0_LSB: out vl_logic;
move_from_RAM_DO_A_23_0_MSB: out vl_logic;
move_from_RAM_DO_A_15_0_MSB: out vl_logic;
move_from_RAM_DO_B_31_0: out vl_logic;
RAM_DI_B_31_0_move_target: out vl_logic;
RAM_DI_B_23_0_move_target: out vl_logic;
RAM_DI_B_15_0_move_target: out vl_logic;
keep_bits_31_24 : out vl_logic;
keep_bits_7_0 : out vl_logic;
Ci_reg_set : out vl_logic;
NegA_reg_set : out vl_logic;
A_reg_hi_set : out vl_logic;
A_reg_lo_set : out vl_logic;
B_reg_hi_set : out vl_logic;
B_reg_lo_set : out vl_logic;
C_reg_hi_set : out vl_logic;
C_reg_lo_set : out vl_logic;
A_reg_hi_clr : out vl_logic;
A_reg_lo_clr : out vl_logic;
B_reg_hi_clr : out vl_logic;
B_reg_lo_clr : out vl_logic;
C_reg_hi_clr : out vl_logic;
C_reg_lo_clr : out vl_logic
);
end F2DSS_ACE_PPE_FSM;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FSM is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PC_override : in vl_logic;
PPE_CTRL : in vl_logic_vector(31 downto 0);
PPE_PC_ETC : in vl_logic_vector(31 downto 0);
PPE_FPTR : in vl_logic_vector(31 downto 0);
RAM_DO_A : in vl_logic_vector(31 downto 0);
RAM_ADDRESSES_EQUAL: in vl_logic;
RAM_RD_A : out vl_logic;
RAM_RD_B : out vl_logic;
RAM_RD_B_hold_en: out vl_logic;
RAM_WR_B : out vl_logic;
RAM_ADDR_A : out vl_logic_vector(8 downto 0);
RAM_ADDR_B : out vl_logic_vector(8 downto 0);
PPE_BUSY : out vl_logic;
PPE2SSE_PREADY : in vl_logic;
PPE2SSE_wr : out vl_logic;
PPE2SSE_rd_hold_en: out vl_logic;
PPE2SSE_sel : out vl_logic;
PPE2SSE_en : out vl_logic;
st_filt_curr_st : in vl_logic;
st_filt_next_qual: in vl_logic;
st_filt_0to1_eq : in vl_logic;
st_filt_1to0_eq : in vl_logic;
C_reg_31 : in vl_logic;
CURRENT_ADC_CHAN: in vl_logic_vector(5 downto 0);
ADC_FIFO_EMPTY : in vl_logic;
OTHER_ADC_FIFOS_NOT_EMPTY: in vl_logic;
RR_DISABLE : in vl_logic;
ADC_FIFO_PTR_inc: out vl_logic;
ADC_FIFO_PTR_clr: out vl_logic;
ADC_FIFO_rd : out vl_logic;
ADC0_FIFO_CTRL_reg_move_target: out vl_logic;
ADC1_FIFO_CTRL_reg_move_target: out vl_logic;
ADC2_FIFO_CTRL_reg_move_target: out vl_logic;
st_filt_cnt_clr : out vl_logic;
st_filt_cnt_inc : out vl_logic;
st_filt_st_one : out vl_logic;
st_filt_st_zero : out vl_logic;
PC_init_addr_ld : out vl_logic;
PC_inc : out vl_logic;
PC_ETC_busy : out vl_logic;
SF_busy : out vl_logic;
THR_busy : out vl_logic;
SCRATCH_busy : out vl_logic;
ALU_CTRL_busy : out vl_logic;
A_busy : out vl_logic;
B_busy : out vl_logic;
C_busy : out vl_logic;
D_busy : out vl_logic;
E_busy : out vl_logic;
Ci_busy : out vl_logic;
NegA_busy : out vl_logic;
C2a_busy : out vl_logic;
s2B_busy : out vl_logic;
C2d_busy : out vl_logic;
PPE_FPTR_busy : out vl_logic;
PPE_FLAGS0_busy : out vl_logic;
PPE_FLAGS1_busy : out vl_logic;
PPE_FLAGS2_busy : out vl_logic;
PPE_FLAGS3_busy : out vl_logic;
PPE_SFFLAGS_busy: out vl_logic;
xfer_load_special_active: out vl_logic;
xfer_move_active: out vl_logic;
PPE_CTRL_reg_move_target: out vl_logic;
PC_ETC_reg_move_target: out vl_logic;
SCRATCH_reg_move_target: out vl_logic;
SF_reg_move_target: out vl_logic;
ALU_CTRL_reg_move_target: out vl_logic;
A_reg_move_target: out vl_logic;
B_reg_move_target: out vl_logic;
C_reg_move_target: out vl_logic;
D_reg_move_target: out vl_logic;
E_reg_move_target: out vl_logic;
PPE_FPTR_reg_move_target: out vl_logic;
PPE_FLAGS0_reg_move_target: out vl_logic;
PPE_FLAGS1_reg_move_target: out vl_logic;
PPE_FLAGS2_reg_move_target: out vl_logic;
PPE_FLAGS3_reg_move_target: out vl_logic;
PPE_SFFLAGS_reg_move_target: out vl_logic;
PPE2SSE_PADDR_reg_move_target: out vl_logic;
PPE2SSE_PWDATA_LSB_reg_move_target: out vl_logic;
PPE2SSE_PWDATA_MSB_reg_move_target: out vl_logic;
PPE_PDMA_DATAOUT_reg_move_target: out vl_logic;
PPE_PDMA_DATAOUT_chan_en: out vl_logic;
PPE_PDMA_DATAOUT_raw_en: out vl_logic;
PPE_PDMA_DATAOUT_tag_en: out vl_logic;
PPE_PDMA_CTRL_reg_move_target: out vl_logic;
PPE_FLAG_bit : out vl_logic;
PPE_FLAG_bit_update: out vl_logic;
PPE_thresh_op_load: out vl_logic;
move_from_PPE_CTRL: out vl_logic;
move_from_PC_ETC: out vl_logic;
move_from_SF : out vl_logic;
move_from_SCRATCH: out vl_logic;
move_from_ALU_CTRL: out vl_logic;
move_from_ALU_STATUS: out vl_logic;
move_from_A : out vl_logic;
move_from_B : out vl_logic;
move_from_C : out vl_logic;
move_from_PPE_FPTR: out vl_logic;
move_from_PPE_FLAGS0: out vl_logic;
move_from_PPE_FLAGS1: out vl_logic;
move_from_PPE_FLAGS2: out vl_logic;
move_from_PPE_FLAGS3: out vl_logic;
move_from_PPE_SFFLAGS: out vl_logic;
move_from_ADC0_FIFO_CTRL: out vl_logic;
move_from_ADC0_FIFO_STATUS: out vl_logic;
move_from_ADC0_FIFO_DATA: out vl_logic;
move_from_ADC1_FIFO_CTRL: out vl_logic;
move_from_ADC1_FIFO_STATUS: out vl_logic;
move_from_ADC1_FIFO_DATA: out vl_logic;
move_from_ADC2_FIFO_CTRL: out vl_logic;
move_from_ADC2_FIFO_STATUS: out vl_logic;
move_from_ADC2_FIFO_DATA: out vl_logic;
move_from_ADC_RESULT_LSB: out vl_logic;
move_from_ADC_RESULT_MSB: out vl_logic;
move_from_PPE2SSE_PRDATA: out vl_logic;
move_from_RAM_DO_A_31_0: out vl_logic;
move_from_RAM_DO_A_23_0_LSB: out vl_logic;
move_from_RAM_DO_A_23_0_MSB: out vl_logic;
move_from_RAM_DO_A_15_0_MSB: out vl_logic;
move_from_RAM_DO_B_31_0: out vl_logic;
RAM_DI_B_31_0_move_target: out vl_logic;
RAM_DI_B_23_0_move_target: out vl_logic;
RAM_DI_B_15_0_move_target: out vl_logic;
keep_bits_31_24 : out vl_logic;
keep_bits_7_0 : out vl_logic;
Ci_reg_set : out vl_logic;
NegA_reg_set : out vl_logic;
A_reg_hi_set : out vl_logic;
A_reg_lo_set : out vl_logic;
B_reg_hi_set : out vl_logic;
B_reg_lo_set : out vl_logic;
C_reg_hi_set : out vl_logic;
C_reg_lo_set : out vl_logic;
A_reg_hi_clr : out vl_logic;
A_reg_lo_clr : out vl_logic;
B_reg_hi_clr : out vl_logic;
B_reg_lo_clr : out vl_logic;
C_reg_hi_clr : out vl_logic;
C_reg_lo_clr : out vl_logic
);
end F2DSS_ACE_PPE_FSM;
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