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-------------------------------------------------------------------------------
-- Title : Testbench for design "beacon_robot"
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.hdlc_pkg.all;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.fifo_sync_pkg.all;
use work.reset_pkg.all;
use work.uart_pkg.all;
use work.utils_pkg.all;
use work.uart_tb_pkg.all;
-------------------------------------------------------------------------------
entity toplevel_tb is
end toplevel_tb;
-------------------------------------------------------------------------------
architecture tb of toplevel_tb is
signal clk : std_logic := '0';
signal rsrx : std_logic := '1';
signal rstx : std_logic := '1';
signal led : std_logic_vector(7 downto 0);
signal sw : std_logic_vector(7 downto 0);
signal so : std_logic_vector(1 downto 0);
signal do : std_logic_vector(1 downto 0);
signal si : std_logic_vector(1 downto 0);
signal di : std_logic_vector(1 downto 0);
begin
toplevel_1 : entity work.toplevel
generic map (
RESET_IMPL => sync)
port map (
so => so,
do => do,
si => si,
di => di,
rsrx => rsrx,
rstx => rstx,
led => led,
sw => sw,
clk => clk);
-- clock generation
Clk <= not Clk after 10 ns;
-- loopback
si(0) <= so(1);
di(0) <= do(1);
si(1) <= so(0);
di(1) <= do(0);
process
begin
wait for 25 ns;
--reset_n <= '0';
wait for 5 us;
-- enable port 0
uart_transmit(rsrx, "0" & x"7e", 250000);
uart_transmit(rsrx, "0" & x"20", 250000);
uart_transmit(rsrx, "0" & x"00", 250000);
uart_transmit(rsrx, "0" & x"12", 250000);
uart_transmit(rsrx, "0" & x"04", 250000);
uart_transmit(rsrx, "0" & x"03", 250000);
uart_transmit(rsrx, "0" & x"4d", 250000); -- crc good
wait for 100 us;
-- enable port 1
uart_transmit(rsrx, "0" & x"7e", 250000);
uart_transmit(rsrx, "0" & x"20", 250000);
uart_transmit(rsrx, "0" & x"00", 250000);
uart_transmit(rsrx, "0" & x"22", 250000);
uart_transmit(rsrx, "0" & x"04", 250000);
uart_transmit(rsrx, "0" & x"03", 250000);
uart_transmit(rsrx, "0" & x"ac", 250000); -- crc good
wait for 100 us;
-- read 0x0011 - port 0 status
uart_transmit(rsrx, "0" & x"7e", 250000);
uart_transmit(rsrx, "0" & x"10", 250000);
uart_transmit(rsrx, "0" & x"00", 250000);
uart_transmit(rsrx, "0" & x"11", 250000);
uart_transmit(rsrx, "0" & x"d5", 250000); -- crc good
wait for 100 us;
-- send 0x41 over port 1
uart_transmit(rsrx, "0" & x"7e", 250000);
uart_transmit(rsrx, "0" & x"20", 250000);
uart_transmit(rsrx, "0" & x"00", 250000);
uart_transmit(rsrx, "0" & x"20", 250000);
uart_transmit(rsrx, "0" & x"00", 250000);
uart_transmit(rsrx, "0" & x"41", 250000);
uart_transmit(rsrx, "0" & x"e7", 250000); -- crc good
wait for 100 us;
-- send EOP over port 1
uart_transmit(rsrx, "0" & x"7e", 250000);
uart_transmit(rsrx, "0" & x"20", 250000);
uart_transmit(rsrx, "0" & x"00", 250000);
uart_transmit(rsrx, "0" & x"20", 250000);
uart_transmit(rsrx, "0" & x"01", 250000);
uart_transmit(rsrx, "0" & x"00", 250000);
uart_transmit(rsrx, "0" & x"32", 250000); -- crc good
wait for 100 us;
-- read data from port 0 (0x0010)
uart_transmit(rsrx, "0" & x"7e", 250000);
uart_transmit(rsrx, "0" & x"10", 250000);
uart_transmit(rsrx, "0" & x"00", 250000);
uart_transmit(rsrx, "0" & x"10", 250000);
uart_transmit(rsrx, "0" & x"d2", 250000); -- crc good
wait for 100 us;
-- read data from port 0 (0x0010)
uart_transmit(rsrx, "0" & x"7e", 250000);
uart_transmit(rsrx, "0" & x"10", 250000);
uart_transmit(rsrx, "0" & x"00", 250000);
uart_transmit(rsrx, "0" & x"10", 250000);
uart_transmit(rsrx, "0" & x"d2", 250000); -- crc good
wait for 100 ms;
end process;
end tb;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memory_control is
port (clk : in std_logic;
rst : in std_logic;
cpu_vid : in std_logic;
cpu_data : in std_logic_vector(15 downto 0);
cpu_addr : in std_logic_vector(22 downto 0);
cpu_valid : in std_logic;
vid_data : out std_logic_vector(15 downto 0);
vid_addr : in std_logic_vector(22 downto 0);
RAM_addr : out std_logic_vector(22 downto 0);
RAM_data_bus : inout std_logic_vector(15 downto 0);
RAM_oe : out std_logic;
RAM_we : out std_logic;
RAM_ub : out std_logic;
RAM_lb : out std_logic;
RAM_ce : out std_logic);
end memory_control;
architecture behavioral of memory_control is
type state_type is (start, check_cpu_vid, check_cpu_valid, write_cpu_data_setup, write_cpu_data_write);
signal state, next_state : state_type;
signal latency_cnt : std_logic_vector(3 downto 0);
signal RAM_data_bus_in : std_logic_vector(15 downto 0);
signal RAM_data_bus_out : std_logic_vector(15 downto 0);
signal wr_RAM_oe : std_logic;
signal wr_RAM_we : std_logic;
signal wr_RAM_ce : std_logic;
begin
next_state_sync: process (clk, rst) is
begin
if rst = '1' then
state <= start;
latency_cnt <= "0001";
else
state <= next_state;
if state = next_state then
latency_cnt <= latency_cnt + 1;
else
latency_cnt <= "0001";
end if;
end if;
end process;
next_state_logic: process (state, cpu_vid, cpu_valid, vid_addr, latency_cnt) is
begin
case (state) is
when start =>
next_state <= check_cpu_vid;
when check_cpu_vid =>
if cpu_vid = '0' then
next_state <= check_cpu_vid; --Stay here if it's just reading memory
else
next_state <= check_cpu_valid; --Else, go write some data
end if;
when check_cpu_valid =>
if cpu_valid = '0' then
next_state <= check_cpu_valid;
else
next_state <= write_cpu_data_setup;
end if;
when write_cpu_data_setup =>
if latency_cnt > 2 then
next_state <= write_cpu_data_write;
else
next_state <= write_cpu_data_setup;
end if;
when write_cpu_data_write =>
if latency_cnt > 2 then
next_state <= check_cpu_vid;
else
next_state <= write_cpu_data_write;
end if;
end case;
end process;
in_state : process (state, cpu_vid, RAM_data_bus_in) is
begin
RAM_data_bus_out <= (others => '0');
wr_RAM_ce <= '1';
wr_RAM_oe <= '1';
wr_RAM_we <= '1';
case (state) is
when start =>
--Reset/default state for all signals
when check_cpu_vid =>
--Taken care of in defaults and MUX for read signals
when check_cpu_valid =>
--Default signals, wating for data to be valid from the CPU
when write_cpu_data_setup =>
wr_RAM_ce <= '0';
wr_RAM_oe <= '1';
wr_RAM_we <= '0';
when write_cpu_data_write =>
wr_RAM_ce <= '0';
wr_RAM_oe <= '1';
wr_RAM_we <= '0';
RAM_data_bus_out <= cpu_data;
end case;
end process;
RAM_data_bus <= RAM_data_bus_out when cpu_vid = '1' else (others => 'Z');
RAM_data_bus_in <= RAM_data_bus;
--MUX FOR SIGNALS (LB/UB ALWAYS) (controlled by cpu/vid)
RAM_sigs_MUX: process (wr_RAM_ce, wr_RAM_oe, wr_RAM_we, cpu_vid) is
begin
--Always zero
RAM_lb <= '0';
RAM_ub <= '0';
--Defaults
RAM_ce <= '1';
RAM_oe <= '1';
RAM_we <= '1';
if cpu_vid = '0' then --Video control, read memory
RAM_ce <= '0';
RAM_oe <= '0';
RAM_we <= '1';
RAM_addr <= vid_addr;
else
RAM_ce <= wr_RAM_ce;
RAM_oe <= wr_RAM_oe;
RAM_we <= wr_RAM_we;
RAM_addr <= cpu_addr;
end if;
end process;
end behavioral; |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync_reset:1.0
-- IP Revision: 25
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_reset_0_0 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_reset_0_0;
ARCHITECTURE system_vga_sync_reset_0_0_arch OF system_vga_sync_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync_reset IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync_reset
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk => clk,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_reset_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync_reset:1.0
-- IP Revision: 25
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_reset_0_0 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_reset_0_0;
ARCHITECTURE system_vga_sync_reset_0_0_arch OF system_vga_sync_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync_reset IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync_reset
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk => clk,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_reset_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync_reset:1.0
-- IP Revision: 25
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_reset_0_0 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_reset_0_0;
ARCHITECTURE system_vga_sync_reset_0_0_arch OF system_vga_sync_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync_reset IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync_reset
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk => clk,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_reset_0_0_arch;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:31:35 09/02/2015
-- Design Name:
-- Module Name: D:/ProySisDigAva/P05_DM74LS151/DM74LS151_tb.vhd
-- Project Name: P05_DM74LS151
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DM74LS151
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY DM74LS151_tb IS
END DM74LS151_tb;
ARCHITECTURE behavior OF DM74LS151_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DM74LS151
PORT(
C : IN std_logic;
B : IN std_logic;
A : IN std_logic;
D : IN std_logic_vector(7 downto 0);
Strobe : IN std_logic;
Y : OUT std_logic;
W : OUT std_logic
);
END COMPONENT;
--Inputs
signal C : std_logic := '0';
signal B : std_logic := '0';
signal A : std_logic := '0';
signal D : std_logic_vector(7 downto 0) := (others => '0');
signal Strobe : std_logic := '0';
--Outputs
signal Y : std_logic;
signal W : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DM74LS151 PORT MAP (
C => C,
B => B,
A => A,
D => D,
Strobe => Strobe,
Y => Y,
W => W
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- wait for <clock>_period*10;
-- insert stimulus here
Strobe <= '1';
wait for 100 ns;
Strobe <= '0'; D <= "10010001";
C <= '0'; B <= '0'; A <= '0';
wait for 100 ns;
C <= '0'; B <= '0'; A <= '1';
wait for 100 ns;
C <= '0'; B <= '1'; A <= '0';
wait for 100 ns;
C <= '0'; B <= '1'; A <= '1';
wait for 100 ns;
C <= '1'; B <= '0'; A <= '0';
wait for 100 ns;
C <= '1'; B <= '0'; A <= '1';
wait for 100 ns;
C <= '1'; B <= '1'; A <= '0';
wait for 100 ns;
C <= '1'; B <= '1'; A <= '1';
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:31:35 09/02/2015
-- Design Name:
-- Module Name: D:/ProySisDigAva/P05_DM74LS151/DM74LS151_tb.vhd
-- Project Name: P05_DM74LS151
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DM74LS151
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY DM74LS151_tb IS
END DM74LS151_tb;
ARCHITECTURE behavior OF DM74LS151_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DM74LS151
PORT(
C : IN std_logic;
B : IN std_logic;
A : IN std_logic;
D : IN std_logic_vector(7 downto 0);
Strobe : IN std_logic;
Y : OUT std_logic;
W : OUT std_logic
);
END COMPONENT;
--Inputs
signal C : std_logic := '0';
signal B : std_logic := '0';
signal A : std_logic := '0';
signal D : std_logic_vector(7 downto 0) := (others => '0');
signal Strobe : std_logic := '0';
--Outputs
signal Y : std_logic;
signal W : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DM74LS151 PORT MAP (
C => C,
B => B,
A => A,
D => D,
Strobe => Strobe,
Y => Y,
W => W
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- wait for <clock>_period*10;
-- insert stimulus here
Strobe <= '1';
wait for 100 ns;
Strobe <= '0'; D <= "10010001";
C <= '0'; B <= '0'; A <= '0';
wait for 100 ns;
C <= '0'; B <= '0'; A <= '1';
wait for 100 ns;
C <= '0'; B <= '1'; A <= '0';
wait for 100 ns;
C <= '0'; B <= '1'; A <= '1';
wait for 100 ns;
C <= '1'; B <= '0'; A <= '0';
wait for 100 ns;
C <= '1'; B <= '0'; A <= '1';
wait for 100 ns;
C <= '1'; B <= '1'; A <= '0';
wait for 100 ns;
C <= '1'; B <= '1'; A <= '1';
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 19:29:54 05/09/2016
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lcd_driver is
generic ( NBITS : natural := 21; -- counter bit size
clk_freq : natural := 50000000; -- frequency of clk (50MHz) in hz
wait_init : natural := 40000; -- wait 40ms
wait_between : natural := 37; -- wait 37us
wait_pause : natural := 1520); -- wait 1.52ms
Port ( clk : in STD_LOGIC; -- Clock Input
reset : in STD_LOGIC; -- High active, async reset
data : in STD_LOGIC_VECTOR (7 downto 0); -- either one ascii char (8bit) or new cursor position/adress
new_character : in STD_LOGIC; -- a new character is available on the data bus
new_pos : in STD_LOGIC; -- a new cursor position is available on the data bus
busy : out STD_LOGIC; -- output which signals that the driver/lcd is currently busy
lcd_db : out STD_LOGIC_VECTOR (7 downto 0); -- lcd output: databus
lcd_en : out STD_LOGIC; -- lcd output: enable
lcd_rs : out STD_LOGIC); -- lcd output: register select
end lcd_driver;
architecture Behavioral of lcd_driver is
-- type definitions
type display_state is (
INIT, -- initialization, wait for 40ms to pass
SEND_FS1, -- send the function set
SEND_FS2, -- send the function set
SEND_SD, -- send the display ON/OFF control
SEND_CD, -- send a clear
SEND_ES, -- send entry mode set
WAITING1, -- wait and toggle lcd_en
WAITING2, -- wait and toggle lcd_en
WAITING3, -- wait and toggle lcd_en
DONE); -- initialization done
-- signals
signal cur_state : display_state := INIT; -- cur_state register
signal next_state : display_state := INIT; -- next_state register
signal ret_state : display_state := INIT; -- ret_state register
signal next_ret_state : display_state := INIT; -- next_ret_state register
signal cur_counter : unsigned(NBITS-1 downto 0) := (others => '0'); -- current counter
signal next_counter : unsigned(NBITS-1 downto 0) := (others => '0'); -- next current counter
signal ret_counter : unsigned(NBITS-1 downto 0) := (others => '0'); -- return current counter
signal next_ret_counter : unsigned(NBITS-1 downto 0) := (others => '0');
signal next_lcd_db : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); -- next lcd databus
signal next_lcd_en : STD_LOGIC := '0'; -- next lcd enable
signal next_lcd_rs : STD_LOGIC := '0'; -- next lcd register select
signal cur_lcd_db : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); -- next lcd databus
signal cur_lcd_en : STD_LOGIC := '0'; -- next lcd enable
signal cur_lcd_rs : STD_LOGIC := '0'; -- next lcd register select
-- constants
constant INIT_COUNT : natural := clk_freq / (1000000 / wait_init); -- number of clock cycles for 40ms
constant PAUSE_COUNT : natural := clk_freq / (1000000 / wait_between); -- number of clock cycles for 37us
constant CLEAR_DISPLAY_COUNT : natural := clk_freq / (1000000 / wait_pause); -- number of clock cycles for 1.52ms
begin
-- purpose : state register
-- type : sequential
-- inputs : clk, reset, next_state
-- outputs : cur_state
REGS: process (clk, reset) is
begin
if(reset = '1') then -- asynchronous reset
cur_state <= INIT;
ret_state <= INIT;
cur_counter <= (others => '0');
ret_counter <= (others => '0');
cur_lcd_db <= (others => '0');
cur_lcd_en <= '0';
cur_lcd_rs <= '0';
elsif rising_edge(clk) then -- synchronous on clk
cur_state <= next_state;
ret_state <= next_ret_state;
cur_counter <= next_counter;
ret_counter <= next_ret_counter;
cur_lcd_db <= next_lcd_db;
cur_lcd_en <= next_lcd_en;
cur_lcd_rs <= next_lcd_rs;
end if;
end process REGS;
-- purpose : Finite state machine next state logic
-- type : sequential
-- inputs : clk, cur_state
-- outputs : none
NSL: process(clk, cur_state, cur_counter, cur_lcd_db, cur_lcd_en, cur_lcd_rs, ret_state, ret_counter, new_character,data,new_pos) is
begin
next_counter <= cur_counter + 1; -- increment counter
next_state <= cur_state;
next_lcd_db <= cur_lcd_db;
next_lcd_en <= cur_lcd_en;
next_lcd_rs <= cur_lcd_rs;
next_ret_state <= ret_state;
next_ret_counter <= ret_counter;
case cur_state is
when INIT => -- switch on current state
next_lcd_db <= "00000000";
next_lcd_en <= '0';
next_lcd_rs <= '0';
next_counter <= (others => '0');
next_ret_state <= SEND_FS1;
next_ret_counter <= to_unsigned(INIT_COUNT, NBITS);
next_state <= WAITING2;
when SEND_FS1 => -- first function set
next_lcd_db <= "00111000";
next_lcd_en <= '1';
next_lcd_rs <= '0';
next_counter <= (others => '0');
next_ret_state <= SEND_FS2;
next_ret_counter <= to_unsigned(PAUSE_COUNT, NBITS);
next_state <= WAITING1;
when SEND_FS2 => -- second function set
next_lcd_db <= "00111000";
next_lcd_en <= '1';
next_lcd_rs <= '0';
next_counter <= (others => '0');
next_ret_state <= SEND_SD;
next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);
next_state <= WAITING1;
when SEND_SD => -- display ON/OFF setting
next_lcd_db <= "00001110";
next_lcd_en <= '1';
next_lcd_rs <= '0';
next_counter <= (others => '0');
next_ret_state <= SEND_CD;
next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);
next_state <= WAITING1;
when SEND_CD => -- clear display
next_lcd_db <= "00000001";
next_lcd_en <= '1';
next_lcd_rs <= '0';
next_counter <= (others => '0');
next_ret_state <= SEND_ES;
next_ret_counter <= to_unsigned(CLEAR_DISPLAY_COUNT,NBITS);
next_state <= WAITING3;
when SEND_ES => -- entry set mode
next_lcd_db <= "00000110";
next_lcd_en <= '1';
next_lcd_rs <= '0';
next_counter <= (others => '0');
next_ret_state <= DONE;
next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);
next_state <= WAITING1;
when DONE => -- initialization done
next_lcd_db <= "00000000";
next_lcd_en <= '1';
next_lcd_rs <= '0';
if(new_character = '1') then -- send data
next_ret_state <= DONE;
next_state <= WAITING1;
next_lcd_rs <= '1';
next_counter <= (others => '0');
next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);
next_lcd_db <= data;
elsif(new_pos = '1') then -- new address
next_state <= WAITING1;
next_ret_state <= DONE;
next_lcd_db <= '1' & data(6 downto 0);
next_counter <= (others => '0');
next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);
end if;
when WAITING1 => -- wait with jump
if(cur_counter >= ret_counter) then
next_state <= WAITING2;
next_counter <= (others => '0');
next_ret_counter <= to_unsigned(PAUSE_COUNT, NBITS);
end if;
next_lcd_en <= '1';
when WAITING2 => -- wait without jump
if(cur_counter >= ret_counter) then
next_state <= ret_state;
end if;
next_lcd_en <= '0';
when WAITING3 => -- wait with counter reset
if(cur_counter >= PAUSE_COUNT) then
next_state <= WAITING2;
next_counter <= (others => '0');
end if;
when others => null; -- do nothing, if we are in a different state
end case;
end process NSL;
-- Output logic
lcd_db <= cur_lcd_db;
lcd_en <= cur_lcd_en;
lcd_rs <= cur_lcd_rs;
busy <= '0' when cur_state = DONE else '1';
end Behavioral; |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_10;
USE proc_sys_reset_v5_0_10.proc_sys_reset;
ENTITY sys_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END sys_rst_processing_system7_0_100M_0;
ARCHITECTURE sys_rst_processing_system7_0_100M_0_arch OF sys_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END sys_rst_processing_system7_0_100M_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_10;
USE proc_sys_reset_v5_0_10.proc_sys_reset;
ENTITY sys_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END sys_rst_processing_system7_0_100M_0;
ARCHITECTURE sys_rst_processing_system7_0_100M_0_arch OF sys_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END sys_rst_processing_system7_0_100M_0_arch;
|
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
port(
-- FX2LP interface ---------------------------------------------------------------------------
fx2Clk_in : in std_logic; -- 48MHz clock from FX2LP
fx2Addr_out : out std_logic_vector(1 downto 0); -- select FIFO: "00" for EP2OUT, "10" for EP6IN
fx2Data_io : inout std_logic_vector(7 downto 0); -- 8-bit data to/from FX2LP
-- When EP2OUT selected:
fx2Read_out : out std_logic; -- asserted (active-low) when reading from FX2LP
fx2GotData_in : in std_logic; -- asserted (active-high) when FX2LP has data for us
-- When EP6IN selected:
fx2Write_out : out std_logic; -- asserted (active-low) when writing to FX2LP
fx2GotRoom_in : in std_logic; -- asserted (active-high) when FX2LP has room for more data from us
fx2PktEnd_out : out std_logic; -- asserted (active-low) when a host read needs to be committed early
-- Onboard peripherals -----------------------------------------------------------------------
sseg_out : out std_logic_vector(7 downto 0); -- seven-segment display cathodes (one for each segment)
anode_out : out std_logic_vector(3 downto 0); -- seven-segment display anodes (one for each digit)
led_out : out std_logic_vector(7 downto 0); -- eight LEDs
sw_in : in std_logic_vector(7 downto 0) -- eight switches
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
-- Reset signal so host can delay startup
signal fx2Reset : std_logic;
begin
-- CommFPGA module
fx2Addr_out(0) <= -- So fx2Addr_out(1)='0' selects EP2OUT, fx2Addr_out(1)='1' selects EP6IN
'0' when fx2Reset = '0'
else 'Z';
comm_fpga_fx2 : entity work.comm_fpga_fx2
port map(
clk_in => fx2Clk_in,
reset_in => '0',
reset_out => fx2Reset,
-- FX2LP interface
fx2FifoSel_out => fx2Addr_out(1),
fx2Data_io => fx2Data_io,
fx2Read_out => fx2Read_out,
fx2GotData_in => fx2GotData_in,
fx2Write_out => fx2Write_out,
fx2GotRoom_in => fx2GotRoom_in,
fx2PktEnd_out => fx2PktEnd_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
swled_app : entity work.swled
port map(
clk_in => fx2Clk_in,
reset_in => '0',
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- External interface
sseg_out => sseg_out,
anode_out => anode_out,
led_out => led_out,
sw_in => sw_in
);
end architecture;
|
----------------------------------------------------------------------------------
-- Company: N/A
-- Engineer: WTMW
-- Create Date: 22:27:15 09/26/2014
-- Design Name:
-- Module Name: Hamming_tests.vhd
-- Project Name: project_nrf
-- Target Devices: Nexys 4
-- Tool versions: ISE WEBPACK 64-Bit
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
use work.project_nrf_subprog.all;
ENTITY Hamming_test IS
END Hamming_test;
ARCHITECTURE behavior OF Hamming_test IS
-- Test Signals
signal data_nib : std_logic_vector(3 downto 0) := "0000";
signal encoded_byte : std_logic_vector(7 downto 0) := "00000000";
signal err_vector : std_logic_vector(7 downto 0) := "00000001";
signal decoded_nib : std_logic_vector(3 downto 0) := "0000";
-- CLK Signals
signal clk : std_logic := '0';
constant clk_period : time := 10 ns;
signal masterReset : std_logic := '1';
BEGIN
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process begin
wait for clk_period*10;
for I in 1 to 16 loop
for I in 1 to 8 loop
wait until rising_edge(clk);
encoded_byte <= Hamming_hByte_encoder(data_nib);
wait for clk_period;
encoded_byte <= encoded_byte XOR err_vector;
err_vector <= err_vector(6 downto 0) & '0';
wait for clk_period;
decoded_nib <= Hamming_hByte_decoder(encoded_byte);
wait for clk_period;
end loop;
data_nib <= data_nib + '1';
err_vector <= "00000001";
wait for clk_period*2;
end loop;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
entity func03 is
port (a : std_logic_vector (7 downto 0);
b : out std_logic_vector (7 downto 0));
end func03;
architecture behav of func03 is
function gen_mask (len : natural) return std_logic_vector is
variable res : std_logic_vector (len - 1 downto 0);
begin
res := (0 => '1', others => '0');
return res;
end gen_mask;
constant mask : std_logic_vector(7 downto 0) := gen_mask (8);
begin
b <= a and mask;
end behav;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_ireg
-- File: ddr_ireg.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: DDR input reg with tech selection
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddr_ireg is
generic ( tech : integer; arch : integer := 0; scantest: integer := 0);
port ( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic;
testen: in std_ulogic;
testrst: in std_ulogic);
end;
architecture rtl of ddr_ireg is
begin
inf : if not((is_unisim(tech) = 1) or (tech = axcel) or
(tech = axdsp) or (tech = apa3) or (tech = apa3e) or
(tech = apa3l) or (tech = rhumc) or (tech = igloo2) or
(tech = rtg4)) generate
inf0 : gen_iddr_reg generic map (scantest,0) port map (Q1, Q2, C1, C2, CE, D, R, S, testen, testrst);
end generate;
ax : if (tech = axcel) or (tech = axdsp) generate
axc0 : axcel_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
pa3 : if (tech = apa3) generate
pa0 : apa3_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
pa3e : if (tech = apa3e) generate
pa0 : apa3e_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
pa3l : if (tech = apa3l) generate
pa0 : apa3l_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
igl20 : igloo2_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
xil : if is_unisim(tech) = 1 generate
xil0 : unisim_iddr_reg generic map (tech, arch) port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
rhu : if (tech = rhumc) generate
rhu0: rhumc_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
--pragma translate_off
assert (tech /= easic45) and (tech /= easic90)
report "ddr_ireg: Not supported on eASIC. Use DDR pad instead."
severity failure;
--pragma translate_on
end architecture;
|
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Shift/Adjust Module --
----------------------------------------------------------
entity swap is
generic
(
exp_bits : integer := 8;
man_bits : integer := 23
);
port
(
--inputs
CLK : in std_logic;
RESET : in std_logic;
STALL : in std_logic;
READY : in std_logic;
IN1 : in std_logic_vector(exp_bits+man_bits downto 0);
IN2 : in std_logic_vector(exp_bits+man_bits downto 0);
--outputs
EXP_DIFF : out std_logic_vector(exp_bits-1 downto 0);
OUT1 : out std_logic_vector(exp_bits+man_bits+2 downto 0);
OUT2 : out std_logic_vector(exp_bits+man_bits+2 downto 0);
DONE : out std_logic
);
end swap;
architecture swap_arch of swap is
--SIGNALS
signal sign1 : std_logic;
signal sign2 : std_logic;
signal sign_large : std_logic;
signal sign_small : std_logic;
signal exp1 : std_logic_vector(exp_bits downto 0);
signal exp2 : std_logic_vector(exp_bits downto 0);
signal difference : std_logic_vector(exp_bits downto 0);
signal difference_cor : std_logic_vector(exp_bits downto 0);
signal exp : std_logic_vector(exp_bits-1 downto 0);
signal man1 : std_logic_vector(man_bits+1 downto 0);
signal man2 : std_logic_vector(man_bits+1 downto 0);
signal man_large : std_logic_vector(man_bits+1 downto 0);
signal man_small : std_logic_vector(man_bits+1 downto 0);
signal large : std_logic_vector(exp_bits+man_bits+2 downto 0);
signal small : std_logic_vector(exp_bits+man_bits+2 downto 0);
signal mux_ctrl : std_logic;
signal two_s_comp : std_logic;
begin
--concurrent
--connect signals
sign1 <= IN1(exp_bits+man_bits);
sign2 <= IN2(exp_bits+man_bits);
exp1 <= '0' & IN1(exp_bits+man_bits-1 downto man_bits);
exp2 <= '0' & IN2(exp_bits+man_bits-1 downto man_bits);
man1 <= IN1(man_bits-1 downto 0) & "00";
man2 <= IN2(man_bits-1 downto 0) & "00";
--instantiate the components
exp_subtractor : parameterized_subtractor
generic map
(
bits => exp_bits + 1
)
port map
(
--inputs
A => exp1,
B => exp2,
--outputs
O => difference
);
diff_cor: difference_cor <= ((not difference) + '1') when (difference(exp_bits) = '1') else difference;
control : mux_ctrl <= difference(exp_bits);
exp_out_mux : parameterized_mux
generic map
(
bits => exp_bits
)
port map
(
--inputs
A => exp2(exp_bits-1 downto 0),
B => exp1(exp_bits-1 downto 0),
S => mux_ctrl,
--outputs
O => exp
);
sign_out_mux1 : sign_large <= sign2 when (mux_ctrl = '1') else sign1;
man_out_mux1 : parameterized_mux
generic map
(
bits => man_bits + 2
)
port map
(
--inputs
A => man2,
B => man1,
S => mux_ctrl,
--outputs
O => man_large
);
sign_out_mux2 : sign_small <= sign1 when (mux_ctrl = '1') else sign2;
man_out_mux2 : parameterized_mux
generic map
(
bits => man_bits + 2
)
port map
(
--inputs
A => man1,
B => man2,
S => mux_ctrl,
--outputs
O => man_small
);
large <= sign_large & exp & man_large;
small <= sign_small & exp & man_small;
--sequential
main : process(CLK,RESET,STALL) is
begin
if (RESET = '1') then
DONE <= '0';
EXP_DIFF <= (others => '0');
OUT1 <= (others=>'0');
OUT2 <= (others=>'0');
elsif(rising_edge(CLK) and STALL = '0') then
DONE <= READY;
EXP_DIFF <= difference_cor(exp_bits-1 downto 0);
OUT1 <= large;
OUT2 <= small;
end if;--CLK
end process MAIN; --main
end swap_arch; --end of architecture
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : AMBA_TestPackage (Package and body declarations)
--
-- File name : amba_tp.vhd
--
-- Purpose : AMBA AHB and APB interface access procedures
--
-- Library : {independent}
--
-- Authors : Aeroflex Gaisler AB
--
-- Contact : mailto:[email protected]
-- http://www.aeroflex.com/gaisler
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--------------------------------------------------------------------------------
-- Version Author Date Changes
-- 0.1 SH 15 Mar 2002 New package
-- 0.2 SH 17 Mar 2003 Updated most packages
-- 0.3 SH 20 May 2003 Memory based on Integer elements
-- 0.4 SH 1 Jul 2003 Name of package changed
-- Compare function improved
-- AHB 32 bit memory with preload added
-- AHB initialisation added
-- 0.5 SH 21 Jul 2003 AHB 32 memory with diagnostics added
-- 0.6 SH 1 Nov 2003 APB read access data sample made earlier
-- AHB 32 memory extended with byte/halfword
-- 0.7 SH 25 Jan 2004 AHB read access data output corrected
-- AHB 32 memory allows overlay addressing
-- 1.7 SH 1 Oct 2004 Ported to GRLIB
-- 1.8 SH 1 Jul 2005 Added configuration support for memories
-- Modified all procedure declarations
-- 1.9 SH 10 Nov 2005 AHB 32 responds with HREADY=0 when error
-- 1.11 SH 27 Dec 2004 Split support added, using HSPLIT element
-- Proper two-cycle error response implemented
-- 1.12 SH 15 Feb 2006 Added bank select to AHB bus accesses
-- 1.13 SH 1 May 2009 AHBQuite gave incorrect TP on error resps.
--------------------------------------------------------------------------------
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
library GRLIB;
use GRLIB.AMBA.all;
use GRLIB.StdLib.all;
use GRLIB.StdIO.all;
package AMBA_TestPackage is
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBInit(
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
constant InstancePath: in String := "APBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True);
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBRead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- Initialise AMBA AHB interface
-----------------------------------------------------------------------------
procedure AHBInit(
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
constant InstancePath: in String := "AHBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBRead";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0);
-----------------------------------------------------------------------------
-- Diagnstics types for behavioural model of memory with AHB interface
-----------------------------------------------------------------------------
type AHB_Diagnostics_In_Type is
record
HADDR: Std_Logic_Vector(31 downto 0);
HWRITE: Std_ULogic;
HWDATA: Std_Logic_Vector(31 downto 0);
HRESP: Std_Logic_Vector(1 downto 0); -- response type
HSPLIT: Std_Logic_Vector(NAHBMST-1 downto 0); -- split completion
end record AHB_Diagnostics_In_Type;
type AHB_Diagnostics_Out_Type is
record
HRDATA: Std_Logic_Vector(31 downto 0);
end record AHB_Diagnostics_Out_Type;
constant AHB_Diagnostics_Init: AHB_Diagnostics_In_Type :=
(X"00000000", '0', X"00000000", HRESP_OKAY, zero32(NAHBMST-1 downto 0));
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory(
constant gAWidth: in Positive := 15; -- address width
constant gDWidth: in Positive := 8; -- data width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory";
constant ScreenOutput: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#);
-----------------------------------------------------------------------------
-- Behavioural model of memory with AMBA AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- file name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#);
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-- Supporting byte, halfword and word read/write accesses.
-- Provices diagnostic support.
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
signal AHBInDiag: in AHB_Diagnostics_In_Type;
signal AHBOutDiag: out AHB_Diagnostics_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- file name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#);
-----------------------------------------------------------------------------
-- Routine for writig data directly to AHB memory
-----------------------------------------------------------------------------
procedure WrAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RdAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RcAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Expected: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
-----------------------------------------------------------------------------
-- Routine for generating a split ack from AHB memory
-----------------------------------------------------------------------------
procedure SplitAHBMem32(
constant Split: in Integer range 0 to NAHBMST-1;
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False);
end AMBA_TestPackage;
--============================================================================--
package body AMBA_TestPackage is
-----------------------------------------------------------------------------
-- Compare function handling '-'
-----------------------------------------------------------------------------
function Compare(O, C: in Std_Logic_Vector) return Boolean is
variable T: Std_Logic_Vector(O'Range) := C;
variable Result: Boolean;
begin
Result := True;
for i in O'Range loop
if not (O(i)=T(i) or T(i)='-' or T(i)='U') then
Result := False;
end if;
end loop;
return Result;
end function Compare;
-----------------------------------------------------------------------------
-- Synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure Synchronise(
signal Clk: in Std_ULogic;
constant Offset: in Time := 5 ns) is
begin
wait until CLK = '1'; -- Synchronise
wait for Offset; -- output offset delay
end procedure Synchronise;
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBInit(
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
constant InstancePath: in String := "APBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True) is
variable L: Line;
begin
if cBack2Back then
Synchronise(PCLK);
end if;
APBIn.PSEL <= (others => '0');
APBIn.PENABLE <= '0';
APBIn.PADDR <= (others => '0');
APBIn.PWRITE <= '0';
APBIn.PWDATA <= (others => '0');
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : APB initalised"));
WriteLine(Output, L);
end if;
end procedure APBInit;
-----------------------------------------------------------------------------
-- AMBA APB write access
-----------------------------------------------------------------------------
procedure APBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(PCLK);
end if;
APBIn.PSEL <= (others => '0');
APBIn.PSEL(PINDEX) <= '1'; -- first clock period
APBIn.PENABLE <= '0';
APBIn.PADDR <= Address;
APBIn.PWRITE <= '1';
APBIn.PWDATA <= Data;
Synchronise(PCLK); -- second clock period
APBIn.PENABLE <= '1';
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : APB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
end if;
Synchronise(PCLK); -- end of access
APBIn.PSEL <= (others => '0');
APBIn.PENABLE <= '0';
APBIn.PADDR <= (others => '-');
APBIn.PWRITE <= '0';
APBIn.PWDATA <= (others => '-');
end procedure APBWrite;
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(PCLK);
end if;
APBIn.PSEL <= (others => '0');
APBIn.PSEL(PINDEX) <= '1'; -- first clock period
APBIn.PENABLE <= '0';
APBIn.PADDR <= Address;
APBIn.PWRITE <= '0';
APBIn.PWDATA <= (others => '-');
Synchronise(PCLK); -- second clock period
APBIn.PENABLE <= '1';
wait for 5 ns;
Data := APBOut.PRDATA;
Synchronise(PCLK); -- end of access
APBIn.PSEL <= (others => '0');
APBIn.PENABLE <= '0';
APBIn.PADDR <= (others => '-');
end procedure APBQuiet;
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBRead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
variable L: Line;
variable Temp: Std_Logic_Vector(31 downto 0);
begin
APBQuiet(Address, Temp, PCLK, APBIn, APBOut, TP, InstancePath, False, cBack2Back, PINDEX);
Data := Temp;
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : APB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Temp);
WriteLine(Output, L);
end if;
end procedure APBRead;
-----------------------------------------------------------------------------
-- AMBA APB read access
-----------------------------------------------------------------------------
procedure APBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal PCLK: in Std_ULogic;
signal APBIn: out APB_Slv_In_Type;
signal APBOut: in APB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "APBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant PINDEX: in Integer := 0) is
variable L: Line;
variable Data: Std_Logic_Vector(31 downto 0);
begin
APBQuiet(Address, Data, PCLK, APBIn, APBOut, TP, InstancePath, False, cBack2Back, PINDEX);
if not Compare(Data, CxData) then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
Write(L, String'(" : expected: "));
HWrite(L, CxData);
Write(L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
end if;
RxData := Data;
end procedure APBComp;
-----------------------------------------------------------------------------
-- Initialise AHB interface
-----------------------------------------------------------------------------
procedure AHBInit(
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
constant InstancePath: in String := "AHBInit";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := True) is
variable L: Line;
begin
if cBack2Back then
Synchronise(HCLK);
end if;
AHBIn.HSEL <= (others => '0');
AHBIn.HADDR <= (others => '0');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '0';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB initalised"));
WriteLine(Output, L);
end if;
end procedure AHBInit;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK); -- first clock period
end if;
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= Address;
AHBIn.HWRITE <= '1';
AHBIn.HTRANS <= HTRANS_NONSEQ;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
Synchronise(HCLK); -- second clock period
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HWDATA <= ahbdrivedata(Data);
AHBIn.HREADY <= AHBOut.HREADY;
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
while AHBOut.HREADY='0' loop
Synchronise(HCLK);
end loop;
if AHBOut.HRESP=HRESP_ERROR then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" ERROR response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_RETRY then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" RETRY response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_SPLIT then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" SPLIT response "));
WriteLine(Output, L);
end if;
TP := False;
else
end if;
Synchronise(HCLK); -- end of access
AHBIn.HSEL <= (others => '0');
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '1';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
end procedure AHBWriteQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure AHBWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable OK: Boolean := True;
variable L: Line;
begin
AHBWriteQuiet(Address, Data, HCLK, AHBIn, AHBOut, OK,
InstancePath, False, cBack2Back, HINDEX, HMBINDEX);
if ScreenOutput and OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
elsif not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
end if;
end procedure AHBWrite;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= Address;
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_NONSEQ;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
Synchronise(HCLK); -- second clock period
AHBIn.HSEL <= (others => '0');
AHBIn.HSEL(HINDEX)<= '1';
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HREADY <= AHBOut.HREADY;
AHBIn.HMBSEL <= (others => '0');
AHBIn.HMBSEL(HMBINDEX) <= '1';
while AHBOut.HREADY='0' loop
Synchronise(HCLK);
end loop;
Data := AHBOut.HRDATA(31 downto 0);
if AHBOut.HRESP=HRESP_ERROR then
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" ERROR response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_RETRY then
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" RETRY response "));
WriteLine(Output, L);
end if;
TP := False;
elsif AHBOut.HRESP=HRESP_SPLIT then
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" SPLIT response "));
WriteLine(Output, L);
end if;
TP := False;
else
end if;
Synchronise(HCLK); -- end of access
AHBIn.HSEL <= (others => '0');
AHBIn.HADDR <= (others => '-');
AHBIn.HWRITE <= '0';
AHBIn.HTRANS <= HTRANS_IDLE;
AHBIn.HSIZE <= HSIZE_WORD;
AHBIn.HBURST <= HBURST_SINGLE;
AHBIn.HWDATA <= (others => '-');
AHBIn.HPROT <= (others => '0');
AHBIn.HREADY <= '1';
AHBIn.HMASTER <= (others => '0');
AHBIn.HMASTLOCK <= '0';
AHBIn.HMBSEL <= (others => '0');
end procedure AHBQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBRead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBRead";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable OK: Boolean := True;
variable L: Line;
variable Temp: Std_Logic_Vector(31 downto 0);
begin
AHBQuiet(Address, Temp, HCLK, AHBIn, AHBOut, OK,
InstancePath, False, cBack2Back, HINDEX, HMBINDEX);
if ScreenOutput and OK then
Data := Temp;
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Temp);
WriteLine(Output, L);
elsif OK then
Data := Temp;
else
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
Data := (others => '-');
TP := False;
end if;
end procedure AHBRead;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure AHBComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBIn: out AHB_Slv_In_Type;
signal AHBOut: in AHB_Slv_Out_Type;
variable TP: inout Boolean;
constant InstancePath: in String := "AHBComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HMBINDEX: in Integer := 0) is
variable OK: Boolean := True;
variable L: Line;
variable Data: Std_Logic_Vector(31 downto 0);
variable Failed: Boolean;
begin
AHBQuiet(Address, Data, HCLK, AHBIn, AHBOut, OK,
InstancePath, False, cBack2Back, HINDEX, HMBINDEX);
if not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
RxData := (others => '-');
elsif not Compare(Data, CxData) then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
Write(L, String'(" : expected: "));
HWrite(L, CxData);
Write(L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
RxData := Data;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
RxData := Data;
else
RxData := Data;
end if;
end procedure AHBComp;
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory(
constant gAWidth: in Positive := 15; -- address width
constant gDWidth: in Positive := 8; -- data width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory";
constant ScreenOutput: in Boolean := False;
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#) is
-- memory definition
subtype ARange is Natural range 0 to 2**gAWidth-1;
subtype DRange is Natural range 0 to gDWidth-1;
type MType is array (ARange) of Integer;
-- memory initialisation
function Init return MType is
variable r: MType;
begin
for i in ARange loop
r(i) := -1;
end loop;
return r;
end function Init;
variable M: MType;
variable A: Std_Logic_Vector(gAWidth-1 downto 0);
variable D: Std_Logic_Vector(0 to gDWidth-1);
variable W: Std_Logic;
-- reset values
procedure Reset is
begin
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= (others => '0');
W := '0';
end procedure Reset;
-- plug&play configuration
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg (0, 0, 0, gAWidth, 0),
4 => ahb_membar(HADDR, '1', '1', HMASK),
others => zero32);
variable alow : std_logic_vector(1 downto 0);
begin
-- fixed AMBA AHB signals, etc.
AHBOut.HSPLIT <= (others => '0');
AHBOut.HCONFIG <= HCONFIG;
loop
if HRESETn='0' then -- asynchronous reset
Reset;
elsif HCLK'Event and HCLK='1' then -- rising edge
-- data phase
if AHBIn.HREADY='1' then
if W='1' then
alow := A(1 downto 0);
case alow is
when "00" =>
D := AHBIn.HWDATA(31 downto 24);
when "01" =>
D := AHBIn.HWDATA(23 downto 16);
when "10" =>
D := AHBIn.HWDATA(15 downto 8);
when others =>
D := AHBIn.HWDATA( 7 downto 0);
end case;
M(Conv_Integer(A)) := Conv_Integer(D);
W := '0';
end if;
end if;
-- address phase
if AHBIn.HSEL(HINDEX)='1' and
AHBIn.HREADY='1' and
AHBIn.HSIZE=HSIZE_BYTE and
(AHBIn.HTRANS=HTRANS_SEQ or
AHBIn.HTRANS=HTRANS_NONSEQ) and
AHBIn.HMASTLOCK='0' then
W := AHBIn.HWRITE;
A := AHBIn.HADDR(gAWidth-1 downto 0);
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
D := Conv_Std_Logic_Vector(
M(Conv_Integer(A)), D'Length);
case alow is
when "00" =>
AHBOut.HRDATA(31 downto 24) <= D;
when "01" =>
AHBOut.HRDATA(23 downto 16) <= D;
when "10" =>
AHBOut.HRDATA(15 downto 8) <= D;
when others =>
AHBOut.HRDATA( 7 downto 0) <= D;
end case;
else
w :='0';
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
end if;
end if;
-- signal sensitivity
wait on HCLK, HRESETn;
end loop;
end procedure AHBMemory;
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- File name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#) is
-- memory definition
type MType is array (0 to 2**(gAWidth-2)-1) of
Std_Logic_Vector(31 downto 0);
--------------------------------------------------------------------------
-- Load memory contents
--------------------------------------------------------------------------
-- ## Does not warn if there is insufficient data in a line.
-- Address read from file is always byte oriented, always 32 bit wide
-- For 16 and 32 bit wide data, each data word read from file must be on a
-- single line and without white space between the characters. For 8 bit
-- wide date, no restrictions apply. Files generated for 32 bit wide data
-- can always be read by 16 or 8 bit memories. The byte/halfwrod address
-- is incremented internally.
--------------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- -- PROM Initialisation Example
-- -----------------------------------------------------------------------
-- -- Supports by 8, 16, 32 bit wide memories
-- 00000000 00010203
-- 00000004 04050607 08090A0B
-- 0000000C 0C0D0E0F
--
-- -- Supported by 8, 16 bit wide memories
-- 00000010 1011 1213
-- 00000014 1415
-- 00000016 1617 1819 1A1B 1C1D 1E1F 2021
-- 00000022 2223 2425 2627 2829 2A2B 2C2D 2E2F
--
-- -- Supported by 8 bit wide memories
-- 00000030 30 31 32 33 3435 3637 3839 3A3B 3C3D 3E3F
-- 00000040 40
-- 00000041 41
-- 00000042 42 43
-- 00000044 4445
-- 00000046 46474849
-- 0000004A 4A4B 4C4D4E4F
--------------------------------------------------------------------------
impure function Initialise(
constant FileName: in String := "";
constant AWidth: in Natural;
constant DWidth: in Natural)
return MType is
variable L: Line;
variable Address: Std_Logic_Vector(31 downto 0);
variable Data: Std_Logic_Vector(31 downto 0);
variable Byte: Std_Logic_Vector( 7 downto 0);
variable Addr: Natural range 0 to 2**AWidth-1;
file ReadFile: Text;
variable Test: Boolean;
variable Result: MType;
begin
-- initialse all data to all zeros
Result := (others => (others => 'U'));
-- load contents from file only if a file name has been provided
if FileName /= "" then
File_Open(ReadFile, FileName, Read_Mode);
-- read data from file
while not EndFile(ReadFile) loop
-- read line
ReadLine(ReadFile, L);
-- read address, always byte oriented, always 32 bit wide
HRead(L, Address, Test);
if Test then -- address read
-- check whether byte address aligned with data width
if Conv_Integer(Address) mod (DWidth/8) /= 0 then
report "Unaligned data in memory initalisation file: " &
FileName
severity Failure;
Test := False;
else -- convert address
-- adapt byte address to address corresponding to the data
-- width of the memory
Addr := (Conv_Integer(Address)/(DWidth/8)) mod
(2**AWidth);
end if;
else -- comment detected
null;
end if;
while Test loop
-- read data
HRead(L, Data(DWidth-1 downto 0), Test);
if Test then
-- initialize memory element
Result(Addr) := Data(DWidth-1 downto 0);
-- increment address, with the memory width
Addr := (Addr + 1) mod (2**AWidth);
end if;
end loop;
end loop;
File_Close(ReadFile);
end if;
return Result;
end function Initialise;
-- memory contents
variable M: MType := Initialise(FileName, gAWidth-2, 32);
variable A: Std_Logic_Vector(gAWidth-1 downto 2);
variable W: Std_Logic;
-- reset values
procedure Reset is
begin
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= (others => '0');
W := '0';
end procedure Reset;
-- plug&play configuration
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg (0, 0, 0, gAWidth, 0),
4 => ahb_membar(HADDR, '1', '1', HMASK),
others => zero32);
begin
-- fixed AMBA AHB signals, etc.
AHBOut.HSPLIT <= (others => '0');
AHBOut.HCONFIG <= HCONFIG;
loop
if HRESETn='0' then -- asynchronous reset
Reset;
elsif HCLK'Event and HCLK='1' then -- rising edge
-- data phase
if AHBIn.HREADY='1' then
if W='1' then
M(Conv_Integer(A)) := AHBIn.HWDATA(31 downto 0);
W := '0';
end if;
end if;
-- address phase
if AHBIn.HSEL(HINDEX)='1' and
AHBIn.HREADY='1' and
AHBIn.HSIZE=HSIZE_WORD and
(AHBIn.HTRANS=HTRANS_SEQ or
AHBIn.HTRANS=HTRANS_NONSEQ) and
AHBIn.HMASTLOCK='0' then
W := AHBIn.HWRITE;
A := AHBIn.HADDR(gAWidth-1 downto 2);
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= ahbdrivedata(M(Conv_Integer(A)));
else
W :='0';
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
end if;
end if;
-- signal sensitivity
wait on HCLK, HRESETn;
end loop;
end procedure AHBMemory32;
-----------------------------------------------------------------------------
-- Behavioural model of memory with AHB interface, no wait states
-- Supporting byte, halfword and word read/write accesses.
-- Provices diagnostic support.
-----------------------------------------------------------------------------
procedure AHBMemory32(
constant gAWidth: in Positive := 18; -- address width
signal HCLK: in Std_ULogic;
signal HRESETn: in Std_ULogic;
signal AHBIn: in AHB_Slv_In_Type;
signal AHBOut: out AHB_Slv_Out_Type;
signal AHBInDiag: in AHB_Diagnostics_In_Type;
signal AHBOutDiag: out AHB_Diagnostics_Out_Type;
constant InstancePath: in String := "AHBMemory32";
constant ScreenOutput: in Boolean := False;
constant FileName: in String := ""; -- File name
constant HINDEX: in Integer := 0;
constant HADDR: in Integer := 0;
constant HMASK: in Integer := 16#FFF#) is
-- memory definition
type MType is array (0 to 2**(gAWidth-2)-1) of
Std_Logic_Vector(31 downto 0);
variable L: Line;
constant Padding: Std_ULogic_Vector(1 to
(4-((gAWidth-2) mod 4))) :=
(others => '0');
--------------------------------------------------------------------------
-- Load memory contents
--------------------------------------------------------------------------
-- ## Does not warn if there is insufficient data in a line.
-- Address read from file is always byte oriented, always 32 bit wide
-- For 16 and 32 bit wide data, each data word read from file must be on a
-- single line and without white space between the characters. For 8 bit
-- wide date, no restrictions apply. Files generated for 32 bit wide data
-- can always be read by 16 or 8 bit memories. The byte/halfwrod address
-- is incremented internally.
--------------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- -- PROM Initialisation Example
-- -----------------------------------------------------------------------
-- -- Supports by 8, 16, 32 bit wide memories
-- 00000000 00010203
-- 00000004 04050607 08090A0B
-- 0000000C 0C0D0E0F
--
-- -- Supported by 8, 16 bit wide memories
-- 00000010 1011 1213
-- 00000014 1415
-- 00000016 1617 1819 1A1B 1C1D 1E1F 2021
-- 00000022 2223 2425 2627 2829 2A2B 2C2D 2E2F
--
-- -- Supported by 8 bit wide memories
-- 00000030 30 31 32 33 3435 3637 3839 3A3B 3C3D 3E3F
-- 00000040 40
-- 00000041 41
-- 00000042 42 43
-- 00000044 4445
-- 00000046 46474849
-- 0000004A 4A4B 4C4D4E4F
--------------------------------------------------------------------------
impure function Initialise(
constant FileName: in String := "";
constant AWidth: in Natural;
constant DWidth: in Natural)
return MType is
variable L: Line;
variable Address: Std_Logic_Vector(31 downto 0);
variable Data: Std_Logic_Vector(31 downto 0);
variable Byte: Std_Logic_Vector( 7 downto 0);
variable Addr: Natural range 0 to 2**AWidth-1;
file ReadFile: Text;
variable Test: Boolean;
variable Result: MType;
begin
-- initialse all data to all zeros
Result := (others => (others => 'U'));
-- load contents from file only if a file name has been provided
if FileName /= "" then
File_Open(ReadFile, FileName, Read_Mode);
-- read data from file
while not EndFile(ReadFile) loop
-- read line
ReadLine(ReadFile, L);
-- read address, always byte oriented, always 32 bit wide
HRead(L, Address, Test);
if Test then -- address read
-- check whether byte address aligned with data width
if Conv_Integer(Address) mod (DWidth/8) /= 0 then
report "Unaligned data in memory initalisation file: " &
FileName
severity Failure;
Test := False;
else -- convert address
-- adapt byte address to address corresponding to the data
-- width of the memory
Addr := (Conv_Integer(Address)/(DWidth/8)) mod
(2**AWidth);
end if;
else -- comment detected
null;
end if;
while Test loop
-- read data
HRead(L, Data(DWidth-1 downto 0), Test);
if Test then
-- initialize memory element
Result(Addr) := Data(DWidth-1 downto 0);
-- increment address, with the memory width
Addr := (Addr + 1) mod (2**AWidth);
end if;
end loop;
end loop;
File_Close(ReadFile);
end if;
return Result;
end function Initialise;
-- memory contents
variable M: MType := Initialise(FileName, gAWidth-2, 32);
variable A: Std_Logic_Vector(gAWidth-1 downto 2);
variable B: Std_Logic_Vector(1 downto 0);
variable W: Std_Logic;
variable S: Std_Logic_Vector(2 downto 0);
variable D: Std_Logic_Vector(31 downto 0);
variable twocycle:Boolean := False;
-- reset values
procedure Reset is
begin
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= (others => '0');
W := '0';
twocycle := False;
end procedure Reset;
-- plug&play configuration
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg (0, 0, 0, gAWidth, 0),
4 => ahb_membar(HADDR, '1', '1', HMASK),
others => zero32);
begin
-- fixed AMBA AHB signals, etc.
AHBOut.HSPLIT <= (others => '0');
AHBOut.HCONFIG <= HCONFIG;
loop
if HRESETn='0' then -- asynchronous reset
Reset;
elsif HCLK'Event and HCLK='1' then -- rising edge
-- data phase
if AHBIn.HREADY='1' then
if W='1' then
-- read back memory
D := M(Conv_Integer(A));
-- replace with new data
if S="000" then -- byte
if B(1 downto 0)="00" then
D := AHBIn.HWDATA(31 downto 24) &
D(23 downto 0);
elsif B(1 downto 0)="01" then
D := D(31 downto 24) &
AHBIn.HWDATA(23 downto 16) &
D(15 downto 0);
elsif B(1 downto 0)="10" then
D := D(31 downto 16) &
AHBIn.HWDATA(15 downto 8) &
D(7 downto 0);
elsif B(1 downto 0)="11" then
D := D(31 downto 8) &
AHBIn.HWDATA(7 downto 0);
end if;
elsif S="001" then -- halfword
if B(1 downto 0)="00" then
D := AHBIn.HWDATA(31 downto 16) &
D(15 downto 0);
elsif B(1 downto 0)="10" then
D := D(31 downto 16) &
AHBIn.HWDATA(15 downto 0);
end if;
else
D := AHBIn.HWDATA(31 downto 0);
end if;
-- write back memory
M(Conv_Integer(A)) := D;
W := '0';
-- comment
if ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath & " Write acces to address :");
if Padding'Length > 0 and Padding'Length < 4 then
HWrite(L, Std_Logic_Vector(Padding) & Std_Logic_Vector(A));
else
HWrite(L, Std_Logic_Vector(A));
end if;
Write(L, String'(" data :"));
HWrite(L, D);
Write(L, String'(" data :"));
Write(L, To_BitVector(D));
Write(L, String'(" size :"));
HWrite(L, "0" & S);
WriteLine(Output, L);
end if;
end if;
end if;
-- address phase
if AHBIn.HSEL(HINDEX)='1' and
AHBIn.HREADY='1' and
(AHBIn.HSIZE=HSIZE_BYTE or
AHBIn.HSIZE=HSIZE_HWORD or
AHBIn.HSIZE=HSIZE_WORD) and
(AHBIn.HTRANS=HTRANS_SEQ or
AHBIn.HTRANS=HTRANS_NONSEQ) and
AHBIn.HMASTLOCK='0' then
if AHBInDiag.HRESP=HRESP_OKAY then
W := AHBIn.HWRITE;
S := AHBIn.HSIZE;
B := AHBIn.HADDR( 1 downto 0);
A := AHBIn.HADDR(gAWidth-1 downto 2);
AHBOut.HREADY <= '1';
AHBOut.HRESP <= HRESP_OKAY;
AHBOut.HRDATA <= ahbdrivedata(M(Conv_Integer(A)));
elsif AHBInDiag.HRESP=HRESP_RETRY then
W :='0';
AHBOut.HREADY <= '0';
AHBOut.HRESP <= HRESP_RETRY;
AHBOut.HRDATA <= (others => 'X');
twocycle := True;
elsif AHBInDiag.HRESP=HRESP_SPLIT then
W :='0';
AHBOut.HREADY <= '0';
AHBOut.HRESP <= HRESP_SPLIT;
AHBOut.HRDATA <= (others => 'X');
twocycle := True;
else
W :='0';
AHBOut.HREADY <= '0';
AHBOut.HRESP <= HRESP_ERROR;
AHBOut.HRDATA <= (others => 'X');
twocycle := True;
end if;
else
W :='0';
AHBOut.HREADY <= '1';
if twocycle then
twocycle := False;
else
AHBOut.HRESP <= HRESP_OKAY;
end if;
end if;
end if;
if HCLK'Event and HCLK='1' then -- rising edge
-- diagnostics
AHBOutDiag.HRData <= M((Conv_Integer(AHBInDiag.HAddr)/4) mod (2**(gAWidth-2)));
if AHBInDiag.HWrite='1' then
M((Conv_Integer(AHBInDiag.HAddr)/4) mod (2**(gAWidth-2))) := AHBInDiag.HWData;
-- Print("Diagnostic write to memory, address: " &
-- Integer'Image(Conv_Integer(AHBInDiag.HAddr)) &
-- " data: " &
-- Integer'Image(Conv_Integer(AHBInDiag.HWData)));
end if;
AHBOut.HSPLIT <= AHBInDiag.HSplit;
end if;
-- signal sensitivity
wait on HCLK, HRESETn;
end loop;
end procedure AHBMemory32;
-----------------------------------------------------------------------------
-- Routine for writig data directly to AHB memory
-----------------------------------------------------------------------------
procedure WrAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
if Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : WrAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(Data));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
AHBInDiag.HAddr <= Addr;
AHBInDiag.HWData <= Data;
AHBInDiag.HWrite <= '1';
Synchronise(HCLK);
AHBInDiag.HWrite <= '0';
end procedure WrAHBMem32;
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RdAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
AHBInDiag.HAddr <= Addr;
AHBInDiag.HWrite <= '0';
Synchronise(HCLK);
Data := AHBOutDiag.HRData;
if Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : RdAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(AHBOutDiag.HRData));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
end procedure RdAHBMem32;
-----------------------------------------------------------------------------
-- Routine for reading data directly from AHB memory
-----------------------------------------------------------------------------
procedure RcAHBMem32(
constant Addr: in Std_Logic_Vector(31 downto 0);
constant Expected: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable Data: Std_Logic_Vector(31 downto 0);
variable L: Line;
begin
Synchronise(HCLK);
AHBInDiag.HAddr <= Addr;
AHBInDiag.HWrite <= '0';
Synchronise(HCLK);
Data := AHBOutDiag.HRData;
if not Compare(Data, Expected) then
Write(L, Now, Right, 15);
Write(L, String'(" : RcAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(", value: "));
HWrite(L, Std_Logic_Vector(Data));
Write(L, String'(", expected: "));
HWrite(L, Std_Logic_Vector(Expected));
Write(L, String'(" # Error "));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
TP := False;
elsif Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : RcAHBMem32: "));
HWrite(L, Std_Logic_Vector(Addr));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(Data));
Write(L, String'(" : "));
HWrite(L, Std_Logic_Vector(Expected));
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
end procedure RcAHBMem32;
-----------------------------------------------------------------------------
-- Routine for generating a split ack from AHB memory
-----------------------------------------------------------------------------
procedure SplitAHBMem32(
constant Split: in Integer range 0 to NAHBMST-1;
signal HCLK: in Std_ULogic;
signal AHBInDiag: out AHB_Diagnostics_In_Type;
signal AHBOutDiag: in AHB_Diagnostics_Out_Type;
variable TP: inout Boolean;
constant Comment: in String := "";
constant Screen: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
AHBInDiag.HSPLIT <= (others => '0');
AHBInDiag.HSPLIT(Split) <= '1';
Synchronise(HCLK);
AHBInDiag.HSPLIT <= (others => '0');
if Screen then
Write(L, Now, Right, 15);
Write(L, String'(" : SplitAHBMem32: split acknowledge to master: "));
Write(L, Split);
if Comment /= "" then
Write(L, " : " & Comment);
end if;
WriteLine(Output, L);
end if;
end procedure SplitAHBMem32;
end package body AMBA_TestPackage; --=========================================--
|
-------------------------------------------------------------------------------
-- $Id: ipif_control_rd.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
--ipif_control_rd.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_control_rd.vhd
--
-- Description: This VHDL design file is for the Point Design of the Mauna
-- Loa Read Packet FIFO IPIF Local Bus Interface control
-- block.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_control_rd.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe March 19,2001 -- V1.00a
--
-- Doug Thorpe June 08-12,2001 -- V1.00b
-- - Corrected an error condition where the FIFO2Bus_Error was getting set
-- at the end of a legitimate burst read operation. If the RdFIFO goes
-- empty after the initiation of the read (at least one FIFO2Bus_RdAck
-- has been issued), an 'Empty' condition causes only an inhibit of the
-- FIFO2Bus_RdAck signal.
-- - Fixed the implimentation of the MIR inclusion/occlusion through the
-- use of if--generate clauses.
--
-- DET June 25, 2001 V1.00c
-- - Removed redundant logic assignments flagged by
-- Synplicity
--
-- DET July 20, 2001
-- - Changed the C_MIR_ENABLE type to Boolean from std_logic.
--
-- DET Aug 20, 2001 Version v1.01a
-- - Platform Generator Compliancy modifications
--
-- DET Sept 17, 2001
-- - Size optimization changes
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
entity ipif_control_rd is
Generic (
C_MIR_ENABLE : Boolean := true;
-- Enable for MIR synthesis (default for disable)
C_BLOCK_ID : integer range 0 to 255 := 255;
-- Platform Generator assigned ID number
C_INTFC_TYPE : integer range 0 to 31 := 1;
-- IPIF block protocol Type
C_VERSION_MAJOR : integer range 0 to 9 := 1;
-- Major versioning of top level design
C_VERSION_MINOR : integer range 0 to 99 := 2;
-- Minor Version of top level design
C_VERSION_REV : integer range 0 to 26 := 0;
-- Revision letter of top level design
C_FIFO_WIDTH : Integer := 32;
-- Width of FIFO data in bits
C_DP_ADDRESS_WIDTH : Integer := 9;
-- Indicates address width of RdFIFO memory
-- (= log2(fifo_depth)
C_SUPPORT_BURST : Boolean := true;
-- Indicates read burst support for the IPIF bus
C_IPIF_DBUS_WIDTH : Integer := 32
-- Width of the IPIF data bus in bits
);
port (
-- Inputs From the IPIF Bus
Bus_rst : In std_logic; -- Master Reset from the IPIF
Bus_Clk : In std_logic; -- Master timing clock from the IPIF
Bus_RdReq : In std_logic;
Bus_WrReq : In std_logic;
Bus2FIFO_RdCE1 : In std_logic;
Bus2FIFO_RdCE2 : In std_logic;
Bus2FIFO_RdCE3 : In std_logic;
Bus2FIFO_WrCE1 : In std_logic;
Bus2FIFO_WrCE2 : In std_logic;
Bus2FIFO_WrCE3 : In std_logic;
Bus_DBus : In std_logic_vector(C_IPIF_DBUS_WIDTH-4 to
C_IPIF_DBUS_WIDTH-1);
-- Inputs from the FIFO Interface Logic
Fifo_rd_data : In std_logic_vector(0 to C_FIFO_WIDTH-1);
BRAMFifo_RdAck : In std_logic;
SRLFifo_RdAck : In std_logic;
Occupancy : In std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
AlmostEmpty : In std_logic;
Empty : In std_logic;
Deadlock : In std_logic;
-- Outputs to the FIFO
Fifo_rst : Out std_logic;
BRAMFifo_RdReq : Out std_logic;
SRLFifo_RdReq : Out std_logic;
Fifo_burst_rd_xfer : Out std_logic;
-- Outputs to the IPIF Bus
FIFO2IRPT_DeadLock : Out std_logic;
FIFO2Bus_DBus : Out std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
FIFO2Bus_WrAck : Out std_logic;
FIFO2Bus_RdAck : Out std_logic;
FIFO2Bus_Error : Out std_logic;
FIFO2Bus_Retry : Out std_logic;
FIFO2Bus_ToutSup : Out std_logic
);
end ipif_control_rd ;
-------------------------------------------------------------------------------
architecture implementation of ipif_control_rd is
-- FUNCTIONS
-----------------------------------------------------------------------------
-- Function set_fwidth
--
-- This function is used to set the value of FIFO width status
-- field based on the setting of the width parameter.
-----------------------------------------------------------------------------
function set_fwidth (fifo_width : integer) return integer is
constant byte_lane_num : Integer := (fifo_width+7)/8;
Variable enc_size : Integer := 0;
begin
case byte_lane_num is
when 0|1 =>
enc_size := 1;
when 2 =>
enc_size := 2;
when 3 | 4 =>
enc_size := 3;
when 5|6|7|8 =>
enc_size := 4;
When 9|10|11|12|13|14|15|16 =>
enc_size := 5;
when others =>
enc_size := 6;
end case;
return(enc_size);
end function set_fwidth;
-- COMPONENTS
-- No components
--TYPES
-- no types
-- CONSTANTS
-- Module Software Reset screen value for write data
Constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- This requires a Hex 'A' to be written
-- to ativate the S/W reset port
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- Bus Width Matching constant
Constant ENC_FIFO_WIDTH : integer := set_fwidth(C_FIFO_WIDTH);
--INTERNAL SIGNALS
signal bus_data_out : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
Signal sw_reset_error : std_logic;
signal reg_occupancy : std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Signal reg_almostempty : std_logic;
Signal reg_empty : std_logic;
Signal reg_deadlock : std_logic;
Signal reg_rdce2 : std_logic;
Signal reg_wrce1 : std_logic;
Signal reg_rdreq : std_logic;
Signal read_ack : std_logic;
Signal reg_read_ack : std_logic;
Signal write_ack : std_logic;
Signal rd_access_error : std_logic;
Signal wr_access_error : std_logic;
Signal burst_rd_xfer : std_logic;
Signal read_req : std_logic;
Signal reg_read_req : std_logic;
Signal write_req : std_logic;
Signal fifo_rd_req : std_logic;
Signal fifo_errack_inhibit : std_logic;
Signal rd_vect : std_logic_vector(0 to 3);
Signal sig_srl_rdack : std_logic;
Signal sig_bram_rdack : std_logic;
Signal sig_rst_match : std_logic;
Signal sig_rst_vect : std_logic_vector(0 to 1);
Signal sig_fifo_rd_data : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
-------------------------------------------------------------------------------
---------- start architecture logic -------------------------------------------
begin
-- General access detection (used to terminate reply signal to the Bus)
read_req <= (Bus2FIFO_RdCE1 or Bus2FIFO_RdCE2 or Bus2FIFO_RdCE3);
write_req <= (Bus2FIFO_WrCE1 or Bus2FIFO_WrCE2 or Bus2FIFO_WrCE3);
-- I/O assignments
FIFO2Bus_DBus <= bus_data_out;
FIFO2Bus_ToutSup <= LOGIC_LOW; -- output signal not currently used so
-- drive low .
FIFO2Bus_Retry <= LOGIC_LOW; -- output signal not currently used so
-- drive low.
FIFO2Bus_WrAck <= write_ack and write_req; -- connect the write
-- acknowledge (drive only
-- if a request is present)
FIFO2Bus_RdAck <= read_ack and read_req; -- connect the read
-- acknowledge (drive only if
-- a request is present)
FIFO2Bus_Error <= (sw_reset_error or
rd_access_error or
wr_access_error) and
(read_req or write_req);
FIFO2IRPT_DeadLock <= Deadlock;
BRAMFifo_RdReq <= Bus_RdReq and Bus2FIFO_RdCE3; -- Read Request to BRAM
-- based FIFO.
SRLFifo_RdReq <= reg_rdreq and Bus2FIFO_RdCE3; -- Read Request to SRL
-- based FIFO
Fifo_burst_rd_xfer <= burst_rd_xfer; -- Burst detect signal to FIFO read
-- controller
sig_srl_rdack <= SRLFifo_RdAck;
sig_bram_rdack <= BRAMFifo_RdAck;
------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- The FIFO data bus width is smaller than the IPIF data bus width so connect
-- the smaller FIFO data to LSB position of data bus to IPIF interface and
-- set the remaining data bus bits to zeroes.
-------------------------------------------------------------------------------
BUS_BIGGER_THAN_FIFO : if (C_IPIF_DBUS_WIDTH > C_FIFO_WIDTH) generate
CONNECT_DBUS : process (fifo_rd_data)
Begin
sig_fifo_rd_data <= (others => '0'); --default bus state
for j in 0 to C_FIFO_WIDTH-1 loop
sig_fifo_rd_data(C_IPIF_DBUS_WIDTH-C_FIFO_WIDTH+j)
<= fifo_rd_data(j);
End loop;
End process; -- CONNECT_DBUS
end generate BUS_BIGGER_THAN_FIFO;
-------------------------------------------------------------------------------
-- The FIFO data bus width is equal to the IPIF data bus width so connect
-- the FIFO data to IPIF data interface.
-------------------------------------------------------------------------------
BUS_EQUAL_TO_FIFO : if (C_IPIF_DBUS_WIDTH = C_FIFO_WIDTH) generate
sig_fifo_rd_data <= fifo_rd_data;
end generate BUS_EQUAL_TO_FIFO;
-------------------------------------------------------------------------------
-- The FIFO data bus width is bigger than the IPIF data bus width !!BAD!!!
-- Connect the LSBits of the FIFO data to the IPIF data bus interface,
-- Don't use (truncate) the MSBits of the FIFO data spilling over the IPIF
-- data bus width.
-------------------------------------------------------------------------------
BUS_SMALLER_THAN_FIFO : if (C_IPIF_DBUS_WIDTH < C_FIFO_WIDTH) generate
CONNECT_DBUS : process (fifo_rd_data)
Begin
for j in C_IPIF_DBUS_WIDTH-1 downto 0 loop
sig_fifo_rd_data(j) <= fifo_rd_data(C_FIFO_WIDTH-
C_IPIF_DBUS_WIDTH+j);
End loop;
End process; -- CONNECT_DBUS
end generate BUS_SMALLER_THAN_FIFO;
------------------------------------------------------------------------------
-- Register the input chip enables
------------------------------------------------------------------------------
REGISTER_CHIP_ENABLES : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
reg_rdce2 <= '0';
reg_wrce1 <= '0';
reg_rdreq <= '0';
reg_read_req <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
reg_rdce2 <= Bus2FIFO_RdCE2;
reg_wrce1 <= Bus2FIFO_WrCE1;
reg_rdreq <= Bus_RdReq;
reg_read_req <= read_req;
Else
null;
End if;
End process; -- REGISTER_CHIP_ENABLES
INCLUDE_BURST : if (C_SUPPORT_BURST = true) generate
--burst_rd_xfer <= reg_rdreq and Bus_RdReq;
-------------------------------------------------------------------------
-- This process detects the completion of at least one valid FIFO data
-- read cycle during a burst read.
-------------------------------------------------------------------------
GEN_ERRACK_INHIB : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
fifo_errack_inhibit <= '0';
burst_rd_xfer <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1' ) Then
burst_rd_xfer <= reg_rdreq and Bus_RdReq;
If (Bus2FIFO_RdCE3 = '1' and sig_bram_rdack = '1') Then
fifo_errack_inhibit <= '1';
Elsif (Bus2FIFO_RdCE3 = '1' and sig_srl_rdack = '1') Then
fifo_errack_inhibit <= '1';
Elsif (Bus2FIFO_RdCE3 = '0') Then
fifo_errack_inhibit <= '0';
else
null;
End if;
else
null;
End if;
End process; -- GEN_ERRACK_INHIB
end generate INCLUDE_BURST;
OMIT_BURST : if (C_SUPPORT_BURST = false) generate
burst_rd_xfer <= '0';
fifo_errack_inhibit <= '0';
end generate OMIT_BURST;
-------------------------------------------------------------------------------
-- Assemble and latch the FIFO status register fields
-------------------------------------------------------------------------------
GET_STATUS : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
reg_occupancy <= (others => '0');
reg_deadlock <= '0';
reg_almostempty <= '0';
reg_empty <= '1';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
If (reg_rdce2 = '1') Then -- hold last value registered during
-- read operation.
null;
else -- register new status every clock
reg_occupancy <= Occupancy ;
reg_deadlock <= Deadlock ;
reg_almostempty <= AlmostEmpty ;
reg_empty <= Empty ;
End if;
else
null; -- do nothing
End if;
End process; -- GET_STATUS
sig_rst_match <= Bus_DBus(C_IPIF_DBUS_WIDTH-4)
and not(Bus_DBus(C_IPIF_DBUS_WIDTH-3))
and Bus_DBus(C_IPIF_DBUS_WIDTH-2)
and not(Bus_DBus(C_IPIF_DBUS_WIDTH-1));
sig_rst_vect <= sig_rst_match & Bus2FIFO_WrCE1;
------------------------------------------------------------------------------
-- Generate the S/W reset as a result of an IPIF Bus write to register
-- port 1 and data on the DBus inputs matching the Reset match value.
------------------------------------------------------------------------------
GENERATE_SOFTWARE_RESET : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
Fifo_rst <= '1';
sw_reset_error <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
Case sig_rst_vect Is
When "11" =>
Fifo_rst <= '1';
sw_reset_error <= '0';
When "01" =>
Fifo_rst <= '0';
sw_reset_error <= '1';
When others =>
Fifo_rst <= '0';
sw_reset_error <= '0';
End case;
Else
null;
End if;
End process; -- GENERATE_SOFTWARE_RESET
-- Synthesis for MIR inclusion ------------------------------------------------
Include_MIR :if (C_MIR_ENABLE = True) generate
signal mir_value : std_logic_vector(0 to 31);
Signal mir_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
Signal status_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
begin
----------------------------------------------------------------------------
-- assemble the MIR fields from the Applicable Generics and Constants
-- Conversion to std_logic_vector is required
----------------------------------------------------------------------------
mir_value(0 to 3) <= CONV_STD_LOGIC_VECTOR(C_VERSION_MAJOR, 4);
mir_value(4 to 10) <= CONV_STD_LOGIC_VECTOR(C_VERSION_MINOR, 7);
mir_value(11 to 15) <= CONV_STD_LOGIC_VECTOR(C_VERSION_REV, 5);
mir_value(16 to 23) <= CONV_STD_LOGIC_VECTOR(C_BLOCK_ID, 8);
mir_value(24 to 31) <= CONV_STD_LOGIC_VECTOR(C_INTFC_TYPE, 8);
BUS_LEQ_32 : if (C_IPIF_DBUS_WIDTH <= 32) generate
begin
BUILD_MIR_BUS : process (mir_value)
Begin
for j in 0 to C_IPIF_DBUS_WIDTH-1 loop
mir_bus(j) <= mir_value((32-C_IPIF_DBUS_WIDTH)+j);
End loop;
End process; -- BUILD_MIR_BUS
end generate BUS_LEQ_32;
BUS_GT_32 : if (C_IPIF_DBUS_WIDTH > 32) generate
begin
BUILD_MIR_BUS : process (mir_value)
Begin
mir_bus <= (others => '0'); -- default bus values
for j in 0 to 31 loop
mir_bus((C_IPIF_DBUS_WIDTH-32)+j) <= mir_value(j);
End loop;
End process; -- BUILD_MIR_BUS
end generate BUS_GT_32;
----------------------------------------------------------------------------
-- The IPIF DBUS is larger than 32 bits in width. Place the 32 bit status
-- word on the 32 LSBits of the data bus.
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_BIG : if (C_IPIF_DBUS_WIDTH >= 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
-- set Encoded FIFO data width
--status_bus(C_IPIF_DBUS_WIDTH-28 to C_IPIF_DBUS_WIDTH-26)
-- <= CONV_STD_LOGIC_VECTOR(ENC_FIFO_WIDTH,3);
-- occupancy is not scaled
status_bus(C_IPIF_DBUS_WIDTH-29) <= '0' ;
status_bus(C_IPIF_DBUS_WIDTH-30) <= reg_deadlock ;
status_bus(C_IPIF_DBUS_WIDTH-31) <= reg_almostempty;
status_bus(C_IPIF_DBUS_WIDTH-32) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_BIG;
----------------------------------------------------------------------------
-- The IPIF DBUS is of sufficient width to contain the complete status
-- information so do not scale the occupancy value down.
-- Note status_bus bit 3 is not set, signaling a complete occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_FIT : if (C_IPIF_DBUS_WIDTH >= C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
-- set Encoded FIFO data width
--status_bus(4 to 6) <= CONV_STD_LOGIC_VECTOR(ENC_FIFO_WIDTH,3);
-- occupancy is not scaled
status_bus(3) <= '0' ;
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_FIT;
----------------------------------------------------------------------------
-- The IPIF DBUS is too narrow to contain the complete status information so
-- scale the occupancy value down until it fits in the available space.
-- Note status_bus bit 3 is now set, signaling a scaled occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_NO_FIT : if (C_IPIF_DBUS_WIDTH < C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
constant OCC_INDEX_END : Integer := (C_IPIF_DBUS_WIDTH-4)-1;
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
-- set Encoded FIFO data width
--status_bus(4 to 6) <= CONV_STD_LOGIC_VECTOR(ENC_FIFO_WIDTH,3);
-- Set Occupancy is scaled in this case
status_bus(3) <= '1';
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in 0 to OCC_INDEX_END loop
status_bus((C_IPIF_DBUS_WIDTH-1)-OCC_INDEX_END+j)
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_NO_FIT;
----------------------------------------------------------------------------
-- Mux the three read data sources to the IPIF Local Bus output port during
-- reads.
----------------------------------------------------------------------------
MUX_THE_OUTPUT_DATA : process (Bus2FIFO_RdCE3, Bus2FIFO_RdCE2,
Bus2FIFO_RdCE1, mir_bus, status_bus,
sig_fifo_rd_data, rd_vect, reg_read_req)
Begin
rd_vect <= reg_read_req & Bus2FIFO_RdCE3 &
Bus2FIFO_RdCE2 & Bus2FIFO_RdCE1;
Case rd_vect Is
When "1001" => -- Read MIR port
bus_data_out <= mir_bus;
When "1010" => -- Read Status port
bus_data_out <= status_bus;
When "1100" => -- Read FIFO data port
bus_data_out <= sig_fifo_rd_data;
When others => -- default to zeroes
bus_data_out <= (others => '0');
End case;
End process; -- MUX_THE_OUTPUT_DATA
----------------------------------------------------------------------------
-- Generate the Read Error Acknowledge Reply to the Bus when
-- an attempted read access by the IPIF Local Bus is invalid
----------------------------------------------------------------------------
GEN_RD_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rd_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_RdCE3 = '1' and Empty = '1' and
fifo_errack_inhibit = '0') Then -- attempting to read the
-- rdfifo with an empty
rd_access_error <= '1'; -- condition is an error,
-- but only on the
-- initiation of the read
Else
rd_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_RD_ERROR
end generate Include_MIR;
-------------------------------------------------------------------------------
-- Synthesis for MIR occlusion
-------------------------------------------------------------------------------
Occlude_MIR : if (C_MIR_ENABLE = False) generate
Signal status_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
begin
----------------------------------------------------------------------------
-- The IPIF DBUS is larger than 32 bits in width. Place the 32 bit status
-- word on the 32 LSBits of the data bus.
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_BIG : if (C_IPIF_DBUS_WIDTH >= 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(C_IPIF_DBUS_WIDTH-29) <= '0' ;
-- occupancy is not scaled in this case.
status_bus(C_IPIF_DBUS_WIDTH-30) <= reg_deadlock ;
status_bus(C_IPIF_DBUS_WIDTH-31) <= reg_almostempty ;
status_bus(C_IPIF_DBUS_WIDTH-32) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_BIG;
----------------------------------------------------------------------------
-- The IPIF DBUS is of sufficient width to contain the complete status
-- information so do not scale the occupancy value down.
-- Note status_bus bit 3 is not set, signaling a complete occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_FIT : if (C_IPIF_DBUS_WIDTH >= C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(3) <= '0' ; -- occupancy is not scaled
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_FIT;
----------------------------------------------------------------------------
-- The IPIF DBUS is too narrow to contain the complete status information so
-- scale the occupancy value down until it fits in the available space.
-- Note status_bus bit 3 is now set, signaling a scaled occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_NO_FIT : if (C_IPIF_DBUS_WIDTH < C_DP_ADDRESS_WIDTH+4) generate
constant OCC_INDEX_END : Integer := (C_IPIF_DBUS_WIDTH-4)-1;
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus(4 to C_IPIF_DBUS_WIDTH-1) <= (others => '0');
-- set default bus values
status_bus(3) <= '1' ;
-- Indicate occupancy is scaled to fit
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in 0 to OCC_INDEX_END loop
status_bus((C_IPIF_DBUS_WIDTH-1)-OCC_INDEX_END+j)
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_NO_FIT;
----------------------------------------------------------------------------
-- Mux the three read data sources to the IPIF Local Bus output port during
-- reads.
----------------------------------------------------------------------------
MUX_THE_OUTPUT_DATA : process (Bus2FIFO_RdCE3, Bus2FIFO_RdCE2,
Bus2FIFO_RdCE1, sig_fifo_rd_data,
status_bus, rd_vect, reg_read_req)
Begin
rd_vect <= reg_read_req & Bus2FIFO_RdCE3 &
Bus2FIFO_RdCE2 & Bus2FIFO_RdCE1;
Case rd_vect Is
When "1010" =>
bus_data_out <= status_bus;
When "1100" =>
bus_data_out <= sig_fifo_rd_data;
When others =>
bus_data_out <= (others => '0');
End case;
End process ; -- MUX_THE_OUTPUT_DATA
----------------------------------------------------------------------------
-- Generate the Read Error Acknowledge Reply to the Bus when
-- an attempted read access by the IPIF Local Bus is invalid
----------------------------------------------------------------------------
GEN_RD_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rd_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_RdCE1 = '1') Then -- attempting to read MIR but it
-- is not included
rd_access_error <= '1';
Elsif (Bus2FIFO_RdCE3 = '1' and Empty = '1' and
fifo_errack_inhibit = '0') Then -- attempting to read the
-- rdfifo with an empty
rd_access_error <= '1'; -- condition is an error,
-- but only on the
-- initiation of the read
Else
rd_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_RD_ERROR
end generate Occlude_MIR;
-------------------------------------------------------------------------------
-- Generate the Read Acknowledge to the Bus
-------------------------------------------------------------------------------
GEN_READ_ACK : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
reg_read_ack <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
If (Bus2FIFO_RdCE1 = '1' ) Then
reg_read_ack <= '1';
Elsif (Bus2FIFO_RdCE2 = '1' ) Then
reg_read_ack <= '1';
Elsif (Bus2FIFO_RdCE3 = '1') Then
reg_read_ack <= sig_bram_rdack;
else
reg_read_ack <= '0';
End if;
Else
null;
End if;
End process; -- GEN_READ_ACK
read_ack <= reg_read_ack
or rd_access_error
or sig_srl_rdack;
write_ack <= reg_wrce1 or wr_access_error;
-------------------------------------------------------------------------------
-- Generate the Write Error Acknowledge Reply to the Bus when
-- an attempted write access by the IPIF Local Bus is invalid
-------------------------------------------------------------------------------
--GEN_WR_ERROR : process (Bus2FIFO_WrCE2, Bus2FIFO_WrCE3)
GEN_WR_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
wr_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_WrCE2 = '1') Then -- attempting to write to the status
-- register.
wr_access_error <= '1';
ElsIf (Bus2FIFO_WrCE3 = '1') Then -- attempting a write to the FIFO
-- Read data port.
wr_access_error <= '1';
Else
wr_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_WR_ERROR
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: ipif_control_rd.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
--ipif_control_rd.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
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-- ** of this text at all times. **
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-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_control_rd.vhd
--
-- Description: This VHDL design file is for the Point Design of the Mauna
-- Loa Read Packet FIFO IPIF Local Bus Interface control
-- block.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_control_rd.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe March 19,2001 -- V1.00a
--
-- Doug Thorpe June 08-12,2001 -- V1.00b
-- - Corrected an error condition where the FIFO2Bus_Error was getting set
-- at the end of a legitimate burst read operation. If the RdFIFO goes
-- empty after the initiation of the read (at least one FIFO2Bus_RdAck
-- has been issued), an 'Empty' condition causes only an inhibit of the
-- FIFO2Bus_RdAck signal.
-- - Fixed the implimentation of the MIR inclusion/occlusion through the
-- use of if--generate clauses.
--
-- DET June 25, 2001 V1.00c
-- - Removed redundant logic assignments flagged by
-- Synplicity
--
-- DET July 20, 2001
-- - Changed the C_MIR_ENABLE type to Boolean from std_logic.
--
-- DET Aug 20, 2001 Version v1.01a
-- - Platform Generator Compliancy modifications
--
-- DET Sept 17, 2001
-- - Size optimization changes
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
entity ipif_control_rd is
Generic (
C_MIR_ENABLE : Boolean := true;
-- Enable for MIR synthesis (default for disable)
C_BLOCK_ID : integer range 0 to 255 := 255;
-- Platform Generator assigned ID number
C_INTFC_TYPE : integer range 0 to 31 := 1;
-- IPIF block protocol Type
C_VERSION_MAJOR : integer range 0 to 9 := 1;
-- Major versioning of top level design
C_VERSION_MINOR : integer range 0 to 99 := 2;
-- Minor Version of top level design
C_VERSION_REV : integer range 0 to 26 := 0;
-- Revision letter of top level design
C_FIFO_WIDTH : Integer := 32;
-- Width of FIFO data in bits
C_DP_ADDRESS_WIDTH : Integer := 9;
-- Indicates address width of RdFIFO memory
-- (= log2(fifo_depth)
C_SUPPORT_BURST : Boolean := true;
-- Indicates read burst support for the IPIF bus
C_IPIF_DBUS_WIDTH : Integer := 32
-- Width of the IPIF data bus in bits
);
port (
-- Inputs From the IPIF Bus
Bus_rst : In std_logic; -- Master Reset from the IPIF
Bus_Clk : In std_logic; -- Master timing clock from the IPIF
Bus_RdReq : In std_logic;
Bus_WrReq : In std_logic;
Bus2FIFO_RdCE1 : In std_logic;
Bus2FIFO_RdCE2 : In std_logic;
Bus2FIFO_RdCE3 : In std_logic;
Bus2FIFO_WrCE1 : In std_logic;
Bus2FIFO_WrCE2 : In std_logic;
Bus2FIFO_WrCE3 : In std_logic;
Bus_DBus : In std_logic_vector(C_IPIF_DBUS_WIDTH-4 to
C_IPIF_DBUS_WIDTH-1);
-- Inputs from the FIFO Interface Logic
Fifo_rd_data : In std_logic_vector(0 to C_FIFO_WIDTH-1);
BRAMFifo_RdAck : In std_logic;
SRLFifo_RdAck : In std_logic;
Occupancy : In std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
AlmostEmpty : In std_logic;
Empty : In std_logic;
Deadlock : In std_logic;
-- Outputs to the FIFO
Fifo_rst : Out std_logic;
BRAMFifo_RdReq : Out std_logic;
SRLFifo_RdReq : Out std_logic;
Fifo_burst_rd_xfer : Out std_logic;
-- Outputs to the IPIF Bus
FIFO2IRPT_DeadLock : Out std_logic;
FIFO2Bus_DBus : Out std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
FIFO2Bus_WrAck : Out std_logic;
FIFO2Bus_RdAck : Out std_logic;
FIFO2Bus_Error : Out std_logic;
FIFO2Bus_Retry : Out std_logic;
FIFO2Bus_ToutSup : Out std_logic
);
end ipif_control_rd ;
-------------------------------------------------------------------------------
architecture implementation of ipif_control_rd is
-- FUNCTIONS
-----------------------------------------------------------------------------
-- Function set_fwidth
--
-- This function is used to set the value of FIFO width status
-- field based on the setting of the width parameter.
-----------------------------------------------------------------------------
function set_fwidth (fifo_width : integer) return integer is
constant byte_lane_num : Integer := (fifo_width+7)/8;
Variable enc_size : Integer := 0;
begin
case byte_lane_num is
when 0|1 =>
enc_size := 1;
when 2 =>
enc_size := 2;
when 3 | 4 =>
enc_size := 3;
when 5|6|7|8 =>
enc_size := 4;
When 9|10|11|12|13|14|15|16 =>
enc_size := 5;
when others =>
enc_size := 6;
end case;
return(enc_size);
end function set_fwidth;
-- COMPONENTS
-- No components
--TYPES
-- no types
-- CONSTANTS
-- Module Software Reset screen value for write data
Constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- This requires a Hex 'A' to be written
-- to ativate the S/W reset port
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- Bus Width Matching constant
Constant ENC_FIFO_WIDTH : integer := set_fwidth(C_FIFO_WIDTH);
--INTERNAL SIGNALS
signal bus_data_out : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
Signal sw_reset_error : std_logic;
signal reg_occupancy : std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Signal reg_almostempty : std_logic;
Signal reg_empty : std_logic;
Signal reg_deadlock : std_logic;
Signal reg_rdce2 : std_logic;
Signal reg_wrce1 : std_logic;
Signal reg_rdreq : std_logic;
Signal read_ack : std_logic;
Signal reg_read_ack : std_logic;
Signal write_ack : std_logic;
Signal rd_access_error : std_logic;
Signal wr_access_error : std_logic;
Signal burst_rd_xfer : std_logic;
Signal read_req : std_logic;
Signal reg_read_req : std_logic;
Signal write_req : std_logic;
Signal fifo_rd_req : std_logic;
Signal fifo_errack_inhibit : std_logic;
Signal rd_vect : std_logic_vector(0 to 3);
Signal sig_srl_rdack : std_logic;
Signal sig_bram_rdack : std_logic;
Signal sig_rst_match : std_logic;
Signal sig_rst_vect : std_logic_vector(0 to 1);
Signal sig_fifo_rd_data : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
-------------------------------------------------------------------------------
---------- start architecture logic -------------------------------------------
begin
-- General access detection (used to terminate reply signal to the Bus)
read_req <= (Bus2FIFO_RdCE1 or Bus2FIFO_RdCE2 or Bus2FIFO_RdCE3);
write_req <= (Bus2FIFO_WrCE1 or Bus2FIFO_WrCE2 or Bus2FIFO_WrCE3);
-- I/O assignments
FIFO2Bus_DBus <= bus_data_out;
FIFO2Bus_ToutSup <= LOGIC_LOW; -- output signal not currently used so
-- drive low .
FIFO2Bus_Retry <= LOGIC_LOW; -- output signal not currently used so
-- drive low.
FIFO2Bus_WrAck <= write_ack and write_req; -- connect the write
-- acknowledge (drive only
-- if a request is present)
FIFO2Bus_RdAck <= read_ack and read_req; -- connect the read
-- acknowledge (drive only if
-- a request is present)
FIFO2Bus_Error <= (sw_reset_error or
rd_access_error or
wr_access_error) and
(read_req or write_req);
FIFO2IRPT_DeadLock <= Deadlock;
BRAMFifo_RdReq <= Bus_RdReq and Bus2FIFO_RdCE3; -- Read Request to BRAM
-- based FIFO.
SRLFifo_RdReq <= reg_rdreq and Bus2FIFO_RdCE3; -- Read Request to SRL
-- based FIFO
Fifo_burst_rd_xfer <= burst_rd_xfer; -- Burst detect signal to FIFO read
-- controller
sig_srl_rdack <= SRLFifo_RdAck;
sig_bram_rdack <= BRAMFifo_RdAck;
------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- The FIFO data bus width is smaller than the IPIF data bus width so connect
-- the smaller FIFO data to LSB position of data bus to IPIF interface and
-- set the remaining data bus bits to zeroes.
-------------------------------------------------------------------------------
BUS_BIGGER_THAN_FIFO : if (C_IPIF_DBUS_WIDTH > C_FIFO_WIDTH) generate
CONNECT_DBUS : process (fifo_rd_data)
Begin
sig_fifo_rd_data <= (others => '0'); --default bus state
for j in 0 to C_FIFO_WIDTH-1 loop
sig_fifo_rd_data(C_IPIF_DBUS_WIDTH-C_FIFO_WIDTH+j)
<= fifo_rd_data(j);
End loop;
End process; -- CONNECT_DBUS
end generate BUS_BIGGER_THAN_FIFO;
-------------------------------------------------------------------------------
-- The FIFO data bus width is equal to the IPIF data bus width so connect
-- the FIFO data to IPIF data interface.
-------------------------------------------------------------------------------
BUS_EQUAL_TO_FIFO : if (C_IPIF_DBUS_WIDTH = C_FIFO_WIDTH) generate
sig_fifo_rd_data <= fifo_rd_data;
end generate BUS_EQUAL_TO_FIFO;
-------------------------------------------------------------------------------
-- The FIFO data bus width is bigger than the IPIF data bus width !!BAD!!!
-- Connect the LSBits of the FIFO data to the IPIF data bus interface,
-- Don't use (truncate) the MSBits of the FIFO data spilling over the IPIF
-- data bus width.
-------------------------------------------------------------------------------
BUS_SMALLER_THAN_FIFO : if (C_IPIF_DBUS_WIDTH < C_FIFO_WIDTH) generate
CONNECT_DBUS : process (fifo_rd_data)
Begin
for j in C_IPIF_DBUS_WIDTH-1 downto 0 loop
sig_fifo_rd_data(j) <= fifo_rd_data(C_FIFO_WIDTH-
C_IPIF_DBUS_WIDTH+j);
End loop;
End process; -- CONNECT_DBUS
end generate BUS_SMALLER_THAN_FIFO;
------------------------------------------------------------------------------
-- Register the input chip enables
------------------------------------------------------------------------------
REGISTER_CHIP_ENABLES : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
reg_rdce2 <= '0';
reg_wrce1 <= '0';
reg_rdreq <= '0';
reg_read_req <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
reg_rdce2 <= Bus2FIFO_RdCE2;
reg_wrce1 <= Bus2FIFO_WrCE1;
reg_rdreq <= Bus_RdReq;
reg_read_req <= read_req;
Else
null;
End if;
End process; -- REGISTER_CHIP_ENABLES
INCLUDE_BURST : if (C_SUPPORT_BURST = true) generate
--burst_rd_xfer <= reg_rdreq and Bus_RdReq;
-------------------------------------------------------------------------
-- This process detects the completion of at least one valid FIFO data
-- read cycle during a burst read.
-------------------------------------------------------------------------
GEN_ERRACK_INHIB : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
fifo_errack_inhibit <= '0';
burst_rd_xfer <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1' ) Then
burst_rd_xfer <= reg_rdreq and Bus_RdReq;
If (Bus2FIFO_RdCE3 = '1' and sig_bram_rdack = '1') Then
fifo_errack_inhibit <= '1';
Elsif (Bus2FIFO_RdCE3 = '1' and sig_srl_rdack = '1') Then
fifo_errack_inhibit <= '1';
Elsif (Bus2FIFO_RdCE3 = '0') Then
fifo_errack_inhibit <= '0';
else
null;
End if;
else
null;
End if;
End process; -- GEN_ERRACK_INHIB
end generate INCLUDE_BURST;
OMIT_BURST : if (C_SUPPORT_BURST = false) generate
burst_rd_xfer <= '0';
fifo_errack_inhibit <= '0';
end generate OMIT_BURST;
-------------------------------------------------------------------------------
-- Assemble and latch the FIFO status register fields
-------------------------------------------------------------------------------
GET_STATUS : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
reg_occupancy <= (others => '0');
reg_deadlock <= '0';
reg_almostempty <= '0';
reg_empty <= '1';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
If (reg_rdce2 = '1') Then -- hold last value registered during
-- read operation.
null;
else -- register new status every clock
reg_occupancy <= Occupancy ;
reg_deadlock <= Deadlock ;
reg_almostempty <= AlmostEmpty ;
reg_empty <= Empty ;
End if;
else
null; -- do nothing
End if;
End process; -- GET_STATUS
sig_rst_match <= Bus_DBus(C_IPIF_DBUS_WIDTH-4)
and not(Bus_DBus(C_IPIF_DBUS_WIDTH-3))
and Bus_DBus(C_IPIF_DBUS_WIDTH-2)
and not(Bus_DBus(C_IPIF_DBUS_WIDTH-1));
sig_rst_vect <= sig_rst_match & Bus2FIFO_WrCE1;
------------------------------------------------------------------------------
-- Generate the S/W reset as a result of an IPIF Bus write to register
-- port 1 and data on the DBus inputs matching the Reset match value.
------------------------------------------------------------------------------
GENERATE_SOFTWARE_RESET : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
Fifo_rst <= '1';
sw_reset_error <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
Case sig_rst_vect Is
When "11" =>
Fifo_rst <= '1';
sw_reset_error <= '0';
When "01" =>
Fifo_rst <= '0';
sw_reset_error <= '1';
When others =>
Fifo_rst <= '0';
sw_reset_error <= '0';
End case;
Else
null;
End if;
End process; -- GENERATE_SOFTWARE_RESET
-- Synthesis for MIR inclusion ------------------------------------------------
Include_MIR :if (C_MIR_ENABLE = True) generate
signal mir_value : std_logic_vector(0 to 31);
Signal mir_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
Signal status_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
begin
----------------------------------------------------------------------------
-- assemble the MIR fields from the Applicable Generics and Constants
-- Conversion to std_logic_vector is required
----------------------------------------------------------------------------
mir_value(0 to 3) <= CONV_STD_LOGIC_VECTOR(C_VERSION_MAJOR, 4);
mir_value(4 to 10) <= CONV_STD_LOGIC_VECTOR(C_VERSION_MINOR, 7);
mir_value(11 to 15) <= CONV_STD_LOGIC_VECTOR(C_VERSION_REV, 5);
mir_value(16 to 23) <= CONV_STD_LOGIC_VECTOR(C_BLOCK_ID, 8);
mir_value(24 to 31) <= CONV_STD_LOGIC_VECTOR(C_INTFC_TYPE, 8);
BUS_LEQ_32 : if (C_IPIF_DBUS_WIDTH <= 32) generate
begin
BUILD_MIR_BUS : process (mir_value)
Begin
for j in 0 to C_IPIF_DBUS_WIDTH-1 loop
mir_bus(j) <= mir_value((32-C_IPIF_DBUS_WIDTH)+j);
End loop;
End process; -- BUILD_MIR_BUS
end generate BUS_LEQ_32;
BUS_GT_32 : if (C_IPIF_DBUS_WIDTH > 32) generate
begin
BUILD_MIR_BUS : process (mir_value)
Begin
mir_bus <= (others => '0'); -- default bus values
for j in 0 to 31 loop
mir_bus((C_IPIF_DBUS_WIDTH-32)+j) <= mir_value(j);
End loop;
End process; -- BUILD_MIR_BUS
end generate BUS_GT_32;
----------------------------------------------------------------------------
-- The IPIF DBUS is larger than 32 bits in width. Place the 32 bit status
-- word on the 32 LSBits of the data bus.
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_BIG : if (C_IPIF_DBUS_WIDTH >= 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
-- set Encoded FIFO data width
--status_bus(C_IPIF_DBUS_WIDTH-28 to C_IPIF_DBUS_WIDTH-26)
-- <= CONV_STD_LOGIC_VECTOR(ENC_FIFO_WIDTH,3);
-- occupancy is not scaled
status_bus(C_IPIF_DBUS_WIDTH-29) <= '0' ;
status_bus(C_IPIF_DBUS_WIDTH-30) <= reg_deadlock ;
status_bus(C_IPIF_DBUS_WIDTH-31) <= reg_almostempty;
status_bus(C_IPIF_DBUS_WIDTH-32) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_BIG;
----------------------------------------------------------------------------
-- The IPIF DBUS is of sufficient width to contain the complete status
-- information so do not scale the occupancy value down.
-- Note status_bus bit 3 is not set, signaling a complete occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_FIT : if (C_IPIF_DBUS_WIDTH >= C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
-- set Encoded FIFO data width
--status_bus(4 to 6) <= CONV_STD_LOGIC_VECTOR(ENC_FIFO_WIDTH,3);
-- occupancy is not scaled
status_bus(3) <= '0' ;
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_FIT;
----------------------------------------------------------------------------
-- The IPIF DBUS is too narrow to contain the complete status information so
-- scale the occupancy value down until it fits in the available space.
-- Note status_bus bit 3 is now set, signaling a scaled occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_NO_FIT : if (C_IPIF_DBUS_WIDTH < C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
constant OCC_INDEX_END : Integer := (C_IPIF_DBUS_WIDTH-4)-1;
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
-- set Encoded FIFO data width
--status_bus(4 to 6) <= CONV_STD_LOGIC_VECTOR(ENC_FIFO_WIDTH,3);
-- Set Occupancy is scaled in this case
status_bus(3) <= '1';
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in 0 to OCC_INDEX_END loop
status_bus((C_IPIF_DBUS_WIDTH-1)-OCC_INDEX_END+j)
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_NO_FIT;
----------------------------------------------------------------------------
-- Mux the three read data sources to the IPIF Local Bus output port during
-- reads.
----------------------------------------------------------------------------
MUX_THE_OUTPUT_DATA : process (Bus2FIFO_RdCE3, Bus2FIFO_RdCE2,
Bus2FIFO_RdCE1, mir_bus, status_bus,
sig_fifo_rd_data, rd_vect, reg_read_req)
Begin
rd_vect <= reg_read_req & Bus2FIFO_RdCE3 &
Bus2FIFO_RdCE2 & Bus2FIFO_RdCE1;
Case rd_vect Is
When "1001" => -- Read MIR port
bus_data_out <= mir_bus;
When "1010" => -- Read Status port
bus_data_out <= status_bus;
When "1100" => -- Read FIFO data port
bus_data_out <= sig_fifo_rd_data;
When others => -- default to zeroes
bus_data_out <= (others => '0');
End case;
End process; -- MUX_THE_OUTPUT_DATA
----------------------------------------------------------------------------
-- Generate the Read Error Acknowledge Reply to the Bus when
-- an attempted read access by the IPIF Local Bus is invalid
----------------------------------------------------------------------------
GEN_RD_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rd_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_RdCE3 = '1' and Empty = '1' and
fifo_errack_inhibit = '0') Then -- attempting to read the
-- rdfifo with an empty
rd_access_error <= '1'; -- condition is an error,
-- but only on the
-- initiation of the read
Else
rd_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_RD_ERROR
end generate Include_MIR;
-------------------------------------------------------------------------------
-- Synthesis for MIR occlusion
-------------------------------------------------------------------------------
Occlude_MIR : if (C_MIR_ENABLE = False) generate
Signal status_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
begin
----------------------------------------------------------------------------
-- The IPIF DBUS is larger than 32 bits in width. Place the 32 bit status
-- word on the 32 LSBits of the data bus.
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_BIG : if (C_IPIF_DBUS_WIDTH >= 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(C_IPIF_DBUS_WIDTH-29) <= '0' ;
-- occupancy is not scaled in this case.
status_bus(C_IPIF_DBUS_WIDTH-30) <= reg_deadlock ;
status_bus(C_IPIF_DBUS_WIDTH-31) <= reg_almostempty ;
status_bus(C_IPIF_DBUS_WIDTH-32) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_BIG;
----------------------------------------------------------------------------
-- The IPIF DBUS is of sufficient width to contain the complete status
-- information so do not scale the occupancy value down.
-- Note status_bus bit 3 is not set, signaling a complete occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_FIT : if (C_IPIF_DBUS_WIDTH >= C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(3) <= '0' ; -- occupancy is not scaled
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_FIT;
----------------------------------------------------------------------------
-- The IPIF DBUS is too narrow to contain the complete status information so
-- scale the occupancy value down until it fits in the available space.
-- Note status_bus bit 3 is now set, signaling a scaled occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_NO_FIT : if (C_IPIF_DBUS_WIDTH < C_DP_ADDRESS_WIDTH+4) generate
constant OCC_INDEX_END : Integer := (C_IPIF_DBUS_WIDTH-4)-1;
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus(4 to C_IPIF_DBUS_WIDTH-1) <= (others => '0');
-- set default bus values
status_bus(3) <= '1' ;
-- Indicate occupancy is scaled to fit
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in 0 to OCC_INDEX_END loop
status_bus((C_IPIF_DBUS_WIDTH-1)-OCC_INDEX_END+j)
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_NO_FIT;
----------------------------------------------------------------------------
-- Mux the three read data sources to the IPIF Local Bus output port during
-- reads.
----------------------------------------------------------------------------
MUX_THE_OUTPUT_DATA : process (Bus2FIFO_RdCE3, Bus2FIFO_RdCE2,
Bus2FIFO_RdCE1, sig_fifo_rd_data,
status_bus, rd_vect, reg_read_req)
Begin
rd_vect <= reg_read_req & Bus2FIFO_RdCE3 &
Bus2FIFO_RdCE2 & Bus2FIFO_RdCE1;
Case rd_vect Is
When "1010" =>
bus_data_out <= status_bus;
When "1100" =>
bus_data_out <= sig_fifo_rd_data;
When others =>
bus_data_out <= (others => '0');
End case;
End process ; -- MUX_THE_OUTPUT_DATA
----------------------------------------------------------------------------
-- Generate the Read Error Acknowledge Reply to the Bus when
-- an attempted read access by the IPIF Local Bus is invalid
----------------------------------------------------------------------------
GEN_RD_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rd_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_RdCE1 = '1') Then -- attempting to read MIR but it
-- is not included
rd_access_error <= '1';
Elsif (Bus2FIFO_RdCE3 = '1' and Empty = '1' and
fifo_errack_inhibit = '0') Then -- attempting to read the
-- rdfifo with an empty
rd_access_error <= '1'; -- condition is an error,
-- but only on the
-- initiation of the read
Else
rd_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_RD_ERROR
end generate Occlude_MIR;
-------------------------------------------------------------------------------
-- Generate the Read Acknowledge to the Bus
-------------------------------------------------------------------------------
GEN_READ_ACK : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
reg_read_ack <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
If (Bus2FIFO_RdCE1 = '1' ) Then
reg_read_ack <= '1';
Elsif (Bus2FIFO_RdCE2 = '1' ) Then
reg_read_ack <= '1';
Elsif (Bus2FIFO_RdCE3 = '1') Then
reg_read_ack <= sig_bram_rdack;
else
reg_read_ack <= '0';
End if;
Else
null;
End if;
End process; -- GEN_READ_ACK
read_ack <= reg_read_ack
or rd_access_error
or sig_srl_rdack;
write_ack <= reg_wrce1 or wr_access_error;
-------------------------------------------------------------------------------
-- Generate the Write Error Acknowledge Reply to the Bus when
-- an attempted write access by the IPIF Local Bus is invalid
-------------------------------------------------------------------------------
--GEN_WR_ERROR : process (Bus2FIFO_WrCE2, Bus2FIFO_WrCE3)
GEN_WR_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
wr_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_WrCE2 = '1') Then -- attempting to write to the status
-- register.
wr_access_error <= '1';
ElsIf (Bus2FIFO_WrCE3 = '1') Then -- attempting a write to the FIFO
-- Read data port.
wr_access_error <= '1';
Else
wr_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_WR_ERROR
end implementation;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:59:58 11/21/2015
-- Design Name:
-- Module Name: parte_operativa - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-- Prodotto m*n
entity parte_operativa is
generic ( n : natural := 4;
m : natural := 4);
Port ( X : in STD_LOGIC_VECTOR (n-1 downto 0);
Y : in STD_LOGIC_VECTOR (m-1 downto 0);
load_a : in STD_LOGIC;
load_q : in STD_LOGIC;
load_m : in STD_LOGIC;
reset_n : in STD_LOGIC;
shift : in STD_LOGIC;
sub : in STD_LOGIC;
clock : in STD_LOGIC;
q0 : out STD_LOGIC;
q_1 : out STD_LOGIC;
P : out STD_LOGIC_VECTOR (n+m-1 downto 0)
);
end parte_operativa;
architecture Structural of parte_operativa is
COMPONENT register_n_bit
generic (n : natural := 8;
delay : time := 0 ns);
Port ( I : in STD_LOGIC_VECTOR (n-1 downto 0);
clock : in STD_LOGIC;
load : in STD_LOGIC;
reset_n : in STD_LOGIC;
O : out STD_LOGIC_VECTOR (n-1 downto 0));
END COMPONENT;
COMPONENT add_sub
generic ( n : natural := 4);
Port ( A : in STD_LOGIC_VECTOR (n-1 downto 0);
B : in STD_LOGIC_VECTOR (n-1 downto 0);
subtract : in STD_LOGIC;
ovfl : out STD_LOGIC;
S : out STD_LOGIC_VECTOR (n-1 downto 0));
END COMPONENT;
COMPONENT shift_register_n_bit
generic (n : natural := 8;
delay : time := 0 ns);
Port (D_IN : in STD_LOGIC_VECTOR (n-1 downto 0);
clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
load : in STD_LOGIC;
shift : in STD_LOGIC;
lt_rt : in STD_LOGIC;
sh_in : in STD_LOGIC;
sh_out : out STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (n-1 downto 0));
END COMPONENT;
signal ingresso_a, uscita_a, moltiplicando : std_logic_vector(n-1 downto 0) := (others => '0');
signal uscita_q : std_logic_vector(m-1 downto 0) := (others => '0');
signal q_1_sig, sh_out_a_q : std_logic := '0';
alias AI is ingresso_a;
alias AU is uscita_a;
alias QU is uscita_q;
alias QU0 is uscita_q(0);
alias QU_1 is q_1_sig;
begin
P <= (AU & QU);
q0 <= QU0;
q_1 <= QU_1;
registro_moltiplicando : register_n_bit
generic map(n)
PORT MAP(I => X, clock => clock, load => load_m, reset_n => reset_n,
O => moltiplicando);
a : shift_register_n_bit
generic map(n)
PORT MAP(D_IN => AI, clock => clock, reset_n => reset_n, load => load_a, shift => shift,
lt_rt => '1', sh_in => uscita_a(n-1), sh_out => sh_out_a_q , D_OUT => AU);
q : shift_register_n_bit
generic map(m)
PORT MAP(D_IN=> Y, clock => clock, reset_n => reset_n, load => load_q, shift => shift,
lt_rt => '1', sh_in => sh_out_a_q, sh_out => q_1_sig, D_OUT => QU);
adder_subtracter : add_sub
generic map(n)
PORT MAP(A => AU, B => moltiplicando, subtract => sub, ovfl => open, S => AI);
end Structural;
|
-------------------------------------------------------------------
--
-- Fichero:
-- damero.vhd 12/7/2013
--
-- (c) J.M. Mendias
-- Diseño Automático de Sistemas
-- Facultad de Informática. Universidad Complutense de Madrid
--
-- Propósito:
-- Muestra un damero sobre un monitor compatible VGA
--
-- Notas de diseño:
-- La sincronización con la pantalla VGA presupone que la
-- frecuencia de reloj del sistema es de 50 MHz
--
-------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
library UNISIM;
use UNISIM.vcomponents.all;
ENTITY tron IS
PORT (
rst: IN std_logic;
clk: IN std_logic;
ps2Data : IN std_logic;
ps2Clk : IN std_logic;
hSyncQ : OUT std_logic;
vSyncQ : OUT std_logic;
RGBQ : OUT std_logic_vector(8 DOWNTO 0)
);
END tron;
ARCHITECTURE tronArch OF tron IS
-- MEMORIA DE REFRESCO
component RAMB16_S1_s1
generic(
WRITE_MODE_A : string := "READ_FIRST";
WRITE_MODE_B : string := "READ_FIRST"
);
port(
DOA0: out std_logic; -- Salida de datos
DOB0: out std_logic;
ADDRA: in std_logic_vector(13 downto 0); -- Direccion
ADDRB: in std_logic_vector(13 downto 0);
CLKA: in std_ulogic; -- Reloj
CLKB: in std_ulogic;
DIA0: in std_logic; -- Entrada de datos
DIB0: in std_logic;
ENA: in std_ulogic; -- Entrada capacitacion
ENB: in std_ulogic;
SSRA: in std_ulogic; -- Inicializacion sincrona para los latches de salida
SSRB: in std_ulogic;
WEA: in std_ulogic; -- Entrada capacitacion escritura
WEB: in std_ulogic
);
end component;
-- SEÑALES VGA
signal pixelCntOut: std_logic_vector(10 downto 0);
signal lineCntOut: std_logic_vector(9 downto 0);
signal blanking, valor: std_logic;
-- SEÑALES PARA PINTAR
signal hSync, vSync : std_logic;
signal RGB : std_logic_vector(8 downto 0);
signal salidaRojo, salidaAzul : std_logic;
signal motoAzul, estelaAzul, motoRoja, estelaRoja : std_logic;
-- MEMORIA DE REFRESCO
signal dirRefrescoVGA, dirEscrituraAzul, dirTrayectoAzul, dirEscrituraRoja, dirTrayectoRoja: std_logic_vector(14 downto 0);
signal readFirstAzul1,DOB0,readFirstAzul2,DOB1,readFirstRoja1,DOB2,readFirstRoja2,DOB3 : std_logic;
signal valorEscritura , enableEscritura: std_logic;
-- LIMPIEZA DE LA MEMORIA
signal limpiarMemoria,limpiezaCompletada : std_logic;
signal csCiclosLimpieza: std_logic_vector(22 downto 0);
-- CONTADORES MOTOS: PELOTA
signal csMotoAzulY: std_logic_vector(6 downto 0); -- 7 bits
signal csMotoAzulX: std_logic_vector(7 downto 0); -- 8 bits
signal csMotoRojaY: std_logic_vector(6 downto 0);
signal csMotoRojaX: std_logic_vector(7 downto 0);
-- CONTROL DIRECCION DE LAS MOTOS
type DIR_MOTO is (ARRIBA, ABAJO, IZQUIERDA, DERECHA);
signal dirMotoAzul, dirMotoAzulNext, dirMotoRoja, dirMotoRojaNext: DIR_MOTO;
-- RALENTIZADOR
signal csRalentizador : std_logic_vector(22 downto 0);
signal mueve : std_logic;
-- VARIABLES DE JUEGO
signal hayGanador, partidaEnCurso, iniciarMotos : std_logic;
signal choqueContrario, choquePropioAzul, choquePropioRoja : std_logic;
-- INTERFAZ TECLADO PS/2
signal data : std_logic_vector (7 DOWNTO 0); -- Salida de datos paralela
signal newData : std_logic; -- Indica la recepción de un nuevo dato por la línea PS2
signal newDataAck : std_logic; -- Reconoce la recepción del nuevo dato
signal ldData, validData, lastBitRcv, ps2ClkSync, ps2ClkFallingEdge: std_logic;
signal ps2DataRegOut: std_logic_vector(10 downto 0);
signal goodParity: std_logic;
-- MAQUINA DE ESTADOS PARA EL CONTROL DE TECLAS
type ESTADOS is (WAITING_PRESS, RELEASE_BUTTON);
signal ESTADO, SIG_ESTADO: ESTADOS;
signal flagSPC, flagSPCnext : std_logic;
-- MAQUINA DE ESTADOS PARA EL CONTROL DEL JUEGO
type GAME_STATES is (WAITING_SPACE, INITIALIZING_GAME, WAITING_WINNER);
signal GAME, NEXT_GAME: GAME_STATES;
BEGIN
pixelCnt:
PROCESS( rst, clk )
BEGIN
IF (rst='0') THEN
pixelCntOut <= (OTHERS=>'0');
ELSIF(clk'EVENT AND clk='1') THEN
IF (pixelCntOut=1588) THEN
pixelCntOut <= (OTHERS=>'0');
ELSE
pixelCntOut <= pixelCntOut+1;
END IF;
END IF;
END PROCESS pixelCnt;
lineCnt:
PROCESS( rst, clk )
BEGIN
IF (rst='0') THEN
lineCntOut <= (OTHERS=>'0');
ELSIF (clk'EVENT AND clk='1') THEN
IF (pixelCntOut=1588) THEN
IF (lineCntOut=527) THEN
lineCntOut <= (others=>'0');
ELSE
lineCntOut <= lineCntOut+1;
END IF;
END IF;
END IF;
END PROCESS lineCnt;
hSync <= '0' WHEN (pixelCntOut > 1304) AND (pixelCntOut <= 1493) ELSE '1';
vSync <= '0' WHEN (lineCntOut > 493) AND (lineCntOut <= 495) ELSE '1';
blanking <= '1' WHEN (pixelCntOut > 1257) OR (lineCntOut > 479) ELSE '0';
--RGB <= salidaRojo & salidaRojo & salidaRojo & '0' & '0' & '0' & salidaAzul & salidaAzul & salidaAzul;
RGB <= salidaAzul & salidaAzul & salidaAzul & '0' & '0' & '0' & salidaRojo & salidaRojo & salidaRojo;
-------------------------------------------------------------------------------------
-- INTRODUCIR CODIGO DESDE AQUI
-- | | | | |
-- v v v v v
-- COMO VA EL LINECOUNT PARA HACER LINEAS MAS GORDAS:
-- 0100
-- 0101
-- 0110
-- 0111
-- 1100 -> Hay que fijarse cuales son los bits comunes para ir
-- 1101 diviendo entre 2. (Con esto, son numeros modulo 2, 4, 8 .. etc)
-- 1110
-- 1111
-- INSTACIAMOS MEMORIA REFRESCO
-- *******************************************************************************
-- Usar una memoria de doble puerto:
-- * los coches almacenan su estela por un puerto (úsese también para borrar estelas)
-- * el refresco se realiza leyendo desde el otro => (Escritura => A y Lectura => B)
-- * para evitar conflictos de lectura y escritura simultánea configurarla en modo READ_FIRST
-- Para simplificar la lógica de direccionamiento (a costa de desperdiciar memoria) usar
-- una de 32Kx2b organizada en 2 slices: uno para el coche rojo y otro para el azul
-- * la dirección de un pixel se obtiene concatenado parte de lineCnt con parte de pixelCnt
-- * usar 4 RAM Blocks de 16 K×1b
-- * Usaremos 2 memorias para cada moto para poder direccionar toda la pantalla.
-- * PxCountMax => 152 px = 8 bits / LineCountMax => 119 px = 7 bits ==> 15 bits
-- * Direccionamos hasta la linea 63 en la primera memoria y de la 64 a la 119 en la segunda memoria
-- * Para distinguir la primera memoria de la segunda usamos bit mas significativo (el de la pos 14 que indica el 64)
-- Para el refresco de la pantalla, leeremos por el puerto B la direccion resultante de
-- concatenar una parte de lineCnt con parte de PixelCnt
dirRefrescoVGA <= lineCntOut(8 downto 2) & pixelCntOut(10 downto 3);
-- Para guardar en memoria la estela azul, usamos como direccion la concatenacion de la
-- coordenada Y (lineCnt) y la X (pixelCnt)
dirTrayectoAzul <= csMotoAzulY & csMotoAzulX;
dirTrayectoRoja <= csMotoRojaY & csMotoRojaX;
-- MEMORIAS MOTO AZUL
-- ···········································································
enableEscritura <= mueve OR limpiarMemoria;
memAzul_1: RAMB16_S1_s1
port map(
readFirstAzul1, -- Salida de Datos (A - Escritura) - Sirve para saber si chocamos contra nuestra propia estela.
DOB0, -- Salida de Datos (B - Lectura)
dirEscrituraAzul(13 downto 0), -- Direccion de escritura (A): Durante el juego es la posicion de la moto y durante la limpieza el Px/ln count
dirRefrescoVGA(13 downto 0), -- Direccion de lectura (B)
clk, -- Mismo reloj para ambos puertos
clk,
valorEscritura, -- Sera 1 durante el juego y 0 durante la limpieza de la memoria
'0', -- Nunca escribimos por el puerto B, asi que ponemos 0 como valor Din por poner algo
not dirEscrituraAzul(14), -- ENABLE A: El modulo de escritura estara activo cuando el lineCnt sea menor que 64
not dirRefrescoVGA(14), -- ENABLE B: El modulo de lectura estara activo cuando el lineCnt sea menor que 64
'0', -- Desactivamos la limpieza de los latches de salida
'0',
enableEscritura, -- Escritura habilitada en puerto A cuando se ha realizado movimiento o durante limpieza
'0' -- Escritura NO habilitada en puerto B
);
memAzul_2: RAMB16_S1_s1
port map(
readFirstAzul2, -- Salida de Datos (A - Escritura) - Sirve para saber si chocamos contra nuestra propia estela.
DOB1, -- Salida de Datos (B - Lectura)
dirEscrituraAzul(13 downto 0),-- Direccion de escritura (A): Durante el juego es la posicion de la moto y durante la limpieza el Px/ln count
dirRefrescoVGA(13 downto 0), -- Direccion de lectura (B)
clk, -- Mismo reloj para ambos puertos
clk,
valorEscritura, -- Sera 1 durante el juego y 0 durante la limpieza de la memoria
'0', -- Nunca escribimos por el puerto B, asi que ponemos 0 como valor Din por poner algo
dirEscrituraAzul(14), -- ENABLE A: El modulo de escritura estara activo cuando el lineCnt sea mayor o igual que 64
dirRefrescoVGA(14), -- ENABLE B: El modulo de lectura estara activo cuando el lineCnt sea mayor o igual que 64
'0', -- Desactivamos la limpieza de los latches de salida
'0',
enableEscritura, -- Escritura habilitada en puerto A cuando se ha realizado movimiento o durante limpieza
'0' -- Escritura NO habilitada en puerto B
);
estelaAzul <= DOB0 OR DOB1;
-- MEMORIAS MOTO ROJA
-- ···········································································
memRoja_1: RAMB16_S1_s1
port map(
readFirstRoja1, -- Salida de Datos (A - Escritura) - Sirve para saber si chocamos contra nuestra propia estela.
DOB2, -- Salida de Datos (B - Lectura)
dirEscrituraRoja(13 downto 0),-- Direccion de escritura (A): Durante el juego es la posicion de la moto y durante la limpieza el Px/ln count
dirRefrescoVGA(13 downto 0), -- Direccion de lectura (B)
clk, -- Mismo reloj para ambos puertos
clk,
valorEscritura, -- Sera 1 durante el juego y 0 durante la limpieza de la memoria
'0', -- Nunca escribimos por el puerto B, asi que ponemos 0 como valor Din por poner algo
not dirEscrituraRoja(14), -- ENABLE A: El modulo de escritura estara activo cuando el lineCnt sea menor que 64
not dirRefrescoVGA(14), -- ENABLE B: El modulo de lectura estara activo cuando el lineCnt sea menor que 64
'0', -- Desactivamos la limpieza de los latches de salida
'0',
enableEscritura, -- Escritura habilitada en puerto A cuando se ha realizado movimiento o durante limpieza
'0' -- Escritura NO habilitada en puerto B
);
memRoja_2: RAMB16_S1_s1
port map(
readFirstRoja2, -- Salida de Datos (A - Escritura) - Sirve para saber si chocamos contra nuestra propia estela.
DOB3, -- Salida de Datos (B - Lectura)
dirEscrituraRoja(13 downto 0),-- Direccion de escritura (A): Durante el juego es la posicion de la moto y durante la limpieza el Px/ln count
dirRefrescoVGA(13 downto 0), -- Direccion de lectura (B)
clk, -- Mismo reloj para ambos puertos
clk,
valorEscritura, -- Sera 1 durante el juego y 0 durante la limpieza de la memoria
'0', -- Nunca escribimos por el puerto B, asi que ponemos 0 como valor Din por poner algo
dirEscrituraRoja(14), -- ENABLE A: El modulo de escritura estara activo cuando el lineCnt sea mayor o igual que 64
dirRefrescoVGA(14), -- ENABLE B: El modulo de lectura estara activo cuando el lineCnt sea mayor o igual que 64
'0', -- Desactivamos la limpieza de los latches de salida
'0',
enableEscritura, -- Escritura habilitada en puerto A cuando se ha realizado movimiento o durante limpieza
'0' -- Escritura NO habilitada en puerto B
);
estelaRoja <= DOB2 OR DOB3;
-- LIMPIEZA DE LA MEMORIA: Contador para esperar durante la limpieza. Cuando el contador finalice la memoria estará limpia.
-- *******************************************************************************
ciclosLimpiezaCnt:
process( clk, rst, csCiclosLimpieza, limpiarMemoria)
begin
if rst = '0' then
limpiezaCompletada <= '0';
csCiclosLimpieza <= (others => '0');
elsif clk'event and clk = '1' then
if limpiarMemoria = '1' then
if csCiclosLimpieza = 5000000 then
limpiezaCompletada <= '1';
else
csCiclosLimpieza <= csCiclosLimpieza + 1;
limpiezaCompletada <= '0';
end if;
else
csCiclosLimpieza <= (others => '0');
limpiezaCompletada <= '0';
end if;
end if;
end process;
-- Durante la limpieza la direccion de escritura es la de refrescoVGA para limpiar (valor 0) toda la pantalla
-- Durante el juego la direccion de escritura es la de los contadores de posicion (valor 1) de las motos.
dirEscrituraAzul <= dirRefrescoVGA WHEN limpiarMemoria = '1' ELSE dirTrayectoAzul;
dirEscrituraRoja <= dirRefrescoVGA WHEN limpiarMemoria = '1' ELSE dirTrayectoRoja;
valorEscritura <= '0' WHEN limpiarMemoria = '1' ELSE '1';
-- DETECTOR DE COLISIONES
-- *******************************************************************************
choqueContrario <= '1' WHEN (DOB0 = '1' AND DOB2 = '1') OR (DOB1 = '1' AND DOB3 = '1') ELSE '0';
choquePropioRoja <= '1' WHEN ((readFirstRoja1 = '1' AND dirEscrituraRoja(14) = '0') OR
(readFirstRoja2 = '1' AND dirEscrituraRoja(14) = '1')) AND
csRalentizador = 0 ELSE '0';
choquePropioAzul <= '1' WHEN ((readFirstAzul1 = '1' AND dirEscrituraAzul(14) = '0') OR
(readFirstAzul2 = '1' AND dirEscrituraAzul(14) = '1')) AND
csRalentizador = 0 ELSE '0';
hayGanador <= choqueContrario OR choquePropioRoja OR choquePropioAzul;
-- PINTAR MOTO AZUL
-- *******************************************************************************
motoAzulY:
process( clk, rst, csMotoAzulY, mueve, dirMotoAzul, iniciarMotos)
begin
if rst = '0' then
csMotoAzulY <= conv_std_logic_vector( 111 , 7 ); -- Abajo de la pantalla (7 bits)
elsif clk'event and clk='1' then
if iniciarMotos = '1' then
csMotoAzulY <= conv_std_logic_vector( 111 , 7 );
elsif mueve = '1' then
-- Ajustar conteo en funcion de la direccion
if dirMotoAzul = ARRIBA then
csMotoAzulY <= csMotoAzulY - 1;
elsif dirMotoAzul = ABAJO then
csMotoAzulY <= csMotoAzulY + 1;
end if;
-- Si se sale por el borde de arriba (0 px) o el de abajo (119 px) aparecer por el contrario
if csMotoAzulY = 0 and dirMotoAzul = ARRIBA then
csMotoAzulY <= conv_std_logic_vector( 119 , 7 );
elsif csMotoAzulY = 119 and dirMotoAzul = ABAJO then
csMotoAzulY <= conv_std_logic_vector( 0 , 7 );
end if;
end if;
end if;
end process;
motoAzulX:
process( clk, rst , csMotoAzulX, mueve, dirMotoAzul, iniciarMotos)
begin
if rst = '0' then
csMotoAzulX <= conv_std_logic_vector( 152 , 8 );
elsif clk'event and clk='1' then
if iniciarMotos = '1' then
csMotoAzulX <= conv_std_logic_vector( 152 , 8 );
elsif mueve = '1' then
-- Ajustar conteo en funcion de la direccion
if dirMotoAzul = IZQUIERDA then
csMotoAzulX <= csMotoAzulX - 1;
elsif dirMotoAzul = DERECHA then
csMotoAzulX <= csMotoAzulX + 1;
end if;
-- Si se sale por el borde de arriba (0 px) o el de abajo (119 px) aparecer por el contrario
if csMotoAzulX = 0 and dirMotoAzul = IZQUIERDA then
csMotoAzulX <= conv_std_logic_vector( 152 , 8 );
elsif csMotoAzulX = 152 and dirMotoAzul = DERECHA then
csMotoAzulX <= conv_std_logic_vector( 0 , 8 );
end if;
end if;
end if;
end process;
-- La moto azul se pinta donde marquen los contadores de los ejes X e Y
motoAzul <= '1' WHEN (pixelCntOut(10 downto 3) > csMotoAzulX-2) AND (pixelCntOut(10 downto 3) < csMotoAzulX+2) AND
(lineCntOut(8 downto 2) > csMotoAzulY-2) AND (lineCntOut(8 downto 2) < csMotoAzulY+2) ELSE '0';
-- PINTAR MOTO ROJA
-- *******************************************************************************
motoRojaY:
process( clk, rst , mueve, csMotoRojaY, mueve, dirMotoRoja, iniciarMotos)
begin
if rst = '0' then
csMotoRojaY <= conv_std_logic_vector( 7, 7 );
elsif clk'event and clk='1' then
if iniciarMotos = '1' then
csMotoRojaY <= conv_std_logic_vector( 7 , 7 );
elsif mueve = '1' then
-- Ajustar conteo en funcion de la direccion
if dirMotoRoja = ARRIBA then
csMotoRojaY <= csMotoRojaY - 1;
elsif dirMotoRoja = ABAJO then
csMotoRojaY <= csMotoRojaY + 1;
end if;
-- Si se sale por el borde de arriba (0 px) o el de abajo (119 px) aparecer por el contrario
if csMotoRojaY = 0 and dirMotoRoja = ARRIBA then
csMotoRojaY <= conv_std_logic_vector( 119 , 7 );
elsif csMotoRojaY = 119 and dirMotoRoja = ABAJO then
csMotoRojaY <= conv_std_logic_vector( 0 , 7 );
end if;
end if;
end if;
end process;
motoRojaX:
process( clk, rst , csMotoRojaX, mueve, dirMotoRoja, iniciarMotos)
begin
if rst = '0' then
csMotoRojaX <= conv_std_logic_vector( 2 , 8 );
elsif clk'event and clk='1' then
if iniciarMotos = '1' then
csMotoRojaX <= conv_std_logic_vector( 2 , 8 );
elsif mueve = '1' then
-- Ajustar conteo en funcion de la direccion
if dirMotoRoja = IZQUIERDA then
csMotoRojaX <= csMotoRojaX - 1;
elsif dirMotoRoja = DERECHA then
csMotoRojaX <= csMotoRojaX + 1;
end if;
-- Si se sale por el borde de arriba (0 px) o el de abajo (119 px) aparecer por el contrario
if csMotoRojaX = 0 and dirMotoRoja = IZQUIERDA then
csMotoRojaX <= conv_std_logic_vector( 152 , 8 );
elsif csMotoRojaX = 152 and dirMotoRoja = DERECHA then
csMotoRojaX <= conv_std_logic_vector( 0 , 8 );
end if;
end if;
end if;
end process;
-- La moto roja se pinta donde marquen los contadores de los ejes X e Y
motoRoja <= '1' WHEN (pixelCntOut(10 downto 3) > csMotoRojaX-2) AND (pixelCntOut(10 downto 3) < csMotoRojaX+2) AND
(lineCntOut(8 downto 2) > csMotoRojaY-2) AND (lineCntOut(8 downto 2) < csMotoRojaY+2) ELSE '0';
-- RALENTIZADOR DE MOVIMIENTO: Evita que las motos se muevan demasiado deprisa
-- *******************************************************************************
ralentizador:
process( clk, rst, csRalentizador, partidaEnCurso)
begin
if rst = '0' then
mueve <= '0';
csRalentizador <= conv_std_logic_vector( 0, 23 );
elsif clk'event and clk = '1' then
if partidaEnCurso = '1' then
if csRalentizador = 2000000 then
mueve <= '1';
csRalentizador <= conv_std_logic_vector( 0, 23 );
else
csRalentizador <= csRalentizador + 1;
mueve <= '0';
end if;
end if;
end if;
end process;
-- RESULTADO FINAL EN MONITOR VGA
-- *******************************************************************************
valor <= NOT blanking;
salidaRojo <= (motoRoja OR estelaRoja) AND NOT blanking;
salidaAzul <= (motoAzul OR estelaAzul) AND NOT blanking;
-- Este biestable evita los glitches en la salida VGA
biestableVGASync:
process(rst, clk)
begin
if rst = '0' then
hSyncQ <= '0';
vSyncQ <= '0';
RGBQ <= valor & valor & valor & valor & valor & valor & valor & valor & valor;
elsif clk'event and clk = '1' then
hSyncQ <= hSync;
vSyncQ <= vSync;
RGBQ <= RGB;
end if;
end process;
-- INTERFAZ TECLADO PS/2
-- *******************************************************************************************
synchronizer:
PROCESS (rst, clk)
VARIABLE aux1: std_logic;
BEGIN
IF (rst='0') THEN
aux1 := '1';
ps2ClkSync <= '1';
ELSIF (clk'EVENT AND clk='1') THEN
ps2ClkSync <= aux1;
aux1 := ps2Clk;
END IF;
END PROCESS synchronizer;
edgeDetector:
PROCESS (rst, clk)
VARIABLE aux1, aux2: std_logic;
BEGIN
ps2ClkFallingEdge <= (NOT aux1) AND aux2;
IF (rst='0') THEN
aux1 := '1';
aux2 := '1';
ELSIF (clk'EVENT AND clk='1') THEN
aux2 := aux1;
aux1 := ps2ClkSync;
END IF;
END PROCESS edgeDetector;
ps2DataReg:
PROCESS (rst, clk)
BEGIN
IF (rst='0') THEN
ps2DataRegOut <= (OTHERS =>'1');
ELSIF (clk'EVENT AND clk='1') THEN
IF (lastBitRcv='1') THEN
ps2DataRegOut <= (OTHERS=>'1');
ELSIF (ps2ClkFallingEdge='1') THEN
ps2DataRegOut <= ps2Data & ps2DataRegOut(10 downto 1);
END IF;
END IF;
END PROCESS ps2DataReg;
oddParityCheker:
goodParity <=
((ps2DataRegOut(9) XOR ps2DataRegOut(8)) XOR (ps2DataRegOut(7) XOR ps2DataRegOut(6)))
XOR ((ps2DataRegOut(5) XOR ps2DataRegOut(4)) XOR (ps2DataRegOut(3) XOR ps2DataRegOut(2)))
XOR ps2DataRegOut(1);
lastBitRcv <= NOT ps2DataRegOut(0);
validData <= lastBitRcv AND goodParity;
dataReg:
PROCESS (rst, clk)
BEGIN
IF (rst='0') THEN
data <= (OTHERS=>'0');
ELSIF (clk'EVENT AND clk='1') THEN
IF (ldData='1') THEN
data <= ps2DataRegOut(8 downto 1);
END IF;
END IF;
END PROCESS dataReg;
controller:
PROCESS (validData, rst, clk)
TYPE states IS (waitingData, waitingNewDataAck);
VARIABLE state: states;
BEGIN
ldData <= '0';
newData <= '0';
CASE state IS
WHEN waitingData =>
IF (validData='1') THEN
ldData <= '1';
END IF;
WHEN waitingNewDataAck =>
newData <= '1';
WHEN OTHERS => NULL;
END CASE;
IF (rst='0') THEN
state := waitingData;
ELSIF (clk'EVENT AND clk='1') THEN
CASE state IS
WHEN waitingData =>
IF (validData='1') THEN
state := waitingNewDataAck;
END IF;
WHEN waitingNewDataAck =>
IF (newDataAck='1') THEN
state := waitingData;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS controller;
-- MAQUINA DE ESTADOS PARA DETECCION DE TECLAS (TECLADO PS/2)
-- *******************************************************************************************
-- MAQUINA ESTADOS: SINCRONO
maqEstadosTecladoSyn:
process(clk,rst)
begin
if rst ='0' then
dirMotoAzul <= IZQUIERDA;
dirMotoRoja <= DERECHA;
flagSPC <= '0';
ESTADO <= WAITING_PRESS;
elsif clk'event and clk='1' then
dirMotoAzul <= dirMotoAzulNext;
dirMotoRoja <= dirMotoRojaNext;
flagSPC <= flagSPCnext;
ESTADO <= SIG_ESTADO;
end if;
end process;
-- MAQUINA ESTADOS: COMBINACIONAL
maqEstadosTecladoComb:
process(ESTADO, newData, data, dirMotoAzul, dirMotoRoja)
begin
dirMotoAzulNext <= dirMotoAzul;
dirMotoRojaNext <= dirMotoRoja;
flagSPCnext <= flagSPC;
SIG_ESTADO <= ESTADO;
case ESTADO is
when WAITING_PRESS =>
newDataAck <= '1';
if newData = '1' then
case data is
-- Si es F0, es una liberacion de tecla
when "11110000" => SIG_ESTADO <= RELEASE_BUTTON;
-- CONTROL MOTO ROJA
-- ···········································································
-- Si es Q = 15 (hex) y NO va hacia abajo
when "00010101" => if dirMotoRoja = IZQUIERDA OR dirMotoRoja = DERECHA then
dirMotoRojaNext <= ARRIBA;
end if;
-- Si es A = 1C (hex) y NO va hacia arriba
when "00011100" => if dirMotoRoja = IZQUIERDA OR dirMotoRoja = DERECHA then
dirMotoRojaNext <= ABAJO;
end if;
-- Si es Z = 1A (hex) y NO va hacia la derecha
when "00011010" => if dirMotoRoja = ARRIBA OR dirMotoRoja = ABAJO then
dirMotoRojaNext <= IZQUIERDA;
end if;
-- Si es X = 22 (hex) y NO va hacia izquierda
when "00100010" => if dirMotoRoja = ARRIBA OR dirMotoRoja = ABAJO then
dirMotoRojaNext <= DERECHA;
end if;
-- CONTROL MOTO AZUL
-- ···········································································
-- Si es P = 4D (hex) y NO va hacia abajo
when "01001101" => if dirMotoAzul = IZQUIERDA OR dirMotoAzul = DERECHA then
dirMotoAzulNext <= ARRIBA;
end if;
-- Si es L = 4B (hex) y NO va hacia arriba
when "01001011" => if dirMotoAzul = IZQUIERDA OR dirMotoAzul = DERECHA then
dirMotoAzulNext <= ABAJO;
end if;
-- Si es N = 31 (hex) y NO va hacia la derecha
when "00110001" => if dirMotoAzul = ARRIBA OR dirMotoAzul = ABAJO then
dirMotoAzulNext <= IZQUIERDA;
end if;
-- Si es M = 3A (hex) y NO va hacia izquierda
when "00111010" => if dirMotoAzul = ARRIBA OR dirMotoAzul = ABAJO then
dirMotoAzulNext <= DERECHA;
end if;
when "00101001" => flagSPCnext <= '1'; -- Si es SPACE = 29 (hex), activamos flag de SPACE
when others => SIG_ESTADO <= WAITING_PRESS;
end case;
end if;
when RELEASE_BUTTON =>
newDataAck <= '1';
flagSPCnext <= '0';
-- No hacemos nada; consumimos liberacion de tecla para no confundirla con una pulsacion
if newData = '1' then
-- Si es el SPC y antes de empezar la partida
if data = "00101001" AND partidaEnCurso = '0' then
dirMotoAzulNext <= IZQUIERDA;
dirMotoRojaNext <= DERECHA;
end if;
SIG_ESTADO <= WAITING_PRESS;
end if;
end case;
end process;
-- MAQUINA DE ESTADOS PARA EL JUEGO
-- *******************************************************************************************
-- MAQUINA ESTADOS: SINCRONO
maqEstadosJuegoSyn:
process(clk,rst)
begin
if rst ='0' then
GAME <= WAITING_SPACE;
elsif clk'event and clk='1' then
GAME <= NEXT_GAME;
end if;
end process;
-- MAQUINA ESTADOS: COMBINACIONAL
maqEstadosJuegoComb:
process(GAME, flagSPC, hayGanador, limpiezaCompletada)
begin
case GAME is
when WAITING_SPACE =>
partidaEnCurso <= '0';
iniciarMotos <= '0';
limpiarMemoria <= '0';
NEXT_GAME <= WAITING_SPACE;
if flagSPC = '1' then
limpiarMemoria <= '1';
NEXT_GAME <= INITIALIZING_GAME;
end if;
when INITIALIZING_GAME =>
partidaEnCurso <= '0';
iniciarMotos <= '1';
limpiarMemoria <= '1';
NEXT_GAME <= INITIALIZING_GAME;
if limpiezaCompletada = '1' then
limpiarMemoria <= '0';
NEXT_GAME <= WAITING_WINNER;
end if;
when WAITING_WINNER =>
partidaEnCurso <= '1';
iniciarMotos <= '0';
limpiarMemoria <= '0';
NEXT_GAME <= WAITING_WINNER;
if hayGanador = '1'then
NEXT_GAME <= WAITING_SPACE;
end if;
end case;
end process;
END tronArch;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0;
USE mult_gen_v12_0.mult_gen_v12_0;
ENTITY multi_fft IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(57 DOWNTO 0)
);
END multi_fft;
ARCHITECTURE multi_fft_arch OF multi_fft IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF multi_fft_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(57 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF multi_fft_arch: ARCHITECTURE IS "mult_gen_v12_0,Vivado 2014.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF multi_fft_arch : ARCHITECTURE IS "multi_fft,mult_gen_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF multi_fft_arch: ARCHITECTURE IS "multi_fft,mult_gen_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=5,C_A_WIDTH=29,C_A_TYPE=0,C_B_WIDTH=29,C_B_TYPE=0,C_OUT_HIGH=57,C_OUT_LOW=0,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "zynq",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 5,
C_A_WIDTH => 29,
C_A_TYPE => 0,
C_B_WIDTH => 29,
C_B_TYPE => 0,
C_OUT_HIGH => 57,
C_OUT_LOW => 0,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END multi_fft_arch;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0;
USE mult_gen_v12_0.mult_gen_v12_0;
ENTITY multi_fft IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(57 DOWNTO 0)
);
END multi_fft;
ARCHITECTURE multi_fft_arch OF multi_fft IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF multi_fft_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(57 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF multi_fft_arch: ARCHITECTURE IS "mult_gen_v12_0,Vivado 2014.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF multi_fft_arch : ARCHITECTURE IS "multi_fft,mult_gen_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF multi_fft_arch: ARCHITECTURE IS "multi_fft,mult_gen_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=5,C_A_WIDTH=29,C_A_TYPE=0,C_B_WIDTH=29,C_B_TYPE=0,C_OUT_HIGH=57,C_OUT_LOW=0,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "zynq",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 5,
C_A_WIDTH => 29,
C_A_TYPE => 0,
C_B_WIDTH => 29,
C_B_TYPE => 0,
C_OUT_HIGH => 57,
C_OUT_LOW => 0,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END multi_fft_arch;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0;
USE mult_gen_v12_0.mult_gen_v12_0;
ENTITY multi_fft IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(57 DOWNTO 0)
);
END multi_fft;
ARCHITECTURE multi_fft_arch OF multi_fft IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF multi_fft_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(57 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF multi_fft_arch: ARCHITECTURE IS "mult_gen_v12_0,Vivado 2014.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF multi_fft_arch : ARCHITECTURE IS "multi_fft,mult_gen_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF multi_fft_arch: ARCHITECTURE IS "multi_fft,mult_gen_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=5,C_A_WIDTH=29,C_A_TYPE=0,C_B_WIDTH=29,C_B_TYPE=0,C_OUT_HIGH=57,C_OUT_LOW=0,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "zynq",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 5,
C_A_WIDTH => 29,
C_A_TYPE => 0,
C_B_WIDTH => 29,
C_B_TYPE => 0,
C_OUT_HIGH => 57,
C_OUT_LOW => 0,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END multi_fft_arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: leon3
-- File: leon3.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: LEON3 types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package leon3 is
constant LEON3_VERSION : integer := 3;
type l3_irq_in_type is record
irl : std_logic_vector(3 downto 0);
rst : std_ulogic;
run : std_ulogic;
rstvec : std_logic_vector(31 downto 12);
iact : std_ulogic;
index : std_logic_vector(3 downto 0);
hrdrst : std_ulogic;
end record;
type l3_irq_out_type is record
intack : std_ulogic;
irl : std_logic_vector(3 downto 0);
pwd : std_ulogic;
fpen : std_ulogic;
idle : std_ulogic;
end record;
type l3_debug_in_type is record
dsuen : std_ulogic; -- DSU enable
denable : std_ulogic; -- diagnostic register access enable
dbreak : std_ulogic; -- debug break-in
step : std_ulogic; -- single step
halt : std_ulogic; -- halt processor
reset : std_ulogic; -- reset processor
dwrite : std_ulogic; -- read/write
daddr : std_logic_vector(23 downto 2); -- diagnostic address
ddata : std_logic_vector(31 downto 0); -- diagnostic data
btrapa : std_ulogic; -- break on IU trap
btrape : std_ulogic; -- break on IU trap
berror : std_ulogic; -- break on IU error mode
bwatch : std_ulogic; -- break on IU watchpoint
bsoft : std_ulogic; -- break on software breakpoint (TA 1)
tenable : std_ulogic;
timer : std_logic_vector(30 downto 0); --
end record;
constant dbgi_none : l3_debug_in_type := ('0', '0', '0', '0', '0',
'0', '0', (others => '0'), (others => '0'), '0', '0', '0', '0', '0', '0', (others => '0'));
constant l3_dbgi_none : l3_debug_in_type := dbgi_none;
type l3_cstat_type is record
cmiss : std_ulogic; -- cache miss
tmiss : std_ulogic; -- TLB miss
chold : std_ulogic; -- cache hold
mhold : std_ulogic; -- cache mmu hold
end record;
constant cstat_none : l3_cstat_type := ('0', '0', '0', '0');
type l3_debug_out_type is record
data : std_logic_vector(31 downto 0);
crdy : std_ulogic;
dsu : std_ulogic;
dsumode : std_ulogic;
error : std_ulogic;
halt : std_ulogic;
pwd : std_ulogic;
idle : std_ulogic;
ipend : std_ulogic;
icnt : std_ulogic;
fcnt : std_ulogic;
optype : std_logic_vector(5 downto 0); -- instruction type
bpmiss : std_ulogic; -- branch predict miss
istat : l3_cstat_type;
dstat : l3_cstat_type;
wbhold : std_ulogic; -- write buffer hold
su : std_ulogic; -- supervisor state
end record;
type l3_debug_in_vector is array (natural range <>) of l3_debug_in_type;
type l3_debug_out_vector is array (natural range <>) of l3_debug_out_type;
constant dbgo_none : l3_debug_out_type := (X"00000000", '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', "000000", '0', cstat_none, cstat_none, '0', '0');
constant l3_dbgo_none : l3_debug_out_type := dbgo_none;
type tracebuf_in_type is record
addr : std_logic_vector(11 downto 0);
data : std_logic_vector(255 downto 0);
enable : std_logic;
write : std_logic_vector(7 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(255 downto 0);
end record;
type tracebuf_2p_in_type is record
renable : std_logic;
raddr : std_logic_vector(11 downto 0);
write : std_logic_vector(7 downto 0);
waddr : std_logic_vector(11 downto 0);
data : std_logic_vector(255 downto 0);
end record;
type tracebuf_2p_out_type is record
data : std_logic_vector(255 downto 0);
end record;
component tbufmem
generic ( tech : integer := 0; tbuf : integer := 0; dwidth : integer := 32; testen: integer := 0);
port (
clk : in std_ulogic;
di : in tracebuf_in_type;
do : out tracebuf_out_type;
testin: in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end component;
component tbufmem_2p is
generic (
tech : integer := 0;
tbuf : integer := 0; -- trace buf size in kB (0 - no trace buffer)
dwidth : integer := 64; -- AHB data width
testen : integer := 0
);
port (
clk : in std_ulogic;
di : in tracebuf_2p_in_type;
do : out tracebuf_2p_out_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end component;
constant tracebuf_out_type_none : tracebuf_out_type :=
(data => (others => '0'));
constant tracebuf_in_type_none : tracebuf_in_type := (
addr => (others => '0'),
data => (others => '0'),
enable => '0',
write => (others => '0')
);
constant tracebuf_2p_out_type_none : tracebuf_2p_out_type :=
(data => (others => '0'));
constant tracebuf_2p_in_type_none : tracebuf_2p_in_type := (
renable => '0',
raddr => (others => '0'),
write => (others => '0'),
waddr => (others => '0'),
data => (others => '0')
);
component leon3s
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type
);
end component;
component leon3cg
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic
);
end component;
component leon3ft
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0; -- cacheability table
netlist : integer := 0; -- use netlist
scantest : integer := 0; -- enable scan test support
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic
);
end component;
type grfpu_in_type is record
start : std_logic;
nonstd : std_logic;
flop : std_logic_vector(8 downto 0);
op1 : std_logic_vector(63 downto 0);
op2 : std_logic_vector(63 downto 0);
opid : std_logic_vector(7 downto 0);
flush : std_logic;
flushid : std_logic_vector(5 downto 0);
rndmode : std_logic_vector(1 downto 0);
req : std_logic_vector(2 downto 0);
end record;
constant grfpu_in_none : grfpu_in_type :=
('0', '0', (others => '0'), (others => '0'), (others => '0'),
(others => '0'), '0', (others => '0'), (others => '0'),
(others => '0'));
type grfpu_out_type is record
res : std_logic_vector(63 downto 0);
exc : std_logic_vector(5 downto 0);
allow : std_logic_vector(2 downto 0);
rdy : std_logic;
cc : std_logic_vector(1 downto 0);
idout : std_logic_vector(7 downto 0);
end record;
constant grfpu_out_none : grfpu_out_type :=
((others => '0'), (others => '0'), (others => '0'),
'0', (others => '0'), (others => '0'));
type grfpu_out_vector_type is array (integer range 0 to 7) of grfpu_out_type;
type grfpu_in_vector_type is array (integer range 0 to 7) of grfpu_in_type;
component grfpushwx
generic (mul : integer := 0;
nshare : integer range 0 to 8 := 0;
tech : integer;
arb : integer range 0 to 2 := 1);
port(
clk : in std_logic;
reset : in std_logic;
fpvi : in grfpu_in_vector_type;
fpvo : out grfpu_out_vector_type
);
end component;
component leon3sh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon3s2x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
clk2x : integer := 1;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
gclk2 : in std_ulogic;
clk2 : in std_ulogic; -- snoop clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
clken : in std_ulogic
);
end component;
component leon3ft2x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
clk2x : integer := 1;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end component;
type dsu_in_type is record
enable : std_ulogic;
break : std_ulogic;
end record;
subtype dsu_astat_type is amba_stat_type;
constant dsu_astat_none : dsu_astat_type := amba_stat_none;
type dsu_out_type is record
active : std_ulogic;
tstop : std_ulogic;
pwd : std_logic_vector(15 downto 0);
astat : dsu_astat_type;
end record;
constant dsu_out_none : dsu_out_type :=
(active => '0', tstop => '0', pwd => (others => '0'),
astat => dsu_astat_none);
component dsu3
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end component;
component dsu3_2x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
end component;
component dsu3x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
clk2x : integer range 0 to 1 := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
end component;
component dsu3_mb
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end component;
type l3stat_src_array is array (15 downto 0) of std_logic_vector(3 downto 0);
type l3stat_in_type is record
event : std_logic_vector(15 downto 0);
esource : l3stat_src_array;
sel : std_logic_vector(15 downto 0);
req : std_logic_vector(15 downto 0);
latcnt : std_ulogic;
timer : std_logic_vector(31 downto 0);
end record;
constant l3stat_in_none : l3stat_in_type :=
(event => (others => '0'),
esource => (others => (others => '0')),
sel => (others => '0'),
req => (others => '0'),
latcnt => '0',
timer => (others => '0'));
component l3stat
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncnt : integer := 2;
ncpu : integer := 1;
nmax : integer := 0;
lahben : integer := 0;
dsuen : integer := 0;
nextev : integer range 0 to 16 := 0;
apb2en : integer := 0;
pindex2 : integer := 0;
paddr2 : integer := 0;
pmask2 : integer := 16#fff#;
astaten : integer := 0;
selreq : integer := 0;
clatch : integer := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbsi : in ahb_slv_in_type;
dbgo : in l3_debug_out_vector(0 to NCPU-1);
dsuo : in dsu_out_type := dsu_out_none;
stati : in l3stat_in_type := l3stat_in_none;
apb2i : in apb_slv_in_type := apb_slv_in_none;
apb2o : out apb_slv_out_type;
astat : in amba_stat_type := amba_stat_none);
end component;
type irq_in_vector is array (Natural range <> ) of l3_irq_in_type;
type irq_out_vector is array (Natural range <> ) of l3_irq_out_type;
component irqmp
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
irqmap : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1)
);
end component;
component irqmp2x
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
clkfact : integer := 2;
irqmap : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
hclken : in std_ulogic
);
end component;
component irqamp
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
nctrl : integer range 1 to 16 := 1;
tstamp : integer range 0 to 16 := 0;
wdogen : integer range 0 to 1 := 0;
nwdog : integer range 1 to 16 := 1;
dynrstaddr : integer range 0 to 1 := 0;
rstaddr : integer range 0 to 16#fffff# := 0;
extrun : integer range 0 to 1 := 0;
irqmap : integer := 0;
exttimer : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
wdog : in std_logic_vector(nwdog-1 downto 0) := (others => '0');
cpurun : in std_logic_vector(ncpu-1 downto 0) := (others => '0');
timer : in std_logic_vector(31 downto 0) := (others => '0')
);
end component;
component irqamp2x
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
nctrl : integer range 1 to 16 := 1;
tstamp : integer range 0 to 16 := 0;
wdogen : integer range 0 to 1 := 0;
nwdog : integer range 1 to 16 := 1;
dynrstaddr : integer range 0 to 1 := 0;
rstaddr : integer range 0 to 16#fffff# := 0;
extrun : integer range 0 to 1 := 0;
clkfact : integer := 2;
irqmap : integer := 0;
exttimer : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
wdog : in std_logic_vector(nwdog-1 downto 0) := (others => '0');
cpurun : in std_logic_vector(ncpu-1 downto 0) := (others => '0');
hclken : in std_ulogic;
timer : in std_logic_vector(31 downto 0) := (others => '0')
);
end component;
component leon3ftsh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic; -- gated clock
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon3x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
clk2x : integer := 1;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end component;
-- disassembly dummy module
component cpu_disasx
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result : in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end component;
end;
|
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY decoder IS
PORT (
codigo : IN std_logic_vector(3 DOWNTO 0);
led : OUT std_logic_vector(6 DOWNTO 0)
);
END ENTITY decoder;
ARCHITECTURE dataflow OF decoder IS
BEGIN
WITH codigo SELECT
led <= "0000001" WHEN "0000",
"1001111" WHEN "0001",
"0010010" WHEN "0010",
"0000110" WHEN "0011",
"1001100" WHEN "0100",
"0100100" WHEN "0101",
"0100000" WHEN "0110",
"0001111" WHEN "0111",
"0000000" WHEN "1000",
"0000100" WHEN "1001",
"1111110" WHEN others;
END ARCHITECTURE dataflow; |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY decoder IS
PORT (
codigo : IN std_logic_vector(3 DOWNTO 0);
led : OUT std_logic_vector(6 DOWNTO 0)
);
END ENTITY decoder;
ARCHITECTURE dataflow OF decoder IS
BEGIN
WITH codigo SELECT
led <= "0000001" WHEN "0000",
"1001111" WHEN "0001",
"0010010" WHEN "0010",
"0000110" WHEN "0011",
"1001100" WHEN "0100",
"0100100" WHEN "0101",
"0100000" WHEN "0110",
"0001111" WHEN "0111",
"0000000" WHEN "1000",
"0000100" WHEN "1001",
"1111110" WHEN others;
END ARCHITECTURE dataflow; |
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : clk_gen.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Clockgenerator
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 27.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
architecture rtl of clk_gen is
signal s_signal : std_logic := '0';
begin
process(clk_i, reset_i)
variable v_count : integer := 0;
begin
if reset_i = '1' then
s_signal <= '0';
v_count := 0;
elsif rising_edge(clk_i) then
if v_count = count_val_i then
v_count := 0;
s_signal <= not s_signal;
else
v_count := v_count + 1;
end if;
end if;
end process;
signal_o <= s_signal;
end rtl; |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_bb
--
-- Generated
-- by: wig
-- on: Tue Nov 29 13:29:43 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_bb-rtl-a.vhd,v 1.3 2005/11/30 14:04:00 wig Exp $
-- $Date: 2005/11/30 14:04:00 $
-- $Log: ent_bb-rtl-a.vhd,v $
-- Revision 1.3 2005/11/30 14:04:00 wig
-- Updated testcase references
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_bb
--
architecture rtl of ent_bb is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : Testbench
-- Last update : 28.11.2013
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.standard.all;
use std.textio.all;
use std.env.all;
library work;
use work.iac_pkg.all;
entity iac_testbench is
end iac_testbench;
architecture sim of iac_testbench is
constant SYSTEM_CYCLE_TIME : time := 20 ns; -- 50MHz
constant SIMULATION_TIME : time := 100000 * SYSTEM_CYCLE_TIME;
constant FULL_DEBUG : natural := 0;
constant SIMULATION_MODE : boolean := true;
signal clock, reset_n, reset : std_ulogic;
signal end_simulation : std_ulogic;
-- 7_seg
signal hex0_n : std_ulogic_vector(6 downto 0);
signal hex1_n : std_ulogic_vector(6 downto 0);
signal hex2_n : std_ulogic_vector(6 downto 0);
signal hex3_n : std_ulogic_vector(6 downto 0);
signal hex4_n : std_ulogic_vector(6 downto 0);
signal hex5_n : std_ulogic_vector(6 downto 0);
signal hex6_n : std_ulogic_vector(6 downto 0);
signal hex7_n : std_ulogic_vector(6 downto 0);
-- gpio
signal gpio : std_logic_vector(15 downto 0);
-- lcd
signal lcd_en : std_ulogic;
signal lcd_rs : std_ulogic;
signal lcd_rw : std_ulogic;
signal lcd_on : std_ulogic;
signal lcd_blon : std_ulogic;
signal lcd_dat : std_ulogic_vector(7 downto 0);
-- led/switches/keys
signal led_green : std_ulogic_vector(8 downto 0);
signal led_red : std_ulogic_vector(17 downto 0);
signal switch : std_ulogic_vector(17 downto 0);
signal key_n, key : std_ulogic_vector(2 downto 0);
-- adc_dac
signal exb_adc_switch : std_ulogic_vector(2 downto 0);
signal exb_adc_en_n : std_ulogic;
signal exb_dac_ldac_n : std_ulogic;
signal exb_spi_clk : std_ulogic;
signal exb_spi_mosi : std_ulogic;
signal exb_spi_miso : std_logic;
signal exb_spi_cs_adc_n : std_ulogic;
signal exb_spi_cs_dac_n : std_ulogic;
-- sram
signal sram_ce_n : std_ulogic;
signal sram_oe_n : std_ulogic;
signal sram_we_n : std_ulogic;
signal sram_ub_n : std_ulogic;
signal sram_lb_n : std_ulogic;
signal sram_addr : std_ulogic_vector(19 downto 0);
signal sram_dq : std_logic_vector(15 downto 0);
-- uart
signal uart_rts : std_ulogic;
signal uart_cts : std_ulogic;
signal uart_rxd : std_ulogic;
signal uart_txd : std_ulogic;
-- audio
signal aud_xclk : std_ulogic;
signal aud_bclk : std_ulogic;
signal aud_adc_lrck : std_ulogic;
signal aud_adc_dat : std_ulogic;
signal aud_dac_lrck : std_ulogic;
signal aud_dac_dat : std_ulogic;
signal i2c_sdat : std_logic;
signal i2c_sclk : std_ulogic;
-- infrared
signal irda_rxd : std_ulogic;
component iac_toplevel is
generic (
SIMULATION : boolean
);
port (
-- global signals
clock_ext_50 : in std_ulogic;
clock_ext2_50 : in std_ulogic;
clock_ext3_50 : in std_ulogic;
reset_n : in std_ulogic; -- (key3)
-- 7_seg
hex0_n : out std_ulogic_vector(6 downto 0);
hex1_n : out std_ulogic_vector(6 downto 0);
hex2_n : out std_ulogic_vector(6 downto 0);
hex3_n : out std_ulogic_vector(6 downto 0);
hex4_n : out std_ulogic_vector(6 downto 0);
hex5_n : out std_ulogic_vector(6 downto 0);
hex6_n : out std_ulogic_vector(6 downto 0);
hex7_n : out std_ulogic_vector(6 downto 0);
-- gpio
gpio : inout std_logic_vector(15 downto 0);
-- lcd
lcd_en : out std_ulogic;
lcd_rs : out std_ulogic;
lcd_rw : out std_ulogic;
lcd_on : out std_ulogic;
lcd_blon : out std_ulogic;
lcd_dat : out std_ulogic_vector(7 downto 0);
-- led/switches/keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key_n : in std_ulogic_vector(2 downto 0);
-- adc_dac
exb_adc_switch : out std_ulogic_vector(2 downto 0);
exb_adc_en_n : out std_ulogic;
exb_dac_ldac_n : out std_ulogic;
exb_spi_clk : out std_ulogic;
exb_spi_mosi : out std_ulogic;
exb_spi_miso : in std_logic;
exb_spi_cs_adc_n : out std_ulogic;
exb_spi_cs_dac_n : out std_ulogic;
-- sram
sram_ce_n : out std_ulogic;
sram_oe_n : out std_ulogic;
sram_we_n : out std_ulogic;
sram_ub_n : out std_ulogic;
sram_lb_n : out std_ulogic;
sram_addr : out std_ulogic_vector(19 downto 0);
sram_dq : inout std_logic_vector(15 downto 0);
-- uart
uart_rts : in std_ulogic;
uart_cts : out std_ulogic;
uart_rxd : in std_ulogic;
uart_txd : out std_ulogic;
-- audio
aud_xclk : out std_ulogic;
aud_bclk : in std_ulogic;
aud_adc_lrck : in std_ulogic;
aud_adc_dat : in std_ulogic;
aud_dac_lrck : in std_ulogic;
aud_dac_dat : out std_ulogic;
i2c_sdat : inout std_logic;
i2c_sclk : inout std_logic;
-- infrared
irda_rxd : in std_ulogic
);
end component iac_toplevel;
component io_model is
generic(
-- file containing static bit-settings for io's
FILE_NAME_SET : string
);
port(
-- io's
gpio : inout std_logic_vector(15 downto 0);
switch : out std_ulogic_vector(17 downto 0);
key : out std_ulogic_vector(2 downto 0)
);
end component io_model;
component adc_model is
generic(
SYSTEM_CYCLE_TIME : time;
FULL_DEBUG : natural;
FILE_NAME_PRELOAD : string
);
port(
-- Global Signals
end_simulation : in std_logic;
-- SPI Signals
spi_clk : in std_ulogic;
spi_miso : out std_logic;
spi_cs_n : in std_ulogic;
-- Switch Signals
swt_select : in std_ulogic_vector(2 downto 0);
swt_enable_n : in std_ulogic
);
end component adc_model;
component dac_model is
generic(
SYSTEM_CYCLE_TIME : time;
FILE_NAME_DUMP : string
);
port(
-- Global Signals
end_simulation : in std_logic;
-- SPI Signals
spi_clk : in std_ulogic;
spi_mosi : in std_ulogic;
spi_cs_n : in std_ulogic;
-- DAC Signals
dac_ldac_n : in std_ulogic
);
end component dac_model;
component seven_seg_model is
generic (
SYSTEM_CYCLE_TIME : time
);
port (
-- Global Signals
end_simulation : in std_ulogic;
-- 7-seg connections
hex0_n : in std_ulogic_vector(6 downto 0);
hex1_n : in std_ulogic_vector(6 downto 0);
hex2_n : in std_ulogic_vector(6 downto 0);
hex3_n : in std_ulogic_vector(6 downto 0);
hex4_n : in std_ulogic_vector(6 downto 0);
hex5_n : in std_ulogic_vector(6 downto 0);
hex6_n : in std_ulogic_vector(6 downto 0);
hex7_n : in std_ulogic_vector(6 downto 0)
);
end component seven_seg_model;
component infrared_model is
generic (
SYSTEM_CYCLE_TIME : time;
-- file with bytes to be send to fpga
FILE_NAME_COMMAND : string;
-- custom code of ir-sender
CUSTOM_CODE : std_ulogic_vector(15 downto 0);
SIMULATION : boolean
);
port (
-- global signals
end_simulation : in std_ulogic;
-- ir-pin
irda_txd : out std_ulogic
);
end component infrared_model;
component lcd_model is
generic(
SYSTEM_CYCLE_TIME : time;
FULL_DEBUG : natural
);
port(
-- Global Signals
end_simulation : in std_ulogic;
-- LCD Signals
disp_en : in std_ulogic;
disp_rs : in std_ulogic;
disp_rw : in std_ulogic;
disp_dat : in std_ulogic_vector(7 downto 0)
);
end component lcd_model;
component sram_model is
generic(
SYSTEM_CYCLE_TIME : time;
FULL_DEBUG : natural;
-- file for preload of sram
FILE_NAME_PRELOAD : string;
-- file for dump at end of simulation
FILE_NAME_DUMP : string;
-- number of addressable words in sram (size of sram)
GV_SRAM_SIZE : natural
);
port(
-- global signals
end_simulation : in std_ulogic;
-- sram connections
sram_ce_n : in std_ulogic;
sram_oe_n : in std_ulogic;
sram_we_n : in std_ulogic;
sram_ub_n : in std_ulogic;
sram_lb_n : in std_ulogic;
sram_addr : in std_ulogic_vector(19 downto 0);
sram_dq : inout std_logic_vector(15 downto 0)
);
end component sram_model;
component uart_model is
generic (
SYSTEM_CYCLE_TIME : time;
-- file with data to be send to fpga
FILE_NAME_COMMAND : string;
-- file for dump of data, received by pc
FILE_NAME_DUMP : string;
-- communication speed for uart-link
BAUD_RATE : natural;
SIMULATION : boolean
);
port (
-- global signals
end_simulation : in std_ulogic;
-- uart-pins (pc side)
rx : in std_ulogic;
tx : out std_ulogic
);
end component uart_model;
signal i2c_sdat_pullup_wire : std_logic;
signal i2c_sclk_pullup_wire : std_logic;
component acodec_model is
generic (
SAMPLE_WIDTH : natural;
SAMPLE_RATE : natural;
SAMPLE_FILE : string
);
port (
-- acodec signals
aud_xclk : in std_ulogic;
aud_bclk : out std_ulogic;
aud_adc_lrck : out std_ulogic;
aud_adc_dat : out std_ulogic;
aud_dac_lrck : out std_ulogic;
aud_dac_dat : in std_ulogic;
i2c_sdat : inout std_logic;
i2c_sclk : in std_logic
);
end component acodec_model;
begin
reset <= not(reset_n);
clk : process
begin
clock <= '1';
wait for SYSTEM_CYCLE_TIME/2;
clock <= '0';
wait for SYSTEM_CYCLE_TIME/2;
end process clk;
rst : process
begin
reset_n <= '0';
wait for 2*SYSTEM_CYCLE_TIME;
reset_n <= '1';
wait;
end process rst;
end_sim : process
variable tmp : line;
begin
end_simulation <= '0';
wait for SIMULATION_TIME;
end_simulation <= '1';
wait for 10*SYSTEM_CYCLE_TIME;
write(tmp, string'("Simulation finished: end time reached!"));
writeline(output, tmp);
stop;
wait;
end process end_sim;
iac_toplevel_inst : iac_toplevel
generic map (
SIMULATION => SIMULATION_MODE
)
port map (
clock_ext_50 => clock,
clock_ext2_50 => clock,
clock_ext3_50 => clock,
reset_n => reset_n,
hex0_n => hex0_n,
hex1_n => hex1_n,
hex2_n => hex2_n,
hex3_n => hex3_n,
hex4_n => hex4_n,
hex5_n => hex5_n,
hex6_n => hex6_n,
hex7_n => hex7_n,
gpio => gpio,
lcd_en => lcd_en,
lcd_rs => lcd_rs,
lcd_rw => lcd_rw,
lcd_on => lcd_on,
lcd_blon => lcd_blon,
lcd_dat => lcd_dat,
led_green => led_green,
led_red => led_red,
switch => switch,
key_n => key_n,
exb_adc_switch => exb_adc_switch,
exb_adc_en_n => exb_adc_en_n,
exb_dac_ldac_n => exb_dac_ldac_n,
exb_spi_clk => exb_spi_clk,
exb_spi_mosi => exb_spi_mosi,
exb_spi_miso => exb_spi_miso,
exb_spi_cs_adc_n => exb_spi_cs_adc_n,
exb_spi_cs_dac_n => exb_spi_cs_dac_n,
sram_ce_n => sram_ce_n,
sram_oe_n => sram_oe_n,
sram_we_n => sram_we_n,
sram_ub_n => sram_ub_n,
sram_lb_n => sram_lb_n,
sram_addr => sram_addr,
sram_dq => sram_dq,
uart_rts => uart_rts,
uart_cts => uart_cts,
uart_rxd => uart_rxd,
uart_txd => uart_txd,
aud_xclk => aud_xclk,
aud_bclk => aud_bclk,
aud_adc_lrck => aud_adc_lrck,
aud_adc_dat => aud_adc_dat,
aud_dac_lrck => aud_dac_lrck,
aud_dac_dat => aud_dac_dat,
i2c_sdat => i2c_sdat_pullup_wire,
i2c_sclk => i2c_sclk_pullup_wire,
irda_rxd => irda_rxd
);
key_n <= not(key);
io_model_inst : io_model
generic map (
FILE_NAME_SET => "io.txt")
port map (
gpio => gpio,
switch => switch,
key => key
);
seven_seg_gen : if CV_EN_SEVENSEG = 1 generate
seven_seg_model_inst : seven_seg_model
generic map (
SYSTEM_CYCLE_TIME => SYSTEM_CYCLE_TIME)
port map (
end_simulation => end_simulation,
hex0_n => hex0_n,
hex1_n => hex1_n,
hex2_n => hex2_n,
hex3_n => hex3_n,
hex4_n => hex4_n,
hex5_n => hex5_n,
hex6_n => hex6_n,
hex7_n => hex7_n
);
end generate seven_seg_gen;
exb_spi_miso <= 'H';
adc_dac_gen : if CV_EN_ADC_DAC = 1 generate
adc_model_inst : adc_model
generic map (
SYSTEM_CYCLE_TIME => SYSTEM_CYCLE_TIME,
FULL_DEBUG => FULL_DEBUG,
FILE_NAME_PRELOAD => "adc_preload.txt")
port map (
end_simulation => end_simulation,
spi_clk => exb_spi_clk,
spi_miso => exb_spi_miso,
spi_cs_n => exb_spi_cs_adc_n,
swt_select => exb_adc_switch,
swt_enable_n => exb_adc_en_n
);
dac_model_inst : dac_model
generic map (
SYSTEM_CYCLE_TIME => SYSTEM_CYCLE_TIME,
FILE_NAME_DUMP => "dac_dump.txt")
port map (
end_simulation => end_simulation,
spi_clk => exb_spi_clk,
spi_mosi => exb_spi_mosi,
spi_cs_n => exb_spi_cs_dac_n,
dac_ldac_n => exb_dac_ldac_n
);
end generate adc_dac_gen;
i2c_sdat_pullup_wire <= 'H';
i2c_sclk_pullup_wire <= 'H';
audio_gen : if CV_EN_AUDIO = 1 generate
acodec_inst : acodec_model
generic map (
SAMPLE_WIDTH => 16,
SAMPLE_RATE => 8*44100,
SAMPLE_FILE => "audio_samples.txt")
port map (
aud_xclk => aud_xclk,
aud_bclk => aud_bclk,
aud_adc_lrck => aud_adc_lrck,
aud_adc_dat => aud_adc_dat,
aud_dac_lrck => aud_dac_lrck,
aud_dac_dat => aud_dac_dat,
i2c_sdat => i2c_sdat_pullup_wire,
i2c_sclk => i2c_sclk_pullup_wire
);
end generate audio_gen;
infrared_gen : if CV_EN_IR = 1 generate
infrared_inst : infrared_model
generic map (
SYSTEM_CYCLE_TIME => SYSTEM_CYCLE_TIME,
FILE_NAME_COMMAND => "ir_command.txt",
CUSTOM_CODE => x"6B86",
SIMULATION => SIMULATION_MODE
)
port map (
end_simulation => end_simulation,
irda_txd => irda_rxd
);
end generate infrared_gen;
lcd_gen : if CV_EN_LCD = 1 generate
lcd_model_inst : lcd_model
generic map(
SYSTEM_CYCLE_TIME => SYSTEM_CYCLE_TIME,
FULL_DEBUG => FULL_DEBUG
)
port map (
end_simulation => end_simulation,
disp_en => lcd_en,
disp_rs => lcd_rs,
disp_rw => lcd_rw,
disp_dat => lcd_dat
);
end generate lcd_gen;
sram_gen : if CV_EN_SRAM = 1 generate
sram_model_inst : sram_model
generic map (
SYSTEM_CYCLE_TIME => SYSTEM_CYCLE_TIME,
FULL_DEBUG => FULL_DEBUG,
FILE_NAME_PRELOAD => "sram_preload.txt",
FILE_NAME_DUMP => "sram_dump.txt",
GV_SRAM_SIZE => 2**20
)
port map (
end_simulation => end_simulation,
sram_ce_n => sram_ce_n,
sram_oe_n => sram_oe_n,
sram_we_n => sram_we_n,
sram_ub_n => sram_ub_n,
sram_lb_n => sram_lb_n,
sram_addr => sram_addr,
sram_dq => sram_dq
);
end generate sram_gen;
uart_gen : if CV_EN_UART = 1 generate
uart_model_inst : uart_model
generic map (
SYSTEM_CYCLE_TIME => SYSTEM_CYCLE_TIME,
FILE_NAME_COMMAND => "uart_command.txt",
FILE_NAME_DUMP => "uart_dump.txt",
BAUD_RATE => CV_UART_BAUDRATE,
SIMULATION => SIMULATION_MODE
)
port map (
end_simulation => end_simulation,
rx => uart_txd,
tx => uart_rxd
);
end generate uart_gen;
end sim;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc826.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b02x00p02n01i00826ent IS
END c01s02b02x00p02n01i00826ent;
ARCHITECTURE c01s02b02x00p02n01i00826arch OF c01s02b02x00p02n01i00826ent IS
BEGIN
return; -- illegal location for return statement
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b02x00p02n01i00826 - Architecture statement can only have concurrent statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b02x00p02n01i00826arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc826.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b02x00p02n01i00826ent IS
END c01s02b02x00p02n01i00826ent;
ARCHITECTURE c01s02b02x00p02n01i00826arch OF c01s02b02x00p02n01i00826ent IS
BEGIN
return; -- illegal location for return statement
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b02x00p02n01i00826 - Architecture statement can only have concurrent statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b02x00p02n01i00826arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc826.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b02x00p02n01i00826ent IS
END c01s02b02x00p02n01i00826ent;
ARCHITECTURE c01s02b02x00p02n01i00826arch OF c01s02b02x00p02n01i00826ent IS
BEGIN
return; -- illegal location for return statement
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b02x00p02n01i00826 - Architecture statement can only have concurrent statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b02x00p02n01i00826arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2001.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n02i02001ent IS
END c07s02b02x00p07n02i02001ent;
ARCHITECTURE c07s02b02x00p07n02i02001arch OF c07s02b02x00p07n02i02001ent IS
BEGIN
TESTING: PROCESS
type CHAR_RECORD is record
C1, C2, C3 : CHARACTER;
end record;
variable k : integer := 0;
variable m : CHAR_RECORD := ('a','b','c');
BEGIN
if (m = CHAR_RECORD'('a','b','c')) then
k := 5;
else
k := 0;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p07n02i02001"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p07n02i02001 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n02i02001arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2001.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n02i02001ent IS
END c07s02b02x00p07n02i02001ent;
ARCHITECTURE c07s02b02x00p07n02i02001arch OF c07s02b02x00p07n02i02001ent IS
BEGIN
TESTING: PROCESS
type CHAR_RECORD is record
C1, C2, C3 : CHARACTER;
end record;
variable k : integer := 0;
variable m : CHAR_RECORD := ('a','b','c');
BEGIN
if (m = CHAR_RECORD'('a','b','c')) then
k := 5;
else
k := 0;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p07n02i02001"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p07n02i02001 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n02i02001arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2001.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n02i02001ent IS
END c07s02b02x00p07n02i02001ent;
ARCHITECTURE c07s02b02x00p07n02i02001arch OF c07s02b02x00p07n02i02001ent IS
BEGIN
TESTING: PROCESS
type CHAR_RECORD is record
C1, C2, C3 : CHARACTER;
end record;
variable k : integer := 0;
variable m : CHAR_RECORD := ('a','b','c');
BEGIN
if (m = CHAR_RECORD'('a','b','c')) then
k := 5;
else
k := 0;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p07n02i02001"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p07n02i02001 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n02i02001arch;
|
entity func1 is
end entity;
architecture test of func1 is
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
p1: process is
variable r : integer;
begin
r := 2;
r := add1(r);
wait;
end process;
end architecture;
|
------------------------------------------------------------------------------------
--state machine:
--1) idle: wait for the period to start the ping sensing
--2) trigger: send the 10us trigger pulse
--3) wait echo: wait for the echo high edge, if timeout_cnt reaches 50ms, restart
--4) echo count: echo rising edge received begin count, end count when echo falling edge, if timeout_cnt reaches 50ms, restart
--5) wait next: wait for timeout to reach 50ms.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;
use ieee.std_logic_unsigned.all;
entity ping_sensor is
generic (CLK_FREQ_NS : positive := 20);
port( clk : in std_logic;
reset: in std_logic;
--ping signals
ping_io: inout std_logic; --tristate option usage
echo_length : out std_logic_vector(15 downto 0);
ping_enable: in std_logic;
echo_done_out: out std_logic;
state_debug: out std_logic_vector(2 downto 0);
timeout: out std_logic;
busy : out std_logic
);
end ping_sensor ;
architecture Behavioral of ping_sensor is
type state_type is (idle, trigger_on, trigger_off, echo_wait, echo_cnt, echo_wait_low, wait_next); --,wait_sample_period);
signal state_reg, state_next: state_type;
--@50Mhz
constant VAL_1us :integer:= 1_000/CLK_FREQ_NS;
constant VAL_WAIT_NEXT_PING: integer := 5000; -- found that at least 170 us need on the parallax sensor.
constant VAL_10us :integer:= 10 ; --10us
constant TIMEOUT_VAL: integer := 50_000; --50ms
signal echo_reading_r: unsigned(31 downto 0);
--general purpose 1us counter used in state machine
signal cnt_us_r: unsigned(31 downto 0);
signal cnt_us_rst, cnt_us_rst_r: std_logic;
signal trigger_out_n, echo_done : std_logic ;
signal timeout_q : std_logic ;
--usec counter signals
signal end_usec, load_usec_counter : std_logic ;
signal usec_counter : std_logic_vector(31 downto 0);
--IF USING TRISTATE VALUES
signal echo_in, trigger_out: std_logic;
signal trigger_out_temp: std_logic;
signal echo_in_r: std_logic;
signal echo_in_debounced: std_logic_vector(7 downto 0);
begin
--tristate option
with state_reg select
ping_io <= '1' when trigger_on,
'Z' when echo_wait,
'Z' when echo_cnt,
'Z' when echo_wait_low,
'0' when others ;
with state_reg select
echo_in <= ping_io when echo_wait,
ping_io when echo_cnt,
'0' when others ;
-- input latch
process(clk, reset)
begin
if reset = '1' then
echo_in_r <= '0';
echo_in_debounced <= (others => '0');
elsif clk'event and clk = '1' then
echo_in_debounced(echo_in_debounced'high downto 1) <= echo_in_debounced((echo_in_debounced'high-1) downto 0);
echo_in_debounced(0) <= echo_in ;
if echo_in_debounced = 0 then
echo_in_r <= '0' ;
elsif echo_in_debounced = X"FF" then
echo_in_r <= '1';
end if ;
end if;
end process ;
--state register
process(clk, reset)
begin
if reset = '1' then
state_reg <= idle;
elsif clk'event and clk = '1' then
state_reg <= state_next;
end if;
end process ;
process(state_reg, ping_enable, echo_in_r,cnt_us_r, end_usec, timeout_q)
begin
state_next <= state_reg;
case state_reg is
when idle =>
if (ping_enable = '1') then --start trigger sequence
state_next <= trigger_on;
end if;
when trigger_on =>
if (cnt_us_r >= VAL_10US and end_usec = '1') then
state_next <= trigger_off;
end if;
when trigger_off =>
if (cnt_us_r >= VAL_10US and end_usec = '1') then
state_next <= echo_wait;
end if;
when echo_wait => --wait for echo to go high
if (echo_in_r = '1' and end_usec = '1') then --echo went high
state_next <= echo_cnt;
elsif timeout_q = '1' then
state_next <= wait_next;
end if;
when echo_cnt => --cnt length of echo pulse
if (echo_in_r = '0' and end_usec = '1') then --ECHO received - DONE!
state_next <= wait_next;
elsif timeout_q = '1' then --check to see if the timeout
state_next <= echo_wait_low;
end if;
when echo_wait_low => --this will wait to ensure echo has gone low, sr04 will timeout @200ms with echo high
if(echo_in_r = '0' and end_usec = '1') then
state_next <= wait_next;
end if;
when wait_next => -- wait end of timeout to start next measurement
if (cnt_us_r >= VAL_WAIT_NEXT_PING and end_usec = '1') then --putting lower values here throws wrencn in the works
state_next <= idle;
end if;
end case;
end process;
with state_reg select
state_debug <= "000" when idle,
"001" when trigger_on,
"010" when trigger_off,
"011" when echo_wait,
"100" when echo_cnt,
"101" when echo_wait_low,
"110" when others ;
cnt_us_rst <= '1' when state_reg = idle else
'1' when state_next /= state_reg else
'0';
echo_done <= '1' when state_reg = echo_cnt and echo_in_r = '0' else
'0' ;
timeout_q <= '1' when state_reg = echo_wait and cnt_us_r >= TIMEOUT_VAL else
'1' when state_reg = echo_cnt and cnt_us_r >= TIMEOUT_VAL else
'0' ;
timeout <= timeout_q ;
busy <= '0' when state_reg = idle and ping_enable = '0' else
'1' ;
-- usec counter
process(clk, reset)
begin
if reset = '1' then
cnt_us_r <= (others => '0');
elsif clk'event and clk = '1' then
if cnt_us_rst = '1' then
cnt_us_r <= (others => '0');
elsif end_usec = '1' then
cnt_us_r <= cnt_us_r + 1 ;
end if ;
end if ;
end process ;
-- main clock divider to generate usec period
process(clk, reset)
begin
if reset = '1' then
usec_counter <= std_logic_vector(to_unsigned(VAL_1us-1, 32));
elsif clk'event and clk = '1' then
if load_usec_counter = '1' then
usec_counter <= std_logic_vector(to_unsigned(VAL_1us-1, 32));
else
usec_counter <= usec_counter - 1 ;
end if ;
end if ;
end process ;
end_usec <= '1' when usec_counter = 0 else
'0' ;
load_usec_counter <= '1' when state_reg = idle else
end_usec;
--result latch
process(clk, reset)
begin
if reset = '1' then
echo_reading_r <= (others => '0');
elsif clk'event and clk = '1' then
if echo_done = '1' then
echo_reading_r <= cnt_us_r;
end if ;
end if ;
end process ;
--register latch the reset signal, getting glic
process(clk, reset)
begin
if reset = '1' then
cnt_us_rst_r <= '0';
elsif clk'event and clk = '1' then
cnt_us_rst_r <= cnt_us_rst ;
end if ;
end process ;
echo_length <= std_logic_vector(echo_reading_r(15 downto 0)) ;
echo_done_out <= echo_done;
end Behavioral;
|
------------------------------------------------------------------------------------
--state machine:
--1) idle: wait for the period to start the ping sensing
--2) trigger: send the 10us trigger pulse
--3) wait echo: wait for the echo high edge, if timeout_cnt reaches 50ms, restart
--4) echo count: echo rising edge received begin count, end count when echo falling edge, if timeout_cnt reaches 50ms, restart
--5) wait next: wait for timeout to reach 50ms.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;
use ieee.std_logic_unsigned.all;
entity ping_sensor is
generic (CLK_FREQ_NS : positive := 20);
port( clk : in std_logic;
reset: in std_logic;
--ping signals
ping_io: inout std_logic; --tristate option usage
echo_length : out std_logic_vector(15 downto 0);
ping_enable: in std_logic;
echo_done_out: out std_logic;
state_debug: out std_logic_vector(2 downto 0);
timeout: out std_logic;
busy : out std_logic
);
end ping_sensor ;
architecture Behavioral of ping_sensor is
type state_type is (idle, trigger_on, trigger_off, echo_wait, echo_cnt, echo_wait_low, wait_next); --,wait_sample_period);
signal state_reg, state_next: state_type;
--@50Mhz
constant VAL_1us :integer:= 1_000/CLK_FREQ_NS;
constant VAL_WAIT_NEXT_PING: integer := 5000; -- found that at least 170 us need on the parallax sensor.
constant VAL_10us :integer:= 10 ; --10us
constant TIMEOUT_VAL: integer := 50_000; --50ms
signal echo_reading_r: unsigned(31 downto 0);
--general purpose 1us counter used in state machine
signal cnt_us_r: unsigned(31 downto 0);
signal cnt_us_rst, cnt_us_rst_r: std_logic;
signal trigger_out_n, echo_done : std_logic ;
signal timeout_q : std_logic ;
--usec counter signals
signal end_usec, load_usec_counter : std_logic ;
signal usec_counter : std_logic_vector(31 downto 0);
--IF USING TRISTATE VALUES
signal echo_in, trigger_out: std_logic;
signal trigger_out_temp: std_logic;
signal echo_in_r: std_logic;
signal echo_in_debounced: std_logic_vector(7 downto 0);
begin
--tristate option
with state_reg select
ping_io <= '1' when trigger_on,
'Z' when echo_wait,
'Z' when echo_cnt,
'Z' when echo_wait_low,
'0' when others ;
with state_reg select
echo_in <= ping_io when echo_wait,
ping_io when echo_cnt,
'0' when others ;
-- input latch
process(clk, reset)
begin
if reset = '1' then
echo_in_r <= '0';
echo_in_debounced <= (others => '0');
elsif clk'event and clk = '1' then
echo_in_debounced(echo_in_debounced'high downto 1) <= echo_in_debounced((echo_in_debounced'high-1) downto 0);
echo_in_debounced(0) <= echo_in ;
if echo_in_debounced = 0 then
echo_in_r <= '0' ;
elsif echo_in_debounced = X"FF" then
echo_in_r <= '1';
end if ;
end if;
end process ;
--state register
process(clk, reset)
begin
if reset = '1' then
state_reg <= idle;
elsif clk'event and clk = '1' then
state_reg <= state_next;
end if;
end process ;
process(state_reg, ping_enable, echo_in_r,cnt_us_r, end_usec, timeout_q)
begin
state_next <= state_reg;
case state_reg is
when idle =>
if (ping_enable = '1') then --start trigger sequence
state_next <= trigger_on;
end if;
when trigger_on =>
if (cnt_us_r >= VAL_10US and end_usec = '1') then
state_next <= trigger_off;
end if;
when trigger_off =>
if (cnt_us_r >= VAL_10US and end_usec = '1') then
state_next <= echo_wait;
end if;
when echo_wait => --wait for echo to go high
if (echo_in_r = '1' and end_usec = '1') then --echo went high
state_next <= echo_cnt;
elsif timeout_q = '1' then
state_next <= wait_next;
end if;
when echo_cnt => --cnt length of echo pulse
if (echo_in_r = '0' and end_usec = '1') then --ECHO received - DONE!
state_next <= wait_next;
elsif timeout_q = '1' then --check to see if the timeout
state_next <= echo_wait_low;
end if;
when echo_wait_low => --this will wait to ensure echo has gone low, sr04 will timeout @200ms with echo high
if(echo_in_r = '0' and end_usec = '1') then
state_next <= wait_next;
end if;
when wait_next => -- wait end of timeout to start next measurement
if (cnt_us_r >= VAL_WAIT_NEXT_PING and end_usec = '1') then --putting lower values here throws wrencn in the works
state_next <= idle;
end if;
end case;
end process;
with state_reg select
state_debug <= "000" when idle,
"001" when trigger_on,
"010" when trigger_off,
"011" when echo_wait,
"100" when echo_cnt,
"101" when echo_wait_low,
"110" when others ;
cnt_us_rst <= '1' when state_reg = idle else
'1' when state_next /= state_reg else
'0';
echo_done <= '1' when state_reg = echo_cnt and echo_in_r = '0' else
'0' ;
timeout_q <= '1' when state_reg = echo_wait and cnt_us_r >= TIMEOUT_VAL else
'1' when state_reg = echo_cnt and cnt_us_r >= TIMEOUT_VAL else
'0' ;
timeout <= timeout_q ;
busy <= '0' when state_reg = idle and ping_enable = '0' else
'1' ;
-- usec counter
process(clk, reset)
begin
if reset = '1' then
cnt_us_r <= (others => '0');
elsif clk'event and clk = '1' then
if cnt_us_rst = '1' then
cnt_us_r <= (others => '0');
elsif end_usec = '1' then
cnt_us_r <= cnt_us_r + 1 ;
end if ;
end if ;
end process ;
-- main clock divider to generate usec period
process(clk, reset)
begin
if reset = '1' then
usec_counter <= std_logic_vector(to_unsigned(VAL_1us-1, 32));
elsif clk'event and clk = '1' then
if load_usec_counter = '1' then
usec_counter <= std_logic_vector(to_unsigned(VAL_1us-1, 32));
else
usec_counter <= usec_counter - 1 ;
end if ;
end if ;
end process ;
end_usec <= '1' when usec_counter = 0 else
'0' ;
load_usec_counter <= '1' when state_reg = idle else
end_usec;
--result latch
process(clk, reset)
begin
if reset = '1' then
echo_reading_r <= (others => '0');
elsif clk'event and clk = '1' then
if echo_done = '1' then
echo_reading_r <= cnt_us_r;
end if ;
end if ;
end process ;
--register latch the reset signal, getting glic
process(clk, reset)
begin
if reset = '1' then
cnt_us_rst_r <= '0';
elsif clk'event and clk = '1' then
cnt_us_rst_r <= cnt_us_rst ;
end if ;
end process ;
echo_length <= std_logic_vector(echo_reading_r(15 downto 0)) ;
echo_done_out <= echo_done;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1443.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01443ent IS
END c08s07b00x00p02n01i01443ent;
ARCHITECTURE c08s07b00x00p02n01i01443arch OF c08s07b00x00p02n01i01443ent IS
begin
transmit: process
variable k : integer := 10;
variable m : integer := 6;
begin
if m > 5 then
while (k > 5) loop
k := k - 1;
end loop;
end if;
assert (k = 5)
report "***FAILED TEST: c08s07b00x00p02n01i01443 - WHILE statement to be sequence statements of IF statement"
severity ERROR;
assert NOT(k = 5)
report "***PASSED TEST: c08s07b00x00p02n01i01443"
severity NOTE;
wait;
end process;
END c08s07b00x00p02n01i01443arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1443.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01443ent IS
END c08s07b00x00p02n01i01443ent;
ARCHITECTURE c08s07b00x00p02n01i01443arch OF c08s07b00x00p02n01i01443ent IS
begin
transmit: process
variable k : integer := 10;
variable m : integer := 6;
begin
if m > 5 then
while (k > 5) loop
k := k - 1;
end loop;
end if;
assert (k = 5)
report "***FAILED TEST: c08s07b00x00p02n01i01443 - WHILE statement to be sequence statements of IF statement"
severity ERROR;
assert NOT(k = 5)
report "***PASSED TEST: c08s07b00x00p02n01i01443"
severity NOTE;
wait;
end process;
END c08s07b00x00p02n01i01443arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1443.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01443ent IS
END c08s07b00x00p02n01i01443ent;
ARCHITECTURE c08s07b00x00p02n01i01443arch OF c08s07b00x00p02n01i01443ent IS
begin
transmit: process
variable k : integer := 10;
variable m : integer := 6;
begin
if m > 5 then
while (k > 5) loop
k := k - 1;
end loop;
end if;
assert (k = 5)
report "***FAILED TEST: c08s07b00x00p02n01i01443 - WHILE statement to be sequence statements of IF statement"
severity ERROR;
assert NOT(k = 5)
report "***PASSED TEST: c08s07b00x00p02n01i01443"
severity NOTE;
wait;
end process;
END c08s07b00x00p02n01i01443arch;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.uart_bfm_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_cmd_pkg is
--===============================================================================================
-- t_operation
-- - Bitvis defined BFM operations
--===============================================================================================
type t_operation is (
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
TRANSMIT, RECEIVE, EXPECT);
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := C_DATA_MAX_LENGTH;
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--===============================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--===============================================================================================
type t_vvc_cmd_record is record
-- Common VVC fields
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued;
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
-- VVC dedicated fields
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
max_receptions : integer;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
operation => FETCH_RESULT, -- Default unless overwritten by a common operation
data => (others => '0'),
max_receptions => 1,
alert_level => failure,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_command_type,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
delay => 0 ns,
quietness => NON_QUIET
);
--===============================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--===============================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--===============================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1));
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
|
-- NEED RESULT: ARCH00631: Index constraints passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00631
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 3.2.1.1 (4)
-- 3.2.1.1 (5)
-- 3.2.1.1 (6)
-- 3.2.1.1 (7)
-- 3.2.1.1 (8)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00631)
-- ENT00631_Test_Bench(ARCH00631_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
-- 18-JAN-1987 - removed refs to predefined attributes on func calls
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES; use STANDARD_TYPES.all ;
architecture ARCH00631 of E00000 is
begin
P :
process
constant c : STANDARD_TYPES.t_arr1 := c_st_arr1_1 ;
variable v : integer ;
attribute a : STANDARD_TYPES.t_arr1 ;
attribute a of v : variable is c_st_arr1_1 ;
type array_access is access STANDARD_TYPES.t_arr1 ;
variable ptr : array_access ;
variable low1, high1, left1, right1,
low2, high2, left2, right2 : integer := 9999 ;
variable st : STANDARD_TYPES.st_arr1 := c_st_arr1_1 ;
subtype t_100 is STANDARD_TYPES.t_arr1
(100+st_arr1'left to 100+st_arr1'right) ;
variable t : t_100 := c_st_arr1_1 ;
procedure proc_with_unconstrained_array ( a : in STANDARD_TYPES.t_arr1 ;
lo,hi,lft,rght : out integer )
is
begin
lo := a'low ;
hi := a'high ;
lft := a'left ;
rght := a'right ;
end proc_with_unconstrained_array ;
procedure proc_with_constrained_array ( a : in STANDARD_TYPES.st_arr1 ;
lo,hi,lft,rght : out integer )
is
begin
lo := a'low ;
hi := a'high ;
lft := a'left ;
rght := a'right ;
end proc_with_constrained_array ;
begin
proc_with_unconstrained_array ( st, low1, high1, left1, right1 ) ;
proc_with_constrained_array ( t, low2, high2, left2, right2 ) ;
ptr := new t_arr1(1 to 10) ;
test_report ( "ARCH00631" ,
"Index constraints" ,
(c'low = st_arr1'low) and -- these test 3.2.1.1 (4)
(c'high = st_arr1'high) and
(c'left = st_arr1'left) and
(c'right = st_arr1'right) and
-- (v'a'low = st_arr1'low) and -- these test 3.2.1.1 (5)
-- (v'a'high = st_arr1'high) and
-- (v'a'left = st_arr1'left) and
-- (v'a'right = st_arr1'right) and
(ptr.all'low = 1) and -- these test 3.2.1.1 (6)
(ptr.all'high = 10) and
(ptr.all'left = 1) and
(ptr.all'right = 10) and
(low1 = st_arr1'low) and -- these test 3.2.1.1 (8)
(high1 = st_arr1'high) and
(left1 = st_arr1'left) and
(right1 = st_arr1'right) and
(low2 = st_arr1'low) and -- these test 3.2.1.1 (7)
(high2 = st_arr1'high) and
(left2 = st_arr1'left) and
(right2 = st_arr1'right)
) ;
wait ;
end process P ;
end ARCH00631 ;
--
entity ENT00631_Test_Bench is
end ENT00631_Test_Bench ;
architecture ARCH00631_Test_Bench of ENT00631_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00631 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00631_Test_Bench ;
--
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05:33:07 11/13/2013
-- Design Name:
-- Module Name: D:/Programming/gitHub/cg3207-proj/IF_test.vhd
-- Project Name: Lab3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Fetch
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY if_test IS
END if_test;
ARCHITECTURE behavior OF if_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Fetch
PORT(
clk : IN std_logic;
reset : IN std_logic;
In_stall_if : IN std_logic;
Instruction : OUT std_logic_vector(31 downto 0);
PC_out : OUT std_logic_vector(31 downto 0);
BEQ_PC : IN std_logic_vector(31 downto 0);
PCSrc : IN std_logic;
Jump : IN std_logic;
JumpPC : IN std_logic_vector(31 downto 0);
IF_ID_Flush : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal In_stall_if : std_logic := '0';
signal BEQ_PC : std_logic_vector(31 downto 0) := (others => '0');
signal PCSrc : std_logic := '0';
signal Jump : std_logic := '0';
signal JumpPC : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal Instruction : std_logic_vector(31 downto 0);
signal PC_out : std_logic_vector(31 downto 0);
signal IF_ID_Flush : std_logic;
-- Clock period definitions
constant clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Fetch PORT MAP (
clk => clk,
reset => reset,
In_stall_if => In_stall_if,
Instruction => Instruction,
PC_out => PC_out,
BEQ_PC => BEQ_PC,
PCSrc => PCSrc,
Jump => Jump,
JumpPC => JumpPC,
IF_ID_Flush => IF_ID_Flush
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '1';
wait for 100 ns;
-- normal, expect PC_out = 00000000
reset <= '0';
In_stall_if <= '0';
BEQ_PC <= X"00000002";
PCSrc <= '0';
Jump <= '0';
JumpPC <= X"00000004";
wait for 100 ns;
-- normal, expect PC_out = 00000001
-- BEQ_PC <= X"00000001";
-- JUMPpC <= X"00000002";
-- wait for 100 ns;
--
-- -- jump, expect PC_out = 0000001C
-- BEQ_PC <= X"00000003";
-- Jump <= '1';
-- JumpPC <= X"0000001C";
-- wait for 100 ns;
--
-- -- normal, expect PC_out = 00000020
-- Jump <= '0';
-- wait for 200 ns;
--
-- -- beq, expect PC_out = 00000004
-- PCSrc <= '1';
-- BEQ_PC <= X"00000004";
-- Jump <= '0';
-- JumpPC <= X"00000004";
-- wait for 100 ns;
--
-- -- normal, expect PC_out = 00000005
-- PCSrc <= '0';
-- wait for 200 ns;
--
-- -- stall, expect PC_out = 00000005
-- In_stall_if <= '1';
-- wait for 100 ns;
--
-- -- normal, expect PC_out = 00000006
-- In_stall_if <= '0';
wait for 500 ns;
wait;
end process;
END;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Mar 28 05:22:49 2017
-- Host : DESKTOP-B1QME94 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_compiler_0_sim_netlist.vhdl
-- Design : dds_compiler_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tready : out STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axis_phase_tlast : in STD_LOGIC;
s_axis_phase_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tvalid : in STD_LOGIC;
s_axis_config_tready : out STD_LOGIC;
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tlast : in STD_LOGIC;
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tready : in STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_data_tlast : out STD_LOGIC;
m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tvalid : out STD_LOGIC;
m_axis_phase_tready : in STD_LOGIC;
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tlast : out STD_LOGIC;
m_axis_phase_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
event_pinc_invalid : out STD_LOGIC;
event_poff_invalid : out STD_LOGIC;
event_phase_in_invalid : out STD_LOGIC;
event_s_phase_tlast_missing : out STD_LOGIC;
event_s_phase_tlast_unexpected : out STD_LOGIC;
event_s_phase_chanid_incorrect : out STD_LOGIC;
event_s_config_tlast_missing : out STD_LOGIC;
event_s_config_tlast_unexpected : out STD_LOGIC;
debug_axi_pinc_in : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_axi_poff_in : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_axi_resync_in : out STD_LOGIC;
debug_axi_chan_in : out STD_LOGIC_VECTOR ( 0 to 0 );
debug_core_nd : out STD_LOGIC;
debug_phase : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_phase_nd : out STD_LOGIC
);
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 22;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 8;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 10000;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 16;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 12;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 12;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE : integer;
attribute C_POR_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_RESYNC : integer;
attribute C_RESYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 24;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is "artix7";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axis_data_tdata\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_i_synth_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_core_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_phase_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_phase_in_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_pinc_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_poff_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_data_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_i_synth_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_i_synth_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_i_synth_m_axis_data_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 11 );
signal NLW_i_synth_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACCUMULATOR_WIDTH of i_synth : label is 22;
attribute C_AMPLITUDE of i_synth : label is 1;
attribute C_CHANNELS of i_synth : label is 1;
attribute C_CHAN_WIDTH of i_synth : label is 1;
attribute C_DEBUG_INTERFACE of i_synth : label is 0;
attribute C_HAS_ACLKEN of i_synth : label is 0;
attribute C_HAS_ARESETN of i_synth : label is 0;
attribute C_HAS_M_DATA of i_synth : label is 1;
attribute C_HAS_M_PHASE of i_synth : label is 0;
attribute C_HAS_PHASEGEN of i_synth : label is 1;
attribute C_HAS_PHASE_OUT of i_synth : label is 0;
attribute C_HAS_SINCOS of i_synth : label is 1;
attribute C_HAS_S_CONFIG of i_synth : label is 0;
attribute C_HAS_S_PHASE of i_synth : label is 1;
attribute C_HAS_TLAST of i_synth : label is 0;
attribute C_HAS_TREADY of i_synth : label is 0;
attribute C_LATENCY of i_synth : label is 8;
attribute C_MEM_TYPE of i_synth : label is 1;
attribute C_MODE_OF_OPERATION of i_synth : label is 0;
attribute C_MODULUS of i_synth : label is 10000;
attribute C_M_DATA_HAS_TUSER of i_synth : label is 0;
attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 16;
attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_M_PHASE_TDATA_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_NEGATIVE_COSINE of i_synth : label is 0;
attribute C_NEGATIVE_SINE of i_synth : label is 0;
attribute C_NOISE_SHAPING of i_synth : label is 0;
attribute C_OPTIMISE_GOAL of i_synth : label is 1;
attribute C_OUTPUTS_REQUIRED of i_synth : label is 0;
attribute C_OUTPUT_FORM of i_synth : label is 0;
attribute C_OUTPUT_WIDTH of i_synth : label is 12;
attribute C_PHASE_ANGLE_WIDTH of i_synth : label is 12;
attribute C_PHASE_INCREMENT of i_synth : label is 3;
attribute C_PHASE_INCREMENT_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET of i_synth : label is 0;
attribute C_PHASE_OFFSET_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE of i_synth : label is 0;
attribute C_RESYNC of i_synth : label is 0;
attribute C_S_CONFIG_SYNC_MODE of i_synth : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH of i_synth : label is 1;
attribute C_S_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_S_PHASE_TDATA_WIDTH of i_synth : label is 24;
attribute C_S_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_USE_DSP48 of i_synth : label is 0;
attribute C_XDEVICEFAMILY of i_synth : label is "artix7";
attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
begin
debug_axi_chan_in(0) <= \<const0>\;
debug_axi_pinc_in(21) <= \<const0>\;
debug_axi_pinc_in(20) <= \<const0>\;
debug_axi_pinc_in(19) <= \<const0>\;
debug_axi_pinc_in(18) <= \<const0>\;
debug_axi_pinc_in(17) <= \<const0>\;
debug_axi_pinc_in(16) <= \<const0>\;
debug_axi_pinc_in(15) <= \<const0>\;
debug_axi_pinc_in(14) <= \<const0>\;
debug_axi_pinc_in(13) <= \<const0>\;
debug_axi_pinc_in(12) <= \<const0>\;
debug_axi_pinc_in(11) <= \<const0>\;
debug_axi_pinc_in(10) <= \<const0>\;
debug_axi_pinc_in(9) <= \<const0>\;
debug_axi_pinc_in(8) <= \<const0>\;
debug_axi_pinc_in(7) <= \<const0>\;
debug_axi_pinc_in(6) <= \<const0>\;
debug_axi_pinc_in(5) <= \<const0>\;
debug_axi_pinc_in(4) <= \<const0>\;
debug_axi_pinc_in(3) <= \<const0>\;
debug_axi_pinc_in(2) <= \<const0>\;
debug_axi_pinc_in(1) <= \<const0>\;
debug_axi_pinc_in(0) <= \<const0>\;
debug_axi_poff_in(21) <= \<const0>\;
debug_axi_poff_in(20) <= \<const0>\;
debug_axi_poff_in(19) <= \<const0>\;
debug_axi_poff_in(18) <= \<const0>\;
debug_axi_poff_in(17) <= \<const0>\;
debug_axi_poff_in(16) <= \<const0>\;
debug_axi_poff_in(15) <= \<const0>\;
debug_axi_poff_in(14) <= \<const0>\;
debug_axi_poff_in(13) <= \<const0>\;
debug_axi_poff_in(12) <= \<const0>\;
debug_axi_poff_in(11) <= \<const0>\;
debug_axi_poff_in(10) <= \<const0>\;
debug_axi_poff_in(9) <= \<const0>\;
debug_axi_poff_in(8) <= \<const0>\;
debug_axi_poff_in(7) <= \<const0>\;
debug_axi_poff_in(6) <= \<const0>\;
debug_axi_poff_in(5) <= \<const0>\;
debug_axi_poff_in(4) <= \<const0>\;
debug_axi_poff_in(3) <= \<const0>\;
debug_axi_poff_in(2) <= \<const0>\;
debug_axi_poff_in(1) <= \<const0>\;
debug_axi_poff_in(0) <= \<const0>\;
debug_axi_resync_in <= \<const0>\;
debug_core_nd <= \<const0>\;
debug_phase(21) <= \<const0>\;
debug_phase(20) <= \<const0>\;
debug_phase(19) <= \<const0>\;
debug_phase(18) <= \<const0>\;
debug_phase(17) <= \<const0>\;
debug_phase(16) <= \<const0>\;
debug_phase(15) <= \<const0>\;
debug_phase(14) <= \<const0>\;
debug_phase(13) <= \<const0>\;
debug_phase(12) <= \<const0>\;
debug_phase(11) <= \<const0>\;
debug_phase(10) <= \<const0>\;
debug_phase(9) <= \<const0>\;
debug_phase(8) <= \<const0>\;
debug_phase(7) <= \<const0>\;
debug_phase(6) <= \<const0>\;
debug_phase(5) <= \<const0>\;
debug_phase(4) <= \<const0>\;
debug_phase(3) <= \<const0>\;
debug_phase(2) <= \<const0>\;
debug_phase(1) <= \<const0>\;
debug_phase(0) <= \<const0>\;
debug_phase_nd <= \<const0>\;
event_phase_in_invalid <= \<const0>\;
event_pinc_invalid <= \<const0>\;
event_poff_invalid <= \<const0>\;
event_s_config_tlast_missing <= \<const0>\;
event_s_config_tlast_unexpected <= \<const0>\;
event_s_phase_chanid_incorrect <= \<const0>\;
event_s_phase_tlast_unexpected <= \<const0>\;
m_axis_data_tdata(15) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(14) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(13) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(12) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(11 downto 0) <= \^m_axis_data_tdata\(11 downto 0);
m_axis_data_tlast <= \<const0>\;
m_axis_data_tuser(0) <= \<const0>\;
m_axis_phase_tdata(0) <= \<const0>\;
m_axis_phase_tlast <= \<const0>\;
m_axis_phase_tuser(0) <= \<const0>\;
m_axis_phase_tvalid <= \<const0>\;
s_axis_config_tready <= \<const1>\;
s_axis_phase_tready <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
i_synth: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13_viv
port map (
aclk => aclk,
aclken => '0',
aresetn => '0',
debug_axi_chan_in(0) => NLW_i_synth_debug_axi_chan_in_UNCONNECTED(0),
debug_axi_pinc_in(21 downto 0) => NLW_i_synth_debug_axi_pinc_in_UNCONNECTED(21 downto 0),
debug_axi_poff_in(21 downto 0) => NLW_i_synth_debug_axi_poff_in_UNCONNECTED(21 downto 0),
debug_axi_resync_in => NLW_i_synth_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => NLW_i_synth_debug_core_nd_UNCONNECTED,
debug_phase(21 downto 0) => NLW_i_synth_debug_phase_UNCONNECTED(21 downto 0),
debug_phase_nd => NLW_i_synth_debug_phase_nd_UNCONNECTED,
event_phase_in_invalid => NLW_i_synth_event_phase_in_invalid_UNCONNECTED,
event_pinc_invalid => NLW_i_synth_event_pinc_invalid_UNCONNECTED,
event_poff_invalid => NLW_i_synth_event_poff_invalid_UNCONNECTED,
event_s_config_tlast_missing => NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED,
event_s_config_tlast_unexpected => NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED,
event_s_phase_chanid_incorrect => NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED,
event_s_phase_tlast_missing => event_s_phase_tlast_missing,
event_s_phase_tlast_unexpected => NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED,
m_axis_data_tdata(15) => \^m_axis_data_tdata\(11),
m_axis_data_tdata(14 downto 11) => NLW_i_synth_m_axis_data_tdata_UNCONNECTED(14 downto 11),
m_axis_data_tdata(10 downto 0) => \^m_axis_data_tdata\(10 downto 0),
m_axis_data_tlast => NLW_i_synth_m_axis_data_tlast_UNCONNECTED,
m_axis_data_tready => '0',
m_axis_data_tuser(0) => NLW_i_synth_m_axis_data_tuser_UNCONNECTED(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => NLW_i_synth_m_axis_phase_tdata_UNCONNECTED(0),
m_axis_phase_tlast => NLW_i_synth_m_axis_phase_tlast_UNCONNECTED,
m_axis_phase_tready => '0',
m_axis_phase_tuser(0) => NLW_i_synth_m_axis_phase_tuser_UNCONNECTED(0),
m_axis_phase_tvalid => NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED,
s_axis_config_tdata(0) => '0',
s_axis_config_tlast => '0',
s_axis_config_tready => NLW_i_synth_s_axis_config_tready_UNCONNECTED,
s_axis_config_tvalid => '0',
s_axis_phase_tdata(23 downto 22) => B"00",
s_axis_phase_tdata(21 downto 0) => s_axis_phase_tdata(21 downto 0),
s_axis_phase_tlast => '0',
s_axis_phase_tready => NLW_i_synth_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => '0',
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "dds_compiler_0,dds_compiler_v6_0_13,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "dds_compiler_v6_0_13,Vivado 2016.4";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_core_nd_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_phase_nd_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_phase_in_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_pinc_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_poff_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_data_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_phase_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_phase_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of U0 : label is 22;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of U0 : label is 1;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of U0 : label is 1;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of U0 : label is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of U0 : label is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of U0 : label is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of U0 : label is 0;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of U0 : label is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of U0 : label is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of U0 : label is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of U0 : label is 0;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of U0 : label is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of U0 : label is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of U0 : label is 1;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of U0 : label is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 8;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of U0 : label is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of U0 : label is 10000;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of U0 : label is 0;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of U0 : label is 16;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of U0 : label is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of U0 : label is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of U0 : label is 1;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of U0 : label is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of U0 : label is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of U0 : label is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of U0 : label is 0;
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of U0 : label is 1;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of U0 : label is 0;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of U0 : label is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of U0 : label is 12;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of U0 : label is 12;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of U0 : label is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of U0 : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of U0 : label is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of U0 : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE : integer;
attribute C_POR_MODE of U0 : label is 0;
attribute C_RESYNC : integer;
attribute C_RESYNC of U0 : label is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of U0 : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of U0 : label is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of U0 : label is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of U0 : label is 24;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of U0 : label is 1;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13
port map (
aclk => aclk,
aclken => '1',
aresetn => '1',
debug_axi_chan_in(0) => NLW_U0_debug_axi_chan_in_UNCONNECTED(0),
debug_axi_pinc_in(21 downto 0) => NLW_U0_debug_axi_pinc_in_UNCONNECTED(21 downto 0),
debug_axi_poff_in(21 downto 0) => NLW_U0_debug_axi_poff_in_UNCONNECTED(21 downto 0),
debug_axi_resync_in => NLW_U0_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => NLW_U0_debug_core_nd_UNCONNECTED,
debug_phase(21 downto 0) => NLW_U0_debug_phase_UNCONNECTED(21 downto 0),
debug_phase_nd => NLW_U0_debug_phase_nd_UNCONNECTED,
event_phase_in_invalid => NLW_U0_event_phase_in_invalid_UNCONNECTED,
event_pinc_invalid => NLW_U0_event_pinc_invalid_UNCONNECTED,
event_poff_invalid => NLW_U0_event_poff_invalid_UNCONNECTED,
event_s_config_tlast_missing => NLW_U0_event_s_config_tlast_missing_UNCONNECTED,
event_s_config_tlast_unexpected => NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED,
event_s_phase_chanid_incorrect => NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED,
event_s_phase_tlast_missing => NLW_U0_event_s_phase_tlast_missing_UNCONNECTED,
event_s_phase_tlast_unexpected => NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED,
m_axis_data_tdata(15 downto 0) => m_axis_data_tdata(15 downto 0),
m_axis_data_tlast => NLW_U0_m_axis_data_tlast_UNCONNECTED,
m_axis_data_tready => '0',
m_axis_data_tuser(0) => NLW_U0_m_axis_data_tuser_UNCONNECTED(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => NLW_U0_m_axis_phase_tdata_UNCONNECTED(0),
m_axis_phase_tlast => NLW_U0_m_axis_phase_tlast_UNCONNECTED,
m_axis_phase_tready => '0',
m_axis_phase_tuser(0) => NLW_U0_m_axis_phase_tuser_UNCONNECTED(0),
m_axis_phase_tvalid => NLW_U0_m_axis_phase_tvalid_UNCONNECTED,
s_axis_config_tdata(0) => '0',
s_axis_config_tlast => '0',
s_axis_config_tready => NLW_U0_s_axis_config_tready_UNCONNECTED,
s_axis_config_tvalid => '0',
s_axis_phase_tdata(23 downto 0) => s_axis_phase_tdata(23 downto 0),
s_axis_phase_tlast => '0',
s_axis_phase_tready => NLW_U0_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => '0',
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
|
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MOS6502CpuMonALS.vhd
-- /___/ /\ Timestamp : 20/09/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MOS6502CpuMonALS
--Device: XC6SLX9
--
--
-- This is a small wrapper around MOS6502CpuMon that add the following signals:
-- OEAH_n
-- OEAL_n
-- OED_n
-- DIRD
-- BE
-- ML_n
-- VP_n
-- (these are not fully implemented yet)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MOS6502CpuMonALS is
generic (
UseT65Core : boolean := true;
UseAlanDCore : boolean := false;
num_comparators : integer := 8;
avr_prog_mem_size : integer := 8 * 1024
);
port (
clock : in std_logic;
-- 6502 Signals
PhiIn : in std_logic;
Phi1Out : out std_logic;
Phi2Out : out std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
Sync : out std_logic;
Addr : out std_logic_vector(15 downto 0);
R_W_n : out std_logic_vector(1 downto 0);
Data : inout std_logic_vector(7 downto 0);
SO_n : in std_logic;
Res_n : in std_logic;
Rdy : in std_logic;
-- 65C02 Signals
BE : in std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
-- Level Shifter Controls
OERW_n : out std_logic;
OEAH_n : out std_logic;
OEAL_n : out std_logic;
OED_n : out std_logic;
DIRD : out std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- ID/mode inputs
mode : in std_logic;
id : in std_logic_vector(3 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- LEDs
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
-- OHO_DY1 LED display
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
);
end MOS6502CpuMonALS;
architecture behavioral of MOS6502CpuMonALS is
signal R_W_n_int : std_logic;
signal sw_reset_cpu : std_logic;
signal sw_reset_avr : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
signal PhiIn1 : std_logic;
signal PhiIn2 : std_logic;
signal PhiIn3 : std_logic;
signal PhiIn4 : std_logic;
begin
sw_reset_cpu <= not sw1;
sw_reset_avr <= not sw2;
led1 <= led_bkpt;
led2 <= led_trig0;
led3 <= led_trig1;
wrapper : entity work.MOS6502CpuMon
generic map (
UseT65Core => UseT65Core,
UseAlanDCore => UseAlanDCore,
ClkMult => 12,
ClkDiv => 25,
ClkPer => 20.000,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock => clock,
-- 6502 Signals
Phi0 => PhiIn,
Phi1 => Phi1Out,
Phi2 => Phi2Out,
IRQ_n => IRQ_n,
NMI_n => NMI_n,
Sync => Sync,
Addr => Addr,
R_W_n => R_W_n_int,
Data => Data,
SO_n => SO_n,
Res_n => Res_n,
Rdy => Rdy,
-- External trigger inputs
trig => trig,
-- Jumpers
fakeTube_n => '1',
-- Serial Console
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
-- Switches
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
-- OHO_DY1 LED display
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk
);
-- 6502 Outputs
R_W_n <= R_W_n_int & R_W_n_int;
-- 65C02 Outputs
ML_n <= '1';
VP_n <= '1';
process(clock)
begin
if rising_edge(clock) then
PhiIn1 <= PhiIn;
PhiIn2 <= PhiIn1;
PhiIn3 <= PhiIn2;
PhiIn4 <= PhiIn3;
end if;
end process;
-- Level Shifter Controls
OERW_n <= '0'; -- not (BE);
OEAH_n <= '0'; -- not (BE);
OEAL_n <= '0'; -- not (BE);
OED_n <= not (BE and PhiIn and PhiIn4); -- TODO: might need to use a slightly delayed version of Phi2 here
DIRD <= R_W_n_int;
end behavioral;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library util;
use util.numeric_pkg.all;
use util.logic_pkg.all;
use util.names_pkg.all;
use std.textio.all;
architecture rtl of syncram_1r1w_inferred is
constant memory_size : natural := 2**addr_bits;
type memory_type is array(0 to memory_size-1) of std_ulogic_vector((data_bits-1) downto 0);
-- fill the memory with pseudo-random (but reproduceable) data
pure function memory_init return memory_type is
constant lfsr_bits : natural := addr_bits + log2ceil(data_bits) + 1;
variable lfsr : std_ulogic_vector(lfsr_bits-1 downto 0);
constant taps : std_ulogic_vector(lfsr_bits-1 downto 0) := lfsr_taps(lfsr_bits);
variable ret : memory_type;
variable initial_bit : integer;
variable name : line;
begin
name := new string'(entity_path_name(syncram_1r1w_inferred'path_name));
for n in name.all'range loop
initial_bit := (initial_bit + character'pos(name.all(n))) mod lfsr_bits;
end loop;
deallocate(name);
lfsr := (others => '0');
lfsr(0) := '1';
lfsr(initial_bit) := '1';
for n in 0 to memory_size-1 loop
for m in data_bits-1 downto 0 loop
ret(n)(m) := lfsr(0);
lfsr(lfsr_bits-1 downto 0) := lfsr(0) & (lfsr(lfsr_bits-1 downto 1) xor ((lfsr_bits-2 downto 0 => lfsr(0)) and taps(lfsr_bits-2 downto 0)));
end loop;
end loop;
return ret;
end;
pure function conv_addr (addr : std_ulogic_vector(addr_bits-1 downto 0)) return natural is
begin
if addr_bits > 0 then
return to_integer(unsigned(addr));
else
return 0;
end if;
end function;
signal memory : memory_type := memory_init;
type reg_type is record
raddr : std_ulogic_vector(addr_bits-1 downto 0);
end record;
signal r : reg_type;
begin
write_process : process(clk)
begin
if rising_edge(clk) then
assert not is_x(we) report "we is invalid" severity warning;
if we = '1' then
assert not is_x(waddr) report "waddr is invalid" severity warning;
if not is_x(waddr) then
memory(conv_addr(waddr)) <= wdata;
end if;
end if;
end if;
end process;
write_first_true_gen: if write_first generate
rdata <= memory(conv_addr(r.raddr)) when not is_x(r.raddr) else (others => 'X');
read_process : process(clk)
begin
if rising_edge(clk) then
assert not is_x(re) report "re is invalid" severity warning;
if re = '1' then
r.raddr <= raddr;
end if;
end if;
end process;
end generate;
write_first_false_gen: if not write_first generate
main : process(clk)
begin
if rising_edge(clk) then
assert not is_x(re) report "re is invalid" severity warning;
if re = '1' then
rdata <= memory(conv_addr(raddr));
end if;
end if;
end process;
end generate;
end;
|
package p is
type int_ptr is access integer; -- OK
type bad1 is access foo; -- Error
type rec;
type rec_ptr is access rec;
type rec is record
value : integer;
link : rec_ptr;
end record;
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
type string_ptr is access string;
end package;
package body p is
procedure test is
variable v : int_ptr;
variable i : integer;
variable r : rec_ptr;
variable a : int_vec_ptr;
variable s : string_ptr;
begin
v := null; -- OK
i := null; -- Error
deallocate(v); -- OK
v := new integer; -- OK
v := new integer'(5); -- OK
v := new 5; -- Error
v := new i; -- Error
v.all := 5; -- OK
v := 5; -- Error
i := v.all + 5; -- OK
r := new rec; -- OK
r.all.value := 1; -- OK
r.value := 1; -- OK
r.link := r; -- OK
r.link := r.all; -- Error
i := r.value; -- OK
r := r.all.link; -- OK
a := new int_vec(1 to 3); -- OK
a.all(5) := 2; -- OK
a(5) := 2; -- OK
a(1 to 2) := (1, 2); -- OK
s := new string'(""); -- OK
s := new integer'(1); -- Error
s := new s(1 to 3); -- Error
end procedure;
procedure test2(x : inout rec_ptr) is
begin
x.value := x.value + 1;
end procedure;
procedure test3 is
type a;
type a is access integer; -- OK
variable v : a; -- OK
begin
end procedure;
type int_ptr_array is array (integer range <>) of int_ptr;
type int_ptr_array_ptr is access int_ptr_array;
procedure alloc_ptr_array(x : out int_ptr_array_ptr) is
begin
x := new int_ptr_array; -- Error
x := new int_ptr_array(1 to 3); -- OK
x.all := (null, null, null); -- OK
end procedure;
procedure tets4 is
type bvp is access bit_vector;
variable x : bvp(1 to 4) := new bit_vector'("1010"); -- OK
variable y : int_ptr(1 to 3) := int_ptr'(null); -- Error
begin
end procedure;
procedure test5 is
type foo;
variable f : foo; -- Error
begin
end procedure;
procedure test6 is
variable v : int_vec(1 to 3);
begin
v(1) := new integer'(5); -- Error
end procedure;
procedure test7 is
type a;
type a_ptr is access a;
variable p : a_ptr;
begin
p := new a; -- Error
end procedure;
procedure test8 is
variable p : int_vec(1 to 3);
begin
for i in p.all'range loop -- Error
end loop;
end procedure;
end package body;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity SRAM is
Port ( ADDR : in std_logic_vector(15 downto 0);
DATA : inout std_logic_vector(7 downto 0);
OE : in std_logic;
WE : in std_logic;
CS : in std_logic);
end SRAM;
architecture Behavioral of SRAM is
subtype byte is std_logic_vector( 7 downto 0 );
type mem_matrix is array (0 to 65535) of byte;
shared variable matrix:mem_matrix;
begin
read:process (CS,OE,ADDR) is
begin
if (CS ='1') OR (OE = '1') then
DATA <= "ZZZZZZZZ";
else
DATA <= matrix(conv_integer(ADDR));
end if;
end process;
write:process (CS,WE) is
begin
if (CS='0') then
if WE = '0' then
matrix (conv_integer(ADDR)):= DATA;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- The following entity is automatically generated by Quartus (a megafunction).
-- As Altera DE1 board does not have a 25.175 MHz, but a 27 Mhz, we
-- instantiate a PLL (Phase Locked Loop) to divide out 27 MHz clock
-- and reach a satisfiable 25.2MHz clock for our VGA controller (14/15 ratio)
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY vga_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END vga_pll;
ARCHITECTURE SYN OF vga_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 15,
clk0_duty_cycle => 50,
clk0_multiply_by => 14,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone II",
lpm_hint => "CBX_MODULE_PREFIX=vga_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
|
-- standard libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PassMe is
port
(
DSSLOT_CLK : in std_logic;
DSSLOT_ROMCS : in std_logic;
DSSLOT_RESET : in std_logic;
DSSLOT_EEPCS : in std_logic;
DSSLOT_IRQ : out std_logic;
DSSLOT_IO : inout std_logic_vector(7 downto 0);
DSCART_CLK : out std_logic;
DSCART_ROMCS : out std_logic;
DSCART_RESET : out std_logic;
DSCART_EEPCS : out std_logic;
DSCART_IRQ : in std_logic;
DSCART_IO : inout std_logic_vector(7 downto 0);
LED0 : out std_logic
);
end entity;
architecture rtl of passme is
-- removes Xilinx mapping errors
attribute CLOCK_BUFFER : string;
attribute CLOCK_BUFFER of DSSLOT_CLK: signal is "ibuf";
attribute CLOCK_BUFFER of DSCART_CLK: signal is "obuf";
signal is_command : boolean;
signal cmddata_cnt : natural range 0 to 511; -- 8 + 504
signal patched_data : std_logic_vector(7 downto 0);
signal patch_en : boolean;
begin
-- direct passthrough
DSCART_CLK <= DSSLOT_CLK;
DSCART_ROMCS <= DSSLOT_ROMCS;
DSCART_RESET <= DSSLOT_RESET;
DSSLOT_IRQ <= DSCART_IRQ;
DSCART_EEPCS <= DSSLOT_EEPCS;
-- activity LED
LED0 <= not DSSLOT_ROMCS;
-- patch
process (cmddata_cnt)
begin
case (cmddata_cnt - 8) is
--! ALL PATCHES ARE TO BE GENERATED HERE
when others => patched_data <= DSCART_IO;
end case;
end process;
-- dataswitcher
process (DSSLOT_RESET, DSSLOT_ROMCS, DSSLOT_EEPCS, DSSLOT_IO, DSCART_IO, patched_data)
begin
DSSLOT_IO <= (others => 'Z'); -- default is high impedance
DSCART_IO <= (others => 'Z'); -- default is high impedance
if (DSSLOT_RESET='1') then -- if not reset
if (DSSLOT_ROMCS='0') then -- ROM is selected
if (is_command) then -- is command byte
DSCART_IO <= DSSLOT_IO; -- from DS to cartridge
else -- is data byte
if (patch_en) then -- patch enabled
DSSLOT_IO <= patched_data;
else
DSSLOT_IO <= DSCART_IO;
end if;
end if;
elsif (DSSLOT_EEPCS='0') then -- EEPROM is selected
DSCART_IO(7) <= DSSLOT_IO(7); -- pass serial data
DSSLOT_IO(6) <= DSCART_IO(6); -- pass serial data in opposite direction
end if;
end if;
end process;
-- patch_en
process (DSSLOT_RESET, DSSLOT_CLK)
begin
if (DSSLOT_RESET='0') then
patch_en <= true; -- patch header
elsif (rising_edge(DSSLOT_CLK)) then
if (is_command) then
if (DSCART_IO(5) = '1') then -- detect 3C command, assume other command bytes are 00
patch_en <= false; -- do not patch other data
end if;
end if;
end if;
end process;
-- cmddata_cnt, is_command
process (DSSLOT_ROMCS, DSSLOT_CLK)
begin
if (DSSLOT_ROMCS='1') then
cmddata_cnt <= 0; -- new transfer
is_command <= true; -- start with command
elsif (rising_edge(DSSLOT_CLK)) then
if (cmddata_cnt mod 8 = 7) then
is_command <= false; -- next byte is data
end if;
cmddata_cnt <= cmddata_cnt + 1; -- next byte
end if;
end process;
end architecture;
|
-- standard libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PassMe is
port
(
DSSLOT_CLK : in std_logic;
DSSLOT_ROMCS : in std_logic;
DSSLOT_RESET : in std_logic;
DSSLOT_EEPCS : in std_logic;
DSSLOT_IRQ : out std_logic;
DSSLOT_IO : inout std_logic_vector(7 downto 0);
DSCART_CLK : out std_logic;
DSCART_ROMCS : out std_logic;
DSCART_RESET : out std_logic;
DSCART_EEPCS : out std_logic;
DSCART_IRQ : in std_logic;
DSCART_IO : inout std_logic_vector(7 downto 0);
LED0 : out std_logic
);
end entity;
architecture rtl of passme is
-- removes Xilinx mapping errors
attribute CLOCK_BUFFER : string;
attribute CLOCK_BUFFER of DSSLOT_CLK: signal is "ibuf";
attribute CLOCK_BUFFER of DSCART_CLK: signal is "obuf";
signal is_command : boolean;
signal cmddata_cnt : natural range 0 to 511; -- 8 + 504
signal patched_data : std_logic_vector(7 downto 0);
signal patch_en : boolean;
begin
-- direct passthrough
DSCART_CLK <= DSSLOT_CLK;
DSCART_ROMCS <= DSSLOT_ROMCS;
DSCART_RESET <= DSSLOT_RESET;
DSSLOT_IRQ <= DSCART_IRQ;
DSCART_EEPCS <= DSSLOT_EEPCS;
-- activity LED
LED0 <= not DSSLOT_ROMCS;
-- patch
process (cmddata_cnt)
begin
case (cmddata_cnt - 8) is
--! ALL PATCHES ARE TO BE GENERATED HERE
when others => patched_data <= DSCART_IO;
end case;
end process;
-- dataswitcher
process (DSSLOT_RESET, DSSLOT_ROMCS, DSSLOT_EEPCS, DSSLOT_IO, DSCART_IO, patched_data)
begin
DSSLOT_IO <= (others => 'Z'); -- default is high impedance
DSCART_IO <= (others => 'Z'); -- default is high impedance
if (DSSLOT_RESET='1') then -- if not reset
if (DSSLOT_ROMCS='0') then -- ROM is selected
if (is_command) then -- is command byte
DSCART_IO <= DSSLOT_IO; -- from DS to cartridge
else -- is data byte
if (patch_en) then -- patch enabled
DSSLOT_IO <= patched_data;
else
DSSLOT_IO <= DSCART_IO;
end if;
end if;
elsif (DSSLOT_EEPCS='0') then -- EEPROM is selected
DSCART_IO(7) <= DSSLOT_IO(7); -- pass serial data
DSSLOT_IO(6) <= DSCART_IO(6); -- pass serial data in opposite direction
end if;
end if;
end process;
-- patch_en
process (DSSLOT_RESET, DSSLOT_CLK)
begin
if (DSSLOT_RESET='0') then
patch_en <= true; -- patch header
elsif (rising_edge(DSSLOT_CLK)) then
if (is_command) then
if (DSCART_IO(5) = '1') then -- detect 3C command, assume other command bytes are 00
patch_en <= false; -- do not patch other data
end if;
end if;
end if;
end process;
-- cmddata_cnt, is_command
process (DSSLOT_ROMCS, DSSLOT_CLK)
begin
if (DSSLOT_ROMCS='1') then
cmddata_cnt <= 0; -- new transfer
is_command <= true; -- start with command
elsif (rising_edge(DSSLOT_CLK)) then
if (cmddata_cnt mod 8 = 7) then
is_command <= false; -- next byte is data
end if;
cmddata_cnt <= cmddata_cnt + 1; -- next byte
end if;
end process;
end architecture;
|
-- standard libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PassMe is
port
(
DSSLOT_CLK : in std_logic;
DSSLOT_ROMCS : in std_logic;
DSSLOT_RESET : in std_logic;
DSSLOT_EEPCS : in std_logic;
DSSLOT_IRQ : out std_logic;
DSSLOT_IO : inout std_logic_vector(7 downto 0);
DSCART_CLK : out std_logic;
DSCART_ROMCS : out std_logic;
DSCART_RESET : out std_logic;
DSCART_EEPCS : out std_logic;
DSCART_IRQ : in std_logic;
DSCART_IO : inout std_logic_vector(7 downto 0);
LED0 : out std_logic
);
end entity;
architecture rtl of passme is
-- removes Xilinx mapping errors
attribute CLOCK_BUFFER : string;
attribute CLOCK_BUFFER of DSSLOT_CLK: signal is "ibuf";
attribute CLOCK_BUFFER of DSCART_CLK: signal is "obuf";
signal is_command : boolean;
signal cmddata_cnt : natural range 0 to 511; -- 8 + 504
signal patched_data : std_logic_vector(7 downto 0);
signal patch_en : boolean;
begin
-- direct passthrough
DSCART_CLK <= DSSLOT_CLK;
DSCART_ROMCS <= DSSLOT_ROMCS;
DSCART_RESET <= DSSLOT_RESET;
DSSLOT_IRQ <= DSCART_IRQ;
DSCART_EEPCS <= DSSLOT_EEPCS;
-- activity LED
LED0 <= not DSSLOT_ROMCS;
-- patch
process (cmddata_cnt)
begin
case (cmddata_cnt - 8) is
--! ALL PATCHES ARE TO BE GENERATED HERE
when others => patched_data <= DSCART_IO;
end case;
end process;
-- dataswitcher
process (DSSLOT_RESET, DSSLOT_ROMCS, DSSLOT_EEPCS, DSSLOT_IO, DSCART_IO, patched_data)
begin
DSSLOT_IO <= (others => 'Z'); -- default is high impedance
DSCART_IO <= (others => 'Z'); -- default is high impedance
if (DSSLOT_RESET='1') then -- if not reset
if (DSSLOT_ROMCS='0') then -- ROM is selected
if (is_command) then -- is command byte
DSCART_IO <= DSSLOT_IO; -- from DS to cartridge
else -- is data byte
if (patch_en) then -- patch enabled
DSSLOT_IO <= patched_data;
else
DSSLOT_IO <= DSCART_IO;
end if;
end if;
elsif (DSSLOT_EEPCS='0') then -- EEPROM is selected
DSCART_IO(7) <= DSSLOT_IO(7); -- pass serial data
DSSLOT_IO(6) <= DSCART_IO(6); -- pass serial data in opposite direction
end if;
end if;
end process;
-- patch_en
process (DSSLOT_RESET, DSSLOT_CLK)
begin
if (DSSLOT_RESET='0') then
patch_en <= true; -- patch header
elsif (rising_edge(DSSLOT_CLK)) then
if (is_command) then
if (DSCART_IO(5) = '1') then -- detect 3C command, assume other command bytes are 00
patch_en <= false; -- do not patch other data
end if;
end if;
end if;
end process;
-- cmddata_cnt, is_command
process (DSSLOT_ROMCS, DSSLOT_CLK)
begin
if (DSSLOT_ROMCS='1') then
cmddata_cnt <= 0; -- new transfer
is_command <= true; -- start with command
elsif (rising_edge(DSSLOT_CLK)) then
if (cmddata_cnt mod 8 = 7) then
is_command <= false; -- next byte is data
end if;
cmddata_cnt <= cmddata_cnt + 1; -- next byte
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00187
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00187
-- PKG00187/BODY
-- ENT00187(ARCH00187)
-- ENT00187_Test_Bench(ARCH00187_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00187 is
type r_st_rec1 is record
f1 : integer ;
f2 : st_rec1 ;
end record ;
function c_r_st_rec1_1 return r_st_rec1 ;
-- (c_integer_1, c_st_rec1_1) ;
function c_r_st_rec1_2 return r_st_rec1 ;
-- (c_integer_2, c_st_rec1_2) ;
--
type r_st_rec2 is record
f1 : integer ;
f2 : st_rec2 ;
end record ;
function c_r_st_rec2_1 return r_st_rec2 ;
-- (c_integer_1, c_st_rec2_1) ;
function c_r_st_rec2_2 return r_st_rec2 ;
-- (c_integer_2, c_st_rec2_2) ;
--
type r_st_rec3 is record
f1 : integer ;
f2 : st_rec3 ;
end record ;
function c_r_st_rec3_1 return r_st_rec3 ;
-- (c_integer_1, c_st_rec3_1) ;
function c_r_st_rec3_2 return r_st_rec3 ;
-- (c_integer_2, c_st_rec3_2) ;
--
--
end PKG00187 ;
--
package body PKG00187 is
function c_r_st_rec1_1 return r_st_rec1
is begin
return (c_integer_1, c_st_rec1_1) ;
end c_r_st_rec1_1 ;
--
function c_r_st_rec1_2 return r_st_rec1
is begin
return (c_integer_2, c_st_rec1_2) ;
end c_r_st_rec1_2 ;
--
--
function c_r_st_rec2_1 return r_st_rec2
is begin
return (c_integer_1, c_st_rec2_1) ;
end c_r_st_rec2_1 ;
--
function c_r_st_rec2_2 return r_st_rec2
is begin
return (c_integer_2, c_st_rec2_2) ;
end c_r_st_rec2_2 ;
--
--
function c_r_st_rec3_1 return r_st_rec3
is begin
return (c_integer_1, c_st_rec3_1) ;
end c_r_st_rec3_1 ;
--
function c_r_st_rec3_2 return r_st_rec3
is begin
return (c_integer_2, c_st_rec3_2) ;
end c_r_st_rec3_2 ;
--
--
--
end PKG00187 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00187.all ;
entity ENT00187 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_rec1 : chk_sig_type := -1 ;
signal chk_r_st_rec2 : chk_sig_type := -1 ;
signal chk_r_st_rec3 : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_r_st_rec1 : inout r_st_rec1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec1.f2.f2 <=
c_r_st_rec1_2.f2.f2 after 10 ns,
c_r_st_rec1_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00187.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_2.f2.f2 after 10 ns ,
c_r_st_rec1_1.f2.f2 after 20 ns ,
c_r_st_rec1_2.f2.f2 after 30 ns ,
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00187" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <= transport
c_r_st_rec1_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00187" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_2.f2.f2 after 10 ns ,
c_r_st_rec1_1.f2.f2 after 20 ns ,
c_r_st_rec1_2.f2.f2 after 30 ns ,
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00187" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00187" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00187" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_r_st_rec2 : inout r_st_rec2 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec2 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec2.f2.f2 <=
c_r_st_rec2_2.f2.f2 after 10 ns,
c_r_st_rec2_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00187.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_2.f2.f2 after 10 ns ,
c_r_st_rec2_1.f2.f2 after 20 ns ,
c_r_st_rec2_2.f2.f2 after 30 ns ,
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00187" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <= transport
c_r_st_rec2_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00187" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_2.f2.f2 after 10 ns ,
c_r_st_rec2_1.f2.f2 after 20 ns ,
c_r_st_rec2_2.f2.f2 after 30 ns ,
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00187" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00187" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00187" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_r_st_rec3 : inout r_st_rec3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec3 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec3.f2.f2 <=
c_r_st_rec3_2.f2.f2 after 10 ns,
c_r_st_rec3_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00187.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_2.f2.f2 after 10 ns ,
c_r_st_rec3_1.f2.f2 after 20 ns ,
c_r_st_rec3_2.f2.f2 after 30 ns ,
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00187" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <= transport
c_r_st_rec3_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00187" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_2.f2.f2 after 10 ns ,
c_r_st_rec3_1.f2.f2 after 20 ns ,
c_r_st_rec3_2.f2.f2 after 30 ns ,
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00187" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00187" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00187" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00187 ;
--
architecture ARCH00187 of ENT00187 is
signal s_r_st_rec1 : r_st_rec1
:= c_r_st_rec1_1 ;
signal s_r_st_rec2 : r_st_rec2
:= c_r_st_rec2_1 ;
signal s_r_st_rec3 : r_st_rec3
:= c_r_st_rec3_1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_r_st_rec1,
counter,
correct,
savtime,
chk_r_st_rec1
) ;
wait until (not s_r_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_r_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_r_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_r_st_rec2,
counter,
correct,
savtime,
chk_r_st_rec2
) ;
wait until (not s_r_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_r_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_r_st_rec3,
counter,
correct,
savtime,
chk_r_st_rec3
) ;
wait until (not s_r_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_r_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
--
end ARCH00187 ;
--
entity ENT00187_Test_Bench is
end ENT00187_Test_Bench ;
--
architecture ARCH00187_Test_Bench of ENT00187_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00187 ( ARCH00187 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00187_Test_Bench ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCM1 is
port (CLKIN_IN : in std_logic;
RST : in std_logic := '0';
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic;
LOCKED : out std_logic
);
end DCM1;
architecture BEHAVIORAL of DCM1 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0,
CLKFX_MULTIPLY => 31,
CLKFX_DIVIDE => 26,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.344,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => RST,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_OUT,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => LOCKED,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
entity aggr1 is
end aggr1;
architecture behav of aggr1 is
procedure proc (b, c : out bit_vector) is
begin
b := (others => '0');
c := ('1', others => '0');
end proc;
begin
end behav;
|
entity aggr1 is
end aggr1;
architecture behav of aggr1 is
procedure proc (b, c : out bit_vector) is
begin
b := (others => '0');
c := ('1', others => '0');
end proc;
begin
end behav;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 35456)
`protect data_block
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fs4=
`protect end_protected
|
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Entity of authenticated encryption unit.
--!
--! Entity for dummy1 core
--!
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity AEAD is
generic (
--! I/O size (bits)
G_W : integer := 32; --! Public data input
G_SW : integer := 32; --! Secret data input
--! Reset behavior
G_ASYNC_RSTN : boolean := False; --! Async active low reset
--! Special features parameters
G_ENABLE_PAD : boolean := True; --! Enable padding
G_CIPH_EXP : boolean := False; --! Ciphertext expansion
G_REVERSE_CIPH : boolean := False; --! Reversed ciphertext
G_MERGE_TAG : boolean := False; --! Merge tag with data segment
--! Block size (bits)
G_ABLK_SIZE : integer := 128; --! Associated data
G_DBLK_SIZE : integer := 128; --! Data
G_KEY_SIZE : integer := 128; --! Key
G_TAG_SIZE : integer := 128; --! Tag
--! Padding options
G_PAD_STYLE : integer := 1; --! Pad style
G_PAD_AD : integer := 1; --! Padding behavior for AD
G_PAD_D : integer := 1 --! Padding behavior for Data
);
port (
--! Global ports
clk : in std_logic;
rst : in std_logic;
--! Publica data ports
pdi_data : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Secret data ports
sdi_data : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out ports
do_data : out std_logic_vector(G_W -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD; |
--!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library riverlib;
use riverlib.river_cfg.all;
entity FpuTop is
generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_ivec : in std_logic_vector(Instr_FPU_Total-1 downto 0);
i_a : in std_logic_vector(63 downto 0);
i_b : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_ex_invalidop : out std_logic; -- Exception: invalid operation
o_ex_divbyzero : out std_logic; -- Exception: divide by zero
o_ex_overflow : out std_logic; -- Exception: overflow
o_ex_underflow : out std_logic; -- Exception: underflow
o_ex_inexact : out std_logic; -- Exception: inexact
o_valid : out std_logic;
o_busy : out std_logic
);
end;
architecture arch_FpuTop of FpuTop is
component DoubleAdd is generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_add : in std_logic;
i_sub : in std_logic;
i_eq : in std_logic;
i_lt : in std_logic;
i_le : in std_logic;
i_max : in std_logic;
i_min : in std_logic;
i_a : in std_logic_vector(63 downto 0);
i_b : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_illegal_op : out std_logic;
o_overflow : out std_logic;
o_valid : out std_logic;
o_busy : out std_logic
);
end component;
component DoubleDiv is generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_a : in std_logic_vector(63 downto 0);
i_b : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_illegal_op : out std_logic;
o_divbyzero : out std_logic;
o_overflow : out std_logic;
o_underflow : out std_logic;
o_valid : out std_logic;
o_busy : out std_logic
);
end component;
component DoubleMul is generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_a : in std_logic_vector(63 downto 0);
i_b : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_illegal_op : out std_logic;
o_overflow : out std_logic;
o_valid : out std_logic;
o_busy : out std_logic
);
end component;
component Double2Long is generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_signed : in std_logic;
i_w32 : in std_logic;
i_a : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_overflow : out std_logic;
o_underflow : out std_logic;
o_valid : out std_logic;
o_busy : out std_logic
);
end component;
component Long2Double is generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_signed : in std_logic;
i_w32 : in std_logic;
i_a : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_valid : out std_logic;
o_busy : out std_logic
);
end component;
type RegistersType is record
ivec : std_logic_vector(Instr_FPU_Total-1 downto 0);
busy : std_logic;
ready : std_logic;
a : std_logic_vector(63 downto 0);
b : std_logic_vector(63 downto 0);
result : std_logic_vector(63 downto 0);
ex_invalidop : std_logic; -- Exception: invalid operation
ex_divbyzero : std_logic; -- Exception: divide by zero
ex_overflow : std_logic; -- Exception: overflow
ex_underflow : std_logic; -- Exception: underflow
ex_inexact : std_logic; -- Exception: inexact
ena_fadd : std_logic;
ena_fdiv : std_logic;
ena_fmul : std_logic;
ena_d2l : std_logic;
ena_l2d : std_logic;
ena_w32 : std_logic;
end record;
constant R_RESET : RegistersType := (
(others => '0'), -- ivec
'0', '0', (others => '0'), (others => '0'), -- busy, ready, a, b
(others => '0'), -- result
'0', '0', '0', -- ex_invalidop, ex_divbyzero, ex_overflow
'0', '0', '0', -- ex_underflow, ex_inexact, ena_fadd
'0', '0', '0', '0', -- ena_fdiv, ena_fmul, ena_d2l, ena_l2d
'0' -- ena_w32
);
signal r, rin : RegistersType;
signal w_fadd_d : std_logic;
signal w_fsub_d : std_logic;
signal w_feq_d : std_logic;
signal w_flt_d : std_logic;
signal w_fle_d : std_logic;
signal w_fmax_d : std_logic;
signal w_fmin_d : std_logic;
signal w_fcvt_signed : std_logic;
signal wb_res_fadd : std_logic_vector(63 downto 0);
signal w_valid_fadd : std_logic;
signal w_illegalop_fadd : std_logic;
signal w_overflow_fadd : std_logic;
signal w_busy_fadd : std_logic;
signal wb_res_fdiv : std_logic_vector(63 downto 0);
signal w_valid_fdiv : std_logic;
signal w_illegalop_fdiv : std_logic;
signal w_divbyzero_fdiv : std_logic;
signal w_overflow_fdiv : std_logic;
signal w_underflow_fdiv : std_logic;
signal w_busy_fdiv : std_logic;
signal wb_res_fmul : std_logic_vector(63 downto 0);
signal w_valid_fmul : std_logic;
signal w_illegalop_fmul : std_logic;
signal w_overflow_fmul : std_logic;
signal w_busy_fmul : std_logic;
signal wb_res_d2l : std_logic_vector(63 downto 0);
signal w_valid_d2l : std_logic;
signal w_overflow_d2l : std_logic;
signal w_underflow_d2l : std_logic;
signal w_busy_d2l : std_logic;
signal wb_res_l2d : std_logic_vector(63 downto 0);
signal w_valid_l2d : std_logic;
signal w_busy_l2d : std_logic;
begin
fadd_d0 : DoubleAdd generic map (
async_reset => async_reset
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_ena => r.ena_fadd,
i_add => w_fadd_d,
i_sub => w_fsub_d,
i_eq => w_feq_d,
i_lt => w_flt_d,
i_le => w_fle_d,
i_max => w_fmax_d,
i_min => w_fmin_d,
i_a => r.a,
i_b => r.b,
o_res => wb_res_fadd,
o_illegal_op => w_illegalop_fadd,
o_overflow => w_overflow_fadd,
o_valid => w_valid_fadd,
o_busy => w_busy_fadd
);
fdiv_d0 : DoubleDiv generic map (
async_reset => async_reset
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_ena => r.ena_fdiv,
i_a => r.a,
i_b => r.b,
o_res => wb_res_fdiv,
o_illegal_op => w_illegalop_fdiv,
o_divbyzero => w_divbyzero_fdiv,
o_overflow => w_overflow_fdiv,
o_underflow => w_underflow_fdiv,
o_valid => w_valid_fdiv,
o_busy => w_busy_fdiv
);
fmul_d0 : DoubleMul generic map (
async_reset => async_reset
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_ena => r.ena_fmul,
i_a => r.a,
i_b => r.b,
o_res => wb_res_fmul,
o_illegal_op => w_illegalop_fmul,
o_overflow => w_overflow_fmul,
o_valid => w_valid_fmul,
o_busy => w_busy_fmul
);
d2l_d0 : Double2Long generic map (
async_reset => async_reset
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_ena => r.ena_d2l,
i_signed => w_fcvt_signed,
i_w32 => r.ena_w32,
i_a => r.a,
o_res => wb_res_d2l,
o_overflow => w_overflow_d2l,
o_underflow => w_underflow_d2l,
o_valid => w_valid_d2l,
o_busy => w_busy_d2l
);
l2d_d0 : Long2Double generic map (
async_reset => async_reset
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_ena => r.ena_l2d,
i_signed => w_fcvt_signed,
i_w32 => r.ena_w32,
i_a => r.a,
o_res => wb_res_l2d,
o_valid => w_valid_l2d,
o_busy => w_busy_l2d
);
-- registers:
comb : process(i_nrst, i_ena, i_ivec, i_a, i_b, r,
wb_res_fadd, w_valid_fadd, w_illegalop_fadd, w_overflow_fadd, w_busy_fadd,
wb_res_fdiv, w_valid_fdiv, w_illegalop_fdiv, w_divbyzero_fdiv, w_overflow_fdiv,
w_underflow_fdiv, w_busy_fdiv,
wb_res_fmul, w_valid_fmul, w_illegalop_fmul, w_overflow_fmul, w_busy_fmul,
wb_res_d2l, w_valid_d2l, w_overflow_d2l, w_underflow_d2l, w_busy_d2l,
wb_res_l2d, w_valid_l2d, w_busy_l2d)
variable v : RegistersType;
variable iv : std_logic_vector(Instr_FPU_Total-1 downto 0);
begin
v := r;
iv := i_ivec;
v.ena_fadd := '0';
v.ena_fdiv := '0';
v.ena_fmul := '0';
v.ena_d2l := '0';
v.ena_l2d := '0';
v.ready := '0';
if i_ena = '1' and r.busy = '0' then
v.busy := '1';
v.a := i_a;
v.b := i_b;
v.ivec := i_ivec;
v.ex_invalidop := '0';
v.ex_divbyzero := '0';
v.ex_overflow := '0';
v.ex_underflow := '0';
v.ex_inexact := '0';
v.ena_fadd := iv(Instr_FADD_D - Instr_FADD_D)
or iv(Instr_FSUB_D - Instr_FADD_D)
or iv(Instr_FLE_D - Instr_FADD_D)
or iv(Instr_FLT_D - Instr_FADD_D)
or iv(Instr_FEQ_D - Instr_FADD_D)
or iv(Instr_FMAX_D - Instr_FADD_D)
or iv(Instr_FMIN_D - Instr_FADD_D);
v.ena_fdiv := iv(Instr_FDIV_D - Instr_FADD_D);
v.ena_fmul := iv(Instr_FMUL_D - Instr_FADD_D);
v.ena_d2l := iv(Instr_FCVT_LU_D - Instr_FADD_D)
or iv(Instr_FCVT_L_D - Instr_FADD_D)
or iv(Instr_FCVT_WU_D - Instr_FADD_D)
or iv(Instr_FCVT_W_D - Instr_FADD_D);
v.ena_l2d := iv(Instr_FCVT_D_LU - Instr_FADD_D)
or iv(Instr_FCVT_D_L - Instr_FADD_D)
or iv(Instr_FCVT_D_WU - Instr_FADD_D)
or iv(Instr_FCVT_D_W - Instr_FADD_D);
v.ena_w32 := iv(Instr_FCVT_WU_D - Instr_FADD_D)
or iv(Instr_FCVT_W_D - Instr_FADD_D)
or iv(Instr_FCVT_D_WU - Instr_FADD_D)
or iv(Instr_FCVT_D_W - Instr_FADD_D);
end if;
if r.busy = '1' and (r.ivec(Instr_FMOV_X_D - Instr_FADD_D)
or r.ivec(Instr_FMOV_D_X - Instr_FADD_D)) = '1' then
v.busy := '0';
v.ready := '1';
v.result := r.a;
elsif w_valid_fadd = '1' then
v.busy := '0';
v.ready := '1';
v.result := wb_res_fadd;
v.ex_invalidop := w_illegalop_fadd;
v.ex_overflow := w_overflow_fadd;
elsif w_valid_fdiv = '1' then
v.busy := '0';
v.ready := '1';
v.result := wb_res_fdiv;
v.ex_invalidop := w_illegalop_fdiv;
v.ex_divbyzero := w_divbyzero_fdiv;
v.ex_overflow := w_overflow_fdiv;
v.ex_underflow := w_underflow_fdiv;
elsif w_valid_fmul = '1' then
v.busy := '0';
v.ready := '1';
v.result := wb_res_fmul;
v.ex_invalidop := w_illegalop_fmul;
v.ex_overflow := w_overflow_fmul;
elsif w_valid_d2l = '1' then
v.busy := '0';
v.ready := '1';
v.result := wb_res_d2l;
v.ex_overflow := w_overflow_d2l;
v.ex_underflow := w_underflow_d2l;
elsif w_valid_l2d = '1' then
v.busy := '0';
v.ready := '1';
v.result := wb_res_l2d;
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
rin <= v;
end process;
w_fadd_d <= r.ivec(Instr_FADD_D - Instr_FADD_D);
w_fsub_d <= r.ivec(Instr_FSUB_D - Instr_FADD_D);
w_feq_d <= r.ivec(Instr_FEQ_D - Instr_FADD_D);
w_flt_d <= r.ivec(Instr_FLT_D - Instr_FADD_D);
w_fle_d <= r.ivec(Instr_FLE_D - Instr_FADD_D);
w_fmax_d <= r.ivec(Instr_FMAX_D - Instr_FADD_D);
w_fmin_d <= r.ivec(Instr_FMIN_D - Instr_FADD_D);
w_fcvt_signed <= r.ivec(Instr_FCVT_L_D - Instr_FADD_D) or
r.ivec(Instr_FCVT_D_L - Instr_FADD_D) or
r.ivec(Instr_FCVT_W_D - Instr_FADD_D) or
r.ivec(Instr_FCVT_D_W - Instr_FADD_D);
o_res <= r.result;
o_ex_invalidop <= r.ex_invalidop;
o_ex_divbyzero <= r.ex_divbyzero;
o_ex_overflow <= r.ex_overflow;
o_ex_underflow <= r.ex_underflow;
o_ex_inexact <= r.ex_inexact;
o_valid <= r.ready;
o_busy <= r.busy;
-- registers:
regs : process(i_nrst, i_clk)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_LDEXP.VHD ***
--*** ***
--*** Function: Single Precision Load Exponent ***
--*** ***
--*** ldexp(x,n) - x*2^n - IEEE in and out ***
--*** ***
--*** Created 11/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_ldexp IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END fp_ldexp;
ARCHITECTURE rtl OF fp_ldexp IS
signal signinff : STD_LOGIC;
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal bbff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal signoutff : STD_LOGIC;
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal satoutff, zerooutff, nanoutff : STD_LOGIC;
signal satnode, zeronode, nannode : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzeroin, expmaxin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeronode, expmaxnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeroout, expmaxout : STD_LOGIC;
signal manzeroin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
signoutff <= '0';
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
bbff(k) <= '0';
END LOOP;
satoutff <= '0';
zerooutff <= '0';
nanoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
exponentinff <= exponentin;
mantissainff <= mantissain;
bbff <= bb(10 DOWNTO 1);
signoutff <= signinff;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeronode)) OR satnode OR nannode;
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= (mantissainff(k) AND NOT(zeronode) AND NOT(satnode)) OR nannode;
END LOOP;
satoutff <= satnode;
zerooutff <= zeronode;
nanoutff <= nannode;
END IF;
END IF;
END PROCESS;
expnode <= ("00" & exponentinff) + bbff;
expzeroin(1) <= exponentinff(1);
expmaxin(1) <= exponentinff(1);
gxa: FOR k IN 2 TO 8 GENERATE
expzeroin(k) <= expzeroin(k-1) OR exponentinff(k);
expmaxin(k) <= expmaxin(k-1) AND exponentinff(k);
END GENERATE;
expzeronode(1) <= expnode(1);
expmaxnode(1) <= expnode(1);
gxb: FOR k IN 2 TO 8 GENERATE
expzeronode(k) <= expzeronode(k-1) OR expnode(k);
expmaxnode(k) <= expmaxnode(k-1) AND expnode(k);
END GENERATE;
expzeroout <= NOT(expzeroin(8)) OR (NOT(expzeronode(8)) AND NOT(expnode(9))) OR (expnode(10));
expmaxout <= expmaxin(8) OR (expmaxnode(8) AND NOT(expnode(9))) OR (expnode(9) AND NOT(expnode(10)));
manzeroin(1) <= mantissainff(1);
gma: FOR k IN 2 TO 23 GENERATE
manzeroin(k) <= manzeroin(k-1) OR mantissainff(k);
END GENERATE;
manzero <= NOT(manzeroin(23));
mannonzero <= manzeroin(23);
satnode <= (expmaxin(8) AND NOT(manzeroin(23))) OR expmaxout;
zeronode <= NOT(expzeroin(8)) OR expzeroout;
nannode <= expmaxin(8) AND manzeroin(23);
signout <= signoutff;
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
satout <= satoutff;
zeroout <= zerooutff;
nanout <= nanoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_LDEXP.VHD ***
--*** ***
--*** Function: Single Precision Load Exponent ***
--*** ***
--*** ldexp(x,n) - x*2^n - IEEE in and out ***
--*** ***
--*** Created 11/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_ldexp IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END fp_ldexp;
ARCHITECTURE rtl OF fp_ldexp IS
signal signinff : STD_LOGIC;
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal bbff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal signoutff : STD_LOGIC;
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal satoutff, zerooutff, nanoutff : STD_LOGIC;
signal satnode, zeronode, nannode : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzeroin, expmaxin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeronode, expmaxnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeroout, expmaxout : STD_LOGIC;
signal manzeroin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
signoutff <= '0';
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
bbff(k) <= '0';
END LOOP;
satoutff <= '0';
zerooutff <= '0';
nanoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
exponentinff <= exponentin;
mantissainff <= mantissain;
bbff <= bb(10 DOWNTO 1);
signoutff <= signinff;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeronode)) OR satnode OR nannode;
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= (mantissainff(k) AND NOT(zeronode) AND NOT(satnode)) OR nannode;
END LOOP;
satoutff <= satnode;
zerooutff <= zeronode;
nanoutff <= nannode;
END IF;
END IF;
END PROCESS;
expnode <= ("00" & exponentinff) + bbff;
expzeroin(1) <= exponentinff(1);
expmaxin(1) <= exponentinff(1);
gxa: FOR k IN 2 TO 8 GENERATE
expzeroin(k) <= expzeroin(k-1) OR exponentinff(k);
expmaxin(k) <= expmaxin(k-1) AND exponentinff(k);
END GENERATE;
expzeronode(1) <= expnode(1);
expmaxnode(1) <= expnode(1);
gxb: FOR k IN 2 TO 8 GENERATE
expzeronode(k) <= expzeronode(k-1) OR expnode(k);
expmaxnode(k) <= expmaxnode(k-1) AND expnode(k);
END GENERATE;
expzeroout <= NOT(expzeroin(8)) OR (NOT(expzeronode(8)) AND NOT(expnode(9))) OR (expnode(10));
expmaxout <= expmaxin(8) OR (expmaxnode(8) AND NOT(expnode(9))) OR (expnode(9) AND NOT(expnode(10)));
manzeroin(1) <= mantissainff(1);
gma: FOR k IN 2 TO 23 GENERATE
manzeroin(k) <= manzeroin(k-1) OR mantissainff(k);
END GENERATE;
manzero <= NOT(manzeroin(23));
mannonzero <= manzeroin(23);
satnode <= (expmaxin(8) AND NOT(manzeroin(23))) OR expmaxout;
zeronode <= NOT(expzeroin(8)) OR expzeroout;
nannode <= expmaxin(8) AND manzeroin(23);
signout <= signoutff;
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
satout <= satoutff;
zeroout <= zerooutff;
nanout <= nanoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_LDEXP.VHD ***
--*** ***
--*** Function: Single Precision Load Exponent ***
--*** ***
--*** ldexp(x,n) - x*2^n - IEEE in and out ***
--*** ***
--*** Created 11/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_ldexp IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END fp_ldexp;
ARCHITECTURE rtl OF fp_ldexp IS
signal signinff : STD_LOGIC;
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal bbff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal signoutff : STD_LOGIC;
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal satoutff, zerooutff, nanoutff : STD_LOGIC;
signal satnode, zeronode, nannode : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzeroin, expmaxin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeronode, expmaxnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeroout, expmaxout : STD_LOGIC;
signal manzeroin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
signoutff <= '0';
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
bbff(k) <= '0';
END LOOP;
satoutff <= '0';
zerooutff <= '0';
nanoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
exponentinff <= exponentin;
mantissainff <= mantissain;
bbff <= bb(10 DOWNTO 1);
signoutff <= signinff;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeronode)) OR satnode OR nannode;
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= (mantissainff(k) AND NOT(zeronode) AND NOT(satnode)) OR nannode;
END LOOP;
satoutff <= satnode;
zerooutff <= zeronode;
nanoutff <= nannode;
END IF;
END IF;
END PROCESS;
expnode <= ("00" & exponentinff) + bbff;
expzeroin(1) <= exponentinff(1);
expmaxin(1) <= exponentinff(1);
gxa: FOR k IN 2 TO 8 GENERATE
expzeroin(k) <= expzeroin(k-1) OR exponentinff(k);
expmaxin(k) <= expmaxin(k-1) AND exponentinff(k);
END GENERATE;
expzeronode(1) <= expnode(1);
expmaxnode(1) <= expnode(1);
gxb: FOR k IN 2 TO 8 GENERATE
expzeronode(k) <= expzeronode(k-1) OR expnode(k);
expmaxnode(k) <= expmaxnode(k-1) AND expnode(k);
END GENERATE;
expzeroout <= NOT(expzeroin(8)) OR (NOT(expzeronode(8)) AND NOT(expnode(9))) OR (expnode(10));
expmaxout <= expmaxin(8) OR (expmaxnode(8) AND NOT(expnode(9))) OR (expnode(9) AND NOT(expnode(10)));
manzeroin(1) <= mantissainff(1);
gma: FOR k IN 2 TO 23 GENERATE
manzeroin(k) <= manzeroin(k-1) OR mantissainff(k);
END GENERATE;
manzero <= NOT(manzeroin(23));
mannonzero <= manzeroin(23);
satnode <= (expmaxin(8) AND NOT(manzeroin(23))) OR expmaxout;
zeronode <= NOT(expzeroin(8)) OR expzeroout;
nannode <= expmaxin(8) AND manzeroin(23);
signout <= signoutff;
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
satout <= satoutff;
zeroout <= zerooutff;
nanout <= nanoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_LDEXP.VHD ***
--*** ***
--*** Function: Single Precision Load Exponent ***
--*** ***
--*** ldexp(x,n) - x*2^n - IEEE in and out ***
--*** ***
--*** Created 11/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_ldexp IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END fp_ldexp;
ARCHITECTURE rtl OF fp_ldexp IS
signal signinff : STD_LOGIC;
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal bbff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal signoutff : STD_LOGIC;
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal satoutff, zerooutff, nanoutff : STD_LOGIC;
signal satnode, zeronode, nannode : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzeroin, expmaxin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeronode, expmaxnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeroout, expmaxout : STD_LOGIC;
signal manzeroin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
signoutff <= '0';
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
bbff(k) <= '0';
END LOOP;
satoutff <= '0';
zerooutff <= '0';
nanoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
exponentinff <= exponentin;
mantissainff <= mantissain;
bbff <= bb(10 DOWNTO 1);
signoutff <= signinff;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeronode)) OR satnode OR nannode;
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= (mantissainff(k) AND NOT(zeronode) AND NOT(satnode)) OR nannode;
END LOOP;
satoutff <= satnode;
zerooutff <= zeronode;
nanoutff <= nannode;
END IF;
END IF;
END PROCESS;
expnode <= ("00" & exponentinff) + bbff;
expzeroin(1) <= exponentinff(1);
expmaxin(1) <= exponentinff(1);
gxa: FOR k IN 2 TO 8 GENERATE
expzeroin(k) <= expzeroin(k-1) OR exponentinff(k);
expmaxin(k) <= expmaxin(k-1) AND exponentinff(k);
END GENERATE;
expzeronode(1) <= expnode(1);
expmaxnode(1) <= expnode(1);
gxb: FOR k IN 2 TO 8 GENERATE
expzeronode(k) <= expzeronode(k-1) OR expnode(k);
expmaxnode(k) <= expmaxnode(k-1) AND expnode(k);
END GENERATE;
expzeroout <= NOT(expzeroin(8)) OR (NOT(expzeronode(8)) AND NOT(expnode(9))) OR (expnode(10));
expmaxout <= expmaxin(8) OR (expmaxnode(8) AND NOT(expnode(9))) OR (expnode(9) AND NOT(expnode(10)));
manzeroin(1) <= mantissainff(1);
gma: FOR k IN 2 TO 23 GENERATE
manzeroin(k) <= manzeroin(k-1) OR mantissainff(k);
END GENERATE;
manzero <= NOT(manzeroin(23));
mannonzero <= manzeroin(23);
satnode <= (expmaxin(8) AND NOT(manzeroin(23))) OR expmaxout;
zeronode <= NOT(expzeroin(8)) OR expzeroout;
nannode <= expmaxin(8) AND manzeroin(23);
signout <= signoutff;
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
satout <= satoutff;
zeroout <= zerooutff;
nanout <= nanoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_LDEXP.VHD ***
--*** ***
--*** Function: Single Precision Load Exponent ***
--*** ***
--*** ldexp(x,n) - x*2^n - IEEE in and out ***
--*** ***
--*** Created 11/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_ldexp IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END fp_ldexp;
ARCHITECTURE rtl OF fp_ldexp IS
signal signinff : STD_LOGIC;
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal bbff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal signoutff : STD_LOGIC;
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal satoutff, zerooutff, nanoutff : STD_LOGIC;
signal satnode, zeronode, nannode : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzeroin, expmaxin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeronode, expmaxnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeroout, expmaxout : STD_LOGIC;
signal manzeroin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
signoutff <= '0';
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
bbff(k) <= '0';
END LOOP;
satoutff <= '0';
zerooutff <= '0';
nanoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
exponentinff <= exponentin;
mantissainff <= mantissain;
bbff <= bb(10 DOWNTO 1);
signoutff <= signinff;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeronode)) OR satnode OR nannode;
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= (mantissainff(k) AND NOT(zeronode) AND NOT(satnode)) OR nannode;
END LOOP;
satoutff <= satnode;
zerooutff <= zeronode;
nanoutff <= nannode;
END IF;
END IF;
END PROCESS;
expnode <= ("00" & exponentinff) + bbff;
expzeroin(1) <= exponentinff(1);
expmaxin(1) <= exponentinff(1);
gxa: FOR k IN 2 TO 8 GENERATE
expzeroin(k) <= expzeroin(k-1) OR exponentinff(k);
expmaxin(k) <= expmaxin(k-1) AND exponentinff(k);
END GENERATE;
expzeronode(1) <= expnode(1);
expmaxnode(1) <= expnode(1);
gxb: FOR k IN 2 TO 8 GENERATE
expzeronode(k) <= expzeronode(k-1) OR expnode(k);
expmaxnode(k) <= expmaxnode(k-1) AND expnode(k);
END GENERATE;
expzeroout <= NOT(expzeroin(8)) OR (NOT(expzeronode(8)) AND NOT(expnode(9))) OR (expnode(10));
expmaxout <= expmaxin(8) OR (expmaxnode(8) AND NOT(expnode(9))) OR (expnode(9) AND NOT(expnode(10)));
manzeroin(1) <= mantissainff(1);
gma: FOR k IN 2 TO 23 GENERATE
manzeroin(k) <= manzeroin(k-1) OR mantissainff(k);
END GENERATE;
manzero <= NOT(manzeroin(23));
mannonzero <= manzeroin(23);
satnode <= (expmaxin(8) AND NOT(manzeroin(23))) OR expmaxout;
zeronode <= NOT(expzeroin(8)) OR expzeroout;
nannode <= expmaxin(8) AND manzeroin(23);
signout <= signoutff;
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
satout <= satoutff;
zeroout <= zerooutff;
nanout <= nanoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_LDEXP.VHD ***
--*** ***
--*** Function: Single Precision Load Exponent ***
--*** ***
--*** ldexp(x,n) - x*2^n - IEEE in and out ***
--*** ***
--*** Created 11/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_ldexp IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END fp_ldexp;
ARCHITECTURE rtl OF fp_ldexp IS
signal signinff : STD_LOGIC;
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal bbff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal signoutff : STD_LOGIC;
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal satoutff, zerooutff, nanoutff : STD_LOGIC;
signal satnode, zeronode, nannode : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzeroin, expmaxin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeronode, expmaxnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeroout, expmaxout : STD_LOGIC;
signal manzeroin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
signoutff <= '0';
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
bbff(k) <= '0';
END LOOP;
satoutff <= '0';
zerooutff <= '0';
nanoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
exponentinff <= exponentin;
mantissainff <= mantissain;
bbff <= bb(10 DOWNTO 1);
signoutff <= signinff;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeronode)) OR satnode OR nannode;
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= (mantissainff(k) AND NOT(zeronode) AND NOT(satnode)) OR nannode;
END LOOP;
satoutff <= satnode;
zerooutff <= zeronode;
nanoutff <= nannode;
END IF;
END IF;
END PROCESS;
expnode <= ("00" & exponentinff) + bbff;
expzeroin(1) <= exponentinff(1);
expmaxin(1) <= exponentinff(1);
gxa: FOR k IN 2 TO 8 GENERATE
expzeroin(k) <= expzeroin(k-1) OR exponentinff(k);
expmaxin(k) <= expmaxin(k-1) AND exponentinff(k);
END GENERATE;
expzeronode(1) <= expnode(1);
expmaxnode(1) <= expnode(1);
gxb: FOR k IN 2 TO 8 GENERATE
expzeronode(k) <= expzeronode(k-1) OR expnode(k);
expmaxnode(k) <= expmaxnode(k-1) AND expnode(k);
END GENERATE;
expzeroout <= NOT(expzeroin(8)) OR (NOT(expzeronode(8)) AND NOT(expnode(9))) OR (expnode(10));
expmaxout <= expmaxin(8) OR (expmaxnode(8) AND NOT(expnode(9))) OR (expnode(9) AND NOT(expnode(10)));
manzeroin(1) <= mantissainff(1);
gma: FOR k IN 2 TO 23 GENERATE
manzeroin(k) <= manzeroin(k-1) OR mantissainff(k);
END GENERATE;
manzero <= NOT(manzeroin(23));
mannonzero <= manzeroin(23);
satnode <= (expmaxin(8) AND NOT(manzeroin(23))) OR expmaxout;
zeronode <= NOT(expzeroin(8)) OR expzeroout;
nannode <= expmaxin(8) AND manzeroin(23);
signout <= signoutff;
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
satout <= satoutff;
zeroout <= zerooutff;
nanout <= nanoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_LDEXP.VHD ***
--*** ***
--*** Function: Single Precision Load Exponent ***
--*** ***
--*** ldexp(x,n) - x*2^n - IEEE in and out ***
--*** ***
--*** Created 11/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_ldexp IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END fp_ldexp;
ARCHITECTURE rtl OF fp_ldexp IS
signal signinff : STD_LOGIC;
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal bbff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal signoutff : STD_LOGIC;
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal satoutff, zerooutff, nanoutff : STD_LOGIC;
signal satnode, zeronode, nannode : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzeroin, expmaxin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeronode, expmaxnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeroout, expmaxout : STD_LOGIC;
signal manzeroin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
signoutff <= '0';
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
bbff(k) <= '0';
END LOOP;
satoutff <= '0';
zerooutff <= '0';
nanoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
exponentinff <= exponentin;
mantissainff <= mantissain;
bbff <= bb(10 DOWNTO 1);
signoutff <= signinff;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeronode)) OR satnode OR nannode;
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= (mantissainff(k) AND NOT(zeronode) AND NOT(satnode)) OR nannode;
END LOOP;
satoutff <= satnode;
zerooutff <= zeronode;
nanoutff <= nannode;
END IF;
END IF;
END PROCESS;
expnode <= ("00" & exponentinff) + bbff;
expzeroin(1) <= exponentinff(1);
expmaxin(1) <= exponentinff(1);
gxa: FOR k IN 2 TO 8 GENERATE
expzeroin(k) <= expzeroin(k-1) OR exponentinff(k);
expmaxin(k) <= expmaxin(k-1) AND exponentinff(k);
END GENERATE;
expzeronode(1) <= expnode(1);
expmaxnode(1) <= expnode(1);
gxb: FOR k IN 2 TO 8 GENERATE
expzeronode(k) <= expzeronode(k-1) OR expnode(k);
expmaxnode(k) <= expmaxnode(k-1) AND expnode(k);
END GENERATE;
expzeroout <= NOT(expzeroin(8)) OR (NOT(expzeronode(8)) AND NOT(expnode(9))) OR (expnode(10));
expmaxout <= expmaxin(8) OR (expmaxnode(8) AND NOT(expnode(9))) OR (expnode(9) AND NOT(expnode(10)));
manzeroin(1) <= mantissainff(1);
gma: FOR k IN 2 TO 23 GENERATE
manzeroin(k) <= manzeroin(k-1) OR mantissainff(k);
END GENERATE;
manzero <= NOT(manzeroin(23));
mannonzero <= manzeroin(23);
satnode <= (expmaxin(8) AND NOT(manzeroin(23))) OR expmaxout;
zeronode <= NOT(expzeroin(8)) OR expzeroout;
nannode <= expmaxin(8) AND manzeroin(23);
signout <= signoutff;
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
satout <= satoutff;
zeroout <= zerooutff;
nanout <= nanoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_LDEXP.VHD ***
--*** ***
--*** Function: Single Precision Load Exponent ***
--*** ***
--*** ldexp(x,n) - x*2^n - IEEE in and out ***
--*** ***
--*** Created 11/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_ldexp IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END fp_ldexp;
ARCHITECTURE rtl OF fp_ldexp IS
signal signinff : STD_LOGIC;
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal bbff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal signoutff : STD_LOGIC;
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal satoutff, zerooutff, nanoutff : STD_LOGIC;
signal satnode, zeronode, nannode : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzeroin, expmaxin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeronode, expmaxnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeroout, expmaxout : STD_LOGIC;
signal manzeroin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
signoutff <= '0';
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
bbff(k) <= '0';
END LOOP;
satoutff <= '0';
zerooutff <= '0';
nanoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
exponentinff <= exponentin;
mantissainff <= mantissain;
bbff <= bb(10 DOWNTO 1);
signoutff <= signinff;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeronode)) OR satnode OR nannode;
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= (mantissainff(k) AND NOT(zeronode) AND NOT(satnode)) OR nannode;
END LOOP;
satoutff <= satnode;
zerooutff <= zeronode;
nanoutff <= nannode;
END IF;
END IF;
END PROCESS;
expnode <= ("00" & exponentinff) + bbff;
expzeroin(1) <= exponentinff(1);
expmaxin(1) <= exponentinff(1);
gxa: FOR k IN 2 TO 8 GENERATE
expzeroin(k) <= expzeroin(k-1) OR exponentinff(k);
expmaxin(k) <= expmaxin(k-1) AND exponentinff(k);
END GENERATE;
expzeronode(1) <= expnode(1);
expmaxnode(1) <= expnode(1);
gxb: FOR k IN 2 TO 8 GENERATE
expzeronode(k) <= expzeronode(k-1) OR expnode(k);
expmaxnode(k) <= expmaxnode(k-1) AND expnode(k);
END GENERATE;
expzeroout <= NOT(expzeroin(8)) OR (NOT(expzeronode(8)) AND NOT(expnode(9))) OR (expnode(10));
expmaxout <= expmaxin(8) OR (expmaxnode(8) AND NOT(expnode(9))) OR (expnode(9) AND NOT(expnode(10)));
manzeroin(1) <= mantissainff(1);
gma: FOR k IN 2 TO 23 GENERATE
manzeroin(k) <= manzeroin(k-1) OR mantissainff(k);
END GENERATE;
manzero <= NOT(manzeroin(23));
mannonzero <= manzeroin(23);
satnode <= (expmaxin(8) AND NOT(manzeroin(23))) OR expmaxout;
zeronode <= NOT(expzeroin(8)) OR expzeroout;
nannode <= expmaxin(8) AND manzeroin(23);
signout <= signoutff;
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
satout <= satoutff;
zeroout <= zerooutff;
nanout <= nanoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_LDEXP.VHD ***
--*** ***
--*** Function: Single Precision Load Exponent ***
--*** ***
--*** ldexp(x,n) - x*2^n - IEEE in and out ***
--*** ***
--*** Created 11/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_ldexp IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END fp_ldexp;
ARCHITECTURE rtl OF fp_ldexp IS
signal signinff : STD_LOGIC;
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal bbff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal signoutff : STD_LOGIC;
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal satoutff, zerooutff, nanoutff : STD_LOGIC;
signal satnode, zeronode, nannode : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzeroin, expmaxin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeronode, expmaxnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeroout, expmaxout : STD_LOGIC;
signal manzeroin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
signoutff <= '0';
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
bbff(k) <= '0';
END LOOP;
satoutff <= '0';
zerooutff <= '0';
nanoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
exponentinff <= exponentin;
mantissainff <= mantissain;
bbff <= bb(10 DOWNTO 1);
signoutff <= signinff;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeronode)) OR satnode OR nannode;
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= (mantissainff(k) AND NOT(zeronode) AND NOT(satnode)) OR nannode;
END LOOP;
satoutff <= satnode;
zerooutff <= zeronode;
nanoutff <= nannode;
END IF;
END IF;
END PROCESS;
expnode <= ("00" & exponentinff) + bbff;
expzeroin(1) <= exponentinff(1);
expmaxin(1) <= exponentinff(1);
gxa: FOR k IN 2 TO 8 GENERATE
expzeroin(k) <= expzeroin(k-1) OR exponentinff(k);
expmaxin(k) <= expmaxin(k-1) AND exponentinff(k);
END GENERATE;
expzeronode(1) <= expnode(1);
expmaxnode(1) <= expnode(1);
gxb: FOR k IN 2 TO 8 GENERATE
expzeronode(k) <= expzeronode(k-1) OR expnode(k);
expmaxnode(k) <= expmaxnode(k-1) AND expnode(k);
END GENERATE;
expzeroout <= NOT(expzeroin(8)) OR (NOT(expzeronode(8)) AND NOT(expnode(9))) OR (expnode(10));
expmaxout <= expmaxin(8) OR (expmaxnode(8) AND NOT(expnode(9))) OR (expnode(9) AND NOT(expnode(10)));
manzeroin(1) <= mantissainff(1);
gma: FOR k IN 2 TO 23 GENERATE
manzeroin(k) <= manzeroin(k-1) OR mantissainff(k);
END GENERATE;
manzero <= NOT(manzeroin(23));
mannonzero <= manzeroin(23);
satnode <= (expmaxin(8) AND NOT(manzeroin(23))) OR expmaxout;
zeronode <= NOT(expzeroin(8)) OR expzeroout;
nannode <= expmaxin(8) AND manzeroin(23);
signout <= signoutff;
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
satout <= satoutff;
zeroout <= zerooutff;
nanout <= nanoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_LDEXP.VHD ***
--*** ***
--*** Function: Single Precision Load Exponent ***
--*** ***
--*** ldexp(x,n) - x*2^n - IEEE in and out ***
--*** ***
--*** Created 11/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_ldexp IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END fp_ldexp;
ARCHITECTURE rtl OF fp_ldexp IS
signal signinff : STD_LOGIC;
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal bbff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal signoutff : STD_LOGIC;
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal satoutff, zerooutff, nanoutff : STD_LOGIC;
signal satnode, zeronode, nannode : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzeroin, expmaxin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeronode, expmaxnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeroout, expmaxout : STD_LOGIC;
signal manzeroin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
signoutff <= '0';
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
bbff(k) <= '0';
END LOOP;
satoutff <= '0';
zerooutff <= '0';
nanoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
exponentinff <= exponentin;
mantissainff <= mantissain;
bbff <= bb(10 DOWNTO 1);
signoutff <= signinff;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeronode)) OR satnode OR nannode;
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= (mantissainff(k) AND NOT(zeronode) AND NOT(satnode)) OR nannode;
END LOOP;
satoutff <= satnode;
zerooutff <= zeronode;
nanoutff <= nannode;
END IF;
END IF;
END PROCESS;
expnode <= ("00" & exponentinff) + bbff;
expzeroin(1) <= exponentinff(1);
expmaxin(1) <= exponentinff(1);
gxa: FOR k IN 2 TO 8 GENERATE
expzeroin(k) <= expzeroin(k-1) OR exponentinff(k);
expmaxin(k) <= expmaxin(k-1) AND exponentinff(k);
END GENERATE;
expzeronode(1) <= expnode(1);
expmaxnode(1) <= expnode(1);
gxb: FOR k IN 2 TO 8 GENERATE
expzeronode(k) <= expzeronode(k-1) OR expnode(k);
expmaxnode(k) <= expmaxnode(k-1) AND expnode(k);
END GENERATE;
expzeroout <= NOT(expzeroin(8)) OR (NOT(expzeronode(8)) AND NOT(expnode(9))) OR (expnode(10));
expmaxout <= expmaxin(8) OR (expmaxnode(8) AND NOT(expnode(9))) OR (expnode(9) AND NOT(expnode(10)));
manzeroin(1) <= mantissainff(1);
gma: FOR k IN 2 TO 23 GENERATE
manzeroin(k) <= manzeroin(k-1) OR mantissainff(k);
END GENERATE;
manzero <= NOT(manzeroin(23));
mannonzero <= manzeroin(23);
satnode <= (expmaxin(8) AND NOT(manzeroin(23))) OR expmaxout;
zeronode <= NOT(expzeroin(8)) OR expzeroout;
nannode <= expmaxin(8) AND manzeroin(23);
signout <= signoutff;
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
satout <= satoutff;
zeroout <= zerooutff;
nanout <= nanoutff;
END rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp_arith is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1; -- '0': non-stallable; '1': stallable
rst_mode : natural range 0 to 2 := 1; -- '0': none; '1': async; '2': sync
op_iso_mode : natural range 0 to 4 := 0); -- '0': apply Power Compiler user setting; '1': noop; '2': and; '3': or; '4' preferred style...'and'
port (
clk : in std_logic; -- register clock
rst_n : in std_logic; -- register reset
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end component;
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
component DW02_mult_2_stage
generic( A_width: POSITIVE; -- multiplier wordlength
B_width: POSITIVE); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
CLK : in std_logic; -- clock for the stage registers.
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp_arith is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1; -- '0': non-stallable; '1': stallable
rst_mode : natural range 0 to 2 := 1; -- '0': none; '1': async; '2': sync
op_iso_mode : natural range 0 to 4 := 0); -- '0': apply Power Compiler user setting; '1': noop; '2': and; '3': or; '4' preferred style...'and'
port (
clk : in std_logic; -- register clock
rst_n : in std_logic; -- register reset
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end component;
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
component DW02_mult_2_stage
generic( A_width: POSITIVE; -- multiplier wordlength
B_width: POSITIVE); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
CLK : in std_logic; -- clock for the stage registers.
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp_arith is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1; -- '0': non-stallable; '1': stallable
rst_mode : natural range 0 to 2 := 1; -- '0': none; '1': async; '2': sync
op_iso_mode : natural range 0 to 4 := 0); -- '0': apply Power Compiler user setting; '1': noop; '2': and; '3': or; '4' preferred style...'and'
port (
clk : in std_logic; -- register clock
rst_n : in std_logic; -- register reset
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end component;
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
component DW02_mult_2_stage
generic( A_width: POSITIVE; -- multiplier wordlength
B_width: POSITIVE); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
CLK : in std_logic; -- clock for the stage registers.
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp_arith is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1; -- '0': non-stallable; '1': stallable
rst_mode : natural range 0 to 2 := 1; -- '0': none; '1': async; '2': sync
op_iso_mode : natural range 0 to 4 := 0); -- '0': apply Power Compiler user setting; '1': noop; '2': and; '3': or; '4' preferred style...'and'
port (
clk : in std_logic; -- register clock
rst_n : in std_logic; -- register reset
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end component;
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
component DW02_mult_2_stage
generic( A_width: POSITIVE; -- multiplier wordlength
B_width: POSITIVE); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
CLK : in std_logic; -- clock for the stage registers.
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc791.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b02x00p03n01i00791ent_1 IS
END ;
-- legal. with entity_simple_name
ENTITY c01s01b02x00p03n01i00791ent_2 IS
END c01s01b02x00p03n01i00791ent_2 ;
-- legal. begin with no statements following
ENTITY c01s01b02x00p03n01i00791ent_3 IS
begin
END c01s01b02x00p03n01i00791ent_3;
-- legal. no space before semicolon
ENTITY c01s01b02x00p03n01i00791ent_4 IS
END c01s01b02x00p03n01i00791ent_4;
-- legal. NEW line before semicolon
ENTITY c01s01b02x00p03n01i00791ent_5 IS
END c01s01b02x00p03n01i00791ent_5
;
--------------------------------
ENTITY c01s01b02x00p03n01i00791ent IS
END c01s01b02x00p03n01i00791ent;
ARCHITECTURE c01s01b02x00p03n01i00791arch OF c01s01b02x00p03n01i00791ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b02x00p03n01i00791"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b02x00p03n01i00791arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc791.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b02x00p03n01i00791ent_1 IS
END ;
-- legal. with entity_simple_name
ENTITY c01s01b02x00p03n01i00791ent_2 IS
END c01s01b02x00p03n01i00791ent_2 ;
-- legal. begin with no statements following
ENTITY c01s01b02x00p03n01i00791ent_3 IS
begin
END c01s01b02x00p03n01i00791ent_3;
-- legal. no space before semicolon
ENTITY c01s01b02x00p03n01i00791ent_4 IS
END c01s01b02x00p03n01i00791ent_4;
-- legal. NEW line before semicolon
ENTITY c01s01b02x00p03n01i00791ent_5 IS
END c01s01b02x00p03n01i00791ent_5
;
--------------------------------
ENTITY c01s01b02x00p03n01i00791ent IS
END c01s01b02x00p03n01i00791ent;
ARCHITECTURE c01s01b02x00p03n01i00791arch OF c01s01b02x00p03n01i00791ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b02x00p03n01i00791"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b02x00p03n01i00791arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc791.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b02x00p03n01i00791ent_1 IS
END ;
-- legal. with entity_simple_name
ENTITY c01s01b02x00p03n01i00791ent_2 IS
END c01s01b02x00p03n01i00791ent_2 ;
-- legal. begin with no statements following
ENTITY c01s01b02x00p03n01i00791ent_3 IS
begin
END c01s01b02x00p03n01i00791ent_3;
-- legal. no space before semicolon
ENTITY c01s01b02x00p03n01i00791ent_4 IS
END c01s01b02x00p03n01i00791ent_4;
-- legal. NEW line before semicolon
ENTITY c01s01b02x00p03n01i00791ent_5 IS
END c01s01b02x00p03n01i00791ent_5
;
--------------------------------
ENTITY c01s01b02x00p03n01i00791ent IS
END c01s01b02x00p03n01i00791ent;
ARCHITECTURE c01s01b02x00p03n01i00791arch OF c01s01b02x00p03n01i00791ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b02x00p03n01i00791"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b02x00p03n01i00791arch;
|
------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) <2013> <Shimafuji Electric Inc., Osaka University, JAXA>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package SpaceWireCODECIPPackage is
--------------------------------------------------------------------------------
-- Declare constants.
--------------------------------------------------------------------------------
constant gDisconnectCountValue : integer range 0 to 255 := 141; -- transmitClock period * gDisconnectCountValue = 850ns.
constant gTimer6p4usValue : integer range 0 to 1023 := 320; -- Clock period * gTimer6p4usValue = 6.4us.
constant gTimer12p8usValue : integer range 0 to 2047 := 640; -- Clock period * gTimer12p8usValue = 12.8us.
constant gInitializeTransmitClockDivideValue : std_logic_vector (5 downto 0) := "001001"; -- transmitClock frequency / (gInitializeTransmitClockDivideValue + 1) = 10MHz.
type bit32X8Array is array (7 downto 0) of std_logic_vector (31 downto 0);
end SpaceWireCODECIPPackage;
package body SpaceWireCODECIPPackage is
end SpaceWireCODECIPPackage;
|
-- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.vital_timing.ALL;
USE IEEE.vital_primitives.ALL;
package CYCLONEIV_HSSI_COMPONENTS is
-- VITAL constants BEGIN
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- VITAL constants END
-- GENERIC utility functions BEGIN
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bit (arg : boolean) return std_logic;
function str2bin (s : string) return std_logic_vector;
function str2int (s : string) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function int2bit (arg : integer) return std_logic;
function tx_top_ctrl_in_width(
double_data_mode : string;
ser_double_data_mode : string
) return integer;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer;
function rx_top_ctrl_out_width(
double_data_mode : string;
des_double_data_mode : string
) return integer;
function rx_top_basic_width (channel_width : integer) return integer;
function rx_top_num_of_basic (channel_width : integer) return integer;
function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic;
function reduction_or (val : std_logic_vector) return std_logic;
function reduction_nor (val : std_logic_vector) return std_logic;
function reduction_xor (val : std_logic_vector) return std_logic;
function reduction_and (val : std_logic_vector) return std_logic;
function reduction_nand (val : std_logic_vector) return std_logic;
function alpha_tolower (given_string : string) return string;
function cycloneiv_tx_pcs_mph_fifo_xn_mapping (ph_fifo_xn_select : integer; ph_fifo_xn_mapping0 : string; ph_fifo_xn_mapping1 : string; ph_fifo_xn_mapping2 : string) return string;
function cycloneiv_tx_pcs_mphfifo_index ( ph_fifo_xn_select : integer) return integer;
function cycloneiv_tx_pcs_miqp_phfifo_index ( ph_fifo_xn_select : integer) return integer;
-- GENERIC utility functions END
TYPE CMU_MULT_STATE_TYPE IS (INITIAL,INACTIVE,ACTIVE);
--
-- cycloneiv_hssi_tx_pma
--
COMPONENT cycloneiv_hssi_tx_pma
GENERIC (
enable_diagnostic_loopback : STRING := "false";
enable_reverse_serial_loopback : STRING := "false";
enable_txclkout_loopback : STRING := "false";
lpm_type : STRING := "cycloneiv_hssi_tx_pma";
channel_number : INTEGER := 0;
common_mode : STRING := "0.65V";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
logical_channel_address : INTEGER := 0;
preemp_tap_1 : INTEGER := 0;
protocol_hint : STRING := "basic";
effective_data_rate : STRING := "unused";
rx_detect : INTEGER := 0;
serialization_factor : INTEGER := 8;
slew_rate : STRING := "low";
termination : STRING := "OCT 100 Ohms";
use_external_termination : STRING := "false";
use_rx_detect : STRING := "false";
vod_selection : INTEGER := 0
);
PORT (
cgbpowerdn : IN STD_LOGIC := '0';
datain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0');
detectrxpowerdown : IN STD_LOGIC := '0';
diagnosticlpbkin : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
fastrefclk0in : IN STD_LOGIC := '0';
forceelecidle : IN STD_LOGIC := '0';
powerdn : IN STD_LOGIC := '0';
refclk0in : IN STD_LOGIC := '0';
refclk0inpulse : IN STD_LOGIC := '0';
reverselpbkin : IN STD_LOGIC := '0';
rxdetectclk : IN STD_LOGIC := '0';
rxdetecten : IN STD_LOGIC := '0';
txpmareset : IN STD_LOGIC := '0';
clockout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
rxdetectvalidout : OUT STD_LOGIC;
rxfoundout : OUT STD_LOGIC;
seriallpbkout : OUT STD_LOGIC
);
END COMPONENT;
--
-- cycloneiv_hssi_rx_pma
--
COMPONENT cycloneiv_hssi_rx_pma
GENERIC (
lpm_type : STRING := "cycloneiv_hssi_rx_pma";
allow_serial_loopback : STRING := "false";
channel_number : INTEGER := 0;
common_mode : STRING := "0.82V";
deserialization_factor : INTEGER := 8;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
enable_local_divider : STRING := "false";
enable_dpa_shift : STRING := "false";
enable_initial_phase_selection : STRING := "false";
enable_pd_counter_accumulate_mode : STRING := "false";
enable_ltd : STRING := "false";
enable_ltr : STRING := "false";
eq_dc_gain : INTEGER := 0;
eq_setting : INTEGER := 1;
force_signal_detect : STRING := "true";
initial_phase_value : INTEGER := 0;
logical_channel_address : INTEGER := 0;
offset_cancellation : INTEGER := 0;
pi_frequency_selector : INTEGER := 0;
ppm_gen1_2_xcnt_en : INTEGER := 1;
ppm_post_eidle : INTEGER := 0;
pd1_counter_setting : INTEGER := 5;
pd2_counter_setting : INTEGER := 5;
pd_rising_edge_only : STRING := "false";
phase_step_add_setting : INTEGER := 2;
phase_step_sub_setting : INTEGER := 1;
ppmselect : INTEGER := 0;
protocol_hint : STRING := "basic";
effective_data_rate : STRING := "unused";
send_reverse_serial_loopback_data : STRING := "false";
send_reverse_serial_loopback_recovered_clk : STRING := "false";
signal_detect_hysteresis : INTEGER := 4;
signal_detect_hysteresis_valid_threshold : INTEGER := 1;
signal_detect_loss_threshold : INTEGER := 1;
termination : STRING := "OCT 100 Ohms";
use_external_termination : STRING := "false";
loop_1_digital_filter : INTEGER := 8;
enable_second_order_loop : STRING := "false"
);
PORT (
crupowerdn : IN STD_LOGIC := '0';
datain : IN STD_LOGIC := '0';
deserclock : IN STD_LOGIC := '0';
dpashift : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
locktodata : IN STD_LOGIC := '0';
locktoref : IN STD_LOGIC := '0';
powerdn : IN STD_LOGIC := '0';
ppmdetectrefclk : IN STD_LOGIC := '0';
rxpmareset : IN STD_LOGIC := '0';
seriallpbkin : IN STD_LOGIC := '0';
testbussel : IN STD_LOGIC_VECTOR(3 DOWNTO 0):= (others => '0');
analogtestbus : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clockout : OUT STD_LOGIC;
datastrobeout : OUT STD_LOGIC;
diagnosticlpbkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
freqlocked : OUT STD_LOGIC;
locktorefout : OUT STD_LOGIC;
recoverdataout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
reverselpbkout : OUT STD_LOGIC;
signaldetect : OUT STD_LOGIC
);
END COMPONENT;
--
-- cycloneiv_hssi_tx_pcs
--
COMPONENT cycloneiv_hssi_tx_pcs
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_bitslipboundaryselect :VitalDelayArrayType01(4 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_ctrlenable :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datain :VitalDelayArrayType01(39 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datainfull :VitalDelayArrayType01(43 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_detectrxloop : VitalDelayType01 := DefpropDelay01;
tipd_digitalreset : VitalDelayType01 := DefpropDelay01;
tipd_dispval :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(149 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_enrevparallellpbk : VitalDelayType01 := DefpropDelay01;
tipd_forcedisp :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_forcedispcompliance : VitalDelayType01 := DefpropDelay01;
tipd_forceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_freezptr : VitalDelayType01 := DefpropDelay01;
tipd_hipdatain :VitalDelayArrayType01(9 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hipdetectrxloop : VitalDelayType01 := DefpropDelay01;
tipd_hipelecidleinfersel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hipforceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_hippowerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hiptxdeemph : VitalDelayType01 := DefpropDelay01;
tipd_hiptxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_invpol : VitalDelayType01 := DefpropDelay01;
tipd_iqpphfifoxnwrenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnrdenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnbytesel :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnrdclk :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_localrefclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifobyteserdisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbytesel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnbottomwrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntopwrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoptrsreset : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnptrsreset :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnrdenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfiforddisable : VitalDelayType01 := DefpropDelay01;
tipd_phfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_phfifowrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntopbytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntoprdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottombytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntoprdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnrdclk :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnbottomrdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottomrdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnwrenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipestatetransdone : VitalDelayType01 := DefpropDelay01;
tipd_pipetxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipetxdeemph : VitalDelayType01 := DefpropDelay01;
tipd_pipetxswing : VitalDelayType01 := DefpropDelay01;
tipd_powerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_prbscidenable : VitalDelayType01 := DefpropDelay01;
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchisdone : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchxndone : VitalDelayType01 := DefpropDelay01;
tipd_refclk : VitalDelayType01 := DefpropDelay01;
tipd_revparallelfdbk :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_xgmctrl : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain :VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_phfifooverflow_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "cycloneiv_hssi_tx_pcs";
allow_polarity_inversion : STRING := "false";
bitslip_enable : STRING := "false";
channel_bonding : STRING := "none"; -- none, x8, x4
channel_number : INTEGER := 0;
channel_width : INTEGER := 8;
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false"; --NEW_PARAM, RTL=
datapath_protocol : STRING := "basic"; --replaced by protocol_hint
disable_ph_low_latency_mode : STRING := "false";
disparity_mode : STRING := "none"; -- legacy, new, none
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
elec_idle_delay : INTEGER := 6; -- new in 6.0 <3-6>
enable_bit_reversal : STRING := "false";
enable_idle_selection : STRING := "false";
enable_phfifo_bypass : STRING := "false";
enable_reverse_parallel_loopback : STRING := "false";
enable_self_test_mode : STRING := "false";
enc_8b_10b_compatibility_mode : STRING := "true";
enc_8b_10b_mode : STRING := "none"; -- cascade, normal, none
force_echar : STRING := "false";
force_kchar : STRING := "false";
hip_enable : STRING := "false";
logical_channel_address : INTEGER := 0;
migrated_from_prev_family : STRING := "false";
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
pipe_voltage_swing_control : STRING := "false"; --NEW_PARAM, RTL=
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : INTEGER := 0;
protocol_hint : STRING := "basic";
refclk_select : STRING := "local"; -- cmu_clk_divider
reset_clock_output_during_digital_reset : STRING := "false";
self_test_mode : STRING := "incremental";
use_double_data_mode : STRING := "false";
wr_clk_mux_select : STRING := "core_clk" -- INT_CLK // int_clk
);
PORT (
bitslipboundaryselect : IN STD_LOGIC_VECTOR(4 DOWNTO 0) := (others => '0');
coreclk : IN STD_LOGIC := '0';
ctrlenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
datain : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0');
datainfull : IN STD_LOGIC_VECTOR(21 DOWNTO 0) := (others => '0'); -- WYS_TO_CHANGE
detectrxloop : IN STD_LOGIC := '0';
digitalreset : IN STD_LOGIC := '0';
dispval : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(149 DOWNTO 0) := (others => '0');
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
enrevparallellpbk : IN STD_LOGIC := '0';
forcedisp : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); --fix_width
forceelecidle : IN STD_LOGIC := '0';
hipdatain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0');
hipdetectrxloop : IN STD_LOGIC := '0';
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
hipforceelecidle : IN STD_LOGIC := '0';
hippowerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
invpol : IN STD_LOGIC := '0';
localrefclk : IN STD_LOGIC := '0';
phfiforddisable : IN STD_LOGIC := '0';
phfiforeset : IN STD_LOGIC := '0';
phfifowrenable : IN STD_LOGIC := '1';
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdclk : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
pipestatetransdone : IN STD_LOGIC := '0';
pipetxswing : IN STD_LOGIC := '0'; --NEW; RTL=txswing
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
prbscidenable : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
refclk : IN STD_LOGIC := '0';
revparallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0');
xgmctrl : IN STD_LOGIC := '0';
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
clkout : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(149 DOWNTO 0);
forceelecidleout : OUT STD_LOGIC;
grayelecidleinferselout : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
hiptxclkout : OUT STD_LOGIC;
parallelfdbkout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
phfifooverflow : OUT STD_LOGIC;
phfiforddisableout : OUT STD_LOGIC;
phfiforesetout : OUT STD_LOGIC;
phfifounderflow : OUT STD_LOGIC;
phfifowrenableout : OUT STD_LOGIC;
pipeenrevparallellpbkout : OUT STD_LOGIC;
pipepowerdownout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pipepowerstateout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rdenablesync : OUT STD_LOGIC;
txdetectrx : OUT STD_LOGIC;
xgmctrlenable : OUT STD_LOGIC;
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
--
-- cycloneiv_hssi_rx_pcs
--
COMPONENT cycloneiv_hssi_rx_pcs
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_a1a2size : VitalDelayType01 := DefpropDelay01;
tipd_alignstatus : VitalDelayType01 := DefpropDelay01;
tipd_alignstatussync : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_cdrctrllocktorefcl : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_digitalreset : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_dprioin : VitalDelayArrayType01(399 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_elecidleinfersel : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_enabledeskew : VitalDelayType01 := DefpropDelay01;
tipd_enabyteord : VitalDelayType01 := DefpropDelay01;
tipd_enapatternalign : VitalDelayType01 := DefpropDelay01;
tipd_fifordin : VitalDelayType01 := DefpropDelay01;
tipd_fiforesetrd : VitalDelayType01 := DefpropDelay01;
tipd_hip8b10binvpolarity : VitalDelayType01 := DefpropDelay01;
tipd_hipelecidleinfersel : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hippowerdown : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_invpol : VitalDelayType01 := DefpropDelay01;
tipd_localrefclk : VitalDelayType01 := DefpropDelay01;
tipd_masterclk : VitalDelayType01 := DefpropDelay01;
tipd_parallelfdbk : VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifordenable : VitalDelayType01 := DefpropDelay01;
tipd_phfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_phfifowrdisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01;
tipd_pipe8b10binvpolarity : VitalDelayType01 := DefpropDelay01;
tipd_pipepowerdown : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipepowerstate : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_powerdn : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_prbscidenable : VitalDelayType01 := DefpropDelay01;
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_recoveredclk : VitalDelayType01 := DefpropDelay01;
tipd_refclk : VitalDelayType01 := DefpropDelay01;
tipd_revbitorderwa : VitalDelayType01 := DefpropDelay01;
tipd_revbyteorderwa : VitalDelayType01 := DefpropDelay01;
tipd_rmfifordena : VitalDelayType01 := DefpropDelay01;
tipd_rmfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_rmfifowrena : VitalDelayType01 := DefpropDelay01;
tipd_rxdetectvalid : VitalDelayType01 := DefpropDelay01;
tipd_rxfound : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_signaldetected : VitalDelayType01 := DefpropDelay01;
tipd_xgmctrlin : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_phfifordenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_phfifordenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_a1a2sizeout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_byteorderalignstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_ctrldetect_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataoutfull_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_disperr_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_errdetect_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_patterndetect_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifooverflow_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatadeleted_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatainserted_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_runningdisp_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_syncstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipebufferstat_posedge : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_pipestatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipephydonestatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipedatavalid_posedge : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "cycloneiv_hssi_rx_pcs";
auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0;
auto_spd_phystatus_notify_count : INTEGER := 0;
align_ordered_set_based : STRING := "false";
align_pattern : STRING := "0101111100"; -- word align: size of align_pattern_length;
align_pattern_length : INTEGER := 10; -- <7, 8, 10, 16, 20, 32, 40>;
align_to_deskew_pattern_pos_disp_only : STRING := "false"; -- <true/false>;
allow_align_polarity_inversion : STRING := "false";
allow_pipe_polarity_inversion : STRING := "false";
bit_slip_enable : STRING := "false";
byte_order_back_compat_enable : STRING := "false";
byte_order_invalid_code_or_run_disp_error : STRING := "false";
byte_order_mode : STRING := "none"; --NEW_PARAM_replace byte_ordering_mode
byte_order_pad_pattern : STRING := "0101111100"; -- <10-bit binary string>;
byte_order_pattern : STRING := "0101111100"; -- <10-bit binary string>;
byte_order_pld_ctrl_enable : STRING := "false"; --ww47_cram added in build 165
cdrctrl_bypass_ppm_detector_cycle : INTEGER := 0;
cdrctrl_cid_mode_enable : STRING := "false";
cdrctrl_enable : STRING := "false";
cdrctrl_mask_cycle : INTEGER := 0;
cdrctrl_min_lock_to_ref_cycle : INTEGER := 0;
cdrctrl_rxvalid_mask : STRING := "false";
channel_bonding : STRING := "none"; -- <none, x4, x8>;
channel_number : INTEGER := 0; -- <integer 0-3>;
channel_width : INTEGER := 10; -- <integer 8,10,16,20,32,40>;
clk1_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, MASTER_CLK, LOCAL_REFCLK, DIGITAL_REFCLK>;
clk2_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, LOCAL_REFCLK, DIGITAL_REFCLK, CORE_CLK>;
clk_pd_enable : STRING := "false"; --ww47_cram_p1
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false";
datapath_protocol : STRING := "basic"; -- <basic/pipe/xaui> replaced by protocol_hint
dec_8b_10b_compatibility_mode : STRING := "true";
dec_8b_10b_mode : STRING := "none"; -- <normal/cascaded/none>;
deskew_pattern : STRING := "1100111100"; -- K28.3
disable_auto_idle_insertion : STRING := "false";
disable_running_disp_in_word_align : STRING := "false";
disallow_kchar_after_pattern_ordered_set : STRING := "false";
elec_idle_eios_detect_priority_over_eidle_disable : STRING := "false";
elec_idle_gen1_sigdet_enable : STRING := "false";
elec_idle_infer_enable : STRING := "false";
elec_idle_num_com_detect : INTEGER := 0;
enable_bit_reversal : STRING := "false";
enable_self_test_mode : STRING := "false";
error_from_wa_or_8b_10b_select : STRING := "false";
force_signal_detect_dig : STRING := "false";
hip_enable : STRING := "false";
infiniband_invalid_code : INTEGER := 0; -- <integer 0-3>;
insert_pad_on_underflow : STRING := "false";
logical_channel_address : INTEGER := 0;
num_align_code_groups_in_ordered_set : INTEGER := 1; -- <integer 0-3>;
num_align_cons_good_data : INTEGER := 3; -- wordalign<Integer 1-256>;
num_align_cons_pat : INTEGER := 4; -- <Integer 1-256>;
num_align_loss_sync_error : INTEGER := 1; --NEW_PARAM_replace align_loss_sync_error_num
ph_fifo_low_latency_enable : STRING := "false";
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
phystatus_delay : INTEGER := 0;
phystatus_reset_toggle : STRING := "false";
pipe_auto_speed_nego_enable : STRING := "false";
prbs_all_one_detect : STRING := "false";
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : INTEGER := 0;
protocol_hint : STRING := "basic";
rate_match_back_to_back : STRING := "false";
rate_match_delete_threshold : INTEGER := 13;
rate_match_empty_threshold : INTEGER := 5;
rate_match_fifo_mode : STRING := "false"; -- <normal/cascaded/generic/cascaded_generic/none> in s2gx, bool in s4gx;
rate_match_full_threshold : INTEGER := 20;
rate_match_insert_threshold : INTEGER := 11;
rate_match_ordered_set_based : STRING := "false"; -- <integer 10 or 20>;
rate_match_pattern1 : STRING := "00000000000010111100"; -- <20-bit binary string>;
rate_match_pattern2 : STRING := "00000000000010111100"; -- <20-bit binary string>;
rate_match_pattern_size : INTEGER := 10; -- <integer 10 or 20>;
rate_match_pipe_enable : STRING := "false";
rate_match_reset_enable : STRING := "true"; --NEW_PARAM - default diff from atom
rate_match_skip_set_based : STRING := "false";
rate_match_start_threshold : INTEGER := 7;
rd_clk_mux_select : STRING := "int clock"; -- <INT_CLK, CORE_CLK>;
recovered_clk_mux_select : STRING := "recovered clock"; -- <RECVD_CLK, LOCAL_REFCLK, DIGITAL_REFCLK>;
reset_clock_output_during_digital_reset : STRING := "false";
run_length : INTEGER := 200; -- <5-320 or 4-254 depending on the deserialization factor>;
run_length_enable : STRING := "false";
rx_detect_bypass : STRING := "false";
rx_phfifo_wait_cnt : INTEGER := 32;
rxstatus_error_report_mode : INTEGER := 0;
self_test_mode : STRING := "incremental"; -- <PRBS_7,PRBS_8,PRBS_10,PRBS_23,low_freq,mixed_freq,high_freq,incremental,cjpat,crpat>;
test_bus_sel : INTEGER := 0;
use_alignment_state_machine : STRING := "false";
use_deskew_fifo : STRING := "false";
use_double_data_mode : STRING := "false";
use_parallel_loopback : STRING := "false";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000"
);
PORT (
a1a2size : IN STD_LOGIC := '0';
alignstatus : IN STD_LOGIC := '0';
alignstatussync : IN STD_LOGIC := '0';
bitslip : IN STD_LOGIC := '0';
cdrctrllocktorefcl : IN STD_LOGIC := '0'; -- pld_ltr
coreclk : IN STD_LOGIC := '0';
datain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0'); --NEW: updated width
digitalreset : IN STD_LOGIC := '0';
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
enabledeskew : IN STD_LOGIC := '0';
enabyteord : IN STD_LOGIC := '0';
enapatternalign : IN STD_LOGIC := '0';
fifordin : IN STD_LOGIC := '0';
fiforesetrd : IN STD_LOGIC := '0';
grayelecidleinferselfromtx : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
hip8b10binvpolarity : IN STD_LOGIC := '0'; -- hip_rxpolarity
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- hip_eidleinfersel_ch
hippowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- hip_powerdown_ch
invpol : IN STD_LOGIC := '0';
localrefclk : IN STD_LOGIC := '0';
masterclk : IN STD_LOGIC := '0';
parallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0');
phfifordenable : IN STD_LOGIC := '1';
phfiforeset : IN STD_LOGIC := '0';
phfifowrdisable : IN STD_LOGIC := '0';
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrclk : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
pipe8b10binvpolarity : IN STD_LOGIC := '0';
pipeenrevparallellpbkfromtx : IN STD_LOGIC := '0';
pipepowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
pipepowerstate : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
pmatestbusin : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
prbscidenable : IN STD_LOGIC := '0'; -- prbs_cid_en
quadreset : IN STD_LOGIC := '0';
recoveredclk : IN STD_LOGIC := '0';
refclk : IN STD_LOGIC := '0';
revbitorderwa : IN STD_LOGIC := '0';
rmfifordena : IN STD_LOGIC := '0';
rmfiforeset : IN STD_LOGIC := '0';
rmfifowrena : IN STD_LOGIC := '0';
rxdetectvalid : IN STD_LOGIC := '0';
rxfound : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
signaldetected : IN STD_LOGIC := '0';
xauidelcondmet : IN STD_LOGIC := '0';
xauififoovr : IN STD_LOGIC := '0';
xauiinsertincomplete : IN STD_LOGIC := '0';
xauilatencycomp : IN STD_LOGIC := '0';
xgmctrlin : IN STD_LOGIC := '0';
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); --54 ins ---
wareset : IN STD_LOGIC := '0';
revbyteorderwa : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(399 DOWNTO 0) := (others => '0');
a1a2sizeout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
a1detect : OUT STD_LOGIC;
a2detect : OUT STD_LOGIC;
adetectdeskew : OUT STD_LOGIC;
alignstatussyncout : OUT STD_LOGIC;
bistdone : OUT STD_LOGIC;
bisterr : OUT STD_LOGIC;
bitslipboundaryselectout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --ww47_out wa_boundary
byteorderalignstatus : OUT STD_LOGIC;
cdrctrlearlyeios : OUT STD_LOGIC; --ww47_out Asserted when K_I or K_X_I is detected on the incoming data. To PMA and/or PLD?
cdrctrllocktorefclkout : OUT STD_LOGIC; --ww47_out Force CDR(RX PLL) to LTR.
clkout : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
ctrldetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
dataoutfull : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- new in 6.1
disperr : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
errdetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
fifordout : OUT STD_LOGIC;
hipdataout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); --ww47_out hip_rxd_ch(8:0)
hipdatavalid : OUT STD_LOGIC; --ww47_out hip_rxvalid
hipelecidle : OUT STD_LOGIC; --ww47_out hip_rxelecidle
hipphydonestatus : OUT STD_LOGIC; --ww47_out hip_phystatus
hipstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --ww47_out hip_rxstatus_ch(2:0)
k1detect : OUT STD_LOGIC;
k2detect : OUT STD_LOGIC;
patterndetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
phfifooverflow : OUT STD_LOGIC;
phfifordenableout : OUT STD_LOGIC;
phfiforesetout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
phfifounderflow : OUT STD_LOGIC;
phfifowrdisableout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
pipebufferstat : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pipedatavalid : OUT STD_LOGIC;
pipeelecidle : OUT STD_LOGIC;
pipephydonestatus : OUT STD_LOGIC;
pipestatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
rdalign : OUT STD_LOGIC;
revparallelfdbkdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
rlv : OUT STD_LOGIC;
rmfifodatadeleted : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rmfifodatainserted : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rmfifoempty : OUT STD_LOGIC;
rmfifofull : OUT STD_LOGIC;
runningdisp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
signaldetect : OUT STD_LOGIC;
syncstatus : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
syncstatusdeskew : OUT STD_LOGIC;
xauidelcondmetout : OUT STD_LOGIC;
xauififoovrout : OUT STD_LOGIC;
xauiinsertincompleteout : OUT STD_LOGIC;
xauilatencycompout : OUT STD_LOGIC;
xgmctrldet : OUT STD_LOGIC;
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
xgmdatavalid : OUT STD_LOGIC;
xgmrunningdisp : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC_VECTOR(399 DOWNTO 0);
pipestatetransdoneout : OUT STD_LOGIC
);
END COMPONENT;
--
-- cycloneiv_hssi_cmu
--
COMPONENT cycloneiv_hssi_cmu
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_txphfiforddisable : VitalDelayType01 := DefpropDelay01;
tipd_txctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txclk : VitalDelayType01 := DefpropDelay01;
tipd_syncstatus : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxpcsdprioin : VitalDelayArrayType01(1599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_scanclk : VitalDelayType01 := DefpropDelay01;
tipd_rdenablesync : VitalDelayType01 := DefpropDelay01;
tipd_dpclk : VitalDelayType01 := DefpropDelay01;
tipd_rxphfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_testin : VitalDelayArrayType01(9999 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxrunningdisp : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatavalid : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txpcsdprioin : VitalDelayArrayType01(599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin : VitalDelayType01 := DefpropDelay01;
tipd_rxctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxanalogreset : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txphfifowrenable : VitalDelayType01 := DefpropDelay01;
tipd_rxphfifowrdisable : VitalDelayType01 := DefpropDelay01;
tipd_rdalign : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_fixedclk : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_scanmode : VitalDelayType01 := DefpropDelay01;
tipd_rxphfifordenable : VitalDelayType01 := DefpropDelay01;
tipd_txphfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_txcoreclk : VitalDelayType01 := DefpropDelay01;
tipd_adet : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxcoreclk : VitalDelayType01 := DefpropDelay01;
tipd_dprioload : VitalDelayType01 := DefpropDelay01;
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_nonuserfromcal : VitalDelayType01 := DefpropDelay01;
tipd_scanshift : VitalDelayType01 := DefpropDelay01;
tipd_txpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_recovclk : VitalDelayType01 := DefpropDelay01;
tipd_rxpowerdown : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dpriooe_posedge : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "cycloneiv_hssi_cmu";
auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0;
auto_spd_phystatus_notify_count : INTEGER := 0;
coreclk_out_gated_by_quad_reset : STRING := "false"; -- cycloneiv_new
devaddr : INTEGER := 1;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
in_xaui_mode : STRING := "false";
pipe_auto_speed_nego_enable : STRING := "false";
portaddr : INTEGER := 1;
rx0_channel_bonding : STRING := "none";
rx0_clk1_mux_select : STRING := "recovered clock";
rx0_clk2_mux_select : STRING := "recovered clock";
rx0_clk_pd_enable : STRING := "false";
rx0_ph_fifo_reg_mode : STRING := "false";
rx0_ph_fifo_reset_enable : STRING := "false";
rx0_ph_fifo_user_ctrl_enable : STRING := "false";
rx0_rd_clk_mux_select : STRING := "int clock";
rx0_recovered_clk_mux_select : STRING := "recovered clock";
rx0_reset_clock_output_during_digital_reset : STRING := "false";
rx0_use_double_data_mode : STRING := "false";
rx_xaui_sm_backward_compatible_enable : STRING := "false";
select_refclk_dig : STRING := "false"; -- cycloneiv_new
tx0_channel_bonding : STRING := "none";
tx0_clk_pd_enable : STRING := "false";
tx0_ph_fifo_reset_enable : STRING := "false";
tx0_ph_fifo_user_ctrl_enable : STRING := "false";
tx0_rd_clk_mux_select : STRING := "int clock";
tx0_reset_clock_output_during_digital_reset : STRING := "false";
tx0_use_double_data_mode : STRING := "false";
tx0_wr_clk_mux_select : STRING := "int_clk";
tx_xaui_sm_backward_compatible_enable : STRING := "false";
use_coreclk_out_post_divider : STRING := "false"; -- cycloneiv_new
use_deskew_fifo : STRING := "false";
rx_logical_to_physical_mapping : INTEGER := 0;
tx_logical_to_physical_mapping : INTEGER := 0;
pll_logical_to_physical_mapping : INTEGER := 0;
rx0_logical_to_physical_mapping : INTEGER := 0;
rx1_logical_to_physical_mapping : INTEGER := 1;
rx2_logical_to_physical_mapping : INTEGER := 2;
rx3_logical_to_physical_mapping : INTEGER := 3;
tx0_logical_to_physical_mapping : INTEGER := 0;
tx1_logical_to_physical_mapping : INTEGER := 1;
tx2_logical_to_physical_mapping : INTEGER := 2;
tx3_logical_to_physical_mapping : INTEGER := 3;
sim_dump_dprio_internal_reg_at_time : INTEGER := 0; -- in ps
sim_dump_filename : STRING := "sim_dprio_dump.txt" -- over-write when multiple CMUs
);
PORT (
adet : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
dpclk : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
dprioload : IN STD_LOGIC := '0';
fixedclk : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
nonuserfromcal : IN STD_LOGIC := '0';
pmacramtest : IN STD_LOGIC := '0'; -- new 9.0 ww47
quadreset : IN STD_LOGIC := '0';
rdalign : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rdenablesync : IN STD_LOGIC := '0';
recovclk : IN STD_LOGIC := '0';
refclkdig : IN STD_LOGIC := '0'; -- cycloneiv_new
rxanalogreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxcoreclk : IN STD_LOGIC := '0';
rxctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
rxdatavalid : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxpcsdprioin : IN STD_LOGIC_VECTOR(1599 DOWNTO 0) := (others => '0');
rxphfifordenable : IN STD_LOGIC := '0';
rxphfiforeset : IN STD_LOGIC := '0';
rxphfifowrdisable : IN STD_LOGIC := '0';
rxpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0) := (others => '0');
rxpowerdown : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxrunningdisp : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
scanclk : IN STD_LOGIC := '0';
scanmode : IN STD_LOGIC := '0';
scanshift : IN STD_LOGIC := '0';
syncstatus : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
testin : IN STD_LOGIC_VECTOR(1999 DOWNTO 0) := (others => '0');
txclk : IN STD_LOGIC := '0';
txcoreclk : IN STD_LOGIC := '0';
txctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
txdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
txdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
txpcsdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0) := (others => '0');
txphfiforddisable : IN STD_LOGIC := '0';
txphfiforeset : IN STD_LOGIC := '0';
txphfifowrenable : IN STD_LOGIC := '0';
txpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0) := (others => '0');
alignstatus : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC; -- stnngray_new
digitaltestout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
dpriodisableout : OUT STD_LOGIC;
dpriooe : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC;
enabledeskew : OUT STD_LOGIC;
fiforesetrd : OUT STD_LOGIC;
quadresetout : OUT STD_LOGIC;
refclkout : OUT STD_LOGIC; -- cycloneiv_new
rxanalogresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxcrupowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rxdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxibpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxpcsdprioout : OUT STD_LOGIC_VECTOR(1599 DOWNTO 0);
rxphfifox4byteselout : OUT STD_LOGIC;
rxphfifox4wrclkout : OUT STD_LOGIC;
rxphfifox4rdenableout : OUT STD_LOGIC;
rxphfifox4wrenableout : OUT STD_LOGIC;
rxpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0);
testout : OUT STD_LOGIC_VECTOR(2399 DOWNTO 0);
txanalogresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
txdetectrxpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdividerpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txobpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txpcsdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0);
txphfifox4byteselout : OUT STD_LOGIC;
txphfifox4rdclkout : OUT STD_LOGIC;
txphfifox4rdenableout : OUT STD_LOGIC;
txphfifox4wrenableout : OUT STD_LOGIC;
txpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0)
);
END COMPONENT;
--
-- cycloneiv_hssi_calibration_block
--
COMPONENT cycloneiv_hssi_calibration_block
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_clk : VitalDelayType01 := DefpropDelay01;
lpm_type : string := "cycloneiv_hssi_calibration_block";
cont_cal_mode : string := "false";
enable_rx_cal_tw : string := "false";
enable_tx_cal_tw : string := "false";
migrated_from_prev_family : string := "false";
rtest : string := "false";
rx_cal_wt_value : integer := 0;
send_rx_cal_status : string := "true";
tx_cal_wt_value : integer := 1);
PORT (
clk : IN std_logic := '0';
powerdn : IN std_logic := '0';
testctrl : IN std_logic := '0';
calibrationstatus : OUT std_logic_vector(4 DOWNTO 0);
nonusertocmu : OUT std_logic
);
END COMPONENT;
end cycloneiv_hssi_components;
package body CYCLONEIV_HSSI_COMPONENTS is
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function str2bin (s : string) return std_logic_vector is
variable len : integer := s'length;
variable result : std_logic_vector(39 DOWNTO 0) := (OTHERS => '0');
variable i : integer;
begin
for i in 1 to len loop
case s(i) is
when '0' => result(len - i) := '0';
when '1' => result(len - i) := '1';
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
end loop;
return result;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function tx_top_ctrl_in_width(double_data_mode : string;
ser_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (ser_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end tx_top_ctrl_in_width;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is
variable real_widthb : integer;
begin
if (des_double_data_mode = "true") then
real_widthb := 2;
else
real_widthb := 1;
end if;
return real_widthb;
end rx_top_a1k1_out_width;
function rx_top_ctrl_out_width(double_data_mode : string;
des_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (des_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (des_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end rx_top_ctrl_out_width;
function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function rx_top_basic_width (channel_width : integer) return integer is
variable basic_width : integer;
begin
if (channel_width mod 10 = 0) then
basic_width := 10;
else
basic_width := 8;
end if;
return(basic_width);
end rx_top_basic_width;
function rx_top_num_of_basic (channel_width : integer) return integer is
variable num_of_basic : integer;
begin
if (channel_width mod 10 = 0) then
num_of_basic := channel_width/10;
else
num_of_basic := channel_width/8;
end if;
return(num_of_basic);
end rx_top_num_of_basic;
function reduction_or (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(result);
end reduction_or;
function reduction_nor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(not result);
end reduction_nor;
function reduction_xor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result xor val(i);
end loop;
return(result);
end reduction_xor;
function reduction_and (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(result);
end reduction_and;
function reduction_nand (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(not result);
end reduction_nand;
function alpha_tolower (given_string : string) return string is
-- VARIABLE DECLARATION
variable string_length : integer := given_string'length;
variable result_string : string(1 to 25) := " ";
begin
for i in 1 to string_length loop
case given_string(i) is
when 'A' => result_string(i) := 'a';
when 'B' => result_string(i) := 'b';
when 'C' => result_string(i) := 'c';
when 'D' => result_string(i) := 'd';
when 'E' => result_string(i) := 'e';
when 'F' => result_string(i) := 'f';
when 'G' => result_string(i) := 'g';
when 'H' => result_string(i) := 'h';
when 'I' => result_string(i) := 'i';
when 'J' => result_string(i) := 'j';
when 'K' => result_string(i) := 'k';
when 'L' => result_string(i) := 'l';
when 'M' => result_string(i) := 'm';
when 'N' => result_string(i) := 'n';
when 'O' => result_string(i) := 'o';
when 'P' => result_string(i) := 'p';
when 'Q' => result_string(i) := 'q';
when 'R' => result_string(i) := 'r';
when 'S' => result_string(i) := 's';
when 'T' => result_string(i) := 't';
when 'U' => result_string(i) := 'u';
when 'V' => result_string(i) := 'v';
when 'W' => result_string(i) := 'w';
when 'X' => result_string(i) := 'x';
when 'Y' => result_string(i) := 'y';
when 'Z' => result_string(i) := 'z';
when others => result_string(i) := given_string(i);
end case;
end loop;
return (result_string(1 to string_length));
end alpha_tolower;
function cycloneiv_tx_pcs_mph_fifo_xn_mapping (ph_fifo_xn_select : integer; ph_fifo_xn_mapping0 : string; ph_fifo_xn_mapping1 : string; ph_fifo_xn_mapping2 : string) return string is
begin
CASE ph_fifo_xn_select IS
WHEN 0 => RETURN ph_fifo_xn_mapping0;
WHEN 1 => RETURN ph_fifo_xn_mapping1;
WHEN 2 => RETURN ph_fifo_xn_mapping2;
WHEN OTHERS => RETURN "none";
END CASE;
end cycloneiv_tx_pcs_mph_fifo_xn_mapping;
function cycloneiv_tx_pcs_mphfifo_index ( ph_fifo_xn_select : integer) return integer is
variable fifo_index : integer;
begin
if ((ph_fifo_xn_select = 0) OR (ph_fifo_xn_select = 1) or (ph_fifo_xn_select = 2)) then
fifo_index := ph_fifo_xn_select;
else
fifo_index := 0;
end if;
return(fifo_index);
end cycloneiv_tx_pcs_mphfifo_index;
function cycloneiv_tx_pcs_miqp_phfifo_index ( ph_fifo_xn_select : integer) return integer is
variable fifo_index : integer;
begin
if ((ph_fifo_xn_select = 0) OR (ph_fifo_xn_select = 1)) then
fifo_index := ph_fifo_xn_select;
else
fifo_index := 0;
end if;
return(fifo_index);
end cycloneiv_tx_pcs_miqp_phfifo_index;
end CYCLONEIV_HSSI_COMPONENTS;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
--========================================================================================================================
-- This VVC was generated with Bitvis VVC Generator
--========================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--========================================================================================================================
--========================================================================================================================
package wishbone_bfm_pkg is
--========================================================================================================================
-- Types and constants for WISHBONE BFM
--========================================================================================================================
constant C_SCOPE : string := "WISHBONE BFM";
type t_wishbone_if is record
-- Common for slave and master interfaces
dat_o : std_logic_vector; -- to dut
dat_i : std_logic_vector; -- from dut
-- Master interface
adr_o : std_logic_vector; -- to dut, address
cyc_o : std_logic; -- to dut, valid bus cycle
stb_o : std_logic; -- to dut, chip select
we_o : std_logic; -- to dut, write enable
ack_i : std_logic; -- from dut
end record;
-- Configuration record to be assigned in the test harness.
type t_wishbone_bfm_config is record
max_wait_cycles : integer;
max_wait_cycles_severity : t_alert_level;
clock_period : time; -- Needed in the VVC
clock_period_margin : time; -- Input clock period margin to specified clock_period
clock_margin_severity : t_alert_level; -- The above margin will have this severity
setup_time : time; -- Setup time for generated signals, set to clock_period/4
hold_time : time; -- Hold time for generated signals, set to clock_period/4
match_strictness : t_match_strictness; -- Matching strictness for std_logic values in check procedures.
id_for_bfm : t_msg_id;
id_for_bfm_wait : t_msg_id;
id_for_bfm_poll : t_msg_id;
end record;
-- Define the default value for the BFM config
constant C_WISHBONE_BFM_CONFIG_DEFAULT : t_wishbone_bfm_config := (
max_wait_cycles => 10,
max_wait_cycles_severity => failure,
clock_period => -1 ns,
clock_period_margin => 0 ns,
clock_margin_severity => TB_ERROR,
setup_time => -1 ns,
hold_time => -1 ns,
match_strictness => MATCH_EXACT,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL
);
--========================================================================================================================
-- BFM procedures
--========================================================================================================================
function init_wishbone_if_signals(
addr_width : natural;
data_width : natural
) return t_wishbone_if;
procedure wishbone_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal wishbone_if : inout t_wishbone_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_wishbone_bfm_config := C_WISHBONE_BFM_CONFIG_DEFAULT
);
procedure wishbone_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal wishbone_if : inout t_wishbone_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_wishbone_bfm_config := C_WISHBONE_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
procedure wishbone_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal wishbone_if : inout t_wishbone_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_wishbone_bfm_config := C_WISHBONE_BFM_CONFIG_DEFAULT
);
end package wishbone_bfm_pkg;
--========================================================================================================================
--========================================================================================================================
package body wishbone_bfm_pkg is
function init_wishbone_if_signals(
addr_width : natural;
data_width : natural
) return t_wishbone_if is
variable result : t_wishbone_if(dat_o(data_width - 1 downto 0),
dat_i(data_width-1 downto 0),
adr_o(addr_width - 1 downto 0)
);
begin
-- BFM to DUT signals
result.dat_o := (result.dat_o'range => '0');
result.adr_o := (result.adr_o'range => '0');
result.cyc_o := '0';
result.stb_o := '0';
result.we_o := '0';
-- DUT to BFM signals
result.dat_i := (result.dat_i'range => 'Z');
result.ack_i := 'Z';
return result;
end function;
procedure wishbone_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal wishbone_if : inout t_wishbone_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_wishbone_bfm_config := C_WISHBONE_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "wishbone_write";
constant proc_call : string := "wishbone_write(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";
-- normalize_and_check to the DUT addr/data widths
variable v_normalized_addr : std_logic_vector(wishbone_if.adr_o'length-1 downto 0) :=
normalize_and_check(std_logic_vector(addr_value), wishbone_if.adr_o, ALLOW_NARROWER, "address", "wishbone_if.adr_o", msg);
variable v_normalized_data : std_logic_vector(wishbone_if.dat_o'length-1 downto 0) :=
normalize_and_check(data_value, wishbone_if.dat_o, ALLOW_NARROWER, "data", "wishbone_if.dat_o", msg);
variable timeout : boolean := false;
variable v_last_falling_edge : time := -1 ns; -- time stamp for clk period checking
begin
-- setup_time and hold_time checking
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_name);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_name);
check_value(config.setup_time > 0 ns, TB_FAILURE, "Sanity check: Check that setup_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_name);
check_value(config.hold_time > 0 ns, TB_FAILURE, "Sanity check: Check that hold_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_name);
-- check if enough room for setup_time in low period
if (clk = '1') and (config.setup_time > (config.clock_period/2 - clk'last_event))then
await_value(clk, '0', 0 ns, config.clock_period/2, TB_FAILURE, proc_name & ": timeout waiting for clk low period for setup_time.");
end if;
-- Wait setup_time specified in config record --wait_until_given_time_after_rising_edge(clk, config.clock_period/4);
wait_until_given_time_after_rising_edge(clk, config.setup_time);
wishbone_if.dat_o <= v_normalized_data;
wishbone_if.adr_o <= v_normalized_addr;
wishbone_if.cyc_o <= '1'; -- Valid bus cycle activated
wishbone_if.stb_o <= '1'; -- Chip-select
wishbone_if.we_o <= '1'; -- Write enable
wait until falling_edge(clk); -- wait for DUT update of signal
-- check if clk period since last rising edge is within specifications and take a new time stamp
if v_last_falling_edge > -1 ns then
check_value_in_range(now - v_last_falling_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
end if;
v_last_falling_edge := now; -- time stamp for clk period checking
for cycle in 1 to config.max_wait_cycles loop
if wishbone_if.ack_i = '0' then
wait until falling_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
if v_last_falling_edge > -1 ns then
check_value_in_range(now - v_last_falling_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
end if;
v_last_falling_edge := now; -- time stamp for clk period checking
else
exit;
end if;
if cycle = config.max_wait_cycles then
timeout := true;
end if;
end loop;
-- did we timeout?
if timeout then
alert(config.max_wait_cycles_severity, proc_call & "=> Failed. Timeout waiting for ack_i" & add_msg_delimiter(msg), scope);
else
wait until rising_edge(clk);
-- Wait hold time specified in config record --wait_until_given_time_after_rising_edge(clk, config.clock_period/4);
wait_until_given_time_after_rising_edge(clk, config.hold_time);
end if;
wishbone_if <= init_wishbone_if_signals(wishbone_if.adr_o'length, wishbone_if.dat_o'length);
log(config.id_for_bfm, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure wishbone_write;
procedure wishbone_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal wishbone_if : inout t_wishbone_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_wishbone_bfm_config := C_WISHBONE_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
-- local_proc_name/call used if called from sequencer or VVC
constant local_proc_name : string := "wishbone_read";
constant local_proc_call : string := local_proc_name & "(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ")";
-- normalize_and_check to the DUT addr/data widths
variable v_normalized_addr : std_logic_vector(wishbone_if.adr_o'length-1 downto 0) :=
normalize_and_check(std_logic_vector(addr_value), wishbone_if.adr_o, ALLOW_NARROWER, "addr", "wishbone_if.adr_o", msg);
variable v_normalized_data : std_logic_vector(wishbone_if.dat_i'length-1 downto 0) :=
normalize_and_check(data_value, wishbone_if.dat_i, ALLOW_NARROWER, "data", "wishbone_if.dat_i", msg);
-- Helper variables
variable timeout : boolean := false;
variable v_last_falling_edge : time := -1 ns; -- time stamp for clk period checking
variable v_last_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable v_proc_call : line;
begin
-- setup_time and hold_time checking
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, local_proc_name);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, local_proc_name);
check_value(config.setup_time > 0 ns, TB_FAILURE, "Sanity check: Check that setup_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, local_proc_name);
check_value(config.hold_time > 0 ns, TB_FAILURE, "Sanity check: Check that hold_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, local_proc_name);
if ext_proc_call = "" then
-- Called directly from sequencer/VVC, log 'wishbone_read...'
write(v_proc_call, local_proc_call);
else
-- Called from another BFM procedure, log 'ext_proc_call while executing wishbone_read...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
-- check if enough room for setup_time in low period
if (clk = '1') and (config.setup_time > (config.clock_period/2 - clk'last_event))then
await_value(clk, '0', 0 ns, config.clock_period/2, TB_FAILURE, local_proc_name & ": timeout waiting for clk low period for setup_time.");
end if;
-- Wait setup_time specified in config record -- wait_until_given_time_after_rising_edge(clk, config.clock_period/4);
wait_until_given_time_after_rising_edge(clk, config.setup_time);
wishbone_if.adr_o <= v_normalized_addr;
wishbone_if.cyc_o <= '1'; -- Valid bus cycle activated
wishbone_if.stb_o <= '1'; -- Chip-select
wishbone_if.we_o <= '0'; -- Read
wait until falling_edge(clk); -- wait for DUT update of signal
-- check if clk period since last rising edge is within specifications and take a new time stamp
if v_last_falling_edge > -1 ns then
check_value_in_range(now - v_last_falling_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
end if;
v_last_falling_edge := now; -- time stamp for clk period checking
for cycle in 1 to config.max_wait_cycles loop
if wishbone_if.ack_i = '0' then
wait until falling_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
if v_last_falling_edge > -1 ns then
check_value_in_range(now - v_last_falling_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
end if;
v_last_falling_edge := now; -- time stamp for clk period checking
else
exit;
end if;
if cycle = config.max_wait_cycles then
timeout := true;
end if;
end loop;
-- did we timeout?
if timeout then
alert(config.max_wait_cycles_severity, v_proc_call.all & "=> Failed. Timeout waiting for ack_i " & add_msg_delimiter(msg), scope);
else
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
if v_last_rising_edge > -1 ns then
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
end if;
v_last_rising_edge := now; -- time stamp for clk period checking
-- Wait hold time specified in config record --wait_until_given_time_after_rising_edge(clk, config.clock_period/4);
wait_until_given_time_after_rising_edge(clk, config.hold_time);
end if;
v_normalized_data := wishbone_if.dat_i;
data_value := v_normalized_data(data_value'length-1 downto 0);
wishbone_if <= init_wishbone_if_signals(wishbone_if.adr_o'length, wishbone_if.dat_i'length);
if ext_proc_call = "" then
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. wishbone_check)
end if;
end procedure wishbone_read;
procedure wishbone_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal wishbone_if : inout t_wishbone_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_wishbone_bfm_config := C_WISHBONE_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "wishbone_check";
constant proc_call : string := "wishbone_check(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
-- normalize_and_check to the DUT addr/data widths
variable v_normalized_data : std_logic_vector(wishbone_if.dat_i'length-1 downto 0) :=
normalize_and_check(data_exp, wishbone_if.dat_i, ALLOW_NARROWER, "data", "wishbone_if.dat_i", msg);
-- Helper variables
variable v_data_value : std_logic_vector(wishbone_if.dat_i'length-1 downto 0) := (others => '0');
variable v_check_ok : boolean := true;
variable v_alert_radix : t_radix;
begin
wishbone_read(addr_value, v_data_value, msg, clk, wishbone_if, scope, msg_id_panel, config, proc_call);
for i in v_normalized_data'range loop
-- Allow don't care in expected value and use match strictness from config for comparison
if v_normalized_data(i) = '-' or check_value(v_data_value(i), v_normalized_data(i), config.match_strictness, NO_ALERT, msg) then
v_check_ok := true;
else
v_check_ok := false;
exit;
end if;
end loop;
if not v_check_ok then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_data_value, v_normalized_data, MATCH_STD, NO_ALERT, msg) else HEX;
alert(alert_level, proc_call & "=> Failed. Was " & to_string(v_data_value, v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " & to_string(v_normalized_data, v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
else
log(config.id_for_bfm, proc_call & "=> OK, received data = " & to_string(v_normalized_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure wishbone_check;
end package body wishbone_bfm_pkg;
|
entity file2 is
end entity;
architecture test of file2 is
subtype bit_vec5 is bit_vector(1 to 5);
type ft is file of bit_vec5;
begin
process is
file f : ft;
variable v : bit_vec5;
begin
file_open(f, "test.bin", WRITE_MODE);
v := "10100";
write(f, v);
file_close(f);
v := "00000";
file_open(f, "test.bin", READ_MODE);
read(f, v);
file_close(f);
assert v = "10100";
wait;
end process;
end architecture;
|
entity file2 is
end entity;
architecture test of file2 is
subtype bit_vec5 is bit_vector(1 to 5);
type ft is file of bit_vec5;
begin
process is
file f : ft;
variable v : bit_vec5;
begin
file_open(f, "test.bin", WRITE_MODE);
v := "10100";
write(f, v);
file_close(f);
v := "00000";
file_open(f, "test.bin", READ_MODE);
read(f, v);
file_close(f);
assert v = "10100";
wait;
end process;
end architecture;
|
entity file2 is
end entity;
architecture test of file2 is
subtype bit_vec5 is bit_vector(1 to 5);
type ft is file of bit_vec5;
begin
process is
file f : ft;
variable v : bit_vec5;
begin
file_open(f, "test.bin", WRITE_MODE);
v := "10100";
write(f, v);
file_close(f);
v := "00000";
file_open(f, "test.bin", READ_MODE);
read(f, v);
file_close(f);
assert v = "10100";
wait;
end process;
end architecture;
|
entity file2 is
end entity;
architecture test of file2 is
subtype bit_vec5 is bit_vector(1 to 5);
type ft is file of bit_vec5;
begin
process is
file f : ft;
variable v : bit_vec5;
begin
file_open(f, "test.bin", WRITE_MODE);
v := "10100";
write(f, v);
file_close(f);
v := "00000";
file_open(f, "test.bin", READ_MODE);
read(f, v);
file_close(f);
assert v = "10100";
wait;
end process;
end architecture;
|
entity file2 is
end entity;
architecture test of file2 is
subtype bit_vec5 is bit_vector(1 to 5);
type ft is file of bit_vec5;
begin
process is
file f : ft;
variable v : bit_vec5;
begin
file_open(f, "test.bin", WRITE_MODE);
v := "10100";
write(f, v);
file_close(f);
v := "00000";
file_open(f, "test.bin", READ_MODE);
read(f, v);
file_close(f);
assert v = "10100";
wait;
end process;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity preamp_config is
port(
preamp_done: out std_logic;
send_data: in std_logic;
busy: out std_logic;
gain_in: in std_logic_vector(3 downto 0);
spi_mosi: out std_logic;
spi_sck: out std_logic;
clk: in std_logic
);
end preamp_config;
architecture Behavioral of preamp_config is
type spi_state is (reset,sending,waiting);
signal curr_state: spi_state;
signal divide_count: integer range 0 to 10;
signal divided_clk: std_logic;
signal spi_count: integer range 0 to 9;
signal spi_clk_sig: std_logic := '0';
begin
clk_div: process(clk)
begin
if(rising_edge(clk)) then
case curr_state is
when reset =>
divided_clk <= '0';
divide_count <= 0;
when sending =>
divided_clk <= '0';
divide_count <= divide_count + 1;
if(divide_count = 10) then
divide_count <= 0;
divided_clk <= '1';
end if;
when waiting =>
end case;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
case curr_state is
when reset =>
curr_state <= waiting;
when sending =>
busy <= '1';
if(divided_clk = '1') then
if(spi_count <= 9) then
spi_clk_sig <= not spi_clk_sig;
end if;
if(spi_clk_sig = '1') then
if(spi_count <= 9) then
spi_count <= spi_count + 1;
preamp_done <= '0';
spi_clk_sig <= '0';
else
preamp_done <= '1';
end if;
case spi_count is
when 0 =>
--amp_cs <= '1';
when 1 =>
--amp_cs <= '0';
spi_mosi <= '1';
when 2 =>
spi_mosi <= '0';
when 3 =>
spi_mosi <= '0';
when 4 =>
spi_mosi <= '0';
when 5 =>
spi_mosi <= gain_in(3);
when 6 =>
spi_mosi <= gain_in(2);
when 7 =>
spi_mosi <= gain_in(1);
when 8 =>
spi_mosi <= gain_in(0);
when others =>
spi_mosi <= '0';
--amp_cs <= '1';
preamp_done <= '1';
curr_state <= waiting;
spi_clk_sig <= '0';
end case;
end if;
end if;
when waiting =>
spi_clk_sig <= '0';
spi_count <= 0;
spi_mosi <= '0';
busy <= '0';
if(send_data = '1') then
curr_state <= sending;
end if;
end case;
end if;
end process;
spi_sck <= spi_clk_sig;
end Behavioral;
|
entity e is
end entity;
architecture a of e is
signal x : real := 1.234; -- OK
type my_real is range 0.0 to 1.0; -- OK
begin
process is
variable v : my_real;
begin
x <= x + 6.1215; -- OK
x <= v; -- Error
end process;
process is
variable i : integer;
begin
i := integer(x); -- OK
x <= real(i); -- OK
x <= real(5); -- OK
x <= real(bit'('1')); -- Error
end process;
process is
variable x : real;
begin
x := real'left; -- OK
x := real'right; -- OK
end process;
process is
constant i : integer := 5;
constant r : real := 252.4;
type t is range i to r; -- Error
begin
end process;
end architecture;
|
architecture RTL of FIFO is
begin
-- These are passing
SIG_LABEL : postponed a <= b;
SIG_LABEL : postponed a <= when c = '0' else '1';
SIG_LABEL : postponed with z select
a <= b when z = "000",
c when z = "001";
-- Failing variations
SIG_LABEL : postponed a <= b;
SIG_LABEL : postponed a <= when c = '0' else '1';
SIG_LABEL : postponed with z select
a <= b when z = "000",
c when z = "001";
-- Remove the labels
postponed a <= b;
postponed a <= when c = '0' else '1';
postponed with z select
a <= b when z = "000",
c when z = "001";
-- Remove the postponed keyword
a <= b;
a <= when c = '0' else '1';
with z select
a <= b when z = "000",
c when z = "001";
BLOCK_LABEL : block
begin
a <= b;
z <= x;
end block BLOCK_LABEL;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.fixed_pkg.all;
package test_pkg is
type t_sf_array is array (natural range <>) of sfixed;
impure function do_something(samples : integer; ret_type : sfixed) return t_sf_array;
end package;
package body test_pkg is
impure function do_something(samples : integer; ret_type : sfixed) return t_sf_array is
variable init_array : t_sf_array(0 to samples - 1)(ret_type'left downto ret_type'right) := (others => (others => '0'));
begin
for i in 0 to (samples - 1) loop
init_array(i) := to_sfixed(1.0/real(1+i), ret_type);
end loop;
return init_array;
end function;
end package body;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2661.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02661ent IS
END c13s03b01x00p02n01i02661ent;
ARCHITECTURE c13s03b01x00p02n01i02661arch OF c13s03b01x00p02n01i02661ent IS
BEGIN
TESTING: PROCESS
variable |k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02661 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02661arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2661.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02661ent IS
END c13s03b01x00p02n01i02661ent;
ARCHITECTURE c13s03b01x00p02n01i02661arch OF c13s03b01x00p02n01i02661ent IS
BEGIN
TESTING: PROCESS
variable |k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02661 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02661arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2661.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02661ent IS
END c13s03b01x00p02n01i02661ent;
ARCHITECTURE c13s03b01x00p02n01i02661arch OF c13s03b01x00p02n01i02661ent IS
BEGIN
TESTING: PROCESS
variable |k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02661 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02661arch;
|
-------------------------------------------------------------------------------
-- Title : Dynamic adder/subtractor
-- Project :
-------------------------------------------------------------------------------
-- File : addsub.vhd
-- Author : Aylons <[email protected]>
-- Company :
-- Created : 2014-05-03
-- Last update: 2014-07-21
-- Platform :
-- Standard : VHDL'93/02/08
-------------------------------------------------------------------------------
-- Description: Depening on sub_i, result_o may be a_i + b_i or a_i - b_i.
-- The three widths must all be the same.
-------------------------------------------------------------------------------
-- This file is part of Concordic.
--
-- Concordic is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Concordic is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-03 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity addsub is
port (
a_i : in signed;
b_i : in signed;
sub_i : in boolean;
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
result_o : out signed;
positive_o : out boolean;
negative_o : out boolean
);
end entity addsub;
-------------------------------------------------------------------------------
architecture str of addsub is
constant width : natural := a_i'length;
signal a_1, b_1 : signed(width-1 downto 0) := (others => '0');
signal mux_result : signed (width-1 downto 0) := (others => '0');
begin -- architecture str
assert a_i'length = b_i'length
report "a_i and b_i have different widths"
severity error;
assert a_i'length = result_o'length
report "invalid result_o width"
severity error;
process(clk_i) is
variable result : signed(width-1 downto 0) := (others => '0');
begin
if rising_edge(clk_i) then
if rst_i = '1' then
result_o <= (width-1 downto 0 => '0');
positive_o <= true;
negative_o <= false;
else
if ce_i = '1' then
result := mux_result;
positive_o <= result(result'left) = '0';
negative_o <= result(result'left) = '1';
result_o <= result;
end if;
end if;
end if;
end process;
mux_result <= a_i + b_i when (not sub_i) else a_i - b_i;
end architecture str;
-------------------------------------------------------------------------------
|
entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent is
signal clk : std_logic;
signal v : std_logic_vector (31 downto 0);
begin
dut: entity work.ent
port map (clk => clk, o => v);
process
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
assert v = x"8000_0000" severity failure;
wait;
end process;
end behav;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity FPMultiply is
port( A_in : in std_logic_vector(31 downto 0);
B_in : in std_logic_vector(31 downto 0);
R : out std_logic_vector(31 downto 0));
end FPMultiply;
architecture Behavioral of FPMultiply is
type array32x64 is array (31 downto 0) of std_logic_vector(63 downto 0);
signal shiftArray : array32x64;-- := (others => (others => '0'));
signal resultRaw : std_logic_vector(63 downto 0) := (others => '0');
signal resultCut, resultSigned : std_logic_vector(31 downto 0) := (others => '0');
signal A, B : std_logic_vector(31 downto 0);
signal sign : std_logic;
begin
signs : process (A_in, B_in) is
begin
sign <= A_in(31) xor B_in(31); --Sign is 0 if the result is positive, 1 if negative
--Flip A if it's negative
if A_in(31) = '1' then
A <= (not A_in) + 1;
else
A <= A_in;
end if;
--Flip B if it's negative
if B_in(31) = '1' then
B <= (not B_in) + 1;
else
B <= B_in;
end if;
end process;
shift_mul : process (A, B) is
begin
if B(0) = '1' then
shiftArray(0) <= "00000000000000000000000000000000" & A;
else
shiftArray(0) <= (others => '0');
end if;
if B(1) = '1' then
shiftArray(1) <= "0000000000000000000000000000000" & A & "0";
else
shiftArray(1) <= (others => '0');
end if;
if B(2) = '1' then
shiftArray(2) <= "000000000000000000000000000000" & A & "00";
else
shiftArray(2) <= (others => '0');
end if;
if B(3) = '1' then
shiftArray(3) <= "00000000000000000000000000000" & A & "000";
else
shiftArray(3) <= (others => '0');
end if;
if B(4) = '1' then
shiftArray(4) <= "0000000000000000000000000000" & A & "0000";
else
shiftArray(4) <= (others => '0');
end if;
if B(5) = '1' then
shiftArray(5) <= "000000000000000000000000000" & A & "00000";
else
shiftArray(5) <= (others => '0');
end if;
if B(6) = '1' then
shiftArray(6) <= "00000000000000000000000000" & A & "000000";
else
shiftArray(6) <= (others => '0');
end if;
if B(7) = '1' then
shiftArray(7) <= "0000000000000000000000000" & A & "0000000";
else
shiftArray(7) <= (others => '0');
end if;
if B(8) = '1' then
shiftArray(8) <= "000000000000000000000000" & A & "00000000";
else
shiftArray(8) <= (others => '0');
end if;
if B(9) = '1' then
shiftArray(9) <= "00000000000000000000000" & A & "000000000";
else
shiftArray(9) <= (others => '0');
end if;
if B(10) = '1' then
shiftArray(10) <= "0000000000000000000000" & A & "0000000000";
else
shiftArray(10) <= (others => '0');
end if;
if B(11) = '1' then
shiftArray(11) <= "000000000000000000000" & A & "00000000000";
else
shiftArray(11) <= (others => '0');
end if;
if B(12) = '1' then
shiftArray(12) <= "00000000000000000000" & A & "000000000000";
else
shiftArray(12) <= (others => '0');
end if;
if B(13) = '1' then
shiftArray(13) <= "0000000000000000000" & A & "0000000000000";
else
shiftArray(13) <= (others => '0');
end if;
if B(14) = '1' then
shiftArray(14) <= "000000000000000000" & A & "00000000000000";
else
shiftArray(14) <= (others => '0');
end if;
if B(15) = '1' then
shiftArray(15) <= "00000000000000000" & A & "000000000000000";
else
shiftArray(15) <= (others => '0');
end if;
if B(16) = '1' then
shiftArray(16) <= "0000000000000000" & A & "0000000000000000";
else
shiftArray(16) <= (others => '0');
end if;
if B(17) = '1' then
shiftArray(17) <= "000000000000000" & A & "00000000000000000";
else
shiftArray(17) <= (others => '0');
end if;
if B(18) = '1' then
shiftArray(18) <= "00000000000000" & A & "000000000000000000";
else
shiftArray(18) <= (others => '0');
end if;
if B(19) = '1' then
shiftArray(19) <= "0000000000000" & A & "0000000000000000000";
else
shiftArray(19) <= (others => '0');
end if;
if B(20) = '1' then
shiftArray(20) <= "000000000000" & A & "00000000000000000000";
else
shiftArray(20) <= (others => '0');
end if;
if B(21) = '1' then
shiftArray(21) <= "00000000000" & A & "000000000000000000000";
else
shiftArray(21) <= (others => '0');
end if;
if B(22) = '1' then
shiftArray(22) <= "0000000000" & A & "0000000000000000000000";
else
shiftArray(22) <= (others => '0');
end if;
if B(23) = '1' then
shiftArray(23) <= "000000000" & A & "00000000000000000000000";
else
shiftArray(23) <= (others => '0');
end if;
if B(24) = '1' then
shiftArray(24) <= "00000000" & A & "000000000000000000000000";
else
shiftArray(24) <= (others => '0');
end if;
if B(25) = '1' then
shiftArray(25) <= "0000000" & A & "0000000000000000000000000";
else
shiftArray(25) <= (others => '0');
end if;
if B(26) = '1' then
shiftArray(26) <= "000000" & A & "00000000000000000000000000";
else
shiftArray(26) <= (others => '0');
end if;
if B(27) = '1' then
shiftArray(27) <= "00000" & A & "000000000000000000000000000";
else
shiftArray(27) <= (others => '0');
end if;
if B(28) = '1' then
shiftArray(28) <= "0000" & A & "0000000000000000000000000000";
else
shiftArray(28) <= (others => '0');
end if;
if B(29) = '1' then
shiftArray(29) <= "000" & A & "00000000000000000000000000000";
else
shiftArray(29) <= (others => '0');
end if;
if B(30) = '1' then
shiftArray(30) <= "00" & A & "000000000000000000000000000000";
else
shiftArray(30) <= (others => '0');
end if;
if B(31) = '1' then
shiftArray(31) <= "0" & A & "0000000000000000000000000000000";
else
shiftArray(31) <= (others => '0');
end if;
end process;
resultRaw <= shiftArray(0) + shiftArray(1) + shiftArray(2) + shiftArray(3) + shiftArray(4) + shiftArray(5) + shiftArray(6) + shiftArray(7) +
shiftArray(8) + shiftArray(9) + shiftArray(10) + shiftArray(11) + shiftArray(12) + shiftArray(13) + shiftArray(14) + shiftArray(15) +
shiftArray(16) + shiftArray(17) + shiftArray(18) + shiftArray(19) + shiftArray(20) + shiftArray(21) + shiftArray(22) + shiftArray(23) +
shiftArray(24) + shiftArray(25) + shiftArray(26) + shiftArray(27) + shiftArray(28) + shiftArray(29) + shiftArray(30) + shiftArray(31);
saturate : process(resultRaw) is
begin
if resultRaw(59 downto 0) > x"07FFFFFFFFFFFFFF" then
resultCut <= x"7FFFFFFF";
else
resultCut <= resultRaw(59 downto 28); --Take the middle out as the result
end if;
end process;
apply_sign : process(sign, resultCut) is
begin
if sign = '1' then
resultSigned <= (not resultCut) + 1;
else
resultSigned <= resultCut;
end if;
end process;
R <= resultSigned;
end Behavioral;
|
-- NEED RESULT: ARCH00430: String literals passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00430
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 13.6 (1)
-- 13.6 (2)
-- 13.6 (3)
-- 13.6 (5)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00430)
-- ENT00430_Test_Bench(ARCH00430_Test_Bench)
--
-- REVISION HISTORY:
--
-- 3-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00430 of E00000 is
begin
process
begin
test_report ( "ARCH00430" ,
"String literals" ,
-- this tests 13.6 (1), 13.6 (2) and 13.6 (5)
(string'(" ") /= "") and
(string'("!") /= "") and
(string'("""") /= "") and
(string'("#") /= "") and
(string'("$") /= "") and
(string'("%") /= "") and
(string'("&") /= "") and
(string'("'") /= "") and
(string'("(") /= "") and
(string'(")") /= "") and
(string'("*") /= "") and
(string'("+") /= "") and
(string'(",") /= "") and
(string'("-") /= "") and
(string'(".") /= "") and
(string'("/") /= "") and
(string'("0") /= "") and
(string'("1") /= "") and
(string'("2") /= "") and
(string'("3") /= "") and
(string'("4") /= "") and
(string'("5") /= "") and
(string'("6") /= "") and
(string'("7") /= "") and
(string'("8") /= "") and
(string'("9") /= "") and
(string'(":") /= "") and
(string'(";") /= "") and
(string'("<") /= "") and
(string'("=") /= "") and
(string'(">") /= "") and
(string'("?") /= "") and
(string'("@") /= "") and
(string'("A") /= "") and
(string'("B") /= "") and
(string'("C") /= "") and
(string'("D") /= "") and
(string'("E") /= "") and
(string'("F") /= "") and
(string'("G") /= "") and
(string'("H") /= "") and
(string'("I") /= "") and
(string'("J") /= "") and
(string'("K") /= "") and
(string'("L") /= "") and
(string'("M") /= "") and
(string'("N") /= "") and
(string'("O") /= "") and
(string'("P") /= "") and
(string'("Q") /= "") and
(string'("R") /= "") and
(string'("S") /= "") and
(string'("T") /= "") and
(string'("U") /= "") and
(string'("V") /= "") and
(string'("W") /= "") and
(string'("X") /= "") and
(string'("Y") /= "") and
(string'("Z") /= "") and
(string'("[") /= "") and
(string'("\") /= "") and
(string'("]") /= "") and
(string'("^") /= "") and
(string'("_") /= "") and
(string'("`") /= "") and
(string'("a") /= "") and
(string'("b") /= "") and
(string'("c") /= "") and
(string'("d") /= "") and
(string'("e") /= "") and
(string'("f") /= "") and
(string'("g") /= "") and
(string'("h") /= "") and
(string'("i") /= "") and
(string'("j") /= "") and
(string'("k") /= "") and
(string'("l") /= "") and
(string'("m") /= "") and
(string'("n") /= "") and
(string'("o") /= "") and
(string'("p") /= "") and
(string'("q") /= "") and
(string'("r") /= "") and
(string'("s") /= "") and
(string'("t") /= "") and
(string'("u") /= "") and
(string'("v") /= "") and
(string'("w") /= "") and
(string'("x") /= "") and
(string'("y") /= "") and
(string'("z") /= "") and
(string'("{") /= "") and
(string'("|") /= "") and
(string'("}") /= "") and
(string'("~") /= "") and
-- this tests 13.6 (3)
(string'("A") /= "a") and
(string'("B") /= "b") and
(string'("C") /= "c") and
(string'("D") /= "d") and
(string'("E") /= "e") and
(string'("F") /= "f") and
(string'("G") /= "g") and
(string'("H") /= "h") and
(string'("I") /= "i") and
(string'("J") /= "j") and
(string'("K") /= "k") and
(string'("L") /= "l") and
(string'("M") /= "m") and
(string'("N") /= "n") and
(string'("O") /= "o") and
(string'("P") /= "p") and
(string'("Q") /= "q") and
(string'("R") /= "r") and
(string'("S") /= "s") and
(string'("T") /= "t") and
(string'("U") /= "u") and
(string'("V") /= "v") and
(string'("W") /= "w") and
(string'("X") /= "x") and
(string'("Y") /= "y") and
(string'("Z") /= "z")
) ;
wait ;
end process ;
end ARCH00430 ;
entity ENT00430_Test_Bench is
end ENT00430_Test_Bench ;
architecture ARCH00430_Test_Bench of ENT00430_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00430 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00430_Test_Bench ;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:52:03 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_util_vector_logic_1_0/system_util_vector_logic_1_0_stub.vhdl
-- Design : system_util_vector_logic_1_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_util_vector_logic_1_0 is
Port (
Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
Res : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_util_vector_logic_1_0;
architecture stub of system_util_vector_logic_1_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "Op1[0:0],Op2[0:0],Res[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "util_vector_logic,Vivado 2016.4";
begin
end;
|
-- $Id: rb_mon.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rb_mon - sim
-- Description: rbus monitor (for tb's)
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-22 346 3.0 renamed rritb_rbmon -> rb_mon
-- 2010-06-05 301 2.1.1 renamed _rpmon -> _rbmon
-- 2010-06-03 299 2.1 new init encoding (WE=0/1 int/ext)
-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2008-03-24 129 1.2.1 CLK_CYCLE now 31 bits
-- 2007-12-23 105 1.2 added AP_LAM display
-- 2007-11-24 98 1.1 added RP_IINT support
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.rblib.all;
entity rb_mon is -- rbus monitor (for tb's)
generic (
DBASE : positive := 2); -- base for writing data values
port (
CLK : in slbit; -- clock
CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end rb_mon;
architecture sim of rb_mon is
begin
proc_moni: process
variable oline : line;
variable nhold : integer := 0;
variable data : slv16 := (others=>'0');
variable tag : string(1 to 8) := (others=>' ');
variable err : slbit := '0';
procedure write_data(L: inout line;
tag: in string;
data: in slv16;
nhold: in integer := 0;
cond: in boolean := false;
ctxt: in string := " ") is
begin
writetimestamp(L, CLK_CYCLE, tag);
write(L, RB_MREQ.addr, right, 10);
write(L, string'(" "));
writegen(L, data, right, 0, DBASE);
write(L, RB_STAT, right, 4);
if nhold > 0 then
write(L, string'(" nhold="));
write(L, nhold);
end if;
if cond then
write(L, ctxt);
end if;
writeline(output, L);
end procedure write_data;
begin
loop
if ENA = '0' then -- if disabled
wait until ENA='1'; -- stall process till enabled
end if;
wait until rising_edge(CLK); -- check at end of clock cycle
if RB_MREQ.aval='1' and (RB_MREQ.re='1' or RB_MREQ.we='1') then
if RB_SRES.err = '1' then
err := '1';
end if;
if RB_SRES.busy = '1' then
nhold := nhold + 1;
else
data := (others=>'0');
tag := ": ???? ";
if RB_MREQ.re = '1' then
data := RB_SRES.dout;
tag := ": rbre ";
end if;
if RB_MREQ.we = '1' then
data := RB_MREQ.din;
tag := ": rbwe ";
end if;
write_data(oline, tag, data, nhold, err='1', " ERR='1'");
nhold := 0;
end if;
else
if nhold > 0 then
write_data(oline, tag, data, nhold, true, " TIMEOUT");
end if;
nhold := 0;
err := '0';
end if;
if RB_MREQ.init = '1' then -- init
if RB_MREQ.we = '1' then
write_data(oline, ": rbini ", RB_MREQ.din); -- external
else
write_data(oline, ": rbint ", RB_MREQ.din); -- internal
end if;
end if;
if unsigned(RB_LAM) /= 0 then
write_data(oline, ": rblam ", RB_LAM, 0, true, " RB_LAM active");
end if;
end loop;
end process proc_moni;
end sim;
|
entity proc1 is
end;
use work.pkg.all;
architecture behav of proc1 is
procedure proc (v : inout rec) is
begin
v.a := 5;
assert v.a = 5 severity failure;
v.s := "Good";
assert v.a = 5 severity failure;
assert v.s = "Good" severity failure;
assert false report "ok" severity note;
end proc;
begin
process
variable v : rec_4;
begin
proc (v);
wait;
end process;
end behav;
|
entity proc1 is
end;
use work.pkg.all;
architecture behav of proc1 is
procedure proc (v : inout rec) is
begin
v.a := 5;
assert v.a = 5 severity failure;
v.s := "Good";
assert v.a = 5 severity failure;
assert v.s = "Good" severity failure;
assert false report "ok" severity note;
end proc;
begin
process
variable v : rec_4;
begin
proc (v);
wait;
end process;
end behav;
|
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