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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1124.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p04n01i01124ent IS
END c06s05b00x00p04n01i01124ent;
ARCHITECTURE c06s05b00x00p04n01i01124arch OF c06s05b00x00p04n01i01124ent IS
BEGIN
TESTING: PROCESS
type BIT_VECTOR is array (positive range <>) of BIT;
variable NUM1 : BIT_VECTOR(1 to 10) := B"01_01_01_01_01";
BEGIN
NUM1(7 to 12) := B"010_010";
assert FALSE
report "***FAILED TEST: c06s05b00x00p04n01i01124 - Bounds of the slice cannot exceed those defined by the discrete range."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p04n01i01124arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1124.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p04n01i01124ent IS
END c06s05b00x00p04n01i01124ent;
ARCHITECTURE c06s05b00x00p04n01i01124arch OF c06s05b00x00p04n01i01124ent IS
BEGIN
TESTING: PROCESS
type BIT_VECTOR is array (positive range <>) of BIT;
variable NUM1 : BIT_VECTOR(1 to 10) := B"01_01_01_01_01";
BEGIN
NUM1(7 to 12) := B"010_010";
assert FALSE
report "***FAILED TEST: c06s05b00x00p04n01i01124 - Bounds of the slice cannot exceed those defined by the discrete range."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p04n01i01124arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1124.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p04n01i01124ent IS
END c06s05b00x00p04n01i01124ent;
ARCHITECTURE c06s05b00x00p04n01i01124arch OF c06s05b00x00p04n01i01124ent IS
BEGIN
TESTING: PROCESS
type BIT_VECTOR is array (positive range <>) of BIT;
variable NUM1 : BIT_VECTOR(1 to 10) := B"01_01_01_01_01";
BEGIN
NUM1(7 to 12) := B"010_010";
assert FALSE
report "***FAILED TEST: c06s05b00x00p04n01i01124 - Bounds of the slice cannot exceed those defined by the discrete range."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p04n01i01124arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FlipFlopD_Demo is
port( SW : in std_logic_vector(2 downto 0);
KEY: in std_logic_vector(0 downto 0);
LEDR: out std_logic_vector(0 downto 0));
end FlipFlopD_Demo;
architecture Shell of FlipFlopD_Demo is
begin
ff_d: entity work.FlipFlopD(Behavioral2)
port map(clk => KEY(0),
d => SW(0),
set => SW(1),
reset => SW(2),
q => LEDR(0));
end Shell; |
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 18.11.2013 10:02:58
-- Design Name:
-- Module Name: switch_input_port_fifo - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- FIFO interface between MAC and switch port on the receive path
-- for decoupling clocks and data widths
-- bandwidth on user interface (read) must be higher than mac interface (write)
-- width = error_width + last_width + data_width
-- depth = 16 entries
-- see switch_mac_rxfifo.svg for further information
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity switch_input_port_fifo is
generic (
GMII_DATA_WIDTH : integer;
RECEIVER_DATA_WIDTH : integer
);
port (
-- User-side interface (read)
rx_fifo_out_clk : in std_logic;
rx_fifo_out_reset : in std_logic;
rx_fifo_out_data : out std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
rx_fifo_out_valid : out std_logic;
rx_fifo_out_last : out std_logic;
rx_fifo_out_error : out std_logic;
-- MAC-side interface (write)
rx_fifo_in_clk : in std_logic;
rx_fifo_in_reset : in std_logic;
rx_fifo_in_data : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
rx_fifo_in_valid : in std_logic;
rx_fifo_in_last : in std_logic;
rx_fifo_in_error : in std_logic
);
end switch_input_port_fifo;
architecture rtl of switch_input_port_fifo is
component fifo_generator_0 is
PORT (
wr_clk : IN std_logic := '0';
rd_clk : IN std_logic := '0';
valid : OUT std_logic := '0';
wr_rst : IN std_logic := '0';
rd_rst : IN std_logic := '0';
wr_en : IN std_logic := '0';
rd_en : IN std_logic := '0';
din : IN std_logic_vector(GMII_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
dout : OUT std_logic_vector(RECEIVER_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
full : OUT std_logic := '0';
empty : OUT std_logic := '1'
);
end component;
signal din_sig : std_logic_vector(GMII_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
signal dout_sig : std_logic_vector(GMII_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
signal empty_sig : std_logic := '0';
signal rd_en_sig : std_logic := '0';
begin
-- FIFO input ports
din_sig <= rx_fifo_in_error & rx_fifo_in_last & rx_fifo_in_data;
rd_en_sig <= not empty_sig;
-- module output ports
rx_fifo_out_error <= dout_sig(RECEIVER_DATA_WIDTH+2-1);
rx_fifo_out_last <= dout_sig(RECEIVER_DATA_WIDTH+1-1);
rx_fifo_out_data <= dout_sig(RECEIVER_DATA_WIDTH-1 downto 0);
-- connecting the FIFO inputs and outputs
rx_fifo_ip : fifo_generator_0
PORT MAP (
wr_clk => rx_fifo_in_clk,
wr_rst => rx_fifo_in_reset,
wr_en => rx_fifo_in_valid,
din => din_sig,
full => open,
rd_clk => rx_fifo_out_clk,
rd_rst => rx_fifo_out_reset,
valid => rx_fifo_out_valid,
rd_en => rd_en_sig,
dout => dout_sig,
empty => empty_sig
);
end rtl;
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 18.11.2013 10:02:58
-- Design Name:
-- Module Name: switch_input_port_fifo - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- FIFO interface between MAC and switch port on the receive path
-- for decoupling clocks and data widths
-- bandwidth on user interface (read) must be higher than mac interface (write)
-- width = error_width + last_width + data_width
-- depth = 16 entries
-- see switch_mac_rxfifo.svg for further information
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity switch_input_port_fifo is
generic (
GMII_DATA_WIDTH : integer;
RECEIVER_DATA_WIDTH : integer
);
port (
-- User-side interface (read)
rx_fifo_out_clk : in std_logic;
rx_fifo_out_reset : in std_logic;
rx_fifo_out_data : out std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
rx_fifo_out_valid : out std_logic;
rx_fifo_out_last : out std_logic;
rx_fifo_out_error : out std_logic;
-- MAC-side interface (write)
rx_fifo_in_clk : in std_logic;
rx_fifo_in_reset : in std_logic;
rx_fifo_in_data : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
rx_fifo_in_valid : in std_logic;
rx_fifo_in_last : in std_logic;
rx_fifo_in_error : in std_logic
);
end switch_input_port_fifo;
architecture rtl of switch_input_port_fifo is
component fifo_generator_0 is
PORT (
wr_clk : IN std_logic := '0';
rd_clk : IN std_logic := '0';
valid : OUT std_logic := '0';
wr_rst : IN std_logic := '0';
rd_rst : IN std_logic := '0';
wr_en : IN std_logic := '0';
rd_en : IN std_logic := '0';
din : IN std_logic_vector(GMII_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
dout : OUT std_logic_vector(RECEIVER_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
full : OUT std_logic := '0';
empty : OUT std_logic := '1'
);
end component;
signal din_sig : std_logic_vector(GMII_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
signal dout_sig : std_logic_vector(GMII_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
signal empty_sig : std_logic := '0';
signal rd_en_sig : std_logic := '0';
begin
-- FIFO input ports
din_sig <= rx_fifo_in_error & rx_fifo_in_last & rx_fifo_in_data;
rd_en_sig <= not empty_sig;
-- module output ports
rx_fifo_out_error <= dout_sig(RECEIVER_DATA_WIDTH+2-1);
rx_fifo_out_last <= dout_sig(RECEIVER_DATA_WIDTH+1-1);
rx_fifo_out_data <= dout_sig(RECEIVER_DATA_WIDTH-1 downto 0);
-- connecting the FIFO inputs and outputs
rx_fifo_ip : fifo_generator_0
PORT MAP (
wr_clk => rx_fifo_in_clk,
wr_rst => rx_fifo_in_reset,
wr_en => rx_fifo_in_valid,
din => din_sig,
full => open,
rd_clk => rx_fifo_out_clk,
rd_rst => rx_fifo_out_reset,
valid => rx_fifo_out_valid,
rd_en => rd_en_sig,
dout => dout_sig,
empty => empty_sig
);
end rtl;
|
--
-- This file is part of top_optim_sharp_driver
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_optim_sharp_driver is
Port ( clk : in STD_LOGIC;
w1a : inout STD_LOGIC_VECTOR (15 downto 0);
w1b : inout STD_LOGIC_VECTOR (15 downto 0));
end top_optim_sharp_driver;
architecture Behavioral of top_optim_sharp_driver is
signal vsync : std_logic;
signal hsync : std_logic;
signal enable : std_logic;
-- Signals to communicate with block giving color
signal x_out : std_logic_vector ( 9 downto 0);
signal y_out : std_logic_vector ( 8 downto 0);
signal reset : std_logic;
begin
--Number of Slices : 71
--Number of Slice Flip Flops: 61
--Number of 4 input LUTs: 128
--Number of bonded IOBs: 23
--Clock : 92.524Mhz
--inst_optim_screen_driver : entity work.driver_sharp(v1_0)
--Number of Slices: 52
--Number of Slice Flip Flops: 48
--Number of 4 input LUTs: 97
--Number of bonded IOBs: 23
-- Clock : 181.455Mhz
--inst_optim_screen_driver : entity work.driver_sharp(v1_1)
--Number of Slices: 16
--Number of Slice Flip Flops: 27
--Number of 4 input LUTs: 29
--Number of bonded IOBs: 23
-- Clock 224.517 Mhz
--inst_optim_screen_driver : entity work.driver_sharp(v1_2)
--Number of Slices: 38
--Number of Slice Flip Flops: 69
--Number of 4 input LUTs: 49
--Number of bonded IOBs: 23
-- Clock : 221.141Mhz
inst_optim_screen_driver : entity work.driver_sharp(v1_3)
port map(
clk => clk,
rst => reset,
vsync => vsync,
hsync => hsync,
enable => enable,
x_out => x_out,
y_out => y_out);
w1a(0) <= vsync;
w1a(1) <= hsync;
w1a(2) <= enable;
w1a(12 downto 3) <= x_out(9 downto 0);
w1b(8 downto 0) <= y_out(8 downto 0);
reset <= '0';
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity g_ethtx_output is
generic(
HEAD_AWIDTH : natural := 5;
BUFF_AWIDTH : natural := 16;
RAM_AWIDTH : natural := 32
);
port(
clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(7 downto 0);
txen : out std_logic;
tx_queue_empty : in std_logic;
tx_head_raddr : out std_logic_vector(HEAD_AWIDTH - 1 downto 0);
tx_head_rdata : in std_logic_vector(7 downto 0);
tx_head_rd_block : out std_logic;
db_queue_empty : in std_logic;
db_head_raddr : out std_logic_vector(HEAD_AWIDTH - 1 downto 0);
db_head_rdata : in std_logic_vector(7 downto 0);
db_head_rd_block : out std_logic;
buff_raddr : out std_logic_vector(BUFF_AWIDTH - 1 downto 0);
buff_rdata : in std_logic_vector(31 downto 0);
dma_start : out std_logic;
dma_start_addr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
dma_length : out std_logic_vector(15 downto 0);
dma_step : out std_logic_vector(7 downto 0);
localtime : in std_logic_vector(31 downto 0)
);
end g_ethtx_output;
architecture arch_ethtx_output of g_ethtx_output is
component crc8_blkrom
port(
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(31 downto 0));
end component;
component fifo_async_almost_full
generic(
DEPTH : NATURAL;
AWIDTH : NATURAL;
DWIDTH : NATURAL;
RAM_TYPE : STRING);
port(
reset : in std_logic;
clr : in std_logic;
clka : in std_logic;
wea : in std_logic;
dia : in std_logic_vector((DWIDTH-1) downto 0);
clkb : in std_logic;
rdb : in std_logic;
dob : out std_logic_vector((DWIDTH-1) downto 0);
empty : out std_logic;
almost_full : out std_logic;
full : out std_logic;
dn : out std_logic_vector((AWIDTH-1) downto 0));
end component;
for all: fifo_async_almost_full use entity WORK.fifo_async_almost_full(fast_write);
component shiftreg
generic(
width : INTEGER;
depth : INTEGER);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector((width-1) downto 0);
Q : out std_logic_vector((width-1) downto 0);
S : out std_logic_vector((width-1) downto 0));
end component;
component ASYNCWRITE
port(
reset: in std_logic;
async_clk: in std_logic;
sync_clk: in std_logic;
async_wren: in std_logic;
trigger: in std_logic;
sync_wren: out std_logic;
over: out std_logic;
flag: out std_logic
);
end component;
constant INFO_LENGTH : natural := 8;
signal ce : std_logic;
signal ce_d1 : std_logic;
signal ce_ext : std_logic;
signal ce_ext_d1 : std_logic;
signal ce_ext_d2 : std_logic;
signal txd_buf : std_logic_vector(7 downto 0);
signal txen_buf : std_logic;
signal txd_buf_d1 : std_logic_vector(7 downto 0);
signal txen_buf_d1 : std_logic;
signal TxFIFO_clr : std_logic;
signal TxFIFO_wea : std_logic;
signal TxFIFO_dia : std_logic_vector(31 downto 0);
signal TxFIFO_rdb : std_logic;
signal TxFIFO_rdb_d1 : std_logic;
signal TxFIFO_dob : std_logic_vector(31 downto 0);
signal TxFIFO_almost_full : std_logic;
signal TxFIFO_empty : std_logic;
signal TxFIFO_DN : std_logic_vector(3 downto 0);
signal busy : std_logic;
signal byte_cnt : std_logic_vector(11 downto 0);
signal byte_cnt_d1 : std_logic_vector(11 downto 0);
signal byte_cnt_ext : std_logic_vector(11 downto 0);
signal byte_cnt_ext_d1 : std_logic_vector(11 downto 0);
signal byte_cnt_ext_d2 : std_logic_vector(11 downto 0);
signal head_length : std_logic_vector(7 downto 0);
signal data_length : std_logic_vector(10 downto 0);
signal source_select : std_logic;
signal head_rd_block : std_logic;
signal info_ena : std_logic;
signal info_ena_d1 : std_logic;
signal info_cnt : integer range 0 to INFO_LENGTH;
signal info_cnt_d1 : integer range 0 to INFO_LENGTH;
signal data_ena : std_logic;
signal data_ena_d8 : std_logic;
signal data_ena_ext : std_logic;
signal data_ena_ext_d1 : std_logic;
signal data_ena_ext_d2 : std_logic;
signal data_ena_ext_d6 : std_logic;
signal data_ena_ext_d8 : std_logic;
signal data_ena_ext_d12 : std_logic;
signal data_ena_ext_d13 : std_logic;
signal head_ena : std_logic;
signal head_ena_d1 : std_logic;
signal buff_ena : std_logic;
signal buff_ena_d1 : std_logic;
signal info_start : std_logic;
signal data_start : std_logic;
signal data_start_ext : std_logic;
signal data_start_ext_wren : std_logic;
signal dword_data_int : std_logic_vector(31 downto 0);
signal dword_data_ext : std_logic_vector(31 downto 0);
signal byte_data : std_logic_vector(7 downto 0);
signal byte_data_buf : std_logic_vector(31 downto 0);
signal byte_data_dly : std_logic_vector(7 downto 0);
signal head_rden : std_logic;
signal head_rdata : std_logic_vector(7 downto 0);
signal head_rdata_buf : std_logic_vector(23 downto 0);
signal head_raddr_buf : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal buff_rden : std_logic;
signal buff_rden_d1 : std_logic;
signal buff_raddr_buf : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal buff_rdata_buf : std_logic_vector(31 downto 0);
signal crc_din : std_logic_vector(7 downto 0);
signal crc_reg : std_logic_vector(31 downto 0);
signal crc_reg_d1 : std_logic_vector(31 downto 0);
signal crcrom_addr : std_logic_vector(7 downto 0);
signal crcrom_dout : std_logic_vector(31 downto 0);
signal v0 : std_logic_vector(0 downto 0);
signal v1 : std_logic_vector(0 downto 0);
signal v2 : std_logic_vector(0 downto 0);
signal v3 : std_logic_vector(0 downto 0);
signal localtime_reg : std_logic_vector(31 downto 0);
signal crc_reg_dly : std_logic_vector(7 downto 0);
signal IFG_cnt : std_logic_vector(4 downto 0);
signal IFG_busy : std_logic;
signal m4_TxFIFO_DN : std_logic_vector( 3 downto 0 );
signal s_N_Empty : std_logic;
signal s_N_Empty_TxClk : std_logic;
signal s_N_Empty_TxClk_D1 : std_logic;
begin
p_info_start : process(clk, reset)
begin
if reset = '1' then
info_start <= '0';
source_select <= '0';
ce_d1 <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if busy = '0' then
if tx_queue_empty = '0' then
info_start <= '1';
source_select <= '0';
elsif db_queue_empty = '0' then
info_start <= '1';
source_select <= '1';
end if;
else
info_start <= '0';
end if;
end if;
ce_d1 <= ce;
end if;
end process;
busy <= info_start or info_ena or data_start or data_ena or data_ena_d8 or data_ena_ext or data_ena_ext_d13 or IFG_busy;
p_info_cnt : process(clk, reset)
begin
if reset = '1' then
info_ena <= '0';
info_cnt <= 0;
info_ena_d1 <= '0';
info_cnt_d1 <= 0;
elsif rising_edge(clk) then
if ce = '1' then
if info_start = '1' then
info_ena <= '1';
elsif info_cnt = INFO_LENGTH - 1 then
info_ena <= '0';
end if;
if info_ena = '0' then
info_cnt <= 0;
else
info_cnt <= info_cnt + 1;
end if;
end if;
info_ena_d1 <= info_ena;
info_cnt_d1 <= info_cnt;
end if;
end process;
------------------------------------------------------------------------------
data_start <= '1' when info_cnt = INFO_LENGTH else '0';
p_byte_cnt : process(clk, reset)
begin
if reset = '1' then
data_ena <= '0';
byte_cnt <= (others => '0');
byte_cnt_d1 <= (others=>'0');
head_ena_d1 <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if data_start = '1' then
data_ena <= '1';
elsif buff_ena = '0' and byte_cnt >= data_length-1 then
data_ena <= '0';
elsif buff_ena = '1' and byte_cnt >= data_length - 4 then
data_ena <= '0';
end if;
if data_start = '1' then
byte_cnt <= (others => '0');
elsif head_ena = '1' then
byte_cnt <= byte_cnt + 1;
elsif buff_ena = '1' then
byte_cnt <= byte_cnt + 4;
end if;
end if;
byte_cnt_d1 <= byte_cnt;
head_ena_d1 <= head_ena;
end if;
end process;
head_ena <= '1' when data_ena = '1' and byte_cnt < head_length else '0';
buff_ena <= '1' when data_ena = '1' and byte_cnt >= head_length else '0';
------------------------------------------------------------------------------
head_rden <= (info_ena or head_ena) and ce;
p_head_raddr : process(clk, reset)
begin
if reset = '1' then
head_raddr_buf <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if info_start = '1' then
head_raddr_buf <= (others => '0');
elsif head_rden = '1' then
head_raddr_buf <= head_raddr_buf + 1;
end if;
end if;
end if;
end process;
tx_head_raddr <= head_raddr_buf;
db_head_raddr <= head_raddr_buf;
head_rdata <= tx_head_rdata when source_select = '0' else db_head_rdata;
head_rd_block <= '1' when byte_cnt = head_length else '0';
tx_head_rd_block <= head_rd_block and ce and (not source_select);
db_head_rd_block <= head_rd_block and ce and source_select;
p_get_info : process(clk, reset)
begin
if reset = '1' then
head_length <= (others => '0');
data_length <= (others => '0');
dma_start_addr <= (others => '0');
dma_step <= (others => '0');
elsif rising_edge(clk) then
if ce_d1 = '1' then
if info_ena_d1 = '1' then
case info_cnt_d1 is
when 0 =>
head_length(7 downto 0) <= head_rdata;
when 1 =>
data_length(7 downto 0) <= head_rdata;
when 2 =>
data_length(10 downto 8) <= head_rdata(2 downto 0);
when 3 =>
dma_start_addr(7 downto 0) <= head_rdata;
when 4 =>
dma_start_addr(15 downto 8) <= head_rdata;
when 5 =>
dma_start_addr(23 downto 16) <= head_rdata;
when 6 =>
dma_start_addr(31 downto 24) <= head_rdata;
when 7 =>
dma_step <= head_rdata;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
dma_start <= '1' when info_cnt_d1 = INFO_LENGTH and ce_d1 = '1' and data_length /= head_length else '0';
dma_length <= EXT(data_length, 16) - EXT(head_length, 16);
-----------------------------------------------------------------------------
p_get_head : process(clk, reset)
begin
if reset = '1' then
head_rdata_buf <= (others=>'0');
elsif rising_edge(clk) then
if ce_d1 = '1' then
if head_ena_d1 = '1' then
if byte_cnt_d1(1 downto 0) = "00" then
head_rdata_buf <= head_rdata & X"0000";
else
head_rdata_buf <= head_rdata & head_rdata_buf(23 downto 8);
end if;
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
buff_rden <= buff_ena and ce;
p_buff_raddr : process(clk, reset)
begin
if reset = '1' then
buff_raddr_buf <= (others => '0');
buff_rdata_buf <= (others=>'0');
buff_ena_d1 <= '0';
buff_rden_d1 <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if data_start = '1' then
buff_raddr_buf <= (others => '0');
elsif buff_rden = '1' then
buff_raddr_buf <= buff_raddr_buf + 1;
end if;
buff_rdata_buf <= buff_rdata;
end if;
buff_ena_d1 <= buff_ena;
buff_rden_d1 <= buff_rden;
end if;
end process;
buff_raddr <= buff_raddr_buf;
------------------------------------------------------------------------------
dword_data_int <= buff_rdata_buf when buff_ena_d1 = '1' else
head_rdata & head_rdata_buf when head_ena_d1 = '1' else
(others=>'0');
ce <= not TxFIFO_almost_full;
TxFIFO_clr <= '1' when data_start = '1' else '0';
TxFIFO_wea <= '1' when (head_ena_d1 = '1' and byte_cnt_d1(1 downto 0) = "11") or buff_rden_d1 = '1' else '0';
TxFIFO_dia <= dword_data_int;
u_txclk_sync : fifo_async_almost_full
generic map(
depth => 16,
awidth => 4,
dwidth => 32,
ram_type => "DIS_RAM"
)
port map(
reset => reset,
clr => TxFIFO_clr,
clka => clk,
wea => TxFIFO_wea,
dia => TxFIFO_dia,
clkb => txclk,
rdb => TxFIFO_rdb,
dob => TxFIFO_dob,
empty => TxFIFO_empty,
almost_full => TxFIFO_almost_full,
full => open,
dn => TxFIFO_DN
);
dword_data_ext <= TxFIFO_dob;
TxFIFO_rdb <= data_ena_ext and ce_ext when byte_cnt_ext(1 downto 0) = "00" else '0';
-------------------------------------------------------------------------------------------------------
data_start_ext_wren <= (not head_ena) and head_ena_d1;
ASYNCWRITE_data_start_ext : ASYNCWRITE
port map(
reset => reset,
async_clk => clk,
sync_clk => txclk,
async_wren => data_start_ext_wren,
trigger => '1',
sync_wren => data_start_ext,
over => open,
flag => open
);
ce_ext <= '1';
p_byte_cnt_ext : process(txclk, reset)
begin
if reset = '1' then
ce_ext_d1 <= '0';
ce_ext_d2 <= '0';
data_ena_ext <= '0';
data_ena_ext_d1 <= '0';
data_ena_ext_d2 <= '0';
byte_cnt_ext <= (others => '0');
byte_cnt_ext_d1 <= (others=>'0');
byte_cnt_ext_d2 <= (others=>'0');
TxFIFO_rdb_d1 <= '0';
elsif rising_edge(txclk) then
if ce_ext = '1' then
if data_start_ext = '1' then
data_ena_ext <= '1';
elsif byte_cnt_ext = data_length - 1 then
data_ena_ext <= '0';
end if;
if data_start_ext = '1' then
byte_cnt_ext <= (others => '0');
else
byte_cnt_ext <= byte_cnt_ext + 1;
end if;
end if;
ce_ext_d1 <= ce_ext;
ce_ext_d2 <= ce_ext_d1;
data_ena_ext_d1 <= data_ena_ext;
data_ena_ext_d2 <= data_ena_ext_d1;
byte_cnt_ext_d1 <= byte_cnt_ext;
byte_cnt_ext_d2 <= byte_cnt_ext_d1;
TxFIFO_rdb_d1 <= TxFIFO_rdb;
end if;
end process;
p_byte_data_buf : process(txclk, reset)
begin
if reset = '1' then
byte_data_buf <= (others => '0');
elsif rising_edge(txclk) then
if ce_ext_d1 = '1' then
if TxFIFO_rdb_d1 = '1' then
byte_data_buf <= TxFIFO_dob;
else
byte_data_buf <= X"00" & byte_data_buf(31 downto 8);
end if;
end if;
end if;
end process;
p_localtime : process(reset, txclk)
begin
if reset = '1' then
localtime_reg <= (others => '0');
elsif rising_edge(txclk) then
if byte_cnt_ext = 7 then
localtime_reg <= localtime;
end if;
end if;
end process;
byte_data <= localtime_reg(31 downto 24) when byte_cnt_ext_d1 = 14 and source_select = '0' else
localtime_reg(23 downto 16) when byte_cnt_ext_d1 = 15 and source_select = '0' else
localtime_reg(15 downto 8) when byte_cnt_ext_d1 = 16 and source_select = '0' else
localtime_reg(7 downto 0) when byte_cnt_ext_d1 = 17 and source_select = '0' else
TxFIFO_dob(7 downto 0) when byte_cnt_ext_d1(1 downto 0) = "00" else
byte_data_buf(15 downto 8);
u_crc_rom : CRC8_BlkRom
port map(
clk => txclk,
addr => crcrom_addr,
dout => crcrom_dout
);
crcrom_addr <= crc_reg(31 downto 24);
crc_din <= (others => '0') when data_ena_ext_d1 = '0' else
not (byte_data(0) & byte_data(1) & byte_data(2) & byte_data(3) & byte_data(4) & byte_data(5) & byte_data(6) & byte_data(7)) when byte_cnt_ext_d1 < 4 else
byte_data(0) & byte_data(1) & byte_data(2) & byte_data(3) & byte_data(4) & byte_data(5) & byte_data(6) & byte_data(7);
crc_reg <= (others=>'0') when data_start_ext = '1' and ce_ext = '1' else
crc_reg_d1 xor crcrom_dout when (data_ena_ext_d2 = '1' or data_ena_ext_d6 = '1') and ce_ext_d2 = '1' else
crc_reg_d1;
p_calc_crc : process(txclk, reset)
begin
if reset = '1' then
crc_reg_d1 <= (others => '0');
elsif rising_edge(txclk) then
if ce_ext_d1 = '1' then
if data_start_ext = '1' then
crc_reg_d1 <= (others => '0');
else
crc_reg_d1 <= (crc_reg(23 downto 0) & crc_din);
end if;
else
crc_reg_d1 <= crc_reg(23 downto 0) & crc_din;
end if;
end if;
end process;
------------------------------------------------------------------------------
u_nibble_data_dly : ShiftReg
generic map(
WIDTH => 8,
DEPTH => 7
)
port map(
clk => txclk,
ce => '1',
D => byte_data,
Q => byte_data_dly,
S => open
);
u_crc_reg_dly : ShiftReg
generic map(
WIDTH => 8,
DEPTH => 3
)
port map(
clk => txclk,
ce => '1',
D => crc_reg(31 downto 24),
Q => crc_reg_dly(7 downto 0),
S => open
);
u_data_ena_d0 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 8
)
port map(
clk => clk,
ce => '1',
D(0) => data_ena,
Q(0) => data_ena_d8,
S => open
);
u_data_ena_d1 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 4
)
port map(
clk => txclk,
ce => '1',
D => v0,
Q => v1,
S => open
);
u_data_ena_d2 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 2
)
port map(
clk => txclk,
ce => '1',
D => v1,
Q => v2,
S => open
);
u_data_ena_d3 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 4
)
port map(
clk => txclk,
ce => '1',
D => v2,
Q => v3,
S => open
);
v0(0) <= data_ena_ext_d2;
data_ena_ext_d6 <= v1(0);
data_ena_ext_d8 <= v2(0);
data_ena_ext_d12 <= v3(0);
txd_buf <= "01010101" when data_ena_ext = '1' and byte_cnt_ext < 7 else
"11010101" when data_ena_ext = '1' and byte_cnt_ext = 7 else
--
byte_data_dly when data_ena_ext_d8 = '1' else
not(crc_reg_dly(0) & crc_reg_dly(1) & crc_reg_dly(2) & crc_reg_dly(3) & crc_reg_dly(4) & crc_reg_dly(5) & crc_reg_dly(6) & crc_reg_dly(7));
txen_buf <= data_ena_ext or data_ena_ext_d12;
------------------------------------------------------------------------------
p_mii_dout : process(reset, txclk)
begin
if ( reset = '1' ) then
txen <= '0';
txd <= ( others => '0' );
elsif rising_edge(txclk) then
txen <= txen_buf;
txd <= txd_buf;
end if;
end process;
p_ifg_count : process(txclk, reset)
begin
if reset = '1' then
IFG_cnt <= "00000";
data_ena_ext_d13 <= '0';
elsif rising_edge(txclk) then
data_ena_ext_d13 <= data_ena_ext_d12;
if IFG_busy = '1' then
IFG_cnt <= IFG_cnt + '1';
else
IFG_cnt <= "00000";
end if;
end if;
end process;
p_ifg_busy_flag : process(txclk, reset)
begin
if reset = '1' then
IFG_busy <= '0';
elsif rising_edge(txclk) then
if data_ena_ext_d12 = '0' and data_ena_ext_d13 = '1' then
IFG_busy <= '1';
elsif IFG_cnt = "11111" then
IFG_busy <= '0';
end if;
end if;
end process;
end arch_ethtx_output;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(24,24);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(4 DOWNTO 0) <= WRITE_ADDR(4 DOWNTO 0);
READ_ADDR_INT(4 DOWNTO 0) <= READ_ADDR(4 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 24
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 24 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 24,
DOUT_WIDTH => 24,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
|
------------------------------------------------------------------------------------------------
-- VGAtonic Color Bar Test --
-- --
-- This code demonstrates VGA and NTSC from the same source clock, a 3.5795454 MHz --
-- colorburst signal for NTSC. Using a PLL, we multiply that source by 7 to get 25.0568 --
-- MHz - a 0.47% error from the VGA standard 25.175 MHz clock (Doing it in the reverse --
-- direction - dividing 25.175 MHz by 7 - gives a rainbow pattern for a single phase... --
-- no good) --
-- --
-- License: MIT (see root directory). --
------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity video is
Port ( CLK : in STD_LOGIC;
-- Output to PLL
CLK_OUT : out STD_LOGIC;
-- Input from a switch (go between NTSC/VGA)
MODE : in STD_LOGIC;
-- VGA Signals
PIXEL : out unsigned(7 downto 0) := "00000000";
HSYNC : out STD_LOGIC;
VSYNC : out STD_LOGIC;
-- NTSC Signals
COLORBURST : out std_logic := '0';
SYNC : out std_logic := '1';
LUMA : out unsigned(3 downto 0) := "0000";
CLK_COUNTER : inout unsigned(10 downto 0) := (others => '0');
ROW_COUNTER : inout unsigned(9 downto 0) := (others => '0')
);
end video;
architecture Behavioral of video is
-- This ring counter pulls double duty.
-- First, it divides our PLL output by 7 for the feedback (to get 25 and change MHz out of 3.5795454
-- - division here becomes multiplication)
-- Second, we have 14 phases of 3.5795454 at the same time - all the positions in the ring counter,
-- and all the 'nots'.
signal PHASE_SHIFTER : unsigned(6 downto 0) := "1111111";
begin
-- For this PLL, position (4) worked best achieving lock - you should experiment
CLK_OUT <= not PHASE_SHIFTER(4);
process (CLK, PHASE_SHIFTER, MODE)
begin
-- Got a ring counter to divide our clock into two for ~ 3.5795454 MHz colorbursts
-- Note that 'EVENT means a double edged flip flop is necessary.
if (CLK'EVENT) then
PHASE_SHIFTER <= unsigned(PHASE_SHIFTER (5 downto 0)) & not PHASE_SHIFTER(6);
end if;
-- Video generation code.
if (rising_edge(CLK)) then
if (MODE = '1') then -- NTSC Mode = '1'. Technically, NTSC-J, fine - but show me a recent TV that cares.
-- Zero out VGA signal while driving NTSC
PIXEL <= "00000000";
HSYNC <= '0';
VSYNC <= '0';
if ( (ROW_COUNTER = "0000000100") or (ROW_COUNTER = "0000000101") or (ROW_COUNTER = "0000000110")) then
-- Sync is reversed on a VSYNC line
if (CLK_COUNTER = "11000110111") then
CLK_COUNTER <= "00000000000";
-- Add another line to row counter
ROW_COUNTER <= row_counter + 1;
-- Kick off our line
SYNC <= '0';
COLORBURST <= '0';
else
CLK_COUNTER <= CLK_COUNTER + 1;
COLORBURST <= '0';
end if;
-- Front porch 0 - 38 cycles
if (clk_counter = 38) then
SYNC <= '1';
COLORBURST <= '0';
end if;
-- Sync end after 155 cycles
if (clk_counter = 156) then
SYNC <= '0';
COLORBURST <= '0';
end if;
else -- Normal, non-VSync lines with a normal reverse sync
if (clk_counter = "11000110111") then
clk_counter <= "00000000000";
if (row_counter = "0100000110") then
row_counter <= "0000000000";
else
-- Add another line to row counter
row_counter <= row_counter + 1;
end if;
-- Kick off our line
SYNC <= '1';
LUMA <= "0000";
COLORBURST <= '0';
else
clk_counter <= clk_counter + 1;
end if;
-- Front porch 0 - 38
if (clk_counter = 38) then
SYNC <= '0';
end if;
-- Sync end after 155
if (clk_counter = 156) then
SYNC <= '1';
end if;
-- After 273, real picture drawing can begin
-- Can only draw picture with row counter above 19
if (row_counter > 19) then
--Color burst - 182 to 245
if (CLK_COUNTER >= 182 and CLK_COUNTER < 245) then
COLORBURST <= PHASE_SHIFTER(0);
elsif (clk_counter >= 244 and CLK_COUNTER < 273) then
-- Voltage Ramp ?
LUMA <= "0000";
COLORBURST <= '0';
end if;
if (CLK_COUNTER >= 300 and CLK_COUNTER < 1590) then
-- Luma is the brightness of the color being sent to the screen.
-- On one of my screens (camera reverse monitor), I could see all
-- 16 steps - but the TVs didn't show the difference in the LSBs.
LUMA <= ROW_COUNTER(6 downto 3);
-- All I'm doing here is assigning colors randomly to these 4 digits of the
-- clock counter. This is your chrominance.
CASE CLK_COUNTER(9 downto 6) IS
WHEN "0000" => COLORBURST <= PHASE_SHIFTER(0);
WHEN "0001" => COLORBURST <= PHASE_SHIFTER(1);
WHEN "0010" => COLORBURST <= PHASE_SHIFTER(2);
WHEN "0011" => COLORBURST <= PHASE_SHIFTER(3);
WHEN "0100" => COLORBURST <= PHASE_SHIFTER(4);
WHEN "0101" => COLORBURST <= PHASE_SHIFTER(5);
WHEN "0110" => COLORBURST <= PHASE_SHIFTER(6);
WHEN "0111" => COLORBURST <= not PHASE_SHIFTER(0);
WHEN "1000" => COLORBURST <= not PHASE_SHIFTER(1);
WHEN "1001" => COLORBURST <= not PHASE_SHIFTER(2);
WHEN "1010" => COLORBURST <= not PHASE_SHIFTER(3);
WHEN "1011" => COLORBURST <= not PHASE_SHIFTER(4);
WHEN "1100" => COLORBURST <= not PHASE_SHIFTER(5);
WHEN "1101" => COLORBURST <= not PHASE_SHIFTER(6);
WHEN OTHERS => COLORBURST <= '0';
END CASE;
elsif clk_counter > 1590 then
LUMA <= "0000";
COLORBURST <= '0';
end if;
end if; -- End of row counter above 19
end if; -- end our 'if not lines 1-9
else -- mode = '0', so do VGA
-- Zero out control signals for NTSC
LUMA <= "0000";
COLORBURST <= '0';
SYNC <= '0';
-- Now clock counter is used to count VGA rows.
if (CLK_COUNTER = "01100100000") then
CLK_COUNTER <= "00000000000";
if (ROW_COUNTER = "1000001100") then
ROW_COUNTER <= "0000000000";
else
ROW_COUNTER <= ROW_COUNTER + 1;
end if;
else
CLK_COUNTER <= CLK_COUNTER + 1;
end if;
-- VGA sync timing
if (CLK_COUNTER >= 656 and CLK_COUNTER < 752) then
HSync <= '0';
else
HSync <= '1';
end if;
if (ROW_COUNTER = 490 or ROW_COUNTER = 491) then
VSync <= '0';
else
VSync <= '1';
end if;
-- Wow, VGA is much easier than NTSC with the color test patterns, eh?
if (ROW_COUNTER < 480 and CLK_COUNTER < 640) then
-- color
PIXEL <= ROW_COUNTER (7 downto 4) & CLK_COUNTER (7 downto 4);
else
-- color
PIXEL <= "00000000";
end if;
end if; -- End MODE Check
end if; -- end clock rising edge
end process;
end Behavioral;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_rdmux;
-------------------------------------------------------------------------------
entity axi_sg_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_sg_rddata_cntl;
architecture implementation of axi_sg_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
-- coverage off
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
-- coverage on
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal mm2s_rlast_del : std_logic;
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
-- mm2s_rready <= '1'; --sig_data2mmap_ready;
-- Read Status Block interface
data2rsc_valid <= mm2s_rlast_del; --sig_coelsc_reg_full ;
data2rsc_cmd_cmplt <= mm2s_rlast_del;
-- data2rsc_valid <= sig_coelsc_reg_full ;
mm2s_strm_wvalid <= mm2s_rvalid;-- and sig_data2mmap_ready;
mm2s_strm_wlast <= mm2s_rlast; -- and sig_data2mmap_ready;
mm2s_strm_wstrb <= (others => '1');
mm2s_strm_wdata <= mm2s_rdata;
-- Adding a register for rready as OVC error out during reset
RREADY_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rready <= '0';
Else
mm2s_rready <= '1';
end if;
end if;
end process RREADY_REG;
STATUS_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rlast_del <= '0';
Else
mm2s_rlast_del <= mm2s_rlast and mm2s_rvalid;
end if;
end if;
end process STATUS_REG;
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
rsc2data_ready = '0') then -- and -- Added more qualification here for simultaneus
-- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
Elsif (mm2s_rvalid = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr );
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
--
-- -- AXI MM2S Stream Channel Port assignments
---- mm2s_strm_wvalid <= (mm2s_rvalid and
---- sig_advance_pipe) or
---- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error
--
--
--
---- mm2s_strm_wlast <= (mm2s_rlast and
-- -- sig_next_eof_reg) or
-- -- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error;
--
--
-- -- Generate the Write Strobes for the Stream interface
---- mm2s_strm_wstrb <= (others => '1')
---- When (sig_halt_reg = '1') -- Force tstrb high on a Halt
-- -- else sig_strt_strb_reg
-- -- When (sig_first_dbeat = '1')
-- -- Else sig_last_strb_reg
-- -- When (sig_last_dbeat = '1')
-- -- Else (others => '1');
--
--
--
--
--
-- -- MM2S Supplimental Controls
-- mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
-- sig_next_cmd_cmplt_reg) or
-- (sig_halt_reg and
-- sig_dqual_reg_full and
-- not(sig_no_posted_cmds) and
-- not(sig_calc_error_reg));
--
--
--
--
--
--
-- -- Address Channel Controller synchro pulse input
-- sig_addr_posted <= addr2data_addr_posted;
--
--
--
-- -- Request to halt the Address Channel Controller
data2skid_halt <= '0';
data2all_dcntlr_halted <= '0';
data2mstr_cmd_ready <= '0';
mm2s_data2sf_cmd_cmplt <= '0';
data2addr_stop_req <= sig_halt_reg;
data2rst_stop_cmplt <= '0';
mm2s_rd_xfer_cmplt <= '0';
--
--
-- -- Halted flag to the reset module
-- data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
-- sig_no_posted_cmds and
-- not(sig_calc_error_reg)) or
-- (sig_halt_reg_dly3 and -- Shutdown after error trap
-- sig_calc_error_reg);
--
--
--
-- -- Read Transfer Completed Status output
-- mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
--
--
--
-- -- Internal logic ------------------------------
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_RD_CMPLT_FLAG
-- --
-- -- Process Description:
-- -- Implements the status flag indicating that a read data
-- -- transfer has completed. This is an echo of a rlast assertion
-- -- and a qualified data beat on the AXI4 Read Data Channel
-- -- inputs.
-- --
-- -------------------------------------------------------------
-- IMP_RD_CMPLT_FLAG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_rd_xfer_cmplt <= '0';
--
-- else
--
-- sig_rd_xfer_cmplt <= sig_mmap2data_last and
-- sig_good_mmap_dbeat;
--
-- end if;
-- end if;
-- end process IMP_RD_CMPLT_FLAG;
--
--
--
--
--
-- -- General flag for advancing the MMap Read and the Stream
-- -- data pipelines
-- sig_advance_pipe <= sig_addr_chan_rdy and
-- sig_dqual_rdy and
-- not(sig_coelsc_reg_full) and -- new status back-pressure term
-- not(sig_calc_error_reg);
--
--
-- -- test for Kevin's status throttle case
-- sig_data2mmap_ready <= (mm2s_strm_wready or
-- sig_halt_reg) and -- Ignore the Stream ready on a Halt request
-- sig_advance_pipe;
--
--
--
-- sig_good_mmap_dbeat <= sig_data2mmap_ready and
-- sig_mmap2data_valid;
--
--
-- sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
-- sig_mmap2data_last;
--
--
-- sig_get_next_dqual <= sig_last_mmap_dbeat;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_READ_MUX
-- --
-- -- Description:
-- -- Instance of the MM2S Read Data Channel Read Mux
-- --
-- ------------------------------------------------------------
-- I_READ_MUX : entity axi_sg_v4_1_3.axi_sg_rdmux
-- generic map (
--
-- C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
-- C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
-- C_STREAM_DWIDTH => C_STREAM_DWIDTH
--
-- )
-- port map (
--
-- mmap_read_data_in => mm2s_rdata ,
-- mux_data_out => open, --mm2s_strm_wdata ,
-- mstr2data_saddr_lsb => sig_addr_lsb_reg
--
-- );
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: REG_LAST_DBEAT
-- --
-- -- Process Description:
-- -- This implements a FLOP that creates a pulse
-- -- indicating the LAST signal for an incoming read data channel
-- -- has been received. Note that it is possible to have back to
-- -- back LAST databeats.
-- --
-- -------------------------------------------------------------
-- REG_LAST_DBEAT : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_last_mmap_dbeat_reg <= '0';
--
-- else
--
-- sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
--
-- end if;
-- end if;
-- end process REG_LAST_DBEAT;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Omits the input data control FIFO if the requested FIFO
-- -- depth is 1. The Data Qualifier Register serves as a
-- -- 1 deep FIFO by itself.
-- --
-- ------------------------------------------------------------
-- GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
--
-- begin
--
-- -- Command Calculator Handshake output
-- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
--
-- sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
--
--
--
-- -- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- -- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- -- pre 13.1 -- no calculation error being propagated
--
-- sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
--
--
--
--
-- sig_fifo_next_tag <= mstr2data_tag ;
-- sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
-- sig_fifo_next_len <= mstr2data_len ;
-- sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
-- sig_fifo_next_last_strb <= mstr2data_last_strb ;
-- sig_fifo_next_drr <= mstr2data_drr ;
-- sig_fifo_next_eof <= mstr2data_eof ;
-- sig_fifo_next_sequential <= mstr2data_sequential ;
-- sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
-- sig_fifo_next_calc_error <= mstr2data_calc_error ;
--
-- sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
-- sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
--
--
--
-- end generate GEN_NO_DATA_CNTL_FIFO;
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Includes the input data control FIFO if the requested
-- -- FIFO depth is more than 1.
-- --
-- ------------------------------------------------------------
---- GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
----
---- begin
----
----
---- -- Command Calculator Handshake output
---- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
----
---- sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
----
----
---- sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
----
----
----
----
----
---- -- Format the input fifo data word
---- sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
---- mstr2data_dre_src_align &
---- mstr2data_calc_error &
---- mstr2data_cmd_cmplt &
---- mstr2data_sequential &
---- mstr2data_eof &
---- mstr2data_drr &
---- mstr2data_last_strb &
---- mstr2data_strt_strb &
---- mstr2data_len &
---- mstr2data_saddr_lsb &
---- mstr2data_tag ;
----
----
---- -- Rip the output fifo data word
---- sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
---- TAG_STRT_INDEX);
---- sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
---- SADDR_LSB_STRT_INDEX);
---- sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
---- LEN_STRT_INDEX);
---- sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- STRT_STRB_STRT_INDEX);
---- sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- LAST_STRB_STRT_INDEX);
---- sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
---- sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
---- sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
---- sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
---- sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
----
---- sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_SRC_STRT_INDEX);
---- sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_DEST_STRT_INDEX);
----
----
----
----
---- ------------------------------------------------------------
---- -- Instance: I_DATA_CNTL_FIFO
---- --
---- -- Description:
---- -- Instance for the Command Qualifier FIFO
---- --
---- ------------------------------------------------------------
---- I_DATA_CNTL_FIFO : entity axi_sg_v4_1_3.axi_sg_fifo
---- generic map (
----
---- C_DWIDTH => DCTL_FIFO_WIDTH ,
---- C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
---- C_IS_ASYNC => USE_SYNC_FIFO ,
---- C_PRIM_TYPE => FIFO_PRIM_TYPE ,
---- C_FAMILY => C_FAMILY
----
---- )
---- port map (
----
---- -- Write Clock and reset
---- fifo_wr_reset => mmap_reset ,
---- fifo_wr_clk => primary_aclk ,
----
---- -- Write Side
---- fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
---- fifo_wr_tready => sig_fifo_wr_cmd_ready ,
---- fifo_wr_tdata => sig_cmd_fifo_data_in ,
---- fifo_wr_full => open ,
----
---- -- Read Clock and reset
---- fifo_async_rd_reset => mmap_reset ,
---- fifo_async_rd_clk => primary_aclk ,
----
---- -- Read Side
---- fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
---- fifo_rd_tready => sig_fifo_rd_cmd_ready ,
---- fifo_rd_tdata => sig_cmd_fifo_data_out ,
---- fifo_rd_empty => sig_cmd_fifo_empty
----
---- );
----
----
---- end generate GEN_DATA_CNTL_FIFO;
----
--
--
--
--
--
--
--
--
-- -- Data Qualifier Register ------------------------------------
--
-- sig_ld_new_cmd <= sig_push_dqual_reg ;
-- sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
-- sig_dqual_rdy <= sig_dqual_reg_full ;
-- sig_strt_strb_reg <= sig_next_strt_strb_reg ;
-- sig_last_strb_reg <= sig_next_last_strb_reg ;
-- sig_tag_reg <= sig_next_tag_reg ;
-- sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
-- sig_calc_error_reg <= sig_next_calc_error_reg ;
--
--
-- -- Flag indicating that there are no posted commands to AXI
-- sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
--
--
--
-- -- new for no bubbles between child requests
-- sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
-- sig_last_dbeat and -- last data beat of transfer
-- sig_next_sequential_reg;-- next queued command is sequential
-- -- to the current command
--
--
-- -- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- -- pre 13.1 sig_dqual_reg_empty) and
-- -- pre 13.1 sig_fifo_rd_cmd_valid and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
-- sig_push_dqual_reg <= (sig_sequential_push or
-- sig_dqual_reg_empty) and
-- sig_fifo_rd_cmd_valid and
-- sig_aposted_cntr_ready and
-- not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
-- not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
--
-- sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
-- sig_get_next_dqual and
-- sig_dqual_reg_full ;
--
--
-- -- new for no bubbles between child requests
-- sig_clr_dqual_reg <= mmap_reset or
-- (sig_pop_dqual_reg and
-- not(sig_push_dqual_reg));
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_DQUAL_REG
-- --
-- -- Process Description:
-- -- This process implements a register for the Data
-- -- Control and qualifiers. It operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_DQUAL_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (sig_clr_dqual_reg = '1') then
--
-- sig_next_tag_reg <= (others => '0');
-- sig_next_strt_strb_reg <= (others => '0');
-- sig_next_last_strb_reg <= (others => '0');
-- sig_next_eof_reg <= '0';
-- sig_next_cmd_cmplt_reg <= '0';
-- sig_next_sequential_reg <= '0';
-- sig_next_calc_error_reg <= '0';
-- sig_next_dre_src_align_reg <= (others => '0');
-- sig_next_dre_dest_align_reg <= (others => '0');
--
-- sig_dqual_reg_empty <= '1';
-- sig_dqual_reg_full <= '0';
--
-- elsif (sig_push_dqual_reg = '1') then
--
-- sig_next_tag_reg <= sig_fifo_next_tag ;
-- sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
-- sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
-- sig_next_eof_reg <= sig_fifo_next_eof ;
-- sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
-- sig_next_sequential_reg <= sig_fifo_next_sequential ;
-- sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
-- sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
-- sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
--
-- sig_dqual_reg_empty <= '0';
-- sig_dqual_reg_full <= '1';
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_DQUAL_REG;
--
--
--
--
--
--
--
-- -- Address LS Cntr logic --------------------------
--
-- sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
-- sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
-- sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_ADDR_LSB_CNTR
-- --
-- -- Process Description:
-- -- Implements the LS Address Counter used for controlling
-- -- the Read Data Mux during Burst transfers
-- --
-- -------------------------------------------------------------
-- DO_ADDR_LSB_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- (sig_pop_dqual_reg = '1' and
-- sig_push_dqual_reg = '0')) then -- Clear the Counter
--
-- sig_ls_addr_cntr <= (others => '0');
--
-- elsif (sig_push_dqual_reg = '1') then -- Load the Counter
--
-- sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
--
-- elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
--
-- sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
--
-- else
-- null; -- Hold Current value
-- end if;
-- end if;
-- end process DO_ADDR_LSB_CNTR;
--
--
--
--
--
--
--
--
--
--
--
--
-- ----- Address posted Counter logic --------------------------------
--
-- sig_incr_addr_posted_cntr <= sig_addr_posted ;
--
--
-- sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
--
--
-- sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
--
-- sig_addr_posted_cntr_eq_0 <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
-- Else '0';
--
-- sig_addr_posted_cntr_max <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
-- Else '0';
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_ADDR_POSTED_FIFO_CNTR
-- --
-- -- Process Description:
-- -- This process implements a register for the Address
-- -- Posted FIFO that operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
--
-- elsif (sig_incr_addr_posted_cntr = '1' and
-- sig_decr_addr_posted_cntr = '0' and
-- sig_addr_posted_cntr_max = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
--
-- elsif (sig_incr_addr_posted_cntr = '0' and
-- sig_decr_addr_posted_cntr = '1' and
-- sig_addr_posted_cntr_eq_0 = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_ADDR_POSTED_FIFO_CNTR;
--
--
--
--
--
--
--
--
-- ------- First/Middle/Last Dbeat detirmination -------------------
--
-- sig_new_len_eq_0 <= '1'
-- When (sig_fifo_next_len = LEN_OF_ZERO)
-- else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_FIRST_MID_LAST
-- --
-- -- Process Description:
-- -- Implements the detection of the First/Mid/Last databeat of
-- -- a transfer.
-- --
-- -------------------------------------------------------------
-- DO_FIRST_MID_LAST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- elsif (sig_ld_new_cmd = '1') then
--
-- sig_first_dbeat <= not(sig_new_len_eq_0);
-- sig_last_dbeat <= sig_new_len_eq_0;
--
-- Elsif (sig_dbeat_cntr_eq_1 = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '1';
--
-- Elsif (sig_dbeat_cntr_eq_0 = '0' and
-- sig_dbeat_cntr_eq_1 = '0' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- else
-- null; -- hols current state
-- end if;
-- end if;
-- end process DO_FIRST_MID_LAST;
--
--
--
--
--
-- ------- Data Controller Halted Indication -------------------------------
--
--
-- data2all_dcntlr_halted <= sig_no_posted_cmds and
-- (sig_calc_error_reg or
-- rst2data_stop_request);
--
--
--
--
-- ------- Data Beat counter logic -------------------------------
-- sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
--
-- sig_dbeat_cntr_eq_0 <= '1'
-- when (sig_dbeat_cntr_int = 0)
-- Else '0';
--
-- sig_dbeat_cntr_eq_1 <= '1'
-- when (sig_dbeat_cntr_int = 1)
-- Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_DBEAT_CNTR
-- --
-- -- Process Description:
-- --
-- --
-- -------------------------------------------------------------
-- DO_DBEAT_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
-- sig_dbeat_cntr <= (others => '0');
-- elsif (sig_ld_new_cmd = '1') then
-- sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
-- Elsif (sig_good_mmap_dbeat = '1' and
-- sig_dbeat_cntr_eq_0 = '0') Then
-- sig_dbeat_cntr <= sig_dbeat_cntr-1;
-- else
-- null; -- Hold current state
-- end if;
-- end if;
-- end process DO_DBEAT_CNTR;
--
--
--
--
--
--
-- ------ Read Response Status Logic ------------------------------
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: LD_NEW_CMD_PULSE
-- --
-- -- Process Description:
-- -- Generate a 1 Clock wide pulse when a new command has been
-- -- loaded into the Command Register
-- --
-- -------------------------------------------------------------
-- LD_NEW_CMD_PULSE : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_ld_new_cmd_reg = '1') then
-- sig_ld_new_cmd_reg <= '0';
-- elsif (sig_ld_new_cmd = '1') then
-- sig_ld_new_cmd_reg <= '1';
-- else
-- null; -- hold State
-- end if;
-- end if;
-- end process LD_NEW_CMD_PULSE;
--
--
--
-- sig_pop_coelsc_reg <= sig_coelsc_reg_full and
-- sig_rsc2data_ready ;
--
-- sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
-- not(sig_coelsc_reg_full)) or
-- (sig_ld_new_cmd_reg and
-- sig_calc_error_reg) ;
--
-- sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
-- sig_calc_error_reg;
--
--
--
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When mm2s_rresp = DECERR
Else '0';
sig_slverr <= '1'
When mm2s_rresp = SLVERR
Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: RD_RESP_COELESC_REG
-- --
-- -- Process Description:
-- -- Implement the Read error/status coelescing register.
-- -- Once a bit is set it will remain set until the overall
-- -- status is written to the Status Controller.
-- -- Tag bits are just registered at each valid dbeat.
-- --
-- -------------------------------------------------------------
---- STATUS_COELESC_REG : process (primary_aclk)
---- begin
---- if (primary_aclk'event and primary_aclk = '1') then
---- if (mmap_reset = '1' or
---- (sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
---- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
----
---- sig_coelsc_tag_reg <= (others => '0');
---- sig_coelsc_cmd_cmplt_reg <= '0';
---- sig_coelsc_interr_reg <= '0';
---- sig_coelsc_decerr_reg <= '0';
---- sig_coelsc_slverr_reg <= '0';
---- sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
----
---- sig_coelsc_reg_full <= '0';
---- sig_coelsc_reg_empty <= '1';
----
----
----
---- Elsif (sig_push_coelsc_reg = '1') Then
----
---- sig_coelsc_tag_reg <= sig_tag_reg;
---- sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_interr_reg <= sig_calc_error_reg or
---- sig_coelsc_interr_reg;
---- sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
---- sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
---- sig_coelsc_okay_reg <= not(sig_decerr or
---- sig_slverr or
---- sig_calc_error_reg );
----
---- sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
----
----
---- else
----
---- null; -- hold current state
----
---- end if;
---- end if;
---- end process STATUS_COELESC_REG;
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DRE
-- --
-- -- If Generate Description:
-- -- Ties off DRE Control signals to logic low when DRE is
-- -- omitted from the MM2S functionality.
-- --
-- --
-- ------------------------------------------------------------
-- GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
--
-- begin
--
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
--
-- end generate GEN_NO_DRE;
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_INCLUDE_DRE_CNTLS
-- --
-- -- If Generate Description:
-- -- Implements the DRE Control logic when MM2S DRE is enabled.
-- --
-- -- - The DRE needs to have forced alignment at a SOF assertion
-- --
-- --
-- ------------------------------------------------------------
-- GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
--
-- -- local signals
-- signal lsig_s_h_dre_autodest : std_logic := '0';
-- signal lsig_s_h_dre_new_align : std_logic := '0';
--
-- begin
--
--
-- mm2s_dre_new_align <= lsig_s_h_dre_new_align;
--
--
--
--
-- -- Autodest is asserted on a new parent command and the
-- -- previous parent command was not delimited with a EOF
-- mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
--
--
--
--
-- -- Assign the DRE Source and Destination Alignments
-- -- Only used when mm2s_dre_new_align is asserted
-- mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
-- mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
--
--
-- -- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- -- asserted and the next transfer is not sequential and not the last
-- -- transfer of a packet.
-- mm2s_dre_flush <= mm2s_rlast and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_NEW_ALIGN
-- --
-- -- Process Description:
-- -- Generates the new alignment command flag to the DRE.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_NEW_ALIGN : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_new_align <= '1';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_NEW_ALIGN;
--
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_AUTODEST
-- --
-- -- Process Description:
-- -- Generates the control for the DRE indicating whether the
-- -- DRE destination alignment should be derived from the write
-- -- strobe stat of the last completed data-beat to the AXI
-- -- stream output.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_AUTODEST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (lsig_s_h_dre_new_align = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_AUTODEST;
--
--
--
--
-- end generate GEN_INCLUDE_DRE_CNTLS;
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------- Soft Shutdown Logic -------------------------------
--
--
-- -- Assign the output port skid buf control
-- data2skid_halt <= sig_data2skid_halt;
--
-- -- Create a 1 clock wide pulse to tell the output
-- -- stream skid buffer to shut down its outputs
-- sig_data2skid_halt <= sig_halt_reg_dly2 and
-- not(sig_halt_reg_dly3);
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG
-- --
-- -- Process Description:
-- -- Implements the flop for capturing the Halt request from
-- -- the Reset module.
-- --
-- -------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG_DLY
-- --
-- -- Process Description:
-- -- Implements the flops for delaying the halt request by 3
-- -- clocks to allow the Address Controller to halt before the
-- -- Data Contoller can safely indicate it has exhausted all
-- -- transfers committed to the AXI Address Channel by the Address
-- -- Controller.
-- --
-- -------------------------------------------------------------
-- IMP_HALT_REQ_REG_DLY : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_halt_reg_dly1 <= '0';
-- sig_halt_reg_dly2 <= '0';
-- sig_halt_reg_dly3 <= '0';
--
-- else
--
-- sig_halt_reg_dly1 <= sig_halt_reg;
-- sig_halt_reg_dly2 <= sig_halt_reg_dly1;
-- sig_halt_reg_dly3 <= sig_halt_reg_dly2;
--
-- end if;
-- end if;
-- end process IMP_HALT_REQ_REG_DLY;
--
--
--
--
--
--
--
--
--
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pr is
port(clk, S_PRlat, S_s_inc : in std_logic;
S_BUS_C : in std_logic_vector(15 downto 0);
S_PR_F : out std_logic_vector(15 downto 0));
end pr;
architecture BEHAVIOR of pr is
signal rst : std_logic_vector(15 downto 0) := "0000000010000000";
begin
S_PR_F <= rst;
process(clk) begin
if clk'event and clk = '1' then
if S_PRlat = '1' then
rst <= S_BUS_C;
elsif S_s_inc = '1' then
rst <= rst + 1;
else
null;
end if;
end if;
end process;
end BEHAVIOR;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pr is
port(clk, S_PRlat, S_s_inc : in std_logic;
S_BUS_C : in std_logic_vector(15 downto 0);
S_PR_F : out std_logic_vector(15 downto 0));
end pr;
architecture BEHAVIOR of pr is
signal rst : std_logic_vector(15 downto 0) := "0000000010000000";
begin
S_PR_F <= rst;
process(clk) begin
if clk'event and clk = '1' then
if S_PRlat = '1' then
rst <= S_BUS_C;
elsif S_s_inc = '1' then
rst <= rst + 1;
else
null;
end if;
end if;
end process;
end BEHAVIOR;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level_tb is
end;
architecture test of top_level_tb is
component top_level
PORT(
--ONLY PHY CONNECTIONS IN TOP LEVEL
CLOCK_50 : IN STD_LOGIC;
SW : IN STD_LOGIC_VECTOR(17 downto 0);
HEX0, HEX1, HEX2, HEX3,
HEX4, HEX5, HEX6, HEX7 : OUT std_logic_vector(6 downto 0)
);
end component;
constant clk_period : time := 20ns;
signal CLOCK_50 : std_logic;
signal SW : std_logic_vector(17 downto 0);
signal HEX0 : std_logic_vector(6 downto 0);
signal HEX1 : std_logic_vector(6 downto 0);
signal HEX2 : std_logic_vector(6 downto 0);
signal HEX3 : std_logic_vector(6 downto 0);
signal HEX4 : std_logic_vector(6 downto 0);
signal HEX5 : std_logic_vector(6 downto 0);
signal HEX6 : std_logic_vector(6 downto 0);
signal HEX7 : std_logic_vector(6 downto 0);
begin
uut : top_level PORT MAP(
CLOCK_50 => CLOCK_50,
SW => SW,
HEX0 => HEX0,
HEX1 => HEX1,
HEX2 => HEX2,
HEX3 => HEX3,
HEX4 => HEX4,
HEX5 => HEX5,
HEX6 => HEX6,
HEX7 => HEX7
);
clk_process : process begin
CLOCK_50 <= '1';
wait for clk_period/2;
CLOCK_50 <= '0';
wait for clk_period/2;
end process;
stim_process : process begin
SW(17) <= '0';
wait for clk_period*2;
SW(17) <= '1';
wait;
end process;
end; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level_tb is
end;
architecture test of top_level_tb is
component top_level
PORT(
--ONLY PHY CONNECTIONS IN TOP LEVEL
CLOCK_50 : IN STD_LOGIC;
SW : IN STD_LOGIC_VECTOR(17 downto 0);
HEX0, HEX1, HEX2, HEX3,
HEX4, HEX5, HEX6, HEX7 : OUT std_logic_vector(6 downto 0)
);
end component;
constant clk_period : time := 20ns;
signal CLOCK_50 : std_logic;
signal SW : std_logic_vector(17 downto 0);
signal HEX0 : std_logic_vector(6 downto 0);
signal HEX1 : std_logic_vector(6 downto 0);
signal HEX2 : std_logic_vector(6 downto 0);
signal HEX3 : std_logic_vector(6 downto 0);
signal HEX4 : std_logic_vector(6 downto 0);
signal HEX5 : std_logic_vector(6 downto 0);
signal HEX6 : std_logic_vector(6 downto 0);
signal HEX7 : std_logic_vector(6 downto 0);
begin
uut : top_level PORT MAP(
CLOCK_50 => CLOCK_50,
SW => SW,
HEX0 => HEX0,
HEX1 => HEX1,
HEX2 => HEX2,
HEX3 => HEX3,
HEX4 => HEX4,
HEX5 => HEX5,
HEX6 => HEX6,
HEX7 => HEX7
);
clk_process : process begin
CLOCK_50 <= '1';
wait for clk_period/2;
CLOCK_50 <= '0';
wait for clk_period/2;
end process;
stim_process : process begin
SW(17) <= '0';
wait for clk_period*2;
SW(17) <= '1';
wait;
end process;
end; |
-- Based on tutorial here:
-- https://www.youtube.com/watch?v=j2lAPIjpF1w&t=309s
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library sevseg_package;
use sevseg_package.my.all;
ENTITY SEVSEG is
PORT(
SW: IN STD_LOGIC_VECTOR(9 downto 0);
HEX0: OUT STD_LOGIC_VECTOR(6 downto 0);
HEX1: OUT STD_LOGIC_VECTOR(6 downto 0);
HEX2: OUT STD_LOGIC_VECTOR(6 downto 0);
HEX3: OUT STD_LOGIC_VECTOR(6 downto 0);
KEY: in STD_LOGIC_VECTOR(3 downto 0);
CLOCK_50: IN STD_LOGIC
);
END SEVSEG;
ARCHITECTURE MAIN of SEVSEG IS
SIGNAL NUMBER: INTEGER RANGE 0 to 9999:=0;
SIGNAL PRESCALER: INTEGER RANGE 0 to 50000000:=0;
SIGNAL SEG0, SEG1, SEG2, SEG3: INTEGER range 0 to 9:=0;
BEGIN
-- Call package procedure to assign values to each 7seg display.
HEX_DEC(NUMBER, SEG0, SEG1, SEG2, SEG3);
-- Call function to update each hex display.
HEX0<=INT_TO7SEG(SEG0);
HEX1<=INT_TO7SEG(SEG1);
HEX2<=INT_TO7SEG(SEG2);
HEX3<=INT_TO7SEG(SEG3);
-- Define clock-driven process:
PROCESS(CLOCK_50)
BEGIN
IF(CLOCK_50'EVENT and CLOCK_50='1') THEN
IF(PRESCALER<100000*to_integer(unsigned(SW))) THEN
PRESCALER<=PRESCALER+1;
ELSE
PRESCALER<=0;
end if;
IF(PRESCALER=0)THEN
IF(KEY(0)='1')THEN
IF(NUMBER<9999)THEN
NUMBER<=NUMBER+1;
ELSE
NUMBER<=9999;
END IF;
ELSE
IF(NUMBER>0) THEN
NUMBER<=NUMBER-1;
ELSE
NUMBER<=0;
END IF;
END IF;
-- Does lack of else here cause a latch situation?
END IF;
END IF;
END PROCESS;
END MAIN; |
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity flipflopD is
port(
clk: in std_logic;
enable: in std_logic;
D: in std_logic;
Q: out std_logic
);
end entity;
architecture a_flipflopD of flipflopD is
begin
process(clk,enable)
begin
if enable='0' then null;
elsif rising_edge(clk) then
Q <= D;
end if;
end process;
end architecture; |
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- Containing RapidIO packet switching functionality contained in the top
-- entity RioSwitch.
--
-- To Do:
-- -
--
-- Author(s):
-- - Magnus Rosenius, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RioSwitch
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for RioSwitch.
-------------------------------------------------------------------------------
entity RioSwitch is
generic(
SWITCH_PORTS : natural range 3 to 255 := 4;
DEVICE_IDENTITY : std_logic_vector(15 downto 0);
DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
DEVICE_REV : std_logic_vector(31 downto 0);
ASSY_IDENTITY : std_logic_vector(15 downto 0);
ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
ASSY_REV : std_logic_vector(15 downto 0));
port(
clk : in std_logic;
areset_n : in std_logic;
writeFrameFull_i : in Array1(SWITCH_PORTS-1 downto 0);
writeFrame_o : out Array1(SWITCH_PORTS-1 downto 0);
writeFrameAbort_o : out Array1(SWITCH_PORTS-1 downto 0);
writeContent_o : out Array1(SWITCH_PORTS-1 downto 0);
writeContentData_o : out Array32(SWITCH_PORTS-1 downto 0);
readFrameEmpty_i : in Array1(SWITCH_PORTS-1 downto 0);
readFrame_o : out Array1(SWITCH_PORTS-1 downto 0);
readFrameRestart_o : out Array1(SWITCH_PORTS-1 downto 0);
readFrameAborted_i : in Array1(SWITCH_PORTS-1 downto 0);
readContentEmpty_i : in Array1(SWITCH_PORTS-1 downto 0);
readContent_o : out Array1(SWITCH_PORTS-1 downto 0);
readContentEnd_i : in Array1(SWITCH_PORTS-1 downto 0);
readContentData_i : in Array32(SWITCH_PORTS-1 downto 0);
portLinkTimeout_o : out std_logic_vector(23 downto 0);
linkInitialized_i : in Array1(SWITCH_PORTS-1 downto 0);
outputPortEnable_o : out Array1(SWITCH_PORTS-1 downto 0);
inputPortEnable_o : out Array1(SWITCH_PORTS-1 downto 0);
localAckIdWrite_o : out Array1(SWITCH_PORTS-1 downto 0);
clrOutstandingAckId_o : out Array1(SWITCH_PORTS-1 downto 0);
inboundAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
outstandingAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
outboundAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
inboundAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
outstandingAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
outboundAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
configStb_o : out std_logic;
configWe_o : out std_logic;
configAddr_o : out std_logic_vector(23 downto 0);
configData_o : out std_logic_vector(31 downto 0);
configData_i : in std_logic_vector(31 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for RioSwitch.
-------------------------------------------------------------------------------
architecture RioSwitchImpl of RioSwitch is
component RouteTableInterconnect is
generic(
WIDTH : natural range 1 to 256 := 8);
port(
clk : in std_logic;
areset_n : in std_logic;
stb_i : in Array1(WIDTH-1 downto 0);
addr_i : in Array16(WIDTH-1 downto 0);
dataM_o : out Array8(WIDTH-1 downto 0);
ack_o : out Array1(WIDTH-1 downto 0);
stb_o : out std_logic;
addr_o : out std_logic_vector(15 downto 0);
dataS_i : in std_logic_vector(7 downto 0);
ack_i : in std_logic);
end component;
component SwitchPortInterconnect is
generic(
WIDTH : natural range 1 to 256 := 8);
port(
clk : in std_logic;
areset_n : in std_logic;
masterCyc_i : in Array1(WIDTH-1 downto 0);
masterStb_i : in Array1(WIDTH-1 downto 0);
masterWe_i : in Array1(WIDTH-1 downto 0);
masterAddr_i : in Array10(WIDTH-1 downto 0);
masterData_i : in Array32(WIDTH-1 downto 0);
masterData_o : out Array1(WIDTH-1 downto 0);
masterAck_o : out Array1(WIDTH-1 downto 0);
slaveCyc_o : out Array1(WIDTH-1 downto 0);
slaveStb_o : out Array1(WIDTH-1 downto 0);
slaveWe_o : out Array1(WIDTH-1 downto 0);
slaveAddr_o : out Array10(WIDTH-1 downto 0);
slaveData_o : out Array32(WIDTH-1 downto 0);
slaveData_i : in Array1(WIDTH-1 downto 0);
slaveAck_i : in Array1(WIDTH-1 downto 0));
end component;
component SwitchPortMaintenance is
generic(
SWITCH_PORTS : natural range 0 to 255;
DEVICE_IDENTITY : std_logic_vector(15 downto 0);
DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
DEVICE_REV : std_logic_vector(31 downto 0);
ASSY_IDENTITY : std_logic_vector(15 downto 0);
ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
ASSY_REV : std_logic_vector(15 downto 0));
port(
clk : in std_logic;
areset_n : in std_logic;
lookupStb_i : in std_logic;
lookupAddr_i : in std_logic_vector(15 downto 0);
lookupData_o : out std_logic_vector(7 downto 0);
lookupAck_o : out std_logic;
masterCyc_o : out std_logic;
masterStb_o : out std_logic;
masterWe_o : out std_logic;
masterAddr_o : out std_logic_vector(9 downto 0);
masterData_o : out std_logic_vector(31 downto 0);
masterData_i : in std_logic;
masterAck_i : in std_logic;
slaveCyc_i : in std_logic;
slaveStb_i : in std_logic;
slaveWe_i : in std_logic;
slaveAddr_i : in std_logic_vector(9 downto 0);
slaveData_i : in std_logic_vector(31 downto 0);
slaveData_o : out std_logic;
slaveAck_o : out std_logic;
lookupStb_o : out std_logic;
lookupAddr_o : out std_logic_vector(15 downto 0);
lookupData_i : in std_logic_vector(7 downto 0);
lookupAck_i : in std_logic;
portLinkTimeout_o : out std_logic_vector(23 downto 0);
linkInitialized_i : in Array1(SWITCH_PORTS-1 downto 0);
outputPortEnable_o : out Array1(SWITCH_PORTS-1 downto 0);
inputPortEnable_o : out Array1(SWITCH_PORTS-1 downto 0);
localAckIdWrite_o : out Array1(SWITCH_PORTS-1 downto 0);
clrOutstandingAckId_o : out Array1(SWITCH_PORTS-1 downto 0);
inboundAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
outstandingAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
outboundAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
inboundAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
outstandingAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
outboundAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
configStb_o : out std_logic;
configWe_o : out std_logic;
configAddr_o : out std_logic_vector(23 downto 0);
configData_o : out std_logic_vector(31 downto 0);
configData_i : in std_logic_vector(31 downto 0));
end component;
component SwitchPort is
generic(
PORT_INDEX : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
masterCyc_o : out std_logic;
masterStb_o : out std_logic;
masterWe_o : out std_logic;
masterAddr_o : out std_logic_vector(9 downto 0);
masterData_o : out std_logic_vector(31 downto 0);
masterData_i : in std_logic;
masterAck_i : in std_logic;
slaveCyc_i : in std_logic;
slaveStb_i : in std_logic;
slaveWe_i : in std_logic;
slaveAddr_i : in std_logic_vector(9 downto 0);
slaveData_i : in std_logic_vector(31 downto 0);
slaveData_o : out std_logic;
slaveAck_o : out std_logic;
lookupStb_o : out std_logic;
lookupAddr_o : out std_logic_vector(15 downto 0);
lookupData_i : in std_logic_vector(7 downto 0);
lookupAck_i : in std_logic;
readFrameEmpty_i : in std_logic;
readFrame_o : out std_logic;
readFrameRestart_o : out std_logic;
readFrameAborted_i : in std_logic;
readContentEmpty_i : in std_logic;
readContent_o : out std_logic;
readContentEnd_i : in std_logic;
readContentData_i : in std_logic_vector(31 downto 0);
writeFrameFull_i : in std_logic;
writeFrame_o : out std_logic;
writeFrameAbort_o : out std_logic;
writeContent_o : out std_logic;
writeContentData_o : out std_logic_vector(31 downto 0));
end component;
signal masterLookupStb : Array1(SWITCH_PORTS downto 0);
signal masterLookupAddr : Array16(SWITCH_PORTS downto 0);
signal masterLookupData : Array8(SWITCH_PORTS downto 0);
signal masterLookupAck : Array1(SWITCH_PORTS downto 0);
signal slaveLookupStb : std_logic;
signal slaveLookupAddr : std_logic_vector(15 downto 0);
signal slaveLookupData : std_logic_vector(7 downto 0);
signal slaveLookupAck : std_logic;
signal masterCyc : Array1(SWITCH_PORTS downto 0);
signal masterStb : Array1(SWITCH_PORTS downto 0);
signal masterWe : Array1(SWITCH_PORTS downto 0);
signal masterAddr : Array10(SWITCH_PORTS downto 0);
signal masterDataWrite : Array32(SWITCH_PORTS downto 0);
signal masterDataRead : Array1(SWITCH_PORTS downto 0);
signal masterAck : Array1(SWITCH_PORTS downto 0);
signal slaveCyc : Array1(SWITCH_PORTS downto 0);
signal slaveStb : Array1(SWITCH_PORTS downto 0);
signal slaveWe : Array1(SWITCH_PORTS downto 0);
signal slaveAddr : Array10(SWITCH_PORTS downto 0);
signal slaveDataWrite : Array32(SWITCH_PORTS downto 0);
signal slaveDataRead : Array1(SWITCH_PORTS downto 0);
signal slaveAck : Array1(SWITCH_PORTS downto 0);
begin
-----------------------------------------------------------------------------
-- The routing table interconnect.
-----------------------------------------------------------------------------
RouteInterconnect: RouteTableInterconnect
generic map(
WIDTH=>SWITCH_PORTS+1)
port map(
clk=>clk, areset_n=>areset_n,
stb_i=>masterLookupStb, addr_i=>masterLookupAddr,
dataM_o=>masterLookupData, ack_o=>masterLookupAck,
stb_o=>slaveLookupStb, addr_o=>slaveLookupAddr,
dataS_i=>slaveLookupData, ack_i=>slaveLookupAck);
-----------------------------------------------------------------------------
-- The port interconnect.
-----------------------------------------------------------------------------
PortInterconnect: SwitchPortInterconnect
generic map(
WIDTH=>SWITCH_PORTS+1)
port map(
clk=>clk, areset_n=>areset_n,
masterCyc_i=>masterCyc, masterStb_i=>masterStb, masterWe_i=>masterWe, masterAddr_i=>masterAddr,
masterData_i=>masterDataWrite, masterData_o=>masterDataRead, masterAck_o=>masterAck,
slaveCyc_o=>slaveCyc, slaveStb_o=>slaveStb, slaveWe_o=>slaveWe, slaveAddr_o=>slaveAddr,
slaveData_o=>slaveDataWrite, slaveData_i=>slaveDataRead, slaveAck_i=>slaveAck);
-----------------------------------------------------------------------------
-- Data relaying port instantiation.
-----------------------------------------------------------------------------
PortGeneration: for portIndex in 0 to SWITCH_PORTS-1 generate
PortInst: SwitchPort
generic map(
PORT_INDEX=>portIndex)
port map(
clk=>clk, areset_n=>areset_n,
masterCyc_o=>masterCyc(portIndex), masterStb_o=>masterStb(portIndex),
masterWe_o=>masterWe(portIndex), masterAddr_o=>masterAddr(portIndex),
masterData_o=>masterDataWrite(portIndex),
masterData_i=>masterDataRead(portIndex), masterAck_i=>masterAck(portIndex),
slaveCyc_i=>slaveCyc(portIndex), slaveStb_i=>slaveStb(portIndex),
slaveWe_i=>slaveWe(portIndex), slaveAddr_i=>slaveAddr(portIndex),
slaveData_i=>slaveDataWrite(portIndex),
slaveData_o=>slaveDataRead(portIndex), slaveAck_o=>slaveAck(portIndex),
lookupStb_o=>masterLookupStb(portIndex),
lookupAddr_o=>masterLookupAddr(portIndex),
lookupData_i=>masterLookupData(portIndex), lookupAck_i=>masterLookupAck(portIndex),
readFrameEmpty_i=>readFrameEmpty_i(portIndex), readFrame_o=>readFrame_o(portIndex),
readFrameRestart_o=>readFrameRestart_o(portIndex),
readFrameAborted_i=>readFrameAborted_i(portIndex),
readContentEmpty_i=>readContentEmpty_i(portIndex), readContent_o=>readContent_o(portIndex),
readContentEnd_i=>readContentEnd_i(portIndex), readContentData_i=>readContentData_i(portIndex),
writeFrameFull_i=>writeFrameFull_i(portIndex), writeFrame_o=>writeFrame_o(portIndex),
writeFrameAbort_o=>writeFrameAbort_o(portIndex), writeContent_o=>writeContent_o(portIndex),
writeContentData_o=>writeContentData_o(portIndex));
end generate;
-----------------------------------------------------------------------------
-- Maintenance port instantiation.
-----------------------------------------------------------------------------
MaintenancePort: SwitchPortMaintenance
generic map(
SWITCH_PORTS=>SWITCH_PORTS,
DEVICE_IDENTITY=>DEVICE_IDENTITY,
DEVICE_VENDOR_IDENTITY=>DEVICE_VENDOR_IDENTITY,
DEVICE_REV=>DEVICE_REV,
ASSY_IDENTITY=>ASSY_IDENTITY,
ASSY_VENDOR_IDENTITY=>ASSY_VENDOR_IDENTITY,
ASSY_REV=>ASSY_REV)
port map(
clk=>clk, areset_n=>areset_n,
lookupStb_i=>slaveLookupStb, lookupAddr_i=>slaveLookupAddr,
lookupData_o=>slaveLookupData, lookupAck_o=>slaveLookupAck,
masterCyc_o=>masterCyc(SWITCH_PORTS), masterStb_o=>masterStb(SWITCH_PORTS),
masterWe_o=>masterWe(SWITCH_PORTS), masterAddr_o=>masterAddr(SWITCH_PORTS),
masterData_o=>masterDataWrite(SWITCH_PORTS),
masterData_i=>masterDataRead(SWITCH_PORTS), masterAck_i=>masterAck(SWITCH_PORTS),
slaveCyc_i=>slaveCyc(SWITCH_PORTS), slaveStb_i=>slaveStb(SWITCH_PORTS),
slaveWe_i=>slaveWe(SWITCH_PORTS), slaveAddr_i=>slaveAddr(SWITCH_PORTS),
slaveData_i=>slaveDataWrite(SWITCH_PORTS),
slaveData_o=>slaveDataRead(SWITCH_PORTS), slaveAck_o=>slaveAck(SWITCH_PORTS),
lookupStb_o=>masterLookupStb(SWITCH_PORTS),
lookupAddr_o=>masterLookupAddr(SWITCH_PORTS),
lookupData_i=>masterLookupData(SWITCH_PORTS), lookupAck_i=>masterLookupAck(SWITCH_PORTS),
portLinkTimeout_o=>portLinkTimeout_o,
linkInitialized_i=>linkInitialized_i,
outputPortEnable_o=>outputPortEnable_o, inputPortEnable_o=>inputPortEnable_o,
localAckIdWrite_o=>localAckIdWrite_o, clrOutstandingAckId_o=>clrOutstandingAckId_o,
inboundAckId_o=>inboundAckId_o, outstandingAckId_o=>outstandingAckId_o,
outboundAckId_o=>outboundAckId_o, inboundAckId_i=>inboundAckId_i,
outstandingAckId_i=>outstandingAckId_i, outboundAckId_i=>outboundAckId_i,
configStb_o=>configStb_o, configWe_o=>configWe_o, configAddr_o=>configAddr_o,
configData_o=>configData_o, configData_i=>configData_i);
end architecture;
-------------------------------------------------------------------------------
-- SwitchPort
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for SwitchPort.
-------------------------------------------------------------------------------
entity SwitchPort is
generic(
PORT_INDEX : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
-- Master port signals.
-- Write frames to other ports.
masterCyc_o : out std_logic;
masterStb_o : out std_logic;
masterWe_o : out std_logic;
masterAddr_o : out std_logic_vector(9 downto 0);
masterData_o : out std_logic_vector(31 downto 0);
masterData_i : in std_logic;
masterAck_i : in std_logic;
-- Slave port signals.
-- Receives frames from other ports.
slaveCyc_i : in std_logic;
slaveStb_i : in std_logic;
slaveWe_i : in std_logic;
slaveAddr_i : in std_logic_vector(9 downto 0);
slaveData_i : in std_logic_vector(31 downto 0);
slaveData_o : out std_logic;
slaveAck_o : out std_logic;
-- Address-lookup interface.
lookupStb_o : out std_logic;
lookupAddr_o : out std_logic_vector(15 downto 0);
lookupData_i : in std_logic_vector(7 downto 0);
lookupAck_i : in std_logic;
-- Physical port frame buffer interface.
readFrameEmpty_i : in std_logic;
readFrame_o : out std_logic;
readFrameRestart_o : out std_logic;
readFrameAborted_i : in std_logic;
readContentEmpty_i : in std_logic;
readContent_o : out std_logic;
readContentEnd_i : in std_logic;
readContentData_i : in std_logic_vector(31 downto 0);
writeFrameFull_i : in std_logic;
writeFrame_o : out std_logic;
writeFrameAbort_o : out std_logic;
writeContent_o : out std_logic;
writeContentData_o : out std_logic_vector(31 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for SwitchPort.
-------------------------------------------------------------------------------
architecture SwitchPortImpl of SwitchPort is
type MasterStateType is (STATE_IDLE,
STATE_WAIT_HEADER_0, STATE_READ_HEADER_0,
STATE_READ_PORT_LOOKUP,
STATE_READ_TARGET_PORT,
STATE_WAIT_TARGET_PORT,
STATE_WAIT_TARGET_WRITE,
STATE_WAIT_COMPLETE);
signal masterState : MasterStateType;
type SlaveStateType is (STATE_IDLE, STATE_SEND_ACK);
signal slaveState : SlaveStateType;
alias ftype : std_logic_vector(3 downto 0) is readContentData_i(19 downto 16);
alias tt : std_logic_vector(1 downto 0) is readContentData_i(21 downto 20);
begin
-----------------------------------------------------------------------------
-- Master interface process.
-----------------------------------------------------------------------------
Master: process(clk, areset_n)
begin
if (areset_n = '0') then
masterState <= STATE_IDLE;
lookupStb_o <= '0';
lookupAddr_o <= (others => '0');
masterCyc_o <= '0';
masterStb_o <= '0';
masterWe_o <= '0';
masterAddr_o <= (others => '0');
masterData_o <= (others => '0');
readContent_o <= '0';
readFrame_o <= '0';
readFrameRestart_o <= '0';
elsif (clk'event and clk = '1') then
readContent_o <= '0';
readFrame_o <= '0';
readFrameRestart_o <= '0';
-- REMARK: Add support for aborted frames...
case masterState is
when STATE_IDLE =>
---------------------------------------------------------------------
-- Wait for a new packet or content of a new packet.
---------------------------------------------------------------------
-- Reset bus signals.
masterCyc_o <= '0';
masterStb_o <= '0';
-- Wait for frame content to be available.
-- Use different signals to trigger the forwarding of packets depending
-- on the switch philosofy.
if (readFrameEmpty_i = '0') then
readContent_o <= '1';
masterState <= STATE_WAIT_HEADER_0;
end if;
when STATE_WAIT_HEADER_0 =>
---------------------------------------------------------------------
-- Wait for the frame buffer output to be updated.
---------------------------------------------------------------------
-- Wait for frame buffer output to be updated.
masterState <= STATE_READ_HEADER_0;
when STATE_READ_HEADER_0 =>
---------------------------------------------------------------------
-- Check the FTYPE and forward it to the maintenance port if it is a
-- maintenance packet. Otherwise, initiate an address lookup and wait
-- for the result.
---------------------------------------------------------------------
-- Check if the frame has ended.
if (readContentEnd_i = '0') then
-- The frame has not ended.
-- This word contains the header and the source id.
-- Read the tt-field to check the source and destination id size.
if (tt = "01") then
-- This frame contains 16-bit addresses.
-- Read the new content.
readContent_o <= '1';
-- Save the content of the header and destination.
masterData_o <= readContentData_i;
-- Check if this is a maintenance frame.
if (ftype = FTYPE_MAINTENANCE_CLASS) then
-- This is a maintenance frame.
-- Always route these frames to the maintenance module in the
-- switch by setting the MSB bit of the port address.
masterAddr_o <= '1' & std_logic_vector(to_unsigned(PORT_INDEX, 8)) & '0';
-- Start an access to the maintenance port.
masterState <= STATE_READ_TARGET_PORT;
else
-- This is not a maintenance frame.
-- Lookup the destination address and proceed to wait for the
-- result.
lookupStb_o <= '1';
lookupAddr_o <= readContentData_i(15 downto 0);
-- Wait for the port lookup to return a result.
masterState <= STATE_READ_PORT_LOOKUP;
end if;
else
-- Unsupported tt-value, discard the frame.
readFrame_o <= '1';
masterState <= STATE_IDLE;
end if;
else
-- End of frame.
-- The frame is too short to contain a valid frame. Discard it.
readFrame_o <= '1';
masterState <= STATE_IDLE;
end if;
when STATE_READ_PORT_LOOKUP =>
---------------------------------------------------------------------
-- Wait for the address lookup to be complete.
---------------------------------------------------------------------
-- Wait for the routing table to complete the request.
if (lookupAck_i = '1') then
-- The address lookup is complete.
-- Terminate the lookup cycle.
lookupStb_o <= '0';
-- Proceed to read the target port.
masterAddr_o <= '0' & lookupData_i & '0';
masterState <= STATE_READ_TARGET_PORT;
else
-- Wait until the address lookup is complete.
-- REMARK: Timeout here???
end if;
when STATE_READ_TARGET_PORT =>
---------------------------------------------------------------------
-- Initiate an access to the target port.
---------------------------------------------------------------------
-- Read the status of the target port using the result from the
-- lookup in the routing table.
masterCyc_o <= '1';
masterStb_o <= '1';
masterWe_o <= '0';
masterState <= STATE_WAIT_TARGET_PORT;
when STATE_WAIT_TARGET_PORT =>
---------------------------------------------------------------------
-- Wait to get access to the target port. When the port is ready
-- check if it is ready to accept a new frame. If it cannot accept a
-- new frame, terminate the access and go back and start a new one.
-- This is to free the interconnect to let other ports access it if
-- it is a shared bus. If the port is ready, initiate a write access
-- to the selected port.
---------------------------------------------------------------------
-- Wait for the target port to complete the request.
if (masterAck_i = '1') then
-- Target port has completed the request.
-- Check the status of the target port.
if (masterData_i = '0') then
-- The target port has empty buffers to receive the frame.
-- Hold the bus with cyc until the cycle is complete.
-- Write the first word of the frame to the target port.
-- The masterData_o has already been assigned.
masterCyc_o <= '1';
masterStb_o <= '1';
masterWe_o <= '1';
masterAddr_o(0) <= '1';
-- Change state to transfer the frame.
masterState <= STATE_WAIT_TARGET_WRITE;
else
-- The target port has no empty buffer to receive the frame.
-- Terminate the cycle and retry later.
masterCyc_o <= '0';
masterStb_o <= '0';
masterState <= STATE_READ_TARGET_PORT;
end if;
else
-- Target port has not completed the request.
-- Dont to anything.
end if;
when STATE_WAIT_TARGET_WRITE =>
---------------------------------------------------------------------
-- Wait for the write access to complete. When complete, write the
-- next content and update the content to the next. If the frame does
-- not have any more data ready, terminate the access but keep the
-- cycle active and proceed to wait for new data.
---------------------------------------------------------------------
-- Wait for the target port to complete the request.
-- REMARK: Remove the ack-condition, we know that the write takes one
-- cycle...
if (masterAck_i = '1') then
-- The target port is ready.
-- Check if the frame has ended.
if (readContentEnd_i = '0') then
-- The frame has not ended.
-- There are more data to transfer.
masterData_o <= readContentData_i;
readContent_o <= '1';
else
-- There are no more data to transfer.
-- Update to the next frame.
readFrame_o <= '1';
-- Tell the target port that the frame is complete.
masterWe_o <= '1';
masterAddr_o(0) <= '0';
masterData_o <= x"00000001";
-- Change state to wait for the target port to finalize the write
-- of the full frame.
masterState <= STATE_WAIT_COMPLETE;
end if;
else
-- Wait for the target port to reply.
-- Dont do anything.
end if;
when STATE_WAIT_COMPLETE =>
---------------------------------------------------------------------
-- Wait for the target port to signal that the frame has been
-- completed.
---------------------------------------------------------------------
-- Wait for the target port to complete the final request.
if (masterAck_i = '1') then
-- The target port has finalized the write of the frame.
-- Reset master bus signals.
masterCyc_o <= '0';
masterStb_o <= '0';
masterState <= STATE_IDLE;
else
-- Wait for the target port to reply.
-- REMARK: Timeout here???
end if;
when others =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- Slave interface process.
-----------------------------------------------------------------------------
-- Addr | Read | Write
-- 0 | full | abort & complete
-- 1 | full | frameData
writeContentData_o <= slaveData_i;
Slave: process(clk, areset_n)
begin
if (areset_n = '0') then
slaveState <= STATE_IDLE;
slaveData_o <= '0';
writeFrame_o <= '0';
writeFrameAbort_o <= '0';
writeContent_o <= '0';
elsif (clk'event and clk = '1') then
writeFrame_o <= '0';
writeFrameAbort_o <= '0';
writeContent_o <= '0';
case slaveState is
when STATE_IDLE =>
---------------------------------------------------------------------
-- Wait for an access from a master.
---------------------------------------------------------------------
-- Check if any cycle is active.
if ((slaveCyc_i = '1') and (slaveStb_i = '1')) then
-- Cycle is active.
-- Check if the cycle is accessing the status- or data address.
if (slaveAddr_i(0) = '0') then
-- Accessing port status address.
-- Check if writing.
if (slaveWe_i = '1') then
-- Writing the status address.
-- Update the buffering output signals according to the input
-- data.
writeFrame_o <= slaveData_i(0);
writeFrameAbort_o <= slaveData_i(1);
else
-- Reading the status address.
slaveData_o <= writeFrameFull_i;
end if;
else
-- Accessing port data address.
-- Check if writing.
if (slaveWe_i = '1') then
-- Write frame content into the frame buffer.
writeContent_o <= '1';
else
slaveData_o <= writeFrameFull_i;
end if;
end if;
-- Change state to send an ack to the master.
slaveState <= STATE_SEND_ACK;
end if;
when STATE_SEND_ACK =>
---------------------------------------------------------------------
-- Wait for acknowledge to be received by the master.
---------------------------------------------------------------------
-- Go back to the idle state and wait for a new cycle.
slaveState <= STATE_IDLE;
when others =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
null;
end case;
end if;
end process;
-- Assign the acknowledge depending on the current slave state.
slaveAck_o <= '1' when (slaveState = STATE_SEND_ACK) else '0';
end architecture;
-------------------------------------------------------------------------------
-- SwitchPortMaintenance
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for SwitchPortMaintenance.
-------------------------------------------------------------------------------
entity SwitchPortMaintenance is
generic(
SWITCH_PORTS : natural range 0 to 255;
DEVICE_IDENTITY : std_logic_vector(15 downto 0);
DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
DEVICE_REV : std_logic_vector(31 downto 0);
ASSY_IDENTITY : std_logic_vector(15 downto 0);
ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
ASSY_REV : std_logic_vector(15 downto 0));
port(
clk : in std_logic;
areset_n : in std_logic;
-- Routing table port lookup signals.
lookupStb_i : in std_logic;
lookupAddr_i : in std_logic_vector(15 downto 0);
lookupData_o : out std_logic_vector(7 downto 0);
lookupAck_o : out std_logic;
-- Master port signals.
-- Write frames to other ports.
masterCyc_o : out std_logic;
masterStb_o : out std_logic;
masterWe_o : out std_logic;
masterAddr_o : out std_logic_vector(9 downto 0);
masterData_o : out std_logic_vector(31 downto 0);
masterData_i : in std_logic;
masterAck_i : in std_logic;
-- Slave port signals.
-- Receives frames from other ports.
slaveCyc_i : in std_logic;
slaveStb_i : in std_logic;
slaveWe_i : in std_logic;
slaveAddr_i : in std_logic_vector(9 downto 0);
slaveData_i : in std_logic_vector(31 downto 0);
slaveData_o : out std_logic;
slaveAck_o : out std_logic;
-- Address-lookup interface.
lookupStb_o : out std_logic;
lookupAddr_o : out std_logic_vector(15 downto 0);
lookupData_i : in std_logic_vector(7 downto 0);
lookupAck_i : in std_logic;
-- Port common access interface.
portLinkTimeout_o : out std_logic_vector(23 downto 0);
-- Port specific access interface.
linkInitialized_i : in Array1(SWITCH_PORTS-1 downto 0);
outputPortEnable_o : out Array1(SWITCH_PORTS-1 downto 0);
inputPortEnable_o : out Array1(SWITCH_PORTS-1 downto 0);
localAckIdWrite_o : out Array1(SWITCH_PORTS-1 downto 0);
clrOutstandingAckId_o : out Array1(SWITCH_PORTS-1 downto 0);
inboundAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
outstandingAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
outboundAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
inboundAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
outstandingAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
outboundAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
-- Configuration space for implementation-defined space.
configStb_o : out std_logic;
configWe_o : out std_logic;
configAddr_o : out std_logic_vector(23 downto 0);
configData_o : out std_logic_vector(31 downto 0);
configData_i : in std_logic_vector(31 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for SwitchPort.
-------------------------------------------------------------------------------
architecture SwitchPortMaintenanceImpl of SwitchPortMaintenance is
component MemoryDualPort is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1);
port(
clkA_i : in std_logic;
enableA_i : in std_logic;
writeEnableA_i : in std_logic;
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
dataA_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
clkB_i : in std_logic;
enableB_i : in std_logic;
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
component MemorySinglePort is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1);
port(
clk_i : in std_logic;
enable_i : in std_logic;
writeEnable_i : in std_logic;
address_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
component Crc16CITT is
port(
d_i : in std_logic_vector(15 downto 0);
crc_i : in std_logic_vector(15 downto 0);
crc_o : out std_logic_vector(15 downto 0));
end component;
type MasterStateType is (STATE_IDLE,
STATE_CHECK_FRAME,
STATE_RELAY_READ_RESPONSE,
STATE_RELAY_WRITE_RESPONSE,
STATE_SEND_READ_REQUEST,
STATE_SEND_WRITE_REQUEST,
STATE_SEND_READ_RESPONSE,
STATE_SEND_WRITE_RESPONSE,
STATE_START_PORT_LOOKUP,
STATE_READ_PORT_LOOKUP,
STATE_READ_TARGET_PORT,
STATE_WAIT_TARGET_PORT,
STATE_WAIT_TARGET_WRITE,
STATE_WAIT_COMPLETE,
STATE_WAIT_SLAVE);
signal masterState : MasterStateType;
signal crc16Data : std_logic_vector(31 downto 0);
signal crc16Current : std_logic_vector(15 downto 0);
signal crc16Temp : std_logic_vector(15 downto 0);
signal crc16Next : std_logic_vector(15 downto 0);
signal configEnable : std_logic;
signal configWrite : std_logic;
signal configAddress : std_logic_vector(23 downto 0);
signal configDataWrite : std_logic_vector(31 downto 0);
signal configDataRead, configDataReadInternal : std_logic_vector(31 downto 0);
signal outboundFrameEnable : std_logic;
signal outboundFrameWrite : std_logic;
signal outboundFrameAddress : std_logic_vector(2 downto 0);
signal outboundFrameDataWrite : std_logic_vector(31 downto 0);
signal outboundFrameDataRead : std_logic_vector(31 downto 0);
signal outboundFrameLength : std_logic_vector(2 downto 0);
type SlaveStateType is (STATE_READY,
STATE_BUSY);
signal slaveState : SlaveStateType;
signal slaveAck : std_logic;
signal inboundFrameReady : std_logic;
signal inboundFramePort : std_logic_vector(7 downto 0);
signal inboundFrameLength : natural range 0 to 7;
signal inboundFrameComplete : std_logic;
signal vc : std_logic;
signal crf : std_logic;
signal prio : std_logic_vector(1 downto 0);
signal tt : std_logic_vector(1 downto 0);
signal ftype : std_logic_vector(3 downto 0);
signal destinationId : std_logic_vector(15 downto 0);
signal sourceId : std_logic_vector(15 downto 0);
signal transaction : std_logic_vector(3 downto 0);
signal size : std_logic_vector(3 downto 0);
signal srcTid : std_logic_vector(7 downto 0);
signal hopCount : std_logic_vector(7 downto 0);
signal configOffset : std_logic_vector(20 downto 0);
signal wdptr : std_logic;
signal content : std_logic_vector(63 downto 0);
-----------------------------------------------------------------------------
-- Route table access signals.
-----------------------------------------------------------------------------
signal address0 : std_logic_vector(7 downto 0);
signal address1 : std_logic_vector(7 downto 0);
signal address2 : std_logic_vector(7 downto 0);
signal address3 : std_logic_vector(7 downto 0);
signal lookupEnable : std_logic;
signal lookupAddress : std_logic_vector(10 downto 0);
signal lookupData : std_logic_vector(7 downto 0);
signal lookupAck : std_logic;
signal routeTableEnable : std_logic;
signal routeTableWrite : std_logic;
signal routeTableAddress : std_logic_vector(10 downto 0);
signal routeTablePortWrite : std_logic_vector(7 downto 0);
signal routeTablePortRead : std_logic_vector(7 downto 0);
signal routeTablePortDefault : std_logic_vector(7 downto 0);
-----------------------------------------------------------------------------
-- Configuration space signals.
-----------------------------------------------------------------------------
signal discovered : std_logic;
signal hostBaseDeviceIdLocked : std_logic;
signal hostBaseDeviceId : std_logic_vector(15 downto 0);
signal componentTag : std_logic_vector(31 downto 0);
signal portLinkTimeout : std_logic_vector(23 downto 0);
signal outputPortEnable : Array1(SWITCH_PORTS-1 downto 0);
signal inputPortEnable : Array1(SWITCH_PORTS-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Memory to contain the outbound frame.
-----------------------------------------------------------------------------
OutboundFrameMemory: MemorySinglePort
generic map(
ADDRESS_WIDTH=>3, DATA_WIDTH=>32)
port map(
clk_i=>clk,
enable_i=>outboundFrameEnable, writeEnable_i=>outboundFrameWrite,
address_i=>outboundFrameAddress,
data_i=>outboundFrameDataWrite, data_o=>outboundFrameDataRead);
-----------------------------------------------------------------------------
-- CRC generation for outbound frames.
-----------------------------------------------------------------------------
crc16Data <= outboundFrameDataWrite;
-- REMARK: Insert FFs here to make the critical path shorter...
Crc16High: Crc16CITT
port map(
d_i=>crc16Data(31 downto 16), crc_i=>crc16Current, crc_o=>crc16Temp);
Crc16Low: Crc16CITT
port map(
d_i=>crc16Data(15 downto 0), crc_i=>crc16Temp, crc_o=>crc16Next);
-----------------------------------------------------------------------------
-- Master interface process.
-----------------------------------------------------------------------------
Master: process(clk, areset_n)
begin
if (areset_n = '0') then
masterState <= STATE_IDLE;
lookupStb_o <= '0';
lookupAddr_o <= (others => '0');
masterCyc_o <= '0';
masterStb_o <= '0';
masterWe_o <= '0';
masterAddr_o <= (others => '0');
masterData_o <= (others => '0');
configEnable <= '0';
configWrite <= '0';
configAddress <= (others => '0');
configDataWrite <= (others => '0');
outboundFrameEnable <= '0';
outboundFrameWrite <= '0';
outboundFrameAddress <= (others=>'0');
outboundFrameDataWrite <= (others=>'0');
outboundFrameLength <= (others=>'0');
inboundFrameComplete <= '0';
elsif (clk'event and clk = '1') then
configEnable <= '0';
configWrite <= '0';
inboundFrameComplete <= '0';
case masterState is
when STATE_IDLE =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
-- Wait for a full frame to be available.
if (inboundFrameReady = '1') then
if (inboundFrameLength > 3) then
masterState <= STATE_CHECK_FRAME;
else
-- Frame is too short.
-- REMARK: Discard the frame.
end if;
end if;
when STATE_CHECK_FRAME =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
-- Check if the frame has 16-bit addresses and is a maintenance frame.
if (tt = "01") and (ftype = FTYPE_MAINTENANCE_CLASS) then
-- Maintenance class frame and 16-bit addresses.
-- Check the frame type.
case transaction is
when "0000" =>
---------------------------------------------------------------
-- Maintenance read request.
---------------------------------------------------------------
-- Check if the frame is for us.
if (hopCount = x"00") then
-- This frame is for us.
configEnable <= '1';
configWrite <= '0';
configAddress <= configOffset & wdptr & "00";
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= (others=>'0');
outboundFrameDataWrite <= "000000" & vc & crf & prio & tt & ftype & sourceId;
crc16Current <= x"ffff";
masterState <= STATE_SEND_READ_RESPONSE;
else
-- This frame is not for us.
-- Decrement hop_count and relay.
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= (others=>'0');
outboundFrameDataWrite <= "000000" & vc & crf & prio & tt & ftype & destinationId;
crc16Current <= x"ffff";
masterState <= STATE_SEND_READ_REQUEST;
end if;
when "0001" =>
---------------------------------------------------------------
-- Maintenance write request.
---------------------------------------------------------------
-- Check if the frame is for us.
if (hopCount = x"00") then
-- This frame is for us.
configEnable <= '1';
configWrite <= '1';
configAddress <= configOffset & wdptr & "00";
if (wdptr = '0') then
configDataWrite <= content(63 downto 32);
else
configDataWrite <= content(31 downto 0);
end if;
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= (others=>'0');
outboundFrameDataWrite <= "000000" & vc & crf & prio & tt & ftype & sourceId;
crc16Current <= x"ffff";
masterState <= STATE_SEND_WRITE_RESPONSE;
else
-- This frame is not for us.
-- Decrement hop_count and relay.
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= (others=>'0');
outboundFrameDataWrite <= "000000" & vc & crf & prio & tt & ftype & destinationId;
crc16Current <= x"ffff";
masterState <= STATE_SEND_WRITE_REQUEST;
end if;
when "0010" =>
---------------------------------------------------------------
-- Maintenance read response frame.
---------------------------------------------------------------
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= (others=>'0');
outboundFrameDataWrite <= "000000" & vc & crf & prio & tt & ftype & destinationId;
crc16Current <= x"ffff";
-- Relay frame.
masterState <= STATE_RELAY_READ_RESPONSE;
when "0011" =>
---------------------------------------------------------------
-- Maintenance write response frame.
---------------------------------------------------------------
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= (others=>'0');
outboundFrameDataWrite <= "000000" & vc & crf & prio & tt & ftype & destinationId;
crc16Current <= x"ffff";
-- Relay frame.
masterState <= STATE_RELAY_WRITE_RESPONSE;
when "0100" =>
---------------------------------------------------------------
-- Maintenance port write frame.
---------------------------------------------------------------
-- REMARK: Support these???
when others =>
---------------------------------------------------------------
-- Unsupported frame type.
---------------------------------------------------------------
-- REMARK: Support these???
end case;
else
-- Non-maintenance class frame or unsupported address type.
-- REMARK: These should not end up here... discard them???
end if;
when STATE_RELAY_READ_RESPONSE =>
---------------------------------------------------------------------
-- A maintenance response has been received. It should be relayed as
-- is using the destinationId.
---------------------------------------------------------------------
case to_integer(unsigned(outboundFrameAddress)) is
when 0 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite <= sourceId & transaction & size & srcTid;
crc16Current <= crc16Next;
when 1 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite <= hopCount & configOffset & wdptr & "00";
crc16Current <= crc16Next;
when 2 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite <= content(63 downto 32);
crc16Current <= crc16Next;
when 3 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite <= content(31 downto 0);
crc16Current <= crc16Next;
when 4 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite(31 downto 16) <= crc16Next;
outboundFrameDataWrite(15 downto 0) <= x"0000";
when others =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '0';
outboundFrameAddress <= (others=>'0');
outboundFrameLength <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
masterState <= STATE_START_PORT_LOOKUP;
end case;
when STATE_RELAY_WRITE_RESPONSE =>
---------------------------------------------------------------------
-- A maintenance response has been received. It should be relayed as
-- is using the destinationId.
---------------------------------------------------------------------
case to_integer(unsigned(outboundFrameAddress)) is
when 0 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite <= sourceId & transaction & size & srcTid;
crc16Current <= crc16Next;
when 1 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite <= hopCount & configOffset & wdptr & "00";
crc16Current <= crc16Next;
when 2 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite(31 downto 16) <= crc16Next;
outboundFrameDataWrite(15 downto 0) <= x"0000";
when others =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '0';
outboundFrameAddress <= (others=>'0');
outboundFrameLength <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
masterState <= STATE_START_PORT_LOOKUP;
end case;
when STATE_SEND_READ_REQUEST =>
---------------------------------------------------------------------
-- A read request has been received but the hopcount is larger than
-- zero. Decrement the hopcount, recalculate the crc and relay the
-- frame using the destinationId.
---------------------------------------------------------------------
case to_integer(unsigned(outboundFrameAddress)) is
when 0 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite <= sourceId & transaction & size & srcTid;
crc16Current <= crc16Next;
when 1 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite <= std_logic_vector(unsigned(hopCount) - 1) & configOffset & wdptr & "00";
crc16Current <= crc16Next;
when 2 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite(31 downto 16) <= crc16Next;
outboundFrameDataWrite(15 downto 0) <= x"0000";
when others =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '0';
outboundFrameAddress <= (others=>'0');
outboundFrameLength <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
masterState <= STATE_START_PORT_LOOKUP;
end case;
when STATE_SEND_WRITE_REQUEST =>
---------------------------------------------------------------------
-- A write request has been received but the hopcount is larger than
-- zero. Decrement the hopcount, recalculate the crc and relay the
-- frame using the destinationId.
---------------------------------------------------------------------
case to_integer(unsigned(outboundFrameAddress)) is
when 0 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite <= sourceId & transaction & size & srcTid;
crc16Current <= crc16Next;
when 1 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite <= std_logic_vector(unsigned(hopCount) - 1) & configOffset & wdptr & "00";
crc16Current <= crc16Next;
when 2 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite <= content(63 downto 32);
crc16Current <= crc16Next;
when 3 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite <= content(31 downto 0);
crc16Current <= crc16Next;
when 4 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite(31 downto 16) <= crc16Next;
outboundFrameDataWrite(15 downto 0) <= x"0000";
when others =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '0';
outboundFrameAddress <= (others=>'0');
outboundFrameLength <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
masterState <= STATE_START_PORT_LOOKUP;
end case;
when STATE_SEND_READ_RESPONSE =>
---------------------------------------------------------------------
-- A read request has been received with a hopcount that are zero.
-- Create a read response, calculate crc and write it to the port it
-- came from.
---------------------------------------------------------------------
case to_integer(unsigned(outboundFrameAddress)) is
when 0 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite <= destinationId & "0010" & "0000" & srcTid;
crc16Current <= crc16Next;
when 1 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite <= x"ff" & x"000000";
crc16Current <= crc16Next;
when 2 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
if (wdptr = '1') then
outboundFrameDataWrite <= (others => '0');
else
outboundFrameDataWrite <= configDataRead(31 downto 0);
end if;
crc16Current <= crc16Next;
when 3 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
if (wdptr = '1') then
outboundFrameDataWrite <= configDataRead(31 downto 0);
else
outboundFrameDataWrite <= (others => '0');
end if;
crc16Current <= crc16Next;
when 4 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite(31 downto 16) <= crc16Next;
outboundFrameDataWrite(15 downto 0) <= x"0000";
when others =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '0';
outboundFrameAddress <= (others=>'0');
outboundFrameLength <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
masterAddr_o <= '0' & inboundFramePort & '0';
masterState <= STATE_READ_TARGET_PORT;
end case;
when STATE_SEND_WRITE_RESPONSE =>
---------------------------------------------------------------------
-- A write request has been received with a hopcount that are zero.
-- Create a write response, calculate crc and write it to the port it
-- came from.
---------------------------------------------------------------------
case to_integer(unsigned(outboundFrameAddress)) is
when 0 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite <= destinationId & "0011" & "0000" & srcTid;
crc16Current <= crc16Next;
when 1 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite <= x"ff" & x"000000";
crc16Current <= crc16Next;
when 2 =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '1';
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
outboundFrameDataWrite(31 downto 16) <= crc16Next;
outboundFrameDataWrite(15 downto 0) <= x"0000";
when others =>
outboundFrameEnable <= '1';
outboundFrameWrite <= '0';
outboundFrameAddress <= (others=>'0');
outboundFrameLength <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
masterAddr_o <= '0' & inboundFramePort & '0';
masterState <= STATE_READ_TARGET_PORT;
end case;
when STATE_START_PORT_LOOKUP =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
-- Initiate a port-lookup of the destination address.
lookupStb_o <= '1';
lookupAddr_o <= destinationId;
masterState <= STATE_READ_PORT_LOOKUP;
when STATE_READ_PORT_LOOKUP =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
-- Wait for the routing table to complete the request.
if (lookupAck_i = '1') then
-- The address lookup is complete.
-- Terminate the lookup cycle.
lookupStb_o <= '0';
-- Wait for the target port to reply.
masterAddr_o <= '0' & lookupData_i & '0';
masterState <= STATE_READ_TARGET_PORT;
else
-- Wait until the address lookup is complete.
-- REMARK: Timeout here???
end if;
when STATE_READ_TARGET_PORT =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
-- Read the status of the target port using the result from the
-- lookup in the routing table.
masterCyc_o <= '1';
masterStb_o <= '1';
masterWe_o <= '0';
masterState <= STATE_WAIT_TARGET_PORT;
when STATE_WAIT_TARGET_PORT =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
-- Wait for the target port to complete the request.
if (masterAck_i = '1') then
if (masterData_i = '0') then
-- The target port has empty buffers to receive the frame.
-- Write the first word of the frame to the target port.
-- The masterData_o has already been assigned.
masterCyc_o <= '1';
masterStb_o <= '1';
masterWe_o <= '1';
masterAddr_o(0) <= '1';
-- Read the first word in the frame and update the frame address.
masterData_o <= outboundFrameDataRead;
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
-- Change state to transfer the frame.
masterState <= STATE_WAIT_TARGET_WRITE;
else
-- The target port has no empty buffer to receive the frame.
-- Terminate the cycle and retry later.
masterCyc_o <= '0';
masterStb_o <= '0';
masterState <= STATE_READ_TARGET_PORT;
end if;
else
-- Wait for the target port to reply.
-- REMARK: Timeout here???
end if;
when STATE_WAIT_TARGET_WRITE =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
-- Wait for the target port to complete the request.
if (masterAck_i = '1') then
-- The target port is ready.
-- Check if the frame has ended.
if (outboundFrameLength /= outboundFrameAddress) then
-- The frame has not ended.
-- There are more data to transfer.
masterData_o <= outboundFrameDataRead;
outboundFrameAddress <= std_logic_vector(unsigned(outboundFrameAddress) + 1);
else
-- There are no more data to transfer.
-- Tell the target port that the frame is complete.
masterWe_o <= '1';
masterAddr_o(0) <= '0';
masterData_o <= x"00000001";
outboundFrameAddress <= (others=>'0');
-- Change state to wait for the target port to finalize the write
-- of the full frame.
masterState <= STATE_WAIT_COMPLETE;
end if;
else
-- Wait for the target port to reply.
-- REMARK: Timeout here???
end if;
when STATE_WAIT_COMPLETE =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
-- Wait for the target port to complete the final request.
if (masterAck_i = '1') then
-- The target port has finalized the write of the frame.
masterCyc_o <= '0';
masterStb_o <= '0';
masterState <= STATE_WAIT_SLAVE;
-- Indicate the frame has been read.
inboundFrameComplete <= '1';
else
-- Wait for the target port to reply.
-- REMARK: Timeout here???
end if;
when STATE_WAIT_SLAVE =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
masterState <= STATE_IDLE;
when others =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- Slave interface process.
-----------------------------------------------------------------------------
-- Addr | Read | Write
-- 0 | full | abort & complete
-- 1 | full | frameData
Slave: process(clk, areset_n)
begin
if (areset_n = '0') then
slaveState <= STATE_READY;
slaveData_o <= '0';
slaveAck <= '0';
vc <= '0';
crf <= '0';
prio <= (others=>'0');
tt <= (others=>'0');
ftype <= (others=>'0');
destinationId <= (others=>'0');
sourceId <= (others=>'0');
transaction <= (others=>'0');
size <= (others=>'0');
srcTid <= (others=>'0');
hopCount <= (others=>'0');
configOffset <= (others=>'0');
wdptr <= '0';
content <= (others=>'0');
inboundFrameReady <= '0';
inboundFramePort <= (others => '0');
inboundFrameLength <= 0;
elsif (clk'event and clk = '1') then
slaveAck <= '0';
case slaveState is
when STATE_READY =>
---------------------------------------------------------------------
-- Ready to receive a new frame.
---------------------------------------------------------------------
-- Check if any cycle is active.
if ((slaveCyc_i = '1') and (slaveStb_i = '1') and (slaveAck = '0')) then
-- Cycle is active.
-- Check if writing.
if (slaveWe_i = '1') then
-- Writing request.
-- Check if the cycle is accessing the status- or data address.
if (slaveAddr_i(0) = '0') then
-- Writing to port status address.
if (slaveData_i(0) = '1') and (slaveData_i(1) = '0') then
-- A frame has been written.
-- Indicate the frame is ready for processing.
-- The slave address contains the number of the accessing port.
inboundFrameReady <= '1';
inboundFramePort <= slaveAddr_i(8 downto 1);
-- Change state until the frame has been processed.
slaveState <= STATE_BUSY;
else
-- The frame has been aborted.
-- Reset the received frame length.
inboundFrameLength <= 0;
end if;
else
-- Write frame content into the frame buffer.
-- Check which frame index that is written.
case inboundFrameLength is
when 0 =>
vc <= slaveData_i(25);
crf <= slaveData_i(24);
prio <= slaveData_i(23 downto 22);
tt <= slaveData_i(21 downto 20);
ftype <= slaveData_i(19 downto 16);
destinationId <= slaveData_i(15 downto 0);
inboundFrameLength <= inboundFrameLength + 1;
when 1 =>
sourceId <= slaveData_i(31 downto 16);
transaction <= slaveData_i(15 downto 12);
size <= slaveData_i(11 downto 8);
srcTid <= slaveData_i(7 downto 0);
inboundFrameLength <= inboundFrameLength + 1;
when 2 =>
hopCount <= slaveData_i(31 downto 24);
configOffset <= slaveData_i(23 downto 3);
wdptr <= slaveData_i(2);
inboundFrameLength <= inboundFrameLength + 1;
when 3 =>
-- Note that crc will be assigned here if there are no
-- content in the frame.
content(63 downto 32) <= slaveData_i;
inboundFrameLength <= inboundFrameLength + 1;
when 4 =>
content(31 downto 0) <= slaveData_i;
inboundFrameLength <= inboundFrameLength + 1;
when others =>
-- Dont support longer frames.
-- REMARK: Add support for longer frames??? Especially
-- received frames that only should be routed...
end case;
end if;
-- Send acknowledge.
slaveAck <= '1';
else
-- Reading request.
-- Reading the status address.
-- Always indicate that we are ready to accept a new frame.
slaveData_o <= '0';
-- Send acknowledge.
slaveAck <= '1';
end if;
else
-- No cycle is active.
end if;
when STATE_BUSY =>
---------------------------------------------------------------------
-- Waiting for a received frame to be processed.
---------------------------------------------------------------------
-- Check if any cycle is active.
if ((slaveCyc_i = '1') and (slaveStb_i = '1') and (slaveAck = '0')) then
-- Cycle is active.
-- Check if writing.
if (slaveWe_i = '1') then
-- Writing.
-- Dont do anything.
-- Send acknowledge.
slaveAck <= '1';
else
-- Read port data address.
-- Reading the status address.
-- Always indicate that we are busy.
slaveData_o <= '1';
-- Send acknowledge.
slaveAck <= '1';
end if;
else
-- No cycle is active.
-- Dont do anything.
end if;
-- Check if the master process has processed the received frame.
if (inboundFrameComplete = '1') then
-- The master has processed the frame.
inboundFrameReady <= '0';
inboundFrameLength <= 0;
slaveState <= STATE_READY;
else
-- The master is not ready yet.
-- Dont do anything.
end if;
when others =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
null;
end case;
end if;
end process;
slaveAck_o <= slaveAck;
-----------------------------------------------------------------------------
-- Logic implementing the routing table access.
-----------------------------------------------------------------------------
-- Lookup interface port memory signals.
lookupEnable <= '1' when (lookupStb_i = '1') and (lookupAddr_i(15 downto 11) = "00000") else '0';
lookupAddress <= lookupAddr_i(10 downto 0);
lookupData_o <= lookupData when (lookupEnable = '1') else routeTablePortDefault;
lookupAck_o <= lookupAck;
LookupProcess: process(clk, areset_n)
begin
if (areset_n = '0') then
lookupAck <= '0';
elsif (clk'event and clk = '1') then
if ((lookupStb_i = '1') and (lookupAck = '0')) then
lookupAck <= '1';
else
lookupAck <= '0';
end if;
end if;
end process;
-- Dual port memory containing the routing table.
RoutingTable: MemoryDualPort
generic map(
ADDRESS_WIDTH=>11, DATA_WIDTH=>8)
port map(
clkA_i=>clk, enableA_i=>routeTableEnable, writeEnableA_i=>routeTableWrite,
addressA_i=>routeTableAddress,
dataA_i=>routeTablePortWrite, dataA_o=>routeTablePortRead,
clkB_i=>clk, enableB_i=>lookupEnable,
addressB_i=>lookupAddress, dataB_o=>lookupData);
-----------------------------------------------------------------------------
-- Configuration memory.
-----------------------------------------------------------------------------
portLinkTimeout_o <= portLinkTimeout;
outputPortEnable_o <= outputPortEnable;
inputPortEnable_o <= inputPortEnable;
configStb_o <= '1' when ((configEnable = '1') and (configAddress(23 downto 16) /= x"00")) else '0';
configWe_o <= configWrite;
configAddr_o <= configAddress;
configData_o <= configDataWrite;
configDataRead <= configData_i when (configAddress(23 downto 16) /= x"00") else
configDataReadInternal;
ConfigMemory: process(areset_n, clk)
begin
if (areset_n = '0') then
configDataReadInternal <= (others => '0');
routeTableEnable <= '1';
routeTableWrite <= '0';
routeTableAddress <= (others => '0');
routeTablePortWrite <= (others => '0');
routeTablePortDefault <= (others => '0');
discovered <= '0';
hostBaseDeviceIdLocked <= '0';
hostBaseDeviceId <= (others => '1');
componentTag <= (others => '0');
portLinkTimeout <= (others => '1');
-- REMARK: These should be set to zero when a port gets initialized...
outputPortEnable <= (others => '0');
inputPortEnable <= (others => '0');
localAckIdWrite_o <= (others => '0');
elsif (clk'event and clk = '1') then
routeTableWrite <= '0';
localAckIdWrite_o <= (others => '0');
if (configEnable = '1') then
-- Check if the access is into implementation defined space or if the
-- access should be handled here.
if (configAddress(23 downto 16) /= x"00") then
-- Accessing implementation defined space.
-- Make an external access and return the resonse.
configDataReadInternal <= (others=>'0');
else
-- Access should be handled here.
case (configAddress) is
when x"000000" =>
-----------------------------------------------------------------
-- Device Identity CAR. Read-only.
-----------------------------------------------------------------
configDataReadInternal(31 downto 16) <= DEVICE_IDENTITY;
configDataReadInternal(15 downto 0) <= DEVICE_VENDOR_IDENTITY;
when x"000004" =>
-----------------------------------------------------------------
-- Device Information CAR. Read-only.
-----------------------------------------------------------------
configDataReadInternal(31 downto 0) <= DEVICE_REV;
when x"000008" =>
-----------------------------------------------------------------
-- Assembly Identity CAR. Read-only.
-----------------------------------------------------------------
configDataReadInternal(31 downto 16) <= ASSY_IDENTITY;
configDataReadInternal(15 downto 0) <= ASSY_VENDOR_IDENTITY;
when x"00000c" =>
-----------------------------------------------------------------
-- Assembly Informaiton CAR. Read-only.
-----------------------------------------------------------------
configDataReadInternal(31 downto 16) <= ASSY_REV;
configDataReadInternal(15 downto 0) <= x"0100";
when x"000010" =>
-----------------------------------------------------------------
-- Processing Element Features CAR. Read-only.
-----------------------------------------------------------------
-- Bridge.
configDataReadInternal(31) <= '0';
-- Memory.
configDataReadInternal(30) <= '0';
-- Processor.
configDataReadInternal(29) <= '0';
-- Switch.
configDataReadInternal(28) <= '1';
-- Reserved.
configDataReadInternal(27 downto 10) <= (others => '0');
-- Extended route table configuration support.
configDataReadInternal(9) <= '0';
-- Standard route table configuration support.
configDataReadInternal(8) <= '1';
-- Reserved.
configDataReadInternal(7 downto 5) <= (others => '0');
-- Common transport large system support.
configDataReadInternal(4) <= '1';
-- Extended features.
configDataReadInternal(3) <= '1';
-- Extended addressing support.
-- Not a processing element.
configDataReadInternal(2 downto 0) <= "000";
when x"000014" =>
-----------------------------------------------------------------
-- Switch Port Information CAR. Read-only.
-----------------------------------------------------------------
-- Reserved.
configDataReadInternal(31 downto 16) <= (others => '0');
-- PortTotal.
configDataReadInternal(15 downto 8) <=
std_logic_vector(to_unsigned(SWITCH_PORTS, 8));
-- PortNumber.
configDataReadInternal(7 downto 0) <= inboundFramePort;
when x"000034" =>
-----------------------------------------------------------------
-- Switch Route Table Destination ID Limit CAR.
-----------------------------------------------------------------
-- Max_destId.
-- Support 2048 addresses.
configDataReadInternal(15 downto 0) <= x"0800";
when x"000068" =>
-----------------------------------------------------------------
-- Host Base Device ID Lock CSR.
-----------------------------------------------------------------
if (configWrite = '1') then
-- Check if this field has been written before.
if (hostBaseDeviceIdLocked = '0') then
-- The field has not been written.
-- Lock the field and set the host base device id.
hostBaseDeviceIdLocked <= '1';
hostBaseDeviceId <= configDataWrite(15 downto 0);
else
-- The field has been written.
-- Check if the written data is the same as the stored.
if (hostBaseDeviceId = configDataWrite(15 downto 0)) then
-- Same as stored, reset the value to its initial value.
hostBaseDeviceIdLocked <= '0';
hostBaseDeviceId <= (others => '1');
else
-- Not writing the same as the stored value.
-- Ignore the write.
end if;
end if;
end if;
configDataReadInternal(31 downto 16) <= (others => '0');
configDataReadInternal(15 downto 0) <= hostBaseDeviceId;
when x"00006c" =>
-----------------------------------------------------------------
-- Component TAG CSR.
-----------------------------------------------------------------
if (configWrite = '1') then
componentTag <= configDataWrite;
end if;
configDataReadInternal <= componentTag;
when x"000070" =>
-----------------------------------------------------------------
-- Standard Route Configuration Destination ID Select CSR.
-----------------------------------------------------------------
if (configWrite = '1') then
-- Write the address to access the routing table.
routeTableAddress <= configDataWrite(10 downto 0);
end if;
configDataReadInternal(31 downto 11) <= (others => '0');
configDataReadInternal(10 downto 0) <= routeTableAddress;
when x"000074" =>
-----------------------------------------------------------------
-- Standard Route Configuration Port Select CSR.
-----------------------------------------------------------------
if (configWrite = '1') then
-- Write the port information for the address selected by the
-- above register.
routeTableWrite <= '1';
routeTablePortWrite <= configDataWrite(7 downto 0);
end if;
configDataReadInternal(31 downto 8) <= (others => '0');
configDataReadInternal(7 downto 0) <= routeTablePortRead;
when x"000078" =>
-----------------------------------------------------------------
-- Standard Route Default Port CSR.
-----------------------------------------------------------------
if (configWrite = '1') then
-- Write the default route device id.
routeTablePortDefault <= configDataWrite(7 downto 0);
end if;
configDataReadInternal(31 downto 8) <= (others => '0');
configDataReadInternal(7 downto 0) <= routeTablePortDefault;
when x"000100" =>
-----------------------------------------------------------------
-- Extended features. LP-Serial Register Block Header.
-----------------------------------------------------------------
-- One feature only, 0x0003=Generic End Point Free Device.
configDataReadInternal(31 downto 16) <= x"0000";
configDataReadInternal(15 downto 0) <= x"0003";
when x"000120" =>
-----------------------------------------------------------------
-- Port Link Timeout Control CSR.
-----------------------------------------------------------------
if (configWrite = '1') then
portLinkTimeout <= configDataWrite(31 downto 8);
end if;
configDataReadInternal(31 downto 8) <= portLinkTimeout;
configDataReadInternal(7 downto 0) <= x"00";
when x"00013c" =>
-----------------------------------------------------------------
-- Port General Control CSR.
-----------------------------------------------------------------
if (configWrite = '1') then
discovered <= configDataWrite(29);
end if;
configDataReadInternal(31 downto 30) <= "00";
configDataReadInternal(29) <= discovered;
configDataReadInternal(28 downto 0) <= (others => '0');
when others =>
-----------------------------------------------------------------
-- Other port specific registers.
-----------------------------------------------------------------
-- Make sure the output is always set to something.
configDataReadInternal <= (others=>'0');
-- Iterate through all active ports.
for portIndex in 0 to SWITCH_PORTS-1 loop
if(unsigned(configAddress) = (x"000148" + (x"000020"*portIndex))) then
-----------------------------------------------------------------
-- Port N Local ackID CSR.
-----------------------------------------------------------------
if (configWrite = '1') then
localAckIdWrite_o(portIndex) <= '1';
clrOutstandingAckId_o(portIndex) <= configDataWrite(31);
inboundAckId_o(portIndex) <= configDataWrite(28 downto 24);
outstandingAckId_o(portIndex) <= configDataWrite(12 downto 8);
outboundAckId_o(portIndex) <= configDataWrite(4 downto 0);
end if;
configDataReadInternal(31 downto 29) <= (others => '0');
configDataReadInternal(28 downto 24) <= inboundAckId_i(portIndex);
configDataReadInternal(23 downto 13) <= (others => '0');
configDataReadInternal(12 downto 8) <= outstandingAckId_i(portIndex);
configDataReadInternal(7 downto 5) <= (others => '0');
configDataReadInternal(4 downto 0) <= outboundAckId_i(portIndex);
elsif(unsigned(configAddress) = (x"000154" + (x"000020"*portIndex))) then
-----------------------------------------------------------------
-- Port N Control 2 CSR.
-----------------------------------------------------------------
configDataReadInternal <= (others => '0');
elsif(unsigned(configAddress) = (x"000158" + (x"000020"*portIndex))) then
-----------------------------------------------------------------
-- Port N Error and Status CSR.
-----------------------------------------------------------------
-- Idle Sequence 2 Support.
configDataReadInternal(31) <= '0';
-- Idle Sequence 2 Enable.
configDataReadInternal(30) <= '0';
-- Idle Sequence.
configDataReadInternal(29) <= '0';
-- Reserved.
configDataReadInternal(28) <= '0';
-- Flow Control Mode.
configDataReadInternal(27) <= '0';
-- Reserved.
configDataReadInternal(26 downto 21) <= (others => '0');
-- Output retry-encountered.
configDataReadInternal(20) <= '0';
-- Output retried.
configDataReadInternal(19) <= '0';
-- Output retried-stopped.
configDataReadInternal(18) <= '0';
-- Output error-encountered.
configDataReadInternal(17) <= '0';
-- Output error-stopped.
configDataReadInternal(16) <= '0';
-- Reserved.
configDataReadInternal(15 downto 11) <= (others => '0');
-- Input retry-stopped.
configDataReadInternal(10) <= '0';
-- Input error-encountered.
configDataReadInternal(9) <= '0';
-- Input error-stopped.
configDataReadInternal(8) <= '0';
-- Reserved.
configDataReadInternal(7 downto 5) <= (others => '0');
-- Port-write pending.
configDataReadInternal(4) <= '0';
-- Port unavailable.
configDataReadInternal(3) <= '0';
-- Port error.
configDataReadInternal(2) <= '0';
-- Port OK.
configDataReadInternal(1) <= linkInitialized_i(portIndex);
-- Port uninitialized.
configDataReadInternal(0) <= not linkInitialized_i(portIndex);
elsif(unsigned(configAddress) = (x"00015c" + (x"000020"*portIndex))) then
-----------------------------------------------------------------
-- Port N Control CSR.
-----------------------------------------------------------------
-- Port Width Support.
configDataReadInternal(31 downto 30) <= (others=>'0');
-- Initialized Port Width.
configDataReadInternal(29 downto 27) <= (others=>'0');
-- Port Width Override.
configDataReadInternal(26 downto 24) <= (others=>'0');
-- Port disable.
configDataReadInternal(23) <= '0';
-- Output Port Enable.
if (configWrite = '1') then
outputPortEnable(portIndex) <= configDataWrite(22);
end if;
configDataReadInternal(22) <= outputPortEnable(portIndex);
-- Input Port Enable.
if (configWrite = '1') then
inputPortEnable(portIndex) <= configDataWrite(21);
end if;
configDataReadInternal(21) <= inputPortEnable(portIndex);
-- Error Checking Disabled.
configDataReadInternal(20) <= '0';
-- Multicast-event Participant.
configDataReadInternal(19) <= '0';
-- Reserved.
configDataReadInternal(18) <= '0';
-- Enumeration Boundry.
configDataReadInternal(17) <= '0';
-- Reserved.
configDataReadInternal(16) <= '0';
-- Extended Port Width Override.
configDataReadInternal(15 downto 14) <= (others=>'0');
-- Extended Port Width Support.
configDataReadInternal(13 downto 12) <= (others=>'0');
-- Implementation defined.
configDataReadInternal(11 downto 4) <= (others=>'0');
-- Reserved.
configDataReadInternal(3 downto 1) <= (others=>'0');
-- Port Type.
configDataReadInternal(0) <= '1';
end if;
end loop;
end case;
end if;
else
-- Config memory not enabled.
end if;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
entity RouteTableInterconnect is
generic(
WIDTH : natural range 1 to 256 := 8);
port(
clk : in std_logic;
areset_n : in std_logic;
stb_i : in Array1(WIDTH-1 downto 0);
addr_i : in Array16(WIDTH-1 downto 0);
dataM_o : out Array8(WIDTH-1 downto 0);
ack_o : out Array1(WIDTH-1 downto 0);
stb_o : out std_logic;
addr_o : out std_logic_vector(15 downto 0);
dataS_i : in std_logic_vector(7 downto 0);
ack_i : in std_logic);
end entity;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
architecture RouteTableInterconnectImpl of RouteTableInterconnect is
signal activeCycle : std_logic;
signal selectedMaster : natural range 0 to WIDTH-1;
begin
-----------------------------------------------------------------------------
-- Arbitration.
-----------------------------------------------------------------------------
Arbiter: process(areset_n, clk)
begin
if (areset_n = '0') then
activeCycle <= '0';
selectedMaster <= 0;
elsif (clk'event and clk = '1') then
if (activeCycle = '0') then
for i in 0 to WIDTH-1 loop
if (stb_i(i) = '1') then
activeCycle <= '1';
selectedMaster <= i;
end if;
end loop;
else
if (stb_i(selectedMaster) = '0') then
activeCycle <= '0';
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Interconnection.
-----------------------------------------------------------------------------
stb_o <= stb_i(selectedMaster);
addr_o <= addr_i(selectedMaster);
Interconnect: for i in 0 to WIDTH-1 generate
dataM_o(i) <= dataS_i;
ack_o(i) <= ack_i when (selectedMaster = i) else '0';
end generate;
end architecture;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
entity SwitchPortInterconnect is
generic(
WIDTH : natural range 1 to 256 := 8);
port(
clk : in std_logic;
areset_n : in std_logic;
masterCyc_i : in Array1(WIDTH-1 downto 0);
masterStb_i : in Array1(WIDTH-1 downto 0);
masterWe_i : in Array1(WIDTH-1 downto 0);
masterAddr_i : in Array10(WIDTH-1 downto 0);
masterData_i : in Array32(WIDTH-1 downto 0);
masterData_o : out Array1(WIDTH-1 downto 0);
masterAck_o : out Array1(WIDTH-1 downto 0);
slaveCyc_o : out Array1(WIDTH-1 downto 0);
slaveStb_o : out Array1(WIDTH-1 downto 0);
slaveWe_o : out Array1(WIDTH-1 downto 0);
slaveAddr_o : out Array10(WIDTH-1 downto 0);
slaveData_o : out Array32(WIDTH-1 downto 0);
slaveData_i : in Array1(WIDTH-1 downto 0);
slaveAck_i : in Array1(WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
architecture SwitchPortInterconnectImpl of SwitchPortInterconnect is
--component ChipscopeIcon1 is
-- port (
-- CONTROL0 : inout STD_LOGIC_VECTOR ( 35 downto 0 )
-- );
--end component;
--component ChipscopeIlaWb is
-- port (
-- CLK : in STD_LOGIC := 'X';
-- TRIG0 : in STD_LOGIC_VECTOR ( 46 downto 0);
-- CONTROL : inout STD_LOGIC_VECTOR ( 35 downto 0 )
-- );
--end component;
--signal control : std_logic_vector(35 downto 0);
--signal trig : std_logic_vector(46 downto 0);
signal activeCycle : std_logic;
signal selectedMaster : natural range 0 to WIDTH-1;
signal selectedSlave : natural range 0 to WIDTH-1;
begin
-----------------------------------------------------------------------------
-- Arbitration process.
-----------------------------------------------------------------------------
RoundRobinArbiter: process(areset_n, clk)
variable index : natural range 0 to WIDTH-1;
begin
if (areset_n = '0') then
activeCycle <= '0';
selectedMaster <= 0;
elsif (clk'event and clk = '1') then
-- Check if a cycle is ongoing.
if (activeCycle = '0') then
-- No ongoing cycles.
-- Iterate through all ports and check if any new cycle has started.
for i in 0 to WIDTH-1 loop
if ((selectedMaster+i) >= WIDTH) then
index := (selectedMaster+i) - WIDTH;
else
index := (selectedMaster+i);
end if;
if (masterCyc_i(index) = '1') then
activeCycle <= '1';
selectedMaster <= index;
end if;
end loop;
else
-- Ongoing cycle.
-- Check if the cycle has ended.
if (masterCyc_i(selectedMaster) = '0') then
-- Cycle has ended.
activeCycle <= '0';
-- Check if a new cycle has started from another master.
-- Start to check from the one that ended its cycle, this way, the
-- ports will be scheduled like round-robin.
for i in 0 to WIDTH-1 loop
if ((selectedMaster+i) >= WIDTH) then
index := (selectedMaster+i) - WIDTH;
else
index := (selectedMaster+i);
end if;
if (masterCyc_i(index) = '1') then
activeCycle <= '1';
selectedMaster <= index;
end if;
end loop;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Address decoding.
-----------------------------------------------------------------------------
-- Select the last port when the top bit is set.
-- The last port must be the maintenance slave port.
selectedSlave <= WIDTH-1 when masterAddr_i(selectedMaster)(9) = '1' else
to_integer(unsigned(masterAddr_i(selectedMaster)(8 downto 1)));
-----------------------------------------------------------------------------
-- Interconnection matrix.
-----------------------------------------------------------------------------
Interconnect: for i in 0 to WIDTH-1 generate
slaveCyc_o(i) <= masterCyc_i(selectedMaster) when (selectedSlave = i) else '0';
slaveStb_o(i) <= masterStb_i(selectedMaster) when (selectedSlave = i) else '0';
slaveWe_o(i) <= masterWe_i(selectedMaster);
slaveAddr_o(i) <= masterAddr_i(selectedMaster);
slaveData_o(i) <= masterData_i(selectedMaster);
masterData_o(i) <= slaveData_i(selectedSlave);
masterAck_o(i) <= slaveAck_i(selectedSlave) when (selectedMaster = i) else '0';
end generate;
-----------------------------------------------------------------------------
-- Chipscope debugging probe.
-----------------------------------------------------------------------------
--trig <= masterCyc_i(selectedMaster) & masterStb_i(selectedMaster) &
-- masterWe_i(selectedMaster) & masterAddr_i(selectedMaster) &
-- masterData_i(selectedMaster) & slaveData_i(selectedSlave) &
-- slaveAck_i(selectedSlave);
--ChipscopeIconInst: ChipscopeIcon1
-- port map(CONTROL0=>control);
--ChipscopeIlaInst: ChipscopeIlaWb
-- port map(CLK=>clk, TRIG0=>trig, CONTROL=>control);
end architecture;
|
--FPGA application for this system.
--copyright(c) 2014 dtysky
--This program is free software; you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation; either version 2 of the License, or
--(at your option) any later version.
--This program is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License along
--with this program; if not, write to the Free Software Foundation, Inc.,
--51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
------------------------------------------------------------------------
--数据传输结束确定后进入LOCK状态，usb_end置1
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity USB_RAM_BUFFER is
port
(
inclk:in std_logic;
usb_clk:out std_logic;
usb_full,usb_empty:in std_logic;
sloe:out std_logic:='0';
slrd,pktend:out std_logic:='0';
slwr:out std_logic:='0';
fifoadr:out std_logic_vector(1 downto 0);
usb_data:inout std_logic_vector(15 downto 0);
pc_rqu:in std_logic;
usb_in:in std_logic
);
end entity;
architecture bufferx of usb_RAM_BUFFER is
component PLL is
port
(
inclk0:in std_logic;
c0,c1,c2,c3:out std_logic;
locked:out std_logic
);
end component;
component FIFO_TO_OTHER is
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end component;
component COUNTER_TIMEOUT IS
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
end component;
----------------Clock------------------
signal clk_usb_p,clk_usb_n,clk_usb_90,clk_usb_270,clk_usb_lock:std_logic;
----------------fifo例化----------------
signal data_to_ram:std_logic_vector(15 downto 0);
signal fifo_utr_write,fifo_utr_read:std_logic:='0';
signal fifo_utr_aclr:std_logic:='0';
signal data_from_usb:std_logic_vector(7 downto 0);
signal data_to_usb:std_logic_vector(15 downto 0);
--------------fifo已写/可读数据-----------
signal fifo_utr_num_w:std_logic_vector(9 downto 0);
signal fifo_utr_num_r:std_logic_vector(8 downto 0);
signal fifo_utr_num_w_buffer:std_logic_vector(9 downto 0);
signal fifo_utr_num_r_buffer:std_logic_vector(8 downto 0);
----------------pc cmd------------------
signal command:std_logic_vector(15 downto 0);
------------------usb-------------------
signal usb_in_rqu,usb_out_rqu:std_logic:='0';
signal usb_in_rqu_last:std_logic:='0';
signal usb_in_ready,usb_out_ready:std_logic:='0';
signal usb_in_ready_last,usb_out_ready_last:std_logic:='0';
signal usb_in_allow:std_logic:='0';
signal usb_out_allow:std_logic:='0';
signal usb_check:std_logic_vector(15 downto 0);
------------------timeout----------------
signal timeout_aclr:std_logic:='1';
signal timeout_clken:std_logic:='0';
signal timeout_q:std_logic_vector(11 downto 0);
signal timeout_buffer:std_logic_vector(11 downto 0);
-----------------flags-------------------
type ustates is (free,full,ack,rd,reset,lock);
signal usb_state,usb_state_buffer:ustates:=free;
begin
usb_clk<=clk_usb_270;
PLL_1:PLL
port map
(
inclk0=>inclk,
c0=>clk_usb_p,c1=>clk_usb_90,c2=>clk_usb_n,c3=>clk_usb_270,
locked=>clk_usb_lock
);
buffer_usb:FIFO_TO_OTHER
port map
(
aclr=>fifo_utr_aclr,
data=>data_from_usb,q(7 downto 0)=>data_to_ram(15 downto 8),q(15 downto 8)=>data_to_ram(7 downto 0),
wrclk=>clk_usb_270,rdclk=>clk_usb_270,
wrreq=>fifo_utr_write,rdreq=>fifo_utr_read,
wrusedw=>fifo_utr_num_w,rdusedw=>fifo_utr_num_r
);
timeout:COUNTER_TIMEOUT
port map
(
aclr=>timeout_aclr,
clk_en=>timeout_clken,
clock=>clk_usb_n,
q=>timeout_q
);
--------------USB------------
usb_control:process(clk_usb_p,clk_usb_lock)
variable con_full:integer range 0 to 7:=0;
variable con_ack:integer range 0 to 7:=0;
begin
if clk_usb_p'event and clk_usb_p='1' and clk_usb_lock='1' then
case usb_state is
-----------IDLE------------
when free =>
usb_data<="ZZZZZZZZZZZZZZZZ";
if usb_full='1' then
usb_state<=full;
else
usb_state<=free;
end if;
-----------FULL------------
when full =>
case con_full is
when 0 =>
fifo_utr_aclr<='0';
fifo_utr_write<='0';
sloe<='0';
slrd<='0';
fifoadr<="00";
con_full:=con_full+1;
when 1 =>
sloe<='1';
con_full:=con_full+1;
when 2 =>
con_full:=con_full+1;
when 3 =>
slrd<='1';
fifo_utr_write<='1';
con_full:=con_full+1;
when others =>
case fifo_utr_num_w_buffer is
when "0111111101" =>
usb_check(7 downto 0)<=usb_data(7 downto 0);
when "0111111110" =>
usb_check(15 downto 8)<=usb_data(7 downto 0);
sloe<='0';
slrd<='0';
fifo_utr_write<='0';
when "1000000000" =>
usb_state<=ack;
con_full:=0;
when others =>
fifo_utr_write<=fifo_utr_write;
end case;
end case;
-------------RD-------------
-- when rd =>
--
-- if fifo_utr_num_r="100000000" then
-- fifo_utr_read<='1';
-- elsif fifo_utr_num_r="000000000" then
-- fifo_utr_read<='0';
-- usb_state<=ack;
-- end if;
-------------ACK------------
when ack =>
case con_ack is
when 0 =>
fifoadr<="10";
slwr<='0';
pktend<='0';
con_ack:=con_ack+1;
when 2 =>
slwr<='1';
usb_data(7 downto 0)<=usb_check(7 downto 0);
con_ack:=con_ack+1;
when 3=>
usb_data(7 downto 0)<=usb_check(15 downto 8);
con_ack:=con_ack+1;
when 4 =>
slwr<='0';
pktend<='1';
con_ack:=con_ack+1;
when 5 =>
pktend<='0';
fifo_utr_aclr<='1';
usb_state<=free;
con_ack:=0;
when others =>
con_ack:=con_ack+1;
end case;
-----------RESET-----------
when reset =>
con_full:=0;
con_ack:=0;
slwr<='0';
fifo_utr_aclr<='1';
usb_state<=free;
-----------LOCK------------
when lock =>
fifo_utr_aclr<='1';
-----------ERROR-----------
when others =>
usb_state<=reset;
end case;
fifo_utr_num_w_buffer<=fifo_utr_num_w;
end if;
end process;
data_from_usb<=usb_data(7 downto 0);
--data_from_usb(15 downto 8)<=usb_data_in(7 downto 0);
end bufferx;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY rotRight IS
PORT (
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Input to be rotated
amnt : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --Amount to Rotate by
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) -- Rotated Input
);
END rotRight;
ARCHITECTURE rtl OF rotRight IS
BEGIN
WITH amnt SELECT -- din <<< amnt
dout<=
din(0) & din(31 DOWNTO 01) WHEN "00001", --01
din(01 DOWNTO 0) & din(31 DOWNTO 02) WHEN "00010", --02
din(02 DOWNTO 0) & din(31 DOWNTO 03) WHEN "00011", --03
din(03 DOWNTO 0) & din(31 DOWNTO 04) WHEN "00100", --04
din(04 DOWNTO 0) & din(31 DOWNTO 05) WHEN "00101", --05
din(05 DOWNTO 0) & din(31 DOWNTO 06) WHEN "00110", --06
din(06 DOWNTO 0) & din(31 DOWNTO 07) WHEN "00111", --07
din(07 DOWNTO 0) & din(31 DOWNTO 08) WHEN "01000", --08
din(08 DOWNTO 0) & din(31 DOWNTO 09) WHEN "01001", --09
din(09 DOWNTO 0) & din(31 DOWNTO 10) WHEN "01010", --10
din(10 DOWNTO 0) & din(31 DOWNTO 11) WHEN "01011", --11
din(11 DOWNTO 0) & din(31 DOWNTO 12) WHEN "01100", --12
din(12 DOWNTO 0) & din(31 DOWNTO 13) WHEN "01101", --13
din(13 DOWNTO 0) & din(31 DOWNTO 14) WHEN "01110", --14
din(14 DOWNTO 0) & din(31 DOWNTO 15) WHEN "01111", --15
din(15 DOWNTO 0) & din(31 DOWNTO 16) WHEN "10000", --16
din(16 DOWNTO 0) & din(31 DOWNTO 17) WHEN "10001", --17
din(17 DOWNTO 0) & din(31 DOWNTO 18) WHEN "10010", --18
din(18 DOWNTO 0) & din(31 DOWNTO 19) WHEN "10011", --19
din(19 DOWNTO 0) & din(31 DOWNTO 20) WHEN "10100", --20
din(20 DOWNTO 0) & din(31 DOWNTO 21) WHEN "10101", --21
din(21 DOWNTO 0) & din(31 DOWNTO 22) WHEN "10110", --22
din(22 DOWNTO 0) & din(31 DOWNTO 23) WHEN "10111", --23
din(23 DOWNTO 0) & din(31 DOWNTO 24) WHEN "11000", --24
din(24 DOWNTO 0) & din(31 DOWNTO 25) WHEN "11001", --25
din(25 DOWNTO 0) & din(31 DOWNTO 26) WHEN "11010", --26
din(26 DOWNTO 0) & din(31 DOWNTO 27) WHEN "11011", --27
din(27 DOWNTO 0) & din(31 DOWNTO 28) WHEN "11100", --28
din(28 DOWNTO 0) & din(31 DOWNTO 29) WHEN "11101", --29
din(29 DOWNTO 0) & din(31 DOWNTO 30) WHEN "11110", --30
din(30 DOWNTO 0) & din(31) WHEN "11111", --31
din WHEN OTHERS; --32
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity func06 is
port (s : natural;
r : out std_logic_vector (15 downto 0));
end func06;
architecture behav of func06 is
function mapv (sel : natural) return std_logic_vector
is
variable res : std_logic_vector(15 downto 0) := (others => '0');
begin
case sel is
when 2 =>
res := x"1234";
when 3 =>
res := x"5678";
when others =>
null;
end case;
return res;
end mapv;
begin
r <= mapv (s);
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity registry is
generic(TOTAL_BITS : integer := 32);
port(
enable: in std_logic := '0';
reset: in std_logic := '0';
clk: in std_logic := '0';
D: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
Q: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end;
architecture registry_arq of registry is
begin
process(clk, reset, enable, D)
begin
if reset = '1' then
Q <= (others => '0');
elsif rising_edge(clk) then
if enable = '1' then
Q <= D;
end if; --No va else para considerar todos los casos porque asi deja el valor anterior de Q.
end if;
end process;
end; |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity keyboard is
port (
clock_i : in std_logic;
reset_i : in std_logic;
-- MSX
rows_coded_i : in std_logic_vector(3 downto 0);
cols_o : out std_logic_vector(7 downto 0);
keymap_addr_i : in std_logic_vector(8 downto 0);
keymap_data_i : in std_logic_vector(7 downto 0);
keymap_we_i : in std_logic;
-- LEDs
led_caps_i : in std_logic;
-- PS/2 interface
ps2_clk_io : inout std_logic;
ps2_data_io : inout std_logic;
-- Direct Access
keyb_valid_o : out std_logic;
keyb_data_o : out std_logic_vector(7 downto 0);
--
reset_o : out std_logic := '0';
por_o : out std_logic := '0';
reload_core_o : out std_logic := '0';
extra_keys_o : out std_logic_vector(3 downto 0) -- F11, Print Screen, Scroll Lock, Pause/Break
);
end entity;
architecture Behavior of Keyboard is
signal clock_km_s : std_logic;
-- Matrix
type key_matrix_t is array (15 downto 0) of std_logic_vector(7 downto 0);
signal matrix_s : key_matrix_t;
signal d_to_send_s : std_logic_vector(7 downto 0) := (others => '0');
signal data_load_s : std_logic := '0';
signal keyb_data_s : std_logic_vector(7 downto 0);
signal keyb_valid_s : std_logic;
signal break_s : std_logic;
signal extended_s : std_logic_vector(1 downto 0);
signal has_keycode_s : std_logic;
signal keymap_addr_s : std_logic_vector(8 downto 0);
signal keymap_data_s : std_logic_vector(7 downto 0);
signal extra_keys_s : std_logic_vector(3 downto 0);
type keymap_seq_t is (KM_IDLE, KM_READ, KM_END);
signal keymap_seq_s : keymap_seq_t;
begin
-- PS/2 interface
ps2_port: entity work.ps2_iobase
port map (
enable_i => '1',
clock_i => clock_i,
reset_i => reset_i,
ps2_data_io => ps2_data_io,
ps2_clk_io => ps2_clk_io,
data_rdy_i => data_load_s,
data_i => d_to_send_s,
data_rdy_o => keyb_valid_s,
data_o => keyb_data_s
);
clock_km_s <= not clock_i;
-- The keymap
keymap: entity work.keymap
port map (
clock_i => clock_km_s,
we_i => keymap_we_i,
addr_wr_i => keymap_addr_i,
data_i => keymap_data_i,
addr_rd_i => keymap_addr_s,
data_o => keymap_data_s
);
-- Interpret scancode received
process (reset_i, clock_i)
variable batcode_v : std_logic := '0';
variable skip_count_v : std_logic_vector(2 downto 0);
variable break_v : std_logic;
variable extended_v : std_logic_vector(1 downto 0);
variable ctrl_v : std_logic;
variable alt_v : std_logic;
variable led_caps_v : std_logic := '0';
variable ed_resp_v : std_logic;
begin
if reset_i = '1' then
reload_core_o <= '0';
reset_o <= '0';
por_o <= '0';
extra_keys_s <= (others => '0');
skip_count_v := "000";
ed_resp_v := '0';
break_v := '0';
extended_v := "00";
ctrl_v := '0';
alt_v := '0';
has_keycode_s <= '0';
break_s <= '0';
extended_s <= "00";
elsif rising_edge(clock_i) then
has_keycode_s <= '0';
data_load_s <= '0';
if keyb_valid_s = '1' then
if keyb_data_s = X"AA" then
-- BAT code (basic assurance test)
batcode_v := '1';
elsif keyb_data_s = X"FA" then
-- 0xED resp
ed_resp_v := '1';
elsif skip_count_v /= "000" then
skip_count_v := skip_count_v - 1;
elsif keyb_data_s = X"E0" then
-- Extended E0 key code follows
extended_v(0) := '1';
elsif keyb_data_s = X"E1" then
-- Extended E1 key code follows
extended_v(1) := '1';
elsif keyb_data_s = X"F0" then
-- Release code (break) follows
break_v := '1';
elsif keyb_data_s = X"14" and extended_v = "10" then -- PAUSE/BREAK E1 [14] (77 E1 F0 14) F0 77
if break_v = '0' then
skip_count_v := "100"; -- Skip the next 4 sequences
extended_v := "00";
end if;
extra_keys_s(0) <= '1';
elsif keyb_data_s = X"77" and extended_v = "00" then -- PAUSE/BREAK release (F0 77)
extra_keys_s(0) <= '0';
elsif keyb_data_s = X"7C" and extended_v = "01" then -- PRINT SCREEN E0,12,E0,7C E0,F0,7C,E0,F0,12
if break_v = '0' then
extended_v := "00";
end if;
extra_keys_s(2) <= not break_v;
else
if keyb_data_s = X"11" and extended_v(1) = '0' then -- LAlt and RAlt
alt_v := not break_v;
elsif keyb_data_s = X"14" and extended_v(1) = '0' then -- LCtrl and RCtrl
ctrl_v := not break_v;
elsif keyb_data_s = X"71" and extended_v = "01" then -- Delete
if alt_v = '1' and ctrl_v = '1' and break_v = '0' then
reset_o <= '1';
end if;
elsif keyb_data_s = X"78" and extended_v = "00" then -- F11
extra_keys_s(3) <= not break_v;
elsif keyb_data_s = X"07" and extended_v = "00" then -- F12
if alt_v = '1' and ctrl_v = '1' and break_v = '0' then
por_o <= '1';
end if;
elsif keyb_data_s = X"66" and extended_v = "00" then -- Backspace
if alt_v = '1' and ctrl_v = '1' and break_v = '0' then
reload_core_o <= '1';
end if;
elsif keyb_data_s = X"7E" and extended_v = "00" then -- Scroll-lock 7E F0 7E
extra_keys_s(1) <= not break_v;
-- if break_v = '0' then
-- extra_keys_s(1) <= not extra_keys_s(1);
-- end if;
end if;
break_s <= break_v;
extended_s <= extended_v;
break_v := '0';
extended_v := "00";
has_keycode_s <= '1';
end if; -- if keyb_data_s...
else -- keyb_valid = 1
if batcode_v = '1' then
batcode_v := '0';
d_to_send_s <= X"55";
data_load_s <= '1';
elsif led_caps_v /= led_caps_i then
led_caps_v := led_caps_i;
d_to_send_s <= X"ED";
data_load_s <= '1';
elsif ed_resp_v = '1' then
ed_resp_v := '0';
d_to_send_s <= "00000" & led_caps_v & "00";
data_load_s <= '1';
end if;
end if; -- keyb_valid_edge = 01
end if;
end process;
-- State machine
process (reset_i, clock_i)
variable keyid_v : std_logic_vector(8 downto 0);
variable row_v : std_logic_vector(3 downto 0);
variable col_v : std_logic_vector(2 downto 0);
begin
if reset_i = '1' then
matrix_s <= (others => (others => '0'));
keymap_addr_s <= (others => '0');
keymap_seq_s <= KM_IDLE;
cols_o <= (others => '1');
elsif rising_edge(clock_i) then
case keymap_seq_s is
when KM_IDLE =>
if has_keycode_s = '1' then
cols_o <= (others => '1');
keyid_v := extended_s(0) & keyb_data_s;
keymap_addr_s <= keyid_v;
keymap_seq_s <= KM_READ;
else
cols_o <= not matrix_s(conv_integer(rows_coded_i));
end if;
when KM_READ =>
row_v := keymap_data_s(3 downto 0);
col_v := keymap_data_s(6 downto 4);
keymap_seq_s <= KM_END;
when KM_END =>
matrix_s(conv_integer(row_v))(conv_integer(col_v)) <= not break_s;
keymap_seq_s <= KM_IDLE;
end case;
end if;
end process;
extra_keys_o <= extra_keys_s;
--
keyb_valid_o <= keyb_valid_s;
keyb_data_o <= keyb_data_s;
end architecture; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2454.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s03b02x02p03n02i02454pkg is
type UN_ARR is array (integer range <>) of character;
subtype CON_ARR is UN_ARR( 1 to 5) ;
end c07s03b02x02p03n02i02454pkg;
use work.c07s03b02x02p03n02i02454pkg.all;
ENTITY c07s03b02x02p03n02i02454ent IS
port (P : in CON_ARR := (others => 'A')); --- No_failure_here
END c07s03b02x02p03n02i02454ent;
ARCHITECTURE c07s03b02x02p03n02i02454arch OF c07s03b02x02p03n02i02454ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(P(1)='A' and P(2)='A' and P(3)='A' and P(4)='A' and P(5)='A')
report "***PASSED TEST: c07s03b02x02p03n02i02454"
severity NOTE;
assert (P(1)='A' and P(2)='A' and P(3)='A' and P(4)='A' and P(5)='A')
report "***FAILED TEST: c07s03b02x02p03n02i02454 - As the default expression defining the default initial value of a port declared to be of a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02454arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2454.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s03b02x02p03n02i02454pkg is
type UN_ARR is array (integer range <>) of character;
subtype CON_ARR is UN_ARR( 1 to 5) ;
end c07s03b02x02p03n02i02454pkg;
use work.c07s03b02x02p03n02i02454pkg.all;
ENTITY c07s03b02x02p03n02i02454ent IS
port (P : in CON_ARR := (others => 'A')); --- No_failure_here
END c07s03b02x02p03n02i02454ent;
ARCHITECTURE c07s03b02x02p03n02i02454arch OF c07s03b02x02p03n02i02454ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(P(1)='A' and P(2)='A' and P(3)='A' and P(4)='A' and P(5)='A')
report "***PASSED TEST: c07s03b02x02p03n02i02454"
severity NOTE;
assert (P(1)='A' and P(2)='A' and P(3)='A' and P(4)='A' and P(5)='A')
report "***FAILED TEST: c07s03b02x02p03n02i02454 - As the default expression defining the default initial value of a port declared to be of a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02454arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2454.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s03b02x02p03n02i02454pkg is
type UN_ARR is array (integer range <>) of character;
subtype CON_ARR is UN_ARR( 1 to 5) ;
end c07s03b02x02p03n02i02454pkg;
use work.c07s03b02x02p03n02i02454pkg.all;
ENTITY c07s03b02x02p03n02i02454ent IS
port (P : in CON_ARR := (others => 'A')); --- No_failure_here
END c07s03b02x02p03n02i02454ent;
ARCHITECTURE c07s03b02x02p03n02i02454arch OF c07s03b02x02p03n02i02454ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(P(1)='A' and P(2)='A' and P(3)='A' and P(4)='A' and P(5)='A')
report "***PASSED TEST: c07s03b02x02p03n02i02454"
severity NOTE;
assert (P(1)='A' and P(2)='A' and P(3)='A' and P(4)='A' and P(5)='A')
report "***FAILED TEST: c07s03b02x02p03n02i02454 - As the default expression defining the default initial value of a port declared to be of a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02454arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := altera;
constant CFG_MEMTECH : integer := altera;
constant CFG_PADTECH : integer := altera;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1;
constant CFG_ATBSZ : integer := 1;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := 1;
constant CFG_GRETH21G : integer := 0;
constant CFG_ETH2_FIFO : integer := 8;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#000F#;
constant CFG_GRGPIO_WIDTH : integer := (2);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Implements a full adder (half adder with carry in and carry out signals).
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port (
a : in std_logic;
b : in std_logic;
c_in : in std_logic;
sum : out std_logic;
c_out : out std_logic
);
end;
architecture BHV of full_adder is
begin
sum <= a xor b xor c_in;
c_out <= (a and b) or (c_in and (a xor b));
end BHV;
|
-- pipeProc.vhd
--
-- entity pipeProc -pipeline processor datapath
-- architecture noIO -register-transfer model
-- synthesizable
------------------------------------------------------------------------------
library ieee; -- packages:
use ieee.std_logic_1164.all; -- std_logic
use ieee.numeric_std.all; -- (un)signed
use work.procPkg.all; -- procPkg (=>opcode)
-- entity --------------------------------------------------------------
------------------------------------------------------------------------------
entity procIdea is
port( clk : in std_logic; -- clock
nRst : in std_logic; -- not reset
iAddr : out std_logic_vector(31 downto 0); -- instMem address
iData : in std_logic_vector(31 downto 0); -- instMem data
dnWE : out std_logic; -- dataMem write-ena
dnOE : out std_logic; -- dataMem output-ena
dAddr : out std_logic_vector(31 downto 0); -- dataMem address
dData : inout std_logic_vector(31 downto 0)); -- dataMem data
end entity procIdea;
-- architecture --------------------------------------------------------------
------------------------------------------------------------------------------
architecture noIO of procIdea is
type regBankTy is array (0 to 31) of std_logic_vector(31 downto 0);
signal regBank : regBankTy;
signal instIF : std_logic_vector(31 downto 0);
signal instID : std_logic_vector(31 downto 0);
signal instEX : std_logic_vector(31 downto 0);
signal instMEM : std_logic_vector(31 downto 0);
signal aluOpc : std_logic_vector(3 downto 0);
signal akku, opA : std_logic_vector(31 downto 0);
signal akkuEX : std_logic_vector(31 downto 0);
signal akkuMEM : std_logic_vector(31 downto 0);
signal achtungFlag : std_logic;
signal alu : signed(31 downto 0);
signal aluEX : std_logic_vector(31 downto 0);
signal regMEM : std_logic_vector(31 downto 0);
signal dDataEna : std_logic;
signal dDataReg : std_logic_vector(31 downto 0);
signal instCntIF : std_logic_vector(31 downto 0);
signal eqzFlag : std_logic;
begin
-- iAddr <= std_logic_vector(instCnt);
iAddr <= regBank(2);
-- IF ------------------------------------------------------
----------------------------------------------------------------------------
pipeIFreg_P: process(nRst, clk) is -- process: register + input-logic
begin --------------------------------------
if nRst = '0' then -- async. reset
instIF <= (others =>'1'); -- no-operation
elsif rising_edge(clk) then
instIF <= iData;
instCntIF <= regBank(2);
end if;
end process pipeIFreg_P;
-- ID / OF ------------------------------------------------------
-- -delayed regBank read in EX and MEM
----------------------------------------------------------------------------
pipeIDreg_P: process(nRst, clk) is -- process: register + input-logic
begin --------------------------------------
if nRst = '0' then -- async. reset
instID <= (others =>'1');
achtungFlag <= '0'; -- no-operation
elsif rising_edge(clk) then
instID <= instIF;
achtungFlag <= '0';
case instIF(31 downto 27) is -- decode instIF.opc --------------
when opcAdd | opcSub | -- 2-operand
opcAnd | opcOr | opcXor | opcShl | opcShr | opcNot =>
if achtungFlag = '0' then -- ALU command
akku <= regBank(0); --Der Akku
opA <= regBank(to_integer(unsigned(instIF(4 downto 0))));
achtungFlag <= '1';
elsif achtungFlag = '1' then
opA <= regBank(to_integer(unsigned(instIF(4 downto 0))));
achtungFlag <= '1';
end if;
-- 23 Bit Verschwendung, yay!
when opcMove =>
akku <= regBank(4);
opA <= "00000" & instIF(26 downto 0); -- Das ist eine Sign-Extention. (27 -> 32 Bit)
achtungFlag <= '1';
when opcAkkuLoad =>
akku <= regBank(4);
opA <= "00000000000000000000000000000000";
achtungFlag <= '1';
when opcAkkuStore =>
if achtungFlag = '0' then
akku <= regBank(4);
opA <= "00000000000000000000000000000000";
achtungFlag <= '0';
elsif achtungFlag = '1' then
opA <= "00000000000000000000000000000000";
achtungFlag <= '0';
end if;
when opcLoadMemory =>
achtungFlag <= '0';
when opcNoOP =>
achtungFlag <= '1';
when opcStoreMemory =>
if achtungFlag = '0' then
akku <= regBank(4);
opA <= "00000" & instIF(26 downto 0);
achtungFlag <= '0';
elsif achtungFlag = '1' then
opA <= "00000" & instIF(26 downto 0);
achtungFlag <= '0';
end if;
when opciStore =>
if achtungFlag = '0' then
akku <= regBank(4);
opA <= "00000" & instIF(26 downto 0);
achtungFlag <= '0';
elsif achtungFlag = '1' then
opA <= "00000" & instIF(26 downto 0);
achtungFlag <= '0';
end if;
when opciLoad =>
achtungFlag <= '0';
when opcJmp =>
akku <= regBank(4);
opA <= regBank(to_integer(unsigned(instIF(4 downto 0))));
achtungFlag <= '0';
when others => null;
end case; -- decode opcode
end if;
end process pipeIDreg_P;
-- EX ------------------------------------------------------
----------------------------------------------------------------------------
-- ALU opcode --------------
-- mode may require addition in ALU
aluOpc <= aluAdd when ((instID(31 downto 27) = opcJmp) or
(instID(31 downto 27) = opcMove) or
(instID(31 downto 27) = opcAkkuLoad) or
(instID(31 downto 27) = opcAkkuStore))
else instID(30 downto 27); -- ALU command
with aluOpc select -- ALU ------------------------------
alu <= signed(akku)+signed(opA) when aluAdd,
signed(akku)-signed(opA) when aluSub,
signed(akku and opA) when aluAnd,
signed(akku or opA) when aluOr,
signed(akku xor opA) when aluXor,
signed(shift_left(unsigned(akku),to_integer(unsigned(opA)))) when aluShl,
signed(shift_right(unsigned(akku),to_integer(unsigned(opA)))) when aluShr,
signed(not(opA)) when aluNot,
(others => '-') when others;
pipeEXreg_P: process(nRst, clk) is -- process: register + input-logic
begin --------------------------------------
if nRst = '0' then -- async. reset
instEx <= (others =>'1'); -- no-operation
dAddr <= (others =>'0'); -- data address
dnWE <= '1'; -- data readopA <= regBank(toInteger(unsigned(instIF(27 downto 0))));
dnOE <= '1'; -- data disabled
dDataEna <= '0'; -- own bus-driver disabled
elsif rising_edge(clk) then
instEX <= instID;
dnWE <= '1';
dnOE <= '1';
dDataEna <= '0';
case instID(31 downto 27) is -- decode instID.opc --------------
when opcAnd | opcOr | opcXor | opcShl | opcShr | opcNot | opcMove | opcJmp =>
-- ALU command
aluEX <= std_logic_vector(alu);
akkuEX <= std_logic_vector(alu);
if alu = 0 then eqzFlag <= '1';
else eqzFlag <= '0';
end if;
when opcAdd | opcSub =>
aluEX <= std_logic_vector(alu);
akkuEX <= std_logic_vector(alu);
if alu = 0 then eqzFlag <= '1';
else eqzFlag <= '0';
end if;
when opcLoadMemory => -- Load
dnOE <= '0'; -- + absolute
dAddr <= "00000" & instID(26 downto 0);
when opcStoreMemory => -- Store
dnWE <= '0';
dDataEna<= '1';
dDataReg<= regBank(0); -- + absolute
dAddr <= "00000" & instID(26 downto 0);
when opcAkkuStore =>
aluEX <= regBank(0);
when opcAkkuLoad =>
aluEX <= regBank(to_integer(unsigned(instID(4 downto 0))));
when opciStore =>
dnWE <= '0';
dDataEna<= '1';
dDataReg<= regBank(0); -- + absolute
dAddr <= regBank(to_integer(unsigned(instID(4 downto 0))));
when opciLoad =>
dnOE <= '0';
dAddr <= regBank(to_integer(unsigned(instID(4 downto 0))));
when others => null;
end case; -- decode opcode
end if;
end process pipeEXreg_P;
-- tristate bus driver --------------
dData <= dDataReg when dDataEna = '1' else -- enabled
(others => 'Z'); -- tristate
-- MEM ------------------------------------------------------
----------------sim:/procsim/procIdeaI/regMEM(3)
------------------------------------------------------------
pipeMEMreg_P: process(nRst, clk) is -- process: register + input-logic
begin --------------------------------------
if nRst = '0' then -- async. reset
instMEM <= (others =>'1'); -- no-operation
elsif rising_edge(clk) then
instMEM <= instEX;
case instEX(31 downto 27) is -- decode instEX.opc --------------
when opcAdd | opcSub |
opcAnd | opcOr | opcXor | opcShl | opcShr | opcNot | opcMove | opcAkkuStore | opcJmp => -- ALU command
regMEM <= aluEX;
when opcLoadMemory | opciLoad => -- Load
regMEM <= dData;
when others => null;
end case; -- decode opcode
end if;
end process pipeMEMreg_P;
-- WB / regBank ------------------------------------------------------
----------------------------------------------------------------------------
pipeWBreg_P: process(nRst,clk) is -- process: register + input-logic
begin
if nRst = '0' then
regBank(0) <= (others => '0');
regBank(1) <= "00000000000000000111111111111111"
regBank(2) <= (others => '0');
regBank(4) <= (others => '0');
--------------------------------------
elsif rising_edge(clk) then
regBank(2) <= std_logic_vector(unsigned(regBank(2)) + 1);
case instMEM(31 downto 27) is -- decode instMEM.opc --------------
when opcAdd | opcSub |
opcAnd | opcOr | opcXor | opcShl | opcShr | opcNot | -- ALU command
opcLoadMemory | opcMove | opcAkkuLoad | opciLoad => -- Load
regBank(0) <= regMEM;
when opcAkkuStore =>
regBank(to_integer(unsigned(instMEM(4 downto 0)))) <= regMEM;
when opcJmp =>
-- Jump =0
if eqzFlag = '1' then -- if=0
regBank(2) <= regMEM; -- absolute
end if; -- condition
when others => null;
end case;
if (iData(31 downto 27) = opcHALTSTOP) or
(instIF(31 downto 27) = opcHALTSTOP) or
(instID(31 downto 27) = opcHALTSTOP) then -- stop
regBank(2) <= regBank(2);
end if; -- decode opcode
end if;
end process pipeWBreg_P;
end architecture noIO;
------------------------------------------------------------------------------
-- pipeProc.vhd - end
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 5 June 2011
-- Design Name:
-- Module Name: UDP_TX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple UDP TX
-- doesnt generate the checksum(supposedly optional)
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Added abort of tx when receive last from upstream
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
entity UDP_TX is
Port (
-- UDP Layer signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
-- IP layer TX signals
ip_tx_start : out std_logic;
ip_tx : out ipv4_tx_type; -- IP tx cxns
ip_tx_result : in std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : in std_logic; -- indicates IP TX is ready to take data
req_ip_layer : out std_logic;
granted_ip_layer : in std_logic
);
end UDP_TX;
architecture Behavioral of UDP_TX is
type tx_state_type is (IDLE, PAUSE, SEND_UDP_HDR, SEND_USER_DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_cnt_type is (RST, SET, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- TX state variables
signal udp_tx_state : tx_state_type;
signal tx_count : unsigned (15 downto 0);
signal tx_result_reg : std_logic_vector (1 downto 0);
signal ip_tx_start_reg : std_logic;
signal data_out_ready_reg : std_logic;
-- tx control signals
signal next_tx_state : tx_state_type;
signal set_tx_state : std_logic;
signal next_tx_result : std_logic_vector (1 downto 0);
signal set_tx_result : std_logic;
signal tx_count_val : unsigned (15 downto 0);
signal tx_count_mode : settable_cnt_type;
signal tx_data : std_logic_vector (7 downto 0);
signal set_last : std_logic;
signal set_ip_tx_start : set_clr_type;
signal tx_data_valid : std_logic; -- indicates whether data is valid to tx or not
signal tx_ip_chn_reqd : std_logic;--AJOUT JOHN
signal set_chn_reqd : set_clr_type;--AJOUT JOHN
-- tx temp signals
signal total_length : std_logic_vector (15 downto 0); -- computed combinatorially from header size
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | source port number | dest port number |
-- | | |
-- --------------------------------------------------------------------------------------------
-- | length (bytes) | checksum |
-- | (header and data combined) | |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
tx_combinatorial : process(
-- input signals
udp_tx_start, udp_txi, clk, ip_tx_result, ip_tx_data_out_ready,
-- state variables
udp_tx_state, tx_count, tx_result_reg, ip_tx_start_reg, data_out_ready_reg, tx_ip_chn_reqd,--ajout john
-- control signals
next_tx_state, set_tx_state, next_tx_result, set_tx_result, tx_count_mode, tx_count_val,
tx_data, set_last, total_length, set_ip_tx_start, tx_data_valid, set_chn_reqd --ajout john
)
begin
-- set output followers
ip_tx_start <= ip_tx_start_reg;
ip_tx.hdr.protocol <= x"11"; -- UDP protocol
ip_tx.hdr.data_length <= total_length;
ip_tx.hdr.dst_ip_addr <= udp_txi.hdr.dst_ip_addr;
req_ip_layer <= tx_ip_chn_reqd;--AJOUT JOHN
if udp_tx_start = '1' and ip_tx_start_reg = '0' then
udp_tx_result <= UDPTX_RESULT_NONE; -- kill the result until have started the IP layer
else
udp_tx_result <= tx_result_reg;
end if;
case udp_tx_state is
when SEND_USER_DATA =>
ip_tx.data.data_out <= udp_txi.data.data_out;
tx_data_valid <= udp_txi.data.data_out_valid;
ip_tx.data.data_out_last <= udp_txi.data.data_out_last;
when SEND_UDP_HDR =>
ip_tx.data.data_out <= tx_data;
tx_data_valid <= ip_tx_data_out_ready;
ip_tx.data.data_out_last <= set_last;
when others =>
ip_tx.data.data_out <= (others => '0');
tx_data_valid <= '0';
ip_tx.data.data_out_last <= set_last;
end case;
ip_tx.data.data_out_valid <= tx_data_valid and ip_tx_data_out_ready;
-- set signal defaults
next_tx_state <= IDLE;
set_tx_state <= '0';
tx_count_mode <= HOLD;
tx_data <= x"00";
set_last <= '0';
next_tx_result <= UDPTX_RESULT_NONE;
set_tx_result <= '0';
set_ip_tx_start <= HOLD;
tx_count_val <= (others => '0');
udp_tx_data_out_ready <= '0';
set_chn_reqd <= HOLD;--ajout john
-- set temp signals
total_length <= std_logic_vector(unsigned(udp_txi.hdr.data_length) + 8); -- total length = user data length + header length (bytes)
-- TX FSM
case udp_tx_state is
when IDLE =>
udp_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
tx_count_mode <= RST;
if udp_tx_start = '1' then
-- check header count for error if too high
if unsigned(udp_txi.hdr.data_length) > 1472 then
next_tx_result <= UDPTX_RESULT_ERR;
set_tx_result <= '1';
set_chn_reqd <= CLR;--ajout john
else
-- start to send UDP header
tx_count_mode <= RST;
next_tx_result <= UDPTX_RESULT_SENDING;
set_ip_tx_start <= SET;
set_tx_result <= '1';
next_tx_state <= PAUSE;
set_tx_state <= '1';
set_chn_reqd <= SET;--ajout john
end if;
else
set_chn_reqd <= CLR;--ajout john
end if;
when PAUSE =>
if granted_ip_layer = '1' then
-- delay one clock for IP layer to respond to ip_tx_start and remove any tx error result
next_tx_state <= SEND_UDP_HDR;
set_tx_state <= '1';
end if;
when SEND_UDP_HDR =>
udp_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if ip_tx_result = IPTX_RESULT_ERR then
set_ip_tx_start <= CLR;
next_tx_result <= UDPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
elsif ip_tx_data_out_ready = '1' then
if tx_count = x"0007" then
tx_count_val <= x"0001";
tx_count_mode <= SET;
next_tx_state <= SEND_USER_DATA;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"0000" => tx_data <= udp_txi.hdr.src_port (15 downto 8); -- src port
when x"0001" => tx_data <= udp_txi.hdr.src_port (7 downto 0);
when x"0002" => tx_data <= udp_txi.hdr.dst_port (15 downto 8); -- dst port
when x"0003" => tx_data <= udp_txi.hdr.dst_port (7 downto 0);
when x"0004" => tx_data <= total_length (15 downto 8); -- length
when x"0005" => tx_data <= total_length (7 downto 0);
when x"0006" => tx_data <= udp_txi.hdr.checksum (15 downto 8); -- checksum (set by upstream)
when x"0007" => tx_data <= udp_txi.hdr.checksum (7 downto 0);
when others =>
-- shouldnt get here - handle as error
next_tx_result <= UDPTX_RESULT_ERR;
set_tx_result <= '1';
end case;
end if;
when SEND_USER_DATA =>
udp_tx_data_out_ready <= ip_tx_data_out_ready; -- in this state, we can accept user data if IP TX rdy
if ip_tx_data_out_ready = '1' then
if udp_txi.data.data_out_valid = '1' or tx_count = x"000" then
-- only increment if ready and valid has been subsequently established, otherwise data count moves on too fast
if unsigned(tx_count) = unsigned(udp_txi.hdr.data_length) then
-- TX terminated due to count - end normally
set_last <= '1';
tx_data <= udp_txi.data.data_out;
next_tx_result <= UDPTX_RESULT_SENT;
set_ip_tx_start <= CLR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
set_chn_reqd <= CLR;--ajout john
elsif udp_txi.data.data_out_last = '1' then
-- terminate tx with error as got last from upstream before exhausting count
set_last <= '1';
tx_data <= udp_txi.data.data_out;
next_tx_result <= UDPTX_RESULT_ERR;
set_ip_tx_start <= CLR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
set_chn_reqd <= CLR;--ajout john
else
-- TX continues
tx_count_mode <= INCR;
tx_data <= udp_txi.data.data_out;
end if;
end if;
end if;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
tx_sequential : process (clk,reset,data_out_ready_reg)
begin
if rising_edge(clk) then
data_out_ready_reg <= ip_tx_data_out_ready;
else
data_out_ready_reg <= data_out_ready_reg;
end if;
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
udp_tx_state <= IDLE;
tx_count <= x"0000";
tx_result_reg <= IPTX_RESULT_NONE;
ip_tx_start_reg <= '0';
tx_ip_chn_reqd <= '0';
else
-- Next udp_tx_state processing
if set_tx_state = '1' then
udp_tx_state <= next_tx_state;
else
udp_tx_state <= udp_tx_state;
end if;
-- ip_tx_start_reg processing
case set_ip_tx_start is
when SET => ip_tx_start_reg <= '1';
when CLR => ip_tx_start_reg <= '0';
when HOLD => ip_tx_start_reg <= ip_tx_start_reg;
end case;
-- tx result processing
if set_tx_result = '1' then
tx_result_reg <= next_tx_result;
else
tx_result_reg <= tx_result_reg;
end if;
-- tx_count processing
case tx_count_mode is
when RST => tx_count <= x"0000";
when SET => tx_count <= tx_count_val;
when INCR => tx_count <= tx_count + 1;
when HOLD => tx_count <= tx_count;
end case;
-- control access request to ip tx chn
case set_chn_reqd is
when SET => tx_ip_chn_reqd <= '1';
when CLR => tx_ip_chn_reqd <= '0';
when HOLD => tx_ip_chn_reqd <= tx_ip_chn_reqd;
end case;
end if;
end if;
end process;
end Behavioral;
|
--
-- Input filter
--
-- Author: Sebastian Witt
-- Data: 06.03.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_input_filter is
generic (
SIZE : natural := 4 -- Filter counter size
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end slib_input_filter;
architecture rtl of slib_input_filter is
signal iCount : integer range 0 to SIZE;
begin
IF_D: process (RST, CLK)
begin
if (RST = '1') then
iCount <= 0;
Q <= '0';
elsif (CLK'event and CLK='1') then
-- Input counter
if (CE = '1' ) then
if (D = '1' and iCount /= SIZE) then
iCount <= iCount + 1;
elsif (D = '0' and iCount /= 0) then
iCount <= iCount - 1;
end if;
end if;
-- Output
if (iCount = SIZE) then
Q <= '1';
elsif (iCount = 0) then
Q <= '0';
end if;
end if;
end process;
end rtl;
|
---------------------------------------------------------
-- JAM CPU core
-- Simple ALU with shift
--
-- License: LGPL v2+ (see the file LICENSE)
-- Copyright © 2002:
-- Anders Lindström, Johan E. Thelin, Michael Nordseth
---------------------------------------------------------
-- This is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Library General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
entity ALU is
port(
op: in std_logic_vector(2 downto 0); -- ALU operation
inv_in2 : in std_logic; -- Invert operator in2
in1, in2: in std_logic_vector(31 downto 0); -- ALU input
ovf: out std_logic; -- ALU overflow
alu_out: out std_logic_vector(31 downto 0));-- ALU result
end;
architecture rev2 of ALU is
--ALU OPS
constant ALU_NOP: std_logic_vector(2 downto 0) := "000"; --pass in1
constant ALU_ADD: std_logic_vector(2 downto 0) := "001";
constant ALU_SUB: std_logic_vector(2 downto 0) := "010";
constant ALU_OR: std_logic_vector(2 downto 0) := "011";
constant ALU_AND: std_logic_vector(2 downto 0) := "100";
constant ALU_XOR: std_logic_vector(2 downto 0) := "101";
constant ALU_SHZ: std_logic_vector(2 downto 0) := "110"; --shift and fill with zero
constant ALU_SHS: std_logic_vector(2 downto 0) := "111"; --shift and fill with sign
constant zero32: std_logic_vector(31 downto 0) := (others => '0');
begin
process(op, in1, in2, inv_in2)
variable shiftin: std_logic_vector(63 downto 0);
variable shiftcnt: std_logic_vector(4 downto 0);
variable result: std_logic_vector(31 downto 0);
variable b_in: std_logic_vector(31 downto 0);
variable cin: std_logic;
begin
if (inv_in2 = '1') or (op = ALU_SUB) then
b_in := not in2;
cin := '1';
else
b_in := in2;
cin := '0';
end if;
if op = ALU_NOP then
ovf <= '0';
result := in1;
elsif ((op = ALU_ADD) or (op = ALU_SUB)) then
result := in1 + b_in + cin;
--overflow
if op = ALU_ADD then
ovf <= (in1(31) and in2(31) and not result(31)) or (result(31) and (not in1(31)) and (not in2(31)));
else
ovf <= (in1(31) and (not in2(31)) and not result(31)) or (result(31) and (not in1(31)) and in2(31));
end if;
elsif op = ALU_OR then
result := in1 or b_in;
ovf <= '0';
elsif op = ALU_AND then
result := in1 and b_in;
ovf <= '0';
elsif op = ALU_XOR then
result := in1 xor b_in;
ovf <= '0';
else
--shifter
if in2(31) = '1' then
shiftcnt := (not in2(4 downto 0)) + 1; --right
shiftin(31 downto 0) := in1;
if ((op = ALU_SHZ) or (in1(31) = '0')) then
shiftin(63 downto 32) := (others => '0');
else
shiftin(63 downto 32) := (others => '1');
end if;
else
shiftcnt := not in2(4 downto 0); --left
if ((op = ALU_SHZ) or (in1(31) = '0')) then
shiftin(31 downto 0) := (others => '0');
else
shiftin(31 downto 0) := (others => '1');
end if;
shiftin(63 downto 31) := '0' & in1;
end if;
if shiftcnt(4) = '1' then
shiftin(47 downto 0) := shiftin(63 downto 16);
end if;
if shiftcnt(3) = '1' then
shiftin(39 downto 0) := shiftin(47 downto 8);
end if;
if shiftcnt(2) = '1' then
shiftin(35 downto 0) := shiftin(39 downto 4);
end if;
if shiftcnt(1) = '1' then
shiftin(33 downto 0) := shiftin(35 downto 2);
end if;
if shiftcnt(0) = '1' then
shiftin(31 downto 0) := shiftin(32 downto 1);
end if;
result := shiftin(31 downto 0);
ovf <= '0';
end if;
alu_out <= result;
end process;
end;
|
-------------------------------------------------------------------------------
--! @file mmSlaveConv-rtl-ea.vhd
--
--! @brief Memory mapped slave interface converter
--
--! @details The slave interface converter is fixed to a 16 bit memory mapped
--! slave, connected to a 32 bit master. The conversion also considers
--! little/big endian (gEndian).
--! Note: Tested with openmacTop entity only!
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity mmSlaveConv is
generic (
--! Endianness of interconnect
gEndian : string := "little";
--! Memory mapped master address width
gMasterAddrWidth : natural := 10
);
port (
--! Reset
iRst : in std_logic;
--! Clock
iClk : in std_logic;
-- Memory mapped master input
--! Master select
iMaster_select : in std_logic;
--! Master write
iMaster_write : in std_logic;
--! Master read
iMaster_read : in std_logic;
--! Master byteenable
iMaster_byteenable : in std_logic_vector(3 downto 0);
--! Master writedata
iMaster_writedata : in std_logic_vector(31 downto 0);
--! Master readdata
oMaster_readdata : out std_logic_vector(31 downto 0);
--! Master address (byte address)
iMaster_address : in std_logic_vector(gMasterAddrWidth-1 downto 0);
--! Master write acknowledge
oMaster_WriteAck : out std_logic;
--! Master read acknowledge
oMaster_ReadAck : out std_logic;
-- Memory mapped slave output
--! Slave select
oSlave_select : out std_logic;
--! Slave write
oSlave_write : out std_logic;
--! Slave read
oSlave_read : out std_logic;
--! Slave address (word address)
oSlave_address : out std_logic_vector(gMasterAddrWidth-1 downto 0);
--! Slave byteenable
oSlave_byteenable : out std_logic_vector(1 downto 0);
--! Slave readdata
iSlave_readdata : in std_logic_vector(15 downto 0);
--! Slave writedata
oSlave_writedata : out std_logic_vector(15 downto 0);
--! Slave acknowledge
iSlave_ack : in std_logic
);
end mmSlaveConv;
architecture rtl of mmSlaveConv is
--! Access fsm_reg type
type tAccessFsm is (
sIdle,
sDoAccess
);
--! Access type
type tAccess is (
sNone,
sDword,
sWord
);
--! Access fsm_reg current state
signal fsm_reg : tAccessFsm;
--! Access fsm_reg next state
signal fsm_next : tAccessFsm;
--! Current master access type
signal masterAccess : tAccess;
--! Counter width
constant cCounterWidth : natural := 2;
--! Counter register
signal counter_reg : std_logic_vector(cCounterWidth-1 downto 0);
--! Next counter register
signal counter_next : std_logic_vector(cCounterWidth-1 downto 0);
--! Counter register load value
signal counter_loadValue : std_logic_vector(cCounterWidth-1 downto 0);
--! Load counter register with counter_loadValue
signal counter_load : std_logic;
--! Decrement counter value by one
signal counter_decrement : std_logic;
--! counter_reg is zero
signal counter_isZero : std_logic;
--! counter_reg is one
signal counter_isOne : std_logic;
--! counter_reg is two
signal counter_isTwo : std_logic;
--! Master acknowledge
signal masterAck : std_logic;
--! Register to store slave readdata word
signal wordStore_reg : std_logic_vector(iSlave_readdata'range);
--! Next value of slave readdata word register
signal wordStore_next : std_logic_vector(wordStore_reg'range);
begin
---------------------------------------------------------------------------
-- Assign outputs
---------------------------------------------------------------------------
oSlave_select <= iMaster_select;
oSlave_write <= iMaster_write and iMaster_select;
oSlave_read <= iMaster_read and iMaster_select;
oMaster_WriteAck <= masterAck and iMaster_write and iMaster_select;
oMaster_ReadAck <= masterAck and iMaster_read and iMaster_select;
--! This process assigns the master readdata port controlled by the current
--! conversion state.
assignMasterPath : process (
iSlave_readdata, wordStore_reg,
masterAccess
)
begin
if masterAccess = sDword then
oMaster_readdata <= iSlave_readdata & wordStore_reg;
else
oMaster_readdata <= iSlave_readdata & iSlave_readdata;
end if;
end process assignMasterPath;
--! This process assigns the slave address, byteenable and writedata controlled
--! by the current conversion state.
assignSlavePath : process (
iMaster_address, iMaster_byteenable, iMaster_writedata,
counter_reg, counter_isOne,
masterAccess
)
begin
-----------------------------------------------------------------------
-- Slave address
-----------------------------------------------------------------------
--default assignment
oSlave_address <= iMaster_address;
if masterAccess = sDword then
case to_integer(unsigned(counter_reg)) is
when 0 | 2 =>
-- First word of dword access
if gEndian = "little" then
oSlave_address(1) <= cInactivated;
else
oSlave_address(1) <= cActivated;
end if;
when 1 =>
-- Second word of dword access
if gEndian = "little" then
oSlave_address(1) <= cActivated;
else
oSlave_address(1) <= cInactivated;
end if;
when others =>
null; --allowed due to default assignment
end case;
end if;
-----------------------------------------------------------------------
-- Slave byteenable
-----------------------------------------------------------------------
if masterAccess = sDword then
oSlave_byteenable <= (others => cActivated);
else
oSlave_byteenable <= iMaster_byteenable(3 downto 2) or iMaster_byteenable(1 downto 0);
end if;
-----------------------------------------------------------------------
-- Slave writedata
-----------------------------------------------------------------------
if (masterAccess = sDword and counter_isOne = cActivated) or iMaster_address(1) = cActivated then
oSlave_writedata <= iMaster_writedata(31 downto 16);
else
oSlave_writedata <= iMaster_writedata(15 downto 0);
end if;
end process assignSlavePath;
--! This process assigns the registers.
regProc : process(iRst, iClk)
begin
if iRst = cActivated then
counter_reg <= (others => cInactivated);
fsm_reg <= sIdle;
wordStore_reg <= (others => cInactivated);
elsif rising_edge(iClk) then
counter_reg <= counter_next;
fsm_reg <= fsm_next;
wordStore_reg <= wordStore_next;
end if;
end process;
--! This process assigns the register next signals.
assignRegNext : process (
iSlave_readdata, iSlave_ack,
wordStore_reg, fsm_reg, counter_reg,
counter_load, counter_loadValue, counter_decrement, counter_isZero,
counter_isTwo, masterAccess
)
begin
-- default assignments
wordStore_next <= wordStore_reg;
fsm_next <= fsm_reg;
counter_next <= counter_reg;
-----------------------------------------------------------------------
-- Counter
-----------------------------------------------------------------------
if counter_load = cActivated then
counter_next <= counter_loadValue;
elsif counter_decrement = cActivated and masterAccess = sDword then
counter_next <= std_logic_vector(unsigned(counter_reg) - 1);
end if;
-----------------------------------------------------------------------
-- Access FSM
-----------------------------------------------------------------------
if counter_isZero = cActivated then
case fsm_reg is
when sIdle =>
if masterAccess = sDword then
fsm_next <= sDoAccess;
end if;
when sDoAccess =>
if masterAccess = sNone then
fsm_next <= sIdle;
end if;
end case;
end if;
-----------------------------------------------------------------------
-- Store slave readdata word
-----------------------------------------------------------------------
if iSlave_ack = cActivated and masterAccess = sDword and counter_isTwo = cActivated then
wordStore_next <= iSlave_readdata;
end if;
end process assignRegNext;
counter_decrement <= iSlave_ack and iMaster_select;
--! This process assigns internal control signals.
assignInternal : process (
iSlave_ack,
iMaster_select, iMaster_byteenable, iMaster_read,
counter_reg, counter_isOne, masterAccess, fsm_reg, fsm_next
)
begin
-----------------------------------------------------------------------
-- Master acknowledge
-----------------------------------------------------------------------
if iSlave_ack = cActivated and masterAccess = sDword and counter_isOne = cActivated then
masterAck <= cActivated;
elsif iSlave_ack = cActivated and masterAccess = sWord then
masterAck <= cActivated;
else
masterAck <= cInactivated;
end if;
-----------------------------------------------------------------------
-- Master access state
-----------------------------------------------------------------------
if iMaster_select = cInactivated then
masterAccess <= sNone;
elsif iMaster_byteenable = "1111" then
masterAccess <= sDword;
else
masterAccess <= sWord;
end if;
-----------------------------------------------------------------------
-- Counter
-----------------------------------------------------------------------
--default
counter_isZero <= cInactivated;
counter_isOne <= cInactivated;
counter_isTwo <= cInactivated;
-- assign counter_is* signals
case to_integer(unsigned(counter_reg)) is
when 0 =>
counter_isZero <= cActivated;
when 1 =>
counter_isOne <= cActivated;
when 2 =>
counter_isTwo <= cActivated;
when others =>
null; --is allowed due to default assignment
end case;
-- assign counter load
if fsm_next = sDoAccess and fsm_reg = sIdle then
counter_load <= cActivated;
else
counter_load <= cInactivated;
end if;
-- assign counter load value
if iMaster_byteenable = "1111" and iMaster_read = cActivated then
counter_loadValue <= "10";
else
counter_loadValue <= "01";
end if;
end process assignInternal;
end rtl;
|
architecture RTL of FIFO is
begin
LABEL0 : if a = 1 generate
end generate LABEL0;
-- Simple test case
LABEL1 : if a = 1 generate
elsif a = 0 generate
elsif a = 1 generate
else generate
end generate LABEL1;
-- Test nesting
LABEL2A: if a = 1 generate
LABEL3A : if x = 0 generate
elsif y = 1 generate
else generate
end generate LABEL3A;
elsif b = 0 generate
elsif c = 1 generate
else generate
end generate LABEL2A;
-- Test multiple layers of nesting
LABEL2A: if a = 1 generate
LABEL3A : if x = 0 generate
LABEL4A : if x = 0 generate
elsif y = 1 generate
else generate
end generate LABEL4A;
elsif y = 1 generate
else generate
end generate LABEL3A;
elsif b = 0 generate
LABEL3A : if x = 0 generate
LABEL4A : if x = 0 generate
elsif y = 1 generate
else generate
end generate LABEL4A;
elsif y = 1 generate
else generate
end generate LABEL3A;
elsif c = 1 generate
LABEL3A : if x = 0 generate
LABEL4A : if x = 0 generate
elsif y = 1 generate
else generate
end generate LABEL4A;
elsif y = 1 generate
else generate
end generate LABEL3A;
else generate
LABEL3A : if x = 0 generate
LABEL4A : if x = 0 generate
elsif y = 1 generate
else generate
end generate LABEL4A;
elsif y = 1 generate
else generate
end generate LABEL3A;
end generate LABEL2A;
end architecture RTL;
|
-- $Id: tbd_serport_uart_rx.vhd 417 2011-10-22 10:30:29Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_serport_uart_rx - syn
-- Description: Wrapper for serport_uart_rx to avoid records. It
-- has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: serport_uart_rx
--
-- To test: serport_uart_rx
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 26 67 0 - t 8.17
-- 2007-10-27 92 9.1 J30 xc3s1000-4 26 67 0 - t 8.25
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 29 90 0 47 s 8.45
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 31 92 0 - s 8.25
--
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2007-10-21 91 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serport.all;
entity tbd_serport_uart_rx is -- serial port uart rx [tb design]
-- generic: CDWIDTH=5
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv5; -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit -- receiver active
);
end tbd_serport_uart_rx;
architecture syn of tbd_serport_uart_rx is
begin
UART : serport_uart_rx
generic map (
CDWIDTH => 5)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT
);
end syn;
|
---------------------------------------------------------------------
-- Filename: gh_fifo_async16_sr.vhd
--
--
-- Description:
-- an Asynchronous FIFO
--
-- Copyright (c) 2006 by George Huber
-- an OpenCores.org Project
-- free to use, but see documentation for conditions
--
-- Revision History:
-- Revision Date Author Comment
-- -------- ---------- --------- -----------
-- 1.0 12/17/06 h lefevre Initial revision
--
--------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
entity gh_fifo_async16_sr is
GENERIC (data_width: INTEGER :=8 ); -- size of data bus
port (
clk_WR : in STD_LOGIC; -- write clock
clk_RD : in STD_LOGIC; -- read clock
rst : in STD_LOGIC; -- resets counters
srst : in STD_LOGIC:='0'; -- resets counters (sync with clk_WR)
WR : in STD_LOGIC; -- write control
RD : in STD_LOGIC; -- read control
D : in STD_LOGIC_VECTOR (data_width-1 downto 0);
Q : out STD_LOGIC_VECTOR (data_width-1 downto 0);
empty : out STD_LOGIC;
full : out STD_LOGIC);
end entity;
architecture a of gh_fifo_async16_sr is
type ram_mem_type is array (15 downto 0)
of STD_LOGIC_VECTOR (data_width-1 downto 0);
signal ram_mem : ram_mem_type;
signal iempty : STD_LOGIC;
signal ifull : STD_LOGIC;
signal add_WR_CE : std_logic;
signal add_WR : std_logic_vector(4 downto 0); -- 4 bits are used to address MEM
signal add_WR_GC : std_logic_vector(4 downto 0); -- 5 bits are used to compare
signal n_add_WR : std_logic_vector(4 downto 0); -- for empty, full flags
signal add_WR_RS : std_logic_vector(4 downto 0); -- synced to read clk
signal add_RD_CE : std_logic;
signal add_RD : std_logic_vector(4 downto 0);
signal add_RD_GC : std_logic_vector(4 downto 0);
signal add_RD_GCwc : std_logic_vector(4 downto 0);
signal n_add_RD : std_logic_vector(4 downto 0);
signal add_RD_WS : std_logic_vector(4 downto 0); -- synced to write clk
signal srst_w : STD_LOGIC;
signal isrst_w : STD_LOGIC;
signal srst_r : STD_LOGIC;
signal isrst_r : STD_LOGIC;
begin
--------------------------------------------
------- memory -----------------------------
--------------------------------------------
process (clk_WR)
begin
if (rising_edge(clk_WR)) then
if ((WR = '1') and (ifull = '0')) then
ram_mem(CONV_INTEGER(add_WR(3 downto 0))) <= D;
end if;
end if;
end process;
Q <= ram_mem(CONV_INTEGER(add_RD(3 downto 0)));
-----------------------------------------
----- Write address counter -------------
-----------------------------------------
add_WR_CE <= '0' when (ifull = '1') else
'0' when (WR = '0') else
'1';
n_add_WR <= add_WR + x"1";
process (clk_WR,rst)
begin
if (rst = '1') then
add_WR <= (others => '0');
add_RD_WS <= "11000";
add_WR_GC <= (others => '0');
elsif (rising_edge(clk_WR)) then
add_RD_WS <= add_RD_GCwc;
if (srst_w = '1') then
add_WR <= (others => '0');
add_WR_GC <= (others => '0');
elsif (add_WR_CE = '1') then
add_WR <= n_add_WR;
add_WR_GC(0) <= n_add_WR(0) xor n_add_WR(1);
add_WR_GC(1) <= n_add_WR(1) xor n_add_WR(2);
add_WR_GC(2) <= n_add_WR(2) xor n_add_WR(3);
add_WR_GC(3) <= n_add_WR(3) xor n_add_WR(4);
add_WR_GC(4) <= n_add_WR(4);
else
add_WR <= add_WR;
add_WR_GC <= add_WR_GC;
end if;
end if;
end process;
full <= ifull;
ifull <= '0' when (iempty = '1') else -- just in case add_RD_WS is reset to "00000"
'0' when (add_RD_WS /= add_WR_GC) else ---- instend of "11000"
'1';
-----------------------------------------
----- Read address counter --------------
-----------------------------------------
add_RD_CE <= '0' when (iempty = '1') else
'0' when (RD = '0') else
'1';
n_add_RD <= add_RD + x"1";
process (clk_RD,rst)
begin
if (rst = '1') then
add_RD <= (others => '0');
add_WR_RS <= (others => '0');
add_RD_GC <= (others => '0');
add_RD_GCwc <= "11000";
elsif (rising_edge(clk_RD)) then
add_WR_RS <= add_WR_GC;
if (srst_r = '1') then
add_RD <= (others => '0');
add_RD_GC <= (others => '0');
add_RD_GCwc <= "11000";
elsif (add_RD_CE = '1') then
add_RD <= n_add_RD;
add_RD_GC(0) <= n_add_RD(0) xor n_add_RD(1);
add_RD_GC(1) <= n_add_RD(1) xor n_add_RD(2);
add_RD_GC(2) <= n_add_RD(2) xor n_add_RD(3);
add_RD_GC(3) <= n_add_RD(3) xor n_add_RD(4);
add_RD_GC(4) <= n_add_RD(4);
add_RD_GCwc(0) <= n_add_RD(0) xor n_add_RD(1);
add_RD_GCwc(1) <= n_add_RD(1) xor n_add_RD(2);
add_RD_GCwc(2) <= n_add_RD(2) xor n_add_RD(3);
add_RD_GCwc(3) <= n_add_RD(3) xor (not n_add_RD(4));
add_RD_GCwc(4) <= (not n_add_RD(4));
else
add_RD <= add_RD;
add_RD_GC <= add_RD_GC;
add_RD_GCwc <= add_RD_GCwc;
end if;
end if;
end process;
empty <= iempty;
iempty <= '1' when (add_WR_RS = add_RD_GC) else
'0';
----------------------------------
--- sync rest stuff --------------
--- srst is sync with clk_WR -----
--- srst_r is sync with clk_RD ---
----------------------------------
process (clk_WR,rst)
begin
if (rst = '1') then
srst_w <= '0';
isrst_r <= '0';
elsif (rising_edge(clk_WR)) then
isrst_r <= srst_r;
if (srst = '1') then
srst_w <= '1';
elsif (isrst_r = '1') then
srst_w <= '0';
end if;
end if;
end process;
process (clk_RD,rst)
begin
if (rst = '1') then
srst_r <= '0';
isrst_w <= '0';
elsif (rising_edge(clk_RD)) then
isrst_w <= srst_w;
if (isrst_w = '1') then
srst_r <= '1';
else
srst_r <= '0';
end if;
end if;
end process;
end architecture;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY blk_mem_gen_1 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END blk_mem_gen_1;
ARCHITECTURE blk_mem_gen_1_arch OF blk_mem_gen_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_1_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(18 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_1_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_1_arch : ARCHITECTURE IS "blk_mem_gen_1,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_1_arch: ARCHITECTURE IS "blk_mem_gen_1,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_1.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=307200,C_READ_DEPTH_A=307200,C_ADDRA_WIDTH=19,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=307200,C_READ_DEPTH_B=307200,C_ADDRB_WIDTH=19,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=103,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 16.887376 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_1.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 307200,
C_READ_DEPTH_A => 307200,
C_ADDRA_WIDTH => 19,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 307200,
C_READ_DEPTH_B => 307200,
C_ADDRB_WIDTH => 19,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "103",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 16.887376 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_1_arch;
|
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
library work;
use work.mips_defs.ALL;
entity decoder is
port (op : in std_logic_vector(5 downto 0);
func : in std_logic_vector(5 downto 0);
reg_write : out std_logic;
mem_to_reg : out std_logic;
mem_read : out std_logic;
mem_write : out std_logic;
branch : out branch_type;
alucontrol : out alucontrol_type;
ovf_en : out std_logic;
cmp : out compare_type;
alu_src : out std_logic;
reg_dst : out std_logic;
imm_extend : out extend_type;
link : out std_logic;
rd31 : out std_logic);
end entity decoder;
architecture rtl of decoder is
begin
process (op, func)
begin
case op is
when OP_SPECIAL =>
reg_write <= '1';
mem_to_reg <= '0';
mem_read <= '0';
mem_write <= '0';
case func is
when FUNC_SLL =>
ovf_en <= '0';
alucontrol <= ALU_SLL;
branch <= NO_BRANCH;
link <= '0';
when FUNC_SRL =>
ovf_en <= '0';
alucontrol <= ALU_SRL;
branch <= NO_BRANCH;
link <= '0';
when FUNC_JR =>
ovf_en <= '0';
alucontrol <= ALU_SLL;
branch <= JUMP_REG;
link <= '0';
when FUNC_JALR =>
ovf_en <= '0';
alucontrol <= ALU_BPLUS4;
branch <= JUMP_REG;
link <= '1';
when FUNC_ADD =>
ovf_en <= '1';
alucontrol <= ALU_ADD;
branch <= NO_BRANCH;
link <= '0';
when FUNC_ADDU =>
ovf_en <= '0';
alucontrol <= ALU_ADD;
branch <= NO_BRANCH;
link <= '0';
when FUNC_SUB =>
ovf_en <= '1';
alucontrol <= ALU_SUB;
branch <= NO_BRANCH;
link <= '0';
when FUNC_SUBU =>
ovf_en <= '0';
alucontrol <= ALU_SUB;
branch <= NO_BRANCH;
link <= '0';
when FUNC_AND =>
ovf_en <= '0';
alucontrol <= ALU_AND;
branch <= NO_BRANCH;
link <= '0';
when FUNC_OR =>
ovf_en <= '0';
alucontrol <= ALU_OR;
branch <= NO_BRANCH;
link <= '0';
when FUNC_XOR =>
ovf_en <= '0';
alucontrol <= ALU_XOR;
branch <= NO_BRANCH;
link <= '0';
when FUNC_NOR =>
ovf_en <= '0';
alucontrol <= ALU_NOR;
branch <= NO_BRANCH;
link <= '0';
when FUNC_SLT =>
ovf_en <= '0';
alucontrol <= ALU_SLT;
branch <= NO_BRANCH;
link <= '0';
when FUNC_SLTU =>
ovf_en <= '0';
alucontrol <= ALU_SLTU;
branch <= NO_BRANCH;
link <= '0';
when others =>
ovf_en <= '0';
alucontrol <= ALU_SLL;
branch <= NO_BRANCH;
link <= '0';
end case;
alu_src <= '0';
reg_dst <= '1';
cmp <= CMP_EQUAL;
imm_extend <= ZERO_EXTEND;
rd31 <= '0';
when OP_LW =>
reg_write <= '1';
mem_to_reg <= '1';
mem_read <= '1';
mem_write <= '0';
branch <= NO_BRANCH;
alu_src <= '1';
reg_dst <= '0';
alucontrol <= ALU_ADD;
ovf_en <= '0';
cmp <= CMP_EQUAL;
imm_extend <= SIGN_EXTEND;
link <= '0';
rd31 <= '0';
when OP_SW =>
reg_write <= '0';
mem_to_reg <= '-';
mem_read <= '0';
mem_write <= '1';
branch <= NO_BRANCH;
alu_src <= '1';
reg_dst <= '-';
alucontrol <= ALU_ADD;
ovf_en <= '0';
cmp <= CMP_EQUAL;
imm_extend <= SIGN_EXTEND;
link <= '0';
rd31 <= '0';
when OP_BEQ =>
reg_write <= '0';
mem_to_reg <= '-';
mem_read <= '0';
mem_write <= '0';
branch <= BRANCH_COND;
alu_src <= '0';
reg_dst <= '-';
alucontrol <= ALU_SUB;
ovf_en <= '0';
cmp <= CMP_EQUAL;
imm_extend <= SIGN_EXTEND;
link <= '0';
rd31 <= '0';
when OP_BNE =>
reg_write <= '0';
mem_to_reg <= '-';
mem_read <= '0';
mem_write <= '0';
branch <= BRANCH_COND;
alu_src <= '0';
reg_dst <= '-';
alucontrol <= ALU_SUB;
ovf_en <= '0';
cmp <= CMP_NOT_EQUAL;
imm_extend <= SIGN_EXTEND;
link <= '0';
rd31 <= '0';
when OP_ADDI =>
reg_write <= '1';
mem_to_reg <= '0';
mem_read <= '0';
mem_write <= '0';
branch <= NO_BRANCH;
alu_src <= '1';
reg_dst <= '0';
alucontrol <= ALU_ADD;
ovf_en <= '1';
cmp <= CMP_EQUAL;
imm_extend <= SIGN_EXTEND;
link <= '0';
rd31 <= '0';
when OP_ANDI =>
reg_write <= '1';
mem_to_reg <= '0';
mem_read <= '0';
mem_write <= '0';
branch <= NO_BRANCH;
alu_src <= '1';
reg_dst <= '0';
alucontrol <= ALU_AND;
ovf_en <= '0';
cmp <= CMP_EQUAL;
imm_extend <= ZERO_EXTEND;
link <= '0';
rd31 <= '0';
when OP_ORI =>
reg_write <= '1';
mem_to_reg <= '0';
mem_read <= '0';
mem_write <= '0';
branch <= NO_BRANCH;
alu_src <= '1';
reg_dst <= '0';
alucontrol <= ALU_OR;
ovf_en <= '0';
cmp <= CMP_EQUAL;
imm_extend <= ZERO_EXTEND;
link <= '0';
rd31 <= '0';
when OP_LUI =>
reg_write <= '1';
mem_to_reg <= '0';
mem_read <= '0';
mem_write <= '0';
branch <= NO_BRANCH;
alu_src <= '1';
reg_dst <= '0';
alucontrol <= ALU_OR;
ovf_en <= '0';
cmp <= CMP_EQUAL;
imm_extend <= SHIFT16_EXTEND;
link <= '0';
rd31 <= '0';
when OP_ADDIU =>
reg_write <= '1';
mem_to_reg <= '0';
mem_read <= '0';
mem_write <= '0';
branch <= NO_BRANCH;
alu_src <= '1';
reg_dst <= '0';
alucontrol <= ALU_ADD;
ovf_en <= '0';
cmp <= CMP_EQUAL;
imm_extend <= SIGN_EXTEND;
link <= '0';
rd31 <= '0';
when OP_J =>
reg_write <= '0';
mem_to_reg <= '-';
mem_read <= '0';
mem_write <= '0';
branch <= JUMP_IMM;
alu_src <= '-';
reg_dst <= '-';
alucontrol <= ALU_SLL;
ovf_en <= '-';
cmp <= CMP_EQUAL;
imm_extend <= ZERO_EXTEND;
link <= '0';
rd31 <= '0';
when OP_JAL =>
reg_write <= '1';
mem_to_reg <= '0';
mem_read <= '0';
mem_write <= '0';
branch <= JUMP_IMM;
alu_src <= '0';
reg_dst <= '1';
alucontrol <= ALU_BPLUS4;
ovf_en <= '0';
cmp <= CMP_EQUAL;
imm_extend <= ZERO_EXTEND;
link <= '1';
rd31 <= '1';
when others =>
reg_write <= '-';
mem_to_reg <= '-';
mem_read <= '-';
mem_write <= '-';
branch <= NO_BRANCH;
alu_src <= '-';
reg_dst <= '-';
alucontrol <= ALU_SLL;
ovf_en <= '-';
cmp <= CMP_EQUAL;
imm_extend <= ZERO_EXTEND;
link <= '0';
rd31 <= '0';
end case;
end process;
end architecture rtl;
|
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: ibm1050.vhd
-- Creation Date: 21:17:39 2005-04-18
-- Description:
-- 1050 (Console Typewriter) attachment
--
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release - no Tilt/Rotate to ASCII conversion on printing or handling
-- of Shift-Up or Shift-Down, also no ASCII to key-code conversion on input
-- (all this is handled inside the CPU)
---------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.Buses_package.all;
use UNISIM.vcomponents.all;
use work.all;
entity ibm1050 is
Port (
SerialIn : inout PCH_CONN; -- Data lines in to CPU
SerialOut : in RDR_CONN; -- Data lines out of CPU
SerialControl : in CONN_1050; -- Control lines out of CPU
-- Serial I/O
serialInput : in Serial_Input_Lines;
serialOutput : out Serial_Output_Lines;
-- 50Mhz clock
clk : in std_logic
);
end ibm1050;
architecture FMD of ibm1050 is
signal SerialBusUngated : STD_LOGIC_VECTOR(7 downto 0);
signal RxDataAvailable : STD_LOGIC;
signal TxBufferEmpty : STD_LOGIC;
signal serialOutputByte : STD_LOGIC_VECTOR(7 downto 0);
signal serialOutputStrobe : STD_LOGIC := '0';
signal RxAck, PunchGate : STD_LOGIC;
signal resetSerial : STD_LOGIC := '0';
type printerStateType is (waitForEnable,printerReset,printerEnabled,printCharacter,waitForCharacter,waitFree,printCR,waitForCR,printLF,waitForLF);
signal printerState : printerStateType := waitForEnable;
signal RDR_1_CLUTCH_timer : STD_LOGIC_VECTOR(15 downto 0);
begin
Printer: process (clk)
begin
if rising_edge(clk) then
case printerState is
when waitForEnable =>
serialIn.HOME_RDR_STT_LCH <= '0'; -- Not running
serialIn.RDR_1_CLUTCH_1050 <= '0'; -- Not ready to receive a character
serialOutputStrobe <= '0';
if (serialControl.HOME_RDR_START='1') then
resetSerial <= '1';
printerState <= printerReset;
elsif (serialControl.CARR_RETURN_AND_LINE_FEED='1') then
printerState <= printCR;
end if;
when printerReset =>
resetSerial <= '0';
printerState <= printerEnabled;
when printerEnabled =>
serialIn.HOME_RDR_STT_LCH <= '1'; -- Running
serialIn.RDR_1_CLUTCH_1050 <= TxBufferEmpty; -- Ready to receive a character
if (serialControl.HOME_RDR_START='0') then
printerState <= waitForEnable;
elsif (serialOut.RD_STROBE='1') then
printerState <= printCharacter;
elsif (serialControl.CARR_RETURN_AND_LINE_FEED='1') then
printerState <= printCR;
end if;
when printCharacter =>
serialIn.RDR_1_CLUTCH_1050 <= '0'; -- Not ready for another character
serialOutputByte <= '0' & SerialOut.RDR_BITS; -- Here we could translate from TILT/ROTATE to ASCII
serialOutputStrobe <= '1';
printerState <= waitForCharacter;
RDR_1_CLUTCH_TIMER <= x"9C40"; -- 9C40 = 40000 = 800us
when waitForCharacter =>
-- Need to wait in this state for long enough to guarantee that
-- RDR_1_CLUTCH is still low at Y_TIME to reset ALLOW_STROBE latch
serialOutputStrobe <= '0';
if (serialOut.RD_STROBE='0') then
RDR_1_CLUTCH_timer <= RDR_1_CLUTCH_timer - "0000000000000001";
if (RDR_1_CLUTCH_timer="0000000000000000") then
printerState <= printerEnabled;
end if;
end if;
when printCR =>
if (TxBufferEmpty='1') then
serialOutputByte <= "00001101"; -- CR
serialOutputStrobe <= '1';
printerState <= waitForCR;
end if;
when waitForCR =>
serialOutputStrobe <= '0';
printerState <= printLF;
when printLF =>
if (TxBufferEmpty='1') then
serialOutputByte <= "00001010"; -- LF
serialOutputStrobe <= '1';
printerState <= waitForLF;
end if;
when waitForLF =>
serialOutputStrobe <= '0';
if (serialControl.CARR_RETURN_AND_LINE_FEED='0') then -- Wait for CRLF to drop
if (serialControl.HOME_RDR_START='0') then
printerState <= waitForEnable;
else
printerState <= printerEnabled;
end if;
end if;
when others =>
printerState <= waitForEnable;
end case;
end if;
end process Printer;
serial_port : entity RS232RefComp port map(
RST => '0', --Master Reset
CLK => clk,
-- Rx (PCH)
RXD => SerialInput.serialRx,
RDA => RxDataAvailable, -- Rx data available
PE => open, -- Parity Error Flag
FE => open, -- Frame Error Flag
OE => open, -- Overwrite Error Flag
DBOUT => SerialBusUngated, -- Rx data (needs to be 0 when RDA=0)
RD => RxAck, -- Read strobe
-- Tx (RDR)
TXD => serialOutput.serialTx,
TBE => TxBufferEmpty, -- Tx buffer empty
DBIN => serialOutputByte, -- Tx data
WR => serialOutputStrobe -- Write Strobe
);
-- Make incoming data 0 when nothing is available
SerialIn.PCH_BITS <= SerialBusUngated(6 downto 0) when PunchGate='1' else "0000000";
PunchStrobeSS : entity SS port map (clk=>clk, count=>2500, D=>RxDataAvailable, Q=>RxAck); -- 50us or so
SerialIn.PCH_1_CLUTCH_1050 <= RxAck;
PunchGateSS : entity SS port map (clk=>clk, count=>3000, D=>RxDataAvailable, Q=>PunchGate); -- A bit more than 50us so Read Interlock is reset after PCH_1_CLUTCH drops
SerialIn.CPU_CONNECTED <= '1'; -- 1050 always on-line
SerialIn.HOME_OUTPUT_DEV_RDY <= '1'; -- Printer always ready
SerialIn.RDR_2_READY <= '0';
-- SerialIn.HOME_RDR_STT_LCH <= SerialControl.HOME_RDR_START;
SerialIn.REQ_KEY <= '0';
SerialOutput.RTS <= '1';
SerialOutput.DTR <= '1';
end FMD;
|
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: BRAM_SYNC_TDP_TB
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BRAM_SYNC_TDP_TB is
end BRAM_SYNC_TDP_TB;
architecture behavior of BRAM_SYNC_TDP_TB is
-- CLK and RST
signal CLK : STD_LOGIC := '0';
signal WE_A : STD_LOGIC := '0';
-- Block memory signals
signal ADDR_A : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
signal DATAIN_A : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal DATAOUT_A : STD_LOGIC_VECTOR(15 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
begin
uut : entity work.BRAM_SYNC_TDP
port map (
-- Port A
CLK => CLK,
WE_A => WE_A,
ADDR_A => ADDR_A,
DATAIN_A => DATAIN_A,
DATAOUT_A => DATAOUT_A,
-- Port B
WE_A => '0',
ADDR_A => (others => '0'),
DATAIN_A => (others => '0'),
DATAOUT_A => open
);
clk_process : process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
sim_proc : process
begin
wait for 100 ns;
wait until rising_edge(CLK);
WE_A <= '1';
ADDR_A <= "0000011111";
DATAIN_A <= "1111111111000000";
wait until rising_edge(CLK);
WE_A <= '0';
ADDR_A <= "0000011110";
wait until rising_edge(CLK);
WE_A <= '0';
ADDR_A <= "0000011111";
wait;
end process;
end;
|
entity FIFO is
port (
I_WR_EN : in std_logic;
I_RD_EN : in std_logic; -- Some comment
I_DATA : in std_logic_vector(15 downto 0);
O_DATA : out std_logic_vector(15 downto 0);
O_RD_FULL : out std_logic;
O_WR_FULL : out std_logic;
O_RD_ALMOST_FULL : out std_logic;
O_WR_ALMOST_FULL : out std_logic -- Some comment
);
end entity FIFO;
|
library ieee;
use ieee.std_logic_1164.all;
entity sr_latch is
port (
s : in std_logic;
r : in std_logic;
q : inout std_logic;
q_n : inout std_logic);
end sr_latch;
architecture behavioral of sr_latch is
begin
q <= r nand q_n;
q_n <= s nand q;
end behavioral;
|
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004/02/18 11:41:48 rherveille Exp $
--
-- $Date: 2004/02/18 11:41:48 $
-- $Revision: 1.5 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_byte_ctrl.vhd,v $
-- Revision 1.5 2004/02/18 11:41:48 rherveille
-- Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
--
-- Revision 1.4 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.3 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.2 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
-- Modified by Jan Andersson ([email protected]:.
-- Changed std_logic_arith to numeric_std.
-- Propagate filter generic
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity i2c_master_byte_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_byte_ctrl;
architecture structural of i2c_master_byte_ctrl is
component i2c_master_bit_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command done
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_bit_ctrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
signal al : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
-- Added init value to dcnt to prevent simulation meta-value
-- - [email protected]
-- removed init value as it is not compatible with Formality
-- - [email protected]
signal dcnt : std_logic_vector(2 downto 0)
-- pragma translate_off
:= (others => '0')
-- pragma translate_on
; -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: i2c_master_bit_ctrl
generic map (filter, dynfilt)
port map(
clk => clk,
rst => rst,
nReset => nReset,
ena => ena,
clk_cnt => clk_cnt,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => al,
din => core_txd,
dout => core_rxd,
filt => filt,
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
i2c_al <= al;
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write or stop) and not host_ack;
-- assign Dout output to shift-register
dout <= sr;
-- generate shift register
shift_register: process(clk, nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt: process(clk, nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = "000") else '0';
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or al = '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start = '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
report ("Byte controller entered illegal state.");
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural;
|
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004/02/18 11:41:48 rherveille Exp $
--
-- $Date: 2004/02/18 11:41:48 $
-- $Revision: 1.5 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_byte_ctrl.vhd,v $
-- Revision 1.5 2004/02/18 11:41:48 rherveille
-- Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
--
-- Revision 1.4 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.3 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.2 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
-- Modified by Jan Andersson ([email protected]:.
-- Changed std_logic_arith to numeric_std.
-- Propagate filter generic
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity i2c_master_byte_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_byte_ctrl;
architecture structural of i2c_master_byte_ctrl is
component i2c_master_bit_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command done
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_bit_ctrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
signal al : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
-- Added init value to dcnt to prevent simulation meta-value
-- - [email protected]
-- removed init value as it is not compatible with Formality
-- - [email protected]
signal dcnt : std_logic_vector(2 downto 0)
-- pragma translate_off
:= (others => '0')
-- pragma translate_on
; -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: i2c_master_bit_ctrl
generic map (filter, dynfilt)
port map(
clk => clk,
rst => rst,
nReset => nReset,
ena => ena,
clk_cnt => clk_cnt,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => al,
din => core_txd,
dout => core_rxd,
filt => filt,
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
i2c_al <= al;
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write or stop) and not host_ack;
-- assign Dout output to shift-register
dout <= sr;
-- generate shift register
shift_register: process(clk, nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt: process(clk, nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = "000") else '0';
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or al = '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start = '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
report ("Byte controller entered illegal state.");
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural;
|
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004/02/18 11:41:48 rherveille Exp $
--
-- $Date: 2004/02/18 11:41:48 $
-- $Revision: 1.5 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_byte_ctrl.vhd,v $
-- Revision 1.5 2004/02/18 11:41:48 rherveille
-- Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
--
-- Revision 1.4 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.3 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.2 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
-- Modified by Jan Andersson ([email protected]:.
-- Changed std_logic_arith to numeric_std.
-- Propagate filter generic
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity i2c_master_byte_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_byte_ctrl;
architecture structural of i2c_master_byte_ctrl is
component i2c_master_bit_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command done
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_bit_ctrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
signal al : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
-- Added init value to dcnt to prevent simulation meta-value
-- - [email protected]
-- removed init value as it is not compatible with Formality
-- - [email protected]
signal dcnt : std_logic_vector(2 downto 0)
-- pragma translate_off
:= (others => '0')
-- pragma translate_on
; -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: i2c_master_bit_ctrl
generic map (filter, dynfilt)
port map(
clk => clk,
rst => rst,
nReset => nReset,
ena => ena,
clk_cnt => clk_cnt,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => al,
din => core_txd,
dout => core_rxd,
filt => filt,
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
i2c_al <= al;
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write or stop) and not host_ack;
-- assign Dout output to shift-register
dout <= sr;
-- generate shift register
shift_register: process(clk, nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt: process(clk, nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = "000") else '0';
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or al = '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start = '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
report ("Byte controller entered illegal state.");
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural;
|
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004/02/18 11:41:48 rherveille Exp $
--
-- $Date: 2004/02/18 11:41:48 $
-- $Revision: 1.5 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_byte_ctrl.vhd,v $
-- Revision 1.5 2004/02/18 11:41:48 rherveille
-- Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
--
-- Revision 1.4 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.3 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.2 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
-- Modified by Jan Andersson ([email protected]:.
-- Changed std_logic_arith to numeric_std.
-- Propagate filter generic
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity i2c_master_byte_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_byte_ctrl;
architecture structural of i2c_master_byte_ctrl is
component i2c_master_bit_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command done
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_bit_ctrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
signal al : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
-- Added init value to dcnt to prevent simulation meta-value
-- - [email protected]
-- removed init value as it is not compatible with Formality
-- - [email protected]
signal dcnt : std_logic_vector(2 downto 0)
-- pragma translate_off
:= (others => '0')
-- pragma translate_on
; -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: i2c_master_bit_ctrl
generic map (filter, dynfilt)
port map(
clk => clk,
rst => rst,
nReset => nReset,
ena => ena,
clk_cnt => clk_cnt,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => al,
din => core_txd,
dout => core_rxd,
filt => filt,
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
i2c_al <= al;
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write or stop) and not host_ack;
-- assign Dout output to shift-register
dout <= sr;
-- generate shift register
shift_register: process(clk, nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt: process(clk, nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = "000") else '0';
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or al = '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start = '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
report ("Byte controller entered illegal state.");
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural;
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3, -- comment
G_GEN_2 => 4, -- comment
G_GEN_3 => 5 -- comment
)
port map (
PORT_1 => w_port_1, -- comment
PORT_2 => w_port_2, -- comment
PORT_3 => w_port_3 -- comment
);
-- Violations below
U_INST1 : INST1
generic map (
G_GEN_1 => 3, -- comment
G_GEN_2 => 4, -- comment
G_GEN_3 => 5 -- comment
)
port map (
PORT_1 => w_port_1, -- comment
PORT_2 => w_port_2,--comment
PORT_3 => w_port_3 -- comment
);
end architecture ARCH;
|
------------------------------------------------------------
-- Receiver (with buffer) component for comport-
-- 1) Stays idle until start bit occurs. Then eceive 8-bit
-- one by one. At stop bit, store the 8 bits in buffer,
-- send notification to the other system. The contents
-- in the buffer remains unchnaged until the next stop
-- bit
-- 2) Sync clock at every start bit
-- States
-- STATE_IDLE
-- STATE_RECEIVING
-- STATE_END_BIT
-- STATE_IDLE
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rs232_receiver is
port(
clock_50MHz: in std_logic;
input: in std_logic; -- connected to comport input pin
receive_data: out std_logic_vector(7 downto 0);
ack: out std_logic -- a pulse notification
);
end rs232_receiver;
architecture arch of rs232_receiver is
type state_type is (STATE_IDLE,
STATE_RECEIVING, STATE_END_BIT,
STATE_ACKING);
signal state: state_type;
signal power_on: std_logic := '0';
signal bit_count: integer;
signal cycle_count: integer;
signal ack_count: integer;
begin
process(clock_50MHz, input)
begin
if(rising_edge(clock_50MHz)) then
if(power_on = '0') then -- init
power_on <= '1';
ack <= '0';
state <= STATE_IDLE;
receive_data <= "00000000";
ack_count <= 0;
else -- non-init
case state is
when STATE_IDLE =>
ack <= '0';
ack_count <= 0;
if(input = '0') then
state <= STATE_RECEIVING;
bit_count <= 0;
cycle_count <= 0;
end if;
when STATE_RECEIVING =>
cycle_count <= cycle_count + 1;
ack <= '0';
if(cycle_count=651 or cycle_count=1085 or cycle_count=1519
or cycle_count=1953 or cycle_count=2387 or cycle_count=2821
or cycle_count=3255 or cycle_count=3689) then
receive_data(bit_count) <= input;
bit_count <= bit_count + 1;
elsif (cycle_count > 3689) then
state <= STATE_END_BIT;
end if;
when STATE_END_BIT =>
cycle_count <= cycle_count + 1;
if (cycle_count > 4123 and input = '1') then
state <= STATE_ACKING;
end if;
when STATE_ACKING =>
ack <= '1';
ack_count <= ack_count + 1;
if (ack_count > 500) then
state <= STATE_IDLE;
end if;
end case;
end if; -- init / non-init
end if; -- rising edge
end process;
end arch;
|
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity spi_reader_tb is
end entity ;
architecture arch of spi_reader_tb is
signal clock : std_logic := '1' ;
signal sclk : std_logic ;
signal miso : std_logic := '0' ;
signal mosi : std_logic ;
signal enx : std_logic ;
signal reset_out : std_logic ;
begin
clock <= not clock after 1 ns ;
U_spi_reader : entity work.spi_reader
port map (
clock => clock,
sclk => sclk,
miso => miso,
mosi => mosi,
enx => enx,
reset_out => reset_out
) ;
end architecture ;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
entity vga_clkgen is
port (
resetn : in std_logic;
sel : in std_logic_vector(1 downto 0);
clk25 : in std_logic;
clk50 : in std_logic;
clkout : out std_logic
);
end;
architecture struct of vga_clkgen is
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal clk65, clksel : std_logic;
begin
-- 65 MHz clock generator
clkgen65 : clkmul_virtex2 generic map (13, 5) port map (resetn, clk25, clk65);
clk_select : process (clk25, clk50, clk65, sel)
begin
case sel is
when "00" => clksel <= clk25;
when "01" => clksel <= clk50;
when "10" => clksel <= clk65;
when others => clksel <= '0';
end case;
end process;
bufg1 : BUFG port map (I => clksel, O => clkout);
end;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:axi_nic:1.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_axi_nic_00_2 IS
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END sys_axi_nic_00_2;
ARCHITECTURE sys_axi_nic_00_2_arch OF sys_axi_nic_00_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_axi_nic_00_2_arch: ARCHITECTURE IS "yes";
COMPONENT nic_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER;
C_S00_AXI_ADDR_WIDTH : INTEGER;
USE_1K_NOT_4K_FIFO_DEPTH : BOOLEAN
);
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END COMPONENT nic_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sys_axi_nic_00_2_arch: ARCHITECTURE IS "nic_v1_0,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sys_axi_nic_00_2_arch : ARCHITECTURE IS "sys_axi_nic_00_2,nic_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF RX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF RX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF TX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF TX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF TX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RREADY";
BEGIN
U0 : nic_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 5,
USE_1K_NOT_4K_FIFO_DEPTH => false
)
PORT MAP (
RX_DATA => RX_DATA,
RX_VALID => RX_VALID,
RX_READY => RX_READY,
TX_DATA => TX_DATA,
TX_VALID => TX_VALID,
TX_READY => TX_READY,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready
);
END sys_axi_nic_00_2_arch;
|
-----------------------------------------------------------------------------------------
-- --
-- This file is part of the CAPH Compiler distribution --
-- http://caph.univ-bpclermont.fr --
-- --
-- Jocelyn SEROT --
-- [email protected] --
-- --
-- Copyright 2011-2015 Jocelyn SEROT. All rights reserved. --
-- This file is distributed under the terms of the GNU Library General Public License --
-- with the special exception on linking described in file ../LICENSE. --
-- --
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
entity stream_out is
generic ( filename: string := "vhdl_result.dat"; size: integer := 10; period: integer := 1 );
port ( empty : in std_logic;
din : in std_logic_vector(size-1 downto 0);
rd : out std_logic;
clk : in std_logic;
rst : in std_logic
);
end stream_out;
architecture beh of stream_out is
begin
process
file output_file: text;
variable file_line: line;
variable token: integer;
variable eof: boolean;
begin
if ( period < 1 ) then
report "stream_out(" & filename & ") : period < 1 !"
severity error;
end if;
eof := false;
file_open(output_file,filename,WRITE_MODE);
while not eof loop
wait until rising_edge(clk);
if ( empty = '0' ) then
write (file_line,to_bitvector(din));
writeline (output_file,file_line);
end if;
end loop; -- TODO: set eof when run is completed ?
file_close(output_file);
wait;
end process;
rd <= not(empty);
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc464.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00464ent IS
END c03s02b01x01p19n01i00464ent;
ARCHITECTURE c03s02b01x01p19n01i00464arch OF c03s02b01x01p19n01i00464ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
constant C66: boolean_vector_range := (others => true);
function complex_scalar(s : boolean_vector_range) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return boolean_vector_range is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : boolean_vector_range;
signal S2 : boolean_vector_range;
signal S3 : boolean_vector_range:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00464"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00464 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00464arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc464.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00464ent IS
END c03s02b01x01p19n01i00464ent;
ARCHITECTURE c03s02b01x01p19n01i00464arch OF c03s02b01x01p19n01i00464ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
constant C66: boolean_vector_range := (others => true);
function complex_scalar(s : boolean_vector_range) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return boolean_vector_range is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : boolean_vector_range;
signal S2 : boolean_vector_range;
signal S3 : boolean_vector_range:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00464"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00464 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00464arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc464.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00464ent IS
END c03s02b01x01p19n01i00464ent;
ARCHITECTURE c03s02b01x01p19n01i00464arch OF c03s02b01x01p19n01i00464ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
constant C66: boolean_vector_range := (others => true);
function complex_scalar(s : boolean_vector_range) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return boolean_vector_range is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : boolean_vector_range;
signal S2 : boolean_vector_range;
signal S3 : boolean_vector_range:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00464"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00464 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00464arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity MMX_GRT_8b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of MMX_GRT_8b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
--process
--begin
-- wait for 1 ns;
-- printmsg("(IMS) MMX 8bis GRT RESSOURCE : ALLOCATION OK !");
-- wait;
--end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp2 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp3 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp4 : STD_LOGIC_VECTOR(7 downto 0);
begin
if( UNSIGNED(INPUT_1( 7 downto 0)) > UNSIGNED(INPUT_2( 7 downto 0)) ) then rTemp1 := "11111111"; else rTemp1 := "00000000"; end if;
if( UNSIGNED(INPUT_1(15 downto 8)) > UNSIGNED(INPUT_2(15 downto 8)) ) then rTemp2 := "11111111"; else rTemp2 := "00000000"; end if;
if( UNSIGNED(INPUT_1(23 downto 16)) > UNSIGNED(INPUT_2(23 downto 16)) ) then rTemp3 := "11111111"; else rTemp3 := "00000000"; end if;
if( UNSIGNED(INPUT_1(31 downto 24)) > UNSIGNED(INPUT_2(31 downto 24)) ) then rTemp4 := "11111111"; else rTemp4 := "00000000"; end if;
OUTPUT_1 <= (rTemp4 & rTemp3 & rTemp2 & rTemp1);
end process;
-------------------------------------------------------------------------
end;
|
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_cmd_nano
-- Date:2015-02-14
-- Author: Gideon
-- Description: I/O registers for controlling commands directly, 16 bits for
-- attachment to nano cpu.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.usb_cmd_pkg.all;
entity usb_cmd_nano is
port (
clock : in std_logic;
reset : in std_logic;
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_wdata : in std_logic_vector(15 downto 0);
io_rdata : out std_logic_vector(15 downto 0);
cmd_req : out t_usb_cmd_req;
cmd_resp : in t_usb_cmd_resp );
end entity;
architecture arch of usb_cmd_nano is
signal done_latch : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if cmd_resp.done = '1' then
cmd_req.request <= '0';
done_latch <= '1';
end if;
if io_write = '1' then
case io_addr is
when X"60" => -- command request
cmd_req.request <= '1';
done_latch <= '0';
cmd_req.togglebit <= io_wdata(11);
--cmd_req.do_split <= io_wdata(7);
cmd_req.do_data <= io_wdata(6);
cmd_req.command <= c_usb_commands_decoded(to_integer(unsigned(io_wdata(2 downto 0))));
when X"61" => -- data buffer control
cmd_req.buffer_index <= unsigned(io_wdata(15 downto 14));
cmd_req.no_data <= io_wdata(13);
cmd_req.data_length(9 downto 0) <= unsigned(io_wdata(9 downto 0));
when X"62" => -- device/endpoint
cmd_req.device_addr <= unsigned(io_wdata(14 downto 8));
cmd_req.endp_addr <= unsigned(io_wdata(3 downto 0));
when X"63" => -- split info
cmd_req.do_split <= io_wdata(15);
cmd_req.split_hub_addr <= unsigned(io_wdata(14 downto 8));
cmd_req.split_port_addr <= unsigned(io_wdata(3 downto 0));
cmd_req.split_sc <= io_wdata(7);
cmd_req.split_sp <= io_wdata(6);
cmd_req.split_et <= io_wdata(5 downto 4);
when others =>
null;
end case;
end if;
if reset='1' then
done_latch <= '0';
cmd_req.request <= '0';
end if;
end if;
end process;
process(cmd_resp, done_latch)
begin
io_rdata(15) <= done_latch;
io_rdata(14 downto 12) <= std_logic_vector(to_unsigned(t_usb_result'pos(cmd_resp.result), 3));
io_rdata(11) <= cmd_resp.togglebit;
io_rdata(10) <= cmd_resp.no_data;
io_rdata(9 downto 0) <= std_logic_vector(cmd_resp.data_length(9 downto 0));
end process;
end arch;
|
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity ccf_operation is
port(
flags_in: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_ccf_operation of ccf_operation is
begin
-- A point of disagreement has been found between the Z80 user manual
-- and Lance Levinthal's book entitled "Z80 Assembly Language Programming".
-- The Z80 user manual says the half-carry bit gets the previous carry;
-- Levinthal says the half-carry bit is unchanged. For now, go with
-- Levinthal's version as the Z80 users manual is inconsistent with
-- itself on other instructions. At this time, no such inconsistencies
-- have been found with Levinthal's work.
flags_out <= ( carry_bit => not flags_in(carry_bit),
half_carry_bit => flags_in(carry_bit),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity sll8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_sll8bit of sll8bit is
signal sll_result: std_logic_vector(7 downto 0);
begin
-- This operation is not documented by Zilog, but seems to work in their
-- finished chip. This code may not work the same way as the Z80 hardware
-- works. The functionality is assumed from the SRL instruction.
sll_result <= operand(6 downto 0) & '0';
output <= sll_result;
flags_out <= ( carry_bit => operand(7),
zero_bit => not (sll_result(7) or sll_result(6) or sll_result(5) or sll_result(4) or
sll_result(3) or sll_result(2) or sll_result(1) or sll_result(0)),
parity_overflow_bit => not (sll_result(7) xor sll_result(6) xor sll_result(5) xor
sll_result(4) xor sll_result(3) xor sll_result(2) xor
sll_result(1) xor sll_result(0)),
sign_bit => operand(6),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity srl8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_srl8bit of srl8bit is
signal srl_result: std_logic_vector(7 downto 0);
begin
srl_result <= '0' & operand(7 downto 1);
output <= srl_result;
flags_out <= ( carry_bit => operand(0),
zero_bit => not (srl_result(7) or srl_result(6) or srl_result(5) or srl_result(4) or
srl_result(3) or srl_result(2) or srl_result(1) or srl_result(0)),
parity_overflow_bit => not (srl_result(7) xor srl_result(6) xor srl_result(5) xor
srl_result(4) xor srl_result(3) xor srl_result(2) xor
srl_result(1) xor srl_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity and8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_and8bit of and8bit is
signal and_result: std_logic_vector(7 downto 0);
begin
and_result <= operand1 and operand2;
flags_out <= ( sign_bit => and_result(7),
zero_bit => not (and_result(7) or and_result(6) or and_result(5) or and_result(4) or
and_result(3) or and_result(2) or and_result(1) or and_result(0)),
half_carry_bit => '1',
parity_overflow_bit => not (and_result(7) xor and_result(6) xor and_result(5) xor
and_result(4) xor and_result(3) xor and_result(2) xor
and_result(1) xor and_result(0)),
others => '0');
output <= and_result;
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity or8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_or8bit of or8bit is
signal or_result: std_logic_vector(7 downto 0);
begin
or_result <= operand1 or operand2;
output <= or_result;
flags_out <= ( sign_bit => or_result(7),
half_carry_bit => '1',
zero_bit => not (or_result(7) or or_result(6) or or_result(5) or or_result(4) or
or_result(3) or or_result(2) or or_result(1) or or_result(0)),
parity_overflow_bit => not (or_result(7) xor or_result(6) xor or_result(5) xor
or_result(4) xor or_result(3) xor or_result(2) xor
or_result(1) xor or_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity sra8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_sra8bit of sra8bit is
signal sra_result: std_logic_vector(7 downto 0);
begin
sra_result <= operand(7) & operand(7 downto 1);
output <= sra_result;
flags_out <= ( carry_bit => operand(0),
zero_bit => not (sra_result(7) or sra_result(6) or sra_result(5) or sra_result(4) or
sra_result(3) or sra_result(2) or sra_result(1) or sra_result(0)),
parity_overflow_bit => not (sra_result(7) xor sra_result(6) xor sra_result(5) xor
sra_result(4) xor sra_result(3) xor sra_result(2) xor
sra_result(1) xor sra_result(0)),
sign_bit => operand(7),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity xor8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_xor8bit of xor8bit is
signal xor_result: std_logic_vector(7 downto 0);
begin
xor_result <= operand1 xor operand2;
output <= xor_result;
flags_out <= ( sign_bit => xor_result(7),
half_carry_bit => '1',
zero_bit => not (xor_result(7) or xor_result(6) or xor_result(5) or xor_result(4) or
xor_result(3) or xor_result(2) or xor_result(1) or xor_result(0)),
parity_overflow_bit => not (xor_result(7) xor xor_result(6) xor xor_result(5) xor
xor_result(4) xor xor_result(3) xor xor_result(2) xor
xor_result(1) xor xor_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity sla8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_sla8bit of sla8bit is
signal sla_result: std_logic_vector(7 downto 0);
begin
sla_result <= operand(6 downto 0) & '0';
output <= sla_result;
flags_out <= ( sign_bit => sla_result(7),
half_carry_bit => '1',
zero_bit => not (sla_result(7) or sla_result(6) or sla_result(5) or sla_result(4) or
sla_result(3) or sla_result(2) or sla_result(1) or sla_result(0)),
parity_overflow_bit => not (sla_result(7) xor sla_result(6) xor sla_result(5) xor
sla_result(4) xor sla_result(3) xor sla_result(2) xor
sla_result(1) xor sla_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity subtractor is
port(
minuend, subtrahend: in std_logic;
borrow_in: in std_logic;
difference: out std_logic;
borrow_out: out std_logic
);
end;
architecture struct_subtractor of subtractor is
begin
-- These expressions were derived from the truth table of a single bit subtractor and simplified with
-- a Karnaugh map.
difference <= (borrow_in and (not minuend) and (not subtrahend)) or
((not borrow_in) and (not minuend) and subtrahend) or
(borrow_in and minuend and subtrahend) or
((not borrow_in) and minuend and (not subtrahend));
borrow_out <= (not minuend and subtrahend) or
(borrow_in and (not minuend)) or
(borrow_in and subtrahend);
end;
library ieee;
use ieee.std_logic_1164.all;
entity subtractorN is
generic(
N: positive
);
port(
minuend: in std_logic_vector((N-1) downto 0);
subtrahend: in std_logic_vector((N-1) downto 0);
borrow_in: in std_logic;
difference: out std_logic_vector((N-1) downto 0);
borrow_out: out std_logic
);
end;
architecture struct_subtractorN of subtractorN is
component subtractor is
port(
minuend, subtrahend: in std_logic;
borrow_in: in std_logic;
difference: out std_logic;
borrow_out: out std_logic
);
end component;
signal borrow: std_logic_vector(N downto 0);
begin
-- These expressions were derived from the truth table of a single bit subtractor and simplified with a
-- Karnaugh map.
-- d = difference, m = minuend, s = subtrahend, b = borrow
--
-- d(i) = (b(i) and (not m(i)) and (not s(i))) or
-- ((not b(i)) and (not m(i)) and s(i)) or
-- (b(i) and m(i) and s(i)) or
-- ((not b(i)) and m(i) and (not s(i)))
--
-- b(i+1) = (not m(i) and s(i)) or
-- (b(i) and (not m(i))) or
-- (b(i) and s(i)
borrow(0) <= borrow_in;
u1: for i in 0 to (N-1) generate
u: subtractor port map(
minuend => minuend(i),
subtrahend => subtrahend(i),
borrow_in => borrow(i),
difference => difference(i),
borrow_out => borrow(i+1)
);
end generate;
borrow_out <= borrow(N);
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity subtractor8x2 is
port(
minuend, subtrahend: in std_logic_vector(7 downto 0);
borrow_in: in std_logic;
difference: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_subtractor8x2 of subtractor8x2 is
component subtractor is
port(
minuend, subtrahend: in std_logic;
borrow_in: in std_logic;
difference: out std_logic;
borrow_out: out std_logic
);
end component;
signal borrow: std_logic_vector(8 downto 0);
signal d: std_logic_vector(7 downto 0);
begin
borrow(0) <= borrow_in;
u1: for i in 0 to 7 generate
u: subtractor port map(
minuend => minuend(i),
subtrahend => subtrahend(i),
borrow_in => borrow(i),
difference => d(i),
borrow_out => borrow(i+1)
);
end generate;
difference <= d;
flags_out <= ( sign_bit => d(7),
zero_bit => not (d(0) or d(1) or d(2) or d(3) or d(4) or d(5) or d(6) or d(7)),
half_carry_bit => borrow(4),
parity_overflow_bit => (minuend(7) xor subtrahend(7)) and (minuend(7) xor d(7)),
add_sub_bit => '1',
carry_bit => borrow(8),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity adder is
port(
addend, augend: in std_logic;
carry_in: in std_logic;
sum: out std_logic;
carry_out: out std_logic
);
end;
architecture struct_adder of adder is
begin
-- These expressions are derived from a single bit full adder truth table and simplified with a
-- Karnaugh map.
sum <= ((not (carry_in)) and (not addend) and augend) or
((not carry_in) and addend and (not augend)) or
(carry_in and (not addend) and (not augend)) or
(carry_in and addend and augend);
carry_out <= (addend and augend) or
(carry_in and addend) or
(carry_in and augend);
end;
library ieee;
use ieee.std_logic_1164.all;
entity adderN is
generic(
N: positive
);
port(
addend: in std_logic_vector((N-1) downto 0);
augend: in std_logic_vector((N-1) downto 0);
carry_in: in std_logic;
sum: out std_logic_vector((N-1) downto 0);
carry_out: out std_logic
);
end;
-- Tested with Modelsim 2015/12/11, works.
architecture struct_adderN of adderN is
component adder is
port(
addend, augend: in std_logic;
carry_in: in std_logic;
sum: out std_logic;
carry_out: out std_logic
);
end component;
signal carry: std_logic_vector(N downto 0);
begin
carry(0) <= carry_in;
u1: for i in 0 to (N-1) generate
u: adder port map(
addend => addend(i),
augend => augend(i),
carry_in => carry(i),
sum => sum(i),
carry_out => carry(i+1)
);
end generate;
carry_out <= carry(N);
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity adder8x2 is
port(
addend, augend: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
sum: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
-- The adderN version is not used because access to carry out of bit 3 is required.
architecture struct_adder8x2 of adder8x2 is
component adder is
port(
addend, augend: in std_logic;
carry_in: in std_logic;
sum: out std_logic;
carry_out: out std_logic
);
end component;
signal result: std_logic_vector(7 downto 0);
signal carry: std_logic_vector(8 downto 0);
begin
carry(0) <= carry_in;
u1: for i in 0 to 7 generate
u: adder port map(
addend => addend(i),
augend => augend(i),
carry_in => carry(i),
sum => result(i),
carry_out => carry(i+1)
);
end generate;
sum <= result;
flags_out <= ( sign_bit => result(7),
zero_bit => not (result(7) or result(6) or result(5) or result(4) or
result(3) or result(2) or result(1) or result(0)),
half_carry_bit => carry(4),
parity_overflow_bit => not (addend(7) xor augend(7)) and
(addend(7) xor result(7)),
add_sub_bit => '0',
carry_bit => carry(8),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity cpl is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_cpl of cpl is
begin
output <= not operand;
flags_out <= ( half_carry_bit => '1',
add_sub_bit => '1',
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rlc8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rlc8bit of rlc8bit is
signal rlc_result: std_logic_vector(7 downto 0);
begin
rlc_result(7 downto 1) <= operand(6 downto 0);
rlc_result(0) <= operand(7);
output <= rlc_result;
flags_out <= ( carry_bit => operand(7),
parity_overflow_bit => not (rlc_result(7) xor rlc_result(6) xor rlc_result(5) xor
rlc_result(4) xor rlc_result(3) xor rlc_result(2) xor
rlc_result(1) xor rlc_result(0)),
zero_bit => not (rlc_result(7) or rlc_result(6) or rlc_result(5) or rlc_result(4) or
rlc_result(3) or rlc_result(2) or rlc_result(1) or rlc_result(0)),
sign_bit => rlc_result(7),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rrc8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rrc8bit of rrc8bit is
signal rrc_result: std_logic_vector(7 downto 0);
begin
rrc_result(6 downto 0) <= operand(7 downto 1);
rrc_result(7) <= operand(0);
output <= rrc_result;
flags_out <= ( carry_bit => operand(0),
zero_bit => not (rrc_result(7) or rrc_result(6) or rrc_result(5) or rrc_result(4) or
rrc_result(3) or rrc_result(2) or rrc_result(1) or rrc_result(0)),
parity_overflow_bit => not (rrc_result(7) xor rrc_result(6) xor rrc_result(5) xor
rrc_result(4) xor rrc_result(3) xor rrc_result(2) xor
rrc_result(1) xor rrc_result(0)),
sign_bit => operand(0),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rl8bit is
port(
operand: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rl8bit of rl8bit is
signal rl_result: std_logic_vector(7 downto 0);
begin
rl_result (7 downto 1) <= operand(6 downto 0);
rl_result(0) <= carry_in;
output <= rl_result;
flags_out <= ( carry_bit => operand(7),
zero_bit => not (rl_result(7) or rl_result(6) or rl_result(5) or rl_result(4) or
rl_result(3) or rl_result(2) or rl_result(1) or rl_result(0)),
parity_overflow_bit => not ((rl_result(7) xor rl_result(6) xor rl_result(5) xor
rl_result(4) xor rl_result(3) xor rl_result(2) xor
rl_result(1) xor rl_result(0))),
sign_bit => operand(6),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rr8bit is
port(
operand: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rr8bit of rr8bit is
signal rr_result: std_logic_vector(7 downto 0);
begin
rr_result(6 downto 0) <= operand(7 downto 1);
rr_result(7) <= carry_in;
output <= rr_result;
flags_out <= ( carry_bit => operand(0),
zero_bit => not (rr_result(7) or rr_result(6) or rr_result(5) or rr_result(4) or
rr_result(3) or rr_result(2) or rr_result(1) or rr_result(0)),
parity_overflow_bit => not (rr_result(7) xor rr_result(6) xor rr_result(5) xor
rr_result(4) xor rr_result(3) xor rr_result(2) xor
rr_result(1) xor rr_result(0)),
sign_bit => carry_in,
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity daa is
port(
operand: in std_logic_vector(7 downto 0);
flags_in: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Untested, this is nothing more than a stub with code to prevent unassigned variable warnings/errors.
architecture struct_daa of daa is
begin
output <= operand;
flags_out <= flags_in;
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity bit_op is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_bit_op of bit_op is
signal zero: std_logic;
begin
zero <= '1' when (operand1 and operand2) = x"00" else '0';
flags_out <= ( zero_bit => zero,
half_carry_bit => '1',
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rld is
port(
primary_op: in std_logic_vector(7 downto 0);
secondary_op: in std_logic_vector(7 downto 0);
result: out std_logic_vector(7 downto 0);
secondary_result: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rld of rld is
signal primary_result: std_logic_vector(7 downto 0);
begin
primary_result(7 downto 4) <= primary_op(7 downto 4);
primary_result(3 downto 0) <= secondary_op(7 downto 4);
result <= primary_result;
secondary_result(7 downto 4) <= secondary_op(3 downto 0);
secondary_result(3 downto 0) <= primary_op(3 downto 0);
flags_out <= ( sign_bit => primary_result(7),
zero_bit => not (primary_result(7) or primary_result(6) or primary_result(5) or
primary_result(4) or primary_result(3) or primary_result(2) or
primary_result(1) or primary_result(0)),
parity_overflow_bit => not (primary_result(7) xor primary_result(6) xor
primary_result(5) xor primary_result(4) xor
primary_result(3) xor primary_result(2) xor
primary_result(1) xor primary_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rrd is
port(
primary_op: in std_logic_vector(7 downto 0);
secondary_op: in std_logic_vector(7 downto 0);
result: out std_logic_vector(7 downto 0);
secondary_result: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rrd of rrd is
signal primary_result: std_logic_vector(7 downto 0);
begin
primary_result(7 downto 4) <= primary_op(7 downto 4);
primary_result(3 downto 0) <= secondary_op(3 downto 0);
result <= primary_result;
secondary_result(7 downto 4) <= primary_op(3 downto 0);
secondary_result(3 downto 0) <= secondary_op(7 downto 4);
flags_out <= ( sign_bit => primary_result(7),
zero_bit => not (primary_result(7) or primary_result(6) or primary_result(5) or
primary_result(4) or primary_result(3) or primary_result(2) or
primary_result(1) or primary_result(0)),
parity_overflow_bit => not (primary_result(7) xor primary_result(6) xor
primary_result(5) xor primary_result(4) xor
primary_result(3) xor primary_result(2) xor
primary_result(1) xor primary_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity in_rc_flags is
port(
operand: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_in_rc_flags of in_rc_flags is
begin
flags_out <= ( zero_bit => not (operand(7) or operand(6) or operand(5) or operand(4) or
operand(3) or operand(2) or operand(1) or operand(0)),
sign_bit => operand(7),
parity_overflow_bit => not (operand(7) xor operand(6) xor operand(5) xor
operand(4) xor operand(3) xor operand(2) xor
operand(1) xor operand(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity bmtc is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_bmtc of bmtc is
signal result: std_logic_vector(7 downto 0);
begin
result <= operand1 or operand2;
output <= result;
flags_out <= ( parity_overflow_bit => not (result(7) or result(6) or result(5) or result(4) or
result(3) or result(2) or result(1) or result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity alu is
port(
-- control
operation: in std_logic_vector(4 downto 0);
-- operands
primary_operand: in std_logic_vector(7 downto 0);
secondary_operand: in std_logic_vector(7 downto 0);
flags_in: in std_logic_vector(7 downto 0);
-- results
output, flags_out: out std_logic_vector(7 downto 0);
secondary_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested 2016/11/22, works on Modelsim simulator along with all components.
architecture struct_alu of alu is
component bmtc is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component srl8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component sll8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component sra8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component sla8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component in_rc_flags is
port(
operand: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component ccf_operation is
port(
flags_in: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component cpl is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component xor8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component or8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component and8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component subtractor8x2 is
port(
minuend, subtrahend: in std_logic_vector(7 downto 0);
borrow_in: in std_logic;
difference: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component adder8x2 is
port(
addend, augend: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
sum: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component magnitudeN is
generic(
N: positive
);
port(
a: in std_logic_vector((N-1) downto 0);
b: in std_logic_vector((N-1) downto 0);
equal: out std_logic;
lt: out std_logic; -- '1' if a < b
gt: out std_logic -- '1' if a > b
);
end component;
component rrd is
port(
primary_op: in std_logic_vector(7 downto 0);
secondary_op: in std_logic_vector(7 downto 0);
result: out std_logic_vector(7 downto 0);
secondary_result: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rld is
port(
primary_op: in std_logic_vector(7 downto 0);
secondary_op: in std_logic_vector(7 downto 0);
result: out std_logic_vector(7 downto 0);
secondary_result: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rlc8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rl8bit is
port(
operand: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rrc8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rr8bit is
port(
operand: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component daa is
port(
operand: in std_logic_vector(7 downto 0);
flags_in: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component bit_op is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component encoder32xN is
generic(
N: positive
);
port(
data0: in std_logic_vector((N-1) downto 0);
data1: in std_logic_vector((N-1) downto 0);
data2: in std_logic_vector((N-1) downto 0);
data3: in std_logic_vector((N-1) downto 0);
data4: in std_logic_vector((N-1) downto 0);
data5: in std_logic_vector((N-1) downto 0);
data6: in std_logic_vector((N-1) downto 0);
data7: in std_logic_vector((N-1) downto 0);
data8: in std_logic_vector((N-1) downto 0);
data9: in std_logic_vector((N-1) downto 0);
data10: in std_logic_vector((N-1) downto 0);
data11: in std_logic_vector((N-1) downto 0);
data12: in std_logic_vector((N-1) downto 0);
data13: in std_logic_vector((N-1) downto 0);
data14: in std_logic_vector((N-1) downto 0);
data15: in std_logic_vector((N-1) downto 0);
data16: in std_logic_vector((N-1) downto 0);
data17: in std_logic_vector((N-1) downto 0);
data18: in std_logic_vector((N-1) downto 0);
data19: in std_logic_vector((N-1) downto 0);
data20: in std_logic_vector((N-1) downto 0);
data21: in std_logic_vector((N-1) downto 0);
data22: in std_logic_vector((N-1) downto 0);
data23: in std_logic_vector((N-1) downto 0);
data24: in std_logic_vector((N-1) downto 0);
data25: in std_logic_vector((N-1) downto 0);
data26: in std_logic_vector((N-1) downto 0);
data27: in std_logic_vector((N-1) downto 0);
data28: in std_logic_vector((N-1) downto 0);
data29: in std_logic_vector((N-1) downto 0);
data30: in std_logic_vector((N-1) downto 0);
data31: in std_logic_vector((N-1) downto 0);
address: in std_logic_vector(4 downto 0);
output: out std_logic_vector((N-1) downto 0)
);
end component;
component encoder2xN_oe is
generic(
N: positive
);
port(
data0: in std_logic_vector((N-1) downto 0);
data1: in std_logic_vector((N-1) downto 0);
selector: in std_logic;
enable: in std_logic;
output: out std_logic_vector((N-1) downto 0)
);
end component;
signal add_result: std_logic_vector(7 downto 0);
signal add_carry_in: std_logic;
signal add_flags: std_logic_vector(7 downto 0);
signal and_result: std_logic_vector(7 downto 0);
signal and_flags: std_logic_vector(7 downto 0);
signal or_result: std_logic_vector(7 downto 0);
signal or_flags: std_logic_vector(7 downto 0);
signal xor_result: std_logic_vector(7 downto 0);
signal xor_flags: std_logic_vector(7 downto 0);
signal cpl_result: std_logic_vector(7 downto 0);
signal cpl_flags: std_logic_vector(7 downto 0);
signal subtract_result: std_logic_vector(7 downto 0);
signal subtract_borrow_in: std_logic;
signal subtract_flags: std_logic_vector(7 downto 0);
signal rlc_result: std_logic_vector(7 downto 0);
signal rlc_flags: std_logic_vector(7 downto 0);
signal rrc_result: std_logic_vector(7 downto 0);
signal rrc_flags: std_logic_vector(7 downto 0);
signal rl_result: std_logic_vector(7 downto 0);
signal rl_flags: std_logic_vector(7 downto 0);
signal rr_result: std_logic_vector(7 downto 0);
signal rr_flags: std_logic_vector(7 downto 0);
signal daa_result: std_logic_vector(7 downto 0);
signal daa_flags: std_logic_vector(7 downto 0);
signal scf_flags: std_logic_vector(7 downto 0);
signal ccf_carry: std_logic;
signal ccf_flags: std_logic_vector(7 downto 0);
signal bit_zero: std_logic;
signal bit_flags: std_logic_vector(7 downto 0);
signal in_flags: std_logic_vector(7 downto 0); -- flags for IN r, C instruction
signal secondary_out_enable: std_logic; -- '1' when executing a rrd/rld
-- instruction
signal rld_result: std_logic_vector(7 downto 0);
signal secondary_rld_result: std_logic_vector(7 downto 0);
signal rld_flags: std_logic_vector(7 downto 0);
signal is_rld: std_logic;
signal rrd_result: std_logic_vector(7 downto 0);
signal secondary_rrd_result: std_logic_vector(7 downto 0);
signal rrd_flags: std_logic_vector(7 downto 0);
signal is_rrd: std_logic;
signal sla_result: std_logic_vector(7 downto 0);
signal sla_flags: std_logic_vector(7 downto 0);
signal sra_result: std_logic_vector(7 downto 0);
signal sra_flags: std_logic_vector(7 downto 0);
signal sll_result: std_logic_vector(7 downto 0);
signal sll_flags: std_logic_vector(7 downto 0);
signal srl_result: std_logic_vector(7 downto 0);
signal srl_flags: std_logic_vector(7 downto 0);
signal bmtc_result: std_logic_vector(7 downto 0);
signal bmtc_flags: std_logic_vector(7 downto 0); -- block move termination criterion
-- flags
begin
-- result multiplexer, 32x8
u1: encoder32xN
generic map(
N => 8
)
port map(
data0 => add_result, -- add, ignore carry bit
data1 => add_result, -- add, add carry bit
data2 => subtract_result, -- sub, ignore borrow bit
data3 => subtract_result, -- sub, subtract borrow bit
data4 => and_result, -- and
data5 => xor_result, -- xor
data6 => or_result, -- or
data7 => subtract_result, -- compare (no-borrow sub with result
-- discarded, used to set flags)
data8 => rlc_result, -- RLC
data9 => rrc_result, -- RRC
data10 => rl_result, -- RL
data11 => rr_result, -- RR
data12 => daa_result, -- DAA
data13 => cpl_result, -- CPL
data14 => primary_operand, -- SCF
data15 => primary_operand, -- CCF
data16 => sla_result, -- SLA
data17 => sra_result, -- SRA
data18 => sll_result, -- SLL
data19 => srl_result, -- SRL
data20 => secondary_operand, -- BIT
data21 => and_result, -- RES
data22 => or_result, -- SET
data23 => primary_operand, -- IN r, (C)
data24 => rld_result, -- RLD
data25 => rrd_result, -- RRD
data26 => bmtc_result, -- block move termination criterion
data27 => (others => '0'), -- reserved
data28 => (others => '0'), -- reserved
data29 => (others => '0'), -- reserved
data30 => (others => '0'), -- reserved
data31 => (others => '0'), -- reserved
address => operation,
output => output
);
-- result flags multiplexer
u2: encoder32xN
generic map(
N => 8
)
port map(
data0 => add_flags, -- add
data1 => add_flags, -- adc
data2 => subtract_flags, -- sub
data3 => subtract_flags, -- sbc
data4 => and_flags, -- and
data5 => xor_flags, -- xor
data6 => or_flags, -- or
data7 => subtract_flags, -- cmp
data8 => rlc_flags, -- rlc
data9 => rrc_flags, -- rrc
data10 => rl_flags, -- rl
data11 => rr_flags, -- rr
data12 => daa_flags, -- daa
data13 => cpl_flags, -- cpl
data14 => scf_flags, -- scf
data15 => ccf_flags, -- ccf
data16 => sla_flags, -- SLA
data17 => sra_flags, -- SRA
data18 => sll_flags, -- SLL
data19 => srl_flags, -- SRL
data20 => bit_flags, -- BIT
data21 => (others => '0'), -- RES, no flags affected
data22 => (others => '0'), -- SET, no flags affected
data23 => in_flags, -- IN r, (C)
data24 => rld_flags, -- RLD
data25 => rrd_flags, -- RRD
data26 => bmtc_flags, -- block move termination criterion
data27 => (others => '0'), -- reserved
data28 => (others => '0'), -- reserved
data29 => (others => '0'), -- reserved
data30 => (others => '0'), -- reserved
data31 => (others => '0'), -- reserved
address => operation,
output => flags_out
);
scf_flags <= (carry_bit => '1', others => '0');
-- adder: This version gets flagged by ModelSim on the carry_in line as an error. Only signals or
-- maybe variables are allowed. Expressions are not.
-- u3: adder8x2 port map(
-- addend => primary_operand,
-- augend => secondary_operand,
-- carry_in => (flags_in(carry_bit) and operation(0)), -- carry only with adc opcode, others
-- -- made irrelevant by result mux
-- sum => add_result,
-- carry_out => carry_out,
-- overflow => add_overflow,
-- interdigit_carry => interdigit_carry,
-- zero => add_zero
-- );
-- adder
u3: adder8x2 port map(
addend => primary_operand,
augend => secondary_operand,
carry_in => add_carry_in,
sum => add_result,
flags_out => add_flags
);
add_carry_in <= flags_in(carry_bit) and operation(0); -- carry only with adc opcode, others made
-- irrelevant by result mux
-- subtractor
u4: subtractor8x2 port map(
minuend => primary_operand,
subtrahend => secondary_operand,
borrow_in => subtract_borrow_in,
difference => subtract_result,
flags_out => subtract_flags
);
-- borrow only with sbc opcode, must remove compare opcode (operation(2 downto 0) = "111"), others
-- made irrelevant by result mux
subtract_borrow_in <= flags_in(carry_bit) and (not operation(2)) and operation(1) and operation(0);
-- bitwise and operation
u5: and8bit port map(
operand1 => primary_operand,
operand2 => secondary_operand,
output => and_result,
flags_out => and_flags
);
-- bitwise exclusive-or operation
u6: xor8bit port map(
operand1 => primary_operand,
operand2 => secondary_operand,
output => xor_result,
flags_out => xor_flags
);
-- bitwise or operation
u7: or8bit port map(
operand1 => primary_operand,
operand2 => secondary_operand,
output => or_result,
flags_out => or_flags
);
-- RLC generator
u8: rlc8bit port map(
operand => primary_operand,
output => rlc_result,
flags_out => rlc_flags
);
-- RRC generator
u9: rrc8bit port map(
operand => primary_operand,
output => rrc_result,
flags_out => rrc_flags
);
-- RL generator
u10: rl8bit port map(
operand => primary_operand,
carry_in => flags_in(carry_bit),
output => rl_result,
flags_out => rl_flags
);
-- RR generator
u11: rr8bit port map(
operand => primary_operand,
carry_in => flags_in(carry_bit),
output => rr_result,
flags_out => rr_flags
);
-- DAA
u12: daa port map(
operand => primary_operand,
flags_in => flags_in,
output => daa_result,
flags_out => daa_flags
);
-- bit testing of secondary operand against mask in primary operand
u13: bit_op port map(
operand1 => primary_operand,
operand2 => secondary_operand,
flags_out => bit_flags
);
u14: rld port map(
primary_op => primary_operand,
secondary_op => secondary_operand,
result => rld_result,
secondary_result => secondary_rld_result,
flags_out => rld_flags
);
u15: magnitudeN
generic map(
N => 5
)
port map(
a => operation,
b => rrd_operation,
equal => is_rrd,
lt => open,
gt => open
);
u16: magnitudeN
generic map(
N => 5
)
port map(
a => operation,
b => rld_operation,
equal => is_rld,
lt => open,
gt => open
);
u17: rrd port map(
primary_op => primary_operand,
secondary_op => secondary_operand,
result => rrd_result,
secondary_result => secondary_rrd_result,
flags_out => rrd_flags
);
u18: encoder2xN_oe
generic map(
N => 8
)
port map(
data0 => secondary_rld_result,
data1 => secondary_rrd_result,
selector => is_rrd,
enable => secondary_out_enable,
output => secondary_out
);
secondary_out_enable <= is_rrd or is_rld;
u19: cpl port map(
operand => primary_operand,
output => cpl_result,
flags_out => cpl_flags
);
u20: ccf_operation port map(
flags_in => flags_in,
flags_out => ccf_flags
);
u21: in_rc_flags port map(
operand => primary_operand,
flags_out => in_flags
);
u22: sla8bit port map(
operand => primary_operand,
output => sla_result,
flags_out => sla_flags
);
u23: sra8bit port map(
operand => primary_operand,
output => sra_result,
flags_out => sra_flags
);
u24: sll8bit port map(
operand => primary_operand,
output => sll_result,
flags_out => sll_flags
);
u25: srl8bit port map(
operand => primary_operand,
output => srl_result,
flags_out => srl_flags
);
u26: bmtc port map(
operand1 => primary_operand,
operand2 => secondary_operand,
output => bmtc_result,
flags_out => bmtc_flags
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity ccf_operation is
port(
flags_in: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_ccf_operation of ccf_operation is
begin
-- A point of disagreement has been found between the Z80 user manual
-- and Lance Levinthal's book entitled "Z80 Assembly Language Programming".
-- The Z80 user manual says the half-carry bit gets the previous carry;
-- Levinthal says the half-carry bit is unchanged. For now, go with
-- Levinthal's version as the Z80 users manual is inconsistent with
-- itself on other instructions. At this time, no such inconsistencies
-- have been found with Levinthal's work.
flags_out <= ( carry_bit => not flags_in(carry_bit),
half_carry_bit => flags_in(carry_bit),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity sll8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_sll8bit of sll8bit is
signal sll_result: std_logic_vector(7 downto 0);
begin
-- This operation is not documented by Zilog, but seems to work in their
-- finished chip. This code may not work the same way as the Z80 hardware
-- works. The functionality is assumed from the SRL instruction.
sll_result <= operand(6 downto 0) & '0';
output <= sll_result;
flags_out <= ( carry_bit => operand(7),
zero_bit => not (sll_result(7) or sll_result(6) or sll_result(5) or sll_result(4) or
sll_result(3) or sll_result(2) or sll_result(1) or sll_result(0)),
parity_overflow_bit => not (sll_result(7) xor sll_result(6) xor sll_result(5) xor
sll_result(4) xor sll_result(3) xor sll_result(2) xor
sll_result(1) xor sll_result(0)),
sign_bit => operand(6),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity srl8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_srl8bit of srl8bit is
signal srl_result: std_logic_vector(7 downto 0);
begin
srl_result <= '0' & operand(7 downto 1);
output <= srl_result;
flags_out <= ( carry_bit => operand(0),
zero_bit => not (srl_result(7) or srl_result(6) or srl_result(5) or srl_result(4) or
srl_result(3) or srl_result(2) or srl_result(1) or srl_result(0)),
parity_overflow_bit => not (srl_result(7) xor srl_result(6) xor srl_result(5) xor
srl_result(4) xor srl_result(3) xor srl_result(2) xor
srl_result(1) xor srl_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity and8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_and8bit of and8bit is
signal and_result: std_logic_vector(7 downto 0);
begin
and_result <= operand1 and operand2;
flags_out <= ( sign_bit => and_result(7),
zero_bit => not (and_result(7) or and_result(6) or and_result(5) or and_result(4) or
and_result(3) or and_result(2) or and_result(1) or and_result(0)),
half_carry_bit => '1',
parity_overflow_bit => not (and_result(7) xor and_result(6) xor and_result(5) xor
and_result(4) xor and_result(3) xor and_result(2) xor
and_result(1) xor and_result(0)),
others => '0');
output <= and_result;
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity or8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_or8bit of or8bit is
signal or_result: std_logic_vector(7 downto 0);
begin
or_result <= operand1 or operand2;
output <= or_result;
flags_out <= ( sign_bit => or_result(7),
half_carry_bit => '1',
zero_bit => not (or_result(7) or or_result(6) or or_result(5) or or_result(4) or
or_result(3) or or_result(2) or or_result(1) or or_result(0)),
parity_overflow_bit => not (or_result(7) xor or_result(6) xor or_result(5) xor
or_result(4) xor or_result(3) xor or_result(2) xor
or_result(1) xor or_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity sra8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_sra8bit of sra8bit is
signal sra_result: std_logic_vector(7 downto 0);
begin
sra_result <= operand(7) & operand(7 downto 1);
output <= sra_result;
flags_out <= ( carry_bit => operand(0),
zero_bit => not (sra_result(7) or sra_result(6) or sra_result(5) or sra_result(4) or
sra_result(3) or sra_result(2) or sra_result(1) or sra_result(0)),
parity_overflow_bit => not (sra_result(7) xor sra_result(6) xor sra_result(5) xor
sra_result(4) xor sra_result(3) xor sra_result(2) xor
sra_result(1) xor sra_result(0)),
sign_bit => operand(7),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity xor8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_xor8bit of xor8bit is
signal xor_result: std_logic_vector(7 downto 0);
begin
xor_result <= operand1 xor operand2;
output <= xor_result;
flags_out <= ( sign_bit => xor_result(7),
half_carry_bit => '1',
zero_bit => not (xor_result(7) or xor_result(6) or xor_result(5) or xor_result(4) or
xor_result(3) or xor_result(2) or xor_result(1) or xor_result(0)),
parity_overflow_bit => not (xor_result(7) xor xor_result(6) xor xor_result(5) xor
xor_result(4) xor xor_result(3) xor xor_result(2) xor
xor_result(1) xor xor_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity sla8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_sla8bit of sla8bit is
signal sla_result: std_logic_vector(7 downto 0);
begin
sla_result <= operand(6 downto 0) & '0';
output <= sla_result;
flags_out <= ( sign_bit => sla_result(7),
half_carry_bit => '1',
zero_bit => not (sla_result(7) or sla_result(6) or sla_result(5) or sla_result(4) or
sla_result(3) or sla_result(2) or sla_result(1) or sla_result(0)),
parity_overflow_bit => not (sla_result(7) xor sla_result(6) xor sla_result(5) xor
sla_result(4) xor sla_result(3) xor sla_result(2) xor
sla_result(1) xor sla_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity subtractor is
port(
minuend, subtrahend: in std_logic;
borrow_in: in std_logic;
difference: out std_logic;
borrow_out: out std_logic
);
end;
architecture struct_subtractor of subtractor is
begin
-- These expressions were derived from the truth table of a single bit subtractor and simplified with
-- a Karnaugh map.
difference <= (borrow_in and (not minuend) and (not subtrahend)) or
((not borrow_in) and (not minuend) and subtrahend) or
(borrow_in and minuend and subtrahend) or
((not borrow_in) and minuend and (not subtrahend));
borrow_out <= (not minuend and subtrahend) or
(borrow_in and (not minuend)) or
(borrow_in and subtrahend);
end;
library ieee;
use ieee.std_logic_1164.all;
entity subtractorN is
generic(
N: positive
);
port(
minuend: in std_logic_vector((N-1) downto 0);
subtrahend: in std_logic_vector((N-1) downto 0);
borrow_in: in std_logic;
difference: out std_logic_vector((N-1) downto 0);
borrow_out: out std_logic
);
end;
architecture struct_subtractorN of subtractorN is
component subtractor is
port(
minuend, subtrahend: in std_logic;
borrow_in: in std_logic;
difference: out std_logic;
borrow_out: out std_logic
);
end component;
signal borrow: std_logic_vector(N downto 0);
begin
-- These expressions were derived from the truth table of a single bit subtractor and simplified with a
-- Karnaugh map.
-- d = difference, m = minuend, s = subtrahend, b = borrow
--
-- d(i) = (b(i) and (not m(i)) and (not s(i))) or
-- ((not b(i)) and (not m(i)) and s(i)) or
-- (b(i) and m(i) and s(i)) or
-- ((not b(i)) and m(i) and (not s(i)))
--
-- b(i+1) = (not m(i) and s(i)) or
-- (b(i) and (not m(i))) or
-- (b(i) and s(i)
borrow(0) <= borrow_in;
u1: for i in 0 to (N-1) generate
u: subtractor port map(
minuend => minuend(i),
subtrahend => subtrahend(i),
borrow_in => borrow(i),
difference => difference(i),
borrow_out => borrow(i+1)
);
end generate;
borrow_out <= borrow(N);
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity subtractor8x2 is
port(
minuend, subtrahend: in std_logic_vector(7 downto 0);
borrow_in: in std_logic;
difference: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_subtractor8x2 of subtractor8x2 is
component subtractor is
port(
minuend, subtrahend: in std_logic;
borrow_in: in std_logic;
difference: out std_logic;
borrow_out: out std_logic
);
end component;
signal borrow: std_logic_vector(8 downto 0);
signal d: std_logic_vector(7 downto 0);
begin
borrow(0) <= borrow_in;
u1: for i in 0 to 7 generate
u: subtractor port map(
minuend => minuend(i),
subtrahend => subtrahend(i),
borrow_in => borrow(i),
difference => d(i),
borrow_out => borrow(i+1)
);
end generate;
difference <= d;
flags_out <= ( sign_bit => d(7),
zero_bit => not (d(0) or d(1) or d(2) or d(3) or d(4) or d(5) or d(6) or d(7)),
half_carry_bit => borrow(4),
parity_overflow_bit => (minuend(7) xor subtrahend(7)) and (minuend(7) xor d(7)),
add_sub_bit => '1',
carry_bit => borrow(8),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity adder is
port(
addend, augend: in std_logic;
carry_in: in std_logic;
sum: out std_logic;
carry_out: out std_logic
);
end;
architecture struct_adder of adder is
begin
-- These expressions are derived from a single bit full adder truth table and simplified with a
-- Karnaugh map.
sum <= ((not (carry_in)) and (not addend) and augend) or
((not carry_in) and addend and (not augend)) or
(carry_in and (not addend) and (not augend)) or
(carry_in and addend and augend);
carry_out <= (addend and augend) or
(carry_in and addend) or
(carry_in and augend);
end;
library ieee;
use ieee.std_logic_1164.all;
entity adderN is
generic(
N: positive
);
port(
addend: in std_logic_vector((N-1) downto 0);
augend: in std_logic_vector((N-1) downto 0);
carry_in: in std_logic;
sum: out std_logic_vector((N-1) downto 0);
carry_out: out std_logic
);
end;
-- Tested with Modelsim 2015/12/11, works.
architecture struct_adderN of adderN is
component adder is
port(
addend, augend: in std_logic;
carry_in: in std_logic;
sum: out std_logic;
carry_out: out std_logic
);
end component;
signal carry: std_logic_vector(N downto 0);
begin
carry(0) <= carry_in;
u1: for i in 0 to (N-1) generate
u: adder port map(
addend => addend(i),
augend => augend(i),
carry_in => carry(i),
sum => sum(i),
carry_out => carry(i+1)
);
end generate;
carry_out <= carry(N);
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity adder8x2 is
port(
addend, augend: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
sum: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
-- The adderN version is not used because access to carry out of bit 3 is required.
architecture struct_adder8x2 of adder8x2 is
component adder is
port(
addend, augend: in std_logic;
carry_in: in std_logic;
sum: out std_logic;
carry_out: out std_logic
);
end component;
signal result: std_logic_vector(7 downto 0);
signal carry: std_logic_vector(8 downto 0);
begin
carry(0) <= carry_in;
u1: for i in 0 to 7 generate
u: adder port map(
addend => addend(i),
augend => augend(i),
carry_in => carry(i),
sum => result(i),
carry_out => carry(i+1)
);
end generate;
sum <= result;
flags_out <= ( sign_bit => result(7),
zero_bit => not (result(7) or result(6) or result(5) or result(4) or
result(3) or result(2) or result(1) or result(0)),
half_carry_bit => carry(4),
parity_overflow_bit => not (addend(7) xor augend(7)) and
(addend(7) xor result(7)),
add_sub_bit => '0',
carry_bit => carry(8),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity cpl is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_cpl of cpl is
begin
output <= not operand;
flags_out <= ( half_carry_bit => '1',
add_sub_bit => '1',
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rlc8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rlc8bit of rlc8bit is
signal rlc_result: std_logic_vector(7 downto 0);
begin
rlc_result(7 downto 1) <= operand(6 downto 0);
rlc_result(0) <= operand(7);
output <= rlc_result;
flags_out <= ( carry_bit => operand(7),
parity_overflow_bit => not (rlc_result(7) xor rlc_result(6) xor rlc_result(5) xor
rlc_result(4) xor rlc_result(3) xor rlc_result(2) xor
rlc_result(1) xor rlc_result(0)),
zero_bit => not (rlc_result(7) or rlc_result(6) or rlc_result(5) or rlc_result(4) or
rlc_result(3) or rlc_result(2) or rlc_result(1) or rlc_result(0)),
sign_bit => rlc_result(7),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rrc8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rrc8bit of rrc8bit is
signal rrc_result: std_logic_vector(7 downto 0);
begin
rrc_result(6 downto 0) <= operand(7 downto 1);
rrc_result(7) <= operand(0);
output <= rrc_result;
flags_out <= ( carry_bit => operand(0),
zero_bit => not (rrc_result(7) or rrc_result(6) or rrc_result(5) or rrc_result(4) or
rrc_result(3) or rrc_result(2) or rrc_result(1) or rrc_result(0)),
parity_overflow_bit => not (rrc_result(7) xor rrc_result(6) xor rrc_result(5) xor
rrc_result(4) xor rrc_result(3) xor rrc_result(2) xor
rrc_result(1) xor rrc_result(0)),
sign_bit => operand(0),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rl8bit is
port(
operand: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rl8bit of rl8bit is
signal rl_result: std_logic_vector(7 downto 0);
begin
rl_result (7 downto 1) <= operand(6 downto 0);
rl_result(0) <= carry_in;
output <= rl_result;
flags_out <= ( carry_bit => operand(7),
zero_bit => not (rl_result(7) or rl_result(6) or rl_result(5) or rl_result(4) or
rl_result(3) or rl_result(2) or rl_result(1) or rl_result(0)),
parity_overflow_bit => not ((rl_result(7) xor rl_result(6) xor rl_result(5) xor
rl_result(4) xor rl_result(3) xor rl_result(2) xor
rl_result(1) xor rl_result(0))),
sign_bit => operand(6),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rr8bit is
port(
operand: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rr8bit of rr8bit is
signal rr_result: std_logic_vector(7 downto 0);
begin
rr_result(6 downto 0) <= operand(7 downto 1);
rr_result(7) <= carry_in;
output <= rr_result;
flags_out <= ( carry_bit => operand(0),
zero_bit => not (rr_result(7) or rr_result(6) or rr_result(5) or rr_result(4) or
rr_result(3) or rr_result(2) or rr_result(1) or rr_result(0)),
parity_overflow_bit => not (rr_result(7) xor rr_result(6) xor rr_result(5) xor
rr_result(4) xor rr_result(3) xor rr_result(2) xor
rr_result(1) xor rr_result(0)),
sign_bit => carry_in,
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity daa is
port(
operand: in std_logic_vector(7 downto 0);
flags_in: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Untested, this is nothing more than a stub with code to prevent unassigned variable warnings/errors.
architecture struct_daa of daa is
begin
output <= operand;
flags_out <= flags_in;
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity bit_op is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_bit_op of bit_op is
signal zero: std_logic;
begin
zero <= '1' when (operand1 and operand2) = x"00" else '0';
flags_out <= ( zero_bit => zero,
half_carry_bit => '1',
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rld is
port(
primary_op: in std_logic_vector(7 downto 0);
secondary_op: in std_logic_vector(7 downto 0);
result: out std_logic_vector(7 downto 0);
secondary_result: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rld of rld is
signal primary_result: std_logic_vector(7 downto 0);
begin
primary_result(7 downto 4) <= primary_op(7 downto 4);
primary_result(3 downto 0) <= secondary_op(7 downto 4);
result <= primary_result;
secondary_result(7 downto 4) <= secondary_op(3 downto 0);
secondary_result(3 downto 0) <= primary_op(3 downto 0);
flags_out <= ( sign_bit => primary_result(7),
zero_bit => not (primary_result(7) or primary_result(6) or primary_result(5) or
primary_result(4) or primary_result(3) or primary_result(2) or
primary_result(1) or primary_result(0)),
parity_overflow_bit => not (primary_result(7) xor primary_result(6) xor
primary_result(5) xor primary_result(4) xor
primary_result(3) xor primary_result(2) xor
primary_result(1) xor primary_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rrd is
port(
primary_op: in std_logic_vector(7 downto 0);
secondary_op: in std_logic_vector(7 downto 0);
result: out std_logic_vector(7 downto 0);
secondary_result: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rrd of rrd is
signal primary_result: std_logic_vector(7 downto 0);
begin
primary_result(7 downto 4) <= primary_op(7 downto 4);
primary_result(3 downto 0) <= secondary_op(3 downto 0);
result <= primary_result;
secondary_result(7 downto 4) <= primary_op(3 downto 0);
secondary_result(3 downto 0) <= secondary_op(7 downto 4);
flags_out <= ( sign_bit => primary_result(7),
zero_bit => not (primary_result(7) or primary_result(6) or primary_result(5) or
primary_result(4) or primary_result(3) or primary_result(2) or
primary_result(1) or primary_result(0)),
parity_overflow_bit => not (primary_result(7) xor primary_result(6) xor
primary_result(5) xor primary_result(4) xor
primary_result(3) xor primary_result(2) xor
primary_result(1) xor primary_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity in_rc_flags is
port(
operand: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_in_rc_flags of in_rc_flags is
begin
flags_out <= ( zero_bit => not (operand(7) or operand(6) or operand(5) or operand(4) or
operand(3) or operand(2) or operand(1) or operand(0)),
sign_bit => operand(7),
parity_overflow_bit => not (operand(7) xor operand(6) xor operand(5) xor
operand(4) xor operand(3) xor operand(2) xor
operand(1) xor operand(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity bmtc is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_bmtc of bmtc is
signal result: std_logic_vector(7 downto 0);
begin
result <= operand1 or operand2;
output <= result;
flags_out <= ( parity_overflow_bit => not (result(7) or result(6) or result(5) or result(4) or
result(3) or result(2) or result(1) or result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity alu is
port(
-- control
operation: in std_logic_vector(4 downto 0);
-- operands
primary_operand: in std_logic_vector(7 downto 0);
secondary_operand: in std_logic_vector(7 downto 0);
flags_in: in std_logic_vector(7 downto 0);
-- results
output, flags_out: out std_logic_vector(7 downto 0);
secondary_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested 2016/11/22, works on Modelsim simulator along with all components.
architecture struct_alu of alu is
component bmtc is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component srl8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component sll8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component sra8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component sla8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component in_rc_flags is
port(
operand: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component ccf_operation is
port(
flags_in: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component cpl is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component xor8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component or8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component and8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component subtractor8x2 is
port(
minuend, subtrahend: in std_logic_vector(7 downto 0);
borrow_in: in std_logic;
difference: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component adder8x2 is
port(
addend, augend: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
sum: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component magnitudeN is
generic(
N: positive
);
port(
a: in std_logic_vector((N-1) downto 0);
b: in std_logic_vector((N-1) downto 0);
equal: out std_logic;
lt: out std_logic; -- '1' if a < b
gt: out std_logic -- '1' if a > b
);
end component;
component rrd is
port(
primary_op: in std_logic_vector(7 downto 0);
secondary_op: in std_logic_vector(7 downto 0);
result: out std_logic_vector(7 downto 0);
secondary_result: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rld is
port(
primary_op: in std_logic_vector(7 downto 0);
secondary_op: in std_logic_vector(7 downto 0);
result: out std_logic_vector(7 downto 0);
secondary_result: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rlc8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rl8bit is
port(
operand: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rrc8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rr8bit is
port(
operand: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component daa is
port(
operand: in std_logic_vector(7 downto 0);
flags_in: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component bit_op is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component encoder32xN is
generic(
N: positive
);
port(
data0: in std_logic_vector((N-1) downto 0);
data1: in std_logic_vector((N-1) downto 0);
data2: in std_logic_vector((N-1) downto 0);
data3: in std_logic_vector((N-1) downto 0);
data4: in std_logic_vector((N-1) downto 0);
data5: in std_logic_vector((N-1) downto 0);
data6: in std_logic_vector((N-1) downto 0);
data7: in std_logic_vector((N-1) downto 0);
data8: in std_logic_vector((N-1) downto 0);
data9: in std_logic_vector((N-1) downto 0);
data10: in std_logic_vector((N-1) downto 0);
data11: in std_logic_vector((N-1) downto 0);
data12: in std_logic_vector((N-1) downto 0);
data13: in std_logic_vector((N-1) downto 0);
data14: in std_logic_vector((N-1) downto 0);
data15: in std_logic_vector((N-1) downto 0);
data16: in std_logic_vector((N-1) downto 0);
data17: in std_logic_vector((N-1) downto 0);
data18: in std_logic_vector((N-1) downto 0);
data19: in std_logic_vector((N-1) downto 0);
data20: in std_logic_vector((N-1) downto 0);
data21: in std_logic_vector((N-1) downto 0);
data22: in std_logic_vector((N-1) downto 0);
data23: in std_logic_vector((N-1) downto 0);
data24: in std_logic_vector((N-1) downto 0);
data25: in std_logic_vector((N-1) downto 0);
data26: in std_logic_vector((N-1) downto 0);
data27: in std_logic_vector((N-1) downto 0);
data28: in std_logic_vector((N-1) downto 0);
data29: in std_logic_vector((N-1) downto 0);
data30: in std_logic_vector((N-1) downto 0);
data31: in std_logic_vector((N-1) downto 0);
address: in std_logic_vector(4 downto 0);
output: out std_logic_vector((N-1) downto 0)
);
end component;
component encoder2xN_oe is
generic(
N: positive
);
port(
data0: in std_logic_vector((N-1) downto 0);
data1: in std_logic_vector((N-1) downto 0);
selector: in std_logic;
enable: in std_logic;
output: out std_logic_vector((N-1) downto 0)
);
end component;
signal add_result: std_logic_vector(7 downto 0);
signal add_carry_in: std_logic;
signal add_flags: std_logic_vector(7 downto 0);
signal and_result: std_logic_vector(7 downto 0);
signal and_flags: std_logic_vector(7 downto 0);
signal or_result: std_logic_vector(7 downto 0);
signal or_flags: std_logic_vector(7 downto 0);
signal xor_result: std_logic_vector(7 downto 0);
signal xor_flags: std_logic_vector(7 downto 0);
signal cpl_result: std_logic_vector(7 downto 0);
signal cpl_flags: std_logic_vector(7 downto 0);
signal subtract_result: std_logic_vector(7 downto 0);
signal subtract_borrow_in: std_logic;
signal subtract_flags: std_logic_vector(7 downto 0);
signal rlc_result: std_logic_vector(7 downto 0);
signal rlc_flags: std_logic_vector(7 downto 0);
signal rrc_result: std_logic_vector(7 downto 0);
signal rrc_flags: std_logic_vector(7 downto 0);
signal rl_result: std_logic_vector(7 downto 0);
signal rl_flags: std_logic_vector(7 downto 0);
signal rr_result: std_logic_vector(7 downto 0);
signal rr_flags: std_logic_vector(7 downto 0);
signal daa_result: std_logic_vector(7 downto 0);
signal daa_flags: std_logic_vector(7 downto 0);
signal scf_flags: std_logic_vector(7 downto 0);
signal ccf_carry: std_logic;
signal ccf_flags: std_logic_vector(7 downto 0);
signal bit_zero: std_logic;
signal bit_flags: std_logic_vector(7 downto 0);
signal in_flags: std_logic_vector(7 downto 0); -- flags for IN r, C instruction
signal secondary_out_enable: std_logic; -- '1' when executing a rrd/rld
-- instruction
signal rld_result: std_logic_vector(7 downto 0);
signal secondary_rld_result: std_logic_vector(7 downto 0);
signal rld_flags: std_logic_vector(7 downto 0);
signal is_rld: std_logic;
signal rrd_result: std_logic_vector(7 downto 0);
signal secondary_rrd_result: std_logic_vector(7 downto 0);
signal rrd_flags: std_logic_vector(7 downto 0);
signal is_rrd: std_logic;
signal sla_result: std_logic_vector(7 downto 0);
signal sla_flags: std_logic_vector(7 downto 0);
signal sra_result: std_logic_vector(7 downto 0);
signal sra_flags: std_logic_vector(7 downto 0);
signal sll_result: std_logic_vector(7 downto 0);
signal sll_flags: std_logic_vector(7 downto 0);
signal srl_result: std_logic_vector(7 downto 0);
signal srl_flags: std_logic_vector(7 downto 0);
signal bmtc_result: std_logic_vector(7 downto 0);
signal bmtc_flags: std_logic_vector(7 downto 0); -- block move termination criterion
-- flags
begin
-- result multiplexer, 32x8
u1: encoder32xN
generic map(
N => 8
)
port map(
data0 => add_result, -- add, ignore carry bit
data1 => add_result, -- add, add carry bit
data2 => subtract_result, -- sub, ignore borrow bit
data3 => subtract_result, -- sub, subtract borrow bit
data4 => and_result, -- and
data5 => xor_result, -- xor
data6 => or_result, -- or
data7 => subtract_result, -- compare (no-borrow sub with result
-- discarded, used to set flags)
data8 => rlc_result, -- RLC
data9 => rrc_result, -- RRC
data10 => rl_result, -- RL
data11 => rr_result, -- RR
data12 => daa_result, -- DAA
data13 => cpl_result, -- CPL
data14 => primary_operand, -- SCF
data15 => primary_operand, -- CCF
data16 => sla_result, -- SLA
data17 => sra_result, -- SRA
data18 => sll_result, -- SLL
data19 => srl_result, -- SRL
data20 => secondary_operand, -- BIT
data21 => and_result, -- RES
data22 => or_result, -- SET
data23 => primary_operand, -- IN r, (C)
data24 => rld_result, -- RLD
data25 => rrd_result, -- RRD
data26 => bmtc_result, -- block move termination criterion
data27 => (others => '0'), -- reserved
data28 => (others => '0'), -- reserved
data29 => (others => '0'), -- reserved
data30 => (others => '0'), -- reserved
data31 => (others => '0'), -- reserved
address => operation,
output => output
);
-- result flags multiplexer
u2: encoder32xN
generic map(
N => 8
)
port map(
data0 => add_flags, -- add
data1 => add_flags, -- adc
data2 => subtract_flags, -- sub
data3 => subtract_flags, -- sbc
data4 => and_flags, -- and
data5 => xor_flags, -- xor
data6 => or_flags, -- or
data7 => subtract_flags, -- cmp
data8 => rlc_flags, -- rlc
data9 => rrc_flags, -- rrc
data10 => rl_flags, -- rl
data11 => rr_flags, -- rr
data12 => daa_flags, -- daa
data13 => cpl_flags, -- cpl
data14 => scf_flags, -- scf
data15 => ccf_flags, -- ccf
data16 => sla_flags, -- SLA
data17 => sra_flags, -- SRA
data18 => sll_flags, -- SLL
data19 => srl_flags, -- SRL
data20 => bit_flags, -- BIT
data21 => (others => '0'), -- RES, no flags affected
data22 => (others => '0'), -- SET, no flags affected
data23 => in_flags, -- IN r, (C)
data24 => rld_flags, -- RLD
data25 => rrd_flags, -- RRD
data26 => bmtc_flags, -- block move termination criterion
data27 => (others => '0'), -- reserved
data28 => (others => '0'), -- reserved
data29 => (others => '0'), -- reserved
data30 => (others => '0'), -- reserved
data31 => (others => '0'), -- reserved
address => operation,
output => flags_out
);
scf_flags <= (carry_bit => '1', others => '0');
-- adder: This version gets flagged by ModelSim on the carry_in line as an error. Only signals or
-- maybe variables are allowed. Expressions are not.
-- u3: adder8x2 port map(
-- addend => primary_operand,
-- augend => secondary_operand,
-- carry_in => (flags_in(carry_bit) and operation(0)), -- carry only with adc opcode, others
-- -- made irrelevant by result mux
-- sum => add_result,
-- carry_out => carry_out,
-- overflow => add_overflow,
-- interdigit_carry => interdigit_carry,
-- zero => add_zero
-- );
-- adder
u3: adder8x2 port map(
addend => primary_operand,
augend => secondary_operand,
carry_in => add_carry_in,
sum => add_result,
flags_out => add_flags
);
add_carry_in <= flags_in(carry_bit) and operation(0); -- carry only with adc opcode, others made
-- irrelevant by result mux
-- subtractor
u4: subtractor8x2 port map(
minuend => primary_operand,
subtrahend => secondary_operand,
borrow_in => subtract_borrow_in,
difference => subtract_result,
flags_out => subtract_flags
);
-- borrow only with sbc opcode, must remove compare opcode (operation(2 downto 0) = "111"), others
-- made irrelevant by result mux
subtract_borrow_in <= flags_in(carry_bit) and (not operation(2)) and operation(1) and operation(0);
-- bitwise and operation
u5: and8bit port map(
operand1 => primary_operand,
operand2 => secondary_operand,
output => and_result,
flags_out => and_flags
);
-- bitwise exclusive-or operation
u6: xor8bit port map(
operand1 => primary_operand,
operand2 => secondary_operand,
output => xor_result,
flags_out => xor_flags
);
-- bitwise or operation
u7: or8bit port map(
operand1 => primary_operand,
operand2 => secondary_operand,
output => or_result,
flags_out => or_flags
);
-- RLC generator
u8: rlc8bit port map(
operand => primary_operand,
output => rlc_result,
flags_out => rlc_flags
);
-- RRC generator
u9: rrc8bit port map(
operand => primary_operand,
output => rrc_result,
flags_out => rrc_flags
);
-- RL generator
u10: rl8bit port map(
operand => primary_operand,
carry_in => flags_in(carry_bit),
output => rl_result,
flags_out => rl_flags
);
-- RR generator
u11: rr8bit port map(
operand => primary_operand,
carry_in => flags_in(carry_bit),
output => rr_result,
flags_out => rr_flags
);
-- DAA
u12: daa port map(
operand => primary_operand,
flags_in => flags_in,
output => daa_result,
flags_out => daa_flags
);
-- bit testing of secondary operand against mask in primary operand
u13: bit_op port map(
operand1 => primary_operand,
operand2 => secondary_operand,
flags_out => bit_flags
);
u14: rld port map(
primary_op => primary_operand,
secondary_op => secondary_operand,
result => rld_result,
secondary_result => secondary_rld_result,
flags_out => rld_flags
);
u15: magnitudeN
generic map(
N => 5
)
port map(
a => operation,
b => rrd_operation,
equal => is_rrd,
lt => open,
gt => open
);
u16: magnitudeN
generic map(
N => 5
)
port map(
a => operation,
b => rld_operation,
equal => is_rld,
lt => open,
gt => open
);
u17: rrd port map(
primary_op => primary_operand,
secondary_op => secondary_operand,
result => rrd_result,
secondary_result => secondary_rrd_result,
flags_out => rrd_flags
);
u18: encoder2xN_oe
generic map(
N => 8
)
port map(
data0 => secondary_rld_result,
data1 => secondary_rrd_result,
selector => is_rrd,
enable => secondary_out_enable,
output => secondary_out
);
secondary_out_enable <= is_rrd or is_rld;
u19: cpl port map(
operand => primary_operand,
output => cpl_result,
flags_out => cpl_flags
);
u20: ccf_operation port map(
flags_in => flags_in,
flags_out => ccf_flags
);
u21: in_rc_flags port map(
operand => primary_operand,
flags_out => in_flags
);
u22: sla8bit port map(
operand => primary_operand,
output => sla_result,
flags_out => sla_flags
);
u23: sra8bit port map(
operand => primary_operand,
output => sra_result,
flags_out => sra_flags
);
u24: sll8bit port map(
operand => primary_operand,
output => sll_result,
flags_out => sll_flags
);
u25: srl8bit port map(
operand => primary_operand,
output => srl_result,
flags_out => srl_flags
);
u26: bmtc port map(
operand1 => primary_operand,
operand2 => secondary_operand,
output => bmtc_result,
flags_out => bmtc_flags
);
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc439.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00439ent IS
END c03s02b01x01p19n01i00439ent;
ARCHITECTURE c03s02b01x01p19n01i00439arch OF c03s02b01x01p19n01i00439ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
function complex_scalar(s : record_cons_array) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return record_cons_array is
begin
return C51;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : record_cons_array;
signal S2 : record_cons_array;
signal S3 : record_cons_array := C51;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C51) and (S2 = C51))
report "***PASSED TEST: c03s02b01x01p19n01i00439"
severity NOTE;
assert ((S1 = C51) and (S2 = C51))
report "***FAILED TEST: c03s02b01x01p19n01i00439 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00439arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc439.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00439ent IS
END c03s02b01x01p19n01i00439ent;
ARCHITECTURE c03s02b01x01p19n01i00439arch OF c03s02b01x01p19n01i00439ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
function complex_scalar(s : record_cons_array) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return record_cons_array is
begin
return C51;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : record_cons_array;
signal S2 : record_cons_array;
signal S3 : record_cons_array := C51;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C51) and (S2 = C51))
report "***PASSED TEST: c03s02b01x01p19n01i00439"
severity NOTE;
assert ((S1 = C51) and (S2 = C51))
report "***FAILED TEST: c03s02b01x01p19n01i00439 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00439arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc439.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00439ent IS
END c03s02b01x01p19n01i00439ent;
ARCHITECTURE c03s02b01x01p19n01i00439arch OF c03s02b01x01p19n01i00439ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
function complex_scalar(s : record_cons_array) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return record_cons_array is
begin
return C51;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : record_cons_array;
signal S2 : record_cons_array;
signal S3 : record_cons_array := C51;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C51) and (S2 = C51))
report "***PASSED TEST: c03s02b01x01p19n01i00439"
severity NOTE;
assert ((S1 = C51) and (S2 = C51))
report "***FAILED TEST: c03s02b01x01p19n01i00439 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00439arch;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
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-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
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--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
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-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
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-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
library altera;
use altera.all;
entity adqout is
port(
clk : in std_logic; -- clk0
clk_oct : in std_logic; -- clk90
dq_h : in std_logic;
dq_l : in std_logic;
dq_oe : in std_logic;
dq_oct : in std_logic; -- gnd = disable
dq_pad : out std_logic -- DQ pad
);
end;
architecture rtl of adqout is
component cycloneiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic;
dfflo : out std_logic;
dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component cycloneiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
port(
i : in std_logic := '0';
oe : in std_logic := '1';
--devoe : in std_logic := '1';
o : out std_logic;
obar : out std_logic--;
--seriesterminationcontrol : in std_logic_vector(15 downto 0) := (others => '0')
);
end component;
component cycloneiii_ddio_oe is
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
port (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic--;
--dfflo : OUT std_logic;
--dffhi : OUT std_logic;
--devclrn : IN std_logic := '1';
--devpor : IN std_logic := '1'
);
end component;
component DFF is
port(
d, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dq_reg : std_logic;
signal dq_oe_reg, dq_oe_reg_n, dq_oct_reg : std_logic;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dq_oe_reg : signal is true;
attribute syn_preserve of dq_oe_reg : signal is true;
attribute syn_keep of dq_oe_reg_n : signal is true;
attribute syn_preserve of dq_oe_reg_n : signal is true;
begin
vcc <= '1'; gnd <= (others => '0');
-- DQ output register --------------------------------------------------------------
dq_reg0 : cycloneiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => dq_l,
datainhi => dq_h,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dq_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Outout enable and oct for DQ -----------------------------------------------------
-- dq_oe_reg0 : stratixiii_ddio_oe
-- generic map(
-- power_up => "low",
-- async_mode => "none",
-- sync_mode => "none",
-- lpm_type => "stratixiii_ddio_oe"
-- )
-- port map(
-- oe => dq_oe,
-- clk => clk,
-- ena => vcc,
-- areset => gnd(0),
-- sreset => gnd(0),
-- dataout => dq_oe_reg--,
-- --dfflo => open,
-- --dffhi => open,
-- --devclrn => vcc,
-- --devpor => vcc
-- );
-- dq_oe_reg0 : dff
-- port map(
-- d => dq_oe,
-- clk => clk,
-- clrn => vcc,
-- prn => vcc,
-- q => dq_oe_reg
-- );
dq_oe_reg0 : process(clk)
begin if rising_edge(clk) then dq_oe_reg <= not dq_oe; end if; end process;
dq_oe_reg_n <= not dq_oe_reg;
-- dq_oct_reg0 : cycloneiii_ddio_oe
-- generic map(
-- power_up => "low",
-- async_mode => "none",
-- sync_mode => "none",
-- lpm_type => "cycloneiii_ddio_oe"
-- )
-- port map(
-- oe => dq_oct,
-- clk => clk_oct,
-- ena => vcc,
-- areset => gnd(0),
-- sreset => gnd(0),
-- dataout => dq_oct_reg--,
-- --dfflo => open,
-- --dffhi => open,
-- --devclrn => vcc,
-- --devpor => vcc
-- );
-- Out buffer (DQ) ------------------------------------------------------------------
dq_buf0 : cycloneiii_io_obuf
generic map(
open_drain_output => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_obuf"
)
port map(
i => dq_reg,
oe => dq_oe_reg,--_n,
--devoe => vcc,
o => dq_pad,
obar => open
--seriesterminationcontrol => gnd,
);
end;
|
-- $Id: simbus.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: simbus
-- Description: Global signals for support control in test benches
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2010-04-24 282 1.1 add SB_(VAL|ADDR|DATA)
-- 2008-03-24 129 1.0.1 use 31 bits for SB_CLKCYCLE
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package simbus is
signal SB_CLKSTOP : slbit := '0'; -- global clock stop
signal SB_CLKCYCLE : slv31 := (others=>'0'); -- global clock cycle
signal SB_CNTL : slv16 := (others=>'0'); -- global signals tb -> uut
signal SB_STAT : slv16 := (others=>'0'); -- global signals uut -> tb
signal SB_VAL : slbit := '0'; -- init bcast valid
signal SB_ADDR : slv8 := (others=>'0'); -- init bcast address
signal SB_DATA : slv16 := (others=>'0'); -- init bcast data
-- Note: SB_CNTL, SB_VAL, SB_ADDR, SB_DATA can have weak ('L','H') and
-- strong ('0','1') drivers. Therefore always remove strenght before
-- using, e.g. with to_x01()
end package simbus;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc47.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p03n02i00047ent IS
END c04s03b01x01p03n02i00047ent;
ARCHITECTURE c04s03b01x01p03n02i00047arch OF c04s03b01x01p03n02i00047ent IS
function retrieve (VM:integer) return integer is
constant pi : real := 3.142;
begin
pi := 45.00; -- Failure_here - pi is a constant
return 12;
end retrieve;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x01p03n02i00047- The value of a constant cannot be changed after the declartion elaboration."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x01p03n02i00047arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc47.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p03n02i00047ent IS
END c04s03b01x01p03n02i00047ent;
ARCHITECTURE c04s03b01x01p03n02i00047arch OF c04s03b01x01p03n02i00047ent IS
function retrieve (VM:integer) return integer is
constant pi : real := 3.142;
begin
pi := 45.00; -- Failure_here - pi is a constant
return 12;
end retrieve;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x01p03n02i00047- The value of a constant cannot be changed after the declartion elaboration."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x01p03n02i00047arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc47.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p03n02i00047ent IS
END c04s03b01x01p03n02i00047ent;
ARCHITECTURE c04s03b01x01p03n02i00047arch OF c04s03b01x01p03n02i00047ent IS
function retrieve (VM:integer) return integer is
constant pi : real := 3.142;
begin
pi := 45.00; -- Failure_here - pi is a constant
return 12;
end retrieve;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x01p03n02i00047- The value of a constant cannot be changed after the declartion elaboration."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x01p03n02i00047arch;
|
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity registers is
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_op: in regops_t;
I_selS1: in std_logic_vector(4 downto 0);
I_selS2: in std_logic_vector(4 downto 0);
I_selD: in std_logic_vector(4 downto 0);
I_data: in std_logic_vector(XLEN-1 downto 0);
O_dataS1: out std_logic_vector(XLEN-1 downto 0) := XLEN_ZERO;
O_dataS2: out std_logic_vector(XLEN-1 downto 0) := XLEN_ZERO
);
end registers;
architecture Behavioral of registers is
type store_t is array(0 to 31) of std_logic_vector(XLEN-1 downto 0);
signal regs: store_t := (others => X"00000000");
attribute ramstyle : string;
attribute ramstyle of regs : signal is "no_rw_check";
begin
process(I_clk, I_en, I_op, I_selS1, I_selS2, I_selD, I_data)
variable data: std_logic_vector(XLEN-1 downto 0);
begin
if rising_edge(I_clk) and I_en = '1' then
data := X"00000000";
if I_op = REGOP_WRITE and I_selD /= "00000" then
data := I_data;
end if;
-- this is a pattern that Quartus RAM synthesis understands
-- as *not* being read-during-write (with no_rw_check attribute)
if I_op = REGOP_WRITE then
regs(to_integer(unsigned(I_selD))) <= data;
else
O_dataS1 <= regs(to_integer(unsigned(I_selS1)));
O_dataS2 <= regs(to_integer(unsigned(I_selS2)));
end if;
end if;
end process;
end Behavioral; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity clock_gen is
end entity clock_gen;
architecture test of clock_gen is
constant T_pw : time := 10 ns;
signal clk : bit;
begin
-- code from book
clock_gen : process (clk) is
begin
if clk = '0' then
clk <= '1' after T_pw, '0' after 2*T_pw;
end if;
end process clock_gen;
-- end code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity clock_gen is
end entity clock_gen;
architecture test of clock_gen is
constant T_pw : time := 10 ns;
signal clk : bit;
begin
-- code from book
clock_gen : process (clk) is
begin
if clk = '0' then
clk <= '1' after T_pw, '0' after 2*T_pw;
end if;
end process clock_gen;
-- end code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity clock_gen is
end entity clock_gen;
architecture test of clock_gen is
constant T_pw : time := 10 ns;
signal clk : bit;
begin
-- code from book
clock_gen : process (clk) is
begin
if clk = '0' then
clk <= '1' after T_pw, '0' after 2*T_pw;
end if;
end process clock_gen;
-- end code from book
end architecture test;
|
----------------------------------------------------------------------------------
-- Company: none
-- Engineer: Jacob Hladky and Curtis Jonaitis
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rat_cpu is
Port( IN_PORT : in STD_LOGIC_VECTOR(7 downto 0);
INT_IN, RST : in STD_LOGIC;
CLK : in STD_LOGIC;
OUT_PORT : out STD_LOGIC_VECTOR(7 downto 0);
PORT_ID : out STD_LOGIC_VECTOR(7 downto 0);
IO_OE : out STD_LOGIC);
end rat_cpu;
architecture rat_cpu_a of rat_cpu is
component prog_rom is
Port( ADDRESS : in STD_LOGIC_VECTOR(9 downto 0);
CLK : in STD_LOGIC;
TRISTATE_IN : in STD_LOGIC_VECTOR(7 downto 0);
INSTRUCTION : out STD_LOGIC_VECTOR(17 downto 0));
end component;
component flag_reg is
Port( IN_FLAG, SAVE : in STD_LOGIC; --flag input // save the flag value (?)
LD, SET, CLR : in STD_LOGIC; --load the out_flag with the in_flag value // set the flag to '1' // clear the flag to '0'
CLK, RESTORE : in STD_LOGIC; --system clock // restore the flag value (?)
OUT_FLAG : out STD_LOGIC); --flag output
end component;
component program_counter is
Port( CLK, RST, OE : in STD_LOGIC;
LOAD : in STD_LOGIC;
SEL : in STD_LOGIC_VECTOR(1 downto 0);
FROM_IMMED : in STD_LOGIC_VECTOR(9 downto 0);
FROM_STACK : in STD_LOGIC_VECTOR(9 downto 0);
PC_COUNT : out STD_LOGIC_VECTOR(9 downto 0);
PC_TRI : inout STD_LOGIC_VECTOR(9 downto 0));
end component;
component stack_pointer is
Port( INC_DEC : in STD_LOGIC_VECTOR (1 downto 0);
D_IN : in STD_LOGIC_VECTOR (7 downto 0);
WE, RST, CLK : in STD_LOGIC;
STK_PNTR : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component scratch_pad is
Port( FROM_IMMED : in STD_LOGIC_VECTOR(7 downto 0);
FROM_SP : in STD_LOGIC_VECTOR(7 downto 0);
FROM_RF : in STD_LOGIC_VECTOR(7 downto 0);
FROM_SP_DEC : in STD_LOGIC_VECTOR(7 downto 0);
SCR_ADDR_SEL : in STD_LOGIC_VECTOR(1 downto 0);
SCR_WE, SCR_OE : in STD_LOGIC;
CLK : in STD_LOGIC;
SP_DATA : inout STD_LOGIC_VECTOR(9 downto 0));
end component;
component alu
Port( SEL : in STD_LOGIC_VECTOR(3 downto 0);
A, B_FROM_REG : in STD_LOGIC_VECTOR(7 downto 0);
B_FROM_INSTR : in STD_LOGIC_VECTOR(7 downto 0);
C_IN, MUX_SEL : in STD_LOGIC;
SUM : out STD_LOGIC_VECTOR(7 downto 0);
C_FLAG, Z_FLAG : out STD_LOGIC);
end component;
component register_file
Port( FROM_IN_PORT : in STD_LOGIC_VECTOR(7 downto 0);
FROM_TRI_STATE : in STD_LOGIC_VECTOR(7 downto 0);
FROM_ALU : in STD_LOGIC_VECTOR(7 downto 0);
RF_MUX_SEL : in STD_LOGIC_VECTOR(1 downto 0);
ADRX, ADRY : in STD_LOGIC_VECTOR(4 downto 0);
WE, CLK, DX_OE : in STD_LOGIC;
DX_OUT, DY_OUT : out STD_LOGIC_VECTOR(7 downto 0));
end component;
component control_unit
Port( CLK, C, Z, INT, RST : in STD_LOGIC;
OPCODE_HI_5 : in STD_LOGIC_VECTOR (4 downto 0); --From the instruction register
OPCODE_LO_2 : in STD_LOGIC_VECTOR (1 downto 0);
PC_LD, PC_OE, SP_LD, RESET : out STD_LOGIC; --Load PC EN // PC output enable // stack pointer load // Reset PC and SP
PC_MUX_SEL, INC_DEC : out STD_LOGIC_VECTOR (1 downto 0); --PC mux sel// SP input mux sel
ALU_MUX_SEL : out STD_LOGIC; --alu mux sel
RF_WR, RF_OE, SCR_WR, SCR_OE : out STD_LOGIC; --RF Write EN // RF Tristate Output // SP write EN // SP output EN
RF_WR_SEL, SCR_ADDR_SEL : out STD_LOGIC_VECTOR (1 downto 0); -- Reg File Mux // sp mux sel
ALU_SEL : out STD_LOGIC_VECTOR (3 downto 0);
C_FLAG_SAVE, C_FLAG_RESTORE : out STD_LOGIC; -- C flag save and restore
Z_FLAG_SAVE, Z_FLAG_RESTORE : out STD_LOGIC; -- Z flag save and restore
C_FLAG_LD, C_FLAG_SET, C_FLAG_CLR : out STD_LOGIC; -- C flag set, clear, and load
Z_FLAG_LD, Z_FLAG_SET, Z_FLAG_CLR : out STD_LOGIC; -- Z flag set, clear, and load
I_FLAG_SET, I_FLAG_CLR, IO_OE : out STD_LOGIC); -- Set Interrupt // clear interrupt // I/O enable
end component;
signal CU_RESET_i, I_COMB_i : STD_LOGIC;
signal C_IN_i, Z_IN_i, C_OUT_i, Z_OUT_i : STD_LOGIC;
signal C_LD_i, Z_LD_i, C_SET_i, Z_SET_i : STD_LOGIC;
signal C_CLR_i, Z_CLR_i, I_SET_i, I_CLR_i : STD_LOGIC;
signal PC_LD_i, PC_OE_i, RF_OE_i, RF_WR_i : STD_LOGIC;
signal ALU_MUX_SEL_i, I_OUT_i, SP_LD_i : STD_LOGIC;
signal SCR_WR_i, SCR_OE_i, Z_SAVE_i : STD_LOGIC;
signal C_RESTORE_i, Z_RESTORE_i, C_SAVE_i : STD_LOGIC;
signal INC_DEC_i, RF_WR_SEL_i : STD_LOGIC_VECTOR(1 downto 0);
signal SCR_ADDR_SEL_i, PC_MUX_SEL_i : STD_LOGIC_VECTOR(1 downto 0);
signal ALU_SEL_i : STD_LOGIC_VECTOR(3 downto 0);
signal ALU_OUT_i, ADRY_OUT_i : STD_LOGIC_VECTOR(7 downto 0);
signal STK_PNTR_OUT_i : STD_LOGIC_VECTOR(7 downto 0);
signal TRISTATE_BUS_i, PC_COUNT_i : STD_LOGIC_VECTOR(9 downto 0);
signal INSTRUCTION_i : STD_LOGIC_VECTOR(17 downto 0);
begin
out_port <= tristate_bus_i(7 downto 0);
port_id <= instruction_i(7 downto 0);
i_comb_i <= int_in and i_out_i;
prog_rom1 : prog_rom port map(
address => pc_count_i,
instruction => instruction_i,
tristate_in => tristate_bus_i(7 downto 0),
clk => clk);
c_flag : flag_reg port map(
in_flag => c_in_i,
ld => c_ld_i,
set => c_set_i,
clr => c_clr_i,
clk => clk,
restore => c_restore_i,
save => c_save_i,
out_flag => c_out_i);
z_flag : flag_reg port map(
in_flag => z_in_i,
ld => z_ld_i,
set => z_set_i,
clr => z_clr_i,
clk => clk,
restore => z_restore_i,
save => z_save_i,
out_flag => z_out_i);
i_flag : flag_reg port map(
in_flag => '0',
ld => '0',
set => i_set_i,
clr => i_clr_i,
clk => clk,
restore => '0',
save => '0',
out_flag => i_out_i);
program_counter1 : program_counter port map(
clk => clk,
rst => cu_reset_i,
load => pc_ld_i,
oe => pc_oe_i,
sel => pc_mux_sel_i,
from_immed => instruction_i(12 downto 3),
from_stack => tristate_bus_i,
pc_count => pc_count_i,
pc_tri => tristate_bus_i);
stack_pointer1 : stack_pointer port map(
inc_dec => inc_dec_i,
d_in => tristate_bus_i(7 downto 0),
we => sp_ld_i,
rst => cu_reset_i,
clk => clk,
stk_pntr => stk_pntr_out_i);
scratch_pad1: scratch_pad port map(
clk => clk,
scr_we => scr_wr_i,
scr_oe => scr_oe_i,
scr_addr_sel => scr_addr_sel_i,
from_immed => instruction_i(7 downto 0),
from_sp => stk_pntr_out_i,
from_sp_dec => stk_pntr_out_i, --This is correct, deincrement is done INTERNALLY
from_rf => adry_out_i,
sp_data => tristate_bus_i);
alu1 : alu port map(
sel => alu_sel_i,
a => tristate_bus_i(7 downto 0),
b_from_reg => adry_out_i,
b_from_instr => instruction_i(7 downto 0),
c_in => c_out_i,
mux_sel => alu_mux_sel_i,
sum => alu_out_i,
c_flag => c_in_i,
z_flag => z_in_i);
register_file1 : register_file port map(
from_in_port => in_port,
from_tri_state => tristate_bus_i(7 downto 0),
from_alu => alu_out_i,
rf_mux_sel => rf_wr_sel_i,
adrx => instruction_i(12 downto 8),
adry => instruction_i(7 downto 3),
we => rf_wr_i,
clk => clk,
dx_oe => rf_oe_i,
dx_out => tristate_bus_i(7 downto 0),
dy_out => adry_out_i);
control_unit1 : control_unit port map(
clk => clk,
c => c_out_i,
z => z_out_i,
int => i_comb_i,
rst => rst,
opcode_hi_5 => instruction_i(17 downto 13),
opcode_lo_2 => instruction_i(1 downto 0),
reset => cu_reset_i,
pc_ld => pc_ld_i,
pc_oe => pc_oe_i,
pc_mux_sel => pc_mux_sel_i,
sp_ld => sp_ld_i,
inc_dec => inc_dec_i,
rf_wr => rf_wr_i,
rf_oe => rf_oe_i,
rf_wr_sel => rf_wr_sel_i,
scr_wr => scr_wr_i,
scr_oe => scr_oe_i,
scr_addr_sel => scr_addr_sel_i,
alu_mux_sel => alu_mux_sel_i,
alu_sel => alu_sel_i,
c_flag_restore => c_restore_i,
c_flag_save => c_save_i,
c_flag_ld => c_ld_i,
c_flag_set => c_set_i,
c_flag_clr => c_clr_i,
z_flag_restore => z_restore_i,
z_flag_save => z_save_i,
z_flag_ld => z_ld_i,
z_flag_set => z_set_i,
z_flag_clr => z_clr_i,
i_flag_set => i_set_i,
i_flag_clr => i_clr_i,
io_oe => io_oe);
end rat_cpu_a; |
-- SIMON 64/128
-- feistel round function test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round IS
END tb_round;
ARCHITECTURE behavior OF tb_round IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
port(v_in : in std_logic_vector(63 downto 0);
v_k : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal v_k : std_logic_vector(31 downto 0) := (others => '0'); -- Round Key
signal v_in : std_logic_vector(63 downto 0) := (others => '0'); -- Input block
--Outputs
signal v_out : std_logic_vector(63 downto 0); -- Output block
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: round_f PORT MAP (
v_in => v_in,
v_k => v_k,
v_out => v_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
-- SIMON 64/128 test vectors
v_in <= X"656B696C20646E75";
v_k <= X"03020100";
-- Do round
wait for clk_period;
assert v_out = X"FC8B8A84656B696C"
report "ROUND_F ERROR (r_0)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
-- SIMON 64/128
-- feistel round function test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round IS
END tb_round;
ARCHITECTURE behavior OF tb_round IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
port(v_in : in std_logic_vector(63 downto 0);
v_k : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal v_k : std_logic_vector(31 downto 0) := (others => '0'); -- Round Key
signal v_in : std_logic_vector(63 downto 0) := (others => '0'); -- Input block
--Outputs
signal v_out : std_logic_vector(63 downto 0); -- Output block
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: round_f PORT MAP (
v_in => v_in,
v_k => v_k,
v_out => v_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
-- SIMON 64/128 test vectors
v_in <= X"656B696C20646E75";
v_k <= X"03020100";
-- Do round
wait for clk_period;
assert v_out = X"FC8B8A84656B696C"
report "ROUND_F ERROR (r_0)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
-- SIMON 64/128
-- feistel round function test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round IS
END tb_round;
ARCHITECTURE behavior OF tb_round IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
port(v_in : in std_logic_vector(63 downto 0);
v_k : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal v_k : std_logic_vector(31 downto 0) := (others => '0'); -- Round Key
signal v_in : std_logic_vector(63 downto 0) := (others => '0'); -- Input block
--Outputs
signal v_out : std_logic_vector(63 downto 0); -- Output block
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: round_f PORT MAP (
v_in => v_in,
v_k => v_k,
v_out => v_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
-- SIMON 64/128 test vectors
v_in <= X"656B696C20646E75";
v_k <= X"03020100";
-- Do round
wait for clk_period;
assert v_out = X"FC8B8A84656B696C"
report "ROUND_F ERROR (r_0)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
package pack is
type rec is record
x, y : natural;
end record;
function rec_to_int (r : rec) return natural;
function int_to_rec (x : natural) return rec;
end package;
package body pack is
function rec_to_int (r : rec) return natural is
begin
return r.x + r.y;
end function;
function int_to_rec (x : natural) return rec is
begin
return (x / 2, x * 2);
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
i1 : in rec;
i2 : in natural );
end entity;
architecture test of sub is
begin
p1: process is
begin
assert i1 = ( 0, 0 );
assert i2 = 0;
wait for 0 ns;
assert i1 = ( 3, 12 );
assert i2 = 5;
wait for 2 ns;
assert i2 = 8;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack.all;
entity conv7 is
end entity;
architecture test of conv7 is
signal s1 : natural;
signal s2 : rec;
begin
uut: entity work.sub
port map (
i1 => int_to_rec(s1),
i2 => rec_to_int(s2) );
main: process is
begin
s1 <= 6;
s2 <= (2, 3);
wait for 1 ns;
s2.y <= 6;
wait;
end process;
end architecture;
|
--
-- package for tagged sorter: constant and others for
--
-- Author: Insop Song
-- Begin Date : 2007 05 01
-- Ver : 0.1
--
-- Revision History
-- ---------------------------------------------------------------
-- Date Author Comments
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package tagged_pak is
-- Design specific settings
constant WIDTH_KEY : integer := 32;
constant WIDTH_DATA : integer := 32;
end tagged_pak;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_b_e
--
-- Generated
-- by: wig
-- on: Thu Apr 27 05:43:23 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-rtl-a.vhd,v 1.3 2006/09/25 09:49:31 wig Exp $
-- $Date: 2006/09/25 09:49:31 $
-- $Log: inst_b_e-rtl-a.vhd,v $
-- Revision 1.3 2006/09/25 09:49:31 wig
-- Update testcase repository.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_b_e
--
architecture rtl of inst_b_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_ba
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ent_bb
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_ba
inst_ba: ent_ba
;
-- End of Generated Instance Port Map for inst_ba
-- Generated Instance Port Map for inst_bb
inst_bb: ent_bb
;
-- End of Generated Instance Port Map for inst_bb
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
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