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------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Delayed bidirectional wire
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity delay_wire is
generic(
data_width : integer := 1;
delay_atob : real := 0.0;
delay_btoa : real := 0.0
);
port(
a : inout std_logic_vector(data_width-1 downto 0);
b : inout std_logic_vector(data_width-1 downto 0);
x : in std_logic_vector(data_width-1 downto 0) := (others => '0')
);
end delay_wire;
architecture rtl of delay_wire is
signal a_dly,b_dly : std_logic_vector(data_width-1 downto 0) := (others => 'Z');
constant zvector : std_logic_vector(data_width-1 downto 0) := (others => 'Z');
function errinj(a,b: std_logic_vector) return std_logic_vector is
variable r: std_logic_vector(a'length-1 downto 0);
begin
r := a;
for k in a'length-1 downto 0 loop
if (a(k)='0' or a(k)='1') and b(k)='1' then
r(k) := not a(k);
end if;
end loop;
return r;
end;
begin
process(a)
begin
if a'event then
if b_dly = zvector then
a_dly <= transport a after delay_atob*1 ns;
else
a_dly <= (others => 'Z');
end if;
end if;
end process;
process(b)
begin
if b'event then
if a_dly = zvector then
b_dly <= transport errinj(b,x) after delay_btoa*1 ns;
else
b_dly <= (others => 'Z');
end if;
end if;
end process;
a <= b_dly; b <= a_dly;
end;
|
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity AEAD is
generic (
G_PWIDTH : integer := 32;
G_SWIDTH : integer := 32;
G_AUX_FIFO_CAPACITY : integer := 131072
);
port (
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_PWIDTH -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SWIDTH -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out signals
do : out std_logic_vector(G_PWIDTH -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD;
-------------------------------------------------------------------------------
--! @brief Architecture definition of crypto_template
-------------------------------------------------------------------------------
architecture structure of AEAD is
constant AUX_FIFO_DEPTH : integer := G_AUX_FIFO_CAPACITY/G_PWIDTH;
signal bypass_fifo_rd : std_logic;
signal bypass_fifo_wr : std_logic;
signal bypass_fifo_data : std_logic_vector(G_PWIDTH-1 downto 0);
signal bypass_fifo_full : std_logic;
signal bypass_fifo_empty : std_logic;
signal aux_fifo_din : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_dout : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_ctrl : std_logic_vector(3 downto 0);
signal aux_fifo_status : std_logic_vector(2 downto 0);
begin
u_logic:
entity work.AEAD_Core(structure)
generic map (
G_W => G_PWIDTH ,
G_SW => G_SWIDTH
)
port map (
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid,
pdi_ready => pdi_ready,
sdi => sdi ,
sdi_valid => sdi_valid,
sdi_ready => sdi_ready,
do => do ,
do_ready => do_ready ,
do_valid => do_valid ,
--! FIFO signals
bypass_fifo_wr => bypass_fifo_wr,
bypass_fifo_rd => bypass_fifo_rd,
bypass_fifo_data => bypass_fifo_data,
bypass_fifo_full => bypass_fifo_full,
bypass_fifo_empty => bypass_fifo_empty,
aux_fifo_din => aux_fifo_din,
aux_fifo_dout => aux_fifo_dout,
aux_fifo_ctrl => aux_fifo_ctrl,
aux_fifo_status => aux_fifo_status
);
u_memory: block
begin
u_bypass_fifo:
entity work.fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => 6)
port map (
clk => clk ,
rst => rst ,
write => bypass_fifo_wr ,
read => bypass_fifo_rd ,
din => pdi ,
dout => bypass_fifo_data ,
almost_full => bypass_fifo_full ,
empty => bypass_fifo_empty
);
u_aux_fifo:
entity work.aux_fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => log2_ceil(AUX_FIFO_DEPTH))
port map (
clk => clk ,
rst => rst ,
fifo_din => aux_fifo_din ,
fifo_dout => aux_fifo_dout ,
fifo_ctrl_in => aux_fifo_ctrl ,
fifo_ctrl_out => aux_fifo_status
);
end block u_memory;
end structure; |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity AEAD is
generic (
G_PWIDTH : integer := 32;
G_SWIDTH : integer := 32;
G_AUX_FIFO_CAPACITY : integer := 131072
);
port (
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_PWIDTH -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SWIDTH -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out signals
do : out std_logic_vector(G_PWIDTH -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD;
-------------------------------------------------------------------------------
--! @brief Architecture definition of crypto_template
-------------------------------------------------------------------------------
architecture structure of AEAD is
constant AUX_FIFO_DEPTH : integer := G_AUX_FIFO_CAPACITY/G_PWIDTH;
signal bypass_fifo_rd : std_logic;
signal bypass_fifo_wr : std_logic;
signal bypass_fifo_data : std_logic_vector(G_PWIDTH-1 downto 0);
signal bypass_fifo_full : std_logic;
signal bypass_fifo_empty : std_logic;
signal aux_fifo_din : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_dout : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_ctrl : std_logic_vector(3 downto 0);
signal aux_fifo_status : std_logic_vector(2 downto 0);
begin
u_logic:
entity work.AEAD_Core(structure)
generic map (
G_W => G_PWIDTH ,
G_SW => G_SWIDTH
)
port map (
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid,
pdi_ready => pdi_ready,
sdi => sdi ,
sdi_valid => sdi_valid,
sdi_ready => sdi_ready,
do => do ,
do_ready => do_ready ,
do_valid => do_valid ,
--! FIFO signals
bypass_fifo_wr => bypass_fifo_wr,
bypass_fifo_rd => bypass_fifo_rd,
bypass_fifo_data => bypass_fifo_data,
bypass_fifo_full => bypass_fifo_full,
bypass_fifo_empty => bypass_fifo_empty,
aux_fifo_din => aux_fifo_din,
aux_fifo_dout => aux_fifo_dout,
aux_fifo_ctrl => aux_fifo_ctrl,
aux_fifo_status => aux_fifo_status
);
u_memory: block
begin
u_bypass_fifo:
entity work.fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => 6)
port map (
clk => clk ,
rst => rst ,
write => bypass_fifo_wr ,
read => bypass_fifo_rd ,
din => pdi ,
dout => bypass_fifo_data ,
almost_full => bypass_fifo_full ,
empty => bypass_fifo_empty
);
u_aux_fifo:
entity work.aux_fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => log2_ceil(AUX_FIFO_DEPTH))
port map (
clk => clk ,
rst => rst ,
fifo_din => aux_fifo_din ,
fifo_dout => aux_fifo_dout ,
fifo_ctrl_in => aux_fifo_ctrl ,
fifo_ctrl_out => aux_fifo_status
);
end block u_memory;
end structure; |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity AEAD is
generic (
G_PWIDTH : integer := 32;
G_SWIDTH : integer := 32;
G_AUX_FIFO_CAPACITY : integer := 131072
);
port (
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_PWIDTH -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SWIDTH -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out signals
do : out std_logic_vector(G_PWIDTH -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD;
-------------------------------------------------------------------------------
--! @brief Architecture definition of crypto_template
-------------------------------------------------------------------------------
architecture structure of AEAD is
constant AUX_FIFO_DEPTH : integer := G_AUX_FIFO_CAPACITY/G_PWIDTH;
signal bypass_fifo_rd : std_logic;
signal bypass_fifo_wr : std_logic;
signal bypass_fifo_data : std_logic_vector(G_PWIDTH-1 downto 0);
signal bypass_fifo_full : std_logic;
signal bypass_fifo_empty : std_logic;
signal aux_fifo_din : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_dout : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_ctrl : std_logic_vector(3 downto 0);
signal aux_fifo_status : std_logic_vector(2 downto 0);
begin
u_logic:
entity work.AEAD_Core(structure)
generic map (
G_W => G_PWIDTH ,
G_SW => G_SWIDTH
)
port map (
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid,
pdi_ready => pdi_ready,
sdi => sdi ,
sdi_valid => sdi_valid,
sdi_ready => sdi_ready,
do => do ,
do_ready => do_ready ,
do_valid => do_valid ,
--! FIFO signals
bypass_fifo_wr => bypass_fifo_wr,
bypass_fifo_rd => bypass_fifo_rd,
bypass_fifo_data => bypass_fifo_data,
bypass_fifo_full => bypass_fifo_full,
bypass_fifo_empty => bypass_fifo_empty,
aux_fifo_din => aux_fifo_din,
aux_fifo_dout => aux_fifo_dout,
aux_fifo_ctrl => aux_fifo_ctrl,
aux_fifo_status => aux_fifo_status
);
u_memory: block
begin
u_bypass_fifo:
entity work.fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => 6)
port map (
clk => clk ,
rst => rst ,
write => bypass_fifo_wr ,
read => bypass_fifo_rd ,
din => pdi ,
dout => bypass_fifo_data ,
almost_full => bypass_fifo_full ,
empty => bypass_fifo_empty
);
u_aux_fifo:
entity work.aux_fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => log2_ceil(AUX_FIFO_DEPTH))
port map (
clk => clk ,
rst => rst ,
fifo_din => aux_fifo_din ,
fifo_dout => aux_fifo_dout ,
fifo_ctrl_in => aux_fifo_ctrl ,
fifo_ctrl_out => aux_fifo_status
);
end block u_memory;
end structure; |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity AEAD is
generic (
G_PWIDTH : integer := 32;
G_SWIDTH : integer := 32;
G_AUX_FIFO_CAPACITY : integer := 131072
);
port (
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_PWIDTH -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SWIDTH -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out signals
do : out std_logic_vector(G_PWIDTH -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD;
-------------------------------------------------------------------------------
--! @brief Architecture definition of crypto_template
-------------------------------------------------------------------------------
architecture structure of AEAD is
constant AUX_FIFO_DEPTH : integer := G_AUX_FIFO_CAPACITY/G_PWIDTH;
signal bypass_fifo_rd : std_logic;
signal bypass_fifo_wr : std_logic;
signal bypass_fifo_data : std_logic_vector(G_PWIDTH-1 downto 0);
signal bypass_fifo_full : std_logic;
signal bypass_fifo_empty : std_logic;
signal aux_fifo_din : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_dout : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_ctrl : std_logic_vector(3 downto 0);
signal aux_fifo_status : std_logic_vector(2 downto 0);
begin
u_logic:
entity work.AEAD_Core(structure)
generic map (
G_W => G_PWIDTH ,
G_SW => G_SWIDTH
)
port map (
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid,
pdi_ready => pdi_ready,
sdi => sdi ,
sdi_valid => sdi_valid,
sdi_ready => sdi_ready,
do => do ,
do_ready => do_ready ,
do_valid => do_valid ,
--! FIFO signals
bypass_fifo_wr => bypass_fifo_wr,
bypass_fifo_rd => bypass_fifo_rd,
bypass_fifo_data => bypass_fifo_data,
bypass_fifo_full => bypass_fifo_full,
bypass_fifo_empty => bypass_fifo_empty,
aux_fifo_din => aux_fifo_din,
aux_fifo_dout => aux_fifo_dout,
aux_fifo_ctrl => aux_fifo_ctrl,
aux_fifo_status => aux_fifo_status
);
u_memory: block
begin
u_bypass_fifo:
entity work.fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => 6)
port map (
clk => clk ,
rst => rst ,
write => bypass_fifo_wr ,
read => bypass_fifo_rd ,
din => pdi ,
dout => bypass_fifo_data ,
almost_full => bypass_fifo_full ,
empty => bypass_fifo_empty
);
u_aux_fifo:
entity work.aux_fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => log2_ceil(AUX_FIFO_DEPTH))
port map (
clk => clk ,
rst => rst ,
fifo_din => aux_fifo_din ,
fifo_dout => aux_fifo_dout ,
fifo_ctrl_in => aux_fifo_ctrl ,
fifo_ctrl_out => aux_fifo_status
);
end block u_memory;
end structure; |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity AEAD is
generic (
G_PWIDTH : integer := 32;
G_SWIDTH : integer := 32;
G_AUX_FIFO_CAPACITY : integer := 131072
);
port (
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_PWIDTH -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SWIDTH -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out signals
do : out std_logic_vector(G_PWIDTH -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD;
-------------------------------------------------------------------------------
--! @brief Architecture definition of crypto_template
-------------------------------------------------------------------------------
architecture structure of AEAD is
constant AUX_FIFO_DEPTH : integer := G_AUX_FIFO_CAPACITY/G_PWIDTH;
signal bypass_fifo_rd : std_logic;
signal bypass_fifo_wr : std_logic;
signal bypass_fifo_data : std_logic_vector(G_PWIDTH-1 downto 0);
signal bypass_fifo_full : std_logic;
signal bypass_fifo_empty : std_logic;
signal aux_fifo_din : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_dout : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_ctrl : std_logic_vector(3 downto 0);
signal aux_fifo_status : std_logic_vector(2 downto 0);
begin
u_logic:
entity work.AEAD_Core(structure)
generic map (
G_W => G_PWIDTH ,
G_SW => G_SWIDTH
)
port map (
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid,
pdi_ready => pdi_ready,
sdi => sdi ,
sdi_valid => sdi_valid,
sdi_ready => sdi_ready,
do => do ,
do_ready => do_ready ,
do_valid => do_valid ,
--! FIFO signals
bypass_fifo_wr => bypass_fifo_wr,
bypass_fifo_rd => bypass_fifo_rd,
bypass_fifo_data => bypass_fifo_data,
bypass_fifo_full => bypass_fifo_full,
bypass_fifo_empty => bypass_fifo_empty,
aux_fifo_din => aux_fifo_din,
aux_fifo_dout => aux_fifo_dout,
aux_fifo_ctrl => aux_fifo_ctrl,
aux_fifo_status => aux_fifo_status
);
u_memory: block
begin
u_bypass_fifo:
entity work.fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => 6)
port map (
clk => clk ,
rst => rst ,
write => bypass_fifo_wr ,
read => bypass_fifo_rd ,
din => pdi ,
dout => bypass_fifo_data ,
almost_full => bypass_fifo_full ,
empty => bypass_fifo_empty
);
u_aux_fifo:
entity work.aux_fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => log2_ceil(AUX_FIFO_DEPTH))
port map (
clk => clk ,
rst => rst ,
fifo_din => aux_fifo_din ,
fifo_dout => aux_fifo_dout ,
fifo_ctrl_in => aux_fifo_ctrl ,
fifo_ctrl_out => aux_fifo_status
);
end block u_memory;
end structure; |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity AEAD is
generic (
G_PWIDTH : integer := 32;
G_SWIDTH : integer := 32;
G_AUX_FIFO_CAPACITY : integer := 131072
);
port (
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_PWIDTH -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SWIDTH -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out signals
do : out std_logic_vector(G_PWIDTH -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD;
-------------------------------------------------------------------------------
--! @brief Architecture definition of crypto_template
-------------------------------------------------------------------------------
architecture structure of AEAD is
constant AUX_FIFO_DEPTH : integer := G_AUX_FIFO_CAPACITY/G_PWIDTH;
signal bypass_fifo_rd : std_logic;
signal bypass_fifo_wr : std_logic;
signal bypass_fifo_data : std_logic_vector(G_PWIDTH-1 downto 0);
signal bypass_fifo_full : std_logic;
signal bypass_fifo_empty : std_logic;
signal aux_fifo_din : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_dout : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_ctrl : std_logic_vector(3 downto 0);
signal aux_fifo_status : std_logic_vector(2 downto 0);
begin
u_logic:
entity work.AEAD_Core(structure)
generic map (
G_W => G_PWIDTH ,
G_SW => G_SWIDTH
)
port map (
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid,
pdi_ready => pdi_ready,
sdi => sdi ,
sdi_valid => sdi_valid,
sdi_ready => sdi_ready,
do => do ,
do_ready => do_ready ,
do_valid => do_valid ,
--! FIFO signals
bypass_fifo_wr => bypass_fifo_wr,
bypass_fifo_rd => bypass_fifo_rd,
bypass_fifo_data => bypass_fifo_data,
bypass_fifo_full => bypass_fifo_full,
bypass_fifo_empty => bypass_fifo_empty,
aux_fifo_din => aux_fifo_din,
aux_fifo_dout => aux_fifo_dout,
aux_fifo_ctrl => aux_fifo_ctrl,
aux_fifo_status => aux_fifo_status
);
u_memory: block
begin
u_bypass_fifo:
entity work.fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => 6)
port map (
clk => clk ,
rst => rst ,
write => bypass_fifo_wr ,
read => bypass_fifo_rd ,
din => pdi ,
dout => bypass_fifo_data ,
almost_full => bypass_fifo_full ,
empty => bypass_fifo_empty
);
u_aux_fifo:
entity work.aux_fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => log2_ceil(AUX_FIFO_DEPTH))
port map (
clk => clk ,
rst => rst ,
fifo_din => aux_fifo_din ,
fifo_dout => aux_fifo_dout ,
fifo_ctrl_in => aux_fifo_ctrl ,
fifo_ctrl_out => aux_fifo_status
);
end block u_memory;
end structure; |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity AEAD is
generic (
G_PWIDTH : integer := 32;
G_SWIDTH : integer := 32;
G_AUX_FIFO_CAPACITY : integer := 131072
);
port (
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_PWIDTH -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SWIDTH -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out signals
do : out std_logic_vector(G_PWIDTH -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD;
-------------------------------------------------------------------------------
--! @brief Architecture definition of crypto_template
-------------------------------------------------------------------------------
architecture structure of AEAD is
constant AUX_FIFO_DEPTH : integer := G_AUX_FIFO_CAPACITY/G_PWIDTH;
signal bypass_fifo_rd : std_logic;
signal bypass_fifo_wr : std_logic;
signal bypass_fifo_data : std_logic_vector(G_PWIDTH-1 downto 0);
signal bypass_fifo_full : std_logic;
signal bypass_fifo_empty : std_logic;
signal aux_fifo_din : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_dout : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_ctrl : std_logic_vector(3 downto 0);
signal aux_fifo_status : std_logic_vector(2 downto 0);
begin
u_logic:
entity work.AEAD_Core(structure)
generic map (
G_W => G_PWIDTH ,
G_SW => G_SWIDTH
)
port map (
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid,
pdi_ready => pdi_ready,
sdi => sdi ,
sdi_valid => sdi_valid,
sdi_ready => sdi_ready,
do => do ,
do_ready => do_ready ,
do_valid => do_valid ,
--! FIFO signals
bypass_fifo_wr => bypass_fifo_wr,
bypass_fifo_rd => bypass_fifo_rd,
bypass_fifo_data => bypass_fifo_data,
bypass_fifo_full => bypass_fifo_full,
bypass_fifo_empty => bypass_fifo_empty,
aux_fifo_din => aux_fifo_din,
aux_fifo_dout => aux_fifo_dout,
aux_fifo_ctrl => aux_fifo_ctrl,
aux_fifo_status => aux_fifo_status
);
u_memory: block
begin
u_bypass_fifo:
entity work.fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => 6)
port map (
clk => clk ,
rst => rst ,
write => bypass_fifo_wr ,
read => bypass_fifo_rd ,
din => pdi ,
dout => bypass_fifo_data ,
almost_full => bypass_fifo_full ,
empty => bypass_fifo_empty
);
u_aux_fifo:
entity work.aux_fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => log2_ceil(AUX_FIFO_DEPTH))
port map (
clk => clk ,
rst => rst ,
fifo_din => aux_fifo_din ,
fifo_dout => aux_fifo_dout ,
fifo_ctrl_in => aux_fifo_ctrl ,
fifo_ctrl_out => aux_fifo_status
);
end block u_memory;
end structure; |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity AEAD is
generic (
G_PWIDTH : integer := 32;
G_SWIDTH : integer := 32;
G_AUX_FIFO_CAPACITY : integer := 131072
);
port (
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_PWIDTH -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SWIDTH -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out signals
do : out std_logic_vector(G_PWIDTH -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD;
-------------------------------------------------------------------------------
--! @brief Architecture definition of crypto_template
-------------------------------------------------------------------------------
architecture structure of AEAD is
constant AUX_FIFO_DEPTH : integer := G_AUX_FIFO_CAPACITY/G_PWIDTH;
signal bypass_fifo_rd : std_logic;
signal bypass_fifo_wr : std_logic;
signal bypass_fifo_data : std_logic_vector(G_PWIDTH-1 downto 0);
signal bypass_fifo_full : std_logic;
signal bypass_fifo_empty : std_logic;
signal aux_fifo_din : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_dout : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_ctrl : std_logic_vector(3 downto 0);
signal aux_fifo_status : std_logic_vector(2 downto 0);
begin
u_logic:
entity work.AEAD_Core(structure)
generic map (
G_W => G_PWIDTH ,
G_SW => G_SWIDTH
)
port map (
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid,
pdi_ready => pdi_ready,
sdi => sdi ,
sdi_valid => sdi_valid,
sdi_ready => sdi_ready,
do => do ,
do_ready => do_ready ,
do_valid => do_valid ,
--! FIFO signals
bypass_fifo_wr => bypass_fifo_wr,
bypass_fifo_rd => bypass_fifo_rd,
bypass_fifo_data => bypass_fifo_data,
bypass_fifo_full => bypass_fifo_full,
bypass_fifo_empty => bypass_fifo_empty,
aux_fifo_din => aux_fifo_din,
aux_fifo_dout => aux_fifo_dout,
aux_fifo_ctrl => aux_fifo_ctrl,
aux_fifo_status => aux_fifo_status
);
u_memory: block
begin
u_bypass_fifo:
entity work.fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => 6)
port map (
clk => clk ,
rst => rst ,
write => bypass_fifo_wr ,
read => bypass_fifo_rd ,
din => pdi ,
dout => bypass_fifo_data ,
almost_full => bypass_fifo_full ,
empty => bypass_fifo_empty
);
u_aux_fifo:
entity work.aux_fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => log2_ceil(AUX_FIFO_DEPTH))
port map (
clk => clk ,
rst => rst ,
fifo_din => aux_fifo_din ,
fifo_dout => aux_fifo_dout ,
fifo_ctrl_in => aux_fifo_ctrl ,
fifo_ctrl_out => aux_fifo_status
);
end block u_memory;
end structure; |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity AEAD is
generic (
G_PWIDTH : integer := 32;
G_SWIDTH : integer := 32;
G_AUX_FIFO_CAPACITY : integer := 131072
);
port (
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_PWIDTH -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SWIDTH -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out signals
do : out std_logic_vector(G_PWIDTH -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD;
-------------------------------------------------------------------------------
--! @brief Architecture definition of crypto_template
-------------------------------------------------------------------------------
architecture structure of AEAD is
constant AUX_FIFO_DEPTH : integer := G_AUX_FIFO_CAPACITY/G_PWIDTH;
signal bypass_fifo_rd : std_logic;
signal bypass_fifo_wr : std_logic;
signal bypass_fifo_data : std_logic_vector(G_PWIDTH-1 downto 0);
signal bypass_fifo_full : std_logic;
signal bypass_fifo_empty : std_logic;
signal aux_fifo_din : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_dout : std_logic_vector(G_PWIDTH-1 downto 0);
signal aux_fifo_ctrl : std_logic_vector(3 downto 0);
signal aux_fifo_status : std_logic_vector(2 downto 0);
begin
u_logic:
entity work.AEAD_Core(structure)
generic map (
G_W => G_PWIDTH ,
G_SW => G_SWIDTH
)
port map (
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid,
pdi_ready => pdi_ready,
sdi => sdi ,
sdi_valid => sdi_valid,
sdi_ready => sdi_ready,
do => do ,
do_ready => do_ready ,
do_valid => do_valid ,
--! FIFO signals
bypass_fifo_wr => bypass_fifo_wr,
bypass_fifo_rd => bypass_fifo_rd,
bypass_fifo_data => bypass_fifo_data,
bypass_fifo_full => bypass_fifo_full,
bypass_fifo_empty => bypass_fifo_empty,
aux_fifo_din => aux_fifo_din,
aux_fifo_dout => aux_fifo_dout,
aux_fifo_ctrl => aux_fifo_ctrl,
aux_fifo_status => aux_fifo_status
);
u_memory: block
begin
u_bypass_fifo:
entity work.fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => 6)
port map (
clk => clk ,
rst => rst ,
write => bypass_fifo_wr ,
read => bypass_fifo_rd ,
din => pdi ,
dout => bypass_fifo_data ,
almost_full => bypass_fifo_full ,
empty => bypass_fifo_empty
);
u_aux_fifo:
entity work.aux_fifo(structure)
generic map (G_W => G_PWIDTH, G_LOG2DEPTH => log2_ceil(AUX_FIFO_DEPTH))
port map (
clk => clk ,
rst => rst ,
fifo_din => aux_fifo_din ,
fifo_dout => aux_fifo_dout ,
fifo_ctrl_in => aux_fifo_ctrl ,
fifo_ctrl_out => aux_fifo_status
);
end block u_memory;
end structure; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 8 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal clk_vga : std_logic := '0';
signal rst : std_logic := '0';
signal rstn1 : std_logic;
signal rstn2 : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic_vector(1 downto 0);
signal ddr_clkb : std_logic_vector(1 downto 0);
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(3 downto 0); -- dm
signal ddr_dqs : std_logic_vector(3 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(3 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(1 downto 0); -- bank address
signal ddr_dq : std_logic_vector(31 downto 0); -- data
signal ddr_dq2 : std_logic_vector(31 downto 0); -- data
signal ddr_odt : std_logic;
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic;
signal erxdt : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
-- SVGA signals
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(3 downto 0);
signal vid_g : std_logic_vector(3 downto 0);
signal vid_b : std_logic_vector(3 downto 0);
-- Select signal for SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_logic;
signal spi_mosi : std_logic;
-- Output signals for LEDs
signal led : std_logic_vector(2 downto 0);
signal brdyn : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk_vga <= not clk_vga after 20 ns;
rst <= '1', '0' after 100 ns;
dsubre <= '0';
urxd <= 'H';
spi_sel_n <= 'H';
spi_clk <= 'L';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
reset => rst,
reset_o1 => rstn1,
reset_o2 => rstn2,
clk_in => clk,
clk_vga => clk_vga,
errorn => error,
-- PROM
address => address(23 downto 0),
data => data(31 downto 24),
romsn => romsn,
oen => oen,
writen => writen,
iosn => iosn,
testdata => data(23 downto 0),
-- DDR2
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_clk_fb_out => ddr_clk_fb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_we => ddr_we,
ddr_ras => ddr_ras,
ddr_cas => ddr_cas,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_dqsn => ddr_dqsn,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
ddr_odt => ddr_odt,
-- Debug Unit
dsubre => dsubre,
-- AHB Uart
dsutx => dsutx,
dsurx => dsurx,
-- PHY
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxdt(3 downto 0),
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxdt(3 downto 0),
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc,
emdio => emdio,
-- SVGA
vid_hsync => vid_hsync,
vid_vsync => vid_vsync,
vid_r => vid_r,
vid_g => vid_g,
vid_b => vid_b,
-- SPI flash select
spi_sel_n => spi_sel_n,
spi_clk => spi_clk,
spi_mosi => spi_mosi,
-- Output signals for LEDs
led => led
);
ddr2mem : if (CFG_DDR2SP /= 0) generate
-- ddr2mem0 : for i in 0 to 1 generate
-- u1 : HY5PS121621F
-- generic map (TimingCheckFlag => true, PUSCheckFlag => false,
-- index => 1-i, bbits => 32, fname => sdramfile)
-- port map (DQ => ddr_dq2(i*16+15 downto i*16),
-- LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2),
-- UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1),
-- LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas,
-- RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba,
-- ADDR => ddr_ad(12 downto 0), CKE => ddr_cke,
-- CLK => ddr_clk(i), CLKB => ddr_clkb(i), UDM => ddr_dm(i*2+1));
-- end generate;
ddr0 : ddr2ram
generic map(width => 32, abits => 13, babits =>2, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2)
port map (ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke, csn => ddr_csb,
odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba(1 downto 0), a => ddr_ad(12 downto 0), dq => ddr_dq2,
dqs => ddr_dqs);
ddr2delay0 : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 1.0)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
prom0 : sram
generic map (index => 6, abits => 24, fname => promfile)
port map (address(23 downto 0), data(31 downto 24), romsn, writen, oen);
phy0 : if (CFG_GRETH = 1) generate
etxdt(7 downto 4) <= "0000";
emdio <= 'H';
p0: phy
generic map (address => 1)
port map(rstn1, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er,
erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, '0');
end generate;
spimem0: if CFG_SPIMCTRL = 1 generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => 0) -- Dual output is not supported in this design
port map (spi_clk, spi_mosi, data(24), spi_sel_n);
end generate spimem0;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data, iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
|
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_top.vhd,v 1.8 2009-01-20 10:38:45 rherveille Exp $
--
-- $Date: 2009-01-20 10:38:45 $
-- $Revision: 1.8 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- Revision 1.7 2004/03/14 10:17:03 rherveille
-- Fixed simulation issue when writing to CR register
--
-- Revision 1.6 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.5 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.4 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.3 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.2 2001/11/10 10:52:44 rherveille
-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_master_top is
generic(
ARST_LVL : std_logic := '0' -- asynchronous reset level
);
port (
-- wishbone signals
wb_clk_i : in std_logic; -- master clock input
wb_rst_i : in std_logic := '0'; -- synchronous active high reset
arst_i : in std_logic := not ARST_LVL; -- asynchronous reset
wb_adr_i : in std_logic_vector(2 downto 0); -- lower address bits
wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input
wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output
wb_we_i : in std_logic; -- Write enable input
wb_stb_i : in std_logic; -- Strobe signals / core select signal
wb_cyc_i : in std_logic; -- Valid bus cycle input
wb_ack_o : out std_logic; -- Bus cycle acknowledge output
wb_inta_o : out std_logic; -- interrupt request output signal
-- i2c lines
scl_pad_i : in std_logic; -- i2c clock line input
scl_pad_o : out std_logic; -- i2c clock line output
scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
sda_pad_i : in std_logic; -- i2c data line input
sda_pad_o : out std_logic; -- i2c data line output
sda_padoen_o : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_top;
architecture structural of i2c_master_top is
component i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic;
ack_out : out std_logic;
i2c_busy : out std_logic;
i2c_al : out std_logic;
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_byte_ctrl;
-- registers
signal prer : unsigned(15 downto 0); -- clock prescale register
signal ctr : std_logic_vector(7 downto 0); -- control register
signal txr : std_logic_vector(7 downto 0); -- transmit register
signal rxr : std_logic_vector(7 downto 0); -- receive register
signal cr : std_logic_vector(7 downto 0); -- command register
signal sr : std_logic_vector(7 downto 0); -- status register
-- internal reset signal, active low
signal rst_n : std_logic;
-- wishbone write access
signal wb_wacc : std_logic;
-- internal acknowledge signal
signal iack_o : std_logic;
-- done signal: command completed, clear command register
signal done : std_logic;
-- command register signals
signal sta, sto, rd, wr, ack, iack : std_logic;
signal core_en : std_logic; -- core enable signal
signal ien : std_logic; -- interrupt enable signal
-- status register signals
signal irxack, rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
signal i2c_busy : std_logic; -- i2c bus busy (start signal detected)
signal i2c_al, al : std_logic; -- arbitration lost
begin
-- generate internal reset signal (active low)
rst_n <= arst_i xor ARST_LVL;
-- generate acknowledge output signal
gen_ack_o : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
end if;
end process gen_ack_o;
wb_ack_o <= iack_o;
-- generate wishbone write access signal
wb_wacc <= wb_we_i and iack_o;
-- assign wb_dat_o
assign_dato : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
case wb_adr_i is
when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8));
when "010" => wb_dat_o <= ctr;
when "011" => wb_dat_o <= rxr; -- write is transmit register TxR
when "100" => wb_dat_o <= sr; -- write is command register CR
-- Debugging registers:
-- These registers are not documented.
-- Functionality could change in future releases
when "101" => wb_dat_o <= txr;
when "110" => wb_dat_o <= cr;
when "111" => wb_dat_o <= (others => '0');
when others => wb_dat_o <= (others => 'X'); -- for simulation only
end case;
end if;
end process assign_dato;
-- generate registers (CR, SR see below)
gen_regs: process(rst_n, wb_clk_i)
begin
if (rst_n = '0') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_wacc = '1') then
case wb_adr_i is
when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
when "010" => ctr <= wb_dat_i;
when "011" => txr <= wb_dat_i;
when "100" => null; --write to CR, avoid executing the others clause
-- illegal cases, for simulation only
when others =>
report ("Illegal write address, setting all registers to unknown.");
prer <= (others => 'X');
ctr <= (others => 'X');
txr <= (others => 'X');
end case;
end if;
end if;
end process gen_regs;
-- generate command register
gen_cr: process(rst_n, wb_clk_i)
begin
if (rst_n = '0') then
cr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
cr <= (others => '0');
elsif (wb_wacc = '1') then
if ( (core_en = '1') and (wb_adr_i = "100") ) then
-- only take new commands when i2c core enabled
-- pending commands are finished
cr <= wb_dat_i;
end if;
else
if (done = '1' or i2c_al = '1') then
cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
end if;
cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0'
cr(0) <= '0'; -- clear IRQ_ACK bit
end if;
end if;
end process gen_cr;
-- decode command register
sta <= cr(7);
sto <= cr(6);
rd <= cr(5);
wr <= cr(4);
ack <= cr(3);
iack <= cr(0);
-- decode control register
core_en <= ctr(7);
ien <= ctr(6);
-- hookup byte controller block
byte_ctrl: i2c_master_byte_ctrl
port map (
clk => wb_clk_i,
rst => wb_rst_i,
nReset => rst_n,
ena => core_en,
clk_cnt => prer,
start => sta,
stop => sto,
read => rd,
write => wr,
ack_in => ack,
i2c_busy => i2c_busy,
i2c_al => i2c_al,
din => txr,
cmd_ack => done,
ack_out => irxack,
dout => rxr,
scl_i => scl_pad_i,
scl_o => scl_pad_o,
scl_oen => scl_padoen_o,
sda_i => sda_pad_i,
sda_o => sda_pad_o,
sda_oen => sda_padoen_o
);
-- status register block + interrupt request signal
st_irq_block : block
begin
-- generate status register bits
gen_sr_bits: process (wb_clk_i, rst_n)
begin
if (rst_n = '0') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
else
al <= i2c_al or (al and not sta);
rxack <= irxack;
tip <= (rd or wr);
-- interrupt request flag is always generated
irq_flag <= (done or i2c_al or irq_flag) and not iack;
end if;
end if;
end process gen_sr_bits;
-- generate interrupt request signals
gen_irq: process (wb_clk_i, rst_n)
begin
if (rst_n = '0') then
wb_inta_o <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
wb_inta_o <= '0';
else
-- interrupt signal is only generated when IEN (interrupt enable bit) is set
wb_inta_o <= irq_flag and ien;
end if;
end if;
end process gen_irq;
-- assign status register bits
sr(7) <= rxack;
sr(6) <= i2c_busy;
sr(5) <= al;
sr(4 downto 2) <= (others => '0'); -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end block;
end architecture structural;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity single_board_computer is
end entity single_board_computer;
-- end not in book
architecture structural of single_board_computer is
-- . . . -- type and signal declarations
-- not in book
subtype word is bit_vector(31 downto 0);
signal sys_clk : bit;
signal cpu_a_d, latched_addr : word;
-- end not in book
component processor is
port ( clk : in bit; a_d : inout word; -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end component processor;
component memory is
port ( addr : in bit_vector(25 downto 0); -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end component memory;
component serial_interface is
port ( clk : in bit; address : in bit_vector(3 downto 0); -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end component serial_interface;
begin
cpu : component processor
port map ( clk => sys_clk, a_d => cpu_a_d, -- . . . );
-- not in book
other_port => open );
-- end not in book
main_memory : component memory
port map ( addr => latched_addr(25 downto 0), -- . . . );
-- not in book
other_port => open );
-- end not in book
serial_interface_a : component serial_interface
port map ( clk => sys_clk, address => latched_addr(3 downto 0), -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture structural;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity single_board_computer is
end entity single_board_computer;
-- end not in book
architecture structural of single_board_computer is
-- . . . -- type and signal declarations
-- not in book
subtype word is bit_vector(31 downto 0);
signal sys_clk : bit;
signal cpu_a_d, latched_addr : word;
-- end not in book
component processor is
port ( clk : in bit; a_d : inout word; -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end component processor;
component memory is
port ( addr : in bit_vector(25 downto 0); -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end component memory;
component serial_interface is
port ( clk : in bit; address : in bit_vector(3 downto 0); -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end component serial_interface;
begin
cpu : component processor
port map ( clk => sys_clk, a_d => cpu_a_d, -- . . . );
-- not in book
other_port => open );
-- end not in book
main_memory : component memory
port map ( addr => latched_addr(25 downto 0), -- . . . );
-- not in book
other_port => open );
-- end not in book
serial_interface_a : component serial_interface
port map ( clk => sys_clk, address => latched_addr(3 downto 0), -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture structural;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity single_board_computer is
end entity single_board_computer;
-- end not in book
architecture structural of single_board_computer is
-- . . . -- type and signal declarations
-- not in book
subtype word is bit_vector(31 downto 0);
signal sys_clk : bit;
signal cpu_a_d, latched_addr : word;
-- end not in book
component processor is
port ( clk : in bit; a_d : inout word; -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end component processor;
component memory is
port ( addr : in bit_vector(25 downto 0); -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end component memory;
component serial_interface is
port ( clk : in bit; address : in bit_vector(3 downto 0); -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end component serial_interface;
begin
cpu : component processor
port map ( clk => sys_clk, a_d => cpu_a_d, -- . . . );
-- not in book
other_port => open );
-- end not in book
main_memory : component memory
port map ( addr => latched_addr(25 downto 0), -- . . . );
-- not in book
other_port => open );
-- end not in book
serial_interface_a : component serial_interface
port map ( clk => sys_clk, address => latched_addr(3 downto 0), -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture structural;
|
component wasca is
port (
abus_avalon_sdram_bridge_0_abus_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
abus_avalon_sdram_bridge_0_abus_read : in std_logic := 'X'; -- read
abus_avalon_sdram_bridge_0_abus_data : inout std_logic_vector(15 downto 0) := (others => 'X'); -- data
abus_avalon_sdram_bridge_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
abus_avalon_sdram_bridge_0_abus_direction : out std_logic; -- direction
abus_avalon_sdram_bridge_0_abus_interrupt_disable_out : out std_logic; -- interrupt_disable_out
abus_avalon_sdram_bridge_0_abus_interrupt : out std_logic; -- interrupt
abus_avalon_sdram_bridge_0_abus_writebyteenable_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- writebyteenable_n
abus_avalon_sdram_bridge_0_abus_reset : in std_logic := 'X'; -- reset
abus_avalon_sdram_bridge_0_sdram_addr : out std_logic_vector(12 downto 0); -- addr
abus_avalon_sdram_bridge_0_sdram_ba : out std_logic_vector(1 downto 0); -- ba
abus_avalon_sdram_bridge_0_sdram_cas_n : out std_logic; -- cas_n
abus_avalon_sdram_bridge_0_sdram_cke : out std_logic; -- cke
abus_avalon_sdram_bridge_0_sdram_cs_n : out std_logic; -- cs_n
abus_avalon_sdram_bridge_0_sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
abus_avalon_sdram_bridge_0_sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
abus_avalon_sdram_bridge_0_sdram_ras_n : out std_logic; -- ras_n
abus_avalon_sdram_bridge_0_sdram_we_n : out std_logic; -- we_n
abus_avalon_sdram_bridge_0_sdram_clk : out std_logic; -- clk
buffered_spi_mosi : out std_logic; -- mosi
buffered_spi_clk : out std_logic; -- clk
buffered_spi_miso : in std_logic := 'X'; -- miso
buffered_spi_cs : out std_logic; -- cs
buffered_spi_sync : in std_logic := 'X'; -- sync
clk_clk : in std_logic := 'X'; -- clk
clock_116_mhz_clk : out std_logic; -- clk
heartbeat_heartbeat_out : out std_logic; -- heartbeat_out
reset_reset_n : in std_logic := 'X'; -- reset_n
reset_controller_0_reset_in1_reset : in std_logic := 'X'; -- reset
uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_0_external_connection_txd : out std_logic -- txd
);
end component wasca;
u0 : component wasca
port map (
abus_avalon_sdram_bridge_0_abus_address => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_address, -- abus_avalon_sdram_bridge_0_abus.address
abus_avalon_sdram_bridge_0_abus_read => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_read, -- .read
abus_avalon_sdram_bridge_0_abus_data => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_data, -- .data
abus_avalon_sdram_bridge_0_abus_chipselect => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_chipselect, -- .chipselect
abus_avalon_sdram_bridge_0_abus_direction => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_direction, -- .direction
abus_avalon_sdram_bridge_0_abus_interrupt_disable_out => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_interrupt_disable_out, -- .interrupt_disable_out
abus_avalon_sdram_bridge_0_abus_interrupt => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_interrupt, -- .interrupt
abus_avalon_sdram_bridge_0_abus_writebyteenable_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_writebyteenable_n, -- .writebyteenable_n
abus_avalon_sdram_bridge_0_abus_reset => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_reset, -- .reset
abus_avalon_sdram_bridge_0_sdram_addr => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_addr, -- abus_avalon_sdram_bridge_0_sdram.addr
abus_avalon_sdram_bridge_0_sdram_ba => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_ba, -- .ba
abus_avalon_sdram_bridge_0_sdram_cas_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cas_n, -- .cas_n
abus_avalon_sdram_bridge_0_sdram_cke => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cke, -- .cke
abus_avalon_sdram_bridge_0_sdram_cs_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cs_n, -- .cs_n
abus_avalon_sdram_bridge_0_sdram_dq => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_dq, -- .dq
abus_avalon_sdram_bridge_0_sdram_dqm => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_dqm, -- .dqm
abus_avalon_sdram_bridge_0_sdram_ras_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_ras_n, -- .ras_n
abus_avalon_sdram_bridge_0_sdram_we_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_we_n, -- .we_n
abus_avalon_sdram_bridge_0_sdram_clk => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_clk, -- .clk
buffered_spi_mosi => CONNECTED_TO_buffered_spi_mosi, -- buffered_spi.mosi
buffered_spi_clk => CONNECTED_TO_buffered_spi_clk, -- .clk
buffered_spi_miso => CONNECTED_TO_buffered_spi_miso, -- .miso
buffered_spi_cs => CONNECTED_TO_buffered_spi_cs, -- .cs
buffered_spi_sync => CONNECTED_TO_buffered_spi_sync, -- .sync
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clock_116_mhz_clk => CONNECTED_TO_clock_116_mhz_clk, -- clock_116_mhz.clk
heartbeat_heartbeat_out => CONNECTED_TO_heartbeat_heartbeat_out, -- heartbeat.heartbeat_out
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
reset_controller_0_reset_in1_reset => CONNECTED_TO_reset_controller_0_reset_in1_reset, -- reset_controller_0_reset_in1.reset
uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd
uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd -- .txd
);
|
-- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
entity opa_dpram is
generic(
g_width : natural;
g_size : natural;
g_equal : t_dpram_equal;
g_regin : boolean;
g_regout : boolean);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
r_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
r_data_o : out std_logic_vector(g_width-1 downto 0);
w_en_i : in std_logic;
w_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
w_data_i : in std_logic_vector(g_width-1 downto 0));
end opa_dpram;
architecture rtl of opa_dpram is
type t_memory is array(g_size-1 downto 0) of std_logic_vector(g_width-1 downto 0);
signal r_memory : t_memory := (others => (others => '0'));
signal s_bypass : std_logic;
signal r_bypass : std_logic;
signal sr_bypass : std_logic;
signal s_data_memory : std_logic_vector(g_width-1 downto 0);
signal r_data_memory : std_logic_vector(g_width-1 downto 0);
signal sr_data_memory : std_logic_vector(g_width-1 downto 0);
signal s_data_bypass : std_logic_vector(g_width-1 downto 0);
signal r_data_bypass : std_logic_vector(g_width-1 downto 0);
signal sr_data_bypass : std_logic_vector(g_width-1 downto 0);
signal sr_data : std_logic_vector(g_width-1 downto 0);
signal srr_data : std_logic_vector(g_width-1 downto 0);
begin
nohw :
assert (g_equal /= OPA_OLD or g_regin)
report "opa_dpram cannot be used in OPA_OLD mode without a registered input"
severity failure;
s_data_bypass <= w_data_i;
s_data_memory <= r_memory(to_integer(unsigned(r_addr_i))) when f_opa_safe(r_addr_i)='1' else (others => 'X');
s_bypass <= f_opa_eq(r_addr_i, w_addr_i) and w_en_i;
main : process(clk_i) is
begin
if rising_edge(clk_i) then
if w_en_i = '1' then
assert (f_opa_safe(w_addr_i) = '1') report "Attempt to write to a meta-valued address" severity failure;
r_memory(to_integer(unsigned(w_addr_i))) <= w_data_i;
end if;
r_data_bypass <= s_data_bypass;
r_data_memory <= s_data_memory;
r_bypass <= s_bypass;
srr_data <= sr_data;
end if;
end process;
sr_data_bypass <= r_data_bypass when g_regin else s_data_bypass;
sr_data_memory <= r_data_memory when g_regin else s_data_memory;
sr_bypass <= r_bypass when g_regin else s_bypass;
sr_data <=
sr_data_memory when sr_bypass = '0' or g_equal = OPA_OLD else
sr_data_bypass when g_equal = OPA_NEW else
(others => 'X');
r_data_o <= srr_data when g_regout else sr_data;
end rtl;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:hls:agito:1.0
-- IP Revision: 1603301709
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY kuuga_test_harness_agito_0_0 IS
PORT (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_return : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
output_loc : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END kuuga_test_harness_agito_0_0;
ARCHITECTURE kuuga_test_harness_agito_0_0_arch OF kuuga_test_harness_agito_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF kuuga_test_harness_agito_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT agito IS
PORT (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_return : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
output_loc : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT agito;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF kuuga_test_harness_agito_0_0_arch: ARCHITECTURE IS "agito,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF kuuga_test_harness_agito_0_0_arch : ARCHITECTURE IS "kuuga_test_harness_agito_0_0,agito,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF kuuga_test_harness_agito_0_0_arch: ARCHITECTURE IS "kuuga_test_harness_agito_0_0,agito,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=hls,x_ipName=agito,x_ipVersion=1.0,x_ipCoreRevision=1603301709,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF ap_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF ap_start: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 ap_ctrl start";
ATTRIBUTE X_INTERFACE_INFO OF ap_done: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 ap_ctrl done";
ATTRIBUTE X_INTERFACE_INFO OF ap_idle: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 ap_ctrl idle";
ATTRIBUTE X_INTERFACE_INFO OF ap_ready: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 ap_ctrl ready";
ATTRIBUTE X_INTERFACE_INFO OF ap_return: SIGNAL IS "xilinx.com:signal:data:1.0 ap_return DATA";
ATTRIBUTE X_INTERFACE_INFO OF output_loc: SIGNAL IS "xilinx.com:signal:data:1.0 output_loc DATA";
BEGIN
U0 : agito
PORT MAP (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => ap_start,
ap_done => ap_done,
ap_idle => ap_idle,
ap_ready => ap_ready,
ap_return => ap_return,
output_loc => output_loc
);
END kuuga_test_harness_agito_0_0_arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.ml50x.all;
use work.pcie.all;
-- pragma translate_off
library unisim;
use unisim.ODDR;
use unisim.IBUFDS;
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
transtech : integer := CFG_TRANSTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
sys_rst_in : in std_ulogic;
clk_100 : in std_ulogic; -- 100 MHz main clock
clk_200_p : in std_ulogic; -- 200 MHz
clk_200_n : in std_ulogic; -- 200 MHz
clk_33 : in std_ulogic; -- 33 MHz
sram_flash_addr : out std_logic_vector(23 downto 0);
sram_flash_data : inout std_logic_vector(31 downto 0);
sram_cen : out std_logic;
sram_bw : out std_logic_vector (0 to 3);
sram_oen : out std_ulogic;
sram_flash_we_n : out std_ulogic;
flash_ce : out std_logic;
flash_oen : out std_logic;
flash_adv_n : out std_logic;
sram_clk : out std_ulogic;
sram_clk_fb : in std_ulogic;
sram_mode : out std_ulogic;
sram_adv_ld_n : out std_ulogic;
--pragma translate_off
iosn : out std_ulogic;
--pragma translate_on
ddr_clk : out std_logic_vector(1 downto 0);
ddr_clkb : out std_logic_vector(1 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_odt : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqsp : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+CFG_DDR2SP downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
gpio : inout std_logic_vector(12 downto 0); -- I/O port
led : out std_logic_vector(12 downto 0);
bus_error : out std_logic_vector(1 downto 0);
phy_gtx_clk : out std_logic;
phy_mii_data : inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
phy_int : in std_ulogic;
sgmii_rx_n : in std_ulogic;
sgmii_rx_p : in std_ulogic;
sgmii_tx_n : out std_ulogic;
sgmii_tx_p : out std_ulogic;
sgmiiclk_qo_n : in std_ulogic;
sgmiiclk_qo_p : in std_ulogic;
ps2_keyb_clk : inout std_logic;
ps2_keyb_data : inout std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
usb_csn : out std_logic;
usb_rstn : out std_logic;
iic_scl_main : inout std_ulogic;
iic_sda_main : inout std_ulogic;
iic_scl_video : inout std_logic;
iic_sda_video : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_d : inout std_logic_vector(15 downto 0);
pci_exp_txp : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_txn : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxp : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxn : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic
);
end;
architecture rtl of leon3mp is
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component svga2ch7301c
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end component;
component IBUFDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART
+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_PCIEXP;
signal ddr_clk_fb : std_logic;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, srclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal sgmii_refclk, sgmii_rst : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal mdio_reset, mdio_o, mdio_oe, mdio_i, mdc, mdint : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal vgalock : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
constant BOARD_FREQ_200 : integer := 200000; -- input frequency in KHz
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
constant IOAEN : integer := CFG_DDR2SP + CFG_GRACECTRL;
signal stati : ahbstat_in_type;
signal ssrclkfb : std_ulogic;
-- Used for connecting input/output signals to the DDR3 controller
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
signal phy_init_done : std_ulogic;
signal clk0_tb, rst0_tb, rst0_tbn : std_ulogic;
signal sysmoni : grsysmon_in_type;
signal sysmono : grsysmon_out_type;
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
attribute syn_keep of clk25 : signal is true;
attribute syn_preserve of clk25 : signal is true;
attribute syn_keep of clk40 : signal is true;
attribute syn_preserve of clk40 : signal is true;
attribute syn_keep of clk65 : signal is true;
attribute syn_preserve of clk65 : signal is true;
attribute syn_keep of clk_200 : signal is true;
attribute syn_preserve of clk_200 : signal is true;
attribute syn_preserve of phy_init_done : signal is true;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute keep of clkvga : signal is true;
attribute keep of clk25 : signal is true;
attribute keep of clk40 : signal is true;
attribute keep of clk65 : signal is true;
attribute keep of clk_200 : signal is true;
attribute keep of phy_init_done : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of clk_33_pad : label is true;
begin
usb_csn <= '1';
usb_rstn <= rstn;
rst0_tbn <= not rst0_tb;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
ssrref_pad : clkpad generic map (tech => padtech)
port map (sram_clk_fb, ssrclkfb);
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (clk_100, lclk);
clk200_pad : clkpad_ds generic map (tech => padtech, level => lvds, voltage => x25v)
port map (clk_200_p, clk_200_n, clk_200);
srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, srclkl);
clk_33_pad : clkpad generic map (tech => padtech)
port map (clk_33, clkace);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo);
gclk : if CFG_GRETH1G /= 0 generate
clkgen1 : clkgen -- Ethernet 1G PHY clock generator
generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
x0 : ODDR port map ( Q => phy_gtx_clk, C => egtx_clk, CE => vcc(0),
D1 => gnd(0), D2 => vcc(0), R => gnd(0), S => gnd(0));
-- D1 => vcc(0), D2 => gnd(0), R => gnd(0), S => gnd(0));
end generate;
nogclk : if CFG_GRETH1G = 0 generate
cgo2.clklock <= '1'; phy_gtx_clk <= '0';
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock and cgo.clklock and cgo2.clklock and vgalock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => CFG_BOARD_SELECTION,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
bus_error(0) <= not dbgo(0).error;
bus_error(1) <= rstn;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.break <= gpioo.val(11); -- South Button
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
led(4) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
dui.rxd <= rxd1 when gpioo.val(0) = '1' else '1';
end generate;
txd1 <= duo.txd when gpioo.val(0) = '1' else u1o.txd;
txd2 <= '0'; -- Second UART is unused
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 16#400# + (CFG_DDR2SP+CFG_MIG_DDR2)*16#800#, rammask => 16#FE0#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
end generate;
flash_adv_n_pad : outpad generic map (tech => padtech)
port map (flash_adv_n, gnd(0));
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
port map (sram_adv_ld_n, gnd(0));
sram_mode_pad : outpad generic map (tech => padtech)
port map (sram_mode, gnd(0));
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (sram_flash_addr, memo.address(24 downto 1));
rams_pad : outpad generic map ( tech => padtech)
port map (sram_cen, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (flash_ce, memo.romsn(0));
ramoen_pad : outpad generic map (tech => padtech)
port map (sram_oen, memo.ramoen(0));
flash_oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
--pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
rwen_pad : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(0 to 1), memo.wrn(3 downto 2));
rwen_pad2 : outpadv generic map (width => 2, tech => padtech)
port map (sram_bw(2 to 3), memo.wrn(1 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (sram_flash_we_n, memo.writen);
data_pads : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
data_pads2 : iopadvv generic map (tech => padtech, width => 16)
port map (sram_flash_data(31 downto 16), memo.data(15 downto 0),
memo.vbdrive(15 downto 0), memi.data(15 downto 0));
migsp0 : if (CFG_MIG_DDR2 = 1) generate
ahb2mig0 : entity work.ahb2mig_ml50x
generic map ( hindex => 0, haddr => 16#400#, hmask => MIGHMASK,
MHz => 400, Mbyte => 512, nosync => 0) --boolean'pos(CFG_MIG_CLK4=12)) --CFG_CLKDIV/12)
port map (
rst_ahb => rstn, rst_ddr => rst0_tbn, clk_ahb => clkm, clk_ddr => clk0_tb,
ahbsi => ahbsi, ahbso => ahbso(0), migi => migi, migo => migo);
migv5 : mig_36_1
generic map (
CKE_WIDTH => CKE_WIDTH, CS_NUM => CS_NUM, CS_WIDTH => CS_WIDTH, CS_BITS => CS_BITS,
COL_WIDTH => COL_WIDTH, ROW_WIDTH => ROW_WIDTH,
NOCLK200 => true, SIM_ONLY => 1)
port map(
ddr2_dq => ddr_dq(DQ_WIDTH-1 downto 0),
ddr2_a => ddr_ad(ROW_WIDTH-1 downto 0),
ddr2_ba => ddr_ba(1 downto 0), ddr2_ras_n => ddr_rasb,
ddr2_cas_n => ddr_casb, ddr2_we_n => ddr_web,
ddr2_cs_n => ddr_csb(CS_NUM-1 downto 0), ddr2_odt => ddr_odt(0 downto 0),
ddr2_cke => ddr_cke(CKE_WIDTH-1 downto 0),
ddr2_dm => ddr_dm(DM_WIDTH-1 downto 0),
sys_clk => clk_200, idly_clk_200 => clk_200, sys_rst_n => rstraw,
phy_init_done => phy_init_done,
rst0_tb => rst0_tb, clk0_tb => clk0_tb,
app_wdf_afull => migo.app_wdf_afull,
app_af_afull => migo.app_af_afull,
rd_data_valid => migo.app_rd_data_valid,
app_wdf_wren => migi.app_wdf_wren,
app_af_wren => migi.app_en, app_af_addr => migi.app_addr,
app_af_cmd => migi.app_cmd,
rd_data_fifo_out => migo.app_rd_data, app_wdf_data => migi.app_wdf_data,
app_wdf_mask_data => migi.app_wdf_mask,
ddr2_dqs => ddr_dqsp(DQS_WIDTH-1 downto 0),
ddr2_dqs_n => ddr_dqsn(DQS_WIDTH-1 downto 0),
ddr2_ck => ddr_clk((CLK_WIDTH-1) downto 0),
ddr2_ck_n => ddr_clkb((CLK_WIDTH-1) downto 0)
);
lock <= phy_init_done;
led(5) <= phy_init_done;
ddr_ad(13) <= '0';
ddr_odt(1) <= '0';
ddr_csb(1) <= '0';
end generate;
ddrsp0 : if (CFG_DDR2SP /= 0) and (CFG_MIG_DDR2 = 0) generate
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ_200/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10, clkdiv => 20, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => 64,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
numidelctrl => 1, norefclk => 0, odten => 3, nclk => 2,
eightbanks => 1)
port map ( rst, rstn, clk_200, clkm, clk_200, lock, clkml, clkml, ahbsi, ahbso(0),
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt);
led(5) <= '0';
end generate;
noddr : if (CFG_DDR2SP = 0) and (CFG_MIG_DDR2 = 0) generate lock <= '1'; led(5) <= '0'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 4, hirq => 3,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(4), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sysace_mpa_pads : outpadv generic map (width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_d_pads : iopadv generic map (tech => padtech, width => 16)
port map (sysace_d, aceo.do, aceo.doen, acei.di);
sysace_mpoe_pad : outpad generic map (tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
u1i.rxd <= rxd1 when gpioo.val(0) = '0' else '1';
end generate;
led(0) <= gpioo.val(0); led(1) <= not rxd1;
led(2) <= not duo.txd when gpioo.val(0) = '1' else not u1o.txd;
led (12 downto 6) <= (others => '0');
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
led(3) <= gpto.wdog;
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(
memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 40000, clk2 => 25000, clk3 => 15385, burstlen => 6,
ahbaccsz => CFG_AHBDW)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : svga2ch7301c generic map (tech => fabtech, idf => 2)
port map (lclk, rstraw, clk_sel, vgao, clkvga, clk25, clk40, clk65,
clkvga, clk25, clk40, clk65, clkvga_p, clkvga_n,
vgalock, lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 6, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none; vgalock <= '1';
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl_video, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda_video, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 13)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
gpio_pads : iopadvv generic map (tech => padtech, width => 13)
port map (gpio, gpioo.dout(12 downto 0), gpioo.oen(12 downto 0),
gpioi.din(12 downto 0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl_main, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda_main, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
gmii_eth: if CFG_GRETH_SGMII_MODE = 0 generate
e1 : grethm
generic map(
hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1
)
port map(
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho
);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
emdintn_pad : inpad generic map (tech => padtech)
port map (phy_int, ethi.mdint);
ethi.gtx_clk <= egtx_clk;
end generate;
sgmii_eth: if CFG_GRETH_SGMII_MODE /= 0 generate
sgmii_rst <= not rst;
refclk_bufds : IBUFDS
port map (
I => sgmiiclk_qo_p,
IB => sgmiiclk_qo_n,
O => sgmii_refclk
);
e1 : greths
generic map(
hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 7,
fabtech => fabtech,
memtech => memtech,
transtech => transtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1
)
port map(
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi,
apbo => apbo(11),
-- High-speed Serial Interface
clk_125 => sgmii_refclk,
rst_125 => sgmii_rst,
eth_rx_p => sgmii_rx_p,
eth_rx_n => sgmii_rx_n,
eth_tx_p => sgmii_tx_p,
eth_tx_n => sgmii_tx_n,
-- MDIO interface
reset => mdio_reset,
mdio_o => mdio_o,
mdio_oe => mdio_oe,
mdio_i => mdio_i,
mdc => mdc,
mdint => mdint,
-- Control signals
phyrstaddr => "00000",
edcladdr => "0000",
edclsepahb => '0',
edcldisable => '0'
);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, mdio_o, mdio_oe, mdio_i);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, mdio_reset);
emdintn_pad : inpad generic map (tech => padtech)
port map (phy_int, mdint);
end generate;
end generate;
-----------------PCI-EXPRESS-Master-Target------------------------------------------
pcie_mt : if CFG_PCIE_TYPE = 1 generate -- master/target without fifo
EP: pcie_master_target_virtex
generic map (
fabtech => fabtech,
hmstndx => NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
hslvndx => 6,
abits => 21,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
pcie_bar_mask => 16#FFE#,
nsync => 2, -- 1 or 2 sync regs between clocks
haddr => 16#a00#,
hmask => 16#fff#,
pindex => 10,
paddr => 10,
pmask => 16#fff#,
Master => CFG_PCIE_SIM_MAS,
lane_width => CFG_NO_OF_LANES
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(6),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(10),
ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE)
);
end generate;
pcie_mf : if CFG_PCIE_TYPE = 3 generate -- master with fifo and DMA
dma:pciedma
generic map (fabtech => fabtech, memtech => memtech, dmstndx =>(NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
dapbndx => 13, dapbaddr => 13,dapbirq => 13, blength => 12, abits => 21,
device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID, pcie_bar_mask => 16#FFE#,
slvndx => 6, apbndx => 10, apbaddr => 10, haddr => 16#A00#,hmask=> 16#FFF#,
nsync => 2,lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
dapbo => apbo(13),
dahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi,
apbo => apbo(10),
ahbmi => ahbmi,
ahbsi => ahbsi,
ahbso => ahbso(6)
);
end generate;
----------------------------------------------------------------------
pcie_mf_no_dma: if CFG_PCIE_TYPE = 2 generate -- master with fifo
EP:pcie_master_fifo_virtex
generic map (fabtech => fabtech, memtech => memtech,
hslvndx => 6, abits => 21, device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID,
pcie_bar_mask => 16#FFE#, pindex => 10, paddr => 10,
haddr => 16#A00#, hmask => 16#FFF#, nsync => 2, lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(6),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(10)
);
end generate;
-----------------------------------------------------------------------
--- SYSTEM MONITOR ---------------------------------------------------
-----------------------------------------------------------------------
grsmon: if CFG_GRSYSMON = 1 generate
sysm0 : grsysmon generic map (tech => fabtech, hindex => 5,
hirq => 10, caddr => 16#003#, cmask => 16#fff#,
saddr => 16#004#, smask => 16#ffe#, split => CFG_SPLIT,
extconvst => 0, wrdalign => 1, INIT_40 => X"0000",
INIT_41 => X"0000", INIT_42 => X"0800", INIT_43 => X"0000",
INIT_44 => X"0000", INIT_45 => X"0000", INIT_46 => X"0000",
INIT_47 => X"0000", INIT_48 => X"0000", INIT_49 => X"0000",
INIT_4A => X"0000", INIT_4B => X"0000", INIT_4C => X"0000",
INIT_4D => X"0000", INIT_4E => X"0000", INIT_4F => X"0000",
INIT_50 => X"0000", INIT_51 => X"0000", INIT_52 => X"0000",
INIT_53 => X"0000", INIT_54 => X"0000", INIT_55 => X"0000",
INIT_56 => X"0000", INIT_57 => X"0000",
SIM_MONITOR_FILE => "sysmon.txt")
port map (rstn, clkm, ahbsi, ahbso(5), sysmoni, sysmono);
sysmoni <= grsysmon_in_gnd;
end generate grsmon;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG+CFG_PCIEXP) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(CFG_BOARD_SELECTION),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_mul_8ns_25ns_32_3_MAC3S_1 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(8 - 1 downto 0);
b: in std_logic_vector(25 - 1 downto 0);
p: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of image_filter_mul_8ns_25ns_32_3_MAC3S_1 is
signal tmp_product : std_logic_vector(32 - 1 downto 0);
signal a_i : std_logic_vector(8 - 1 downto 0);
signal b_i : std_logic_vector(25 - 1 downto 0);
signal p_tmp : std_logic_vector(32 - 1 downto 0);
signal a_reg0 : std_logic_vector(8 - 1 downto 0);
signal b_reg0 : std_logic_vector(25 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(32 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(a_reg0) * unsigned(b_reg0), 32));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity image_filter_mul_8ns_25ns_32_3 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of image_filter_mul_8ns_25ns_32_3 is
component image_filter_mul_8ns_25ns_32_3_MAC3S_1 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
image_filter_mul_8ns_25ns_32_3_MAC3S_1_U : component image_filter_mul_8ns_25ns_32_3_MAC3S_1
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_mul_8ns_25ns_32_3_MAC3S_1 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(8 - 1 downto 0);
b: in std_logic_vector(25 - 1 downto 0);
p: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of image_filter_mul_8ns_25ns_32_3_MAC3S_1 is
signal tmp_product : std_logic_vector(32 - 1 downto 0);
signal a_i : std_logic_vector(8 - 1 downto 0);
signal b_i : std_logic_vector(25 - 1 downto 0);
signal p_tmp : std_logic_vector(32 - 1 downto 0);
signal a_reg0 : std_logic_vector(8 - 1 downto 0);
signal b_reg0 : std_logic_vector(25 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(32 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(a_reg0) * unsigned(b_reg0), 32));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity image_filter_mul_8ns_25ns_32_3 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of image_filter_mul_8ns_25ns_32_3 is
component image_filter_mul_8ns_25ns_32_3_MAC3S_1 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
image_filter_mul_8ns_25ns_32_3_MAC3S_1_U : component image_filter_mul_8ns_25ns_32_3_MAC3S_1
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: outpad_ddr, outpad_ddrv
-- File: outpad_ddr.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Wrapper that instantiates a DDR register connected to an
-- output pad. The generic tech wrappers are not used for nextreme
-- since this technology requires that the output enable signal is
-- connected between the DDR register and the pad.
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allddr.all;
use techmap.allpads.all;
entity outpad_ddr is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12
);
port (
pad : out std_ulogic;
i1, i2 : in std_ulogic;
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic
);
end;
architecture rtl of outpad_ddr is
signal q, oe, vcc : std_ulogic;
begin
vcc <= '1';
def: if (tech /= easic90) and (tech /= easic45) generate
ddrreg : ddr_oreg generic map (tech)
port map (q, c1, c2, ce, i1, i2, r, s);
p : outpad generic map (tech, level, slew, voltage, strength)
port map (pad, q);
oe <= '0';
end generate def;
nex : if (tech = easic90) generate
ddrreg : nextreme_oddr_reg
port map (ck => c1, dh => i1, dl => i2, doe => vcc, q => q, oe => oe, rstb => r);
p : nextreme_toutpad generic map (level, slew, voltage, strength)
port map(pad, q, oe);
end generate;
n2x : if (tech = easic45) generate
-- ddrpad : n2x_outpad_ddr generic map (level, slew, voltage, strength)
-- port map ();
--pragma translate_off
assert false report "outpad_ddr: Not yet supported on Nextreme2"
severity failure;
--pragma translate_on
q <= '0'; oe <= '0';
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity outpad_ddrv is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := 0;
strength : integer := 12;
width : integer := 1
);
port (
pad : out std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic
);
end;
architecture rtl of outpad_ddrv is
begin
v : for j in width-1 downto 0 generate
x0 : outpad_ddr generic map (tech, level, slew, voltage, strength)
port map (pad(j), i1(j), i2(j), c1, c2, ce, r, s);
end generate;
end;
|
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 17, 2017
--! @brief Contains the package and component declaration of the
--! Plasma-SoC's UART Core. Please refer to the documentation
--! in plasoc_uart.vhd for more information.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package plasoc_uart_pack is
constant default_uart_fifo_depth : integer := 8;
constant default_uart_axi_control_offset : integer := 0;
constant default_uart_axi_control_status_in_avail_bit_loc : integer := 0;
constant default_uart_axi_control_status_out_avail_bit_loc : integer := 1;
constant default_uart_axi_in_fifo_offset : integer := 4;
constant default_uart_axi_out_fifo_offset : integer := 8;
constant default_uart_baud : positive := 9600;
constant default_uart_clock_frequency : positive := 50000000;
constant axi_resp_okay : std_logic_vector := "00";
component plasoc_uart is
generic (
fifo_depth : integer := default_uart_fifo_depth;
axi_address_width : integer := 16;
axi_data_width : integer := 32;
axi_control_offset : integer := default_uart_axi_control_offset;
axi_control_status_in_avail_bit_loc : integer := default_uart_axi_control_status_in_avail_bit_loc;
axi_control_status_out_avail_bit_loc : integer := default_uart_axi_control_status_out_avail_bit_loc;
axi_in_fifo_offset : integer := default_uart_axi_in_fifo_offset;
axi_out_fifo_offset : integer := default_uart_axi_out_fifo_offset;
baud : positive := default_uart_baud;
clock_frequency : positive := default_uart_clock_frequency);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_awprot : in std_logic_vector(2 downto 0);
axi_awvalid : in std_logic;
axi_awready : out std_logic;
axi_wvalid : in std_logic;
axi_wready : out std_logic;
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
axi_bvalid : out std_logic;
axi_bready : in std_logic;
axi_bresp : out std_logic_vector(1 downto 0);
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_arprot : in std_logic_vector(2 downto 0);
axi_arvalid : in std_logic;
axi_arready : out std_logic;
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
axi_rvalid : out std_logic;
axi_rready : in std_logic;
axi_rresp : out std_logic_vector(1 downto 0);
tx : out std_logic;
rx : in std_logic;
status_in_avail : out std_logic);
end component;
function clogb2(bit_depth : in integer ) return integer;
end package;
package body plasoc_uart_pack is
function flogb2(bit_depth : in natural ) return integer is
variable result : integer := 0;
variable bit_depth_buff : integer := bit_depth;
begin
while bit_depth_buff>1 loop
bit_depth_buff := bit_depth_buff/2;
result := result+1;
end loop;
return result;
end function flogb2;
function clogb2 (bit_depth : in natural ) return natural is
variable result : integer := 0;
begin
result := flogb2(bit_depth);
if (bit_depth > (2**result)) then
return(result + 1);
else
return result;
end if;
end function clogb2;
end; |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_a
--
-- Generated
-- by: wig
-- on: Fri Jun 9 05:15:53 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../highlow.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-rtl-a.vhd,v 1.3 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: ent_a-rtl-a.vhd,v $
-- Revision 1.3 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_a
--
architecture rtl of ent_a is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_aa
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
high_bus_3_0 : in std_ulogic_vector(3 downto 0); -- Ground wire_low port
low_bit_aa : in std_ulogic;
mix_logic0_bus_2 : in std_ulogic_vector(3 downto 0); -- Ground port
mix_logic1_0 : in std_ulogic; -- Wire bit to high
part_zero : out std_ulogic_vector(3 downto 0) -- Wire two bits to port
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
component ent_ab
-- No Generated Generics
port (
-- Generated Port for Entity ent_ab
low_bus_6_0 : in std_ulogic_vector(6 downto 0); -- Wide low port
port_part_zero_u : in std_ulogic_vector(3 downto 0) -- Wire two bits to portWire two bits to low
-- End of Generated Port for Entity ent_ab
);
end component;
-- ---------
component ent_ac
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ent_ad
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ent_ae
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic1_0 : std_ulogic;
signal mix_logic1_bus_1 : std_ulogic_vector(3 downto 0);
signal mix_logic0_1 : std_ulogic;
signal mix_logic0_bus_2 : std_ulogic_vector(3 downto 0);
signal mix_logic0_bus_3 : std_ulogic_vector(6 downto 0);
signal mix_logic0_bus_4 : std_ulogic_vector(1 downto 0);
signal part_zero : std_ulogic_vector(3 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic1_0 <= '1';
mix_logic1_bus_1 <= ( others => '1' );
mix_logic0_1 <= '0';
mix_logic0_bus_2 <= ( others => '0' );
mix_logic0_bus_3 <= ( others => '0' );
mix_logic0_bus_4 <= ( others => '0' );
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa
port map (
high_bus_3_0 => mix_logic1_bus_1, -- Ground wire_low port
low_bit_aa => mix_logic0_1,
mix_logic0_bus_2 => mix_logic0_bus_2, -- Ground port
mix_logic1_0 => mix_logic1_0, -- Wire bit to high
part_zero => part_zero -- Wire two bits to port
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab
port map (
low_bus_6_0 => mix_logic0_bus_3, -- Wide low port
port_part_zero_u(1 downto 0) => part_zero(3 downto 2), -- Wire two bits to port
port_part_zero_u(3 downto 2) => mix_logic0_bus_4 -- __W_PORT -- Wire two bits to low
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: ent_ac
;
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: ent_ad
;
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: ent_ae
;
-- End of Generated Instance Port Map for inst_ae
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_bb_e
--
-- Generated
-- by: wig
-- on: Wed Apr 5 12:50:28 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_bb_e-e.vhd,v 1.1 2006/04/10 15:42:11 wig Exp $
-- $Date: 2006/04/10 15:42:11 $
-- $Log: inst_bb_e-e.vhd,v $
-- Revision 1.1 2006/04/10 15:42:11 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_bb_e
--
entity inst_bb_e is
HOOK: global hook in entity
-- Generics:
-- No Generated Generics for Entity inst_bb_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_bb_e
port_bb_o : out std_ulogic_vector(7 downto 0) -- vector test bb to ab
-- End of Generated Port for Entity inst_bb_e
);
end inst_bb_e;
--
-- End of Generated Entity inst_bb_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
architecture RTL of FIFO is
procedure proc1 is
begin
end procedure proc1;
signal wr_en : std_logic;
-- Violations follow
procedure proc1 is
begin
end procedure proc1;
signal wr_en : std_logic;
begin
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use work.init_funcs.all;
use std.textio.all;
entity test_vga_system is
end test_vga_system;
architecture behavioural of test_vga_system is
component VGA_system is
generic (
display_rows : natural := 480;
display_cols : natural := 640
);
port (
clock : in std_logic; -- 100 MHz Clock
hsync : out std_logic;
vsync : out std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(2 downto 1)
);
end component VGA_system;
signal clock : std_logic;
signal hsync : std_logic;
signal vsync : std_logic;
signal red : std_logic_vector(2 downto 0);
signal green : std_logic_vector(2 downto 0);
signal blue : std_logic_vector(2 downto 1);
begin
SYSTEM: VGA_system port map (
clock,
hsync,
vsync,
red,
green,
blue
);
process
variable vsync_holder : std_logic;
variable hsync_holder : std_logic;
variable log_line, data_line : line;
file file_pointer: text is out "vga_log.txt";
begin
for i in 1 to 2000000 loop
vsync_holder := vsync;
clock <= '0';
wait for 5 ns;
clock <= '1'; -- Delay2 -> Read
wait for 5 ns;
clock <= '0';
wait for 5 ns;
clock <= '1'; -- Read -> Update
wait for 5 ns;
clock <= '0';
wait for 5 ns;
clock <= '1'; -- Update -> Delay1
wait for 5 ns;
write(data_line, now); -- write the line.
write(data_line, ':'); -- write the line.
-- Write the hsync
write(data_line, ' ');
write(data_line, chr(hsync)); -- write the line.
-- Write the vsync
write(data_line, ' ');
write(data_line, chr(vsync)); -- write the line.
-- Write the red
write(data_line, ' ');
write(data_line, str(red)); -- write the line.
-- Write the green
write(data_line, ' ');
write(data_line, str(green)); -- write the line.
-- Write the blue
write(data_line, ' ');
write(data_line, str(blue)); -- write the line.
writeline(file_pointer, data_line); -- write the contents into the file.
clock <= '0';
wait for 5 ns;
clock <= '1'; -- Delay1 -> Delay2
wait for 5 ns;
end loop;
wait;
end process;
end behavioural;
|
library ieee;
use ieee.std_logic_1164.all;
use work.init_funcs.all;
use std.textio.all;
entity test_vga_system is
end test_vga_system;
architecture behavioural of test_vga_system is
component VGA_system is
generic (
display_rows : natural := 480;
display_cols : natural := 640
);
port (
clock : in std_logic; -- 100 MHz Clock
hsync : out std_logic;
vsync : out std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(2 downto 1)
);
end component VGA_system;
signal clock : std_logic;
signal hsync : std_logic;
signal vsync : std_logic;
signal red : std_logic_vector(2 downto 0);
signal green : std_logic_vector(2 downto 0);
signal blue : std_logic_vector(2 downto 1);
begin
SYSTEM: VGA_system port map (
clock,
hsync,
vsync,
red,
green,
blue
);
process
variable vsync_holder : std_logic;
variable hsync_holder : std_logic;
variable log_line, data_line : line;
file file_pointer: text is out "vga_log.txt";
begin
for i in 1 to 2000000 loop
vsync_holder := vsync;
clock <= '0';
wait for 5 ns;
clock <= '1'; -- Delay2 -> Read
wait for 5 ns;
clock <= '0';
wait for 5 ns;
clock <= '1'; -- Read -> Update
wait for 5 ns;
clock <= '0';
wait for 5 ns;
clock <= '1'; -- Update -> Delay1
wait for 5 ns;
write(data_line, now); -- write the line.
write(data_line, ':'); -- write the line.
-- Write the hsync
write(data_line, ' ');
write(data_line, chr(hsync)); -- write the line.
-- Write the vsync
write(data_line, ' ');
write(data_line, chr(vsync)); -- write the line.
-- Write the red
write(data_line, ' ');
write(data_line, str(red)); -- write the line.
-- Write the green
write(data_line, ' ');
write(data_line, str(green)); -- write the line.
-- Write the blue
write(data_line, ' ');
write(data_line, str(blue)); -- write the line.
writeline(file_pointer, data_line); -- write the contents into the file.
clock <= '0';
wait for 5 ns;
clock <= '1'; -- Delay1 -> Delay2
wait for 5 ns;
end loop;
wait;
end process;
end behavioural;
|
--------------------------------------------------------------------------------
-- Entity: dm_simple
-- Date: 2014-12-08
-- Author: Gideon
--
-- Description: Simple direct mapped cache controller, compatible with the
-- I/D buses of the mblite
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.core_Pkg.all;
-- type dmem_in_type is record
-- dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
-- ena_i : std_logic;
-- end record;
--
-- type dmem_out_type is record
-- dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
-- adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
-- sel_o : std_logic_vector(3 downto 0);
-- we_o : std_logic;
-- ena_o : std_logic;
-- end record;
-- type imem_in_type is record
-- dat_i : std_logic_vector(CFG_dmem_WIDTH - 1 downto 0);
-- ena_i : std_logic;
-- end record;
--
-- type imem_out_type is record
-- adr_o : std_logic_vector(CFG_dmem_SIZE - 1 downto 0);
-- ena_o : std_logic;
-- end record;
entity dm_simple is
generic (
g_address_swap : std_logic_vector(31 downto 0) := X"00000000";
g_registered_out: boolean := false;
g_data_register : boolean := true;
g_mem_direct : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
dmem_i : in dmem_out_type;
dmem_o : out dmem_in_type;
mem_o : out dmem_out_type;
mem_i : in dmem_in_type );
end entity;
architecture arch of dm_simple is
constant c_cachable_area_bits : natural := 25;
constant c_cache_size_bits : natural := 11; -- 2**11 bytes = 2KB
-- constant c_tag_compare_width : natural := c_cachable_area_bits - c_cache_size_bits;
constant c_tag_size_bits : natural := c_cache_size_bits - 2; -- 4 bytes per cache entry
type t_tag is record
addr_high : std_logic_vector(c_cachable_area_bits-1 downto c_cache_size_bits);
valid : std_logic;
end record;
constant c_valid_zero_tag : t_tag := ( addr_high => (others => '0'), valid => '1' );
function extend32(a : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0) := (others => '0');
begin
ret(a'length-1 downto 0) := a;
return ret;
end function;
function address_to_tag (addr : std_logic_vector;
valid : std_logic) return t_tag is
variable v_addr : std_logic_vector(31 downto 0);
variable ret : t_tag;
begin
v_addr := extend32(addr);
ret.addr_high := v_addr(c_cachable_area_bits-1 downto c_cache_size_bits);
ret.valid := valid;
return ret;
end function;
constant c_tag_width : natural := c_cachable_area_bits - c_cache_size_bits + 1;
function tag_to_vector(i: t_tag) return std_logic_vector is
begin
return i.valid & i.addr_high;
end function;
constant c_valid_zero_tag_vector : std_logic_vector(c_tag_width-1 downto 0) := tag_to_vector(c_valid_zero_tag);
function vector_to_tag(i : std_logic_vector(c_tag_width-1 downto 0)) return t_tag is
variable ret : t_tag;
begin
ret.valid := i(c_tag_width-1);
ret.addr_high := i(c_tag_width-2 downto 0);
return ret;
end function;
function get_tag_index (addr : std_logic_vector) return unsigned is
begin
return unsigned(addr(c_tag_size_bits+1 downto 2));
end function;
function is_cacheable (addr : std_logic_vector) return boolean is
variable v_addr : std_logic_vector(31 downto 0);
begin
v_addr := extend32(addr);
return unsigned(v_addr(31 downto c_cachable_area_bits)) = 0;
end function;
-- type t_tag_ram is record
--
-- end record;
signal tag_ram_a_address : unsigned(c_tag_size_bits-1 downto 0);
signal tag_ram_a_rdata : std_logic_vector(c_tag_width-1 downto 0);
signal tag_ram_a_wdata : std_logic_vector(c_tag_width-1 downto 0);
signal tag_ram_a_en : std_logic;
signal tag_ram_a_we : std_logic;
signal tag_ram_b_address : unsigned(c_tag_size_bits-1 downto 0) := (others => '0');
signal tag_ram_b_rdata : std_logic_vector(c_tag_width-1 downto 0) := (others => '0');
signal tag_ram_b_wdata : std_logic_vector(c_tag_width-1 downto 0) := (others => '0');
signal tag_ram_b_en : std_logic := '0';
signal tag_ram_b_we : std_logic := '0';
signal cache_ram_a_address : unsigned(c_cache_size_bits-1 downto 2);
signal cache_ram_a_rdata : std_logic_vector(31 downto 0);
signal cache_ram_a_wdata : std_logic_vector(31 downto 0);
signal cache_ram_a_en : std_logic;
signal cache_ram_a_we : std_logic;
signal cache_ram_b_address : unsigned(c_cache_size_bits-1 downto 2) := (others => '0');
signal cache_ram_b_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal cache_ram_b_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal cache_ram_b_en : std_logic := '0';
signal cache_ram_b_we : std_logic := '0';
signal d_tag_ram_out : t_tag;
signal d_miss : std_logic;
signal data_reg : std_logic_vector(31 downto 0);
signal dmem_r : dmem_out_type;
signal dmem_o_comb : dmem_in_type;
signal dmem_o_reg : dmem_in_type;
type t_state is (idle, fill, reg);
signal state : t_state;
begin
i_tag_ram: entity work.dpram_sc
generic map (
g_width_bits => c_tag_width,
g_depth_bits => c_tag_size_bits,
g_global_init => c_valid_zero_tag_vector,
g_read_first_a => true,
g_read_first_b => true,
g_storage => "block" )
port map (
clock => clock,
a_address => tag_ram_a_address,
a_rdata => tag_ram_a_rdata,
a_wdata => tag_ram_a_wdata,
a_en => tag_ram_a_en,
a_we => tag_ram_a_we,
b_address => tag_ram_b_address,
b_rdata => tag_ram_b_rdata,
b_wdata => tag_ram_b_wdata,
b_en => tag_ram_b_en,
b_we => tag_ram_b_we );
i_cache_ram: entity work.dpram_sc
generic map (
g_width_bits => 32,
g_depth_bits => c_cache_size_bits-2,
g_global_init => X"FFFFFFFF",
g_read_first_a => true,
g_read_first_b => true,
g_storage => "block" )
port map (
clock => clock,
a_address => cache_ram_a_address,
a_rdata => cache_ram_a_rdata,
a_wdata => cache_ram_a_wdata,
a_en => cache_ram_a_en,
a_we => cache_ram_a_we,
b_address => cache_ram_b_address,
b_rdata => cache_ram_b_rdata,
b_wdata => cache_ram_b_wdata,
b_en => cache_ram_b_en,
b_we => cache_ram_b_we );
d_tag_ram_out <= vector_to_tag(tag_ram_a_rdata);
-- handle the dmem address request here; split it up
process(state, dmem_i, dmem_r, mem_i, d_tag_ram_out, cache_ram_a_rdata, data_reg)
begin
if g_registered_out then
dmem_o_comb.ena_i <= '0'; -- registered out, use this signal as register load enable
else
dmem_o_comb.ena_i <= '1'; -- direct out, use this signal as enable output
end if;
dmem_o_comb.dat_i <= (others => 'X');
d_miss <= '0';
tag_ram_a_address <= get_tag_index(dmem_i.adr_o);
tag_ram_a_wdata <= (others => 'X');
tag_ram_a_we <= '0';
tag_ram_a_en <= '0';
cache_ram_a_address <= unsigned(dmem_i.adr_o(c_cache_size_bits-1 downto 2));
cache_ram_a_wdata <= dmem_i.dat_o;
cache_ram_a_we <= '0';
cache_ram_a_en <= '0';
tag_ram_b_address <= get_tag_index(dmem_r.adr_o);
tag_ram_b_wdata <= tag_to_vector(address_to_tag(dmem_r.adr_o, '1'));
tag_ram_b_we <= '0';
tag_ram_b_en <= '0';
cache_ram_b_address <= unsigned(dmem_r.adr_o(c_cache_size_bits-1 downto 2));
cache_ram_b_wdata <= mem_i.dat_i;
cache_ram_b_we <= '0';
cache_ram_b_en <= '0';
if dmem_i.ena_o = '1' then -- processor address is valid, let's do our thing
if dmem_i.we_o = '0' then -- read
tag_ram_a_en <= '1';
cache_ram_a_en <= '1';
else -- write
tag_ram_a_en <= '1';
cache_ram_a_en <= '1';
tag_ram_a_we <= '1';
cache_ram_a_we <= '1';
if dmem_i.sel_o = "1111" then -- full word results in a valid cache line
tag_ram_a_wdata <= tag_to_vector(address_to_tag(dmem_i.adr_o, '1')); -- valid
else
tag_ram_a_wdata <= tag_to_vector(address_to_tag(dmem_i.adr_o, '0')); -- invalid
end if;
end if;
end if;
-- response to processor
case state is
when idle =>
if dmem_r.ena_o = '1' then -- registered (=delayed request valid)
if (address_to_tag(dmem_r.adr_o, '1') = d_tag_ram_out) and (dmem_r.we_o='0') and is_cacheable(dmem_r.adr_o) then -- read hit!
dmem_o_comb.dat_i <= cache_ram_a_rdata;
dmem_o_comb.ena_i <= '1';
else -- miss or write
dmem_o_comb.ena_i <= '0';
d_miss <= '1';
end if;
end if; -- else use default values, hence X
when fill =>
dmem_o_comb.ena_i <= '0';
if mem_i.ena_i = '1' then
if g_mem_direct then
dmem_o_comb.dat_i <= mem_i.dat_i; -- ouch, 32-bit multiplexer!
dmem_o_comb.ena_i <= '1';
end if;
if dmem_r.we_o='0' then -- was a read
tag_ram_b_en <= '1';
cache_ram_b_en <= '1';
tag_ram_b_we <= '1';
cache_ram_b_we <= '1';
end if;
end if;
when reg =>
dmem_o_comb.dat_i <= data_reg; -- ouch, 3rd input to 32-bit multiplexer!
dmem_o_comb.ena_i <= '1';
end case;
end process;
-- type dmem_out_type is record
-- dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
-- adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
-- sel_o : std_logic_vector(3 downto 0);
-- we_o : std_logic;
-- ena_o : std_logic;
-- end record;
r_comb: if not g_registered_out generate
dmem_o <= dmem_o_comb;
end generate;
r_reg: if g_registered_out generate
dmem_o <= dmem_o_reg;
end generate;
process(state, dmem_r, d_miss)
begin
mem_o <= dmem_r;
mem_o.adr_o <= dmem_r.adr_o xor g_address_swap(dmem_r.adr_o'range);
mem_o.ena_o <= d_miss;
end process;
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
if d_miss = '1' then
state <= fill;
end if;
when fill =>
if mem_i.ena_i = '1' then
data_reg <= mem_i.dat_i; -- ouch, 32-bit register
dmem_r.ena_o <= '0';
if g_registered_out then
state <= idle;
elsif dmem_i.ena_o = '0' then
if g_data_register then
state <= reg;
else
report "No data register support, but it seems to be needed!"
severity error;
end if;
else
state <= idle;
end if;
end if;
when reg =>
if dmem_i.ena_o = '1' then
if d_miss = '1' then
state <= fill;
else
state <= idle;
end if;
end if;
end case;
if dmem_i.ena_o = '1' then
dmem_o_reg.ena_i <= '0';
elsif dmem_o_comb.ena_i = '1' then
dmem_o_reg.dat_i <= dmem_o_comb.dat_i;
dmem_o_reg.ena_i <= '1';
end if;
if dmem_i.ena_o = '1' then
dmem_r <= dmem_i;
end if;
if reset='1' then
state <= idle;
dmem_o_reg.ena_i <= '1';
end if;
end if;
end process;
end arch;
|
entity loop2 is
end entity;
architecture test of loop2 is
procedure p3(t : in time) is
begin
loop
if t >= 1 ps then
return;
end if;
end loop;
end procedure;
begin
end architecture;
|
entity loop2 is
end entity;
architecture test of loop2 is
procedure p3(t : in time) is
begin
loop
if t >= 1 ps then
return;
end if;
end loop;
end procedure;
begin
end architecture;
|
entity loop2 is
end entity;
architecture test of loop2 is
procedure p3(t : in time) is
begin
loop
if t >= 1 ps then
return;
end if;
end loop;
end procedure;
begin
end architecture;
|
entity loop2 is
end entity;
architecture test of loop2 is
procedure p3(t : in time) is
begin
loop
if t >= 1 ps then
return;
end if;
end loop;
end procedure;
begin
end architecture;
|
entity loop2 is
end entity;
architecture test of loop2 is
procedure p3(t : in time) is
begin
loop
if t >= 1 ps then
return;
end if;
end loop;
end procedure;
begin
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity processor is
port ( address : out std_logic_vector (15 downto 0);
Pstrobe : out std_logic;
Prw : out std_logic;
Pready : in std_logic;
Pdata : inout std_logic_vector (32 downto 0));
end processor; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book
package cpu_types is
constant word_size : positive := 16;
constant address_size : positive := 24;
subtype word is bit_vector(word_size - 1 downto 0);
subtype address is bit_vector(address_size - 1 downto 0);
type status_value is ( halted, idle, fetch, mem_read, mem_write,
io_read, io_write, int_ack );
end package cpu_types;
-- end code from book
package cpu_types_test is
constant status :
-- code from book
work.cpu_types.status_value
-- end code from book
:=
-- code from book
work.cpu_types.status_value'(work.cpu_types.fetch)
-- end code from book
;
end package cpu_types_test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book
package cpu_types is
constant word_size : positive := 16;
constant address_size : positive := 24;
subtype word is bit_vector(word_size - 1 downto 0);
subtype address is bit_vector(address_size - 1 downto 0);
type status_value is ( halted, idle, fetch, mem_read, mem_write,
io_read, io_write, int_ack );
end package cpu_types;
-- end code from book
package cpu_types_test is
constant status :
-- code from book
work.cpu_types.status_value
-- end code from book
:=
-- code from book
work.cpu_types.status_value'(work.cpu_types.fetch)
-- end code from book
;
end package cpu_types_test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book
package cpu_types is
constant word_size : positive := 16;
constant address_size : positive := 24;
subtype word is bit_vector(word_size - 1 downto 0);
subtype address is bit_vector(address_size - 1 downto 0);
type status_value is ( halted, idle, fetch, mem_read, mem_write,
io_read, io_write, int_ack );
end package cpu_types;
-- end code from book
package cpu_types_test is
constant status :
-- code from book
work.cpu_types.status_value
-- end code from book
:=
-- code from book
work.cpu_types.status_value'(work.cpu_types.fetch)
-- end code from book
;
end package cpu_types_test;
|
--===========================================================================--
-- --
-- Synthesizable Character Generator using Xilinx RAMB16_S9 Block RAM --
-- --
--===========================================================================--
--
-- File name : char_rom2k_b16.vhd
--
-- Entity name : char_rom
--
-- Purpose : Implements a character generator ROM
-- using one Xilinx RAMB16_S9 Block RAM
-- Used by vdu8.vhd in the System09 SoC
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_arith
--
-- Uses : RAMB16_S9 (Xilinx 16KBit Block RAM)
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- Description : Characters are 7 pixels x 11 rows x 128 characters
-- Stored as 8 bits x 16 locations x 128 characters
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Date Author Changes
--
-- 0.1 2004-10-18 John Kent Initial relaease
--
-- 0.2 2010-06-17 John Kent Updated header and description and added GPL
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.vcomponents.all;
entity char_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector (10 downto 0);
rw : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end char_rom;
architecture rtl of char_rom is
signal we : std_logic;
signal dp : std_logic;
begin
ROM : RAMB16_S9
generic map (
INIT_00 => x"0000000009090F09090038043840380000000000070404040400444C54644400",
INIT_01 => x"00000000110A040A110078407040780000000000110A040A1100380438403800",
INIT_02 => x"000000000D1215110E0078407040780000000000040404041F00784070407800",
INIT_03 => x"000000000F080808080070487048700000000000090A0C0A0900487848483000",
INIT_04 => x"00000000040404041F0044447C444400000000000E010E100E00704870487000",
INIT_05 => x"00000000040404041F001028444444000000000010101E101F007C4040404000",
INIT_06 => x"0000000011111E111E003C4040403C000000000008080E080F00404070407800",
INIT_07 => x"00000000070202020700380438403800000000000E1111110E00380438403800",
INIT_08 => x"00000000070202060200704848487000000000000F080E080F00704848487000",
INIT_09 => x"000000000E0107020F00704848487000000000000F0806090700704848487000",
INIT_0a => x"00000000090A0C0A0900444C546444000000000001010F090900704848487000",
INIT_0b => x"000000000E090E090E0078407040780000000000111315191100380438403800",
INIT_0c => x"000000001111151B110078407040780000000000111315191100384040403800",
INIT_0d => x"000000000E1010100E00784070407800000000000E090E090E00380438403800",
INIT_0e => x"000000000E010E100E00384858403800000000000E010E100E00404070407800",
INIT_0f => x"000000000E010E100E00304848484800000000000E010E100E00485070487000",
INIT_10 => x"0000000008080000080808080808080000000000000000000000000000000000",
INIT_11 => x"000000002424247E2424247E2424240000000000000000000000001212121200",
INIT_12 => x"0000000043434020100804020161610000000000083E4909093E4848493E0800",
INIT_13 => x"00000000000000000000002010080C00000000003D4244444438444444443800",
INIT_14 => x"0000000020100804040404040810200000000000020408101010101008040200",
INIT_15 => x"0000000000000808087F0808080000000000000000004122147F142241000000",
INIT_16 => x"0000000000000000007F00000000000000402010181800000000000000000000",
INIT_17 => x"0000000040404020100804020101010000000000181800000000000000000000",
INIT_18 => x"000000003E080808080808082818080000000000081422414141414122140800",
INIT_19 => x"000000003E410101010E010101413E00000000007F4020100804020141423C00",
INIT_1a => x"000000003E410101615E404040407F000000000002020202027F22120A060200",
INIT_1b => x"00000000404020100804020101017F00000000001E214141615E404040211E00",
INIT_1c => x"000000003C420101013D434141423C00000000003E414141413E414141413E00",
INIT_1d => x"0000402010181818000000181818000000000000001818180000001818180000",
INIT_1e => x"00000000000000007F00007F0000000000000000010204081020100804020100",
INIT_1f => x"00000000080800080808060101413E0000000000402010080402040810204000",
INIT_20 => x"0000000041414141417F414122140800000000001C224140404E494541221C00",
INIT_21 => x"000000001E2141404040404041211E00000000007E212121213E212121217E00",
INIT_22 => x"000000007F404040407C404040407F00000000007C2221212121212121227C00",
INIT_23 => x"000000001E2141414147404040211E000000000040404040407C404040407F00",
INIT_24 => x"000000003E0808080808080808083E000000000041414141417F414141414100",
INIT_25 => x"00000000414244485060504844424100000000003C4202020202020202020700",
INIT_26 => x"00000000414141414141494955634100000000007F4040404040404040404000",
INIT_27 => x"000000003E4141414141414141413E0000000000414141434549495161414100",
INIT_28 => x"000000003D4245494141414141413E000000000040404040407E414141417E00",
INIT_29 => x"000000003E410101013E404040413E000000000041424448507E414141417E00",
INIT_2a => x"000000003E414141414141414141410000000000080808080808080808087F00",
INIT_2b => x"0000000022225555494941414141410000000000080814141422222241414100",
INIT_2c => x"0000000008080808080814224141410000000000414141221408142241414100",
INIT_2d => x"000000001E1010101010101010101E00000000007F4040201008040201017F00",
INIT_2e => x"000000003C0404040404040404043C0000000000010101020408102040404000",
INIT_2f => x"000000007F000000000000000000000000000000000000000000004122140800",
INIT_30 => x"000000003F41413F01013E000000000000000000000000000000000204081800",
INIT_31 => x"000000001E21404040211E0000000000000000005E61616141615E4040404000",
INIT_32 => x"000000003E40407F41413E0000000000000000003D43414141433D0101010100",
INIT_33 => x"003C4202023E424242423D0100000000000000001010101010107C1010110E00",
INIT_34 => x"000000003E0808080808180000080800000000004141414141615E4040404000",
INIT_35 => x"00000000414448704844414040404000003C4202020202020202020000020200",
INIT_36 => x"00000000414141494955220000000000000000001C0808080808080808081800",
INIT_37 => x"000000003E41414141413E0000000000000000004141414141615E0000000000",
INIT_38 => x"00010101013D434343433D000000000000404040405E616161615E0000000000",
INIT_39 => x"000000003E01013E40403E0000000000000000002020202020314E0000000000",
INIT_3a => x"000000003D4242424242420000000000000000000C12101010107C1010101000",
INIT_3b => x"0000000022554949414141000000000000000000081414222241410000000000",
INIT_3c => x"003C4202023A4642424242000000000000000000412214081422410000000000",
INIT_3d => x"00000000070808081020100808080700000000007F20100804027F0000000000",
INIT_3e => x"0000000070080808040204080808700000000000080808080800080808080800",
INIT_3f => x"0000000049224922492249224922490000000000000000000000000046493100"
)
port map (
do => data_out,
dop(0)=> dp,
addr => addr,
clk => clk,
di => data_in,
dip(0)=> dp,
en => cs,
ssr => rst,
we => we
);
my_char_rom : process ( rw )
begin
we <= not rw;
end process;
end architecture rtl;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
ELSIF c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
ELSIF x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: DPU_matrix_multiplication_timesim.vhd
-- /___/ /\ Timestamp: Mon Feb 22 00:04:32 2016
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -s 4 -pcf DPU_matrix_multiplication.pcf -rpw 100 -tpw 0 -ar Structure -tm DPU_matrix_multiplication -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim DPU_matrix_multiplication.ncd DPU_matrix_multiplication_timesim.vhd
-- Device : 3s400tq144-4 (PRODUCTION 1.39 2013-10-13)
-- Input file : DPU_matrix_multiplication.ncd
-- Output file : E:\Works\GitHub\Systolic-Processor-On-FPGA\ISE Design Files\DPU_matrix_multiplication\netgen\par\DPU_matrix_multiplication_timesim.vhd
-- # of Entities : 1
-- Design Name : DPU_matrix_multiplication
-- Xilinx : D:\Xilinx\14.7\ISE_DS\ISE\
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity DPU_matrix_multiplication is
port (
CLK : in STD_LOGIC := 'X';
Result : out STD_LOGIC_VECTOR ( 9 downto 0 );
Bout : out STD_LOGIC_VECTOR ( 3 downto 0 );
Aout : out STD_LOGIC_VECTOR ( 3 downto 0 );
Ain : in STD_LOGIC_VECTOR ( 3 downto 0 );
Bin : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end DPU_matrix_multiplication;
architecture Structure of DPU_matrix_multiplication is
signal CLK_BUFGP : STD_LOGIC;
signal Ain_1_IBUF_376 : STD_LOGIC;
signal R2_DFF2_Q_377 : STD_LOGIC;
signal Ain_2_IBUF_378 : STD_LOGIC;
signal R2_DFF3_Q_379 : STD_LOGIC;
signal Ain_3_IBUF_380 : STD_LOGIC;
signal R2_DFF4_Q_381 : STD_LOGIC;
signal R2_DFF5_Q_382 : STD_LOGIC;
signal R2_DFF6_Q_383 : STD_LOGIC;
signal R2_DFF7_Q_384 : STD_LOGIC;
signal R2_DFF8_Q_385 : STD_LOGIC;
signal R2_DFF9_Q_386 : STD_LOGIC;
signal R1_DFF0_Q_1_387 : STD_LOGIC;
signal R1_DFF1_Q_1_389 : STD_LOGIC;
signal R1_DFF2_Q_1_391 : STD_LOGIC;
signal R1_DFF3_Q_1_393 : STD_LOGIC;
signal R0_DFF0_Q_1_395 : STD_LOGIC;
signal R1_DFF2_Q_399 : STD_LOGIC;
signal R0_DFF1_Q_400 : STD_LOGIC;
signal R0_DFF2_Q_403 : STD_LOGIC;
signal R1_DFF1_Q_404 : STD_LOGIC;
signal R1_DFF0_Q_405 : STD_LOGIC;
signal MAC_S2_1_0 : STD_LOGIC;
signal R2_DFF1_Q_408 : STD_LOGIC;
signal R2_DFF0_Q_409 : STD_LOGIC;
signal R0_DFF0_Q_411 : STD_LOGIC;
signal N7_0 : STD_LOGIC;
signal N6_0 : STD_LOGIC;
signal FA_FA6_Cout1_O : STD_LOGIC;
signal FA_D_5_0 : STD_LOGIC;
signal FA_FA6_Cout1_SW2_O : STD_LOGIC;
signal N15_0 : STD_LOGIC;
signal S3_7_0 : STD_LOGIC;
signal FA_D_1_0 : STD_LOGIC;
signal FA_FA6_Cout1_SW0_O : STD_LOGIC;
signal MAC_C3_2_0 : STD_LOGIC;
signal R1_DFF3_Q_423 : STD_LOGIC;
signal R0_DFF3_Q_424 : STD_LOGIC;
signal MAC_S3_2_0 : STD_LOGIC;
signal N2_0 : STD_LOGIC;
signal MAC_HAM23_A : STD_LOGIC;
signal MAC_FAM30_A_0 : STD_LOGIC;
signal MAC_C2_0_0 : STD_LOGIC;
signal MAC_S2_2_0 : STD_LOGIC;
signal MAC_C2_1_0 : STD_LOGIC;
signal S3_4_0 : STD_LOGIC;
signal FA_D_2_0 : STD_LOGIC;
signal N11_0 : STD_LOGIC;
signal FA_D_3_0 : STD_LOGIC;
signal N18_0 : STD_LOGIC;
signal S3_5_0 : STD_LOGIC;
signal MAC_S1_1_0 : STD_LOGIC;
signal MAC_FAM22_H2_Mxor_Sout_Result1_SW0_O : STD_LOGIC;
signal N4_0 : STD_LOGIC;
signal Aout_2_O : STD_LOGIC;
signal Aout_1_O : STD_LOGIC;
signal Result_2_O : STD_LOGIC;
signal MAC_S3_1_pack_1 : STD_LOGIC;
signal MAC_C3_1_pack_1 : STD_LOGIC;
signal MAC_FAM22_H2_Mxor_Sout_Result1_SW0_O_pack_1 : STD_LOGIC;
signal R2_DFF6_Q_DYMUX_1195 : STD_LOGIC;
signal R2_DFF6_Q_CLKINV_1186 : STD_LOGIC;
signal S3_3_pack_1 : STD_LOGIC;
signal MAC_FAM30_A : STD_LOGIC;
signal R2_DFF0_Q_DYMUX_1216 : STD_LOGIC;
signal R2_DFF0_Q_CLKINV_1207 : STD_LOGIC;
signal N15 : STD_LOGIC;
signal S3_6_pack_1 : STD_LOGIC;
signal R2_DFF2_Q_DYMUX_1243 : STD_LOGIC;
signal R2_DFF2_Q_CLKINV_1234 : STD_LOGIC;
signal R2_DFF4_Q_DYMUX_1279 : STD_LOGIC;
signal R2_DFF4_Q_CLKINV_1270 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal R2_DFF5_Q_DYMUX_1177 : STD_LOGIC;
signal R2_DFF5_Q_CLKINV_1168 : STD_LOGIC;
signal R0_DFF0_Q_DYMUX_1312 : STD_LOGIC;
signal R0_DFF0_Q_CLKINV_1310 : STD_LOGIC;
signal MAC_C1_0_pack_2 : STD_LOGIC;
signal R2_DFF3_Q_DYMUX_1261 : STD_LOGIC;
signal R2_DFF3_Q_CLKINV_1252 : STD_LOGIC;
signal FA_D_4_pack_1 : STD_LOGIC;
signal N7 : STD_LOGIC;
signal N6 : STD_LOGIC;
signal R0_DFF1_Q_DYMUX_1345 : STD_LOGIC;
signal R0_DFF1_Q_CLKINV_1343 : STD_LOGIC;
signal R0_DFF2_Q_DYMUX_1354 : STD_LOGIC;
signal R0_DFF2_Q_CLKINV_1352 : STD_LOGIC;
signal MAC_S1_2_pack_1 : STD_LOGIC;
signal MAC_C2_2_pack_1 : STD_LOGIC;
signal MAC_HAM23_A_pack_1 : STD_LOGIC;
signal S3_2_pack_1 : STD_LOGIC;
signal R0_DFF3_Q_DYMUX_1363 : STD_LOGIC;
signal R0_DFF3_Q_CLKINV_1361 : STD_LOGIC;
signal R1_DFF0_Q_DYMUX_1372 : STD_LOGIC;
signal R1_DFF0_Q_CLKINV_1370 : STD_LOGIC;
signal R1_DFF1_Q_DYMUX_1381 : STD_LOGIC;
signal R1_DFF1_Q_CLKINV_1379 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal R1_DFF3_Q_DYMUX_1411 : STD_LOGIC;
signal R1_DFF3_Q_CLKINV_1409 : STD_LOGIC;
signal Aout_0_O : STD_LOGIC;
signal Result_0_O : STD_LOGIC;
signal Result_1_O : STD_LOGIC;
signal R1_DFF2_Q_DYMUX_1402 : STD_LOGIC;
signal R1_DFF2_Q_CLKINV_1400 : STD_LOGIC;
signal N18 : STD_LOGIC;
signal Aout_3_O : STD_LOGIC;
signal Result_3_O : STD_LOGIC;
signal Result_7_O : STD_LOGIC;
signal Bin_0_IFF_IFFDMUX_570 : STD_LOGIC;
signal Bin_0_IFF_ICLK1INV_572 : STD_LOGIC;
signal Bin_0_INBUF : STD_LOGIC;
signal Bin_1_INBUF : STD_LOGIC;
signal Result_8_O : STD_LOGIC;
signal Result_6_O : STD_LOGIC;
signal Result_5_O : STD_LOGIC;
signal Result_9_O : STD_LOGIC;
signal Result_4_O : STD_LOGIC;
signal Bin_2_INBUF : STD_LOGIC;
signal Bin_3_INBUF : STD_LOGIC;
signal Bout_1_O : STD_LOGIC;
signal Bout_0_O : STD_LOGIC;
signal Ain_1_INBUF : STD_LOGIC;
signal Ain_0_INBUF : STD_LOGIC;
signal Bout_2_O : STD_LOGIC;
signal Bout_3_O : STD_LOGIC;
signal CLK_INBUF : STD_LOGIC;
signal R2_DFF1_Q_DXMUX_757 : STD_LOGIC;
signal S3_0_pack_2 : STD_LOGIC;
signal R2_DFF1_Q_CLKINV_740 : STD_LOGIC;
signal Ain_3_INBUF : STD_LOGIC;
signal Ain_2_INBUF : STD_LOGIC;
signal R2_DFF9_Q_DXMUX_787 : STD_LOGIC;
signal FA_FA6_Cout1_O_pack_2 : STD_LOGIC;
signal R2_DFF9_Q_CLKINV_771 : STD_LOGIC;
signal S3_1_pack_1 : STD_LOGIC;
signal MAC_C1_1_pack_2 : STD_LOGIC;
signal R2_DFF7_Q_DXMUX_871 : STD_LOGIC;
signal FA_FA6_Cout1_SW0_O_pack_2 : STD_LOGIC;
signal R2_DFF7_Q_CLKINV_854 : STD_LOGIC;
signal R2_DFF8_Q_DXMUX_817 : STD_LOGIC;
signal FA_FA6_Cout1_SW2_O_pack_2 : STD_LOGIC;
signal R2_DFF8_Q_CLKINV_802 : STD_LOGIC;
signal CLK_BUFGP_BUFG_S_INVNOT : STD_LOGIC;
signal CLK_BUFGP_BUFG_I0_INV : STD_LOGIC;
signal MAC_C4_1_pack_1 : STD_LOGIC;
signal Aout_2_OUTPUT_OFF_O1INV_484 : STD_LOGIC;
signal R0_DFF2_Q_1_487 : STD_LOGIC;
signal Aout_2_OUTPUT_OTCLK1INV_481 : STD_LOGIC;
signal Aout_3_OUTPUT_OFF_O1INV_508 : STD_LOGIC;
signal R0_DFF3_Q_1_511 : STD_LOGIC;
signal Aout_3_OUTPUT_OTCLK1INV_505 : STD_LOGIC;
signal Aout_1_OUTPUT_OFF_O1INV_460 : STD_LOGIC;
signal R0_DFF1_Q_1_463 : STD_LOGIC;
signal Aout_1_OUTPUT_OTCLK1INV_457 : STD_LOGIC;
signal Ain_0_IFF_ICLK1INV_672 : STD_LOGIC;
signal Ain_0_IFF_IFFDMUX_670 : STD_LOGIC;
signal Bin_1_IFF_ICLK1INV_589 : STD_LOGIC;
signal Bin_1_IFF_IFFDMUX_587 : STD_LOGIC;
signal Bin_2_IFF_ICLK1INV_606 : STD_LOGIC;
signal Bin_2_IFF_IFFDMUX_604 : STD_LOGIC;
signal Bin_3_IFF_ICLK1INV_623 : STD_LOGIC;
signal Bin_3_IFF_IFFDMUX_621 : STD_LOGIC;
signal VCC : STD_LOGIC;
signal GND : STD_LOGIC;
signal MAC_C1 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal MAC_S1 : STD_LOGIC_VECTOR ( 2 downto 1 );
signal S3 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal MAC_C4 : STD_LOGIC_VECTOR ( 1 downto 1 );
signal MAC_C3 : STD_LOGIC_VECTOR ( 2 downto 1 );
signal MAC_S3 : STD_LOGIC_VECTOR ( 2 downto 1 );
signal MAC_C2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal FA_D : STD_LOGIC_VECTOR ( 5 downto 1 );
signal MAC_S2 : STD_LOGIC_VECTOR ( 2 downto 1 );
signal S6 : STD_LOGIC_VECTOR ( 9 downto 0 );
begin
Aout_2_OBUF : X_OBUF
generic map(
LOC => "PAD181"
)
port map (
I => Aout_2_O,
O => Aout(2)
);
Aout_1_OBUF : X_OBUF
generic map(
LOC => "PAD236"
)
port map (
I => Aout_1_O,
O => Aout(1)
);
Result_2_OBUF : X_OBUF
generic map(
LOC => "PAD222"
)
port map (
I => Result_2_O,
O => Result(2)
);
S3_4_XUSED : X_BUF
generic map(
LOC => "SLICE_X5Y6",
PATHPULSE => 605 ps
)
port map (
I => S3(4),
O => S3_4_0
);
S3_4_YUSED : X_BUF
generic map(
LOC => "SLICE_X5Y6",
PATHPULSE => 605 ps
)
port map (
I => MAC_S3_1_pack_1,
O => MAC_S3(1)
);
S3_5_XUSED : X_BUF
generic map(
LOC => "SLICE_X7Y6",
PATHPULSE => 605 ps
)
port map (
I => S3(5),
O => S3_5_0
);
S3_5_YUSED : X_BUF
generic map(
LOC => "SLICE_X7Y6",
PATHPULSE => 605 ps
)
port map (
I => MAC_C3_1_pack_1,
O => MAC_C3(1)
);
MAC_S2_2_XUSED : X_BUF
generic map(
LOC => "SLICE_X6Y5",
PATHPULSE => 605 ps
)
port map (
I => MAC_S2(2),
O => MAC_S2_2_0
);
MAC_S2_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X6Y5",
PATHPULSE => 605 ps
)
port map (
I => MAC_FAM22_H2_Mxor_Sout_Result1_SW0_O_pack_1,
O => MAC_FAM22_H2_Mxor_Sout_Result1_SW0_O
);
R2_DFF6_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X2Y8",
PATHPULSE => 605 ps
)
port map (
I => S6(6),
O => R2_DFF6_Q_DYMUX_1195
);
R2_DFF6_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y8",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF6_Q_CLKINV_1186
);
FA_D_3_XUSED : X_BUF
generic map(
LOC => "SLICE_X3Y6",
PATHPULSE => 605 ps
)
port map (
I => FA_D(3),
O => FA_D_3_0
);
FA_D_3_YUSED : X_BUF
generic map(
LOC => "SLICE_X3Y6",
PATHPULSE => 605 ps
)
port map (
I => S3_3_pack_1,
O => S3(3)
);
R2_DFF0_Q_XUSED : X_BUF
generic map(
LOC => "SLICE_X4Y8",
PATHPULSE => 605 ps
)
port map (
I => MAC_FAM30_A,
O => MAC_FAM30_A_0
);
R2_DFF0_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X4Y8",
PATHPULSE => 605 ps
)
port map (
I => S6(0),
O => R2_DFF0_Q_DYMUX_1216
);
R2_DFF0_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X4Y8",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF0_Q_CLKINV_1207
);
N15_XUSED : X_BUF
generic map(
LOC => "SLICE_X5Y7",
PATHPULSE => 605 ps
)
port map (
I => N15,
O => N15_0
);
N15_YUSED : X_BUF
generic map(
LOC => "SLICE_X5Y7",
PATHPULSE => 605 ps
)
port map (
I => S3_6_pack_1,
O => S3(6)
);
R2_DFF2_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X5Y8",
PATHPULSE => 605 ps
)
port map (
I => S6(2),
O => R2_DFF2_Q_DYMUX_1243
);
R2_DFF2_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X5Y8",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF2_Q_CLKINV_1234
);
R2_DFF4_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X3Y7",
PATHPULSE => 605 ps
)
port map (
I => S6(4),
O => R2_DFF4_Q_DYMUX_1279
);
R2_DFF4_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X3Y7",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF4_Q_CLKINV_1270
);
N4_XUSED : X_BUF
generic map(
LOC => "SLICE_X6Y6",
PATHPULSE => 605 ps
)
port map (
I => N4,
O => N4_0
);
N4_YUSED : X_BUF
generic map(
LOC => "SLICE_X6Y6",
PATHPULSE => 605 ps
)
port map (
I => N11,
O => N11_0
);
R2_DFF5_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X0Y6",
PATHPULSE => 605 ps
)
port map (
I => S6(5),
O => R2_DFF5_Q_DYMUX_1177
);
R2_DFF5_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X0Y6",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF5_Q_CLKINV_1168
);
R0_DFF0_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X1Y5",
PATHPULSE => 605 ps
)
port map (
I => Ain_0_INBUF,
O => R0_DFF0_Q_DYMUX_1312
);
R0_DFF0_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X1Y5",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R0_DFF0_Q_CLKINV_1310
);
MAC_C2_0_XUSED : X_BUF
generic map(
LOC => "SLICE_X4Y4",
PATHPULSE => 605 ps
)
port map (
I => MAC_C2(0),
O => MAC_C2_0_0
);
MAC_C2_0_YUSED : X_BUF
generic map(
LOC => "SLICE_X4Y4",
PATHPULSE => 605 ps
)
port map (
I => MAC_C1_0_pack_2,
O => MAC_C1(0)
);
R2_DFF3_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X2Y7",
PATHPULSE => 605 ps
)
port map (
I => S6(3),
O => R2_DFF3_Q_DYMUX_1261
);
R2_DFF3_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y7",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF3_Q_CLKINV_1252
);
FA_D_5_XUSED : X_BUF
generic map(
LOC => "SLICE_X2Y6",
PATHPULSE => 605 ps
)
port map (
I => FA_D(5),
O => FA_D_5_0
);
FA_D_5_YUSED : X_BUF
generic map(
LOC => "SLICE_X2Y6",
PATHPULSE => 605 ps
)
port map (
I => FA_D_4_pack_1,
O => FA_D(4)
);
N7_XUSED : X_BUF
generic map(
LOC => "SLICE_X3Y8",
PATHPULSE => 605 ps
)
port map (
I => N7,
O => N7_0
);
N7_YUSED : X_BUF
generic map(
LOC => "SLICE_X3Y8",
PATHPULSE => 605 ps
)
port map (
I => N6,
O => N6_0
);
R0_DFF1_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X0Y10",
PATHPULSE => 605 ps
)
port map (
I => Ain_1_IBUF_376,
O => R0_DFF1_Q_DYMUX_1345
);
R0_DFF1_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X0Y10",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R0_DFF1_Q_CLKINV_1343
);
R0_DFF2_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X7Y3",
PATHPULSE => 605 ps
)
port map (
I => Ain_2_IBUF_378,
O => R0_DFF2_Q_DYMUX_1354
);
R0_DFF2_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X7Y3",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R0_DFF2_Q_CLKINV_1352
);
MAC_C2_1_XUSED : X_BUF
generic map(
LOC => "SLICE_X4Y7",
PATHPULSE => 605 ps
)
port map (
I => MAC_C2(1),
O => MAC_C2_1_0
);
MAC_C2_1_YUSED : X_BUF
generic map(
LOC => "SLICE_X4Y7",
PATHPULSE => 605 ps
)
port map (
I => MAC_S1_2_pack_1,
O => MAC_S1(2)
);
MAC_S3_2_XUSED : X_BUF
generic map(
LOC => "SLICE_X7Y5",
PATHPULSE => 605 ps
)
port map (
I => MAC_S3(2),
O => MAC_S3_2_0
);
MAC_S3_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X7Y5",
PATHPULSE => 605 ps
)
port map (
I => MAC_C2_2_pack_1,
O => MAC_C2(2)
);
MAC_C3_2_XUSED : X_BUF
generic map(
LOC => "SLICE_X6Y4",
PATHPULSE => 605 ps
)
port map (
I => MAC_C3(2),
O => MAC_C3_2_0
);
MAC_C3_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X6Y4",
PATHPULSE => 605 ps
)
port map (
I => MAC_HAM23_A_pack_1,
O => MAC_HAM23_A
);
FA_D_2_XUSED : X_BUF
generic map(
LOC => "SLICE_X5Y4",
PATHPULSE => 605 ps
)
port map (
I => FA_D(2),
O => FA_D_2_0
);
FA_D_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X5Y4",
PATHPULSE => 605 ps
)
port map (
I => S3_2_pack_1,
O => S3(2)
);
R0_DFF3_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X5Y5",
PATHPULSE => 605 ps
)
port map (
I => Ain_3_IBUF_380,
O => R0_DFF3_Q_DYMUX_1363
);
R0_DFF3_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X5Y5",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R0_DFF3_Q_CLKINV_1361
);
R1_DFF0_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X18Y4",
PATHPULSE => 605 ps
)
port map (
I => Bin_0_INBUF,
O => R1_DFF0_Q_DYMUX_1372
);
R1_DFF0_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X18Y4",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R1_DFF0_Q_CLKINV_1370
);
R1_DFF1_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X14Y3",
PATHPULSE => 605 ps
)
port map (
I => Bin_1_INBUF,
O => R1_DFF1_Q_DYMUX_1381
);
R1_DFF1_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X14Y3",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R1_DFF1_Q_CLKINV_1379
);
N2_XUSED : X_BUF
generic map(
LOC => "SLICE_X6Y7",
PATHPULSE => 605 ps
)
port map (
I => N2,
O => N2_0
);
R1_DFF3_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X22Y0",
PATHPULSE => 605 ps
)
port map (
I => Bin_3_INBUF,
O => R1_DFF3_Q_DYMUX_1411
);
R1_DFF3_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X22Y0",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R1_DFF3_Q_CLKINV_1409
);
Aout_0_OBUF : X_OBUF
generic map(
LOC => "PAD205"
)
port map (
I => Aout_0_O,
O => Aout(0)
);
Result_0_OBUF : X_OBUF
generic map(
LOC => "PAD216"
)
port map (
I => Result_0_O,
O => Result(0)
);
Result_1_OBUF : X_OBUF
generic map(
LOC => "PAD220"
)
port map (
I => Result_1_O,
O => Result(1)
);
R1_DFF2_Q_DYMUX : X_BUF
generic map(
LOC => "SLICE_X16Y3",
PATHPULSE => 605 ps
)
port map (
I => Bin_2_INBUF,
O => R1_DFF2_Q_DYMUX_1402
);
R1_DFF2_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X16Y3",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R1_DFF2_Q_CLKINV_1400
);
MAC_S1_1_XUSED : X_BUF
generic map(
LOC => "SLICE_X4Y5",
PATHPULSE => 605 ps
)
port map (
I => MAC_S1(1),
O => MAC_S1_1_0
);
MAC_S1_1_YUSED : X_BUF
generic map(
LOC => "SLICE_X4Y5",
PATHPULSE => 605 ps
)
port map (
I => N18,
O => N18_0
);
Aout_3_OBUF : X_OBUF
generic map(
LOC => "PAD204"
)
port map (
I => Aout_3_O,
O => Aout(3)
);
Result_3_OBUF : X_OBUF
generic map(
LOC => "PAD223"
)
port map (
I => Result_3_O,
O => Result(3)
);
Result_7_OBUF : X_OBUF
generic map(
LOC => "PAD182"
)
port map (
I => Result_7_O,
O => Result(7)
);
R1_DFF0_Q_1 : X_FF
generic map(
LOC => "PAD173",
INIT => '0'
)
port map (
I => Bin_0_IFF_IFFDMUX_570,
CE => VCC,
CLK => Bin_0_IFF_ICLK1INV_572,
SET => GND,
RST => GND,
O => R1_DFF0_Q_1_387
);
Bin_0_IFF_ICLK1INV : X_BUF
generic map(
LOC => "PAD173",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => Bin_0_IFF_ICLK1INV_572
);
Bin_0_IFF_IFFDMUX : X_BUF
generic map(
LOC => "PAD173",
PATHPULSE => 605 ps
)
port map (
I => Bin_0_INBUF,
O => Bin_0_IFF_IFFDMUX_570
);
Bin_0_IBUF : X_BUF
generic map(
LOC => "PAD173",
PATHPULSE => 605 ps
)
port map (
I => Bin(0),
O => Bin_0_INBUF
);
Bin_1_IBUF : X_BUF
generic map(
LOC => "PAD171",
PATHPULSE => 605 ps
)
port map (
I => Bin(1),
O => Bin_1_INBUF
);
Result_8_OBUF : X_OBUF
generic map(
LOC => "PAD218"
)
port map (
I => Result_8_O,
O => Result(8)
);
Result_6_OBUF : X_OBUF
generic map(
LOC => "PAD219"
)
port map (
I => Result_6_O,
O => Result(6)
);
Result_5_OBUF : X_OBUF
generic map(
LOC => "PAD221"
)
port map (
I => Result_5_O,
O => Result(5)
);
Result_9_OBUF : X_OBUF
generic map(
LOC => "PAD217"
)
port map (
I => Result_9_O,
O => Result(9)
);
Result_4_OBUF : X_OBUF
generic map(
LOC => "PAD215"
)
port map (
I => Result_4_O,
O => Result(4)
);
Bin_2_IBUF : X_BUF
generic map(
LOC => "PAD168",
PATHPULSE => 605 ps
)
port map (
I => Bin(2),
O => Bin_2_INBUF
);
Bin_3_IBUF : X_BUF
generic map(
LOC => "PAD167",
PATHPULSE => 605 ps
)
port map (
I => Bin(3),
O => Bin_3_INBUF
);
Bout_1_OBUF : X_OBUF
generic map(
LOC => "PAD172"
)
port map (
I => Bout_1_O,
O => Bout(1)
);
Bout_0_OBUF : X_OBUF
generic map(
LOC => "PAD174"
)
port map (
I => Bout_0_O,
O => Bout(0)
);
Ain_1_IBUF : X_BUF
generic map(
LOC => "PAD235",
PATHPULSE => 605 ps
)
port map (
I => Ain(1),
O => Ain_1_INBUF
);
Ain_0_IBUF : X_BUF
generic map(
LOC => "PAD206",
PATHPULSE => 605 ps
)
port map (
I => Ain(0),
O => Ain_0_INBUF
);
Bout_2_OBUF : X_OBUF
generic map(
LOC => "PAD166"
)
port map (
I => Bout_2_O,
O => Bout(2)
);
Bout_3_OBUF : X_OBUF
generic map(
LOC => "PAD164"
)
port map (
I => Bout_3_O,
O => Bout(3)
);
CLK_BUFGP_IBUFG : X_BUF
generic map(
LOC => "PAD169",
PATHPULSE => 605 ps
)
port map (
I => CLK,
O => CLK_INBUF
);
R2_DFF1_Q_DXMUX : X_BUF
generic map(
LOC => "SLICE_X2Y10",
PATHPULSE => 605 ps
)
port map (
I => S6(1),
O => R2_DFF1_Q_DXMUX_757
);
R2_DFF1_Q_YUSED : X_BUF
generic map(
LOC => "SLICE_X2Y10",
PATHPULSE => 605 ps
)
port map (
I => S3_0_pack_2,
O => S3(0)
);
R2_DFF1_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y10",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF1_Q_CLKINV_740
);
Ain_3_IBUF : X_BUF
generic map(
LOC => "PAD203",
PATHPULSE => 605 ps
)
port map (
I => Ain(3),
O => Ain_3_INBUF
);
Ain_2_IBUF : X_BUF
generic map(
LOC => "PAD183",
PATHPULSE => 605 ps
)
port map (
I => Ain(2),
O => Ain_2_INBUF
);
R2_DFF9_Q_DXMUX : X_BUF
generic map(
LOC => "SLICE_X2Y9",
PATHPULSE => 605 ps
)
port map (
I => S6(9),
O => R2_DFF9_Q_DXMUX_787
);
R2_DFF9_Q_YUSED : X_BUF
generic map(
LOC => "SLICE_X2Y9",
PATHPULSE => 605 ps
)
port map (
I => FA_FA6_Cout1_O_pack_2,
O => FA_FA6_Cout1_O
);
R2_DFF9_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y9",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF9_Q_CLKINV_771
);
FA_D_1_XUSED : X_BUF
generic map(
LOC => "SLICE_X2Y11",
PATHPULSE => 605 ps
)
port map (
I => FA_D(1),
O => FA_D_1_0
);
FA_D_1_YUSED : X_BUF
generic map(
LOC => "SLICE_X2Y11",
PATHPULSE => 605 ps
)
port map (
I => S3_1_pack_1,
O => S3(1)
);
MAC_S2_1_XUSED : X_BUF
generic map(
LOC => "SLICE_X4Y6",
PATHPULSE => 605 ps
)
port map (
I => MAC_S2(1),
O => MAC_S2_1_0
);
MAC_S2_1_YUSED : X_BUF
generic map(
LOC => "SLICE_X4Y6",
PATHPULSE => 605 ps
)
port map (
I => MAC_C1_1_pack_2,
O => MAC_C1(1)
);
R2_DFF7_Q_DXMUX : X_BUF
generic map(
LOC => "SLICE_X3Y9",
PATHPULSE => 605 ps
)
port map (
I => S6(7),
O => R2_DFF7_Q_DXMUX_871
);
R2_DFF7_Q_YUSED : X_BUF
generic map(
LOC => "SLICE_X3Y9",
PATHPULSE => 605 ps
)
port map (
I => FA_FA6_Cout1_SW0_O_pack_2,
O => FA_FA6_Cout1_SW0_O
);
R2_DFF7_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X3Y9",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF7_Q_CLKINV_854
);
R2_DFF8_Q_DXMUX : X_BUF
generic map(
LOC => "SLICE_X5Y9",
PATHPULSE => 605 ps
)
port map (
I => S6(8),
O => R2_DFF8_Q_DXMUX_817
);
R2_DFF8_Q_YUSED : X_BUF
generic map(
LOC => "SLICE_X5Y9",
PATHPULSE => 605 ps
)
port map (
I => FA_FA6_Cout1_SW2_O_pack_2,
O => FA_FA6_Cout1_SW2_O
);
R2_DFF8_Q_CLKINV : X_BUF
generic map(
LOC => "SLICE_X5Y9",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => R2_DFF8_Q_CLKINV_802
);
CLK_BUFGP_BUFG : X_BUFGMUX
generic map(
LOC => "BUFGMUX0"
)
port map (
I0 => CLK_BUFGP_BUFG_I0_INV,
I1 => GND,
S => CLK_BUFGP_BUFG_S_INVNOT,
O => CLK_BUFGP
);
CLK_BUFGP_BUFG_SINV : X_INV
generic map(
LOC => "BUFGMUX0",
PATHPULSE => 605 ps
)
port map (
I => '1',
O => CLK_BUFGP_BUFG_S_INVNOT
);
CLK_BUFGP_BUFG_I0_USED : X_BUF
generic map(
LOC => "BUFGMUX0",
PATHPULSE => 605 ps
)
port map (
I => CLK_INBUF,
O => CLK_BUFGP_BUFG_I0_INV
);
S3_7_XUSED : X_BUF
generic map(
LOC => "SLICE_X7Y7",
PATHPULSE => 605 ps
)
port map (
I => S3(7),
O => S3_7_0
);
S3_7_YUSED : X_BUF
generic map(
LOC => "SLICE_X7Y7",
PATHPULSE => 605 ps
)
port map (
I => MAC_C4_1_pack_1,
O => MAC_C4(1)
);
Aout_2_OUTPUT_OFF_O1INV : X_BUF
generic map(
LOC => "PAD181",
PATHPULSE => 605 ps
)
port map (
I => Ain_2_IBUF_378,
O => Aout_2_OUTPUT_OFF_O1INV_484
);
Aout_2_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD181",
PATHPULSE => 605 ps
)
port map (
I => R0_DFF2_Q_1_487,
O => Aout_2_O
);
Aout_2_OUTPUT_OTCLK1INV : X_BUF
generic map(
LOC => "PAD181",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => Aout_2_OUTPUT_OTCLK1INV_481
);
R0_DFF2_Q_1 : X_FF
generic map(
LOC => "PAD181",
INIT => '0'
)
port map (
I => Aout_2_OUTPUT_OFF_O1INV_484,
CE => VCC,
CLK => Aout_2_OUTPUT_OTCLK1INV_481,
SET => GND,
RST => GND,
O => R0_DFF2_Q_1_487
);
R0_DFF3_Q_1 : X_FF
generic map(
LOC => "PAD204",
INIT => '0'
)
port map (
I => Aout_3_OUTPUT_OFF_O1INV_508,
CE => VCC,
CLK => Aout_3_OUTPUT_OTCLK1INV_505,
SET => GND,
RST => GND,
O => R0_DFF3_Q_1_511
);
Aout_3_OUTPUT_OFF_O1INV : X_BUF
generic map(
LOC => "PAD204",
PATHPULSE => 605 ps
)
port map (
I => Ain_3_IBUF_380,
O => Aout_3_OUTPUT_OFF_O1INV_508
);
Aout_3_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD204",
PATHPULSE => 605 ps
)
port map (
I => R0_DFF3_Q_1_511,
O => Aout_3_O
);
Aout_3_OUTPUT_OTCLK1INV : X_BUF
generic map(
LOC => "PAD204",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => Aout_3_OUTPUT_OTCLK1INV_505
);
R0_DFF1_Q_1 : X_FF
generic map(
LOC => "PAD236",
INIT => '0'
)
port map (
I => Aout_1_OUTPUT_OFF_O1INV_460,
CE => VCC,
CLK => Aout_1_OUTPUT_OTCLK1INV_457,
SET => GND,
RST => GND,
O => R0_DFF1_Q_1_463
);
Aout_1_OUTPUT_OFF_O1INV : X_BUF
generic map(
LOC => "PAD236",
PATHPULSE => 605 ps
)
port map (
I => Ain_1_IBUF_376,
O => Aout_1_OUTPUT_OFF_O1INV_460
);
Aout_1_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD236",
PATHPULSE => 605 ps
)
port map (
I => R0_DFF1_Q_1_463,
O => Aout_1_O
);
Aout_1_OUTPUT_OTCLK1INV : X_BUF
generic map(
LOC => "PAD236",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => Aout_1_OUTPUT_OTCLK1INV_457
);
Ain_0_IFF_IFFDMUX : X_BUF
generic map(
LOC => "PAD206",
PATHPULSE => 605 ps
)
port map (
I => Ain_0_INBUF,
O => Ain_0_IFF_IFFDMUX_670
);
Ain_0_IFF_ICLK1INV : X_BUF
generic map(
LOC => "PAD206",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => Ain_0_IFF_ICLK1INV_672
);
R0_DFF0_Q_1 : X_FF
generic map(
LOC => "PAD206",
INIT => '0'
)
port map (
I => Ain_0_IFF_IFFDMUX_670,
CE => VCC,
CLK => Ain_0_IFF_ICLK1INV_672,
SET => GND,
RST => GND,
O => R0_DFF0_Q_1_395
);
Bin_1_IFF_IFFDMUX : X_BUF
generic map(
LOC => "PAD171",
PATHPULSE => 605 ps
)
port map (
I => Bin_1_INBUF,
O => Bin_1_IFF_IFFDMUX_587
);
Bin_1_IFF_ICLK1INV : X_BUF
generic map(
LOC => "PAD171",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => Bin_1_IFF_ICLK1INV_589
);
R1_DFF1_Q_1 : X_FF
generic map(
LOC => "PAD171",
INIT => '0'
)
port map (
I => Bin_1_IFF_IFFDMUX_587,
CE => VCC,
CLK => Bin_1_IFF_ICLK1INV_589,
SET => GND,
RST => GND,
O => R1_DFF1_Q_1_389
);
R1_DFF2_Q_1 : X_FF
generic map(
LOC => "PAD168",
INIT => '0'
)
port map (
I => Bin_2_IFF_IFFDMUX_604,
CE => VCC,
CLK => Bin_2_IFF_ICLK1INV_606,
SET => GND,
RST => GND,
O => R1_DFF2_Q_1_391
);
Bin_2_IFF_IFFDMUX : X_BUF
generic map(
LOC => "PAD168",
PATHPULSE => 605 ps
)
port map (
I => Bin_2_INBUF,
O => Bin_2_IFF_IFFDMUX_604
);
Bin_2_IFF_ICLK1INV : X_BUF
generic map(
LOC => "PAD168",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => Bin_2_IFF_ICLK1INV_606
);
R1_DFF3_Q_1 : X_FF
generic map(
LOC => "PAD167",
INIT => '0'
)
port map (
I => Bin_3_IFF_IFFDMUX_621,
CE => VCC,
CLK => Bin_3_IFF_ICLK1INV_623,
SET => GND,
RST => GND,
O => R1_DFF3_Q_1_393
);
Bin_3_IFF_IFFDMUX : X_BUF
generic map(
LOC => "PAD167",
PATHPULSE => 605 ps
)
port map (
I => Bin_3_INBUF,
O => Bin_3_IFF_IFFDMUX_621
);
Bin_3_IFF_ICLK1INV : X_BUF
generic map(
LOC => "PAD167",
PATHPULSE => 605 ps
)
port map (
I => CLK_BUFGP,
O => Bin_3_IFF_ICLK1INV_623
);
Ain_3_IFF_IMUX : X_BUF
generic map(
LOC => "PAD203",
PATHPULSE => 605 ps
)
port map (
I => Ain_3_INBUF,
O => Ain_3_IBUF_380
);
R2_DFF9_Q : X_FF
generic map(
LOC => "SLICE_X2Y9",
INIT => '0'
)
port map (
I => R2_DFF9_Q_DXMUX_787,
CE => VCC,
CLK => R2_DFF9_Q_CLKINV_771,
SET => GND,
RST => GND,
O => R2_DFF9_Q_386
);
FA_FA6_Cout1 : X_LUT4
generic map(
INIT => X"FAA0",
LOC => "SLICE_X2Y9"
)
port map (
ADR0 => S3(6),
ADR1 => VCC,
ADR2 => FA_D_5_0,
ADR3 => R2_DFF6_Q_383,
O => FA_FA6_Cout1_O_pack_2
);
FA_FA6_Cout1_SW2 : X_LUT4
generic map(
INIT => X"1117",
LOC => "SLICE_X5Y9"
)
port map (
ADR0 => S3_7_0,
ADR1 => R2_DFF7_Q_384,
ADR2 => R2_DFF6_Q_383,
ADR3 => S3(6),
O => FA_FA6_Cout1_SW2_O_pack_2
);
MAC_HAM11_H1_Cout1 : X_LUT4
generic map(
INIT => X"8000",
LOC => "SLICE_X4Y6"
)
port map (
ADR0 => R0_DFF2_Q_403,
ADR1 => R0_DFF1_Q_400,
ADR2 => R1_DFF0_Q_405,
ADR3 => R1_DFF1_Q_404,
O => MAC_C1_1_pack_2
);
MAC_FAM21_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"963C",
LOC => "SLICE_X4Y6"
)
port map (
ADR0 => R0_DFF1_Q_400,
ADR1 => MAC_C1(1),
ADR2 => MAC_S1(2),
ADR3 => R1_DFF2_Q_399,
O => MAC_S2(1)
);
MAC_S0_0_and00001 : X_LUT4
generic map(
INIT => X"AA00",
LOC => "SLICE_X2Y10"
)
port map (
ADR0 => R0_DFF0_Q_411,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => R1_DFF0_Q_405,
O => S3_0_pack_2
);
Ain_1_IFF_IMUX : X_BUF
generic map(
LOC => "PAD235",
PATHPULSE => 605 ps
)
port map (
I => Ain_1_INBUF,
O => Ain_1_IBUF_376
);
R2_DFF1_Q : X_FF
generic map(
LOC => "SLICE_X2Y10",
INIT => '0'
)
port map (
I => R2_DFF1_Q_DXMUX_757,
CE => VCC,
CLK => R2_DFF1_Q_CLKINV_740,
SET => GND,
RST => GND,
O => R2_DFF1_Q_408
);
FA_FA9_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"A959",
LOC => "SLICE_X2Y9"
)
port map (
ADR0 => R2_DFF9_Q_386,
ADR1 => N6_0,
ADR2 => FA_FA6_Cout1_O,
ADR3 => N7_0,
O => S6(9)
);
Ain_2_IFF_IMUX : X_BUF
generic map(
LOC => "PAD183",
PATHPULSE => 605 ps
)
port map (
I => Ain_2_INBUF,
O => Ain_2_IBUF_378
);
FA_FA1_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"963C",
LOC => "SLICE_X2Y10"
)
port map (
ADR0 => R2_DFF0_Q_409,
ADR1 => R2_DFF1_Q_408,
ADR2 => S3(1),
ADR3 => S3(0),
O => S6(1)
);
MAC_HAM10_H1_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"6CA0",
LOC => "SLICE_X2Y11"
)
port map (
ADR0 => R0_DFF0_Q_411,
ADR1 => R0_DFF1_Q_400,
ADR2 => R1_DFF1_Q_404,
ADR3 => R1_DFF0_Q_405,
O => S3_1_pack_1
);
MAC_FAM30_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"6996",
LOC => "SLICE_X3Y6"
)
port map (
ADR0 => MAC_C2_0_0,
ADR1 => N11_0,
ADR2 => MAC_C1(1),
ADR3 => MAC_S1(2),
O => S3_3_pack_1
);
MAC_FAM31_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"963C",
LOC => "SLICE_X5Y6"
)
port map (
ADR0 => R1_DFF3_Q_423,
ADR1 => MAC_S2_2_0,
ADR2 => MAC_C2_1_0,
ADR3 => R0_DFF1_Q_400,
O => MAC_S3_1_pack_1
);
MAC_HAM23_A1 : X_LUT4
generic map(
INIT => X"CC00",
LOC => "SLICE_X6Y4"
)
port map (
ADR0 => VCC,
ADR1 => R0_DFF3_Q_424,
ADR2 => VCC,
ADR3 => R1_DFF2_Q_399,
O => MAC_HAM23_A_pack_1
);
FA_FA1_Cout1 : X_LUT4
generic map(
INIT => X"E8C0",
LOC => "SLICE_X2Y11"
)
port map (
ADR0 => R2_DFF0_Q_409,
ADR1 => R2_DFF1_Q_408,
ADR2 => S3(1),
ADR3 => S3(0),
O => FA_D(1)
);
FA_FA8_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"A965",
LOC => "SLICE_X5Y9"
)
port map (
ADR0 => R2_DFF8_Q_385,
ADR1 => FA_D_5_0,
ADR2 => N15_0,
ADR3 => FA_FA6_Cout1_SW2_O,
O => S6(8)
);
MAC_FA41_Cout1 : X_LUT4
generic map(
INIT => X"E888",
LOC => "SLICE_X7Y7"
)
port map (
ADR0 => MAC_C3(1),
ADR1 => MAC_S3_2_0,
ADR2 => N2_0,
ADR3 => MAC_S3(1),
O => MAC_C4_1_pack_1
);
MAC_FA42_Cout1 : X_LUT4
generic map(
INIT => X"EA80",
LOC => "SLICE_X7Y7"
)
port map (
ADR0 => MAC_C3_2_0,
ADR1 => R0_DFF3_Q_424,
ADR2 => R1_DFF3_Q_423,
ADR3 => MAC_C4(1),
O => S3(7)
);
FA_FA3_Cout1 : X_LUT4
generic map(
INIT => X"FCC0",
LOC => "SLICE_X3Y6"
)
port map (
ADR0 => VCC,
ADR1 => R2_DFF3_Q_379,
ADR2 => S3(3),
ADR3 => FA_D_2_0,
O => FA_D(3)
);
MAC_FA42_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"9666",
LOC => "SLICE_X5Y7"
)
port map (
ADR0 => MAC_C3_2_0,
ADR1 => MAC_C4(1),
ADR2 => R1_DFF3_Q_423,
ADR3 => R0_DFF3_Q_424,
O => S3_6_pack_1
);
MAC_FAM32_Cout1 : X_LUT4
generic map(
INIT => X"E8A0",
LOC => "SLICE_X6Y4"
)
port map (
ADR0 => MAC_C2(2),
ADR1 => R0_DFF2_Q_403,
ADR2 => MAC_HAM23_A,
ADR3 => R1_DFF3_Q_423,
O => MAC_C3(2)
);
MAC_HA40_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"1E78",
LOC => "SLICE_X5Y6"
)
port map (
ADR0 => MAC_FAM30_A_0,
ADR1 => MAC_C2_0_0,
ADR2 => MAC_S3(1),
ADR3 => MAC_S2_1_0,
O => S3(4)
);
FA_FA7_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"17E8",
LOC => "SLICE_X3Y9"
)
port map (
ADR0 => S3(6),
ADR1 => FA_D_5_0,
ADR2 => R2_DFF6_Q_383,
ADR3 => FA_FA6_Cout1_SW0_O,
O => S6(7)
);
R2_DFF7_Q : X_FF
generic map(
LOC => "SLICE_X3Y9",
INIT => '0'
)
port map (
I => R2_DFF7_Q_DXMUX_871,
CE => VCC,
CLK => R2_DFF7_Q_CLKINV_854,
SET => GND,
RST => GND,
O => R2_DFF7_Q_384
);
FA_FA6_Cout1_SW0 : X_LUT4
generic map(
INIT => X"0FF0",
LOC => "SLICE_X3Y9"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => S3_7_0,
ADR3 => R2_DFF7_Q_384,
O => FA_FA6_Cout1_SW0_O_pack_2
);
R2_DFF8_Q : X_FF
generic map(
LOC => "SLICE_X5Y9",
INIT => '0'
)
port map (
I => R2_DFF8_Q_DXMUX_817,
CE => VCC,
CLK => R2_DFF8_Q_CLKINV_802,
SET => GND,
RST => GND,
O => R2_DFF8_Q_385
);
FA_FA5_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"9966",
LOC => "SLICE_X0Y6"
)
port map (
ADR0 => S3_5_0,
ADR1 => FA_D(4),
ADR2 => VCC,
ADR3 => R2_DFF5_Q_382,
O => S6(5)
);
MAC_FAM20_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"9666",
LOC => "SLICE_X5Y4"
)
port map (
ADR0 => MAC_C1(0),
ADR1 => MAC_S1_1_0,
ADR2 => R0_DFF0_Q_411,
ADR3 => R1_DFF2_Q_399,
O => S3_2_pack_1
);
MAC_FAM21_Cout1 : X_LUT4
generic map(
INIT => X"F880",
LOC => "SLICE_X4Y7"
)
port map (
ADR0 => R0_DFF1_Q_400,
ADR1 => R1_DFF2_Q_399,
ADR2 => MAC_S1(2),
ADR3 => MAC_C1(1),
O => MAC_C2(1)
);
MAC_FAM32_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"936C",
LOC => "SLICE_X7Y5"
)
port map (
ADR0 => R1_DFF3_Q_423,
ADR1 => MAC_HAM23_A,
ADR2 => R0_DFF2_Q_403,
ADR3 => MAC_C2(2),
O => MAC_S3(2)
);
FA_FA5_Cout1 : X_LUT4
generic map(
INIT => X"EE88",
LOC => "SLICE_X2Y6"
)
port map (
ADR0 => S3_5_0,
ADR1 => R2_DFF5_Q_382,
ADR2 => VCC,
ADR3 => FA_D(4),
O => FA_D(5)
);
MAC_FAM22_H2_Mxor_Sout_Result1_SW0 : X_LUT4
generic map(
INIT => X"55FF",
LOC => "SLICE_X6Y5"
)
port map (
ADR0 => R1_DFF1_Q_404,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => R0_DFF3_Q_424,
O => MAC_FAM22_H2_Mxor_Sout_Result1_SW0_O_pack_1
);
FA_FA6_Cout1_SW1 : X_LUT4
generic map(
INIT => X"173F",
LOC => "SLICE_X5Y7"
)
port map (
ADR0 => R2_DFF6_Q_383,
ADR1 => R2_DFF7_Q_384,
ADR2 => S3_7_0,
ADR3 => S3(6),
O => N15
);
FA_FA2_Cout1 : X_LUT4
generic map(
INIT => X"FCC0",
LOC => "SLICE_X5Y4"
)
port map (
ADR0 => VCC,
ADR1 => R2_DFF2_Q_377,
ADR2 => S3(2),
ADR3 => FA_D_1_0,
O => FA_D(2)
);
MAC_HAM12_H1_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"6CA0",
LOC => "SLICE_X4Y7"
)
port map (
ADR0 => R1_DFF0_Q_405,
ADR1 => R0_DFF2_Q_403,
ADR2 => R0_DFF3_Q_424,
ADR3 => R1_DFF1_Q_404,
O => MAC_S1_2_pack_1
);
MAC_HAM10_H1_Cout1 : X_LUT4
generic map(
INIT => X"8000",
LOC => "SLICE_X4Y4"
)
port map (
ADR0 => R1_DFF0_Q_405,
ADR1 => R0_DFF1_Q_400,
ADR2 => R1_DFF1_Q_404,
ADR3 => R0_DFF0_Q_411,
O => MAC_C1_0_pack_2
);
MAC_FAM22_Cout1 : X_LUT4
generic map(
INIT => X"C080",
LOC => "SLICE_X7Y5"
)
port map (
ADR0 => R1_DFF2_Q_399,
ADR1 => N18_0,
ADR2 => R1_DFF1_Q_404,
ADR3 => R1_DFF0_Q_405,
O => MAC_C2_2_pack_1
);
MAC_FAM22_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"CB07",
LOC => "SLICE_X6Y5"
)
port map (
ADR0 => R1_DFF0_Q_405,
ADR1 => R0_DFF2_Q_403,
ADR2 => MAC_FAM22_H2_Mxor_Sout_Result1_SW0_O,
ADR3 => R1_DFF2_Q_399,
O => MAC_S2(2)
);
MAC_FA41_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"3C96",
LOC => "SLICE_X7Y6"
)
port map (
ADR0 => MAC_S3(1),
ADR1 => MAC_S3_2_0,
ADR2 => MAC_C3(1),
ADR3 => N4_0,
O => S3(5)
);
MAC_FAM20_Cout1 : X_LUT4
generic map(
INIT => X"EC80",
LOC => "SLICE_X4Y4"
)
port map (
ADR0 => R1_DFF2_Q_399,
ADR1 => MAC_S1_1_0,
ADR2 => R0_DFF0_Q_411,
ADR3 => MAC_C1(0),
O => MAC_C2(0)
);
MAC_FAM31_Cout1 : X_LUT4
generic map(
INIT => X"E8C0",
LOC => "SLICE_X7Y6"
)
port map (
ADR0 => R1_DFF3_Q_423,
ADR1 => MAC_C2_1_0,
ADR2 => MAC_S2_2_0,
ADR3 => R0_DFF1_Q_400,
O => MAC_C3_1_pack_1
);
FA_FA4_Cout1 : X_LUT4
generic map(
INIT => X"FAA0",
LOC => "SLICE_X2Y6"
)
port map (
ADR0 => R2_DFF4_Q_381,
ADR1 => VCC,
ADR2 => FA_D_3_0,
ADR3 => S3_4_0,
O => FA_D_4_pack_1
);
FA_FA2_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"C33C",
LOC => "SLICE_X5Y8"
)
port map (
ADR0 => VCC,
ADR1 => R2_DFF2_Q_377,
ADR2 => S3(2),
ADR3 => FA_D_1_0,
O => S6(2)
);
R2_DFF3_Q : X_FF
generic map(
LOC => "SLICE_X2Y7",
INIT => '0'
)
port map (
I => R2_DFF3_Q_DYMUX_1261,
CE => VCC,
CLK => R2_DFF3_Q_CLKINV_1252,
SET => GND,
RST => GND,
O => R2_DFF3_Q_379
);
R2_DFF6_Q : X_FF
generic map(
LOC => "SLICE_X2Y8",
INIT => '0'
)
port map (
I => R2_DFF6_Q_DYMUX_1195,
CE => VCC,
CLK => R2_DFF6_Q_CLKINV_1186,
SET => GND,
RST => GND,
O => R2_DFF6_Q_383
);
MAC_FAM30_H2_Mxor_Sout_Result1_SW0 : X_LUT4
generic map(
INIT => X"6AC0",
LOC => "SLICE_X6Y6"
)
port map (
ADR0 => R0_DFF1_Q_400,
ADR1 => R1_DFF3_Q_423,
ADR2 => R0_DFF0_Q_411,
ADR3 => R1_DFF2_Q_399,
O => N11
);
MAC_FAM30_A1 : X_LUT4
generic map(
INIT => X"8888",
LOC => "SLICE_X4Y8"
)
port map (
ADR0 => R0_DFF0_Q_411,
ADR1 => R1_DFF3_Q_423,
ADR2 => VCC,
ADR3 => VCC,
O => MAC_FAM30_A
);
FA_FA8_H2_Cout1_SW1 : X_LUT4
generic map(
INIT => X"555F",
LOC => "SLICE_X3Y8"
)
port map (
ADR0 => R2_DFF8_Q_385,
ADR1 => VCC,
ADR2 => S3_7_0,
ADR3 => R2_DFF7_Q_384,
O => N7
);
R0_DFF0_Q : X_FF
generic map(
LOC => "SLICE_X1Y5",
INIT => '0'
)
port map (
I => R0_DFF0_Q_DYMUX_1312,
CE => VCC,
CLK => R0_DFF0_Q_CLKINV_1310,
SET => GND,
RST => GND,
O => R0_DFF0_Q_411
);
FA_FA8_H2_Cout1_SW0 : X_LUT4
generic map(
INIT => X"5FFF",
LOC => "SLICE_X3Y8"
)
port map (
ADR0 => R2_DFF8_Q_385,
ADR1 => VCC,
ADR2 => S3_7_0,
ADR3 => R2_DFF7_Q_384,
O => N6
);
R2_DFF2_Q : X_FF
generic map(
LOC => "SLICE_X5Y8",
INIT => '0'
)
port map (
I => R2_DFF2_Q_DYMUX_1243,
CE => VCC,
CLK => R2_DFF2_Q_CLKINV_1234,
SET => GND,
RST => GND,
O => R2_DFF2_Q_377
);
R2_DFF5_Q : X_FF
generic map(
LOC => "SLICE_X0Y6",
INIT => '0'
)
port map (
I => R2_DFF5_Q_DYMUX_1177,
CE => VCC,
CLK => R2_DFF5_Q_CLKINV_1168,
SET => GND,
RST => GND,
O => R2_DFF5_Q_382
);
FA_FA4_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"9966",
LOC => "SLICE_X3Y7"
)
port map (
ADR0 => R2_DFF4_Q_381,
ADR1 => FA_D_3_0,
ADR2 => VCC,
ADR3 => S3_4_0,
O => S6(4)
);
R2_DFF4_Q : X_FF
generic map(
LOC => "SLICE_X3Y7",
INIT => '0'
)
port map (
I => R2_DFF4_Q_DYMUX_1279,
CE => VCC,
CLK => R2_DFF4_Q_CLKINV_1270,
SET => GND,
RST => GND,
O => R2_DFF4_Q_381
);
MAC_HA40_Cout1_SW1 : X_LUT4
generic map(
INIT => X"1777",
LOC => "SLICE_X6Y6"
)
port map (
ADR0 => MAC_S2_1_0,
ADR1 => MAC_C2_0_0,
ADR2 => R0_DFF0_Q_411,
ADR3 => R1_DFF3_Q_423,
O => N4
);
FA_FA6_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"C33C",
LOC => "SLICE_X2Y8"
)
port map (
ADR0 => VCC,
ADR1 => R2_DFF6_Q_383,
ADR2 => FA_D_5_0,
ADR3 => S3(6),
O => S6(6)
);
FA_HA0_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"66CC",
LOC => "SLICE_X4Y8"
)
port map (
ADR0 => R0_DFF0_Q_411,
ADR1 => R2_DFF0_Q_409,
ADR2 => VCC,
ADR3 => R1_DFF0_Q_405,
O => S6(0)
);
R2_DFF0_Q : X_FF
generic map(
LOC => "SLICE_X4Y8",
INIT => '0'
)
port map (
I => R2_DFF0_Q_DYMUX_1216,
CE => VCC,
CLK => R2_DFF0_Q_CLKINV_1207,
SET => GND,
RST => GND,
O => R2_DFF0_Q_409
);
FA_FA3_H2_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"9696",
LOC => "SLICE_X2Y7"
)
port map (
ADR0 => FA_D_2_0,
ADR1 => S3(3),
ADR2 => R2_DFF3_Q_379,
ADR3 => VCC,
O => S6(3)
);
R1_DFF0_Q : X_FF
generic map(
LOC => "SLICE_X18Y4",
INIT => '0'
)
port map (
I => R1_DFF0_Q_DYMUX_1372,
CE => VCC,
CLK => R1_DFF0_Q_CLKINV_1370,
SET => GND,
RST => GND,
O => R1_DFF0_Q_405
);
R1_DFF1_Q : X_FF
generic map(
LOC => "SLICE_X14Y3",
INIT => '0'
)
port map (
I => R1_DFF1_Q_DYMUX_1381,
CE => VCC,
CLK => R1_DFF1_Q_CLKINV_1379,
SET => GND,
RST => GND,
O => R1_DFF1_Q_404
);
MAC_FAM22_Cout1_SW0 : X_LUT4
generic map(
INIT => X"F000",
LOC => "SLICE_X4Y5"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => R0_DFF2_Q_403,
ADR3 => R0_DFF3_Q_424,
O => N18
);
R0_DFF3_Q : X_FF
generic map(
LOC => "SLICE_X5Y5",
INIT => '0'
)
port map (
I => R0_DFF3_Q_DYMUX_1363,
CE => VCC,
CLK => R0_DFF3_Q_CLKINV_1361,
SET => GND,
RST => GND,
O => R0_DFF3_Q_424
);
MAC_HA40_Cout1_SW0 : X_LUT4
generic map(
INIT => X"E888",
LOC => "SLICE_X6Y7"
)
port map (
ADR0 => MAC_S2_1_0,
ADR1 => MAC_C2_0_0,
ADR2 => R0_DFF0_Q_411,
ADR3 => R1_DFF3_Q_423,
O => N2
);
R1_DFF2_Q : X_FF
generic map(
LOC => "SLICE_X16Y3",
INIT => '0'
)
port map (
I => R1_DFF2_Q_DYMUX_1402,
CE => VCC,
CLK => R1_DFF2_Q_CLKINV_1400,
SET => GND,
RST => GND,
O => R1_DFF2_Q_399
);
R0_DFF2_Q : X_FF
generic map(
LOC => "SLICE_X7Y3",
INIT => '0'
)
port map (
I => R0_DFF2_Q_DYMUX_1354,
CE => VCC,
CLK => R0_DFF2_Q_CLKINV_1352,
SET => GND,
RST => GND,
O => R0_DFF2_Q_403
);
R1_DFF3_Q : X_FF
generic map(
LOC => "SLICE_X22Y0",
INIT => '0'
)
port map (
I => R1_DFF3_Q_DYMUX_1411,
CE => VCC,
CLK => R1_DFF3_Q_CLKINV_1409,
SET => GND,
RST => GND,
O => R1_DFF3_Q_423
);
MAC_HAM11_H1_Mxor_Sout_Result1 : X_LUT4
generic map(
INIT => X"6AC0",
LOC => "SLICE_X4Y5"
)
port map (
ADR0 => R1_DFF0_Q_405,
ADR1 => R0_DFF1_Q_400,
ADR2 => R1_DFF1_Q_404,
ADR3 => R0_DFF2_Q_403,
O => MAC_S1(1)
);
R0_DFF1_Q : X_FF
generic map(
LOC => "SLICE_X0Y10",
INIT => '0'
)
port map (
I => R0_DFF1_Q_DYMUX_1345,
CE => VCC,
CLK => R0_DFF1_Q_CLKINV_1343,
SET => GND,
RST => GND,
O => R0_DFF1_Q_400
);
Result_2_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD222",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF2_Q_377,
O => Result_2_O
);
Aout_0_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD205",
PATHPULSE => 605 ps
)
port map (
I => R0_DFF0_Q_1_395,
O => Aout_0_O
);
Result_0_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD216",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF0_Q_409,
O => Result_0_O
);
Result_1_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD220",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF1_Q_408,
O => Result_1_O
);
Result_3_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD223",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF3_Q_379,
O => Result_3_O
);
Result_7_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD182",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF7_Q_384,
O => Result_7_O
);
Result_8_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD218",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF8_Q_385,
O => Result_8_O
);
Result_6_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD219",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF6_Q_383,
O => Result_6_O
);
Result_5_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD221",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF5_Q_382,
O => Result_5_O
);
Result_9_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD217",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF9_Q_386,
O => Result_9_O
);
Result_4_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD215",
PATHPULSE => 605 ps
)
port map (
I => R2_DFF4_Q_381,
O => Result_4_O
);
Bout_1_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD172",
PATHPULSE => 605 ps
)
port map (
I => R1_DFF1_Q_1_389,
O => Bout_1_O
);
Bout_0_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD174",
PATHPULSE => 605 ps
)
port map (
I => R1_DFF0_Q_1_387,
O => Bout_0_O
);
Bout_2_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD166",
PATHPULSE => 605 ps
)
port map (
I => R1_DFF2_Q_1_391,
O => Bout_2_O
);
Bout_3_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD164",
PATHPULSE => 605 ps
)
port map (
I => R1_DFF3_Q_1_393,
O => Bout_3_O
);
NlwBlock_DPU_matrix_multiplication_VCC : X_ONE
port map (
O => VCC
);
NlwBlock_DPU_matrix_multiplication_GND : X_ZERO
port map (
O => GND
);
NlwBlockROC : X_ROC
generic map (ROC_WIDTH => 100 ns)
port map (O => GSR);
NlwBlockTOC : X_TOC
port map (O => GTS);
end Structure;
|
-------------------------------------------------------------------------------
--! @file AEAD_pkg.vhd
--! @brief Package used for authenticated encyryption
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package AEAD_pkg is
--! =======================================================================
--! BDI Type Encoding for CipherCore (based on SegmentType(3 downto 1))
constant BDI_TYPE_ASS : std_logic_vector(3 -1 downto 1) := "00";
constant BDI_TYPE_ASS0 : std_logic_vector(3 -1 downto 0) := "000";
constant BDI_TYPE_ASS1 : std_logic_vector(3 -1 downto 0) := "001";
constant BDI_TYPE_DAT : std_logic_vector(3 -1 downto 1) := "01";
constant BDI_TYPE_DAT0 : std_logic_vector(3 -1 downto 0) := "010";
constant BDI_TYPE_DAT1 : std_logic_vector(3 -1 downto 0) := "011";
constant BDI_TYPE_TAG : std_logic_vector(3 -1 downto 0) := "100";
constant BDI_TYPE_LEN : std_logic_vector(3 -1 downto 0) := "101";
constant BDI_TYPE_NPUB : std_logic_vector(3 -1 downto 0) := "110";
constant BDI_TYPE_NSEC : std_logic_vector(3 -1 downto 0) := "111";
--! =======================================================================
--! Opcode (used by Pre- and Post-Processors)
constant OP_ENCDEC : std_logic_vector(3 -1 downto 0) := "001";
constant OP_ENC : std_logic_vector(4 -1 downto 0) := "0010";
constant OP_DEC : std_logic_vector(4 -1 downto 0) := "0011";
constant OP_LDKEY : std_logic_vector(4 -1 downto 0) := "0100";
constant OP_ACTKEY : std_logic_vector(4 -1 downto 0) := "0111";
--! =======================================================================
--! Status (used by Pre- and Post-Processors)
constant STAT_SUCCESS : std_logic_vector(4 -1 downto 0) := "1110";
constant STAT_FAILURE : std_logic_vector(4 -1 downto 0) := "1111";
--! =======================================================================
--! Segment Type Encoding (used by Pre- and Post-Processors)
--! 00XX
constant ST_A : std_logic_vector(2 -1 downto 0) := "00";
constant ST_AD : std_logic_vector(4 -1 downto 0) := "0001";
constant ST_NPUB_AD : std_logic_vector(4 -1 downto 0) := "0010";
constant ST_AD_NPUB : std_logic_vector(4 -1 downto 0) := "0011";
--! 01XX
constant ST_D : std_logic_vector(2 -1 downto 0) := "01";
constant ST_PT : std_logic_vector(4 -1 downto 0) := "0100";
constant ST_CT : std_logic_vector(4 -1 downto 0) := "0101";
constant ST_CT_TAG : std_logic_vector(4 -1 downto 0) := "0110";
--! 10XX
constant ST_TAG : std_logic_vector(4 -1 downto 0) := "1000";
constant ST_LEN : std_logic_vector(4 -1 downto 0) := "1010";
--! 11XX
constant ST_KEY : std_logic_vector(4 -1 downto 0) := "1100";
constant ST_NPUB : std_logic_vector(4 -1 downto 0) := "1101";
constant ST_NSEC : std_logic_vector(3 -1 downto 0) := "111";
constant ST_NSEC_PT : std_logic_vector(4 -1 downto 0) := "1110";
constant ST_NSEC_CT : std_logic_vector(4 -1 downto 0) := "1111";
--! =======================================================================
--! Maximum supported length
constant SINGLE_PASS_MAX : integer := 32;
constant TWO_PASS_MAX : integer := 11;
--! =======================================================================
--! Functions
function log2_ceil (N: natural) return natural; --! Log(2) ceil
end AEAD_pkg;
package body AEAD_pkg is
--! Log of base 2
function log2_ceil (N: natural) return natural is
begin
if ( N = 0 ) then
return 0;
elsif N <= 2 then
return 1;
else
if (N mod 2 = 0) then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end if;
end function log2_ceil;
end package body AEAD_pkg;
|
-- $Id: tb_tst_serloop.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop - sim
-- Description: Generic test bench for sys_tst_serloop_xx
--
-- Dependencies: vlib/serport/serport_uart_rxtx
-- vlib/serport/serport_xontx
--
-- To test: sys_tst_serloop_xx
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 425 1.0 Initial version
-- 2011-11-06 420 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.serport.all;
entity tb_tst_serloop is
port (
CLKS : in slbit; -- clock for serport
CLKH : in slbit; -- clock for humanio
CLK_STOP : out slbit; -- clock stop
P0_RXD : out slbit; -- port 0 receive data (board view)
P0_TXD : in slbit; -- port 0 transmit data (board view)
P0_RTS_N : in slbit; -- port 0 rts_n
P0_CTS_N : out slbit; -- port 0 cts_n
P1_RXD : out slbit; -- port 1 receive data (board view)
P1_TXD : in slbit; -- port 1 transmit data (board view)
P1_RTS_N : in slbit; -- port 1 rts_n
P1_CTS_N : out slbit; -- port 1 cts_n
SWI : out slv8; -- hio switches
BTN : out slv4 -- hio buttons
);
end tb_tst_serloop;
architecture sim of tb_tst_serloop is
signal CLK_STOP_L : slbit := '0';
signal CLK_CYCLE : slv31 := (others=>'0');
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal CLKDIV : slv13 := (others=>'0');
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal ACTPORT : slbit := '0';
signal BREAK : slbit := '0';
signal CTS_CYCLE : integer := 0;
signal CTS_FRACT : integer := 0;
signal XON_CYCLE : integer := 0;
signal XON_FRACT : integer := 0;
signal S2M_ACTIVE : slbit := '0';
signal S2M_SIZE : integer := 0;
signal S2M_ENAESC : slbit := '0';
signal S2M_ENAXON : slbit := '0';
signal M2S_XONSEEN : slbit := '0';
signal M2S_XOFFSEEN : slbit := '0';
signal R_XONRXOK : slbit := '1';
signal R_XONTXOK : slbit := '1';
begin
proc_cycle: process (CLKS)
begin
if rising_edge(CLKS) then
CLK_CYCLE <= slv(unsigned(CLK_CYCLE) + 1);
end if;
end process proc_cycle;
UART : serport_uart_rxtx
generic map (
CDWIDTH => 13)
port map (
CLK => CLKS,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY
);
XONTX : serport_xontx
port map (
CLK => CLKS,
RESET => UART_RESET,
ENAXON => S2M_ENAXON,
ENAESC => S2M_ENAESC,
UART_TXDATA => UART_TXDATA,
UART_TXENA => UART_TXENA,
UART_TXBUSY => UART_TXBUSY,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXOK => R_XONRXOK,
TXOK => R_XONTXOK
);
proc_port_mux: process (ACTPORT, BREAK, UART_TXD, CTS_N,
P0_TXD, P0_RTS_N, P1_TXD, P1_RTS_N)
variable eff_txd : slbit := '0';
begin
if BREAK = '0' then -- if no break active
eff_txd := UART_TXD; -- send uart
else -- otherwise
eff_txd := '0'; -- force '0'
end if;
if ACTPORT = '0' then -- use port 0
P0_RXD <= eff_txd; -- write port 0 inputs
P0_CTS_N <= CTS_N;
UART_RXD <= P0_TXD; -- get port 0 outputs
RTS_N <= P0_RTS_N;
P1_RXD <= '1'; -- port 1 inputs to idle state
P1_CTS_N <= '0';
else -- use port 1
P1_RXD <= eff_txd; -- write port 1 inputs
P1_CTS_N <= CTS_N;
UART_RXD <= P1_TXD; -- get port 1 outputs
RTS_N <= P1_RTS_N;
P0_RXD <= '1'; -- port 0 inputs to idle state
P0_CTS_N <= '0';
end if;
end process proc_port_mux;
proc_cts: process(CLKS)
variable cts_timer : integer := 0;
begin
if rising_edge(CLKS) then
if CTS_CYCLE = 0 then -- if cts throttle off
CTS_N <= '0'; -- cts permanently asserted
else -- otherwise determine throttling
if cts_timer>0 and cts_timer<CTS_CYCLE then -- unless beyond ends
cts_timer := cts_timer - 1; -- decrement
else
cts_timer := CTS_CYCLE-1; -- otherwise reload
end if;
if cts_timer < cts_fract then -- if in lower 'fract' counts
CTS_N <= '1'; -- throttle: deassert CTS
else -- otherwise
CTS_N <= '0'; -- let go: assert CTS
end if;
end if;
end if;
end process proc_cts;
proc_xonrxok: process(CLKS)
variable xon_timer : integer := 0;
begin
if rising_edge(CLKS) then
if XON_CYCLE = 0 then -- if xon throttle off
R_XONRXOK <= '1'; -- xonrxok permanently asserted
else -- otherwise determine throttling
if xon_timer>0 and xon_timer<XON_CYCLE then -- unless beyond ends
xon_timer := xon_timer - 1; -- decrement
else
xon_timer := XON_CYCLE-1; -- otherwise reload
end if;
if xon_timer < xon_fract then -- if in lower 'fract' counts
R_XONRXOK <= '0'; -- throttle: deassert xonrxok
else -- otherwise
R_XONRXOK <= '1'; -- let go: assert xonrxok
end if;
end if;
end if;
end process proc_xonrxok;
proc_xontxok: process(CLKS)
begin
if rising_edge(CLKS) then
if M2S_XONSEEN = '1' then
R_XONTXOK <= '1';
elsif M2S_XOFFSEEN = '1' then
R_XONTXOK <= '0';
end if;
end if;
end process proc_xontxok;
proc_stim: process
file fstim : text open read_mode is "tb_tst_serloop_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable iactport : slbit := '0';
variable iswi : slv8 := (others=>'0');
variable btn_num : integer := 0;
variable i_cycle : integer := 0;
variable i_fract : integer := 0;
variable nbyte : integer := 0;
variable enaesc : slbit := '0';
variable enaxon : slbit := '0';
variable bcnt : integer := 0;
variable itxdata : slv8 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
procedure waitclk(ncyc : in integer) is
begin
for i in 1 to ncyc loop
wait until rising_edge(CLKS);
end loop; -- i
end procedure waitclk;
begin
-- initialize some top level out signals
SWI <= (others=>'0');
BTN <= (others=>'0');
wait until rising_edge(CLKS);
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when "wait " => -- wait
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": wait ");
write(oline, idelta, right, 5);
writeline(output, oline);
waitclk(idelta);
when "port " => -- switch rs232 port
read_ea(iline, iactport);
ACTPORT <= iactport;
writetimestamp(oline, CLK_CYCLE, ": port ");
write(oline, iactport, right, 5);
writeline(output, oline);
when "cts " => -- setup cts throttling
read_ea(iline, i_cycle);
read_ea(iline, i_fract);
CTS_CYCLE <= i_cycle;
CTS_FRACT <= i_fract;
writetimestamp(oline, CLK_CYCLE, ": cts ");
write(oline, i_cycle, right, 5);
write(oline, i_fract, right, 5);
writeline(output, oline);
when "xon " => -- setup xon throttling
read_ea(iline, i_cycle);
read_ea(iline, i_fract);
XON_CYCLE <= i_cycle;
XON_FRACT <= i_fract;
writetimestamp(oline, CLK_CYCLE, ": cts ");
write(oline, i_cycle, right, 5);
write(oline, i_fract, right, 5);
writeline(output, oline);
when "swi " => -- new SWI settings
read_ea(iline, iswi);
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": swi ");
write(oline, iswi, right, 10);
write(oline, idelta, right, 5);
writeline(output, oline);
wait until rising_edge(CLKH);
SWI <= iswi;
wait until rising_edge(CLKS);
waitclk(idelta);
when "btn " => -- BTN push (3 cyc down + 3 cyc wait)
read_ea(iline, btn_num);
read_ea(iline, idelta);
if btn_num>=0 and btn_num<=3 then
writetimestamp(oline, CLK_CYCLE, ": btn ");
write(oline, btn_num, right, 5);
write(oline, idelta, right, 5);
writeline(output, oline);
wait until rising_edge(CLKH);
BTN(btn_num) <= '1'; -- 3 cycle BTN pulse
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
BTN(btn_num) <= '0';
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKS);
waitclk(idelta);
else
write(oline, string'("!! btn: btn number out of range"));
writeline(output, oline);
end if;
when "expect" => -- expect n bytes data
read_ea(iline, nbyte);
read_ea(iline, enaesc);
read_ea(iline, enaxon);
writetimestamp(oline, CLK_CYCLE, ": expect");
write(oline, nbyte, right, 5);
write(oline, enaesc, right, 3);
write(oline, enaxon, right, 3);
writeline(output, oline);
if nbyte > 0 then
S2M_ACTIVE <= '1';
S2M_SIZE <= nbyte;
else
S2M_ACTIVE <= '0';
end if;
S2M_ENAESC <= enaesc;
S2M_ENAXON <= enaxon;
wait until rising_edge(CLKS);
when "send " => -- send n bytes data
read_ea(iline, nbyte);
read_ea(iline, enaesc);
read_ea(iline, enaxon);
writetimestamp(oline, CLK_CYCLE, ": send ");
write(oline, nbyte, right, 5);
write(oline, enaesc, right, 3);
write(oline, enaxon, right, 3);
writeline(output, oline);
bcnt := 0;
itxdata := (others=>'0');
wait until falling_edge(CLKS);
while bcnt < nbyte loop
while TXBUSY='1' or RTS_N='1' loop
wait until falling_edge(CLKS);
end loop;
TXDATA <= itxdata;
itxdata := slv(unsigned(itxdata) + 1);
bcnt := bcnt + 1;
TXENA <= '1';
wait until falling_edge(CLKS);
TXENA <= '0';
wait until falling_edge(CLKS);
end loop;
while TXBUSY='1' or RTS_N='1' loop -- wait till last char send...
wait until falling_edge(CLKS);
end loop;
wait until rising_edge(CLKS);
when "break " => -- send a break for n cycles
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": break ");
write(oline, idelta, right, 5);
writeline(output, oline);
-- send break for n cycles
BREAK <= '1';
waitclk(idelta);
BREAK <= '0';
-- wait for 3 bit cell width
waitclk(3*to_integer(unsigned(CLKDIV)+1));
-- send 'sync' character
wait until falling_edge(CLKS);
TXDATA <= "10000000";
TXENA <= '1';
wait until falling_edge(CLKS);
TXENA <= '0';
wait until rising_edge(CLKS);
when "clkdiv" => -- set new clock divider
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": clkdiv");
write(oline, idelta, right, 5);
writeline(output, oline);
CLKDIV <= slv(to_unsigned(idelta, CLKDIV'length));
UART_RESET <= '1';
wait until rising_edge(CLKS);
UART_RESET <= '0';
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
-- extra wait for at least two character times (20 bit times)
-- to allow tx and rx of the last character
waitclk(20*(to_integer(unsigned(CLKDIV))+1));
CLK_STOP_L <= '1';
wait for 500 ns; -- allows dcm's to stop
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
CLK_STOP <= CLK_STOP_L;
proc_moni: process
variable oline : line;
variable dclk : integer := 0;
variable active_1 : slbit := '0';
variable irxdata : slv8 := (others=>'0');
variable irxeff : slv8 := (others=>'0');
variable irxval : slbit := '0';
variable doesc : slbit := '0';
variable bcnt : integer := 0;
variable xseen : slbit := '0';
begin
loop
wait until falling_edge(CLKS);
M2S_XONSEEN <= '0';
M2S_XOFFSEEN <= '0';
if S2M_ACTIVE='1' and active_1='0' then -- start expect message
irxdata := (others=>'0');
bcnt := 0;
end if;
if S2M_ACTIVE='0' and active_1='1' then -- end expect message
if bcnt = S2M_SIZE then
writetimestamp(oline, CLK_CYCLE, ": OK: message seen");
else
writetimestamp(oline, CLK_CYCLE, ": FAIL: missing chars, seen=");
write(oline, bcnt, right, 5);
write(oline, string'(" expect="));
write(oline, S2M_SIZE, right, 5);
end if;
writeline(output, oline);
end if;
active_1 := S2M_ACTIVE;
if RXVAL = '1' then
writetimestamp(oline, CLK_CYCLE, ": char: ");
write(oline, RXDATA, right, 10);
write(oline, string'(" ("));
writeoct(oline, RXDATA, right, 3);
write(oline, string'(") dt="));
write(oline, dclk, right, 4);
irxeff := RXDATA;
irxval := '1';
if doesc = '1' then
irxeff := not RXDATA;
irxval := '1';
doesc := '0';
write(oline, string'(" eff="));
write(oline, irxeff, right, 10);
write(oline, string'(" ("));
writeoct(oline, irxeff, right, 3);
write(oline, string'(")"));
elsif S2M_ENAESC='1' and RXDATA=c_serport_xesc then
doesc := '1';
irxval := '0';
write(oline, string'(" XESC seen"));
end if;
xseen := '0';
if S2M_ENAXON = '1' then
if RXDATA = c_serport_xon then
write(oline, string'(" XON seen"));
M2S_XONSEEN <= '1';
xseen := '1';
elsif RXDATA = c_serport_xoff then
write(oline, string'(" XOFF seen"));
M2S_XOFFSEEN <= '1';
xseen := '1';
end if;
end if;
if S2M_ACTIVE='1' and irxval='1' and xseen='0' then
if irxeff = irxdata then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL: expect="));
write(oline, irxdata, right, 10);
end if;
irxdata := slv(unsigned(irxdata) + 1);
bcnt := bcnt + 1;
end if;
writeline(output, oline);
dclk := 0;
end if;
if RXERR = '1' then
writetimestamp(oline, CLK_CYCLE, ": FAIL: RXERR='1'");
writeline(output, oline);
end if;
dclk := dclk + 1;
end loop;
end process proc_moni;
end sim;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity REP is port(
a: in std_logic;
z: out std_logic
);
end REP;
--
architecture REP of REP is
begin
z <= a;
end REP; |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Tue Jun 06 02:30:20 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
apply : in STD_LOGIC;
clk_100 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hsync : in STD_LOGIC;
pclk : in STD_LOGIC;
ready : out STD_LOGIC;
reset : in STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
state : out STD_LOGIC_VECTOR ( 1 downto 0 );
transform : in STD_LOGIC;
transform_led : out STD_LOGIC;
trigger : in STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=27,numReposBlks=27,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end component system_ov7670_controller_0_0;
component system_zed_hdmi_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
end component system_zed_hdmi_0_0;
component system_rgb565_to_rgb888_0_0 is
port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_rgb565_to_rgb888_0_0;
component system_vga_buffer_0_0 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_buffer_0_0;
component system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_0_0;
component system_vga_sync_ref_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_ref_0_0;
component system_debounce_0_0 is
port (
clk : in STD_LOGIC;
signal_in : in STD_LOGIC;
signal_out : out STD_LOGIC
);
end component system_debounce_0_0;
component system_ov7670_vga_0_0 is
port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_ov7670_vga_0_0;
component system_clock_splitter_0_0 is
port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end component system_clock_splitter_0_0;
component system_vga_buffer_1_1 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_buffer_1_1;
component system_vga_overlay_0_0 is
port (
clk : in STD_LOGIC;
rgb_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_overlay_0_0;
component system_rgb888_to_g8_0_0 is
port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component system_rgb888_to_g8_0_0;
component system_clk_wiz_0_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC
);
end component system_clk_wiz_0_0;
component system_clk_wiz_1_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC
);
end component system_clk_wiz_1_0;
component system_xlconstant_0_3 is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_xlconstant_0_3;
component system_vga_transform_0_1 is
port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
rot_m00 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m01 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m11 : in STD_LOGIC_VECTOR ( 15 downto 0 );
t_x : in STD_LOGIC_VECTOR ( 9 downto 0 );
t_y : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_transform_0_1;
component system_rgb888_to_g8_1_0 is
port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component system_rgb888_to_g8_1_0;
component system_vga_pll_0_0 is
port (
clk_100 : in STD_LOGIC;
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC
);
end component system_vga_pll_0_0;
component system_c_addsub_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 9 downto 0 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
S : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_c_addsub_0_0;
component system_vga_hessian_0_0 is
port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_vga_hessian_0_0;
component system_vga_hessian_1_0 is
port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_vga_hessian_1_0;
component system_vga_sync_reset_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_reset_0_0;
component system_vga_feature_transform_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
rst : in STD_LOGIC;
active : in STD_LOGIC;
vsync : in STD_LOGIC;
x_addr_0 : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_0 : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_addr_1 : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_1 : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
rot_m00 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m01 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m10 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m11 : out STD_LOGIC_VECTOR ( 15 downto 0 );
t_x : out STD_LOGIC_VECTOR ( 9 downto 0 );
t_y : out STD_LOGIC_VECTOR ( 9 downto 0 );
state : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component system_vga_feature_transform_0_0;
component system_buffer_register_0_0 is
port (
clk : in STD_LOGIC;
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_buffer_register_0_0;
component system_buffer_register_1_0 is
port (
clk : in STD_LOGIC;
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_buffer_register_1_0;
component system_util_ds_buf_0_0 is
port (
BUFG_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_O : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_util_ds_buf_0_0;
component system_util_ds_buf_1_0 is
port (
BUFG_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_O : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_util_ds_buf_1_0;
signal Net : STD_LOGIC;
signal Net1 : STD_LOGIC;
signal buffer_register_0_val_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffer_register_1_val_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal c_addsub_0_S : STD_LOGIC_VECTOR ( 9 downto 0 );
signal clk_100_1 : STD_LOGIC;
signal clk_wiz_0_clk_out1 : STD_LOGIC;
signal clk_wiz_1_clk_out1 : STD_LOGIC;
signal clock_splitter_0_clk_out : STD_LOGIC;
signal data_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal debounce_0_o : STD_LOGIC;
signal hsync_1 : STD_LOGIC;
signal inverter_0_x_not : STD_LOGIC;
signal ov7670_controller_0_config_finished : STD_LOGIC;
signal ov7670_controller_0_sioc : STD_LOGIC;
signal ov7670_vga_0_rgb : STD_LOGIC_VECTOR ( 15 downto 0 );
signal pclk_1 : STD_LOGIC;
signal reset_1 : STD_LOGIC;
signal rgb565_to_rgb888_0_rgb_888 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal rgb888_to_g8_0_g8 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rgb888_to_g8_1_g8 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal transform_1 : STD_LOGIC;
signal trigger_1 : STD_LOGIC;
signal twenty_u_dout : STD_LOGIC_VECTOR ( 9 downto 0 );
signal util_ds_buf_0_BUFG_O : STD_LOGIC_VECTOR ( 0 to 0 );
signal vga_buffer_0_data_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_buffer_1_data_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_feature_transform_0_rot_m00 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_feature_transform_0_rot_m01 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_feature_transform_0_rot_m10 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_feature_transform_0_rot_m11 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_feature_transform_0_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vga_feature_transform_0_t_x : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_feature_transform_0_t_y : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_hessian_0_hessian_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vga_hessian_1_hessian_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vga_overlay_0_rgb : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_pll_0_clk_12_5 : STD_LOGIC_VECTOR ( 0 to 0 );
signal vga_pll_0_clk_12_6 : STD_LOGIC;
signal vga_pll_0_clk_25 : STD_LOGIC;
signal vga_sync_ref_0_active : STD_LOGIC;
signal vga_sync_ref_0_start : STD_LOGIC;
signal vga_sync_ref_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_ref_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_reset_0_active : STD_LOGIC;
signal vga_sync_reset_0_hsync : STD_LOGIC;
signal vga_sync_reset_0_vsync : STD_LOGIC;
signal vga_sync_reset_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_reset_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_transform_0_x_addr_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_transform_0_y_addr_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vsync_1 : STD_LOGIC;
signal zed_hdmi_0_hdmi_clk : STD_LOGIC;
signal zed_hdmi_0_hdmi_d : STD_LOGIC_VECTOR ( 15 downto 0 );
signal zed_hdmi_0_hdmi_de : STD_LOGIC;
signal zed_hdmi_0_hdmi_hsync : STD_LOGIC;
signal zed_hdmi_0_hdmi_scl : STD_LOGIC;
signal zed_hdmi_0_hdmi_vsync : STD_LOGIC;
signal NLW_ov7670_controller_0_pwdn_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_reset_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_xclk_UNCONNECTED : STD_LOGIC;
signal NLW_vga_pll_0_clk_50_UNCONNECTED : STD_LOGIC;
signal NLW_vga_pll_0_clk_6_25_UNCONNECTED : STD_LOGIC;
begin
clk_100_1 <= clk_100;
data_1(7 downto 0) <= data(7 downto 0);
hdmi_clk <= zed_hdmi_0_hdmi_clk;
hdmi_d(15 downto 0) <= zed_hdmi_0_hdmi_d(15 downto 0);
hdmi_de <= zed_hdmi_0_hdmi_de;
hdmi_hsync <= zed_hdmi_0_hdmi_hsync;
hdmi_scl <= zed_hdmi_0_hdmi_scl;
hdmi_vsync <= zed_hdmi_0_hdmi_vsync;
hsync_1 <= hsync;
pclk_1 <= pclk;
ready <= ov7670_controller_0_config_finished;
reset_1 <= reset;
sioc <= ov7670_controller_0_sioc;
state(1 downto 0) <= vga_feature_transform_0_state(1 downto 0);
transform_1 <= transform;
transform_led <= transform_1;
trigger_1 <= trigger;
vsync_1 <= vsync;
xclk <= clk_wiz_0_clk_out1;
buffer_register_0: component system_buffer_register_0_0
port map (
clk => vga_pll_0_clk_12_5(0),
val_in(31 downto 0) => vga_hessian_0_hessian_out(31 downto 0),
val_out(31 downto 0) => buffer_register_0_val_out(31 downto 0)
);
buffer_register_1: component system_buffer_register_1_0
port map (
clk => vga_pll_0_clk_12_5(0),
val_in(31 downto 0) => vga_hessian_1_hessian_out(31 downto 0),
val_out(31 downto 0) => buffer_register_1_val_out(31 downto 0)
);
c_addsub_0: component system_c_addsub_0_0
port map (
A(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
B(9 downto 0) => twenty_u_dout(9 downto 0),
S(9 downto 0) => c_addsub_0_S(9 downto 0)
);
clk_wiz_0: component system_clk_wiz_0_0
port map (
clk_in1 => clk_100_1,
clk_out1 => clk_wiz_0_clk_out1
);
clk_wiz_1: component system_clk_wiz_1_0
port map (
clk_in1 => clk_100_1,
clk_out1 => clk_wiz_1_clk_out1
);
clock_splitter_0: component system_clock_splitter_0_0
port map (
clk_in => pclk_1,
clk_out => clock_splitter_0_clk_out,
latch_edge => vsync_1
);
debounce_0: component system_debounce_0_0
port map (
clk => util_ds_buf_0_BUFG_O(0),
signal_in => reset_1,
signal_out => debounce_0_o
);
inverter_0: component system_inverter_0_0
port map (
x => vga_sync_ref_0_start,
x_not => inverter_0_x_not
);
ov7670_controller_0: component system_ov7670_controller_0_0
port map (
clk => util_ds_buf_0_BUFG_O(0),
config_finished => ov7670_controller_0_config_finished,
pwdn => NLW_ov7670_controller_0_pwdn_UNCONNECTED,
resend => debounce_0_o,
reset => NLW_ov7670_controller_0_reset_UNCONNECTED,
sioc => ov7670_controller_0_sioc,
siod => siod,
xclk => NLW_ov7670_controller_0_xclk_UNCONNECTED
);
ov7670_vga_0: component system_ov7670_vga_0_0
port map (
active => vga_sync_ref_0_active,
clk_x2 => pclk_1,
data(7 downto 0) => data_1(7 downto 0),
rgb(15 downto 0) => ov7670_vga_0_rgb(15 downto 0)
);
rgb565_to_rgb888_0: component system_rgb565_to_rgb888_0_0
port map (
clk => clock_splitter_0_clk_out,
rgb_565(15 downto 0) => ov7670_vga_0_rgb(15 downto 0),
rgb_888(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0)
);
rgb888_to_g8_0: component system_rgb888_to_g8_0_0
port map (
clk => vga_pll_0_clk_12_5(0),
g8(7 downto 0) => rgb888_to_g8_0_g8(7 downto 0),
rgb888(23 downto 0) => vga_buffer_0_data_r(23 downto 0)
);
rgb888_to_g8_1: component system_rgb888_to_g8_1_0
port map (
clk => vga_pll_0_clk_12_5(0),
g8(7 downto 0) => rgb888_to_g8_1_g8(7 downto 0),
rgb888(23 downto 0) => vga_buffer_1_data_r(23 downto 0)
);
twenty_u: component system_xlconstant_0_3
port map (
dout(9 downto 0) => twenty_u_dout(9 downto 0)
);
util_ds_buf_0: component system_util_ds_buf_0_0
port map (
BUFG_I(0) => vga_pll_0_clk_25,
BUFG_O(0) => util_ds_buf_0_BUFG_O(0)
);
util_ds_buf_1: component system_util_ds_buf_1_0
port map (
BUFG_I(0) => vga_pll_0_clk_12_6,
BUFG_O(0) => vga_pll_0_clk_12_5(0)
);
vga_buffer_0: component system_vga_buffer_0_0
port map (
clk_r => vga_pll_0_clk_12_5(0),
clk_w => clock_splitter_0_clk_out,
data_r(23 downto 0) => vga_buffer_0_data_r(23 downto 0),
data_w(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0),
wen => vga_sync_ref_0_active,
x_addr_r(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_w(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
y_addr_r(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_w(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_buffer_1: component system_vga_buffer_1_1
port map (
clk_r => vga_pll_0_clk_12_5(0),
clk_w => clock_splitter_0_clk_out,
data_r(23 downto 0) => vga_buffer_1_data_r(23 downto 0),
data_w(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0),
wen => vga_sync_ref_0_active,
x_addr_r(9 downto 0) => vga_transform_0_x_addr_out(9 downto 0),
x_addr_w(9 downto 0) => c_addsub_0_S(9 downto 0),
y_addr_r(9 downto 0) => vga_transform_0_y_addr_out(9 downto 0),
y_addr_w(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_feature_transform_0: component system_vga_feature_transform_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_5(0),
clk_x2 => util_ds_buf_0_BUFG_O(0),
hessian_0(31 downto 0) => buffer_register_0_val_out(31 downto 0),
hessian_1(31 downto 0) => buffer_register_1_val_out(31 downto 0),
rot_m00(15 downto 0) => vga_feature_transform_0_rot_m00(15 downto 0),
rot_m01(15 downto 0) => vga_feature_transform_0_rot_m01(15 downto 0),
rot_m10(15 downto 0) => vga_feature_transform_0_rot_m10(15 downto 0),
rot_m11(15 downto 0) => vga_feature_transform_0_rot_m11(15 downto 0),
rst => ov7670_controller_0_config_finished,
state(1 downto 0) => vga_feature_transform_0_state(1 downto 0),
t_x(9 downto 0) => vga_feature_transform_0_t_x(9 downto 0),
t_y(9 downto 0) => vga_feature_transform_0_t_y(9 downto 0),
vsync => vsync_1,
x_addr_0(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_1(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
y_addr_0(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_1(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
vga_hessian_0: component system_vga_hessian_0_0
port map (
active => vga_sync_reset_0_active,
clk_x16 => clk_wiz_1_clk_out1,
g_in(7 downto 0) => rgb888_to_g8_0_g8(7 downto 0),
hessian_out(31 downto 0) => vga_hessian_0_hessian_out(31 downto 0),
rst => vga_sync_reset_0_vsync,
x_addr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
y_addr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
vga_hessian_1: component system_vga_hessian_1_0
port map (
active => vga_sync_reset_0_active,
clk_x16 => clk_wiz_1_clk_out1,
g_in(7 downto 0) => rgb888_to_g8_1_g8(7 downto 0),
hessian_out(31 downto 0) => vga_hessian_1_hessian_out(31 downto 0),
rst => vga_sync_reset_0_vsync,
x_addr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
y_addr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
vga_overlay_0: component system_vga_overlay_0_0
port map (
clk => vga_pll_0_clk_12_5(0),
rgb(23 downto 0) => vga_overlay_0_rgb(23 downto 0),
rgb_0(23 downto 0) => vga_buffer_0_data_r(23 downto 0),
rgb_1(23 downto 0) => vga_buffer_1_data_r(23 downto 0)
);
vga_pll_0: component system_vga_pll_0_0
port map (
clk_100 => clk_100_1,
clk_12_5 => vga_pll_0_clk_12_6,
clk_25 => vga_pll_0_clk_25,
clk_50 => NLW_vga_pll_0_clk_50_UNCONNECTED,
clk_6_25 => NLW_vga_pll_0_clk_6_25_UNCONNECTED
);
vga_sync_ref_0: component system_vga_sync_ref_0_0
port map (
active => vga_sync_ref_0_active,
clk => clock_splitter_0_clk_out,
hsync => hsync_1,
rst => ov7670_controller_0_config_finished,
start => vga_sync_ref_0_start,
vsync => vsync_1,
xaddr(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_sync_reset_0: component system_vga_sync_reset_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_5(0),
hsync => vga_sync_reset_0_hsync,
rst => inverter_0_x_not,
vsync => vga_sync_reset_0_vsync,
xaddr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
vga_transform_0: component system_vga_transform_0_1
port map (
clk => vga_pll_0_clk_12_5(0),
enable => transform_1,
rot_m00(15 downto 0) => vga_feature_transform_0_rot_m00(15 downto 0),
rot_m01(15 downto 0) => vga_feature_transform_0_rot_m01(15 downto 0),
rot_m10(15 downto 0) => vga_feature_transform_0_rot_m10(15 downto 0),
rot_m11(15 downto 0) => vga_feature_transform_0_rot_m11(15 downto 0),
t_x(9 downto 0) => vga_feature_transform_0_t_x(9 downto 0),
t_y(9 downto 0) => vga_feature_transform_0_t_y(9 downto 0),
x_addr_in(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_out(9 downto 0) => vga_transform_0_x_addr_out(9 downto 0),
y_addr_in(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_out(9 downto 0) => vga_transform_0_y_addr_out(9 downto 0)
);
zed_hdmi_0: component system_zed_hdmi_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_5(0),
clk_100 => clk_100_1,
clk_x2 => util_ds_buf_0_BUFG_O(0),
hdmi_clk => zed_hdmi_0_hdmi_clk,
hdmi_d(15 downto 0) => zed_hdmi_0_hdmi_d(15 downto 0),
hdmi_de => zed_hdmi_0_hdmi_de,
hdmi_hsync => zed_hdmi_0_hdmi_hsync,
hdmi_scl => zed_hdmi_0_hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => zed_hdmi_0_hdmi_vsync,
hsync => vga_sync_reset_0_hsync,
rgb888(23 downto 0) => vga_overlay_0_rgb(23 downto 0),
vsync => vga_sync_reset_0_vsync
);
end STRUCTURE;
|
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 13:41:21 06/19/2016
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY rotary_tb IS
END rotary_tb;
ARCHITECTURE behavior OF rotary_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT rotary_dec
PORT(
clk : IN std_logic;
A : IN std_logic;
B : IN std_logic;
btn : IN std_logic;
btn_deb : OUT std_logic;
enc_right : OUT std_logic;
enc_ce : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal A : std_logic := '0';
signal B : std_logic := '0';
signal btn : std_logic := '0';
--Outputs
signal btn_deb : std_logic;
signal enc_right : std_logic;
signal enc_ce : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: rotary_dec PORT MAP (
clk => clk,
A => A,
B => B,
btn => btn,
btn_deb => btn_deb,
enc_right => enc_right,
enc_ce => enc_ce
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FLOW is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
ROW_A : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_B : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_C : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_D : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_E : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_W : IN STD_LOGIC_VECTOR(9 downto 0);
HAZARD : IN STD_LOGIC;
EQUALITY : OUT STD_LOGIC;
ADDRESS_A : OUT STD_LOGIC_VECTOR(9 downto 0);
ADDRESS_B : OUT STD_LOGIC_VECTOR(9 downto 0);
SEL_VECTOR : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
WREN_A : OUT STD_LOGIC;
WREN_B : OUT STD_LOGIC
);
end;
architecture flow of FLOW is
component SELECTOR
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
EQUALITY : OUT STD_LOGIC;
sel_A_0 : OUT STD_LOGIC;
sel_B_0 : OUT STD_LOGIC;
sel_C_0 : OUT STD_LOGIC;
sel_D_0 : OUT STD_LOGIC;
sel_E_0 : OUT STD_LOGIC;
sel_W_0 : OUT STD_LOGIC;
sel_A_1 : OUT STD_LOGIC;
sel_B_1 : OUT STD_LOGIC;
sel_C_1 : OUT STD_LOGIC;
sel_D_1 : OUT STD_LOGIC;
sel_E_1 : OUT STD_LOGIC;
sel_W_1 : OUT STD_LOGIC
);
end component;
component tristate
PORT(
my_in : in std_logic_vector(9 downto 0);
sel : in std_logic;
my_out : out std_logic_vector(9 downto 0)
);
end component;
signal sel_a0 : std_logic;
signal sel_b0 : std_logic;
signal sel_c0 : std_logic;
signal sel_d0 : std_logic;
signal sel_e0 : std_logic;
signal sel_w0 : std_logic;
signal sel_a1 : std_logic;
signal sel_b1 : std_logic;
signal sel_c1 : std_logic;
signal sel_d1 : std_logic;
signal sel_e1 : std_logic;
signal sel_w1 : std_logic;
begin
select_address : SELECTOR PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE,
EQUALITY => EQUALITY,
SEL_A_0 => sel_a0,
SEL_B_0 => sel_b0,
SEL_C_0 => sel_c0,
SEL_D_0 => sel_d0,
SEL_E_0 => sel_e0,
SEL_W_0 => sel_w0,
SEL_A_1 => sel_a1,
SEL_B_1 => sel_b1,
SEL_C_1 => sel_c1,
SEL_D_1 => sel_d1,
SEL_E_1 => sel_e1,
SEL_W_1 => sel_w1
);
TRI_0_PORT_A : tristate PORT MAP (
my_in => ROW_A,
sel => sel_a0,
my_out => ADDRESS_A
);
TRI_1_PORT_A : tristate PORT MAP (
my_in => ROW_B,
sel => sel_b0,
my_out => ADDRESS_A
);
TRI_2_PORT_A : tristate PORT MAP (
my_in => ROW_C,
sel => sel_c0,
my_out => ADDRESS_A
);
TRI_3_PORT_A : tristate PORT MAP (
my_in => ROW_D,
sel => sel_d0,
my_out => ADDRESS_A
);
TRI_4_PORT_A : tristate PORT MAP (
my_in => ROW_E,
sel => sel_e0,
my_out => ADDRESS_A
);
TRI_5_PORT_A : tristate PORT MAP (
my_in => ROW_W,
sel => sel_w0,
my_out => ADDRESS_A
);
TRI_0_PORT_B : tristate PORT MAP (
my_in => ROW_A,
sel => sel_a1,
my_out => ADDRESS_B
);
TRI_1_PORT_B : tristate PORT MAP (
my_in => ROW_B,
sel => sel_b1,
my_out => ADDRESS_B
);
TRI_2_PORT_B : tristate PORT MAP (
my_in => ROW_C,
sel => sel_c1,
my_out => ADDRESS_B
);
TRI_3_PORT_B : tristate PORT MAP (
my_in => ROW_D,
sel => sel_d1,
my_out => ADDRESS_B
);
TRI_4_PORT_B : tristate PORT MAP (
my_in => ROW_E,
sel => sel_e1,
my_out => ADDRESS_B
);
TRI_5_PORT_B : tristate PORT MAP (
my_in => ROW_W,
sel => sel_w1,
my_out => ADDRESS_B
);
WREN_A <= '0';
process (HAZARD, OPCODE) begin --addred this if block
if (HAZARD = '1') then
WREN_B <= '0';
else
WREN_B <= OPCODE(0); --used to be just this line
end if;
end process;
SEL_VECTOR <= sel_a0 & sel_a1 & sel_b0 & sel_b1 & sel_c0 & sel_c1 & sel_d0 & sel_d1 & sel_e0 & sel_e1;
end; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FLOW is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
ROW_A : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_B : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_C : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_D : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_E : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_W : IN STD_LOGIC_VECTOR(9 downto 0);
HAZARD : IN STD_LOGIC;
EQUALITY : OUT STD_LOGIC;
ADDRESS_A : OUT STD_LOGIC_VECTOR(9 downto 0);
ADDRESS_B : OUT STD_LOGIC_VECTOR(9 downto 0);
SEL_VECTOR : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
WREN_A : OUT STD_LOGIC;
WREN_B : OUT STD_LOGIC
);
end;
architecture flow of FLOW is
component SELECTOR
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
EQUALITY : OUT STD_LOGIC;
sel_A_0 : OUT STD_LOGIC;
sel_B_0 : OUT STD_LOGIC;
sel_C_0 : OUT STD_LOGIC;
sel_D_0 : OUT STD_LOGIC;
sel_E_0 : OUT STD_LOGIC;
sel_W_0 : OUT STD_LOGIC;
sel_A_1 : OUT STD_LOGIC;
sel_B_1 : OUT STD_LOGIC;
sel_C_1 : OUT STD_LOGIC;
sel_D_1 : OUT STD_LOGIC;
sel_E_1 : OUT STD_LOGIC;
sel_W_1 : OUT STD_LOGIC
);
end component;
component tristate
PORT(
my_in : in std_logic_vector(9 downto 0);
sel : in std_logic;
my_out : out std_logic_vector(9 downto 0)
);
end component;
signal sel_a0 : std_logic;
signal sel_b0 : std_logic;
signal sel_c0 : std_logic;
signal sel_d0 : std_logic;
signal sel_e0 : std_logic;
signal sel_w0 : std_logic;
signal sel_a1 : std_logic;
signal sel_b1 : std_logic;
signal sel_c1 : std_logic;
signal sel_d1 : std_logic;
signal sel_e1 : std_logic;
signal sel_w1 : std_logic;
begin
select_address : SELECTOR PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE,
EQUALITY => EQUALITY,
SEL_A_0 => sel_a0,
SEL_B_0 => sel_b0,
SEL_C_0 => sel_c0,
SEL_D_0 => sel_d0,
SEL_E_0 => sel_e0,
SEL_W_0 => sel_w0,
SEL_A_1 => sel_a1,
SEL_B_1 => sel_b1,
SEL_C_1 => sel_c1,
SEL_D_1 => sel_d1,
SEL_E_1 => sel_e1,
SEL_W_1 => sel_w1
);
TRI_0_PORT_A : tristate PORT MAP (
my_in => ROW_A,
sel => sel_a0,
my_out => ADDRESS_A
);
TRI_1_PORT_A : tristate PORT MAP (
my_in => ROW_B,
sel => sel_b0,
my_out => ADDRESS_A
);
TRI_2_PORT_A : tristate PORT MAP (
my_in => ROW_C,
sel => sel_c0,
my_out => ADDRESS_A
);
TRI_3_PORT_A : tristate PORT MAP (
my_in => ROW_D,
sel => sel_d0,
my_out => ADDRESS_A
);
TRI_4_PORT_A : tristate PORT MAP (
my_in => ROW_E,
sel => sel_e0,
my_out => ADDRESS_A
);
TRI_5_PORT_A : tristate PORT MAP (
my_in => ROW_W,
sel => sel_w0,
my_out => ADDRESS_A
);
TRI_0_PORT_B : tristate PORT MAP (
my_in => ROW_A,
sel => sel_a1,
my_out => ADDRESS_B
);
TRI_1_PORT_B : tristate PORT MAP (
my_in => ROW_B,
sel => sel_b1,
my_out => ADDRESS_B
);
TRI_2_PORT_B : tristate PORT MAP (
my_in => ROW_C,
sel => sel_c1,
my_out => ADDRESS_B
);
TRI_3_PORT_B : tristate PORT MAP (
my_in => ROW_D,
sel => sel_d1,
my_out => ADDRESS_B
);
TRI_4_PORT_B : tristate PORT MAP (
my_in => ROW_E,
sel => sel_e1,
my_out => ADDRESS_B
);
TRI_5_PORT_B : tristate PORT MAP (
my_in => ROW_W,
sel => sel_w1,
my_out => ADDRESS_B
);
WREN_A <= '0';
process (HAZARD, OPCODE) begin --addred this if block
if (HAZARD = '1') then
WREN_B <= '0';
else
WREN_B <= OPCODE(0); --used to be just this line
end if;
end process;
SEL_VECTOR <= sel_a0 & sel_a1 & sel_b0 & sel_b1 & sel_c0 & sel_c1 & sel_d0 & sel_d1 & sel_e0 & sel_e1;
end; |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_09.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
-- not in book
entity alarm_clock is
end entity alarm_clock;
-- end not in book
architecture top_level of alarm_clock is
--use work.counter_types.digit;
use work.counter_types.all;
signal reset_to_midnight, seconds_clk : bit;
signal seconds_units, seconds_tens : digit;
-- . . .
begin
seconds : configuration work.counter_down_to_gate_level
port map ( clk => seconds_clk, clr => reset_to_midnight,
q0 => seconds_units, q1 => seconds_tens );
-- . . .
-- not in book
clk_gen : seconds_clk <= not seconds_clk after 20 ns;
clr_gen : reset_to_midnight <= '1' after 95 ns,
'0' after 135 ns;
-- end not in book;
end architecture top_level;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_09.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
-- not in book
entity alarm_clock is
end entity alarm_clock;
-- end not in book
architecture top_level of alarm_clock is
--use work.counter_types.digit;
use work.counter_types.all;
signal reset_to_midnight, seconds_clk : bit;
signal seconds_units, seconds_tens : digit;
-- . . .
begin
seconds : configuration work.counter_down_to_gate_level
port map ( clk => seconds_clk, clr => reset_to_midnight,
q0 => seconds_units, q1 => seconds_tens );
-- . . .
-- not in book
clk_gen : seconds_clk <= not seconds_clk after 20 ns;
clr_gen : reset_to_midnight <= '1' after 95 ns,
'0' after 135 ns;
-- end not in book;
end architecture top_level;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_09.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
-- not in book
entity alarm_clock is
end entity alarm_clock;
-- end not in book
architecture top_level of alarm_clock is
--use work.counter_types.digit;
use work.counter_types.all;
signal reset_to_midnight, seconds_clk : bit;
signal seconds_units, seconds_tens : digit;
-- . . .
begin
seconds : configuration work.counter_down_to_gate_level
port map ( clk => seconds_clk, clr => reset_to_midnight,
q0 => seconds_units, q1 => seconds_tens );
-- . . .
-- not in book
clk_gen : seconds_clk <= not seconds_clk after 20 ns;
clr_gen : reset_to_midnight <= '1' after 95 ns,
'0' after 135 ns;
-- end not in book;
end architecture top_level;
|
library ieee;
use ieee.std_logic_1164.all;
package eclipse_components is
component RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end component;
component RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end component;
component RAM512X4_25um
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end component;
component RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end component;
end eclipse_components;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity eclipse_sim_ram is
generic (abits : integer := 8; dbits : integer := 16);
port (WA, RA : in std_logic_vector (abits-1 downto 0);
WD : in std_logic_vector (dbits-1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (dbits-1 downto 0) );
end;
architecture arch of eclipse_sim_ram is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
begin
rp : process(rclk, wclk, re, ra, asyncrd)
variable rfd : dregtype;
begin
if rising_edge(wclk) then
if we = '1' then rfd(conv_integer(wa)) := WD; end if;
end if;
if (re = '1') and (ASYNCRD = '1') then
RD <= rfd(conv_integer(ra));
end if;
if rising_edge(rclk) and (re = '1') and (ASYNCRD = '0') then
RD <= rfd(conv_integer(ra));
end if;
end process;
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end RAM128X18_25um;
architecture arch of RAM128X18_25um is
begin
x : entity work.eclipse_sim_ram generic map (7, 18)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end RAM256X9_25um;
architecture arch of RAM256X9_25um is
begin
x : entity work.eclipse_sim_ram generic map (8, 9)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM512X4_25um is
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end RAM512X4_25um;
architecture arch of RAM512X4_25um is
begin
x : entity work.eclipse_sim_ram generic map (9, 4)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end RAM1024X2_25um;
architecture arch of RAM1024X2_25um is
begin
x : entity work.eclipse_sim_ram generic map (10, 2)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
|
library ieee;
use ieee.std_logic_1164.all;
package eclipse_components is
component RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end component;
component RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end component;
component RAM512X4_25um
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end component;
component RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end component;
end eclipse_components;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity eclipse_sim_ram is
generic (abits : integer := 8; dbits : integer := 16);
port (WA, RA : in std_logic_vector (abits-1 downto 0);
WD : in std_logic_vector (dbits-1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (dbits-1 downto 0) );
end;
architecture arch of eclipse_sim_ram is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
begin
rp : process(rclk, wclk, re, ra, asyncrd)
variable rfd : dregtype;
begin
if rising_edge(wclk) then
if we = '1' then rfd(conv_integer(wa)) := WD; end if;
end if;
if (re = '1') and (ASYNCRD = '1') then
RD <= rfd(conv_integer(ra));
end if;
if rising_edge(rclk) and (re = '1') and (ASYNCRD = '0') then
RD <= rfd(conv_integer(ra));
end if;
end process;
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end RAM128X18_25um;
architecture arch of RAM128X18_25um is
begin
x : entity work.eclipse_sim_ram generic map (7, 18)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end RAM256X9_25um;
architecture arch of RAM256X9_25um is
begin
x : entity work.eclipse_sim_ram generic map (8, 9)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM512X4_25um is
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end RAM512X4_25um;
architecture arch of RAM512X4_25um is
begin
x : entity work.eclipse_sim_ram generic map (9, 4)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end RAM1024X2_25um;
architecture arch of RAM1024X2_25um is
begin
x : entity work.eclipse_sim_ram generic map (10, 2)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
|
library ieee;
use ieee.std_logic_1164.all;
package eclipse_components is
component RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end component;
component RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end component;
component RAM512X4_25um
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end component;
component RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end component;
end eclipse_components;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity eclipse_sim_ram is
generic (abits : integer := 8; dbits : integer := 16);
port (WA, RA : in std_logic_vector (abits-1 downto 0);
WD : in std_logic_vector (dbits-1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (dbits-1 downto 0) );
end;
architecture arch of eclipse_sim_ram is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
begin
rp : process(rclk, wclk, re, ra, asyncrd)
variable rfd : dregtype;
begin
if rising_edge(wclk) then
if we = '1' then rfd(conv_integer(wa)) := WD; end if;
end if;
if (re = '1') and (ASYNCRD = '1') then
RD <= rfd(conv_integer(ra));
end if;
if rising_edge(rclk) and (re = '1') and (ASYNCRD = '0') then
RD <= rfd(conv_integer(ra));
end if;
end process;
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end RAM128X18_25um;
architecture arch of RAM128X18_25um is
begin
x : entity work.eclipse_sim_ram generic map (7, 18)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end RAM256X9_25um;
architecture arch of RAM256X9_25um is
begin
x : entity work.eclipse_sim_ram generic map (8, 9)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM512X4_25um is
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end RAM512X4_25um;
architecture arch of RAM512X4_25um is
begin
x : entity work.eclipse_sim_ram generic map (9, 4)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end RAM1024X2_25um;
architecture arch of RAM1024X2_25um is
begin
x : entity work.eclipse_sim_ram generic map (10, 2)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
|
library ieee;
use ieee.std_logic_1164.all;
package eclipse_components is
component RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end component;
component RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end component;
component RAM512X4_25um
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end component;
component RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end component;
end eclipse_components;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity eclipse_sim_ram is
generic (abits : integer := 8; dbits : integer := 16);
port (WA, RA : in std_logic_vector (abits-1 downto 0);
WD : in std_logic_vector (dbits-1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (dbits-1 downto 0) );
end;
architecture arch of eclipse_sim_ram is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
begin
rp : process(rclk, wclk, re, ra, asyncrd)
variable rfd : dregtype;
begin
if rising_edge(wclk) then
if we = '1' then rfd(conv_integer(wa)) := WD; end if;
end if;
if (re = '1') and (ASYNCRD = '1') then
RD <= rfd(conv_integer(ra));
end if;
if rising_edge(rclk) and (re = '1') and (ASYNCRD = '0') then
RD <= rfd(conv_integer(ra));
end if;
end process;
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end RAM128X18_25um;
architecture arch of RAM128X18_25um is
begin
x : entity work.eclipse_sim_ram generic map (7, 18)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end RAM256X9_25um;
architecture arch of RAM256X9_25um is
begin
x : entity work.eclipse_sim_ram generic map (8, 9)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM512X4_25um is
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end RAM512X4_25um;
architecture arch of RAM512X4_25um is
begin
x : entity work.eclipse_sim_ram generic map (9, 4)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end RAM1024X2_25um;
architecture arch of RAM1024X2_25um is
begin
x : entity work.eclipse_sim_ram generic map (10, 2)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
|
library ieee;
use ieee.std_logic_1164.all;
package eclipse_components is
component RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end component;
component RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end component;
component RAM512X4_25um
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end component;
component RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end component;
end eclipse_components;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity eclipse_sim_ram is
generic (abits : integer := 8; dbits : integer := 16);
port (WA, RA : in std_logic_vector (abits-1 downto 0);
WD : in std_logic_vector (dbits-1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (dbits-1 downto 0) );
end;
architecture arch of eclipse_sim_ram is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
begin
rp : process(rclk, wclk, re, ra, asyncrd)
variable rfd : dregtype;
begin
if rising_edge(wclk) then
if we = '1' then rfd(conv_integer(wa)) := WD; end if;
end if;
if (re = '1') and (ASYNCRD = '1') then
RD <= rfd(conv_integer(ra));
end if;
if rising_edge(rclk) and (re = '1') and (ASYNCRD = '0') then
RD <= rfd(conv_integer(ra));
end if;
end process;
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end RAM128X18_25um;
architecture arch of RAM128X18_25um is
begin
x : entity work.eclipse_sim_ram generic map (7, 18)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end RAM256X9_25um;
architecture arch of RAM256X9_25um is
begin
x : entity work.eclipse_sim_ram generic map (8, 9)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM512X4_25um is
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end RAM512X4_25um;
architecture arch of RAM512X4_25um is
begin
x : entity work.eclipse_sim_ram generic map (9, 4)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end RAM1024X2_25um;
architecture arch of RAM1024X2_25um is
begin
x : entity work.eclipse_sim_ram generic map (10, 2)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
use work.PIC_pkg.all;
use work.RS232_test.all;
entity PICtop_tb is
end PICtop_tb;
architecture TestBench of PICtop_tb is
component PICtop
port (
Reset : in std_logic;
Clk : in std_logic;
RS232_RX : in std_logic;
RS232_TX : out std_logic;
switches : out std_logic_vector(7 downto 0);
Temp_L : out std_logic_vector(6 downto 0);
Temp_H : out std_logic_vector(6 downto 0));
end component;
-----------------------------------------------------------------------------
-- Internal signals
-----------------------------------------------------------------------------
signal Reset : std_logic;
signal Clk : std_logic;
signal RS232_RX : std_logic;
signal RS232_TX : std_logic;
signal switches : std_logic_vector(7 downto 0);
signal Temp_L : std_logic_vector(6 downto 0);
signal Temp_H : std_logic_vector(6 downto 0);
begin -- TestBench
UUT: PICtop
port map (
Reset => Reset,
Clk => Clk,
RS232_RX => RS232_RX,
RS232_TX => RS232_TX,
switches => switches,
Temp_L => Temp_L,
Temp_H => Temp_H);
-----------------------------------------------------------------------------
-- Reset & clock generator
-----------------------------------------------------------------------------
Reset <= '0', '1' after 75 ns;
p_clk : PROCESS
BEGIN
clk <= '1', '0' after 25 ns;
wait for 50 ns;
END PROCESS;
-------------------------------------------------------------------------------
-- Sending some stuff through RS232 port
-------------------------------------------------------------------------------
SEND_STUFF : process
begin
RS232_RX <= '1';
wait for 40 us;
Transmit(RS232_RX, X"49");
wait for 40 us;
Transmit(RS232_RX, X"34");
wait for 40 us;
Transmit(RS232_RX, X"31");
wait;
end process SEND_STUFF;
end TestBench;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:26:46 02/24/2015
-- Design Name:
-- Module Name: rc_shr - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rc_shr is
port(clk : in std_logic;
rst : in std_logic;
rc_in : in std_logic_vector(407 downto 0);
rc_out : out std_logic_vector(7 downto 0));
end rc_shr;
architecture Behavioral of rc_shr is
signal sh_reg : std_logic_vector(407 downto 0);
begin
pr_shr: process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
sh_reg <= rc_in;
else
sh_reg <= sh_reg(399 downto 0) & sh_reg(407 downto 400);
end if;
end if;
end process;
rc_out <= sh_reg(407 downto 400);
end Behavioral;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/TWDLMULT_SDNF1_3_block6.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLMULT_SDNF1_3_block6
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLMULT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TWDLMULT_SDNF1_3_block6 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_14_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_14_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_16_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_16_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_vld : IN std_logic;
twdl_3_15_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_15_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_16_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_16_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_16_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_15_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_15_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_16_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_16_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_15_vld : OUT std_logic
);
END TWDLMULT_SDNF1_3_block6;
ARCHITECTURE rtl OF TWDLMULT_SDNF1_3_block6 IS
-- Component Declarations
COMPONENT Complex3Multiply_block9
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din1_re_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din1_im_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din1_vld_dly3 : IN std_logic;
twdl_3_15_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_15_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_15_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_15_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin1_vld : OUT std_logic
);
END COMPONENT;
COMPONENT Complex3Multiply_block10
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din2_re_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din2_im_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
di2_vld_dly3 : IN std_logic;
twdl_3_16_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_16_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_16_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_16_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin2_vld : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Complex3Multiply_block9
USE ENTITY work.Complex3Multiply_block9(rtl);
FOR ALL : Complex3Multiply_block10
USE ENTITY work.Complex3Multiply_block10(rtl);
-- Signals
SIGNAL dout_14_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_14_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_vld_dly1 : std_logic;
SIGNAL din1_vld_dly2 : std_logic;
SIGNAL din1_vld_dly3 : std_logic;
SIGNAL twdlXdin_15_re_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
SIGNAL twdlXdin_15_im_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
SIGNAL twdlXdin1_vld : std_logic;
SIGNAL dout_16_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_16_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL di2_vld_dly1 : std_logic;
SIGNAL di2_vld_dly2 : std_logic;
SIGNAL di2_vld_dly3 : std_logic;
SIGNAL twdlXdin_16_re_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
SIGNAL twdlXdin_16_im_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
BEGIN
u_MUL3_1 : Complex3Multiply_block9
PORT MAP( clk => clk,
reset => reset,
enb => enb,
din1_re_dly3 => std_logic_vector(din1_re_dly3), -- sfix17
din1_im_dly3 => std_logic_vector(din1_im_dly3), -- sfix17
din1_vld_dly3 => din1_vld_dly3,
twdl_3_15_re => twdl_3_15_re, -- sfix17_En15
twdl_3_15_im => twdl_3_15_im, -- sfix17_En15
softReset => softReset,
twdlXdin_15_re => twdlXdin_15_re_tmp, -- sfix17
twdlXdin_15_im => twdlXdin_15_im_tmp, -- sfix17
twdlXdin1_vld => twdlXdin1_vld
);
u_MUL3_2 : Complex3Multiply_block10
PORT MAP( clk => clk,
reset => reset,
enb => enb,
din2_re_dly3 => std_logic_vector(din2_re_dly3), -- sfix17
din2_im_dly3 => std_logic_vector(din2_im_dly3), -- sfix17
di2_vld_dly3 => di2_vld_dly3,
twdl_3_16_re => twdl_3_16_re, -- sfix17_En15
twdl_3_16_im => twdl_3_16_im, -- sfix17_En15
softReset => softReset,
twdlXdin_16_re => twdlXdin_16_re_tmp, -- sfix17
twdlXdin_16_im => twdlXdin_16_im_tmp, -- sfix17
twdlXdin2_vld => twdlXdin_15_vld
);
dout_14_re_signed <= signed(dout_14_re);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly1 <= dout_14_re_signed;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly2 <= din1_re_dly1;
END IF;
END IF;
END PROCESS intdelay_1_process;
dout_14_im_signed <= signed(dout_14_im);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly1 <= dout_14_im_signed;
END IF;
END IF;
END PROCESS intdelay_2_process;
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly2 <= din1_im_dly1;
END IF;
END IF;
END PROCESS intdelay_3_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly3 <= din1_re_dly2;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly3 <= din1_im_dly2;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_vld_dly2 <= din1_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_7_process;
intdelay_8_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_vld_dly3 <= din1_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_8_process;
dout_16_re_signed <= signed(dout_16_re);
intdelay_9_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly1 <= dout_16_re_signed;
END IF;
END IF;
END PROCESS intdelay_9_process;
intdelay_10_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly2 <= din2_re_dly1;
END IF;
END IF;
END PROCESS intdelay_10_process;
dout_16_im_signed <= signed(dout_16_im);
intdelay_11_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly1 <= dout_16_im_signed;
END IF;
END IF;
END PROCESS intdelay_11_process;
intdelay_12_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly2 <= din2_im_dly1;
END IF;
END IF;
END PROCESS intdelay_12_process;
intdelay_13_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly3 <= din2_re_dly2;
END IF;
END IF;
END PROCESS intdelay_13_process;
intdelay_14_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly3 <= din2_im_dly2;
END IF;
END IF;
END PROCESS intdelay_14_process;
intdelay_15_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_15_process;
intdelay_16_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly2 <= di2_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_16_process;
intdelay_17_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly3 <= di2_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_17_process;
twdlXdin_15_re <= twdlXdin_15_re_tmp;
twdlXdin_15_im <= twdlXdin_15_im_tmp;
twdlXdin_16_re <= twdlXdin_16_re_tmp;
twdlXdin_16_im <= twdlXdin_16_im_tmp;
END rtl;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:54:25 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_ov7670_vga_1_0 -prefix
-- system_ov7670_vga_1_0_ system_ov7670_vga_0_0_sim_netlist.vhdl
-- Design : system_ov7670_vga_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_1_0_ov7670_vga is
port (
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 );
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end system_ov7670_vga_1_0_ov7670_vga;
architecture STRUCTURE of system_ov7670_vga_1_0_ov7670_vga is
signal cycle : STD_LOGIC;
signal p_0_in0 : STD_LOGIC;
begin
cycle_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => pclk,
CE => '1',
D => p_0_in0,
Q => cycle,
R => '0'
);
\rgb[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => cycle,
O => p_0_in0
);
\rgb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(0),
Q => rgb(0),
R => '0'
);
\rgb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(2),
Q => rgb(10),
R => '0'
);
\rgb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(3),
Q => rgb(11),
R => '0'
);
\rgb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(4),
Q => rgb(12),
R => '0'
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(5),
Q => rgb(13),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(6),
Q => rgb(14),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(7),
Q => rgb(15),
R => '0'
);
\rgb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(1),
Q => rgb(1),
R => '0'
);
\rgb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(2),
Q => rgb(2),
R => '0'
);
\rgb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(3),
Q => rgb(3),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(4),
Q => rgb(4),
R => '0'
);
\rgb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(5),
Q => rgb(5),
R => '0'
);
\rgb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(6),
Q => rgb(6),
R => '0'
);
\rgb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(7),
Q => rgb(7),
R => '0'
);
\rgb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(0),
Q => rgb(8),
R => '0'
);
\rgb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(1),
Q => rgb(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_1_0 is
port (
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_vga_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_vga_1_0 : entity is "system_ov7670_vga_0_0,ov7670_vga,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_vga_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_vga_1_0 : entity is "ov7670_vga,Vivado 2016.4";
end system_ov7670_vga_1_0;
architecture STRUCTURE of system_ov7670_vga_1_0 is
begin
U0: entity work.system_ov7670_vga_1_0_ov7670_vga
port map (
data(7 downto 0) => data(7 downto 0),
pclk => pclk,
rgb(15 downto 0) => rgb(15 downto 0)
);
end STRUCTURE;
|
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity uart is
port (
-- FPGA internal interface to the TX and RX FIFOs
clock : in std_logic ;
reset : in std_logic ;
enable : in std_logic ;
-- RS232 interface
rs232_rxd : out std_logic ;
rs232_txd : in std_logic ;
-- UART -> FIFO interface
txd_we : out std_logic ;
txd_full : in std_logic ;
txd_data : out std_logic_vector(7 downto 0) ;
-- FIFO -> UART interface
rxd_re : out std_logic ;
rxd_empty : in std_logic ;
rxd_data : in std_logic_vector(7 downto 0)
) ;
end entity ; -- uart
architecture arch of uart is
-- TODO: Make this a generic instead of a constant
constant CLOCKS_PER_BIT : natural := 10 ;
-- Send and receive state machine definitions
type send_fsm_t is (IDLE, SEND_START, SEND_DATA, SEND_STOP ) ;
type receive_fsm_t is (WAIT_FOR_START, CENTER_START, SAMPLE_DATA, WAIT_FOR_STOP) ;
-- FSM signals
signal send_fsm : send_fsm_t ;
signal receive_fsm : receive_fsm_t ;
-- Synchronization signals for asynchronous input
signal reg_txd : std_logic ;
signal sync_txd : std_logic ;
begin
-- Synchronize asynchronous inputs
reg_txd <= rs232_txd when rising_edge( clock ) ;
sync_txd <= reg_txd when rising_edge( clock ) ;
-- Receive data from the UART and put it in the FIFO
receive_from_uart : process(all)
variable bits : std_logic_vector(7 downto 0) ;
variable bit_count : natural range 0 to bits'length ;
variable clock_count : natural range 0 to CLOCKS_PER_BIT ;
variable txd_delay : std_logic ;
begin
if( reset = '1' ) then
receive_fsm <= WAIT_FOR_START ;
txd_we <= '0' ;
txd_data <= (others =>'0') ;
bits := (others =>'0') ;
bit_count := 0 ;
clock_count := 0 ;
txd_delay := '0' ;
elsif( rising_edge(clock) ) then
if( enable = '0' ) then
txd_we <= '0' ;
txd_data <= (others =>'0') ;
bits := (others =>'0') ;
bit_count := 0 ;
clock_count := 0 ;
txd_delay := '0' ;
else
txd_we <= '0' ;
case receive_fsm is
-- Wait for the start signal
when WAIT_FOR_START =>
if( sync_txd = '0' and txd_delay = '1' ) then
receive_fsm <= CENTER_START ;
clock_count := CLOCKS_PER_BIT/2-1 ;
end if ;
txd_delay := sync_txd ;
-- Center the start bit
when CENTER_START =>
clock_count := clock_count - 1 ;
if( clock_count = 0 ) then
receive_fsm <= SAMPLE_DATA ;
clock_count := CLOCKS_PER_BIT ;
bit_count := bits'length ;
end if ;
-- Sample the bits
when SAMPLE_DATA =>
clock_count := clock_count - 1 ;
if( clock_count = 0 ) then
bits := sync_txd & bits(bits'high downto 1) ;
bit_count := bit_count - 1 ;
clock_count := CLOCKS_PER_BIT ;
if( bit_count = 0 ) then
receive_fsm <= WAIT_FOR_STOP ;
txd_data <= bits ;
txd_we <= '1' ;
end if ;
end if ;
-- Wait for the stop bit
when WAIT_FOR_STOP =>
clock_count := clock_count - 1 ;
if( clock_count = 0 ) then
receive_fsm <= WAIT_FOR_START ;
assert sync_txd = '1' report "STOP bit not found!" severity error ;
end if ;
when others =>
end case ;
end if ;
end if ;
end process ;
-- Send data to the UART from the FIFO
send_to_uart : process(all)
variable bits : std_logic_vector(7 downto 0) ;
variable bit_count : natural range 0 to bits'length ;
variable clock_count : natural range 0 to CLOCKS_PER_BIT ;
begin
if( reset = '1' ) then
send_fsm <= IDLE ;
rxd_re <= '0' ;
rs232_rxd <= '1' ;
bit_count := 0 ;
clock_count := 0 ;
bits := (others =>'0') ;
elsif( rising_edge(clock) ) then
if( enable = '0' ) then
send_fsm <= IDLE ;
rxd_re <= '0' ;
rs232_rxd <= '1' ;
bit_count := 0 ;
clock_count := 0 ;
bits := (others =>'0') ;
else
rxd_re <= '0' ;
case send_fsm is
-- Wait until we have something to send
when IDLE =>
rs232_rxd <= '1' ;
if( rxd_empty = '0' ) then
send_fsm <= SEND_START ;
rxd_re <= '1' ;
bit_count := bits'length ;
clock_count := CLOCKS_PER_BIT ;
end if ;
-- Send the start bit
when SEND_START =>
rs232_rxd <= '0' ;
-- bits := rxd_data ;
clock_count := clock_count - 1 ;
if( clock_count = 0 ) then
send_fsm <= SEND_DATA ;
clock_count := CLOCKS_PER_BIT ;
elsif( clock_count = 9 ) then
bits := rxd_data ;
end if ;
-- Send the data
when SEND_DATA =>
rs232_rxd <= bits(0) ;
clock_count := clock_count - 1 ;
if( clock_count = 0 ) then
bits := '0' & bits(bits'high downto 1) ;
bit_count := bit_count - 1 ;
clock_count := CLOCKS_PER_BIT ;
if( bit_count = 0 ) then
send_fsm <= SEND_STOP ;
end if ;
end if ;
-- Send the stop bit
when SEND_STOP =>
rs232_rxd <= '1' ;
clock_count := clock_count - 1 ;
if( clock_count = 0 ) then
send_fsm <= IDLE ;
end if ;
-- Weird
when others =>
send_fsm <= IDLE ;
rs232_rxd <= '1' ;
bit_count := 0 ;
clock_count := 0 ;
bits := (others =>'0') ;
end case ;
end if ;
end if ;
end process ;
end architecture ; -- arch
|
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rmii_tx_fixed.vhd
--
-- Version: v1.01.a
-- Description: Top level of RMII(reduced media independent interface)
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- include library containing the entities you're configuring
------------------------------------------------------------------------------
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_GEN1 -- description of generic, if description doesn't fit
-- -- align with first part of description
-- C_GEN2 -- description of generic
--
-- Definition of Ports:
-- Port_name1 -- description of port, indicate source or destination
-- Port_name2 -- description of port
--
------------------------------------------------------------------------------
entity rmii_tx_fixed is
generic (
C_RESET_ACTIVE : std_logic := '0'
);
port (
Tx_speed_100 : in std_logic;
------------------ System Signals -------------------------------
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
------------------ MII <--> RMII --------------------------------
Mac2Rmii_tx_en : in std_logic;
Mac2Rmii_txd : in std_logic_vector(3 downto 0);
Mac2Rmii_tx_er : in std_logic;
Rmii2Mac_tx_clk : out std_logic;
------------------ RMII <--> PHY --------------------------------
Rmii2Phy_txd : out std_logic_vector(1 downto 0);
Rmii2Phy_tx_en : out std_logic
);
end rmii_tx_fixed;
------------------------------------------------------------------------------
-- Configurations
------------------------------------------------------------------------------
-- No Configurations
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture simulation of rmii_tx_fixed is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
-- Note that global constants and parameters (such as RESET_ACTIVE, default
-- values for address and data --widths, initialization values, etc.) should be
-- collected into a global package or include file.
-- Constants are all uppercase.
-- Constants or parameters should be used for all numeric values except for
-- single "0" or "1" values.
-- Constants should also be used when denoting a bit location within a register.
-- If no constants are required, simply state this in a comment below the file
-- section separation comments.
------------------------------------------------------------------------------
-- No Constants
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
type STATES_TYPE is (
IDLE_CLK_L,
IDLE_CLK_H,
TX100_DIBIT_0_CLK_L,
TX100_DIBIT_1_CLK_H,
TX10_DIBIT_0_CLK_L0,
TX10_DIBIT_0_CLK_L1,
TX10_DIBIT_0_CLK_L2,
TX10_DIBIT_0_CLK_L3,
TX10_DIBIT_0_CLK_L4,
TX10_DIBIT_0_CLK_L5,
TX10_DIBIT_0_CLK_L6,
TX10_DIBIT_0_CLK_L7,
TX10_DIBIT_0_CLK_L8,
TX10_DIBIT_0_CLK_L9,
TX10_DIBIT_1_CLK_H0,
TX10_DIBIT_1_CLK_H1,
TX10_DIBIT_1_CLK_H2,
TX10_DIBIT_1_CLK_H3,
TX10_DIBIT_1_CLK_H4,
TX10_DIBIT_1_CLK_H5,
TX10_DIBIT_1_CLK_H6,
TX10_DIBIT_1_CLK_H7,
TX10_DIBIT_1_CLK_H8,
TX10_DIBIT_1_CLK_H9
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
signal mac2Rmii_tx_en_d : std_logic;
signal mac2Rmii_txd_d : std_logic_vector(3 downto 0);
signal mac2Rmii_tx_er_d : std_logic;
signal tx_in_reg_en : std_logic;
signal txd_dibit : std_logic;
signal txd_error : std_logic;
begin
------------------------------------------------------------------------------
-- TX_IN_REG_PROCESS
------------------------------------------------------------------------------
TX_IN_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
mac2Rmii_tx_en_d <= '0';
mac2Rmii_txd_d <= (others => '0');
mac2Rmii_tx_er_d <= '0';
elsif (tx_in_reg_en = '1') then
mac2Rmii_tx_en_d <= Mac2Rmii_tx_en;
mac2Rmii_txd_d <= Mac2Rmii_txd;
mac2Rmii_tx_er_d <= Mac2Rmii_tx_er;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_OUT_REG_PROCESS
------------------------------------------------------------------------------
TX_OUT_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
Rmii2Phy_txd(0) <= '0';
Rmii2Phy_txd(1) <= '0';
Rmii2Phy_tx_en <= '0';
elsif (txd_dibit = '0') then
Rmii2Phy_txd(0) <= mac2Rmii_txd_d(0) xor txd_error;
Rmii2Phy_txd(1) <= mac2Rmii_txd_d(1) or txd_error;
Rmii2Phy_tx_en <= mac2Rmii_tx_en_d;
elsif (txd_dibit = '1') then
Rmii2Phy_txd(0) <= mac2Rmii_txd_d(2) xor txd_error;
Rmii2Phy_txd(1) <= mac2Rmii_txd_d(3) or txd_error;
Rmii2Phy_tx_en <= mac2Rmii_tx_en_d;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_CONTROL_SYNC_PROCESS
------------------------------------------------------------------------------
TX_CONTROL_SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IDLE_CLK_L;
else
present_state <= next_state;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_CONTROL_NEXT_STATE_PROCESS
------------------------------------------------------------------------------
TX_CONTROL_NEXT_STATE_PROCESS : process (
present_state,
mac2Rmii_tx_er_d,
Tx_speed_100
)
begin
case present_state is
when IDLE_CLK_L =>
next_state <= IDLE_CLK_H;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '0';
txd_error <= '0';
when IDLE_CLK_H =>
if (Tx_speed_100 = '1') then
next_state <= TX100_DIBIT_0_CLK_L;
else
next_state <= TX10_DIBIT_0_CLK_L0;
end if;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX100_DIBIT_0_CLK_L =>
next_state <= TX100_DIBIT_1_CLK_H;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '1';
txd_error <= mac2Rmii_tx_er_d;
when TX100_DIBIT_1_CLK_H =>
next_state <= TX100_DIBIT_0_CLK_L;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= mac2Rmii_tx_er_d;
when TX10_DIBIT_0_CLK_L0 =>
next_state <= TX10_DIBIT_0_CLK_L1;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L1 =>
next_state <= TX10_DIBIT_0_CLK_L2;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L2 =>
next_state <= TX10_DIBIT_0_CLK_L3;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L3 =>
next_state <= TX10_DIBIT_0_CLK_L4;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L4 =>
next_state <= TX10_DIBIT_0_CLK_L5;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L5 =>
next_state <= TX10_DIBIT_0_CLK_L6;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L6 =>
next_state <= TX10_DIBIT_0_CLK_L7;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L7 =>
next_state <= TX10_DIBIT_0_CLK_L8;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L8 =>
next_state <= TX10_DIBIT_0_CLK_L9;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L9 =>
next_state <= TX10_DIBIT_1_CLK_H0;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H0 =>
next_state <= TX10_DIBIT_1_CLK_H1;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H1 =>
next_state <= TX10_DIBIT_1_CLK_H2;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H2 =>
next_state <= TX10_DIBIT_1_CLK_H3;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H3 =>
next_state <= TX10_DIBIT_1_CLK_H4;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H4 =>
next_state <= TX10_DIBIT_1_CLK_H5;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H5 =>
next_state <= TX10_DIBIT_1_CLK_H6;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H6 =>
next_state <= TX10_DIBIT_1_CLK_H7;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H7 =>
next_state <= TX10_DIBIT_1_CLK_H8;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H8 =>
next_state <= TX10_DIBIT_1_CLK_H9;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H9 =>
next_state <= TX10_DIBIT_0_CLK_L0;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
end case;
end process;
end simulation;
|
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rmii_tx_fixed.vhd
--
-- Version: v1.01.a
-- Description: Top level of RMII(reduced media independent interface)
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- include library containing the entities you're configuring
------------------------------------------------------------------------------
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_GEN1 -- description of generic, if description doesn't fit
-- -- align with first part of description
-- C_GEN2 -- description of generic
--
-- Definition of Ports:
-- Port_name1 -- description of port, indicate source or destination
-- Port_name2 -- description of port
--
------------------------------------------------------------------------------
entity rmii_tx_fixed is
generic (
C_RESET_ACTIVE : std_logic := '0'
);
port (
Tx_speed_100 : in std_logic;
------------------ System Signals -------------------------------
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
------------------ MII <--> RMII --------------------------------
Mac2Rmii_tx_en : in std_logic;
Mac2Rmii_txd : in std_logic_vector(3 downto 0);
Mac2Rmii_tx_er : in std_logic;
Rmii2Mac_tx_clk : out std_logic;
------------------ RMII <--> PHY --------------------------------
Rmii2Phy_txd : out std_logic_vector(1 downto 0);
Rmii2Phy_tx_en : out std_logic
);
end rmii_tx_fixed;
------------------------------------------------------------------------------
-- Configurations
------------------------------------------------------------------------------
-- No Configurations
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture simulation of rmii_tx_fixed is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
-- Note that global constants and parameters (such as RESET_ACTIVE, default
-- values for address and data --widths, initialization values, etc.) should be
-- collected into a global package or include file.
-- Constants are all uppercase.
-- Constants or parameters should be used for all numeric values except for
-- single "0" or "1" values.
-- Constants should also be used when denoting a bit location within a register.
-- If no constants are required, simply state this in a comment below the file
-- section separation comments.
------------------------------------------------------------------------------
-- No Constants
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
type STATES_TYPE is (
IDLE_CLK_L,
IDLE_CLK_H,
TX100_DIBIT_0_CLK_L,
TX100_DIBIT_1_CLK_H,
TX10_DIBIT_0_CLK_L0,
TX10_DIBIT_0_CLK_L1,
TX10_DIBIT_0_CLK_L2,
TX10_DIBIT_0_CLK_L3,
TX10_DIBIT_0_CLK_L4,
TX10_DIBIT_0_CLK_L5,
TX10_DIBIT_0_CLK_L6,
TX10_DIBIT_0_CLK_L7,
TX10_DIBIT_0_CLK_L8,
TX10_DIBIT_0_CLK_L9,
TX10_DIBIT_1_CLK_H0,
TX10_DIBIT_1_CLK_H1,
TX10_DIBIT_1_CLK_H2,
TX10_DIBIT_1_CLK_H3,
TX10_DIBIT_1_CLK_H4,
TX10_DIBIT_1_CLK_H5,
TX10_DIBIT_1_CLK_H6,
TX10_DIBIT_1_CLK_H7,
TX10_DIBIT_1_CLK_H8,
TX10_DIBIT_1_CLK_H9
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
signal mac2Rmii_tx_en_d : std_logic;
signal mac2Rmii_txd_d : std_logic_vector(3 downto 0);
signal mac2Rmii_tx_er_d : std_logic;
signal tx_in_reg_en : std_logic;
signal txd_dibit : std_logic;
signal txd_error : std_logic;
begin
------------------------------------------------------------------------------
-- TX_IN_REG_PROCESS
------------------------------------------------------------------------------
TX_IN_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
mac2Rmii_tx_en_d <= '0';
mac2Rmii_txd_d <= (others => '0');
mac2Rmii_tx_er_d <= '0';
elsif (tx_in_reg_en = '1') then
mac2Rmii_tx_en_d <= Mac2Rmii_tx_en;
mac2Rmii_txd_d <= Mac2Rmii_txd;
mac2Rmii_tx_er_d <= Mac2Rmii_tx_er;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_OUT_REG_PROCESS
------------------------------------------------------------------------------
TX_OUT_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
Rmii2Phy_txd(0) <= '0';
Rmii2Phy_txd(1) <= '0';
Rmii2Phy_tx_en <= '0';
elsif (txd_dibit = '0') then
Rmii2Phy_txd(0) <= mac2Rmii_txd_d(0) xor txd_error;
Rmii2Phy_txd(1) <= mac2Rmii_txd_d(1) or txd_error;
Rmii2Phy_tx_en <= mac2Rmii_tx_en_d;
elsif (txd_dibit = '1') then
Rmii2Phy_txd(0) <= mac2Rmii_txd_d(2) xor txd_error;
Rmii2Phy_txd(1) <= mac2Rmii_txd_d(3) or txd_error;
Rmii2Phy_tx_en <= mac2Rmii_tx_en_d;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_CONTROL_SYNC_PROCESS
------------------------------------------------------------------------------
TX_CONTROL_SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IDLE_CLK_L;
else
present_state <= next_state;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_CONTROL_NEXT_STATE_PROCESS
------------------------------------------------------------------------------
TX_CONTROL_NEXT_STATE_PROCESS : process (
present_state,
mac2Rmii_tx_er_d,
Tx_speed_100
)
begin
case present_state is
when IDLE_CLK_L =>
next_state <= IDLE_CLK_H;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '0';
txd_error <= '0';
when IDLE_CLK_H =>
if (Tx_speed_100 = '1') then
next_state <= TX100_DIBIT_0_CLK_L;
else
next_state <= TX10_DIBIT_0_CLK_L0;
end if;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX100_DIBIT_0_CLK_L =>
next_state <= TX100_DIBIT_1_CLK_H;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '1';
txd_error <= mac2Rmii_tx_er_d;
when TX100_DIBIT_1_CLK_H =>
next_state <= TX100_DIBIT_0_CLK_L;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= mac2Rmii_tx_er_d;
when TX10_DIBIT_0_CLK_L0 =>
next_state <= TX10_DIBIT_0_CLK_L1;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L1 =>
next_state <= TX10_DIBIT_0_CLK_L2;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L2 =>
next_state <= TX10_DIBIT_0_CLK_L3;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L3 =>
next_state <= TX10_DIBIT_0_CLK_L4;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L4 =>
next_state <= TX10_DIBIT_0_CLK_L5;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L5 =>
next_state <= TX10_DIBIT_0_CLK_L6;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L6 =>
next_state <= TX10_DIBIT_0_CLK_L7;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L7 =>
next_state <= TX10_DIBIT_0_CLK_L8;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L8 =>
next_state <= TX10_DIBIT_0_CLK_L9;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L9 =>
next_state <= TX10_DIBIT_1_CLK_H0;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H0 =>
next_state <= TX10_DIBIT_1_CLK_H1;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H1 =>
next_state <= TX10_DIBIT_1_CLK_H2;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H2 =>
next_state <= TX10_DIBIT_1_CLK_H3;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H3 =>
next_state <= TX10_DIBIT_1_CLK_H4;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H4 =>
next_state <= TX10_DIBIT_1_CLK_H5;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H5 =>
next_state <= TX10_DIBIT_1_CLK_H6;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H6 =>
next_state <= TX10_DIBIT_1_CLK_H7;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H7 =>
next_state <= TX10_DIBIT_1_CLK_H8;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H8 =>
next_state <= TX10_DIBIT_1_CLK_H9;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H9 =>
next_state <= TX10_DIBIT_0_CLK_L0;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
end case;
end process;
end simulation;
|
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rmii_tx_fixed.vhd
--
-- Version: v1.01.a
-- Description: Top level of RMII(reduced media independent interface)
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- include library containing the entities you're configuring
------------------------------------------------------------------------------
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_GEN1 -- description of generic, if description doesn't fit
-- -- align with first part of description
-- C_GEN2 -- description of generic
--
-- Definition of Ports:
-- Port_name1 -- description of port, indicate source or destination
-- Port_name2 -- description of port
--
------------------------------------------------------------------------------
entity rmii_tx_fixed is
generic (
C_RESET_ACTIVE : std_logic := '0'
);
port (
Tx_speed_100 : in std_logic;
------------------ System Signals -------------------------------
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
------------------ MII <--> RMII --------------------------------
Mac2Rmii_tx_en : in std_logic;
Mac2Rmii_txd : in std_logic_vector(3 downto 0);
Mac2Rmii_tx_er : in std_logic;
Rmii2Mac_tx_clk : out std_logic;
------------------ RMII <--> PHY --------------------------------
Rmii2Phy_txd : out std_logic_vector(1 downto 0);
Rmii2Phy_tx_en : out std_logic
);
end rmii_tx_fixed;
------------------------------------------------------------------------------
-- Configurations
------------------------------------------------------------------------------
-- No Configurations
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture simulation of rmii_tx_fixed is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
-- Note that global constants and parameters (such as RESET_ACTIVE, default
-- values for address and data --widths, initialization values, etc.) should be
-- collected into a global package or include file.
-- Constants are all uppercase.
-- Constants or parameters should be used for all numeric values except for
-- single "0" or "1" values.
-- Constants should also be used when denoting a bit location within a register.
-- If no constants are required, simply state this in a comment below the file
-- section separation comments.
------------------------------------------------------------------------------
-- No Constants
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
type STATES_TYPE is (
IDLE_CLK_L,
IDLE_CLK_H,
TX100_DIBIT_0_CLK_L,
TX100_DIBIT_1_CLK_H,
TX10_DIBIT_0_CLK_L0,
TX10_DIBIT_0_CLK_L1,
TX10_DIBIT_0_CLK_L2,
TX10_DIBIT_0_CLK_L3,
TX10_DIBIT_0_CLK_L4,
TX10_DIBIT_0_CLK_L5,
TX10_DIBIT_0_CLK_L6,
TX10_DIBIT_0_CLK_L7,
TX10_DIBIT_0_CLK_L8,
TX10_DIBIT_0_CLK_L9,
TX10_DIBIT_1_CLK_H0,
TX10_DIBIT_1_CLK_H1,
TX10_DIBIT_1_CLK_H2,
TX10_DIBIT_1_CLK_H3,
TX10_DIBIT_1_CLK_H4,
TX10_DIBIT_1_CLK_H5,
TX10_DIBIT_1_CLK_H6,
TX10_DIBIT_1_CLK_H7,
TX10_DIBIT_1_CLK_H8,
TX10_DIBIT_1_CLK_H9
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
signal mac2Rmii_tx_en_d : std_logic;
signal mac2Rmii_txd_d : std_logic_vector(3 downto 0);
signal mac2Rmii_tx_er_d : std_logic;
signal tx_in_reg_en : std_logic;
signal txd_dibit : std_logic;
signal txd_error : std_logic;
begin
------------------------------------------------------------------------------
-- TX_IN_REG_PROCESS
------------------------------------------------------------------------------
TX_IN_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
mac2Rmii_tx_en_d <= '0';
mac2Rmii_txd_d <= (others => '0');
mac2Rmii_tx_er_d <= '0';
elsif (tx_in_reg_en = '1') then
mac2Rmii_tx_en_d <= Mac2Rmii_tx_en;
mac2Rmii_txd_d <= Mac2Rmii_txd;
mac2Rmii_tx_er_d <= Mac2Rmii_tx_er;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_OUT_REG_PROCESS
------------------------------------------------------------------------------
TX_OUT_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
Rmii2Phy_txd(0) <= '0';
Rmii2Phy_txd(1) <= '0';
Rmii2Phy_tx_en <= '0';
elsif (txd_dibit = '0') then
Rmii2Phy_txd(0) <= mac2Rmii_txd_d(0) xor txd_error;
Rmii2Phy_txd(1) <= mac2Rmii_txd_d(1) or txd_error;
Rmii2Phy_tx_en <= mac2Rmii_tx_en_d;
elsif (txd_dibit = '1') then
Rmii2Phy_txd(0) <= mac2Rmii_txd_d(2) xor txd_error;
Rmii2Phy_txd(1) <= mac2Rmii_txd_d(3) or txd_error;
Rmii2Phy_tx_en <= mac2Rmii_tx_en_d;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_CONTROL_SYNC_PROCESS
------------------------------------------------------------------------------
TX_CONTROL_SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IDLE_CLK_L;
else
present_state <= next_state;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_CONTROL_NEXT_STATE_PROCESS
------------------------------------------------------------------------------
TX_CONTROL_NEXT_STATE_PROCESS : process (
present_state,
mac2Rmii_tx_er_d,
Tx_speed_100
)
begin
case present_state is
when IDLE_CLK_L =>
next_state <= IDLE_CLK_H;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '0';
txd_error <= '0';
when IDLE_CLK_H =>
if (Tx_speed_100 = '1') then
next_state <= TX100_DIBIT_0_CLK_L;
else
next_state <= TX10_DIBIT_0_CLK_L0;
end if;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX100_DIBIT_0_CLK_L =>
next_state <= TX100_DIBIT_1_CLK_H;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '1';
txd_error <= mac2Rmii_tx_er_d;
when TX100_DIBIT_1_CLK_H =>
next_state <= TX100_DIBIT_0_CLK_L;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= mac2Rmii_tx_er_d;
when TX10_DIBIT_0_CLK_L0 =>
next_state <= TX10_DIBIT_0_CLK_L1;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L1 =>
next_state <= TX10_DIBIT_0_CLK_L2;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L2 =>
next_state <= TX10_DIBIT_0_CLK_L3;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L3 =>
next_state <= TX10_DIBIT_0_CLK_L4;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L4 =>
next_state <= TX10_DIBIT_0_CLK_L5;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L5 =>
next_state <= TX10_DIBIT_0_CLK_L6;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L6 =>
next_state <= TX10_DIBIT_0_CLK_L7;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L7 =>
next_state <= TX10_DIBIT_0_CLK_L8;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L8 =>
next_state <= TX10_DIBIT_0_CLK_L9;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L9 =>
next_state <= TX10_DIBIT_1_CLK_H0;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H0 =>
next_state <= TX10_DIBIT_1_CLK_H1;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H1 =>
next_state <= TX10_DIBIT_1_CLK_H2;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H2 =>
next_state <= TX10_DIBIT_1_CLK_H3;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H3 =>
next_state <= TX10_DIBIT_1_CLK_H4;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H4 =>
next_state <= TX10_DIBIT_1_CLK_H5;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H5 =>
next_state <= TX10_DIBIT_1_CLK_H6;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H6 =>
next_state <= TX10_DIBIT_1_CLK_H7;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H7 =>
next_state <= TX10_DIBIT_1_CLK_H8;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H8 =>
next_state <= TX10_DIBIT_1_CLK_H9;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H9 =>
next_state <= TX10_DIBIT_0_CLK_L0;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
end case;
end process;
end simulation;
|
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rmii_tx_fixed.vhd
--
-- Version: v1.01.a
-- Description: Top level of RMII(reduced media independent interface)
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- include library containing the entities you're configuring
------------------------------------------------------------------------------
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_GEN1 -- description of generic, if description doesn't fit
-- -- align with first part of description
-- C_GEN2 -- description of generic
--
-- Definition of Ports:
-- Port_name1 -- description of port, indicate source or destination
-- Port_name2 -- description of port
--
------------------------------------------------------------------------------
entity rmii_tx_fixed is
generic (
C_RESET_ACTIVE : std_logic := '0'
);
port (
Tx_speed_100 : in std_logic;
------------------ System Signals -------------------------------
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
------------------ MII <--> RMII --------------------------------
Mac2Rmii_tx_en : in std_logic;
Mac2Rmii_txd : in std_logic_vector(3 downto 0);
Mac2Rmii_tx_er : in std_logic;
Rmii2Mac_tx_clk : out std_logic;
------------------ RMII <--> PHY --------------------------------
Rmii2Phy_txd : out std_logic_vector(1 downto 0);
Rmii2Phy_tx_en : out std_logic
);
end rmii_tx_fixed;
------------------------------------------------------------------------------
-- Configurations
------------------------------------------------------------------------------
-- No Configurations
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture simulation of rmii_tx_fixed is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
-- Note that global constants and parameters (such as RESET_ACTIVE, default
-- values for address and data --widths, initialization values, etc.) should be
-- collected into a global package or include file.
-- Constants are all uppercase.
-- Constants or parameters should be used for all numeric values except for
-- single "0" or "1" values.
-- Constants should also be used when denoting a bit location within a register.
-- If no constants are required, simply state this in a comment below the file
-- section separation comments.
------------------------------------------------------------------------------
-- No Constants
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
type STATES_TYPE is (
IDLE_CLK_L,
IDLE_CLK_H,
TX100_DIBIT_0_CLK_L,
TX100_DIBIT_1_CLK_H,
TX10_DIBIT_0_CLK_L0,
TX10_DIBIT_0_CLK_L1,
TX10_DIBIT_0_CLK_L2,
TX10_DIBIT_0_CLK_L3,
TX10_DIBIT_0_CLK_L4,
TX10_DIBIT_0_CLK_L5,
TX10_DIBIT_0_CLK_L6,
TX10_DIBIT_0_CLK_L7,
TX10_DIBIT_0_CLK_L8,
TX10_DIBIT_0_CLK_L9,
TX10_DIBIT_1_CLK_H0,
TX10_DIBIT_1_CLK_H1,
TX10_DIBIT_1_CLK_H2,
TX10_DIBIT_1_CLK_H3,
TX10_DIBIT_1_CLK_H4,
TX10_DIBIT_1_CLK_H5,
TX10_DIBIT_1_CLK_H6,
TX10_DIBIT_1_CLK_H7,
TX10_DIBIT_1_CLK_H8,
TX10_DIBIT_1_CLK_H9
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
signal mac2Rmii_tx_en_d : std_logic;
signal mac2Rmii_txd_d : std_logic_vector(3 downto 0);
signal mac2Rmii_tx_er_d : std_logic;
signal tx_in_reg_en : std_logic;
signal txd_dibit : std_logic;
signal txd_error : std_logic;
begin
------------------------------------------------------------------------------
-- TX_IN_REG_PROCESS
------------------------------------------------------------------------------
TX_IN_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
mac2Rmii_tx_en_d <= '0';
mac2Rmii_txd_d <= (others => '0');
mac2Rmii_tx_er_d <= '0';
elsif (tx_in_reg_en = '1') then
mac2Rmii_tx_en_d <= Mac2Rmii_tx_en;
mac2Rmii_txd_d <= Mac2Rmii_txd;
mac2Rmii_tx_er_d <= Mac2Rmii_tx_er;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_OUT_REG_PROCESS
------------------------------------------------------------------------------
TX_OUT_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
Rmii2Phy_txd(0) <= '0';
Rmii2Phy_txd(1) <= '0';
Rmii2Phy_tx_en <= '0';
elsif (txd_dibit = '0') then
Rmii2Phy_txd(0) <= mac2Rmii_txd_d(0) xor txd_error;
Rmii2Phy_txd(1) <= mac2Rmii_txd_d(1) or txd_error;
Rmii2Phy_tx_en <= mac2Rmii_tx_en_d;
elsif (txd_dibit = '1') then
Rmii2Phy_txd(0) <= mac2Rmii_txd_d(2) xor txd_error;
Rmii2Phy_txd(1) <= mac2Rmii_txd_d(3) or txd_error;
Rmii2Phy_tx_en <= mac2Rmii_tx_en_d;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_CONTROL_SYNC_PROCESS
------------------------------------------------------------------------------
TX_CONTROL_SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IDLE_CLK_L;
else
present_state <= next_state;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_CONTROL_NEXT_STATE_PROCESS
------------------------------------------------------------------------------
TX_CONTROL_NEXT_STATE_PROCESS : process (
present_state,
mac2Rmii_tx_er_d,
Tx_speed_100
)
begin
case present_state is
when IDLE_CLK_L =>
next_state <= IDLE_CLK_H;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '0';
txd_error <= '0';
when IDLE_CLK_H =>
if (Tx_speed_100 = '1') then
next_state <= TX100_DIBIT_0_CLK_L;
else
next_state <= TX10_DIBIT_0_CLK_L0;
end if;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX100_DIBIT_0_CLK_L =>
next_state <= TX100_DIBIT_1_CLK_H;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '1';
txd_error <= mac2Rmii_tx_er_d;
when TX100_DIBIT_1_CLK_H =>
next_state <= TX100_DIBIT_0_CLK_L;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= mac2Rmii_tx_er_d;
when TX10_DIBIT_0_CLK_L0 =>
next_state <= TX10_DIBIT_0_CLK_L1;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L1 =>
next_state <= TX10_DIBIT_0_CLK_L2;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L2 =>
next_state <= TX10_DIBIT_0_CLK_L3;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L3 =>
next_state <= TX10_DIBIT_0_CLK_L4;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L4 =>
next_state <= TX10_DIBIT_0_CLK_L5;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L5 =>
next_state <= TX10_DIBIT_0_CLK_L6;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L6 =>
next_state <= TX10_DIBIT_0_CLK_L7;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L7 =>
next_state <= TX10_DIBIT_0_CLK_L8;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L8 =>
next_state <= TX10_DIBIT_0_CLK_L9;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L9 =>
next_state <= TX10_DIBIT_1_CLK_H0;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H0 =>
next_state <= TX10_DIBIT_1_CLK_H1;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H1 =>
next_state <= TX10_DIBIT_1_CLK_H2;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H2 =>
next_state <= TX10_DIBIT_1_CLK_H3;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H3 =>
next_state <= TX10_DIBIT_1_CLK_H4;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H4 =>
next_state <= TX10_DIBIT_1_CLK_H5;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H5 =>
next_state <= TX10_DIBIT_1_CLK_H6;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H6 =>
next_state <= TX10_DIBIT_1_CLK_H7;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H7 =>
next_state <= TX10_DIBIT_1_CLK_H8;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H8 =>
next_state <= TX10_DIBIT_1_CLK_H9;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H9 =>
next_state <= TX10_DIBIT_0_CLK_L0;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
end case;
end process;
end simulation;
|
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Elod Gyorgy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 17:18:33 02/21/2014
-- Design Name:
-- Module Name: FPGAMonitor - Behavioral
-- Project Name: Nexys4 User Demo
-- Target Devices:
-- Tool versions:
-- Description:
-- This module measures the FPGA temperature using the FPGA internal
-- XADC temperature monitor
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.all;
use IEEE.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity FPGAMonitor is
Generic (CLOCKFREQ : natural := 100); -- input CLK frequency in MHz
Port ( CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
TEMP_O : out STD_LOGIC_VECTOR (11 downto 0));
end FPGAMonitor;
architecture Behavioral of FPGAMonitor is
component LocalRst
Generic ( RESET_PERIOD : natural := 4);
Port ( RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
SRST_O : out STD_LOGIC);
end component;
constant DADDR_TEMP : std_logic_vector(6 downto 0) := "0000000";
constant DELAY : NATURAL := 10; --us
constant DELAY_CYCLES : NATURAL :=
natural(ceil(real(DELAY*CLOCKFREQ)));
type state_type is (stIdle, stReadRequest, stReadWait, stRead);
signal state, nstate : state_type := stIdle;
signal x_den, x_drdy, x_drdy_r : std_logic;
signal x_do, x_do_r : std_logic_vector(15 downto 0);
signal waitCnt : natural range 0 to DELAY_CYCLES := DELAY_CYCLES;
signal waitCntEn, SysRst : std_logic;
begin
----------------------------------------------------------------------------------
-- Sync Reset
----------------------------------------------------------------------------------
Sync_Reset : LocalRst
port map (
RST_I => RST_I,
CLK_I => CLK_I,
SRST_O => SysRst
);
----------------------------------------------------------------------------------
-- Instantiate XADC primitive, single channel (temperature), continuous mode
----------------------------------------------------------------------------------
XADC_INST : XADC
generic map(
INIT_40 => X"1000", -- config reg 0
INIT_41 => X"3f3f", -- config reg 1
INIT_42 => X"0400", -- config reg 2
INIT_48 => X"0100", -- Sequencer channel selection
INIT_49 => X"0000", -- Sequencer channel selection
INIT_4A => X"0000", -- Sequencer Average selection
INIT_4B => X"0000", -- Sequencer Average selection
INIT_4C => X"0000", -- Sequencer Bipolar selection
INIT_4D => X"0000", -- Sequencer Bipolar selection
INIT_4E => X"0000", -- Sequencer Acq time selection
INIT_4F => X"0000", -- Sequencer Acq time selection
INIT_50 => X"b5ed", -- Temp alarm trigger
INIT_51 => X"57e4", -- Vccint upper alarm limit
INIT_52 => X"a147", -- Vccaux upper alarm limit
INIT_53 => X"ca33", -- Temp alarm OT upper
INIT_54 => X"a93a", -- Temp alarm reset
INIT_55 => X"52c6", -- Vccint lower alarm limit
INIT_56 => X"9555", -- Vccaux lower alarm limit
INIT_57 => X"ae4e", -- Temp alarm OT reset
INIT_58 => X"5999", -- Vbram upper alarm limit
INIT_5C => X"5111", -- Vbram lower alarm limit
SIM_DEVICE => "7SERIES"
)
port map (
CONVST => '0',
CONVSTCLK => '0',
DADDR(6 downto 0) => DADDR_TEMP,
DCLK => CLK_I,
DEN => x_den,
DI(15 downto 0) => x"0000",
DWE => '0',
RESET => '0',
VAUXN(15 downto 0) => x"0000",
VAUXP(15 downto 0) => x"0000",
ALM => open,
BUSY => open,
CHANNEL => open,
DO(15 downto 0) => x_do,
DRDY => x_drdy,
EOC => open,
EOS => open,
JTAGBUSY => open,
JTAGLOCKED => open,
JTAGMODIFIED => open,
OT => open,
MUXADDR => open,
VN => '0',
VP => '0'
);
----------------------------------------------------------------------------------
-- Register Temperature
----------------------------------------------------------------------------------
process(CLK_I)
begin
if Rising_Edge(CLK_I) then
if (x_drdy_r = '1') then
TEMP_O <= x_do_r(15 downto 4);
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- Register XADC outputs
----------------------------------------------------------------------------------
process(CLK_I)
begin
if Rising_Edge(CLK_I) then
x_do_r <= x_do;
x_drdy_r <= x_drdy;
end if;
end process;
----------------------------------------------------------------------------------
-- Delay Counter
----------------------------------------------------------------------------------
Wait_CNT: process (CLK_I)
begin
if Rising_Edge(CLK_I) then
if (waitCntEn = '0') then
waitCnt <= DELAY_CYCLES;
else
waitCnt <= waitCnt - 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- Continuous temperature read FSM
----------------------------------------------------------------------------------
SYNC_PROC: process (CLK_I)
begin
if Rising_Edge(CLK_I) then
if (SysRst = '1') then
state <= stIdle;
else
state <= nstate;
end if;
end if;
end process;
OUTPUT_DECODE: process (state)
begin
x_den <= '0';
waitCntEn <= '0';
case (state) is
when stIdle =>
waitCntEn <= '1';
when stReadRequest =>
x_den <= '1';
when others =>
end case;
end process;
NEXT_STATE_DECODE: process (state)
begin
--declare default state for nstate to avoid latches
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (waitCnt = 0 and x_drdy_r = '0') then
nstate <= stReadRequest;
end if;
when stReadRequest =>
nstate <= stReadWait;
when stReadWait =>
if (x_drdy_r = '1') then
nstate <= stIdle;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
signal voice1_signed : signed(12 downto 0);
signal voice2_signed : signed(12 downto 0);
signal voice3_signed : signed(12 downto 0);
constant ext_in_signed : signed(12 downto 0) := to_signed(0,13);
signal filtered_audio : signed(18 downto 0);
signal tick_q1, tick_q2 : std_logic;
signal input_valid : std_logic;
signal unsigned_audio : std_logic_vector(17 downto 0);
signal unsigned_filt : std_logic_vector(18 downto 0);
signal ff1 : std_logic;
-------------------------------------------------------------------------------
begin
digital_to_analog: entity work.pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => unsigned_audio(17 downto 8),
dac_o => audio_out
);
paddle_x: entity work.pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: entity work.pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: entity work.sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: entity work.sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: entity work.sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid <= '1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed("0" & voice_1) - 2048;
voice2_signed <= signed("0" & voice_2) - 2048;
voice3_signed <= signed("0" & voice_3) - 2048;
filters: entity work.sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- Company : HSLU, Waj
-- Create Date: 20-Apr-12
-- Project : ECS, Uebung 2
-- Description: Testbench for enable gate with configuration selection
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb_EnableGate is
end tb_EnableGate;
architecture TB of tb_EnableGate is
component EnableGate
port(
x : in std_ulogic_vector(3 downto 0);
en : in std_ulogic;
y : out std_ulogic_vector(3 downto 0));
end component EnableGate;
-- configure architecture of UUT to be simulated
for UUT1 : EnableGate use entity work.EnableGate(A_conc_sig_ass_1);
for UUT2 : EnableGate use entity work.EnableGate(A_conc_sig_ass_2);
for UUT3 : EnableGate use entity work.EnableGate(A_cond_sig_ass_1);
for UUT4 : EnableGate use entity work.EnableGate(A_sel_sig_ass_1);
for UUT5 : EnableGate use entity work.EnableGate(A_proc_seq_sig_ass_1);
signal x : std_ulogic_vector(3 downto 0);
signal en : std_ulogic;
signal y1 : std_ulogic_vector(3 downto 0);
signal y2 : std_ulogic_vector(3 downto 0);
signal y3 : std_ulogic_vector(3 downto 0);
signal y4 : std_ulogic_vector(3 downto 0);
signal y5 : std_ulogic_vector(3 downto 0);
begin
-- Unit Under Test port map
UUT1 : EnableGate
port map (
x => x,
en => en,
y => y1
);
UUT2 : EnableGate
port map (
x => x,
en => en,
y => y2
);
UUT3 : EnableGate
port map (
x => x,
en => en,
y => y3
);
UUT4 : EnableGate
port map (
x => x,
en => en,
y => y4
);
UUT5 : EnableGate
port map (
x => x,
en => en,
y => y5
);
process
begin
for e in std_ulogic'('0') to '1' loop
en <= e;
for i in 0 to 3 loop
x <= (others => '0');
x(i) <= '1';
wait for 1us; -- wait before checking response and applying next stimuli vector
if e = '1' then
assert y1 = x report "ERROR: Simulation failed!!!" severity failure;
assert y2 = x report "ERROR: Simulation failed!!!" severity failure;
assert y3 = x report "ERROR: Simulation failed!!!" severity failure;
assert y4 = x report "ERROR: Simulation failed!!!" severity failure;
assert y5 = x report "ERROR: Simulation failed!!!" severity failure;
else
assert y1 = "0000" report "ERROR: Simulation failed!!!" severity failure;
assert y2 = "0000" report "ERROR: Simulation failed!!!" severity failure;
assert y3 = "0000" report "ERROR: Simulation failed!!!" severity failure;
assert y4 = "0000" report "ERROR: Simulation failed!!!" severity failure;
assert y5 = "0000" report "ERROR: Simulation failed!!!" severity failure;
end if;
end loop;
end loop;
report "Simulation completed - Waiting for 8hr";
wait for 153min;
report "o.k. Simulation done" severity failure; -- failure: stop simulation
-- note: continue simulation
wait; -- suspend process forever
end process;
end TB;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (lin64) Build 1215546 Mon Apr 27 19:07:21 MDT 2015
-- Date : Fri Sep 18 12:15:17 2015
-- Host : parallella running 64-bit Ubuntu 14.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/aolofsson/Work_all/oh/xilibs/ip/fifo_async_104x32/fifo_async_104x32_stub.vhdl
-- Design : fifo_async_104x32
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z015clg485-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fifo_async_104x32 is
Port (
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 103 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 103 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
empty : out STD_LOGIC;
valid : out STD_LOGIC;
prog_full : out STD_LOGIC
);
end fifo_async_104x32;
architecture stub of fifo_async_104x32 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "wr_clk,wr_rst,rd_clk,rd_rst,din[103:0],wr_en,rd_en,dout[103:0],full,almost_full,empty,valid,prog_full";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v12_0,Vivado 2015.1";
begin
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 432;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03002040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"83480000";
when 16#0002D# => romdata <= X"8330600C";
when 16#0002E# => romdata <= X"80886001";
when 16#0002F# => romdata <= X"02800019";
when 16#00030# => romdata <= X"01000000";
when 16#00031# => romdata <= X"07000000";
when 16#00032# => romdata <= X"8610E118";
when 16#00033# => romdata <= X"C108C000";
when 16#00034# => romdata <= X"C118C000";
when 16#00035# => romdata <= X"C518C000";
when 16#00036# => romdata <= X"C918C000";
when 16#00037# => romdata <= X"CD18C000";
when 16#00038# => romdata <= X"D118C000";
when 16#00039# => romdata <= X"D518C000";
when 16#0003A# => romdata <= X"D918C000";
when 16#0003B# => romdata <= X"DD18C000";
when 16#0003C# => romdata <= X"E118C000";
when 16#0003D# => romdata <= X"E518C000";
when 16#0003E# => romdata <= X"E918C000";
when 16#0003F# => romdata <= X"ED18C000";
when 16#00040# => romdata <= X"F118C000";
when 16#00041# => romdata <= X"F518C000";
when 16#00042# => romdata <= X"F918C000";
when 16#00043# => romdata <= X"10800005";
when 16#00044# => romdata <= X"FD18C000";
when 16#00045# => romdata <= X"01000000";
when 16#00046# => romdata <= X"00000000";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"87444000";
when 16#00049# => romdata <= X"8730E01C";
when 16#0004A# => romdata <= X"8688E00F";
when 16#0004B# => romdata <= X"1280000A";
when 16#0004C# => romdata <= X"03200000";
when 16#0004D# => romdata <= X"05040E00";
when 16#0004E# => romdata <= X"8410A033";
when 16#0004F# => romdata <= X"C4204000";
when 16#00050# => romdata <= X"05000005";
when 16#00051# => romdata <= X"8410A25A";
when 16#00052# => romdata <= X"C4206004";
when 16#00053# => romdata <= X"050003FC";
when 16#00054# => romdata <= X"C4206008";
when 16#00055# => romdata <= X"05000008";
when 16#00056# => romdata <= X"82100000";
when 16#00057# => romdata <= X"80A0E000";
when 16#00058# => romdata <= X"02800005";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"82004002";
when 16#0005B# => romdata <= X"10BFFFFC";
when 16#0005C# => romdata <= X"8620E001";
when 16#0005D# => romdata <= X"3D103FFF";
when 16#0005E# => romdata <= X"BC17A3E0";
when 16#0005F# => romdata <= X"BC278001";
when 16#00060# => romdata <= X"9C27A060";
when 16#00061# => romdata <= X"03100000";
when 16#00062# => romdata <= X"81C04000";
when 16#00063# => romdata <= X"01000000";
when 16#00064# => romdata <= X"01000000";
when 16#00065# => romdata <= X"01000000";
when 16#00066# => romdata <= X"01000000";
when 16#00067# => romdata <= X"01000000";
when 16#00068# => romdata <= X"00000000";
when 16#00069# => romdata <= X"00000000";
when 16#0006A# => romdata <= X"00000000";
when 16#0006B# => romdata <= X"00000000";
when 16#0006C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
entity tb is
end;
architecture rtl of tb is
component top is
port( clk : in std_logic;
reset : in std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(1 downto 0);
hs : out std_logic;
vs : out std_logic);
end component;
signal clk : std_logic;
signal reset : std_logic;
signal red : std_logic_vector(2 downto 0);
signal green : std_logic_vector(2 downto 0);
signal blue : std_logic_vector(1 downto 0);
signal hs : std_logic;
signal vs : std_logic;
begin
top_0: top
port map (clk, reset, red, green, blue, hs, vs);
clk_gen:
process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
reset_gen:
process
begin
reset <= '1';
wait for 10 ns;
reset <= '0';
wait;
end process;
end rtl;
|
package pkg is
procedure proc(length : integer);
end package;
package body pkg is
procedure proc(length : integer) is
-- Runtime error
variable bv : bit_vector(length-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
end procedure;
end package body;
use work.pkg.all;
entity issue200 is
end entity;
architecture a of issue200 is
begin
main : process
-- Static error
variable bv : bit_vector(-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
proc(0);
wait;
end process;
end architecture;
|
package pkg is
procedure proc(length : integer);
end package;
package body pkg is
procedure proc(length : integer) is
-- Runtime error
variable bv : bit_vector(length-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
end procedure;
end package body;
use work.pkg.all;
entity issue200 is
end entity;
architecture a of issue200 is
begin
main : process
-- Static error
variable bv : bit_vector(-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
proc(0);
wait;
end process;
end architecture;
|
package pkg is
procedure proc(length : integer);
end package;
package body pkg is
procedure proc(length : integer) is
-- Runtime error
variable bv : bit_vector(length-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
end procedure;
end package body;
use work.pkg.all;
entity issue200 is
end entity;
architecture a of issue200 is
begin
main : process
-- Static error
variable bv : bit_vector(-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
proc(0);
wait;
end process;
end architecture;
|
package pkg is
procedure proc(length : integer);
end package;
package body pkg is
procedure proc(length : integer) is
-- Runtime error
variable bv : bit_vector(length-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
end procedure;
end package body;
use work.pkg.all;
entity issue200 is
end entity;
architecture a of issue200 is
begin
main : process
-- Static error
variable bv : bit_vector(-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
proc(0);
wait;
end process;
end architecture;
|
package pkg is
procedure proc(length : integer);
end package;
package body pkg is
procedure proc(length : integer) is
-- Runtime error
variable bv : bit_vector(length-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
end procedure;
end package body;
use work.pkg.all;
entity issue200 is
end entity;
architecture a of issue200 is
begin
main : process
-- Static error
variable bv : bit_vector(-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
proc(0);
wait;
end process;
end architecture;
|
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := (
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"),
(name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
begin
proc_label : process
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
begin end process;
end architecture rtl;
architecture rtl of fifo is
constant avmm_master_null : avmm_master_t := (
(others => '0'),
(others => '0'),
'0',
'0'
);
begin end architecture rtl;
architecture rtl of fifo is
constant cons1 : t_type := (
1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(
G_GENERIC3
)
)
)
)
);
constant cons1 : t_type := (1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(G_GENERIC3))
))
);
constant cons1 : t_type := (1 => func1(G_GENERIC1, G_GENERIC2),
2 => func2(func3(func4(
func5(G_GENERIC3))
)));
constant cons1 : t_type :=
(
1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(
G_GENERIC3
)
)
)
)
);
begin end architecture rtl;
architecture rtl of fifo is
constant cons1 : t_type := '0';
constant cons2 : t_type := '0' and '1'
and '0' or '1';
constant cons2 : t_type := func1(G_GENERIC1, G_GENERIC_2,
func2(G_GENERIC3));
begin end architecture rtl;
|
-------------------------------------------------------------------------------
--! @file nf_top.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-02-24
--! @brief FGClite NanoFIP FPGA (NF) top-level.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.nf_top_pkg.all;
--! @brief Entity declaration of nf_top
--! @details
--! The top-level component for the NanoFIP FPGA implementation.
entity nf_top is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! @}
--! @name NanoFIP core
--! @{
--! The FGClite station ID
subs_i : in std_ulogic_vector(4 downto 0);
--! Fieldrive reception activity detection
fd_rxcdn_i : in std_ulogic;
--! Fieldrive receiver data
fd_rxd_i : in std_ulogic;
--! Fieldrive transmitter error
fd_txer_i : in std_ulogic;
--! Fieldrive watchdog on transmitter
fd_wdgn_i : in std_ulogic;
--! Push-button reset
rstin_i : in std_ulogic;
--! Power-on reset
rstpon_i : inout std_logic;
--! JTAG TDO
jc_tdo_i : in std_ulogic;
--! Fieldrive reset
fd_rstn_o : out std_ulogic;
--! Fieldrive transmitter clock
fd_txck_o : out std_ulogic;
--! Fieldrive transmitter data
fd_txd_o : out std_ulogic;
--! Fieldrive transmitter enable
fd_txena_o : out std_ulogic;
--! Reset output (FGClite power cycle to PF)
rston_o : out std_ulogic;
--! NanoFIP status byte - bit 5
r_fcser_o : out std_ulogic;
--! NanoFIP status byte - bit 4
r_tler_o : out std_ulogic;
--! NanoFIP status byte - bit 2
u_cacer_o : out std_ulogic;
--! NanoFIP status byte - bit 3
u_pacer_o : out std_ulogic;
--! JTAG TMS
jc_tms_o : out std_ulogic;
--! JTAG TDI
jc_tdi_o : out std_ulogic;
--! JTAG TCK
jc_tck_o : out std_ulogic;
--! @}
--! @name NanoFIP extensions
--! @{
--! JTAG TRST
jc_trst_o : out std_ulogic;
--! CF and XF reset
cfxf_rst_n_o : out std_ulogic;
--! CMD 0 was received
cmd_0_o : out std_ulogic;
--! VAR3 (TX buffer) can be accessed
tx_rdy_o : out std_ulogic;
--! PF inhibit
pf_inh_n_o : out std_ulogic;
--! @}
--! @name 3-wire serial receiver from CF
--! @{
--! Frame
cf_rx_frame_i : in std_ulogic;
--! Bit enable
cf_rx_bit_en_i : in std_ulogic;
--! Data
cf_rx_i : in std_ulogic;
--! @}
--! @name 3-wire serial transmitter to CF
--! @{
--! Frame
cf_tx_frame_o : out std_ulogic;
--! Bit enable
cf_tx_bit_en_o : out std_ulogic;
--! Data
cf_tx_o : out std_ulogic;
--! @}
--! @name Debugging
--! @{
--! Serial receiver
debug_rx_i : in std_ulogic;
--! Serial transmitter
debug_tx_o : out std_ulogic;
--! Debugging probe
debug_probe_o : out std_ulogic);
--! @}
end entity nf_top;
--! RTL implementation of nf_top
architecture rtl of nf_top is
---------------------------------------------------------------------------
--! @name Internal Wires
---------------------------------------------------------------------------
--! @{
-- Safe reset generation
signal rstpon : std_ulogic;
signal nanofip_rst : std_ulogic;
signal rst : std_ulogic;
-- Input synchronization and glitch filter
signal station_id_syn : std_ulogic_vector(4 downto 0);
signal cf_rx_frame_syn : std_ulogic;
signal cf_rx_bit_en_syn : std_ulogic;
signal cf_rx_syn : std_ulogic;
signal debug_rx_syn : std_ulogic;
-- NanoFIP core
signal var1_rdy : std_ulogic;
signal var1_acc : std_ulogic;
signal var2_rdy : std_ulogic;
signal var2_acc : std_ulogic;
signal var3_rdy : std_ulogic;
signal var3_acc : std_ulogic;
signal nf_wb_rst : std_ulogic;
signal nf_wb_addr : std_ulogic_vector(9 downto 0);
signal nf_wb_data_rx : std_ulogic_vector(7 downto 0);
signal nf_wb_data_tx : std_ulogic_vector(7 downto 0);
signal nf_wb_we : std_ulogic;
signal nf_wb_stb : std_ulogic;
signal nf_wb_cyc : std_ulogic;
signal nf_wb_ack : std_ulogic;
-- NanoFIP Wishbone interface
signal wb_if_rx_var1_rdy : std_ulogic;
signal wb_if_rx_var2_rdy : std_ulogic;
signal wb_if_rx_var_sel : std_ulogic;
signal wb_if_rx_addr : std_ulogic_vector(6 downto 0);
signal wb_if_rx_en : std_ulogic;
signal wb_if_rx_data : std_ulogic_vector(7 downto 0);
signal wb_if_rx_data_en : std_ulogic;
signal wb_if_tx_addr : std_ulogic_vector(6 downto 0);
signal wb_if_tx_en : std_ulogic;
signal wb_if_tx_data : std_ulogic_vector(7 downto 0);
signal wb_if_err_rw_coll : std_ulogic;
signal wb_if_err_bsy : std_ulogic;
signal wb_if_err_not_rdy : std_ulogic;
signal wb_if_err_timeout : std_ulogic;
-- NanoFIP extensions
signal jtag_trst : std_ulogic;
signal cmd_0 : std_ulogic;
-- VAR1 receiver
signal var1_rx_addr : std_ulogic_vector(6 downto 0);
signal var1_rx_en : std_ulogic;
signal var1_rx_data : std_ulogic_vector(7 downto 0);
signal var1_rx_data_en : std_ulogic;
-- VAR2 receiver
signal var2_rx_addr : std_ulogic_vector(6 downto 0);
signal var2_rx_en : std_ulogic;
signal var2_rx_data : std_ulogic_vector(7 downto 0);
signal var2_rx_data_en : std_ulogic;
-- 3-wire serial receiver from CF
signal cf_rx_data : std_ulogic_vector(14 downto 0);
signal cf_rx_data_en : std_ulogic;
-- 3-wire serial transmitter to CF
signal cf_tx_data : std_ulogic_vector(39 downto 0);
signal cf_tx_data_en : std_ulogic;
signal cf_tx_busy : std_ulogic;
-- Debugging
signal debug_tx_data : std_ulogic_vector(7 downto 0);
signal debug_tx_data_en : std_ulogic;
signal debug_tx_done : std_ulogic;
--! @}
begin -- architecture rtl
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
tx_rdy_o <= var3_rdy;
cmd_0_o <= cmd_0;
cfxf_rst_n_o <= not rst;
pf_inh_n_o <= jtag_trst;
jc_trst_o <= jtag_trst;
debug_probe_o <= cmd_0;
---------------------------------------------------------------------------
-- Signal Assignments
---------------------------------------------------------------------------
wb_if_tx_addr <= cf_rx_data(14 downto 8);
wb_if_tx_data <= cf_rx_data(7 downto 0);
wb_if_tx_en <= cf_rx_data_en;
wb_if_rx_addr <= var1_rx_addr when wb_if_rx_var_sel = '0' else var2_rx_addr;
wb_if_rx_en <= var1_rx_en when wb_if_rx_var_sel = '0' else var2_rx_en;
var1_rx_data <= wb_if_rx_data;
var1_rx_data_en <= wb_if_rx_data_en when wb_if_rx_var_sel = '0' else '0';
var2_rx_data <= wb_if_rx_data;
var2_rx_data_en <= wb_if_rx_data_en when wb_if_rx_var_sel = '1' else '0';
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! Power-on reset generation for Microsemi devices
po_reset_inst : entity work.microsemi_reset_generator
generic map (
num_delay_g => 4,
active_g => '0')
port map (
clk_i => clk_i,
rst_asy_io => rstpon_i,
rst_o => rstpon);
--! Safe reset generation for logic except NanoFIP core
nf_reset_inst : entity work.reset_generator
generic map (
num_delay_g => 16,
active_g => '1')
port map (
clk_i => clk_i,
rst_asy_i => nanofip_rst,
rst_o => rst);
--! Input synchronization and glitch filter for serial receiver
ext_inputs_inst_0 : entity work.external_inputs
generic map (
init_value_g => '0',
num_inputs_g => 4)
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
sig_i(0) => cf_rx_frame_i,
sig_i(1) => cf_rx_bit_en_i,
sig_i(2) => cf_rx_i,
sig_i(3) => debug_rx_i,
sig_o(0) => cf_rx_frame_syn,
sig_o(1) => cf_rx_bit_en_syn,
sig_o(2) => cf_rx_syn,
sig_o(3) => debug_rx_syn);
--! Input synchronization and glitch filter for station ID
ext_inputs_inst_1 : entity work.external_inputs
generic map (
init_value_g => '0',
num_inputs_g => subs_i'length)
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
sig_i => subs_i,
sig_o => station_id_syn);
--! NanoFIP core
nanofip_inst: entity work.nanofip
port map (
nanofip_rst_o => nanofip_rst,
c_id_i => "0001",
m_id_i => "0001",
p3_lgth_i => "101",
rate_i => "10",
subs_i(4 downto 0) => std_logic_vector(subs_i),
subs_i(7 downto 5) => "000",
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
nostat_i => '0',
rstin_i => rstin_i,
rstpon_i => rstpon,
slone_i => '0',
uclk_i => clk_i,
var1_acc_i => var1_acc,
var2_acc_i => var2_acc,
var3_acc_i => var3_acc,
wclk_i => clk_i,
adr_i => std_logic_vector(nf_wb_addr),
cyc_i => nf_wb_cyc,
dat_i(7 downto 0) => std_logic_vector(nf_wb_data_tx),
dat_i(15 downto 8) => x"00",
rst_i => nf_wb_rst,
stb_i => nf_wb_stb,
we_i => nf_wb_we,
jc_tdo_i => jc_tdo_i,
--s_id_o => open, -- UNUSED: Information is not used anywhere
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena_o,
rston_o => rston_o,
r_fcser_o => r_fcser_o,
r_tler_o => r_tler_o,
u_cacer_o => u_cacer_o,
u_pacer_o => u_pacer_o,
var1_rdy_o => var1_rdy,
var2_rdy_o => var2_rdy,
var3_rdy_o => var3_rdy,
std_ulogic_vector(dat_o) => nf_wb_data_rx,
ack_o => nf_wb_ack,
jc_tms_o => jc_tms_o,
jc_tdi_o => jc_tdi_o,
jc_tck_o => jc_tck_o);
--! NanoFIP Wishbone interface
nanofip_wb_if_inst : entity work.nanofip_wb_if
generic map (
watchdog_max_g => 32)
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
var1_rdy_i => var1_rdy,
var1_acc_o => var1_acc,
var2_rdy_i => var2_rdy,
var2_acc_o => var2_acc,
var3_rdy_i => var3_rdy,
var3_acc_o => var3_acc,
wb_clk_o => open,
wb_rst_o => nf_wb_rst,
wb_addr_o => nf_wb_addr,
wb_data_i => nf_wb_data_rx,
wb_data_o => nf_wb_data_tx,
wb_we_o => nf_wb_we,
wb_stb_o => nf_wb_stb,
wb_cyc_o => nf_wb_cyc,
wb_ack_i => nf_wb_ack,
rx_var1_rdy_o => wb_if_rx_var1_rdy,
rx_var2_rdy_o => wb_if_rx_var2_rdy,
rx_var_sel_i => wb_if_rx_var_sel,
rx_addr_i => wb_if_rx_addr,
rx_en_i => wb_if_rx_en,
rx_data_o => wb_if_rx_data,
rx_data_en_o => wb_if_rx_data_en,
tx_rdy_o => open, -- UNUSED: CF knows when VAR3 is ready
tx_addr_i => wb_if_tx_addr,
tx_en_i => wb_if_tx_en,
tx_data_i => wb_if_tx_data,
tx_done_o => open, -- UNUSED: Serial receiver is slower than Wishbone interface
err_rw_coll_o => wb_if_err_rw_coll,
err_bsy_o => wb_if_err_bsy,
err_not_rdy_o => wb_if_err_not_rdy,
err_timeout_o => wb_if_err_timeout);
--! Receiver VAR select
rx_var_sel_inst : entity work.rx_var_select
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
var1_rdy_i => wb_if_rx_var1_rdy,
var2_rdy_i => wb_if_rx_var2_rdy,
var_select_o => wb_if_rx_var_sel);
--! VAR1 receiver
var1_rx_inst : entity work.var1_rx
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
rx_rdy_i => wb_if_rx_var1_rdy,
rx_addr_o => var1_rx_addr,
rx_en_o => var1_rx_en,
rx_data_i => var1_rx_data,
rx_data_en_i => var1_rx_data_en,
jtag_trst_o => jtag_trst,
err_rw_coll_i => wb_if_err_rw_coll,
err_bsy_i => wb_if_err_bsy,
err_not_rdy_i => wb_if_err_not_rdy,
err_timeout_i => wb_if_err_timeout);
--! VAR2 receiver
var2_rx_inst : entity work.var2_rx
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
station_id_i => station_id_syn,
cmd_0_o => cmd_0,
rx_rdy_i => wb_if_rx_var2_rdy,
rx_addr_o => var2_rx_addr,
rx_en_o => var2_rx_en,
rx_data_i => var2_rx_data,
rx_data_en_i => var2_rx_data_en,
tx_data_o => cf_tx_data,
tx_data_en_o => cf_tx_data_en,
tx_bsy_i => cf_tx_busy,
err_rw_coll_i => wb_if_err_rw_coll,
err_bsy_i => wb_if_err_bsy,
err_not_rdy_i => wb_if_err_not_rdy,
err_timeout_i => wb_if_err_timeout);
--! 3-wire serial receiver from CF
cf_rx_inst : entity work.serial_3wire_rx
generic map (
data_width_g => 15)
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
rx_frame_i => cf_rx_frame_syn,
rx_bit_en_i => cf_rx_bit_en_syn,
rx_i => cf_rx_syn,
data_o => cf_rx_data,
data_en_o => cf_rx_data_en,
error_o => open); -- UNUSED: CF can't be notified of errors anyway
--! 3-wire serial transmitter to CF
cf_tx_inst : entity work.serial_3wire_tx
generic map (
data_width_g => 44,
num_ticks_g => 6)
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
data_i(43 downto 40) => NF_VERSION_c,
data_i(39 downto 0) => cf_tx_data,
data_en_i => cf_tx_data_en,
busy_o => cf_tx_busy,
done_o => open,
tx_frame_o => cf_tx_frame_o,
tx_bit_en_o => cf_tx_bit_en_o,
tx_o => cf_tx_o);
--! Serial debugging receiver
debug_rx_inst : entity work.uart_rx
generic map (
data_width_g => 8,
parity_g => 0,
stop_bits_g => 1,
num_ticks_g => 156)
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
rx_i => debug_rx_syn,
data_o => open,
data_en_o => open,
error_o => open);
--! Serial debugging transmitter
debug_tx_inst : entity work.uart_tx
generic map (
data_width_g => 8,
parity_g => 0,
stop_bits_g => 1,
num_ticks_g => 156)
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
data_i => debug_tx_data,
data_en_i => debug_tx_data_en,
busy_o => open,
done_o => debug_tx_done,
tx_o => debug_tx_o);
--! Debugging packet transmitter
debug_array_tx_inst : entity work.array_tx
generic map (
data_count_g => 5,
data_width_g => 8)
port map (
clk_i => clk_i,
rst_asy_n_i => '1',
rst_syn_i => rst,
data_i => cf_tx_data,
data_en_i => cf_tx_data_en,
busy_o => open,
done_o => open,
tx_data_o => debug_tx_data,
tx_data_en_o => debug_tx_data_en,
tx_done_i => debug_tx_done);
end architecture rtl;
|
--
-- SpaceWire Transmitter
--
-- This entity translates outgoing characters and tokens into
-- data-strobe signalling.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spwpkg.all;
entity spwxmit is
port (
-- System clock.
clk: in std_logic;
-- Synchronous reset (active-high).
rst: in std_logic;
-- Scaling factor minus 1, used to scale the system clock into the
-- transmission bit rate. The system clock is divided by
-- (unsigned(divcnt) + 1). Changing this signal will immediately
-- change the transmission rate.
divcnt: in std_logic_vector(7 downto 0);
-- Input signals from spwlink.
xmiti: in spw_xmit_in_type;
-- Output signals to spwlink.
xmito: out spw_xmit_out_type;
-- Data Out signal to SpaceWire bus.
spw_do: out std_logic;
-- Strobe Out signal to SpaceWire bus.
spw_so: out std_logic
);
end entity spwxmit;
architecture spwxmit_arch of spwxmit is
-- Registers
type regs_type is record
-- tx clock
txclken: std_ulogic; -- high if a bit must be transmitted
txclkcnt: unsigned(7 downto 0);
-- output shift register
bitshift: std_logic_vector(12 downto 0);
bitcnt: unsigned(3 downto 0);
-- output signals
out_data: std_ulogic;
out_strobe: std_ulogic;
-- parity flag
parity: std_ulogic;
-- pending time tick
pend_tick: std_ulogic;
pend_time: std_logic_vector(7 downto 0);
-- transmitter mode
allow_fct: std_ulogic; -- allowed to send FCTs
allow_char: std_ulogic; -- allowed to send data and time
sent_null: std_ulogic; -- sent at least one NULL token
sent_fct: std_ulogic; -- sent at least one FCT token
end record;
-- Initial state
constant regs_reset: regs_type := (
txclken => '0',
txclkcnt => "00000000",
bitshift => (others => '0'),
bitcnt => "0000",
out_data => '0',
out_strobe => '0',
parity => '0',
pend_tick => '0',
pend_time => (others => '0'),
allow_fct => '0',
allow_char => '0',
sent_null => '0',
sent_fct => '0' );
-- Registers
signal r: regs_type := regs_reset;
signal rin: regs_type;
begin
-- Combinatorial process
process (r, rst, divcnt, xmiti) is
variable v: regs_type;
begin
v := r;
-- Generate TX clock.
if r.txclkcnt = 0 then
v.txclkcnt := unsigned(divcnt);
v.txclken := '1';
else
v.txclkcnt := r.txclkcnt - 1;
v.txclken := '0';
end if;
if xmiti.txen = '0' then
-- Transmitter disabled; reset state.
v.bitcnt := "0000";
v.parity := '0';
v.pend_tick := '0';
v.allow_fct := '0';
v.allow_char := '0';
v.sent_null := '0';
v.sent_fct := '0';
-- Gentle reset of spacewire bus signals
if r.txclken = '1' then
v.out_data := r.out_data and r.out_strobe;
v.out_strobe := '0';
end if;
else
-- Transmitter enabled.
v.allow_fct := (not xmiti.stnull) and r.sent_null;
v.allow_char := (not xmiti.stnull) and r.sent_null and
(not xmiti.stfct) and r.sent_fct;
-- On tick of transmission clock, put next bit on the output.
if r.txclken = '1' then
if r.bitcnt = 0 then
-- Need to start a new character.
if (r.allow_char = '1') and (r.pend_tick = '1') then
-- Send Time-Code.
v.out_data := r.parity;
v.bitshift(12 downto 5) := r.pend_time;
v.bitshift(4 downto 0) := "01111";
v.bitcnt := to_unsigned(13, v.bitcnt'length);
v.parity := '0';
v.pend_tick := '0';
elsif (r.allow_fct = '1') and (xmiti.fct_in = '1') then
-- Send FCT.
v.out_data := r.parity;
v.bitshift(2 downto 0) := "001";
v.bitcnt := to_unsigned(3, v.bitcnt'length);
v.parity := '1';
v.sent_fct := '1';
elsif (r.allow_char = '1') and (xmiti.txwrite = '1') then
-- Send N-Char.
v.bitshift(0) := xmiti.txflag;
v.parity := xmiti.txflag;
if xmiti.txflag = '0' then
-- Data byte
v.out_data := not r.parity;
v.bitshift(8 downto 1) := xmiti.txdata;
v.bitcnt := to_unsigned(9, v.bitcnt'length);
else
-- EOP or EEP
v.out_data := r.parity;
v.bitshift(1) := xmiti.txdata(0);
v.bitshift(2) := not xmiti.txdata(0);
v.bitcnt := to_unsigned(3, v.bitcnt'length);
end if;
else
-- Send NULL.
v.out_data := r.parity;
v.bitshift(6 downto 0) := "0010111";
v.bitcnt := to_unsigned(7, v.bitcnt'length);
v.parity := '0';
v.sent_null := '1';
end if;
else
-- Shift next bit to the output.
v.out_data := r.bitshift(0);
v.parity := r.parity xor r.bitshift(0);
v.bitshift(r.bitshift'high-1 downto 0) := r.bitshift(r.bitshift'high downto 1);
v.bitcnt := r.bitcnt - 1;
end if;
-- Data-Strobe encoding.
v.out_strobe := not (r.out_strobe xor r.out_data xor v.out_data);
end if;
-- Store requests for time tick transmission.
if xmiti.tick_in = '1' then
v.pend_tick := '1';
v.pend_time := xmiti.ctrl_in & xmiti.time_in;
end if;
end if;
-- Synchronous reset
if rst = '1' then
v := regs_reset;
end if;
-- Drive outputs.
-- Note: the outputs are combinatorially dependent on certain inputs.
-- Set fctack high if (transmitter enabled) AND
-- (ready for token) AND (FCTs allowed) AND
-- ((characters not allowed) OR (no timecode pending)) AND
-- (FCT requested)
if (xmiti.txen = '1') and
(r.txclken = '1') and (r.bitcnt = 0) and (r.allow_fct = '1') and
((r.allow_char = '0') or (r.pend_tick = '0')) then
xmito.fctack <= xmiti.fct_in;
else
xmito.fctack <= '0';
end if;
-- Set txrdy high if (transmitter enabled) AND
-- (ready for token) AND (characters enabled) AND
-- (no timecode pending) AND (no FCT requested) AND
-- (character requested)
if (xmiti.txen = '1') and
(r.txclken = '1') and (r.bitcnt = 0) and (r.allow_char = '1') and
(r.pend_tick = '0') and (xmiti.fct_in = '0') then
xmito.txack <= xmiti.txwrite;
else
xmito.txack <= '0';
end if;
-- Update registers
rin <= v;
end process;
-- Synchronous process
process (clk) is
begin
if rising_edge(clk) then
-- Update registers
r <= rin;
-- Drive spacewire output signals
spw_do <= r.out_data;
spw_so <= r.out_strobe;
end if;
end process;
end architecture spwxmit_arch;
|
--
-- SpaceWire Transmitter
--
-- This entity translates outgoing characters and tokens into
-- data-strobe signalling.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spwpkg.all;
entity spwxmit is
port (
-- System clock.
clk: in std_logic;
-- Synchronous reset (active-high).
rst: in std_logic;
-- Scaling factor minus 1, used to scale the system clock into the
-- transmission bit rate. The system clock is divided by
-- (unsigned(divcnt) + 1). Changing this signal will immediately
-- change the transmission rate.
divcnt: in std_logic_vector(7 downto 0);
-- Input signals from spwlink.
xmiti: in spw_xmit_in_type;
-- Output signals to spwlink.
xmito: out spw_xmit_out_type;
-- Data Out signal to SpaceWire bus.
spw_do: out std_logic;
-- Strobe Out signal to SpaceWire bus.
spw_so: out std_logic
);
end entity spwxmit;
architecture spwxmit_arch of spwxmit is
-- Registers
type regs_type is record
-- tx clock
txclken: std_ulogic; -- high if a bit must be transmitted
txclkcnt: unsigned(7 downto 0);
-- output shift register
bitshift: std_logic_vector(12 downto 0);
bitcnt: unsigned(3 downto 0);
-- output signals
out_data: std_ulogic;
out_strobe: std_ulogic;
-- parity flag
parity: std_ulogic;
-- pending time tick
pend_tick: std_ulogic;
pend_time: std_logic_vector(7 downto 0);
-- transmitter mode
allow_fct: std_ulogic; -- allowed to send FCTs
allow_char: std_ulogic; -- allowed to send data and time
sent_null: std_ulogic; -- sent at least one NULL token
sent_fct: std_ulogic; -- sent at least one FCT token
end record;
-- Initial state
constant regs_reset: regs_type := (
txclken => '0',
txclkcnt => "00000000",
bitshift => (others => '0'),
bitcnt => "0000",
out_data => '0',
out_strobe => '0',
parity => '0',
pend_tick => '0',
pend_time => (others => '0'),
allow_fct => '0',
allow_char => '0',
sent_null => '0',
sent_fct => '0' );
-- Registers
signal r: regs_type := regs_reset;
signal rin: regs_type;
begin
-- Combinatorial process
process (r, rst, divcnt, xmiti) is
variable v: regs_type;
begin
v := r;
-- Generate TX clock.
if r.txclkcnt = 0 then
v.txclkcnt := unsigned(divcnt);
v.txclken := '1';
else
v.txclkcnt := r.txclkcnt - 1;
v.txclken := '0';
end if;
if xmiti.txen = '0' then
-- Transmitter disabled; reset state.
v.bitcnt := "0000";
v.parity := '0';
v.pend_tick := '0';
v.allow_fct := '0';
v.allow_char := '0';
v.sent_null := '0';
v.sent_fct := '0';
-- Gentle reset of spacewire bus signals
if r.txclken = '1' then
v.out_data := r.out_data and r.out_strobe;
v.out_strobe := '0';
end if;
else
-- Transmitter enabled.
v.allow_fct := (not xmiti.stnull) and r.sent_null;
v.allow_char := (not xmiti.stnull) and r.sent_null and
(not xmiti.stfct) and r.sent_fct;
-- On tick of transmission clock, put next bit on the output.
if r.txclken = '1' then
if r.bitcnt = 0 then
-- Need to start a new character.
if (r.allow_char = '1') and (r.pend_tick = '1') then
-- Send Time-Code.
v.out_data := r.parity;
v.bitshift(12 downto 5) := r.pend_time;
v.bitshift(4 downto 0) := "01111";
v.bitcnt := to_unsigned(13, v.bitcnt'length);
v.parity := '0';
v.pend_tick := '0';
elsif (r.allow_fct = '1') and (xmiti.fct_in = '1') then
-- Send FCT.
v.out_data := r.parity;
v.bitshift(2 downto 0) := "001";
v.bitcnt := to_unsigned(3, v.bitcnt'length);
v.parity := '1';
v.sent_fct := '1';
elsif (r.allow_char = '1') and (xmiti.txwrite = '1') then
-- Send N-Char.
v.bitshift(0) := xmiti.txflag;
v.parity := xmiti.txflag;
if xmiti.txflag = '0' then
-- Data byte
v.out_data := not r.parity;
v.bitshift(8 downto 1) := xmiti.txdata;
v.bitcnt := to_unsigned(9, v.bitcnt'length);
else
-- EOP or EEP
v.out_data := r.parity;
v.bitshift(1) := xmiti.txdata(0);
v.bitshift(2) := not xmiti.txdata(0);
v.bitcnt := to_unsigned(3, v.bitcnt'length);
end if;
else
-- Send NULL.
v.out_data := r.parity;
v.bitshift(6 downto 0) := "0010111";
v.bitcnt := to_unsigned(7, v.bitcnt'length);
v.parity := '0';
v.sent_null := '1';
end if;
else
-- Shift next bit to the output.
v.out_data := r.bitshift(0);
v.parity := r.parity xor r.bitshift(0);
v.bitshift(r.bitshift'high-1 downto 0) := r.bitshift(r.bitshift'high downto 1);
v.bitcnt := r.bitcnt - 1;
end if;
-- Data-Strobe encoding.
v.out_strobe := not (r.out_strobe xor r.out_data xor v.out_data);
end if;
-- Store requests for time tick transmission.
if xmiti.tick_in = '1' then
v.pend_tick := '1';
v.pend_time := xmiti.ctrl_in & xmiti.time_in;
end if;
end if;
-- Synchronous reset
if rst = '1' then
v := regs_reset;
end if;
-- Drive outputs.
-- Note: the outputs are combinatorially dependent on certain inputs.
-- Set fctack high if (transmitter enabled) AND
-- (ready for token) AND (FCTs allowed) AND
-- ((characters not allowed) OR (no timecode pending)) AND
-- (FCT requested)
if (xmiti.txen = '1') and
(r.txclken = '1') and (r.bitcnt = 0) and (r.allow_fct = '1') and
((r.allow_char = '0') or (r.pend_tick = '0')) then
xmito.fctack <= xmiti.fct_in;
else
xmito.fctack <= '0';
end if;
-- Set txrdy high if (transmitter enabled) AND
-- (ready for token) AND (characters enabled) AND
-- (no timecode pending) AND (no FCT requested) AND
-- (character requested)
if (xmiti.txen = '1') and
(r.txclken = '1') and (r.bitcnt = 0) and (r.allow_char = '1') and
(r.pend_tick = '0') and (xmiti.fct_in = '0') then
xmito.txack <= xmiti.txwrite;
else
xmito.txack <= '0';
end if;
-- Update registers
rin <= v;
end process;
-- Synchronous process
process (clk) is
begin
if rising_edge(clk) then
-- Update registers
r <= rin;
-- Drive spacewire output signals
spw_do <= r.out_data;
spw_so <= r.out_strobe;
end if;
end process;
end architecture spwxmit_arch;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Wed Aug 17 14:15:47 2016
--Host : andrewandrepowell2-desktop running 64-bit Ubuntu 16.04 LTS
--Command : generate_target block_design_wrapper.bd
--Design : block_design_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity block_design_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
vga_b : out STD_LOGIC_VECTOR ( 4 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 5 downto 0 );
vga_hs : out STD_LOGIC;
vga_r : out STD_LOGIC_VECTOR ( 4 downto 0 );
vga_vs : out STD_LOGIC
);
end block_design_wrapper;
architecture STRUCTURE of block_design_wrapper is
component block_design is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
vga_b : out STD_LOGIC_VECTOR ( 4 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 5 downto 0 );
vga_r : out STD_LOGIC_VECTOR ( 4 downto 0 );
vga_hs : out STD_LOGIC;
vga_vs : out STD_LOGIC
);
end component block_design;
begin
block_design_i: component block_design
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
vga_b(4 downto 0) => vga_b(4 downto 0),
vga_g(5 downto 0) => vga_g(5 downto 0),
vga_hs => vga_hs,
vga_r(4 downto 0) => vga_r(4 downto 0),
vga_vs => vga_vs
);
end STRUCTURE;
|
entity Latch is
port (
Din: in Word;
Dout: out Word;
Load: in Bit;
Clk: in Bit);
constant Setup: Time := 12 ns;
constant PulseWidth: Time := 50 ns;
use Work.TimingMonitors.all;
begin
assert Clk='1' or Clk'Delayed'Stable (PulseWidth);
CheckTiming (Setup, Din, Load, Clk);
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:21:30 03/04/2017
-- Design Name:
-- Module Name: gal_progcounter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity gal_progcounter is
Port ( reset : in STD_LOGIC;
clock : in STD_LOGIC;
macro_i : in STD_LOGIC_VECTOR (7 downto 0);
execute : in STD_LOGIC;
branch : in STD_LOGIC;
callorreturn: in STD_LOGIC;
pc : buffer STD_LOGIC_VECTOR (9 downto 0));
end gal_progcounter;
architecture Behavioral of gal_progcounter is
type mem4x10 is array (0 to 3) of std_logic_vector(9 downto 0);
signal branchoffset: std_logic_vector(9 downto 0);
signal stack: mem4x10;
signal sp: integer range 0 to 3;
begin
branchoffset <= "00" & macro_i when (macro_i(7) = '0') else "11" & macro_i;
pc <= stack(sp);
update_pc: process(reset, clock, execute, branch)
begin
if (reset = '1') then
stack(0) <= "0000000000";
sp <= 0;
else
if (rising_edge(clock)) then
if (execute = '1') then
-- CONTINUE
stack(sp) <= std_logic_vector(unsigned(stack(sp)) + 1);
else
if (callorreturn = '1') then
if (branch = '1') then
-- CALL
stack(sp + 1) <= std_logic_vector(unsigned(stack(sp)) + unsigned(branchoffset));
sp <= sp + 1;
else
-- RETURN
stack(sp - 1) <= std_logic_vector(unsigned(stack(sp - 1)) + unsigned(branchoffset));
sp <= sp - 1;
end if;
else
if (branch = '1') then
-- BRANCH
stack(sp) <= std_logic_vector(unsigned(stack(sp)) + unsigned(branchoffset));
else
-- DO NOT BRANCH
stack(sp) <= std_logic_vector(unsigned(stack(sp)) + 1);
end if;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-- megafunction wizard: %LPM_DIVIDE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_DIVIDE
-- ============================================================
-- File Name: Divider.vhd
-- Megafunction Name(s):
-- LPM_DIVIDE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 173 11/01/2011 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY Divider IS
PORT
(
denom : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
remain : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END Divider;
ARCHITECTURE SYN OF divider IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT lpm_divide
GENERIC (
lpm_drepresentation : STRING;
lpm_hint : STRING;
lpm_nrepresentation : STRING;
lpm_type : STRING;
lpm_widthd : NATURAL;
lpm_widthn : NATURAL
);
PORT (
denom : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
remain : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
quotient <= sub_wire0(31 DOWNTO 0);
remain <= sub_wire1(31 DOWNTO 0);
LPM_DIVIDE_component : LPM_DIVIDE
GENERIC MAP (
lpm_drepresentation => "UNSIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
lpm_nrepresentation => "UNSIGNED",
lpm_type => "LPM_DIVIDE",
lpm_widthd => 32,
lpm_widthn => 32
)
PORT MAP (
denom => denom,
numer => numer,
quotient => sub_wire0,
remain => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
-- Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
-- Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
-- Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32"
-- Retrieval info: USED_PORT: denom 0 0 32 0 INPUT NODEFVAL "denom[31..0]"
-- Retrieval info: USED_PORT: numer 0 0 32 0 INPUT NODEFVAL "numer[31..0]"
-- Retrieval info: USED_PORT: quotient 0 0 32 0 OUTPUT NODEFVAL "quotient[31..0]"
-- Retrieval info: USED_PORT: remain 0 0 32 0 OUTPUT NODEFVAL "remain[31..0]"
-- Retrieval info: CONNECT: @denom 0 0 32 0 denom 0 0 32 0
-- Retrieval info: CONNECT: @numer 0 0 32 0 numer 0 0 32 0
-- Retrieval info: CONNECT: quotient 0 0 32 0 @quotient 0 0 32 0
-- Retrieval info: CONNECT: remain 0 0 32 0 @remain 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Divider.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Divider.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Divider.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Divider.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Divider_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity SeqDetector is
port( CLOCK_50 : in std_logic;
SW : in std_logic_vector(0 downto 0);
LEDR : out std_logic_vector(0 downto 0);
LEDG : out std_logic_vector(0 downto 0));
end SeqDetector;
architecture Shell of SeqDetector is
signal s_clk : std_logic;
begin
LEDG(0) <= s_clk;
clk_div: entity Work.ClkDividerN(Behavioral)
generic map(divFactor => 200000000)
port map(reset => '0',
clkIn => CLOCK_50,
clkOut=> s_clk);
seqdetFSM_mealy: entity Work.SeqDetFSM(MealyArch)
port map(xin => SW(0),
yout => LEDR(0),
clk => s_clk);
end Shell; |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_10 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_10 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(10, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_10 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_10 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(10, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_10 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_10 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(10, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_10 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_10 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(10, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_10 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_10 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(10, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:57:17 11/20/2014
-- Design Name:
-- Module Name: ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ctrl is
Port (
rst : in STD_ULOGIC;
clk : in STD_ULOGIC;
rot_c : in STD_ULOGIC;
btn_east : in STD_ULOGIC;
btn_west : in STD_ULOGIC;
btn_north : in STD_ULOGIC;
sw : in STD_ULOGIC_VECTOR (3 downto 0);
op1 : out STD_ULOGIC_VECTOR (3 downto 0);
op2 : out STD_ULOGIC_VECTOR (3 downto 0);
op : out STD_ULOGIC_VECTOR (2 downto 0));
end ctrl;
architecture Behavioral of ctrl is
type state is (s_start, s_op1, s_op2, s_add, s_sub, s_mult);
signal c_st : state;
signal n_st : state;
signal rot_c_prev : STD_ULOGIC;
signal op1_ff : STD_ULOGIC_VECTOR (3 downto 0);
signal op2_ff : STD_ULOGIC_VECTOR (3 downto 0);
begin
-- memorizing process
p_seq: process (rst, clk)
begin
if rst = '1' then
c_st <= s_start;
rot_c_prev <= '0';
elsif rising_edge(clk) then
c_st <= n_st;
rot_c_prev <= rot_c;
op1 <= op1_ff;
op2 <= op2_ff;
else
c_st <= c_st;
rot_c_prev <= rot_c_prev;
end if;
end process;
-- memoryless process
p_com: process (rst, rot_c, btn_east, btn_west, btn_north, sw, c_st)
begin
-- default assignments
n_st <= c_st; -- remain in current state
op1_ff <= "0000"; --
op2_ff <= "0000"; --
op <= "000"; --
-- specific assignments
case c_st is
when s_start =>
if rot_c = '1' and rot_c_prev = '0' then
n_st <= s_op1;
else
n_st <= c_st;
end if;
op1_ff <= "0000";
op2_ff <= "0000";
op <= "000";
when s_op1 =>
if rot_c = '1' and rot_c_prev = '0' then
n_st <= s_op2;
else
n_st <= c_st;
end if;
op1_ff <= sw;
op2_ff <= "0000";
op <= "001"; -- display op1
when s_op2 =>
if btn_west = '1' then
n_st <= s_add;
elsif btn_east = '1' then
n_st <= s_sub;
elsif btn_north = '1' then
n_st <= s_mult;
else
n_st <= c_st;
end if;
op1_ff <= op1_ff;
op2_ff <= sw;
op <= "010"; -- display op2
when s_add =>
if rst = '1' then
n_st <= s_start;
else
n_st <= c_st;
end if;
op1_ff <= op1_ff;
op2_ff <= op2_ff;
op <= "011"; -- add
when s_sub =>
if rst = '1' then
n_st <= s_start;
else
n_st <= c_st;
end if;
op1_ff <= op1_ff;
op2_ff <= op2_ff;
op <= "100"; -- sub
when s_mult =>
if rst = '1' then
n_st <= s_start;
else
n_st <= c_st;
end if;
op1_ff <= op1_ff;
op2_ff <= op2_ff;
op <= "101"; -- mul
when others =>
n_st <= s_start; -- undefined state -> reset to start
op1_ff <= "0000";
op2_ff <= "0000";
op <= "000";
end case;
end process;
end Behavioral;
|
entity operator3 is
end entity;
architecture test of operator3 is
type int_array is array (integer range <>) of integer;
begin
process is
variable x : int_array(1 to 3);
variable y : bit_vector(1 to 3);
begin
x := (1, 2, 3);
assert x < (2, 2, 3);
assert x > (0, 0, 0);
assert x < (1, 2, 4);
assert x < (1, 2, 3, 4);
assert not (x < (1, 2));
assert x <= (1, 2, 3);
assert x >= (1, 2, 3);
assert x >= (1, 1, 1);
y := "000";
assert not (y < "000");
assert not (y < "00");
assert not ("000" < y);
assert "00" < y;
assert y <= "000";
assert not (y <= "00");
assert "000" <= y;
assert "00" <= y;
assert not (y > "000");
assert not ("000" > y);
assert y > "00";
assert not ("00" > y);
wait;
end process;
end architecture;
|
entity operator3 is
end entity;
architecture test of operator3 is
type int_array is array (integer range <>) of integer;
begin
process is
variable x : int_array(1 to 3);
variable y : bit_vector(1 to 3);
begin
x := (1, 2, 3);
assert x < (2, 2, 3);
assert x > (0, 0, 0);
assert x < (1, 2, 4);
assert x < (1, 2, 3, 4);
assert not (x < (1, 2));
assert x <= (1, 2, 3);
assert x >= (1, 2, 3);
assert x >= (1, 1, 1);
y := "000";
assert not (y < "000");
assert not (y < "00");
assert not ("000" < y);
assert "00" < y;
assert y <= "000";
assert not (y <= "00");
assert "000" <= y;
assert "00" <= y;
assert not (y > "000");
assert not ("000" > y);
assert y > "00";
assert not ("00" > y);
wait;
end process;
end architecture;
|
entity operator3 is
end entity;
architecture test of operator3 is
type int_array is array (integer range <>) of integer;
begin
process is
variable x : int_array(1 to 3);
variable y : bit_vector(1 to 3);
begin
x := (1, 2, 3);
assert x < (2, 2, 3);
assert x > (0, 0, 0);
assert x < (1, 2, 4);
assert x < (1, 2, 3, 4);
assert not (x < (1, 2));
assert x <= (1, 2, 3);
assert x >= (1, 2, 3);
assert x >= (1, 1, 1);
y := "000";
assert not (y < "000");
assert not (y < "00");
assert not ("000" < y);
assert "00" < y;
assert y <= "000";
assert not (y <= "00");
assert "000" <= y;
assert "00" <= y;
assert not (y > "000");
assert not ("000" > y);
assert y > "00";
assert not ("00" > y);
wait;
end process;
end architecture;
|
entity operator3 is
end entity;
architecture test of operator3 is
type int_array is array (integer range <>) of integer;
begin
process is
variable x : int_array(1 to 3);
variable y : bit_vector(1 to 3);
begin
x := (1, 2, 3);
assert x < (2, 2, 3);
assert x > (0, 0, 0);
assert x < (1, 2, 4);
assert x < (1, 2, 3, 4);
assert not (x < (1, 2));
assert x <= (1, 2, 3);
assert x >= (1, 2, 3);
assert x >= (1, 1, 1);
y := "000";
assert not (y < "000");
assert not (y < "00");
assert not ("000" < y);
assert "00" < y;
assert y <= "000";
assert not (y <= "00");
assert "000" <= y;
assert "00" <= y;
assert not (y > "000");
assert not ("000" > y);
assert y > "00";
assert not ("00" > y);
wait;
end process;
end architecture;
|
entity operator3 is
end entity;
architecture test of operator3 is
type int_array is array (integer range <>) of integer;
begin
process is
variable x : int_array(1 to 3);
variable y : bit_vector(1 to 3);
begin
x := (1, 2, 3);
assert x < (2, 2, 3);
assert x > (0, 0, 0);
assert x < (1, 2, 4);
assert x < (1, 2, 3, 4);
assert not (x < (1, 2));
assert x <= (1, 2, 3);
assert x >= (1, 2, 3);
assert x >= (1, 1, 1);
y := "000";
assert not (y < "000");
assert not (y < "00");
assert not ("000" < y);
assert "00" < y;
assert y <= "000";
assert not (y <= "00");
assert "000" <= y;
assert "00" <= y;
assert not (y > "000");
assert not ("000" > y);
assert y > "00";
assert not ("00" > y);
wait;
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.2 2007/03/03 17:24:06 wig Exp $
-- $Date: 2007/03/03 17:24:06 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.2 2007/03/03 17:24:06 wig
-- Updated testcase for case matches. Added filename serialization.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_A_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_a_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
case_a_p : out std_ulogic
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
case_b_p : in std_ulogic
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal case : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_A
inst_A: inst_A_e
;
-- End of Generated Instance Port Map for inst_A
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
case_a_p => case
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: inst_b_e
port map (
case_b_p => case
);
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
------------------------------------------------------------------------------
---- ----
---- I2C Master Core (Byte Controller) ----
---- ----
---- Internal file, can't be downloaded. ----
---- Based on code from: http://www.opencores.org/projects/i2c/ ----
---- ----
---- Description: ----
---- I2C master peripheral for the Wishbone bus. ----
---- Byte controller stuff. That's almost the same code from OpenCores. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Authors: ----
---- - Richard Herveille, [email protected] ----
---- - Salvador E. Tropea, salvador en inti gov ar (small changes) ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2005 Salvador E. Tropea <salvador en inti gov ar> ----
---- Copyright (c) 2005 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2000 Richard Herveille <[email protected]> ----
---- ----
---- Covered by the GPL license. ----
---- ----
---- Original distribution policy: ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: I2C_MasterByteCtrl(Structural) (Entity and arch.) ----
---- File name: i2c_master_byte_ctrl.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: i2c_mwb ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan II (XC2S100-5-PQ208) ----
---- Language: VHDL ----
---- Wishbone: None ----
---- Synthesis tools: Xilinx Release 6.2.03i - xst G.31a ----
---- Simulation tools: GHDL [Sokcho edition] (0.1x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
--
-- CVS Log
--
-- $Id: i2c_master_byte_ctrl.vhdl,v 1.8 2006/04/17 19:44:43 salvador Exp $
--
-- $Date: 2006/04/17 19:44:43 $
-- $Revision: 1.8 $
-- $Author: salvador $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_byte_ctrl.vhdl,v $
-- Revision 1.8 2006/04/17 19:44:43 salvador
-- * Modified: License to GPL.
--
-- Revision 1.7 2005/05/20 14:39:05 salvador
-- * Modificado: Mejorado el indentado usando bakalint 0.3.7.
--
-- Revision 1.6 2005/05/18 14:50:19 salvador
-- * Modificado: Los encabezados de los archivos para que cumplan con nuestras
-- recomendaciones.
--
-- Revision 1.5 2005/05/11 22:39:17 salvador
-- * Modificado: Pasado por el bakalint 0.3.5.
--
-- Revision 1.4 2005/03/29 20:35:44 salvador
-- * Modificado: Encerrado con "translate off/on" el código de simulación para
-- que el XST no moleste.
-- * Agregado: Un generic para que las interrupciones esten siempre
-- habilitadas.
-- * Agregado: Default para wb_cyc_i de manera tal que no sea necesario
-- conectarlo.
-- * Modificado: Para ahorrar algunos F/F en registros que tienen bits sin
-- usar. A consecuencia de esto el bit "iack" se corrió.
--
-- Revision 1.3 2005/03/10 19:40:07 salvador
-- * Modificado: Para usar "rising_edge" que hace más legible el código.
-- * Agregado: MUX_BETTER para elegir que use muxs en lugar de tri-states.
-- Por defecto es falso con lo que ahorra unos 12 slice.
-- * Agregado: FULL_SYNC para lograr el comportamiento original con 1 WS.
-- * Agregado: FIXED_PRER con lo que se puede fijar el valor del prescaler lo
-- que ahorra unos 11 slice.
-- * Modificado: Los case de lectura/escritura de los registros por if/elsif
-- que permite controlar mejor el uso de los generic.
-- * Modificado: El testbench para que soporte FIXED_PRER.
--
-- Revision 1.2 2005/03/09 17:41:16 salvador
-- * Agregado: Hojas de datos del 24LC02B.
-- * Modificado: Reemplazo de Report por Assert porque las herramientas de
-- Xilinx no lo soportan.
-- * Modificado: Comentado los printf en core porque no tengo el equivalente
-- para Xilinx.
-- * Corregido: El TB de la memoria no contestaba ACK luego de la escritura.
-- Ahora si y además el TB verifica que no falten ACKs.
--
-- Revision 1.1 2005/03/08 15:57:36 salvador
-- * Movido al repositorio CVS.
-- * Agregado: TestBench en VHDL.
--
-- Revision 1.5 2004/02/18 11:41:48 rherveille
-- Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
--
-- Revision 1.4 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.3 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.2 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity I2C_MasterByteCtrl is
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nreset_i : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena_i : in std_logic; -- core enable signal
clk_cnt_i : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start_i : in std_logic;
stop_i : in std_logic;
read_i : in std_logic;
write_i : in std_logic;
ack_in_i : in std_logic;
din_i : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack_o : out std_logic; -- command done
ack_out_o : out std_logic;
i2c_busy_o : out std_logic; -- arbitration lost
i2c_al_o : out std_logic; -- i2c bus busy
dout_o : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen_o : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen_o : out std_logic -- i2c data line output enable, active low
);
end entity I2C_MasterByteCtrl;
architecture Structural of I2C_MasterByteCtrl is
component I2C_MasterBitCtrl is
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
nreset_i : in std_logic;
ena_i : in std_logic; -- core enable signal
clk_cnt_i : in unsigned(15 downto 0); -- clock prescale value
cmd_i : in std_logic_vector(3 downto 0);
cmd_ack_o : out std_logic; -- command done
busy_o : out std_logic; -- i2c bus busy
al_o : out std_logic; -- arbitration lost
din_i : in std_logic;
dout_o : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen_o : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen_o : out std_logic -- i2c data line output enable, active low
);
end component I2C_MasterBitCtrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack : std_logic;
signal core_txd : std_logic;
signal core_rxd : std_logic;
signal al_o : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
signal dcnt : unsigned(2 downto 0); -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: I2C_MasterBitCtrl
port map(
wb_clk_i=> wb_clk_i,
wb_rst_i=> wb_rst_i,
nreset_i=> nreset_i,
ena_i => ena_i,
clk_cnt_i=> clk_cnt_i,
cmd_i => core_cmd,
cmd_ack_o=> core_ack,
busy_o => i2c_busy_o,
al_o => al_o,
din_i => core_txd,
dout_o => core_rxd,
scl_i => scl_i,
scl_o => scl_o,
scl_oen_o=> scl_oen_o,
sda_i => sda_i,
sda_o => sda_o,
sda_oen_o=> sda_oen_o );
i2c_al_o<= al_o;
-- generate host-command-acknowledge
cmd_ack_o<= host_ack;
-- generate go-signal
go <= (read_i or write_i or stop_i) and not host_ack;
-- assign Dout output to shift-register
dout_o<= sr;
-- generate shift register
shift_register:
process(wb_clk_i, nreset_i)
begin
if (nreset_i= '0') then
sr <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i= '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din_i;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt:
process(wb_clk_i, nreset_i)
begin
if (nreset_i= '0') then
dcnt <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i= '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = 0) else '0';
--
-- state machine
--
statemachine:
block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder:
process(wb_clk_i, nreset_i)
begin
if (nreset_i= '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out_o<= '0';
elsif rising_edge(wb_clk_i) then
if (wb_rst_i= '1' or al_o= '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out_o<= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start_i= '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read_i= '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write_i= '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read_i= '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in_i;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop_i= '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out_o<= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in_i;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
--synopsys translate off
assert false
report "Byte controller entered illegal state."
severity failure;
--synopsys translate on
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture Structural;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 14:57:12 07/30/2009
-- Design Name:
-- Module Name: Comp_ClockGen - Behavioral
-- Project Name: Clock Generator
-- Target Devices:
-- Tool versions:
-- Description: A device that generates a buffered clock signal in refernce to
-- a 50 MHz outside clock. The output can be reconfigured through
-- software to generate a different frequency.
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - First draft written
-- Revision 0.15 - Sytax errors fixed
-- Revision 0.30 - UCF File written
-- Revision 1.00 - Generated programming file with a successful hardware test
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Comp_ClockGen400Hz is
Port ( Board_Clk : in STD_LOGIC;
Clock_Out : out STD_LOGIC);
end Comp_ClockGen400Hz;
architecture Behavioral of Comp_ClockGen400Hz is
begin
main : process(Board_Clk) is
constant hertz : integer := 400;
constant cycles : integer := (25_000_000/hertz);
variable count : integer := 0;
variable output : STD_LOGIC := '0';
begin
if rising_edge(Board_Clk) then
count := count + 1;
if count > cycles then
count := 0;
output := not output;
end if;
end if;
Clock_Out <= output;
end process main;
end Behavioral;
|
--accm
-- ************************************
-- Automatically Generated FSM
-- IDEA_chan
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity IDEA_chan is
generic(
G_ADDR_WIDTH : integer := 32;
G_DATA_WIDTH : integer := 32;
DATA_WIDTH : integer := 32;
OPCODE_BITS : integer := 6;
FUNC_BITS : integer := 6
);
port
(
Vector_A_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_A_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_rENA0 : out std_logic;
Vector_A_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_B_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_B_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_rENA0 : out std_logic;
Vector_B_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_C_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_C_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_rENA0 : out std_logic;
Vector_C_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity IDEA_chan;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of IDEA_chan is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
fetch,
get_instr,
decode,
IDEA_state1,
extra1,
read_x1,
extra2,
read_x2,
extra3,
read_x3,
extra4,
start_round,
extra5,
r1_1,
extra6,
r1_2,
extra7,
r1_3,
extra8,
r1_4,
extra9,
r1_5,
extra10,
r1_6,
extra11,
r1_7,
extra12,
round_part0,
extra13,
r2_1,
extra14,
r2_2,
extra15,
r2_3,
extra16,
r2_4,
extra17,
r2_5,
extra18,
r2_6,
extra19,
r2_7,
extra20,
extra21,
r3_1,
extra22,
r3_2,
extra23,
r3_3,
extra24,
r3_4,
extra25,
r3_5,
extra26,
r3_6,
extra27,
r3_7,
extra28,
extra29,
r4_1,
extra30,
r4_2,
extra31,
r4_3,
extra32,
r4_4,
extra33,
r4_5,
extra34,
r4_6,
extra35,
r4_7,
extra36,
extra37,
r5_1,
extra38,
r5_2,
extra39,
r5_3,
extra40,
r5_4,
extra41,
r5_5,
extra42,
r5_6,
extra43,
r5_7,
extra44,
extra45,
r6_1,
extra46,
r6_2,
extra47,
r6_3,
extra48,
r6_4,
extra49,
r6_5,
extra50,
r6_6,
extra51,
r6_7,
extra52,
extra53,
r7_1,
extra54,
r7_2,
extra55,
r7_3,
extra56,
r7_4,
extra57,
r7_5,
extra58,
r7_6,
extra59,
r7_7,
extra60,
extra61,
r8_1,
extra62,
r8_2,
extra63,
r8_3,
extra64,
r8_4,
extra65,
r8_5,
extra66,
r8_6,
extra67,
r8_7,
extra68,
extra69,
r9_4,
extra70,
r9_2,
extra71,
r9_3,
extra72,
pre_calc_results,
round_part1,
round_part2,
round_part3,
round_part4,
round_part5,
round_part6,
round_part7,
round_part8,
calc_results,
output_results,
next_result,
next_next_result,
next_next_next_result,
halt
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal in_Vector_A_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal in_Vector_B_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal in_Vector_C_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal swapped, swapped_next : std_logic;
signal i, i_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal n, n_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal n_new, n_new_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal instruction, instruction_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal index, index_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal ret, ret_next : std_logic_vector(0 to G_DATA_WIDTH + G_DATA_WIDTH - 1);
signal dataA1, dataA1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataA2, dataA2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataB1, dataB1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataB2, dataB2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataC1, dataC1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataC2, dataC2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataMUL, dataMUL_next : std_logic_vector(0 to G_DATA_WIDTH + G_DATA_WIDTH - 1);
signal op, op_next : std_logic_vector(0 to 1);
signal rs, rs_next : std_logic_vector(2 to 16);
signal rt, rt_next : std_logic_vector(17 to 31);
signal r, r_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal mult_res1, mult_res1_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal mult_res2, mult_res2_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal mult_res3, mult_res3_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal mult_res4, mult_res4_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal out1, out1_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal out2, out2_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal out3, out3_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal out4, out4_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal x1, x1_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal x2, x2_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal x3, x3_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal x4, x4_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal kk, kk_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal t1, t1_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal t2, t2_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal a, a_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal z1_r, z1_r_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal z2_r, z2_r_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal z3_r, z3_r_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal z4_r, z4_r_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal z5_r, z5_r_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal z6_r, z6_r_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal z7_r, z7_r_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal z8_r, z8_r_next : std_logic_vector(0 to DATA_WIDTH - 1);
signal z9_r, z9_r_next : std_logic_vector(0 to DATA_WIDTH - 1);
shared variable mul1 : std_logic_vector(0 to 63) := x"0000000000000000";
shared variable mul2 : std_logic_vector(0 to 63) := x"0000000000000000";
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
constant maxim : std_logic_vector(0 to DATA_WIDTH-1) := conv_std_logic_vector(65537,DATA_WIDTH);
constant one : std_logic_vector(0 to DATA_WIDTH-1) := conv_std_logic_vector(65535,DATA_WIDTH);
function mul( a : std_logic_vector(0 to DATA_WIDTH -1); b : std_logic_vector(0 to DATA_WIDTH-1); q : std_logic_vector(0 to DATA_WIDTH-1)) return std_logic_vector is
variable p : std_logic_vector(0 to DATA_WIDTH-1);
variable x : std_logic_vector(0 to DATA_WIDTH-1);
begin
if (a = 0) then
p := maxim - b;
elsif (b = 0) then
p := maxim - a;
else
x := (q and one);
p := x - (x"0000" & q(0 to DATA_WIDTH/2-1));
--if (p <= 0) then -- Need to change this check to handle signed/unsigned stuff, probably just check the MSB
if (p(0) = '1') then -- Need to change this check to handle signed/unsigned stuff, probably just check the MSB
p := p + maxim;
end if;
end if;
return (p and one);
end function mul;
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
Vector_A_addr0 <= in_Vector_A_addr0(2 to 31) & "00";
Vector_B_addr0 <= in_Vector_B_addr0(2 to 31) & "00";
Vector_C_addr0 <= in_Vector_C_addr0(2 to 31) & "00";
-- ************************
-- BRAM implementations
-- ************************
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
swapped_next,
i_next,
n_next,
n_new_next,
instruction_next,
index_next,
ret_next,
dataA1_next,
dataA2_next,
dataB1_next,
dataB2_next,
dataC1_next,
dataC2_next,
dataMUL_next,
op_next,
rs_next,
rt_next,
r_next,
mult_res1_next,
mult_res2_next,
mult_res3_next,
mult_res4_next,
out1_next,
out2_next,
out3_next,
out4_next,
x1_next,
x2_next,
x3_next,
x4_next,
kk_next,
t1_next,
t2_next,
a_next,
z1_r_next,
z2_r_next,
z3_r_next,
z4_r_next,
z5_r_next,
z6_r_next,
z7_r_next,
z8_r_next,
z9_r_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
swapped <= '0';
i <= (others => '0');
n <= (others => '0');
n_new <= (others => '0');
instruction <= (others => '0');
index <= (others => '0');
ret <= (others => '0');
dataA1 <= (others => '0');
dataA2 <= (others => '0');
dataB1 <= (others => '0');
dataB2 <= (others => '0');
dataC1 <= (others => '0');
dataC2 <= (others => '0');
dataMUL <= (others => '0');
op <= (others => '0');
rs <= (others => '0');
rt <= (others => '0');
r <= (others => '0');
mult_res1 <= (others => '0');
mult_res2 <= (others => '0');
mult_res3 <= (others => '0');
mult_res4 <= (others => '0');
out1 <= (others => '0');
out2 <= (others => '0');
out3 <= (others => '0');
out4 <= (others => '0');
x1 <= (others => '0');
x2 <= (others => '0');
x3 <= (others => '0');
x4 <= (others => '0');
kk <= (others => '0');
t1 <= (others => '0');
t2 <= (others => '0');
a <= (others => '0');
z1_r <= (others => '0');
z2_r <= (others => '0');
z3_r <= (others => '0');
z4_r <= (others => '0');
z5_r <= (others => '0');
z6_r <= (others => '0');
z7_r <= (others => '0');
z8_r <= (others => '0');
z9_r <= (others => '0');
current_state <= reset;
else
-- Transition to next state
swapped <= swapped_next;
i <= i_next;
n <= n_next;
n_new <= n_new_next;
instruction <= instruction_next;
index <= index_next;
ret <= ret_next;
dataA1 <= dataA1_next;
dataA2 <= dataA2_next;
dataB1 <= dataB1_next;
dataB2 <= dataB2_next;
dataC1 <= dataC1_next;
dataC2 <= dataC2_next;
dataMUL <= dataMUL_next;
op <= op_next;
rs <= rs_next;
rt <= rt_next;
r <= r_next;
mult_res1 <= mult_res1_next;
mult_res2 <= mult_res2_next;
mult_res3 <= mult_res3_next;
mult_res4 <= mult_res4_next;
out1 <= out1_next;
out2 <= out2_next;
out3 <= out3_next;
out4 <= out4_next;
x1 <= x1_next;
x2 <= x2_next;
x3 <= x3_next;
x4 <= x4_next;
kk <= kk_next;
t1 <= t1_next;
t2 <= t2_next;
a <= a_next;
z1_r <= z1_r_next;
z2_r <= z2_r_next;
z3_r <= z3_r_next;
z4_r <= z4_r_next;
z5_r <= z5_r_next;
z6_r <= z6_r_next;
z7_r <= z7_r_next;
z8_r <= z8_r_next;
z9_r <= z9_r_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
Vector_A_dOUT0,
Vector_B_dOUT0,
Vector_C_dOUT0,
chan1_channelDataOut, chan1_full, chan1_exists,
swapped,
i,
n,
n_new,
instruction,
index,
ret,
dataA1,
dataA2,
dataB1,
dataB2,
dataC1,
dataC2,
dataMUL,
op,
rs,
rt,
r,
mult_res1,
mult_res2,
mult_res3,
mult_res4,
out1,
out2,
out3,
out4,
x1,
x2,
x3,
x4,
kk,
t1,
t2,
a,
z1_r,
z2_r,
z3_r,
z4_r,
z5_r,
z6_r,
z7_r,
z8_r,
z9_r,
current_state) is
begin
-- Default signal assignments
swapped_next <= swapped;
i_next <= i;
n_next <= n;
n_new_next <= n_new;
instruction_next <= instruction;
index_next <= index;
ret_next <= ret;
dataA1_next <= dataA1;
dataA2_next <= dataA2;
dataB1_next <= dataB1;
dataB2_next <= dataB2;
dataC1_next <= dataC1;
dataC2_next <= dataC2;
dataMUL_next <= dataMUL;
op_next <= op;
rs_next <= rs;
rt_next <= rt;
r_next <= r;
mult_res1_next <= mult_res1;
mult_res2_next <= mult_res2;
mult_res3_next <= mult_res3;
mult_res4_next <= mult_res4;
out1_next <= out1;
out2_next <= out2;
out3_next <= out3;
out4_next <= out4;
x1_next <= x1;
x2_next <= x2;
x3_next <= x3;
x4_next <= x4;
kk_next <= kk;
t1_next <= t1;
t2_next <= t2;
a_next <= a;
z1_r_next <= z1_r;
z2_r_next <= z2_r;
z3_r_next <= z3_r;
z4_r_next <= z4_r;
z5_r_next <= z5_r;
z6_r_next <= z6_r;
z7_r_next <= z7_r;
z8_r_next <= z8_r;
z9_r_next <= z9_r;
in_Vector_A_addr0 <= (others => '0');
Vector_A_dIN0 <= (others => '0');
Vector_A_rENA0 <= '0';
Vector_A_wENA0 <= (others => '0');
in_Vector_B_addr0 <= (others => '0');
Vector_B_dIN0 <= (others => '0');
Vector_B_rENA0 <= '0';
Vector_B_wENA0 <= (others => '0');
in_Vector_C_addr0 <= (others => '0');
Vector_C_dIN0 <= (others => '0');
Vector_C_rENA0 <= '0';
Vector_C_wENA0 <= (others => '0');
chan1_channelDataIn <= (others => '0');
chan1_channelRead <= '0';
chan1_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when IDEA_state1 =>
in_Vector_A_addr0 <= i;
Vector_A_rENA0 <= '1';
next_state <= extra1;
when calc_results =>
out4_next <= mul(x4,z4_r,mult_res2);
out3_next <= ( x2 + z3_r ) and one;
out2_next <= ( x3 + z2_r ) and one;
out1_next <= mul(x1,z1_r,mult_res1);
next_state <= output_results;
when decode =>
i_next <= index;
next_state <= IDEA_state1;
when extra1 =>
x1_next <= Vector_A_dOUT0;
next_state <= read_x1;
when extra10 =>
z6_r_next <= Vector_B_dOUT0;
next_state <= r1_6;
when extra11 =>
z7_r_next <= Vector_B_dOUT0;
next_state <= r1_7;
when extra12 =>
z8_r_next <= Vector_B_dOUT0;
next_state <= round_part0;
when extra13 =>
z1_r_next <= Vector_B_dOUT0;
next_state <= r2_1;
when extra14 =>
z2_r_next <= Vector_B_dOUT0;
next_state <= r2_2;
when extra15 =>
z3_r_next <= Vector_B_dOUT0;
next_state <= r2_3;
when extra16 =>
z4_r_next <= Vector_B_dOUT0;
next_state <= r2_4;
when extra17 =>
z5_r_next <= Vector_B_dOUT0;
next_state <= r2_5;
when extra18 =>
z6_r_next <= Vector_B_dOUT0;
next_state <= r2_6;
when extra19 =>
z7_r_next <= Vector_B_dOUT0;
next_state <= r2_7;
when extra2 =>
x2_next <= Vector_A_dOUT0;
next_state <= read_x2;
when extra20 =>
z8_r_next <= Vector_B_dOUT0;
next_state <= round_part0;
when extra21 =>
z1_r_next <= Vector_B_dOUT0;
next_state <= r3_1;
when extra22 =>
z2_r_next <= Vector_B_dOUT0;
next_state <= r3_2;
when extra23 =>
z3_r_next <= Vector_B_dOUT0;
next_state <= r3_3;
when extra24 =>
z4_r_next <= Vector_B_dOUT0;
next_state <= r3_4;
when extra25 =>
z5_r_next <= Vector_B_dOUT0;
next_state <= r3_5;
when extra26 =>
z6_r_next <= Vector_B_dOUT0;
next_state <= r3_6;
when extra27 =>
z7_r_next <= Vector_B_dOUT0;
next_state <= r3_7;
when extra28 =>
z8_r_next <= Vector_B_dOUT0;
next_state <= round_part0;
when extra29 =>
z1_r_next <= Vector_B_dOUT0;
next_state <= r4_1;
when extra3 =>
x3_next <= Vector_A_dOUT0;
next_state <= read_x3;
when extra30 =>
z2_r_next <= Vector_B_dOUT0;
next_state <= r4_2;
when extra31 =>
z3_r_next <= Vector_B_dOUT0;
next_state <= r4_3;
when extra32 =>
z4_r_next <= Vector_B_dOUT0;
next_state <= r4_4;
when extra33 =>
z5_r_next <= Vector_B_dOUT0;
next_state <= r4_5;
when extra34 =>
z6_r_next <= Vector_B_dOUT0;
next_state <= r4_6;
when extra35 =>
z7_r_next <= Vector_B_dOUT0;
next_state <= r4_7;
when extra36 =>
z8_r_next <= Vector_B_dOUT0;
next_state <= round_part0;
when extra37 =>
z1_r_next <= Vector_B_dOUT0;
next_state <= r5_1;
when extra38 =>
z2_r_next <= Vector_B_dOUT0;
next_state <= r5_2;
when extra39 =>
z3_r_next <= Vector_B_dOUT0;
next_state <= r5_3;
when extra4 =>
r_next <= conv_std_logic_vector(1,DATA_WIDTH);
x4_next <= Vector_A_dOUT0;
next_state <= start_round;
when extra40 =>
z4_r_next <= Vector_B_dOUT0;
next_state <= r5_4;
when extra41 =>
z5_r_next <= Vector_B_dOUT0;
next_state <= r5_5;
when extra42 =>
z6_r_next <= Vector_B_dOUT0;
next_state <= r5_6;
when extra43 =>
z7_r_next <= Vector_B_dOUT0;
next_state <= r5_7;
when extra44 =>
z8_r_next <= Vector_B_dOUT0;
next_state <= round_part0;
when extra45 =>
z1_r_next <= Vector_B_dOUT0;
next_state <= r6_1;
when extra46 =>
z2_r_next <= Vector_B_dOUT0;
next_state <= r6_2;
when extra47 =>
z3_r_next <= Vector_B_dOUT0;
next_state <= r6_3;
when extra48 =>
z4_r_next <= Vector_B_dOUT0;
next_state <= r6_4;
when extra49 =>
z5_r_next <= Vector_B_dOUT0;
next_state <= r6_5;
when extra5 =>
z1_r_next <= Vector_B_dOUT0;
next_state <= r1_1;
when extra50 =>
z6_r_next <= Vector_B_dOUT0;
next_state <= r6_6;
when extra51 =>
z7_r_next <= Vector_B_dOUT0;
next_state <= r6_7;
when extra52 =>
z8_r_next <= Vector_B_dOUT0;
next_state <= round_part0;
when extra53 =>
z1_r_next <= Vector_B_dOUT0;
next_state <= r7_1;
when extra54 =>
z2_r_next <= Vector_B_dOUT0;
next_state <= r7_2;
when extra55 =>
z3_r_next <= Vector_B_dOUT0;
next_state <= r7_3;
when extra56 =>
z4_r_next <= Vector_B_dOUT0;
next_state <= r7_4;
when extra57 =>
z5_r_next <= Vector_B_dOUT0;
next_state <= r7_5;
when extra58 =>
z6_r_next <= Vector_B_dOUT0;
next_state <= r7_6;
when extra59 =>
z7_r_next <= Vector_B_dOUT0;
next_state <= r7_7;
when extra6 =>
z2_r_next <= Vector_B_dOUT0;
next_state <= r1_2;
when extra60 =>
z8_r_next <= Vector_B_dOUT0;
next_state <= round_part0;
when extra61 =>
z1_r_next <= Vector_B_dOUT0;
next_state <= r8_1;
when extra62 =>
z2_r_next <= Vector_B_dOUT0;
next_state <= r8_2;
when extra63 =>
z3_r_next <= Vector_B_dOUT0;
next_state <= r8_3;
when extra64 =>
z4_r_next <= Vector_B_dOUT0;
next_state <= r8_4;
when extra65 =>
z5_r_next <= Vector_B_dOUT0;
next_state <= r8_5;
when extra66 =>
z6_r_next <= Vector_B_dOUT0;
next_state <= r8_6;
when extra67 =>
z7_r_next <= Vector_B_dOUT0;
next_state <= r8_7;
when extra68 =>
z8_r_next <= Vector_B_dOUT0;
next_state <= round_part0;
when extra69 =>
z1_r_next <= Vector_B_dOUT0;
next_state <= r9_4;
when extra7 =>
z3_r_next <= Vector_B_dOUT0;
next_state <= r1_3;
when extra70 =>
z4_r_next <= Vector_B_dOUT0;
next_state <= r9_2;
when extra71 =>
z2_r_next <= Vector_B_dOUT0;
next_state <= r9_3;
when extra72 =>
z3_r_next <= Vector_B_dOUT0;
next_state <= pre_calc_results;
when extra8 =>
z4_r_next <= Vector_B_dOUT0;
next_state <= r1_4;
when extra9 =>
z5_r_next <= Vector_B_dOUT0;
next_state <= r1_5;
when fetch =>
if chan1_exists = '0' then
next_state <= fetch;
elsif chan1_exists /= '0' then
instruction_next <= chan1_channelDataOut;
chan1_channelRead <= '1';
next_state <= get_instr;
end if;
when get_instr =>
ret_next <= (others => '0');
index_next <= "00000000000000000" & instruction(17 to 31);
n_next <= "00000000000000000" & instruction(2 to 16);
op_next <= instruction(0 to 1);
next_state <= decode;
when halt =>
if chan1_full /= '0' then
next_state <= halt;
elsif chan1_full = '0' then
chan1_channelDataIn <= ret(32 to 63);
chan1_channelWrite <= '1';
next_state <= fetch;
end if;
when next_next_next_result =>
in_Vector_C_addr0 <= x"00000003";
Vector_C_dIN0 <= out4;
Vector_C_wENA0 <= (others => '1');
Vector_C_rENA0 <= '1';
next_state <= halt;
when next_next_result =>
in_Vector_C_addr0 <= x"00000002";
Vector_C_dIN0 <= out3;
Vector_C_wENA0 <= (others => '1');
Vector_C_rENA0 <= '1';
next_state <= next_next_next_result;
when next_result =>
in_Vector_C_addr0 <= x"00000001";
Vector_C_dIN0 <= out2;
Vector_C_wENA0 <= (others => '1');
Vector_C_rENA0 <= '1';
next_state <= next_next_result;
when output_results =>
in_Vector_C_addr0 <= x"00000000";
Vector_C_dIN0 <= out1;
Vector_C_wENA0 <= (others => '1');
Vector_C_rENA0 <= '1';
next_state <= next_result;
when pre_calc_results =>
mul1 := x4 * z4_r;
mult_res2_next <= mul1(0 to 31);
mul2 := x1 * z1_r;
mult_res1_next <= mul2(0 to 31);
next_state <= calc_results;
when r1_1 =>
in_Vector_B_addr0 <= x"00000001";
Vector_B_rENA0 <= '1';
next_state <= extra6;
when r1_2 =>
in_Vector_B_addr0 <= x"00000002";
Vector_B_rENA0 <= '1';
next_state <= extra7;
when r1_3 =>
in_Vector_B_addr0 <= x"00000003";
Vector_B_rENA0 <= '1';
next_state <= extra8;
when r1_4 =>
in_Vector_B_addr0 <= x"00000004";
Vector_B_rENA0 <= '1';
next_state <= extra9;
when r1_5 =>
in_Vector_B_addr0 <= x"00000005";
Vector_B_rENA0 <= '1';
next_state <= extra10;
when r1_6 =>
in_Vector_B_addr0 <= x"00000006";
Vector_B_rENA0 <= '1';
next_state <= extra11;
when r1_7 =>
in_Vector_B_addr0 <= x"00000007";
Vector_B_rENA0 <= '1';
next_state <= extra12;
when r2_1 =>
in_Vector_B_addr0 <= x"00000009";
Vector_B_rENA0 <= '1';
next_state <= extra14;
when r2_2 =>
in_Vector_B_addr0 <= x"0000000a";
Vector_B_rENA0 <= '1';
next_state <= extra15;
when r2_3 =>
in_Vector_B_addr0 <= x"0000000b";
Vector_B_rENA0 <= '1';
next_state <= extra16;
when r2_4 =>
in_Vector_B_addr0 <= x"0000000c";
Vector_B_rENA0 <= '1';
next_state <= extra17;
when r2_5 =>
in_Vector_B_addr0 <= x"0000000d";
Vector_B_rENA0 <= '1';
next_state <= extra18;
when r2_6 =>
in_Vector_B_addr0 <= x"0000000e";
Vector_B_rENA0 <= '1';
next_state <= extra19;
when r2_7 =>
in_Vector_B_addr0 <= x"0000000f";
Vector_B_rENA0 <= '1';
next_state <= extra20;
when r3_1 =>
in_Vector_B_addr0 <= x"00000011";
Vector_B_rENA0 <= '1';
next_state <= extra22;
when r3_2 =>
in_Vector_B_addr0 <= x"00000012";
Vector_B_rENA0 <= '1';
next_state <= extra23;
when r3_3 =>
in_Vector_B_addr0 <= x"00000013";
Vector_B_rENA0 <= '1';
next_state <= extra24;
when r3_4 =>
in_Vector_B_addr0 <= x"00000014";
Vector_B_rENA0 <= '1';
next_state <= extra25;
when r3_5 =>
in_Vector_B_addr0 <= x"00000015";
Vector_B_rENA0 <= '1';
next_state <= extra26;
when r3_6 =>
in_Vector_B_addr0 <= x"00000016";
Vector_B_rENA0 <= '1';
next_state <= extra27;
when r3_7 =>
in_Vector_B_addr0 <= x"00000017";
Vector_B_rENA0 <= '1';
next_state <= extra28;
when r4_1 =>
in_Vector_B_addr0 <= x"00000019";
Vector_B_rENA0 <= '1';
next_state <= extra30;
when r4_2 =>
in_Vector_B_addr0 <= x"0000001a";
Vector_B_rENA0 <= '1';
next_state <= extra31;
when r4_3 =>
in_Vector_B_addr0 <= x"0000001b";
Vector_B_rENA0 <= '1';
next_state <= extra32;
when r4_4 =>
in_Vector_B_addr0 <= x"0000001c";
Vector_B_rENA0 <= '1';
next_state <= extra33;
when r4_5 =>
in_Vector_B_addr0 <= x"0000001d";
Vector_B_rENA0 <= '1';
next_state <= extra34;
when r4_6 =>
in_Vector_B_addr0 <= x"0000001e";
Vector_B_rENA0 <= '1';
next_state <= extra35;
when r4_7 =>
in_Vector_B_addr0 <= x"0000001f";
Vector_B_rENA0 <= '1';
next_state <= extra36;
when r5_1 =>
in_Vector_B_addr0 <= x"00000021";
Vector_B_rENA0 <= '1';
next_state <= extra38;
when r5_2 =>
in_Vector_B_addr0 <= x"00000022";
Vector_B_rENA0 <= '1';
next_state <= extra39;
when r5_3 =>
in_Vector_B_addr0 <= x"00000023";
Vector_B_rENA0 <= '1';
next_state <= extra40;
when r5_4 =>
in_Vector_B_addr0 <= x"00000024";
Vector_B_rENA0 <= '1';
next_state <= extra41;
when r5_5 =>
in_Vector_B_addr0 <= x"00000025";
Vector_B_rENA0 <= '1';
next_state <= extra42;
when r5_6 =>
in_Vector_B_addr0 <= x"00000026";
Vector_B_rENA0 <= '1';
next_state <= extra43;
when r5_7 =>
in_Vector_B_addr0 <= x"00000027";
Vector_B_rENA0 <= '1';
next_state <= extra44;
when r6_1 =>
in_Vector_B_addr0 <= x"00000029";
Vector_B_rENA0 <= '1';
next_state <= extra46;
when r6_2 =>
in_Vector_B_addr0 <= x"0000002a";
Vector_B_rENA0 <= '1';
next_state <= extra47;
when r6_3 =>
in_Vector_B_addr0 <= x"0000002b";
Vector_B_rENA0 <= '1';
next_state <= extra48;
when r6_4 =>
in_Vector_B_addr0 <= x"0000002c";
Vector_B_rENA0 <= '1';
next_state <= extra49;
when r6_5 =>
in_Vector_B_addr0 <= x"0000002d";
Vector_B_rENA0 <= '1';
next_state <= extra50;
when r6_6 =>
in_Vector_B_addr0 <= x"0000002e";
Vector_B_rENA0 <= '1';
next_state <= extra51;
when r6_7 =>
in_Vector_B_addr0 <= x"0000002f";
Vector_B_rENA0 <= '1';
next_state <= extra52;
when r7_1 =>
in_Vector_B_addr0 <= x"00000031";
Vector_B_rENA0 <= '1';
next_state <= extra54;
when r7_2 =>
in_Vector_B_addr0 <= x"00000032";
Vector_B_rENA0 <= '1';
next_state <= extra55;
when r7_3 =>
in_Vector_B_addr0 <= x"00000033";
Vector_B_rENA0 <= '1';
next_state <= extra56;
when r7_4 =>
in_Vector_B_addr0 <= x"00000034";
Vector_B_rENA0 <= '1';
next_state <= extra57;
when r7_5 =>
in_Vector_B_addr0 <= x"00000035";
Vector_B_rENA0 <= '1';
next_state <= extra58;
when r7_6 =>
in_Vector_B_addr0 <= x"00000036";
Vector_B_rENA0 <= '1';
next_state <= extra59;
when r7_7 =>
in_Vector_B_addr0 <= x"00000037";
Vector_B_rENA0 <= '1';
next_state <= extra60;
when r8_1 =>
in_Vector_B_addr0 <= x"00000039";
Vector_B_rENA0 <= '1';
next_state <= extra62;
when r8_2 =>
in_Vector_B_addr0 <= x"0000003a";
Vector_B_rENA0 <= '1';
next_state <= extra63;
when r8_3 =>
in_Vector_B_addr0 <= x"0000003b";
Vector_B_rENA0 <= '1';
next_state <= extra64;
when r8_4 =>
in_Vector_B_addr0 <= x"0000003c";
Vector_B_rENA0 <= '1';
next_state <= extra65;
when r8_5 =>
in_Vector_B_addr0 <= x"0000003d";
Vector_B_rENA0 <= '1';
next_state <= extra66;
when r8_6 =>
in_Vector_B_addr0 <= x"0000003e";
Vector_B_rENA0 <= '1';
next_state <= extra67;
when r8_7 =>
in_Vector_B_addr0 <= x"0000003f";
Vector_B_rENA0 <= '1';
next_state <= extra68;
when r9_2 =>
in_Vector_B_addr0 <= x"00000041";
Vector_B_rENA0 <= '1';
next_state <= extra71;
when r9_3 =>
in_Vector_B_addr0 <= x"00000042";
Vector_B_rENA0 <= '1';
next_state <= extra72;
when r9_4 =>
in_Vector_B_addr0 <= x"00000043";
Vector_B_rENA0 <= '1';
next_state <= extra70;
when read_x1 =>
in_Vector_A_addr0 <= i + 1;
Vector_A_rENA0 <= '1';
next_state <= extra2;
when read_x2 =>
in_Vector_A_addr0 <= i + 2;
Vector_A_rENA0 <= '1';
next_state <= extra3;
when read_x3 =>
in_Vector_A_addr0 <= i + 3;
Vector_A_rENA0 <= '1';
next_state <= extra4;
when reset =>
next_state <= fetch;
when round_part0 =>
mul1 := x4 * z4_r;
mult_res2_next <= mul1(0 to 31);
mul2 := x1 * z1_r;
mult_res1_next <= mul2(0 to 31);
next_state <= round_part1;
when round_part1 =>
x4_next <= mul(x4,z4_r,mult_res2);
x3_next <= ( x3 + z3_r ) and one;
x2_next <= ( x2 + z2_r ) and one;
x1_next <= mul(x1,z1_r,mult_res1);
next_state <= round_part2;
when round_part2 =>
mul1 := z5_r * ( x1 xor x3 );
mult_res1_next <= mul1(0 to 31);
kk_next <= ( x1 xor x3 );
next_state <= round_part3;
when round_part3 =>
kk_next <= mul(z5_r,kk,mult_res1);
next_state <= round_part4;
when round_part4 =>
mul1 := z6_r * ( ( kk + ( x2 xor x4 ) ) and one );
mult_res1_next <= mul1(0 to 31);
t1_next <= ( kk + ( x2 xor x4 ) ) and one;
next_state <= round_part5;
when round_part5 =>
t1_next <= mul(z6_r,t1,mult_res1);
next_state <= round_part6;
when round_part6 =>
t2_next <= ( kk + t1 ) and one;
next_state <= round_part7;
when round_part7 =>
x3_next <= x2 xor t2;
a_next <= x2 xor t2;
x4_next <= x4 xor t2;
x2_next <= x3 xor t1;
x1_next <= x1 xor t1;
next_state <= round_part8;
when round_part8 =>
r_next <= r + 1;
next_state <= start_round;
when start_round =>
if ( r = 1 ) then
in_Vector_B_addr0 <= x"00000000";
Vector_B_rENA0 <= '1';
next_state <= extra5;
elsif ( r = 2 ) then
in_Vector_B_addr0 <= x"00000008";
Vector_B_rENA0 <= '1';
next_state <= extra13;
elsif ( r = 3 ) then
in_Vector_B_addr0 <= x"00000010";
Vector_B_rENA0 <= '1';
next_state <= extra21;
elsif ( r = 4 ) then
in_Vector_B_addr0 <= x"00000018";
Vector_B_rENA0 <= '1';
next_state <= extra29;
elsif ( r = 5 ) then
in_Vector_B_addr0 <= x"00000020";
Vector_B_rENA0 <= '1';
next_state <= extra37;
elsif ( r = 6 ) then
in_Vector_B_addr0 <= x"00000028";
Vector_B_rENA0 <= '1';
next_state <= extra45;
elsif ( r = 7 ) then
in_Vector_B_addr0 <= x"00000030";
Vector_B_rENA0 <= '1';
next_state <= extra53;
elsif ( r = 8 ) then
in_Vector_B_addr0 <= x"00000038";
Vector_B_rENA0 <= '1';
next_state <= extra61;
else
in_Vector_B_addr0 <= x"00000040";
Vector_B_rENA0 <= '1';
next_state <= extra69;
end if;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
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