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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2425.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n02i02425ent IS
END c07s03b02x01p01n02i02425ent;
ARCHITECTURE c07s03b02x01p01n02i02425arch OF c07s03b02x01p01n02i02425ent IS
type rec is record
a: integer;
b: integer;
c: integer;
d: integer;
end record;
constant y: rec := (a => 12, others => 10); -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(y.a=12 and y.b=10 and y.c=10 and y.d=10)
report "***PASSED TEST: c07s03b02x01p01n02i02425"
severity NOTE;
assert (y.a=12 and y.b=10 and y.c=10 and y.d=10)
report "***FAILED TEST: c07s03b02x01p01n02i02425 - If the choice others is given as a choice of a record aggregate, it must represent at least one element."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n02i02425arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2425.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n02i02425ent IS
END c07s03b02x01p01n02i02425ent;
ARCHITECTURE c07s03b02x01p01n02i02425arch OF c07s03b02x01p01n02i02425ent IS
type rec is record
a: integer;
b: integer;
c: integer;
d: integer;
end record;
constant y: rec := (a => 12, others => 10); -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(y.a=12 and y.b=10 and y.c=10 and y.d=10)
report "***PASSED TEST: c07s03b02x01p01n02i02425"
severity NOTE;
assert (y.a=12 and y.b=10 and y.c=10 and y.d=10)
report "***FAILED TEST: c07s03b02x01p01n02i02425 - If the choice others is given as a choice of a record aggregate, it must represent at least one element."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n02i02425arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2425.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n02i02425ent IS
END c07s03b02x01p01n02i02425ent;
ARCHITECTURE c07s03b02x01p01n02i02425arch OF c07s03b02x01p01n02i02425ent IS
type rec is record
a: integer;
b: integer;
c: integer;
d: integer;
end record;
constant y: rec := (a => 12, others => 10); -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(y.a=12 and y.b=10 and y.c=10 and y.d=10)
report "***PASSED TEST: c07s03b02x01p01n02i02425"
severity NOTE;
assert (y.a=12 and y.b=10 and y.c=10 and y.d=10)
report "***FAILED TEST: c07s03b02x01p01n02i02425 - If the choice others is given as a choice of a record aggregate, it must represent at least one element."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n02i02425arch;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_aa_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_aa_e-rtl-a_1.vhd,v 1.1 2007/03/03 17:24:06 wig Exp $
-- $Date: 2007/03/03 17:24:06 $
-- $Log: inst_aa_e-rtl-a_1.vhd,v $
-- Revision 1.1 2007/03/03 17:24:06 wig
-- Updated testcase for case matches. Added filename serialization.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_aa_e
--
architecture rtl of inst_aa_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: ahbctrl
-- File: ahbctrl.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Modified: Edvin Catovic, Gaisler Research
-- Description: AMBA arbiter, decoder and multiplexer with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.config_types.all;
use grlib.config.all;
-- pragma translate_off
use grlib.devices.all;
use std.textio.all;
-- pragma translate_on
entity ahbctrl is
generic (
defmast : integer := 0; -- default master
split : integer := 0; -- split support
rrobin : integer := 0; -- round-robin arbitration
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#; -- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask
nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen : integer range 0 to 15 := 1; -- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- report cores to console
fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding
icheck : integer range 0 to 1 := 1;
devid : integer := 0; -- unique device ID
enbusmon : integer range 0 to 1 := 0; --enable bus monitor
assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings
asserterr : integer range 0 to 1 := 0; --enable assertions for errors
hmstdisable : integer := 0; --disable master checks
hslvdisable : integer := 0; --disable slave checks
arbdisable : integer := 0; --disable arbiter checks
mprio : integer := 0; --master with highest priority
mcheck : integer range 0 to 2 := 1; --check memory map for intersects
ccheck : integer range 0 to 1 := 1; --perform sanity checks on pnp config
acdm : integer := 0; --AMBA compliant data muxing (for hsize > word)
index : integer := 0; --Index for trace print-out
ahbtrace : integer := 0; --AHB trace enable
hwdebug : integer := 0; --Hardware debug
fourgslv : integer := 0 --1=Single slave with single 4 GB bar
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
msti : out ahb_mst_in_type;
msto : in ahb_mst_out_vector;
slvi : out ahb_slv_in_type;
slvo : in ahb_slv_out_vector;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
scanen : in std_ulogic := '0';
testoen : in std_ulogic := '1';
testsig : in std_logic_vector(1+GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra) downto 0) := (others => '0')
);
end;
architecture rtl of ahbctrl is
constant nahbmx : integer := 2**log2(nahbm);
type nmstarr is array (1 to 3) of integer range 0 to nahbmx-1;
type nvalarr is array (1 to 3) of boolean;
type reg_type is record
hmaster : integer range 0 to nahbmx -1;
hmasterd : integer range 0 to nahbmx -1;
hslave : integer range 0 to nahbs-1;
hmasterlock : std_ulogic;
hmasterlockd : std_ulogic;
hready : std_ulogic;
defslv : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
haddr : std_logic_vector(15 downto 2);
cfgsel : std_ulogic;
cfga11 : std_ulogic;
hrdatam : std_logic_vector(31 downto 0);
hrdatas : std_logic_vector(31 downto 0);
beat : std_logic_vector(3 downto 0);
defmst : std_ulogic;
ldefmst : std_ulogic;
lsplmst : integer range 0 to nahbmx-1;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES_r : reg_type := (
hmaster => 0, hmasterd => 0, hslave => 0, hmasterlock => '0',
hmasterlockd => '0', hready => '1', defslv => '0',
htrans => HTRANS_IDLE, hsize => (others => '0'),
haddr => (others => '0'), cfgsel => '0', cfga11 => '0',
hrdatam => (others => '0'), hrdatas => (others => '0'),
beat => (others => '0'), defmst => '0', ldefmst => '0',
lsplmst => 0);
constant RES_split : std_logic_vector(0 to nahbmx-1) := (others => '0');
constant primst : std_logic_vector(NAHBMST downto 0) := conv_std_logic_vector(mprio, NAHBMST+1);
type l0_type is array (0 to 15) of std_logic_vector(2 downto 0);
type l1_type is array (0 to 7) of std_logic_vector(3 downto 0);
type l2_type is array (0 to 3) of std_logic_vector(4 downto 0);
type l3_type is array (0 to 1) of std_logic_vector(5 downto 0);
type tztab_type is array (0 to 15) of std_logic_vector(2 downto 0);
--returns the index number of the highest priority request
--signal in the two lsb bits when indexed with a 4-bit
--request vector with the highest priority signal on the
--lsb. the returned msb bit indicates if a request was
--active ('1' = no request active corresponds to "0000")
constant tztab : tztab_type := ("100", "000", "001", "000",
"010", "000", "001", "000",
"011", "000", "001", "000",
"010", "000", "001", "000");
--calculate the number of the highest priority request signal(up to 64
--requests are supported) in vect_in using a divide and conquer
--algorithm. The lower the index in the vector the higher the priority
--of the signal. First 4-bit slices are indexed in tztab and the msb
--indicates whether there is an active request or not. Then the resulting
--3 bit vectors are compared in pairs (the one corresponding to (3:0) with
--(7:4), (11:8) with (15:12) and so on). If the least significant of the two
--contains an active signal a '0' is added to the msb side (the vector
--becomes one bit wider at each level) to the next level to indicate that
--there are active signals in the lower nibble of the two. Otherwise
--the msb is removed from the vector corresponding to the higher nibble
--and "10" is added if it does not contain active requests and "01" if
--does contain active signals. Thus the msb still indicates if the new
--slice contains active signals and a '1' is added if it is the higher
--part. This results in a 6-bit vector containing the index number
--of the highest priority master in 5:0 if bit 6 is '0' otherwise
--no master requested the bus.
function tz(vect_in : std_logic_vector) return std_logic_vector is
variable vect : std_logic_vector(63 downto 0);
variable l0 : l0_type;
variable l1 : l1_type;
variable l2 : l2_type;
variable l3 : l3_type;
variable l4 : std_logic_vector(6 downto 0);
variable bci_lsb, bci_msb : std_logic_vector(3 downto 0);
variable bco_lsb, bco_msb : std_logic_vector(2 downto 0);
variable sel : std_logic;
begin
vect := (others => '1');
vect(vect_in'length-1 downto 0) := vect_in;
-- level 0
for i in 0 to 7 loop
bci_lsb := vect(8*i+3 downto 8*i);
bci_msb := vect(8*i+7 downto 8*i+4);
--lookup the highest priority request in each nibble
bco_lsb := tztab(conv_integer(bci_lsb));
bco_msb := tztab(conv_integer(bci_msb));
--select which of two nibbles contain the highest priority ACTIVE
--signal, and forward the corresponding vector to the next level
sel := bco_lsb(2);
if sel = '0' then l1(i) := '0' & bco_lsb;
else l1(i) := bco_msb(2) & not bco_msb(2) & bco_msb(1 downto 0); end if;
end loop;
-- level 1
for i in 0 to 3 loop
sel := l1(2*i)(3);
--select which of two 8-bit vectors contain the
--highest priority ACTIVE signal. the msb set at the previous level
--for each 8-bit slice determines this
if sel = '0' then l2(i) := '0' & l1(2*i);
else
l2(i) := l1(2*i+1)(3) & not l1(2*i+1)(3) & l1(2*i+1)(2 downto 0);
end if;
end loop;
-- level 2
for i in 0 to 1 loop
--16-bit vectors, the msb set at the previous level for each 16-bit
--slice determines the higher priority slice
sel := l2(2*i)(4);
if sel = '0' then l3(i) := '0' & l2(2*i);
else
l3(i) := l2(2*i+1)(4) & not l2(2*i+1)(4) & l2(2*i+1)(3 downto 0);
end if;
end loop;
--level 3
--32-bit vectors, the msb set at the previous level for each 32-bit
--slice determines the higher priority slice
if l3(0)(5) = '0' then l4 := '0' & l3(0);
else l4 := l3(1)(5) & not l3(1)(5) & l3(1)(4 downto 0); end if;
return(l4);
end;
--invert the bit order of the hbusreq signals located in vect_in
--since the highest hbusreq has the highest priority but the
--algorithm in tz has the highest priority on lsb
function lz(vect_in : std_logic_vector) return std_logic_vector is
variable vect : std_logic_vector(vect_in'length-1 downto 0);
variable vect2 : std_logic_vector(vect_in'length-1 downto 0);
begin
vect := vect_in;
for i in vect'right to vect'left loop
vect2(i) := vect(vect'left-i);
end loop;
return(tz(vect2));
end;
-- Find next master:
-- * 2 arbitration policies: fixed priority or round-robin
-- * Fixed priority: priority is fixed, highest index has highest priority
-- * Round-robin: arbiter maintains circular queue of masters
-- * (master 0, master 1, ..., master (nahbmx-1)). First requesting master
-- * in the queue is granted access to the bus and moved to the end of the queue.
-- * splitted masters are not granted
-- * bus is re-arbited when current owner does not request the bus,
-- or when it performs non-burst accesses
-- * fix length burst transfers will not be interrupted
-- * incremental bursts should assert hbusreq until last access
procedure selmast(r : in reg_type;
msto : in ahb_mst_out_vector;
rsplit : in std_logic_vector(0 to nahbmx-1);
mast : out integer range 0 to nahbmx-1;
defmst : out std_ulogic) is
variable nmst : nmstarr;
variable nvalid : nvalarr;
variable rrvec : std_logic_vector(nahbmx*2-1 downto 0);
variable zcnt : std_logic_vector(log2(nahbmx)+1 downto 0);
variable hpvec : std_logic_vector(nahbmx-1 downto 0);
variable zcnt2 : std_logic_vector(log2(nahbmx) downto 0);
begin
nvalid(1 to 3) := (others => false); nmst(1 to 3) := (others => 0);
mast := r.hmaster;
defmst := '0';
if nahbm = 1 then
mast := 0;
elsif rrobin = 0 then
hpvec := (others => '0');
for i in 0 to nahbmx-1 loop
--masters which have received split are not granted
if ((rsplit(i) = '0') or (split = 0)) then
hpvec(i) := msto(i).hbusreq;
end if;
end loop;
--check if any bus requests are active (nvalid(2) set to true)
--and determine the index (zcnt2) of the highest priority master
zcnt2 := lz(hpvec)(log2(nahbmx) downto 0);
if zcnt2(log2(nahbmx)) = '0' then nvalid(2) := true; end if;
nmst(2) := conv_integer(not (zcnt2(log2(nahbmx)-1 downto 0)));
--find the default master number
for i in 0 to nahbmx-1 loop
if not ((nmst(3) = defmast) and nvalid(3)) then
nmst(3) := i; nvalid(3) := true;
end if;
end loop;
else
rrvec := (others => '0');
--mask requests up to and including current master. Concatenate
--an unmasked request vector above the masked vector. Otherwise
--the rules are the same as for fixed priority
for i in 0 to nahbmx-1 loop
if ((rsplit(i) = '0') or (split = 0)) then
if (i <= r.hmaster) then rrvec(i) := '0';
else rrvec(i) := msto(i).hbusreq; end if;
rrvec(nahbmx+i) := msto(i).hbusreq;
end if;
end loop;
--find the next master uzing tz which gives priority to lower
--indexes
zcnt := tz(rrvec)(log2(nahbmx)+1 downto 0);
--was there a master requesting the bus?
if zcnt(log2(nahbmx)+1) = '0' then nvalid(2) := true; end if;
nmst(2) := conv_integer(zcnt(log2(nahbmx)-1 downto 0));
--if no other master is requesting the bus select the current one
nmst(3) := r.hmaster; nvalid(3) := true;
--check if any masters configured with higher priority are requesting
--the bus
if mprio /= 0 then
for i in 0 to nahbm-1 loop
if (((rsplit(i) = '0') or (split = 0)) and (primst(i) = '1')) then
if msto(i).hbusreq = '1' then nmst(1) := i; nvalid(1) := true; end if;
end if;
end loop;
end if;
end if;
--select the next master. If for round robin a high priority master
--(mprio) requested the bus if nvalid(1) is true. Otherwise
--if nvalid(2) is true at least one master was requesting the bus
--and the one with highest priority was selected. If none of these
--were true then the default master is selected (nvalid(3) true)
for i in 1 to 3 loop
if nvalid(i) then mast := nmst(i); exit; end if;
end loop;
--if no master was requesting the bus and split is enabled
--then select builtin dummy master which only does
--idle transfers
if (not (nvalid(1) or nvalid(2))) and (split /= 0) then
defmst := orv(rsplit);
end if;
end;
constant MIMAX : integer := log2x(nahbmx) - 1;
constant SIMAX : integer := log2x(nahbs) - 1;
constant IOAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(ioaddr, 12);
constant IOMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(iomask, 12);
constant CFGAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(cfgaddr, 12);
constant CFGMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(cfgmask, 12);
constant FULLPNP : boolean := (fpnpen /= 0);
signal r, rin : reg_type;
signal rsplit, rsplitin : std_logic_vector(0 to nahbmx-1);
-- pragma translate_off
signal lmsti : ahb_mst_in_type;
signal lslvi : ahb_slv_in_type;
-- pragma translate_on
begin
comb : process(rst, msto, slvo, r, rsplit, testen, testrst, scanen, testoen, testsig)
variable v : reg_type;
variable nhmaster: integer range 0 to nahbmx -1;
variable hgrant : std_logic_vector(0 to NAHBMST-1); -- bus grant
variable hsel : std_logic_vector(0 to 31); -- slave select
variable hmbsel : std_logic_vector(0 to NAHBAMR-1);
variable nslave : natural range 0 to 31;
variable vsplit : std_logic_vector(0 to nahbmx-1);
variable bnslave : std_logic_vector(3 downto 0);
variable area : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable defslv : std_ulogic;
variable cfgsel : std_ulogic;
variable hresp : std_logic_vector(1 downto 0);
variable hrdata : std_logic_vector(AHBDW-1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable arb : std_ulogic;
variable hconfndx : integer range 0 to 7;
variable vslvi : ahb_slv_in_type;
variable defmst : std_ulogic;
variable tmpv : std_logic_vector(0 to nahbmx-1);
begin
v := r; hgrant := (others => '0'); defmst := '0';
haddr := msto(r.hmaster).haddr;
nhmaster := r.hmaster;
--determine if bus should be rearbitrated. This is done if the current
--master is not performing a locked transfer and if not in the middle
--of burst
arb := '0';
if (r.hmasterlock or r.ldefmst) = '0' then
case msto(r.hmaster).htrans is
when HTRANS_IDLE => arb := '1';
when HTRANS_NONSEQ =>
case msto(r.hmaster).hburst is
when HBURST_SINGLE => arb := '1';
when HBURST_INCR => arb := not msto(r.hmaster).hbusreq;
when others =>
end case;
when HTRANS_SEQ =>
case msto(r.hmaster).hburst is
when HBURST_WRAP4 | HBURST_INCR4 => if (fixbrst = 1) and (r.beat(1 downto 0) = "11") then arb := '1'; end if;
when HBURST_WRAP8 | HBURST_INCR8 => if (fixbrst = 1) and (r.beat(2 downto 0) = "111") then arb := '1'; end if;
when HBURST_WRAP16 | HBURST_INCR16 => if (fixbrst = 1) and (r.beat(3 downto 0) = "1111") then arb := '1'; end if;
when HBURST_INCR => arb := not msto(r.hmaster).hbusreq;
when others =>
end case;
when others => arb := '0';
end case;
end if;
if (split /= 0) then
for i in 0 to nahbmx-1 loop
tmpv(i) := (msto(i).htrans(1) or (msto(i).hbusreq)) and not rsplit(i) and not r.ldefmst;
end loop;
if (r.defmst and orv(tmpv)) = '1' then arb := '1'; end if;
end if;
--rearbitrate bus with selmast. If not arbitrated one must
--ensure that the dummy master is selected for locked splits.
if (arb = '1') then
selmast(r, msto, rsplit, nhmaster, defmst);
elsif (split /= 0) then
defmst := r.defmst;
end if;
-- slave decoding
hsel := (others => '0'); hmbsel := (others => '0');
if fourgslv = 0 then
for i in 0 to nahbs-1 loop
for j in NAHBIR to NAHBCFG-1 loop
area := slvo(i).hconfig(j)(1 downto 0);
case area is
when "10" =>
if ((ioen = 0) or ((IOAREA and IOMSK) /= (haddr(31 downto 20) and IOMSK))) and
((slvo(i).hconfig(j)(31 downto 20) and slvo(i).hconfig(j)(15 downto 4)) =
(haddr(31 downto 20) and slvo(i).hconfig(j)(15 downto 4))) and
(slvo(i).hconfig(j)(15 downto 4) /= "000000000000")
then hsel(i) := '1'; hmbsel(j-NAHBIR) := '1'; end if;
when "11" =>
if ((ioen /= 0) and ((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK))) and
((slvo(i).hconfig(j)(31 downto 20) and slvo(i).hconfig(j)(15 downto 4)) =
(haddr(19 downto 8) and slvo(i).hconfig(j)(15 downto 4))) and
(slvo(i).hconfig(j)(15 downto 4) /= "000000000000")
then hsel(i) := '1'; hmbsel(j-NAHBIR) := '1'; end if;
when others =>
end case;
end loop;
end loop;
else
-- There is only one slave on the bus. The slave has only one bar, which
-- maps 4 GB address space.
hsel(0) := '1'; hmbsel(0) := '1';
end if;
if r.defmst = '1' then hsel := (others => '0'); end if;
bnslave(0) := hsel(1) or hsel(3) or hsel(5) or hsel(7) or
hsel(9) or hsel(11) or hsel(13) or hsel(15);
bnslave(1) := hsel(2) or hsel(3) or hsel(6) or hsel(7) or
hsel(10) or hsel(11) or hsel(14) or hsel(15);
bnslave(2) := hsel(4) or hsel(5) or hsel(6) or hsel(7) or
hsel(12) or hsel(13) or hsel(14) or hsel(15);
bnslave(3) := hsel(8) or hsel(9) or hsel(10) or hsel(11) or
hsel(12) or hsel(13) or hsel(14) or hsel(15);
nslave := conv_integer(bnslave(SIMAX downto 0));
if ((((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK)) and (ioen /= 0))
or ((IOAREA = haddr(31 downto 20)) and (ioen = 0))) and
((CFGAREA and CFGMSK) = (haddr(19 downto 8) and CFGMSK))
and (cfgmask /= 0)
then cfgsel := '1'; hsel := (others => '0');
else cfgsel := '0'; end if;
if (nslave = 0) and (hsel(0) = '0') and (cfgsel = '0') then defslv := '1';
else defslv := '0'; end if;
if r.defmst = '1' then
cfgsel := '0'; defslv := '1';
end if;
-- error response on undecoded area
v.hready := '0';
hready := slvo(r.hslave).hready; hresp := slvo(r.hslave).hresp;
if r.defslv = '1' then
-- default slave
if (r.htrans = HTRANS_IDLE) or (r.htrans = HTRANS_BUSY) then
hresp := HRESP_OKAY; hready := '1';
else
-- return two-cycle error in case of unimplemented slave access
hresp := HRESP_ERROR; hready := r.hready; v.hready := not r.hready;
end if;
end if;
if acdm = 0 then
hrdata := slvo(r.hslave).hrdata;
else
hrdata := ahbselectdata(slvo(r.hslave).hrdata, r.haddr(4 downto 2), r.hsize);
end if;
if cfgmask /= 0 then
-- plug&play information for masters
if FULLPNP then hconfndx := conv_integer(r.haddr(4 downto 2)); else hconfndx := 0; end if;
if (r.haddr(10 downto MIMAX+6) = zero32(10 downto MIMAX+6)) and (FULLPNP or (r.haddr(4 downto 2) = "000"))
then v.hrdatam := msto(conv_integer(r.haddr(MIMAX+5 downto 5))).hconfig(hconfndx);
else v.hrdatam := (others => '0'); end if;
-- plug&play information for slaves
if (r.haddr(10 downto SIMAX+6) = zero32(10 downto SIMAX+6)) and
(FULLPNP or (r.haddr(4 downto 2) = "000") or (r.haddr(4) = '1'))
then v.hrdatas := slvo(conv_integer(r.haddr(SIMAX+5 downto 5))).hconfig(conv_integer(r.haddr(4 downto 2)));
else v.hrdatas := (others => '0'); end if;
-- device ID, library build and potentially debug information
if r.haddr(10 downto 4) = "1111111" then
if hwdebug = 0 or r.haddr(3 downto 2) = "00" then
v.hrdatas(15 downto 0) := conv_std_logic_vector(LIBVHDL_BUILD, 16);
v.hrdatas(31 downto 16) := conv_std_logic_vector(devid, 16);
elsif r.haddr(3 downto 2) = "01" then
for i in 0 to nahbmx-1 loop v.hrdatas(i) := msto(i).hbusreq; end loop;
else
for i in 0 to nahbmx-1 loop v.hrdatas(i) := rsplit(i); end loop;
end if;
end if;
if r.cfgsel = '1' then
hrdata := (others => '0');
-- default slave
if (r.htrans = HTRANS_IDLE) or (r.htrans = HTRANS_BUSY) then
hresp := HRESP_OKAY; hready := '1';
else
-- return two-cycle read/write respons
hresp := HRESP_OKAY; hready := r.hready; v.hready := not r.hready;
end if;
if r.cfga11 = '0' then hrdata := ahbdrivedata(r.hrdatam);
else hrdata := ahbdrivedata(r.hrdatas); end if;
end if;
end if;
--degrant all masters when split occurs for locked access
if (r.hmasterlockd = '1') then
if (hresp = HRESP_RETRY) or ((split /= 0) and (hresp = HRESP_SPLIT)) then
nhmaster := r.hmaster;
end if;
if split /= 0 then
if hresp = HRESP_SPLIT then
v.ldefmst := '1'; defmst := '1';
v.lsplmst := nhmaster;
end if;
end if;
end if;
if split /= 0 and r.ldefmst = '1' then
if rsplit(r.lsplmst) = '0' then
v.ldefmst := '0'; defmst := '0';
end if;
end if;
if (split = 0) or (defmst = '0') then hgrant(nhmaster) := '1'; end if;
-- latch active master and slave
if hready = '1' then
v.hmaster := nhmaster; v.hmasterd := r.hmaster;
v.hsize := msto(r.hmaster).hsize;
v.hslave := nslave; v.defslv := defslv;
v.hmasterlockd := r.hmasterlock;
if (split = 0) or (r.defmst = '0') then v.htrans := msto(r.hmaster).htrans;
else v.htrans := HTRANS_IDLE; end if;
v.cfgsel := cfgsel;
v.cfga11 := msto(r.hmaster).haddr(11);
v.haddr := msto(r.hmaster).haddr(15 downto 2);
if (msto(r.hmaster).htrans = HTRANS_NONSEQ) or (msto(r.hmaster).htrans = HTRANS_IDLE) then
v.beat := "0001";
elsif (msto(r.hmaster).htrans = HTRANS_SEQ) then
if (fixbrst = 1) then v.beat := r.beat + 1; end if;
end if;
if (split /= 0) then v.defmst := defmst; end if;
end if;
--assign new hmasterlock, v.hmaster is used because if hready
--then master can have changed, and when not hready then the
--previous master will still be selected
v.hmasterlock := msto(v.hmaster).hlock or (r.hmasterlock and not hready);
--if the master asserting hlock received a SPLIT/RETRY response
--to the previous access then disregard the current lock request.
--the bus will otherwise be locked when the previous access is
--retried instead of treating hlock as coupled to the next access.
--use hmasterlockd to keep the bus locked for SPLIT/RETRY to locked
--accesses.
if v.hmaster = r.hmasterd and slvo(r.hslave).hresp(1) = '1' then
if r.hmasterlockd = '0' then
v.hmasterlock := '0'; v.hmasterlockd := '0';
end if;
end if;
-- split support
vsplit := (others => '0');
if SPLIT /= 0 then
vsplit := rsplit;
if slvo(r.hslave).hresp = HRESP_SPLIT then vsplit(r.hmasterd) := '1'; end if;
for i in 0 to nahbs-1 loop
for j in 0 to nahbmx-1 loop
vsplit(j) := vsplit(j) and not slvo(i).hsplit(j);
end loop;
end loop;
end if;
-- interrupt merging
hirq := (others => '0');
if disirq = 0 then
for i in 0 to nahbs-1 loop hirq := hirq or slvo(i).hirq; end loop;
for i in 0 to nahbm-1 loop hirq := hirq or msto(i).hirq; end loop;
end if;
if (split = 0) or (r.defmst = '0') then
vslvi.haddr := haddr;
vslvi.htrans := msto(r.hmaster).htrans;
vslvi.hwrite := msto(r.hmaster).hwrite;
vslvi.hsize := msto(r.hmaster).hsize;
vslvi.hburst := msto(r.hmaster).hburst;
vslvi.hready := hready;
vslvi.hprot := msto(r.hmaster).hprot;
-- vslvi.hmastlock := msto(r.hmaster).hlock;
vslvi.hmastlock := r.hmasterlock;
vslvi.hmaster := conv_std_logic_vector(r.hmaster, 4);
vslvi.hsel := hsel(0 to NAHBSLV-1);
vslvi.hmbsel := hmbsel;
vslvi.hirq := hirq;
else
vslvi := ahbs_in_none;
vslvi.hready := hready;
vslvi.hirq := hirq;
end if;
if acdm = 0 then
vslvi.hwdata := msto(r.hmasterd).hwdata;
else
vslvi.hwdata := ahbselectdata(msto(r.hmasterd).hwdata, r.haddr(4 downto 2), r.hsize);
end if;
vslvi.testen := testen;
vslvi.testrst := testrst;
vslvi.scanen := scanen and testen;
vslvi.testoen := testoen;
vslvi.testin := testen & (scanen and testen) & testsig;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.hmaster := RES_r.hmaster; v.hmasterlock := RES_r.hmasterlock;
vsplit := (others => '0');
v.htrans := RES_r.htrans; v.defslv := RES_r.defslv;
v.hslave := RES_r.hslave; v.cfgsel := RES_r.cfgsel;
v.defmst := RES_r.defmst; v.ldefmst := RES_r.ldefmst;
end if;
-- drive master inputs
msti.hgrant <= hgrant;
msti.hready <= hready;
msti.hresp <= hresp;
msti.hrdata <= hrdata;
msti.hirq <= hirq;
msti.testen <= testen;
msti.testrst <= testrst;
msti.scanen <= scanen and testen;
msti.testoen <= testoen;
msti.testin <= testen & (scanen and testen) & testsig;
-- drive slave inputs
slvi <= vslvi;
-- pragma translate_off
--drive internal signals to bus monitor
lslvi <= vslvi;
lmsti.hgrant <= hgrant;
lmsti.hready <= hready;
lmsti.hresp <= hresp;
lmsti.hrdata <= hrdata;
lmsti.hirq <= hirq;
-- pragma translate_on
if split = 0 then v.ldefmst := '0'; v.lsplmst := 0; end if;
rin <= v; rsplitin <= vsplit;
end process;
reg0 : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES_r;
end if;
end if;
if (split = 0) then r.defmst <= '0'; end if;
end process;
splitreg : if SPLIT /= 0 generate
reg1 : process(clk)
begin
if rising_edge(clk) then
rsplit <= rsplitin;
if RESET_ALL and rst = '0' then
rsplit <= RES_split;
end if;
end if;
end process;
end generate;
nosplitreg : if SPLIT = 0 generate
rsplit <= (others => '0');
end generate;
-- pragma translate_off
ahblog : if ahbtrace /= 0 generate
log : process (clk)
variable hwrite : std_logic;
variable hsize : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable hmaster : std_logic_vector(3 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hwdata, hrdata : std_logic_vector(127 downto 0);
variable mbit, bitoffs : integer;
variable t : integer;
begin
if rising_edge(clk) then
if htrans(1)='1' and lmsti.hready='0' and (lmsti.hresp="01") then
if hwrite = '1' then
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " write " & tost(mbit/8) & " bytes [" & tost(lslvi.hwdata(mbit-1+bitoffs downto bitoffs)) & "] - ERROR!");
else
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " read " & tost(mbit/8) & " bytes [" & tost(lmsti.hrdata(mbit-1+bitoffs downto bitoffs)) & "] - ERROR!");
end if;
end if;
if ((htrans(1) and lmsti.hready) = '1') and (lmsti.hresp = "00") then
mbit := 2**conv_integer(hsize)*8;
bitoffs := 0;
if mbit < ahbdw then
bitoffs := mbit * conv_integer(haddr(log2(ahbdw/8)-1 downto conv_integer(hsize)));
bitoffs := lslvi.hwdata'length-mbit-bitoffs;
end if;
t := (now/1 ns);
if hwrite = '1' then
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " write " & tost(mbit/8) & " bytes [" & tost(lslvi.hwdata(mbit-1+bitoffs downto bitoffs)) & "]");
else
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " read " & tost(mbit/8) & " bytes [" & tost(lmsti.hrdata(mbit-1+bitoffs downto bitoffs)) & "]");
end if;
end if;
if lmsti.hready = '1' then
hwrite := lslvi.hwrite;
hsize := lslvi.hsize;
haddr := lslvi.haddr;
htrans := lslvi.htrans;
hmaster := lslvi.hmaster;
end if;
end if;
end process;
end generate;
mon0 : if enbusmon /= 0 generate
mon : ahbmon
generic map(
asserterr => asserterr,
assertwarn => assertwarn,
hmstdisable => hmstdisable,
hslvdisable => hslvdisable,
arbdisable => arbdisable,
nahbm => nahbm,
nahbs => nahbs)
port map(
rst => rst,
clk => clk,
ahbmi => lmsti,
ahbmo => msto,
ahbsi => lslvi,
ahbso => slvo,
err => open);
end generate;
diag : process
type ahbsbank_type is record
start : std_logic_vector(31 downto 8);
stop : std_logic_vector(31 downto 8);
io : std_ulogic;
end record;
type ahbsbanks_type is array (0 to 3) of ahbsbank_type;
type memmap_type is array (0 to nahbs-1) of ahbsbanks_type;
variable k : integer;
variable mask : std_logic_vector(11 downto 0);
variable device : std_logic_vector(11 downto 0);
variable devicei : integer;
variable vendor : std_logic_vector( 7 downto 0);
variable area : std_logic_vector( 1 downto 0);
variable vendori : integer;
variable iosize, tmp : integer;
variable iounit : string(1 to 5) := " byte";
variable memtype : string(1 to 9);
variable iostart : std_logic_vector(11 downto 0) := IOAREA and IOMSK;
variable cfgstart : std_logic_vector(11 downto 0) := CFGAREA and CFGMSK;
variable L1 : line := new string'("");
variable S1 : string(1 to 255);
variable memmap : memmap_type;
begin
wait for 2 ns;
if debug = 0 then wait; end if;
if debug > 0 then
k := 0; mask := IOMSK;
while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
print("ahbctrl: AHB arbiter/multiplexer rev 1");
if ioen /= 0 then
print("ahbctrl: Common I/O area at " & tost(iostart) & "00000, " & tost(2**k) & " Mbyte");
else
print("ahbctrl: Common I/O area disabled");
end if;
print("ahbctrl: AHB masters: " & tost(nahbm) & ", AHB slaves: " & tost(nahbs));
if cfgmask /= 0 then
print("ahbctrl: Configuration area at " & tost(iostart & cfgstart) & "00, 4 kbyte");
else
print("ahbctrl: Configuration area disabled");
end if;
end if;
for i in 0 to nahbm-1 loop
vendor := msto(i).hconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
if debug > 1 then
device := msto(i).hconfig(0)(23 downto 12);
devicei := conv_integer(device);
print("ahbctrl: mst" & tost(i) & ": " & iptable(vendori).vendordesc &
iptable(vendori).device_table(devicei));
end if;
for j in 1 to NAHBIR-1 loop
assert (msto(i).hconfig(j) = zx or FULLPNP or ccheck = 0 or cfgmask = 0)
report "AHB master " & tost(i) & " propagates non-zero user defined PnP data, " &
"but AHBCTRL full PnP decoding has not been enabled (check fpnpen VHDL generic)"
severity warning;
end loop;
assert (msto(i).hindex = i) or (icheck = 0)
report "AHB master index error on master " & tost(i) &
". Detected index value " & tost(msto(i).hindex) severity failure;
else
for j in 0 to NAHBCFG-1 loop
assert (msto(i).hconfig(j) = zx or ccheck = 0)
report "AHB master " & tost(i) & " appears to be disabled, " &
"but the master config record is not driven to zero " &
"(check vendor ID or drive unused bus index with appropriate values)."
severity warning;
end loop;
end if;
end loop;
if nahbm < NAHBMST then
for i in nahbm to NAHBMST-1 loop
for j in 0 to NAHBCFG-1 loop
assert (msto(i).hconfig(j) = zx or ccheck = 0)
report "AHB master " & tost(i) & " is outside the range of " &
"decoded master indexes but the master config record is not driven to zero " &
"(check nahbm VHDL generic)."
severity warning;
end loop;
end loop;
end if;
for i in 0 to nahbs-1 loop
vendor := slvo(i).hconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
if debug > 1 then
device := slvo(i).hconfig(0)(23 downto 12);
devicei := conv_integer(device);
std.textio.write(L1, "ahbctrl: slv" & tost(i) & ": " & iptable(vendori).vendordesc &
iptable(vendori).device_table(devicei));
std.textio.writeline(OUTPUT, L1);
end if;
for j in 1 to NAHBIR-1 loop
assert (slvo(i).hconfig(j) = zx or FULLPNP or ccheck = 0 or cfgmask = 0)
report "AHB slave " & tost(i) & " propagates non-zero user defined PnP data, " &
"but AHBCTRL full PnP decoding has not been enabled (check fpnpen VHDL generic)."
severity warning;
end loop;
for j in NAHBIR to NAHBCFG-1 loop
area := slvo(i).hconfig(j)(1 downto 0);
mask := slvo(i).hconfig(j)(15 downto 4);
memmap(i)(j mod NAHBIR).start := (others => '0');
memmap(i)(j mod NAHBIR).stop := (others => '0');
memmap(i)(j mod NAHBIR).io := slvo(i).hconfig(j)(0);
if (mask /= "000000000000" or fourgslv = 1) then
case area is
when "01" =>
when "10" =>
k := 0;
while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
if debug > 1 then
std.textio.write(L1, "ahbctrl: memory at " &
tost(slvo(i).hconfig(j)(31 downto 20) and mask) &
"00000, size "& tost(2**k) & " Mbyte");
if slvo(i).hconfig(j)(16) = '1' then
std.textio.write(L1, string'(", cacheable"));
end if;
if slvo(i).hconfig(j)(17) = '1' then
std.textio.write(L1, string'(", prefetch"));
end if;
std.textio.writeline(OUTPUT, L1);
end if;
memmap(i)(j mod NAHBIR).start(31 downto 20) := slvo(i).hconfig(j)(31 downto 20);
memmap(i)(j mod NAHBIR).start(31 downto 20) :=
(slvo(i).hconfig(j)(31 downto 20) and mask);
memmap(i)(j mod NAHBIR).start(19 downto 8) := (others => '0');
memmap(i)(j mod NAHBIR).stop := memmap(i)(j mod NAHBIR).start + 2**(k+12) - 1;
-- Be verbose if an address with bits set outside the area
-- selected by the mask is encountered
assert ((slvo(i).hconfig(j)(31 downto 20) and not mask) = zero32(11 downto 0)) report
"AHB slave " & tost(i) & " may decode an area larger than intended. Bar " &
tost(j mod NAHBIR) & " will have base address " &
tost(slvo(i).hconfig(j)(31 downto 20) and mask) &
"00000, the intended base address may have been " &
tost(slvo(i).hconfig(j)(31 downto 20)) & "00000"
severity warning;
when "11" =>
if ioen /= 0 then
k := 0;
while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
memmap(i)(j mod NAHBIR).start := iostart & (slvo(i).hconfig(j)(31 downto 20) and
slvo(i).hconfig(j)(15 downto 4));
memmap(i)(j mod NAHBIR).stop := memmap(i)(j mod NAHBIR).start + 2**k - 1;
if debug > 1 then
iosize := 256 * 2**k; iounit(1) := ' ';
if (iosize > 1023) then
iosize := iosize/1024; iounit(1) := 'k';
end if;
print("ahbctrl: I/O port at " & tost(iostart &
((slvo(i).hconfig(j)(31 downto 20)) and slvo(i).hconfig(j)(15 downto 4))) &
"00, size "& tost(iosize) & iounit);
end if;
assert ((slvo(i).hconfig(j)(31 downto 20) and not mask) = zero32(11 downto 0)) report
"AHB slave " & tost(i) & " may decode an I/O area larger than intended. Bar " &
tost(j mod NAHBIR) & " will have base address " &
tost(iostart & (slvo(i).hconfig(j)(31 downto 20) and mask)) &
"00, the intended base address may have been " &
tost(iostart & slvo(i).hconfig(j)(31 downto 20)) & "00"
severity warning;
else
assert false report
"AHB slave " & tost(i) & " maps bar " & tost(j mod NAHBIR) &
" to the IO area, but this AHBCTRL has been configured with VHDL generic ioen = 0"
severity warning;
end if;
when others =>
end case;
end if;
end loop;
assert (slvo(i).hindex = i) or (icheck = 0)
report "AHB slave index error on slave " & tost(i) &
". Detected index value " & tost(slvo(i).hindex) severity failure;
if mcheck /= 0 then
for j in 0 to i loop
for k in memmap(i)'range loop
if memmap(i)(k).stop /= zero32(memmap(i)(k).stop'range) then
for l in memmap(j)'range loop
assert ((memmap(i)(k).start >= memmap(j)(l).stop) or
(memmap(i)(k).stop <= memmap(j)(l).start) or
(mcheck /= 2 and (memmap(i)(k).io xor memmap(j)(l).io) = '1') or
(i = j and k = l))
report "AHB slave " & tost(i) & " bank " & tost(k) &
" intersects with AHB slave " & tost(j) & " bank " & tost(l)
severity failure;
end loop;
end if;
end loop;
end loop;
end if;
else
for j in 0 to NAHBCFG-1 loop
assert (slvo(i).hconfig(j) = zx or ccheck = 0)
report "AHB slave " & tost(i) & " appears to be disabled, " &
"but the slave config record is not driven to zero " &
"(check vendor ID or drive unused bus index with appropriate values)."
severity warning;
end loop;
end if;
end loop;
if nahbs < NAHBSLV then
for i in nahbs to NAHBSLV-1 loop
for j in 0 to NAHBCFG-1 loop
assert (slvo(i).hconfig(j) = zx or ccheck = 0)
report "AHB slave " & tost(i) & " is outside the range of " &
"decoded slave indexes but the slave config record is not driven to zero " &
"(check nahbs VHDL generic)."
severity warning;
end loop;
end loop;
end if;
wait;
end process;
-- pragma translate_on
end;
|
lpm_add_sub1_inst : lpm_add_sub1 PORT MAP (
dataa => dataa_sig,
datab => datab_sig,
cout => cout_sig,
result => result_sig
);
|
-- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2017 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/chameleon.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- 1 Mhz clock source
--
-- -----------------------------------------------------------------------
-- clk_ticks_per_usec - Specifies clockspeed of clk in MHz, calibrates timer.
-- -----------------------------------------------------------------------
-- clk - system clock input
-- ena_1mhz - 1 Mhz output. Signal is one cycle '1' each micro-second.
-- ena_1mhz_2 - One cycle trigger output that shifted by 0.5 micro-second against ena_1mhz
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon_1mhz is
generic (
clk_ticks_per_usec : integer
);
port (
clk : in std_logic;
ena_1mhz : out std_logic;
ena_1mhz_2 : out std_logic
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_1mhz is
constant maxcount : integer := clk_ticks_per_usec-1;
signal cnt : integer range 0 to maxcount := maxcount;
signal ena_out : std_logic := '0';
signal ena2_out : std_logic := '0';
begin
ena_1mhz <= ena_out;
ena_1mhz_2 <= ena2_out;
process(clk)
begin
if rising_edge(clk) then
ena_out <= '0';
if cnt = 0 then
cnt <= maxcount;
ena_out <= '1';
else
cnt <= cnt - 1;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
ena2_out <= '0';
if cnt = (maxcount / 2) then
ena2_out <= '1';
end if;
end if;
end process;
end architecture;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package textio is
type line is access string;
type text is file of string;
type side is (right, left);
subtype width is natural;
file input : text open read_mode is "std_input";
file output : text open write_mode is "std_output";
procedure readline(file f: text; l: out line);
procedure read ( L : inout line; value: out bit; good : out boolean );
procedure read ( L : inout line; value: out bit );
procedure read ( L : inout line; value: out bit_vector; good : out boolean );
procedure read ( L : inout line; value: out bit_vector );
procedure read ( L : inout line; value: out boolean; good : out boolean );
procedure read ( L : inout line; value: out boolean );
procedure read ( L : inout line; value: out character; good : out boolean );
procedure read ( L : inout line; value: out character );
procedure read ( L : inout line; value: out integer; good : out boolean );
procedure read ( L : inout line; value: out integer );
procedure read ( L : inout line; value: out real; good : out boolean );
procedure read ( L : inout line; value: out real );
procedure read ( L : inout line; value: out string; good : out boolean );
procedure read ( L : inout line; value: out string );
procedure read ( L : inout line; value: out time; good : out boolean );
procedure read ( L : inout line; value: out time );
procedure writeline ( file f : text; L : inout line );
procedure write ( L : inout line; value : in bit;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in bit_vector;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in boolean;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in character;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in integer;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in real;
justified: in side := right; field: in width := 0;
digits: in natural := 0 );
procedure write ( L : inout line; value : in string;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in time;
justified: in side := right; field: in width := 0;
unit: in time := ns );
end package textio;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package textio is
type line is access string;
type text is file of string;
type side is (right, left);
subtype width is natural;
file input : text open read_mode is "std_input";
file output : text open write_mode is "std_output";
procedure readline(file f: text; l: out line);
procedure read ( L : inout line; value: out bit; good : out boolean );
procedure read ( L : inout line; value: out bit );
procedure read ( L : inout line; value: out bit_vector; good : out boolean );
procedure read ( L : inout line; value: out bit_vector );
procedure read ( L : inout line; value: out boolean; good : out boolean );
procedure read ( L : inout line; value: out boolean );
procedure read ( L : inout line; value: out character; good : out boolean );
procedure read ( L : inout line; value: out character );
procedure read ( L : inout line; value: out integer; good : out boolean );
procedure read ( L : inout line; value: out integer );
procedure read ( L : inout line; value: out real; good : out boolean );
procedure read ( L : inout line; value: out real );
procedure read ( L : inout line; value: out string; good : out boolean );
procedure read ( L : inout line; value: out string );
procedure read ( L : inout line; value: out time; good : out boolean );
procedure read ( L : inout line; value: out time );
procedure writeline ( file f : text; L : inout line );
procedure write ( L : inout line; value : in bit;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in bit_vector;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in boolean;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in character;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in integer;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in real;
justified: in side := right; field: in width := 0;
digits: in natural := 0 );
procedure write ( L : inout line; value : in string;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in time;
justified: in side := right; field: in width := 0;
unit: in time := ns );
end package textio;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package textio is
type line is access string;
type text is file of string;
type side is (right, left);
subtype width is natural;
file input : text open read_mode is "std_input";
file output : text open write_mode is "std_output";
procedure readline(file f: text; l: out line);
procedure read ( L : inout line; value: out bit; good : out boolean );
procedure read ( L : inout line; value: out bit );
procedure read ( L : inout line; value: out bit_vector; good : out boolean );
procedure read ( L : inout line; value: out bit_vector );
procedure read ( L : inout line; value: out boolean; good : out boolean );
procedure read ( L : inout line; value: out boolean );
procedure read ( L : inout line; value: out character; good : out boolean );
procedure read ( L : inout line; value: out character );
procedure read ( L : inout line; value: out integer; good : out boolean );
procedure read ( L : inout line; value: out integer );
procedure read ( L : inout line; value: out real; good : out boolean );
procedure read ( L : inout line; value: out real );
procedure read ( L : inout line; value: out string; good : out boolean );
procedure read ( L : inout line; value: out string );
procedure read ( L : inout line; value: out time; good : out boolean );
procedure read ( L : inout line; value: out time );
procedure writeline ( file f : text; L : inout line );
procedure write ( L : inout line; value : in bit;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in bit_vector;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in boolean;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in character;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in integer;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in real;
justified: in side := right; field: in width := 0;
digits: in natural := 0 );
procedure write ( L : inout line; value : in string;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in time;
justified: in side := right; field: in width := 0;
unit: in time := ns );
end package textio;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity chroma_motion is
generic(
data_width : integer := 64;
addr_width : integer := 4;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic
--debug
--state_out : out std_logic_vector(7 downto 0)
);
end entity chroma_motion;
architecture fsmd of chroma_motion is
--- Components ------------------------------------------------------------
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
--- Types -----------------------------------------------------------------
type chroma_motion_states is (idle,
sel_vc,
rx_header,
dequeue_header,
wait_rx_cr,
rx_cr,
dequeue_cr,
wait_rx_cb,
rx_cb,
dequeue_cb,
wait_rx_crcb,
rx_crcb,
dequeue_crcb,
wait_tx_header,
tx_header,
wait_tx_data,
tx_data);
type reference_array is array (8 downto 0) of integer;
type result_array is array (3 downto 0) of integer;
--- signals and registers -------------------------------------------------
signal cr_ref_d : reference_array;
signal cb_ref_d : reference_array;
signal cr_ref_q : reference_array;
signal cb_ref_q : reference_array;
signal cr_result : result_array;
signal cb_result : result_array;
signal cr_x_frac_d : integer;
signal cr_y_frac_d : integer;
signal cr_x_frac_q : integer;
signal cr_y_frac_q : integer;
signal cb_x_frac_d : integer;
signal cb_y_frac_d : integer;
signal cb_x_frac_q : integer;
signal cb_y_frac_q : integer;
signal ref_d : std_logic_vector(7 downto 0);
signal ref_q : std_logic_vector(7 downto 0);
signal result_vect : std_logic_vector(63 downto 0);
signal resp_header : std_logic_vector(63 downto 0);
signal state : chroma_motion_states;
signal next_state : chroma_motion_states;
signal sel_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_enc : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_one_hot : std_logic_vector(num_vc-1 downto 0);
begin
---------------------------------------------------------------------------
--- DATAPATH --------------------------------------------------------------
---------------------------------------------------------------------------
--components
u2: component priority_encoder
generic map(
encoded_word_size => vc_sel_width
)
Port map(
input => data_in_buffer,
output => sel_vc_enc
);
--registers
regs: process(clk, rst) begin
if rst = '1' then
cr_ref_q <= (others => 0);
cb_ref_q <= (others => 0);
cr_x_frac_q <= 0;
cr_y_frac_q <= 0;
cb_x_frac_q <= 0;
cb_y_frac_q <= 0;
ref_q <= (others => '0');
sel_vc_q <= (others => '0');
state <= idle;
elsif rising_edge(clk) then
cr_ref_q <= cr_ref_d;
cb_ref_q <= cb_ref_d;
cr_x_frac_q <= cr_x_frac_d;
cr_y_frac_q <= cr_y_frac_d;
cb_x_frac_q <= cb_x_frac_d;
cb_y_frac_q <= cb_y_frac_d;
ref_q <= ref_d;
sel_vc_q <= sel_vc_d;
state <= next_state;
end if;
end process;
--register update
reg_update: for i in 7 downto 0 generate
constant recv_data_low_index : integer := i * 8;
constant recv_data_high_index : integer := recv_data_low_index + 7;
begin
cr_ref_d(i) <= to_integer(unsigned(recv_data(recv_data_high_index downto
recv_data_low_index))) when state = rx_cr
else cr_ref_q(i);
cb_ref_d(i) <= to_integer(unsigned(recv_data(recv_data_high_index downto
recv_data_low_index))) when state = rx_cb
else cb_ref_q(i);
end generate;
cr_ref_d(8) <= to_integer(unsigned(recv_data(39 downto 32))) when state = rx_crcb else cr_ref_q(8);
cb_ref_d(8) <= to_integer(unsigned(recv_data(7 downto 0 ))) when state = rx_crcb else cb_ref_q(8);
cr_x_frac_d <= to_integer(unsigned(recv_data(39 downto 32))) when state = rx_header else cr_x_frac_q;
cr_y_frac_d <= to_integer(unsigned(recv_data(31 downto 24))) when state = rx_header else cr_y_frac_q;
cb_x_frac_d <= to_integer(unsigned(recv_data(23 downto 16))) when state = rx_header else cb_x_frac_q;
cb_y_frac_d <= to_integer(unsigned(recv_data(15 downto 8 ))) when state = rx_header else cb_y_frac_q;
ref_d <= recv_data(7 downto 0) when state = rx_header else ref_q;
sel_vc_d <= sel_vc_enc when state = sel_vc else sel_vc_q;
--the algorithm
chroma_motion_x: for x in 1 downto 0 generate
chroma_motion_y: for y in 1 downto 0 generate
constant ref_0_0_index : integer := x + y*3;
constant ref_0_1_index : integer := x + (y+1)*3;
constant ref_1_0_index : integer := (x+1) + y*3;
constant ref_1_1_index : integer := (x+1) + (y+1) * 3;
constant cr_cb_result_index : integer := x + y*2;
begin
cr_result(cr_cb_result_index) <=
((8-cr_x_frac_q)*(8-cr_y_frac_q)*cr_ref_q(ref_0_0_index) +
cr_x_frac_q*(8-cr_y_frac_q)*cr_ref_q(ref_1_0_index) +
(8-cr_x_frac_q)*cr_y_frac_q*cr_ref_q(ref_0_1_index) +
cr_x_frac_q*cr_y_frac_q*cr_ref_q(ref_1_1_index) +
32
)/64;
cb_result(cr_cb_result_index) <=
((8-cb_x_frac_q)*(8-cb_y_frac_q)*cb_ref_q(ref_0_0_index) +
cb_x_frac_q*(8-cb_y_frac_q)*cb_ref_q(ref_1_0_index) +
(8-cb_x_frac_q)*cb_y_frac_q*cb_ref_q(ref_0_1_index) +
cb_x_frac_q*cb_y_frac_q*cb_ref_q(ref_1_1_index) +
32
)/64;
end generate;
end generate;
--output formatting
result_vect <= std_logic_vector(to_unsigned(cr_result(0), 8)) &
std_logic_vector(to_unsigned(cr_result(1), 8)) &
std_logic_vector(to_unsigned(cr_result(2), 8)) &
std_logic_vector(to_unsigned(cr_result(3), 8)) &
std_logic_vector(to_unsigned(cb_result(0), 8)) &
std_logic_vector(to_unsigned(cb_result(1), 8)) &
std_logic_vector(to_unsigned(cb_result(2), 8)) &
std_logic_vector(to_unsigned(cb_result(3), 8));
resp_header <= x"00000000000000" & ref_q;
--packet generation
send_data <= resp_header when state = wait_tx_header or state = tx_header else result_vect;
dest_addr <= std_logic_vector(to_unsigned(7, addr_width));
set_tail_flit <= '1' when state = wait_tx_data or state = tx_data else '0';
send_flit <= '1' when state = tx_header or state = tx_data else '0';
--rx controls
dequeue <= sel_vc_one_hot when state = dequeue_cb or state = dequeue_cr or state = dequeue_crcb or state = dequeue_header else "00";
select_vc_read <= sel_vc_q;
sel_vc_one_hot <= "01" when sel_vc_q = "0" else "10";
---------------------------------------------------------------------------
--- STATE MACHINE ---------------------------------------------------------
---------------------------------------------------------------------------
process(state, data_in_buffer, is_tail_flit, sel_vc_one_hot, ready_to_send)
begin
next_state <= state;
if state = idle and or_reduce(data_in_buffer) = '1' then
next_state <= sel_vc;
end if;
if state = sel_vc then
next_state <= rx_header;
end if;
if state = rx_header then
next_state <= dequeue_header;
end if;
if state = dequeue_header then
next_state <= wait_rx_cr;
end if;
if state = wait_rx_cr and or_reduce(sel_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx_cr;
end if;
if state = rx_cr then
next_state <= dequeue_cr;
end if;
if state = dequeue_cr then
next_state <= wait_rx_cb;
end if;
if state = wait_rx_cb and or_reduce(sel_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx_cb;
end if;
if state = rx_cb then
next_state <= dequeue_cb;
end if;
if state = dequeue_cb then
next_state <= wait_rx_crcb;
end if;
if state = wait_rx_crcb and or_reduce(sel_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx_crcb;
end if;
if state = rx_crcb then
next_state <= dequeue_crcb;
end if;
if state = dequeue_crcb then
next_state <= wait_tx_header;
end if;
if state = wait_tx_header and ready_to_send = '1' then
next_state <= tx_header;
end if;
if state = tx_header then
next_state <= wait_tx_data;
end if;
if state = wait_tx_data and ready_to_send = '1' then
next_state <= tx_data;
end if;
if state = tx_data then
next_state <= idle;
end if;
end process;
--state_out <= x"00" when state = idle else
-- x"01" when state = sel_vc else
-- x"02" when state = rx_header else
-- x"03" when state = dequeue_header else
-- x"04" when state = wait_rx_cr else
-- x"05" when state = rx_cr else
-- x"06" when state = dequeue_cr else
-- x"07" when state = wait_rx_cb else
-- x"08" when state = rx_cb else
-- x"09" when state = dequeue_cb else
-- x"0A" when state = wait_rx_crcb else
-- x"0B" when state = rx_crcb else
-- x"0C" when state = dequeue_crcb else
-- x"0D" when state = wait_tx_header else
-- x"0E" when state = tx_header else
-- x"0F" when state = wait_tx_data else
-- x"10" when state = tx_data else
-- x"FF";
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Jg7ZSB2xI/J/jQikm8Zlko862zAjpKBGuPSRLj2TaHEWC5rTzr3rFiYHZX6yv0DYk/Y584dxn1Aj
ZJ3fEMF2Eg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
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`protect begin_protected
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`protect begin_protected
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`protect begin_protected
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`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: charrom_package
-- File: charrom_package.vhd
-- Author: Marcus Hellqvist
-- Description: Charrom types and component
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
package charrom_package is
type rom_type is record
addr : std_logic_vector(11 downto 0);
data : std_logic_vector(7 downto 0);
end record;
component charrom
port(
clk : in std_ulogic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end component;
end package;
|
--------------------------------------------------------------------------------
--! @file RBCP_Sender.vhd
--! @brief convert RBCP signal to SRAM read signal
--! @author Takehiro Shiozaki
--! @date 2013-11-05
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RBCP_Sender is
generic(
G_ADDR : std_logic_vector(31 downto 0);
G_LEN : integer;
G_ADDR_WIDTH : integer
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- RBCP interface
RBCP_ACT : in std_logic;
RBCP_ADDR : in std_logic_vector(31 downto 0);
RBCP_RE : in std_logic;
RBCP_RD : out std_logic_vector(7 downto 0);
RBCP_ACK : out std_logic;
-- SRAM interface
ADDR : out std_logic_vector(G_ADDR_WIDTH - 1 downto 0);
RD : in std_logic_vector(7 downto 0)
);
end RBCP_Sender;
architecture RTL of RBCP_Sender is
signal ReadEnable : std_logic;
signal DelayedReadEnable : std_logic_vector(1 downto 0);
signal DelayedRd : std_logic_vector(7 downto 0);
signal DelayedAddr : std_logic_vector(G_ADDR_WIDTH - 1 downto 0);
begin
ReadEnable <= '1' when(RBCP_ACT = '1' and RBCP_RE = '1' and
G_ADDR <= RBCP_ADDR and
RBCP_ADDR <= G_ADDR + G_LEN - 1) else
'0';
process(CLK, RESET)
begin
if(RESET = '1') then
DelayedReadEnable <= (others => '0');
elsif(CLK'event and CLK = '1') then
DelayedReadEnable(0) <= ReadEnable;
DelayedReadEnable(1) <= DelayedReadEnable(0);
end if;
end process;
process(CLK, RESET)
begin
if(RESET = '1') then
DelayedRd <= (others => '0');
elsif(CLK'event and CLK = '1') then
DelayedRd <= RD;
end if;
end process;
RBCP_RD <= DelayedRd;
process(CLK, RESET)
begin
if(RESET = '1') then
RBCP_ACK <= '0';
elsif(CLK'event and CLK = '1') then
RBCP_ACK <= DelayedReadEnable(1);
end if;
end process;
process(CLK, RESET)
begin
if(RESET = '1') then
DelayedAddr <= (others => '0');
elsif(CLK'event and CLK = '1') then
DelayedAddr <= conv_std_logic_vector(conv_integer(RBCP_ADDR - G_ADDR), G_ADDR_WIDTH);
end if;
end process;
ADDR <= DelayedAddr;
end RTL;
|
------------------------------------------------------------
-- School: University of Massachusetts Dartmouth --
-- Department: Computer and Electrical Engineering --
-- Class: ECE 368 Digital Design --
-- Engineer: Daniel Noyes --
-- Massarrah Tannous --
------------------------------------------------------------
--
-- Create Date: Spring 2014
-- Module Name: GenReg_16
-- Project Name: UMD-RISC 24
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- Code was modified from Handout Code: Dr.Fortier(c)
-- 16 General Purpose Registers
--
-- Notes:
-- [Insert Notes]
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Incorporated a memory init [1]
--
-- Additional Comments:
-- [1]: code adaptive from the following blog
-- http://myfpgablog.blogspot.com/2011/12/memory-initialization-methods.html
-- this site pointed to XST user guide
--
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity REG_S16 is
generic(
REG_WIDTH: integer:=4; -- select between 16 different possible registers
DATA_WIDTH: integer:=24
);
port(
CLOCK : in std_logic;
WE : in std_logic;
--RESETN : in std_logic;
--Register A
REG_A_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_A : out std_logic_vector(DATA_WIDTH-1 downto 0);
--Register B
REG_B_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_B : out std_logic_vector(DATA_WIDTH-1 downto 0);
--CHANGE REGISTER
REG_A_IN_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_A_IN : in std_logic_vector(DATA_WIDTH-1 downto 0)
);
end REG_S16;
architecture REG_ARCH of REG_S16 is
type ram_type is array (0 to 2**REG_WIDTH-1) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal ram: ram_type := (
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 0 - 7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000" -- 8 - F
);
signal ADDR_A_REG: std_logic_vector(REG_WIDTH-1 downto 0);
signal ADDR_B_REG: std_logic_vector(REG_WIDTH-1 downto 0);
begin
process(CLOCK,WE)
begin
if (CLOCK'event and CLOCK = '0') then
if (WE = '1') then
ram(to_integer(unsigned(REG_A_IN_ADDR))) <= REG_A_IN;
end if;
ADDR_A_REG <= REG_A_ADDR;
ADDR_B_REG <= REG_B_ADDR;
end if;
end process;
REG_A <= ram(to_integer(unsigned(ADDR_A_REG)));
REG_B <= ram(to_integer(unsigned(ADDR_B_REG)));
end REG_ARCH;
|
-------------------------------------------------------------------------------
-- system_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_stub is
port (
SWs_8Bits_TRI_IO : inout std_logic_vector(7 downto 0);
BTNs_5Bits_TRI_IO : inout std_logic_vector(4 downto 0);
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : in std_logic;
processing_system7_0_PS_CLK : in std_logic;
processing_system7_0_PS_PORB : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
conware_0_M_AXIS_TVALID_pin : out std_logic;
conware_0_M_AXIS_TLAST_pin : out std_logic;
conware_0_M_AXIS_TREADY_pin : out std_logic;
conware_0_M_AXIS_TKEEP_pin : out std_logic_vector(3 downto 0);
conware_0_ACLK_pin : out std_logic;
cownare_ctl_0_in_states_pin : out std_logic_vector(7 downto 0)
);
end system_stub;
architecture STRUCTURE of system_stub is
component system is
port (
SWs_8Bits_TRI_IO : inout std_logic_vector(7 downto 0);
BTNs_5Bits_TRI_IO : inout std_logic_vector(4 downto 0);
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : in std_logic;
processing_system7_0_PS_CLK : in std_logic;
processing_system7_0_PS_PORB : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
conware_0_M_AXIS_TVALID_pin : out std_logic;
conware_0_M_AXIS_TLAST_pin : out std_logic;
conware_0_M_AXIS_TREADY_pin : out std_logic;
conware_0_M_AXIS_TKEEP_pin : out std_logic_vector(3 downto 0);
conware_0_ACLK_pin : out std_logic;
cownare_ctl_0_in_states_pin : out std_logic_vector(7 downto 0)
);
end component;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system : component is "user_black_box";
begin
system_i : system
port map (
SWs_8Bits_TRI_IO => SWs_8Bits_TRI_IO,
BTNs_5Bits_TRI_IO => BTNs_5Bits_TRI_IO,
processing_system7_0_MIO => processing_system7_0_MIO,
processing_system7_0_PS_SRSTB => processing_system7_0_PS_SRSTB,
processing_system7_0_PS_CLK => processing_system7_0_PS_CLK,
processing_system7_0_PS_PORB => processing_system7_0_PS_PORB,
processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP,
conware_0_M_AXIS_TVALID_pin => conware_0_M_AXIS_TVALID_pin,
conware_0_M_AXIS_TLAST_pin => conware_0_M_AXIS_TLAST_pin,
conware_0_M_AXIS_TREADY_pin => conware_0_M_AXIS_TREADY_pin,
conware_0_M_AXIS_TKEEP_pin => conware_0_M_AXIS_TKEEP_pin,
conware_0_ACLK_pin => conware_0_ACLK_pin,
cownare_ctl_0_in_states_pin => cownare_ctl_0_in_states_pin
);
end architecture STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bar_rom is
port(
clk: in std_logic;
addr: in std_logic_vector(5 downto 0);
data: out std_logic_vector(0 to 19)
);
end bar_rom;
architecture content of bar_rom is
type rom_type is array(0 to 63) of std_logic_vector(19 downto 0);
constant BAR: rom_type :=
(
"11111101111111110111",
"11010100000000010001",
"10110010101010101101",
"10011000100010000101",
"10101000000000010011",
"10101100000000000101",
"10101100001000000101",
"10100110001000000101",
"10101110000101001011",
"10100011010001010101",
"10100101010000100101",
"10100100101010100101",
"10001001010100000101",
"10100010001100000101",
"10101000010110100011",
"01001010010010010001",
"10100000101110100111",
"10100000000101010001",
"10100000010010100111",
"10100000000101100001",
"10000010101011000111",
"11100000001011000001",
"10000010010110000111",
"10100010001010000001",
"10100001010100100111",
"10100001010100100001",
"10101010111000000111",
"10100101101000010001",
"10110111000000100111",
"11011110000000100001",
"10110000100001001011",
"10101100000001000101",
"10001100000000010111",
"11101100000000000001",
"10111000000000101011",
"11011000000100000001",
"10110000001000000111",
"11111000000010000001",
"10010000000100000101",
"11011000010001000101",
"10101000100010010011",
"11011100000000000101",
"10101100001000000101",
"10100110001000000101",
"10101110000101001011",
"10100011010001010101",
"10100101010000100101",
"10100100101010100101",
"10001001010100000101",
"10100010001100000101",
"10101000010110100011",
"01001010010010010001",
"10100000101110100111",
"10100000000101010001",
"10100000010010100111",
"10100000000101100001",
"10000010101011000111",
"11100000001011000001",
"10000010010110000111",
"10100010001010000001",
"10100001010100100111",
"11010101011101010101",
"10101101111010101111",
"11111111111111111111"
);
signal addr_reg: std_logic_vector(5 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
addr_reg <= addr;
end if;
end process;
data <= BAR(conv_integer(addr_reg));
end content;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bar_rom is
port(
clk: in std_logic;
addr: in std_logic_vector(5 downto 0);
data: out std_logic_vector(0 to 19)
);
end bar_rom;
architecture content of bar_rom is
type rom_type is array(0 to 63) of std_logic_vector(19 downto 0);
constant BAR: rom_type :=
(
"11111101111111110111",
"11010100000000010001",
"10110010101010101101",
"10011000100010000101",
"10101000000000010011",
"10101100000000000101",
"10101100001000000101",
"10100110001000000101",
"10101110000101001011",
"10100011010001010101",
"10100101010000100101",
"10100100101010100101",
"10001001010100000101",
"10100010001100000101",
"10101000010110100011",
"01001010010010010001",
"10100000101110100111",
"10100000000101010001",
"10100000010010100111",
"10100000000101100001",
"10000010101011000111",
"11100000001011000001",
"10000010010110000111",
"10100010001010000001",
"10100001010100100111",
"10100001010100100001",
"10101010111000000111",
"10100101101000010001",
"10110111000000100111",
"11011110000000100001",
"10110000100001001011",
"10101100000001000101",
"10001100000000010111",
"11101100000000000001",
"10111000000000101011",
"11011000000100000001",
"10110000001000000111",
"11111000000010000001",
"10010000000100000101",
"11011000010001000101",
"10101000100010010011",
"11011100000000000101",
"10101100001000000101",
"10100110001000000101",
"10101110000101001011",
"10100011010001010101",
"10100101010000100101",
"10100100101010100101",
"10001001010100000101",
"10100010001100000101",
"10101000010110100011",
"01001010010010010001",
"10100000101110100111",
"10100000000101010001",
"10100000010010100111",
"10100000000101100001",
"10000010101011000111",
"11100000001011000001",
"10000010010110000111",
"10100010001010000001",
"10100001010100100111",
"11010101011101010101",
"10101101111010101111",
"11111111111111111111"
);
signal addr_reg: std_logic_vector(5 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
addr_reg <= addr;
end if;
end process;
data <= BAR(conv_integer(addr_reg));
end content;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.zpu_top_pkg.all;
use work.wishbone_pkg.all;
use work.zpupkg.all;
use work.zpu_config.all;
entity zpu_wb_bridge is
port ( -- Native ZPU interface
clk : in std_logic;
areset : in std_logic;
mem_req : in std_logic;
mem_we : in std_logic;
mem_ack : out std_logic;
mem_read : out std_logic_vector(wordSize-1 downto 0);
mem_write : in std_logic_vector(wordSize-1 downto 0);
out_mem_addr : in std_logic_vector(maxAddrBitIncIO downto 0);
mem_writeMask : in std_logic_vector(wordBytes-1 downto 0);
-- Wishbone from ZPU
zpu_wb_i : in wishbone_bus_out;
zpu_wb_o : out wishbone_bus_in);
end zpu_wb_bridge;
architecture behave of zpu_wb_bridge is
begin
mem_read <= zpu_wb_i.dat;
mem_ack <= zpu_wb_i.ack;
zpu_wb_o.adr <= out_mem_addr;
zpu_wb_o.dat <= mem_write;
zpu_wb_o.sel <= mem_writeMask;
zpu_wb_o.stb <= mem_req;
zpu_wb_o.cyc <= mem_req;
zpu_wb_o.we <= mem_we;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity test_round is
end test_round;
architecture behavior of test_round is
signal left_plain: std_logic_vector(0 to 31);
signal right_plain: std_logic_vector(0 to 31);
signal subkey: std_logic_vector(0 to 47);
signal left_data_out: std_logic_vector(0 to 31);
signal right_data_out: std_logic_vector(0 to 31);
begin
uut: entity round port map(left_plain,right_plain,subkey,left_data_out,right_data_out);
testprocess: process is
begin
left_plain<="00000000000000000000000000000000";
right_plain<="00000000000000000000000000000000";
subkey<="000000000000000000000000000000000000000000000000";
wait for 10 ns;
end process testprocess;
end architecture behavior;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_gen_v7_3.vhd when simulating
-- the core, blk_mem_gen_v7_3. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_gen_v7_3 IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END blk_mem_gen_v7_3;
ARCHITECTURE blk_mem_gen_v7_3_a OF blk_mem_gen_v7_3 IS
-- synthesis translate_off
COMPONENT wrapped_blk_mem_gen_v7_3
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_blk_mem_gen_v7_3 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 16,
c_addrb_width => 16,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "blk_mem_gen_v7_3.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 43000,
c_read_depth_b => 43000,
c_read_width_a => 10,
c_read_width_b => 10,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 43000,
c_write_depth_b => 43000,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 10,
c_write_width_b => 10,
c_xdevicefamily => "spartan3"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_gen_v7_3
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END blk_mem_gen_v7_3_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_gen_v7_3.vhd when simulating
-- the core, blk_mem_gen_v7_3. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_gen_v7_3 IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END blk_mem_gen_v7_3;
ARCHITECTURE blk_mem_gen_v7_3_a OF blk_mem_gen_v7_3 IS
-- synthesis translate_off
COMPONENT wrapped_blk_mem_gen_v7_3
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_blk_mem_gen_v7_3 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 16,
c_addrb_width => 16,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "blk_mem_gen_v7_3.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 43000,
c_read_depth_b => 43000,
c_read_width_a => 10,
c_read_width_b => 10,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 43000,
c_write_depth_b => 43000,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 10,
c_write_width_b => 10,
c_xdevicefamily => "spartan3"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_gen_v7_3
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END blk_mem_gen_v7_3_a;
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_qspi_xip_if.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_qspi_xip_if.vhd
-- Version: v3.0
-- Description: This is the top-level design file for the AXI Quad SPI core
-- in XIP mode.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
-- use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
library lib_fifo_v1_0;
use lib_fifo_v1_0.async_fifo_fg;
library lib_cdc_v1_0;
use lib_cdc_v1_0.cdc_sync;
library axi_quad_spi_v3_2;
use axi_quad_spi_v3_2.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity axi_qspi_xip_if is
generic(
-- General Parameters
C_FAMILY : string := "virtex7";
Async_Clk : integer := 0;
C_SUB_FAMILY : string := "virtex7";
-------------------------
C_SPI_MEM_ADDR_BITS : integer ; -- default is 24 bit, options are 24 or 32 bits
-------------------------
-- C_AXI4_CLK_PS : integer := 10000;--AXI clock period
-- C_EXT_SPI_CLK_PS : integer := 10000;--ext clock period
C_XIP_FIFO_DEPTH : integer := 64;-- Fixed value for XIP mode.
C_SCK_RATIO : integer := 16;--default in legacy mode
C_NUM_SS_BITS : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS : integer := 8; -- Fixed 8 bit for XIP mode
-------------------------
C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating
-- Standard, Dual or Quad mode
-- in Ports as well as internal
-- functionality
C_USE_STARTUP : integer range 0 to 1 := 1; --
C_SPI_MEMORY : integer range 0 to 3 := 1; -- 0 - mixed mode,
-- 1 - winbond,
-- 2 - numonyx
-- 3 - spansion
-- used to differentiate
-- internal look up table
-- for commands.
-------------------------
-- AXI4 Lite Interface Parameters
--*C_S_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer range 7 to 7 := 7;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
-------------------------
--*C_BASEADDR : std_logic_vector := x"FFFFFFFF";
--*C_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
-- AXI4 Full Interface Parameters
--*C_S_AXI4_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ADDR_WIDTH : integer ;-- range 32 to 32 := 32;
C_S_AXI4_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH : integer range 1 to 16 := 4;
-------------------------
--*C_AXI4_BASEADDR : std_logic_vector := x"FFFFFFFF";
--*C_AXI4_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
C_XIP_FULL_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_0100_0000", -- IP user0 base address
X"0000_0000_01FF_FFFF" -- IP user0 high address
);
C_XIP_FULL_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
2,
1 -- User0 CE Number
)
);
port(
-- external async clock for SPI interface logic
EXT_SPI_CLK : in std_logic;
S_AXI4_ACLK : in std_logic;
Rst_to_spi : in std_logic;
S_AXI4_ARESET : in std_logic;
-------------------------------
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
------------------------------------
-- AXI Write Address Channel Signals
------------------------------------
S_AXI4_AWID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);
S_AXI4_AWLEN : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK : in std_logic; -- not supported in design
S_AXI4_AWCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID : in std_logic;
S_AXI4_AWREADY : out std_logic;
---------------------------------------
-- AXI4 Full Write Data Channel Signals
---------------------------------------
S_AXI4_WDATA : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST : in std_logic;
S_AXI4_WVALID : in std_logic;
S_AXI4_WREADY : out std_logic;
-------------------------------------------
-- AXI4 Full Write Response Channel Signals
-------------------------------------------
S_AXI4_BID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP : out std_logic_vector(1 downto 0);
S_AXI4_BVALID : out std_logic;
S_AXI4_BREADY : in std_logic;
-----------------------------------
-- AXI Read Address Channel Signals
-----------------------------------
S_AXI4_ARID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);
S_AXI4_ARLEN : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK : in std_logic; -- not supported in design
S_AXI4_ARCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID : in std_logic;
S_AXI4_ARREADY : out std_logic;
--------------------------------
-- AXI Read Data Channel Signals
--------------------------------
S_AXI4_RID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP : out std_logic_vector(1 downto 0);
S_AXI4_RLAST : out std_logic;
S_AXI4_RVALID : out std_logic;
S_AXI4_RREADY : in std_logic;
--------------------------------
XIPSR_CPHA_CPOL_ERR : in std_logic;
TO_XIPSR_trans_error : out std_logic;
--------------------------------
TO_XIPSR_mst_modf_err : out std_logic;
TO_XIPSR_axi_rx_full : out std_logic;
TO_XIPSR_axi_rx_empty : out std_logic;
XIPCR_1_CPOL : in std_logic;
XIPCR_0_CPHA : in std_logic;
-------------------------------
--*SPI port interface * --
-------------------------------
IO0_I : in std_logic; -- MOSI signal in standard SPI
IO0_O : out std_logic;
IO0_T : out std_logic;
-------------------------------
IO1_I : in std_logic; -- MISO signal in standard SPI
IO1_O : out std_logic;
IO1_T : out std_logic;
-----------------
-- quad mode pins
-----------------
IO2_I : in std_logic;
IO2_O : out std_logic;
IO2_T : out std_logic;
---------------
IO3_I : in std_logic;
IO3_O : out std_logic;
IO3_T : out std_logic;
---------------------------------
-- common pins
----------------
SPISEL : in std_logic;
-----
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
-----
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic
---------------------------------
);
end entity axi_qspi_xip_if;
--------------------------------------------------------------------------------
architecture imp of axi_qspi_xip_if is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
constant NEW_LOGIC : integer := 0; -- 3/29/2013
constant ACTIVE_LOW_RESET : std_logic := '0';
constant CMD_BITS_LENGTH : integer:= 8; -- 3/29/2013
-----
-- code coverage -- function assign_addr_bits (logic_info : integer) return integer is
-- code coverage -- variable addr_width_24 : integer:= 24;
-- code coverage -- variable addr_width_32 : integer:= 32;
-- code coverage -- begin
-- code coverage -- if logic_info = 0 then -- old logic for 24 bit addressing
-- code coverage -- return addr_width_24;
-- code coverage -- else
-- code coverage -- return addr_width_32;
-- code coverage -- end if;
-- code coverage -- end function assign_addr_bits;
signal nm_wr_en_CMD : std_logic_vector(7 downto 0);
signal nm_4byte_addr_en_CMD : std_logic_vector(7 downto 0);
type NM_WR_EN_STATE_TYPE is
(NM_WR_EN_IDLE, -- decode command can be combined here later
NM_WR_EN,
NM_WR_EN_DONE
);
signal nm_wr_en_cntrl_ps : NM_WR_EN_STATE_TYPE;
signal nm_wr_en_cntrl_ns : NM_WR_EN_STATE_TYPE;
signal wr_en_under_process : std_logic;
signal wr_en_under_process_d1 : std_logic;
signal load_wr_en, wr_en_done_reg : std_logic;
signal wr_en_done_d1, wr_en_done_d2 : std_logic;
signal wr_en_done : std_logic;
signal data_loaded, cmd_sent : std_logic;
type NM_32_BIT_WR_EN_STATE_TYPE is
(NM_32_BIT_IDLE, -- decode command can be combined here later
NM_32_BIT_EN,
NM_32_BIT_EN_DONE
);
signal nm_sm_4_byte_addr_ps : NM_32_BIT_WR_EN_STATE_TYPE;
signal nm_sm_4_byte_addr_ns : NM_32_BIT_WR_EN_STATE_TYPE;
signal four_byte_en_under_process : std_logic;
signal four_byte_addr_under_process_d1 : std_logic;
signal load_4_byte_addr_en, four_byte_en_done, four_byte_en_done_reg : std_logic;
-----
-- constant declaration
constant FAST_READ : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="00001011"; -- 0B
constant FAST_READ_DUAL_IO : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="00111011"; -- 3B
constant FAST_READ_QUAD_IO : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="10111011"; -- BB
constant C_RD_COUNT_WIDTH_INT : integer := clog2(C_XIP_FIFO_DEPTH);
constant C_WR_COUNT_WIDTH_INT : integer := clog2(C_XIP_FIFO_DEPTH);
constant RX_FIFO_CNTR_WIDTH : integer := clog2(C_XIP_FIFO_DEPTH);
constant XIP_MIN_SIZE : std_logic_vector(31 downto 0):= X"00ffffff";-- 24 bit address
--constant XIP_ADDR_BITS : integer := 24;
constant XIP_ADDR_BITS : integer := C_SPI_MEM_ADDR_BITS; -- assign_addr_bits(NEW_LOGIC);
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
constant ACTIVE_HIGH_RESET : std_logic := '1';
constant ZERO_RX_FIFO_CNT : std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
signal rx_fifo_count: std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0);
constant ALL_1 : std_logic_vector(0 to RX_FIFO_CNTR_WIDTH-1)
:= (others => '0');
signal updown_cnt_en_rx,down_cnt_en_rx : std_logic;
type AXI_IF_STATE_TYPE is
(
IDLE, -- decode command can be combined here later
RD_BURST
);
signal xip_sm_ps: AXI_IF_STATE_TYPE;
signal xip_sm_ns: AXI_IF_STATE_TYPE;
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
CMD_SEND,
HPM_DUMMY,
ADDR_SEND,
TEMP_ADDR_SEND,
--DUMMY_SEND,
DATA_SEND,
TEMP_DATA_SEND,
DATA_RECEIVE,
TEMP_DATA_RECEIVE
);
signal qspi_cntrl_ns : STATE_TYPE;
signal qspi_cntrl_ps : STATE_TYPE;
type WB_STATE_TYPE is
(WB_IDLE, -- decode command can be combined here later
WB_WR_HPM,
WB_DONE
);
signal wb_cntrl_ns : WB_STATE_TYPE;
signal wb_cntrl_ps : WB_STATE_TYPE;
signal valid_decode : std_logic;
signal s_axi_arready_cmb : std_logic;
signal temp_i : std_logic;
signal SS_frm_axi : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal SS_frm_axi_int : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal SS_frm_axi_reg : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst : std_logic; --_vector(1 downto 0);
signal axi_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal size_length : std_logic_vector(1 downto 0);
signal S_AXI4_RID_reg : std_logic_vector(C_S_AXI4_ID_WIDTH-1 downto 0);
signal XIP_ADDR : std_logic_vector(XIP_ADDR_BITS-1 downto 0);
signal one_byte_transfer : std_logic;
signal two_byte_transfer : std_logic;
signal four_byte_transfer: std_logic;
signal dtr_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal write_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal s_axi_rvalid_i : std_logic;
signal dtr_cntr_empty : std_logic;
signal last_bt_one_data_cmb : std_logic;
signal last_data_cmb : std_logic;
signal last_data_acked : std_logic;
signal last_data : std_logic;
signal rd_error_int : std_logic;
signal Data_From_Rx_FIFO : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal S_AXI4_RRESP_i : std_logic_vector(1 downto 0);
signal S_AXI4_RDATA_i : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
-- signal s_axi_rvalid_i : std_logic;
signal s_axi_rvalid_cmb : std_logic;
signal xip_pr_state_idle : std_logic;
signal pr_state_idle : std_logic;
signal rready_i : std_logic;
signal wrap_around_to_axi_clk : std_logic;
signal spiXfer_done_to_axi_1 : std_logic;
signal Rx_FIFO_Empty : std_logic;
signal IO0_T_cntrl_axi : std_logic;
signal IO1_T_cntrl_axi : std_logic;
signal IO2_T_cntrl_axi : std_logic;
signal IO3_T_cntrl_axi : std_logic;
signal SCK_T_cntrl_axi : std_logic;
signal load_axi_data_frm_axi : std_logic;
--signal Transmit_addr_int : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_addr_int : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- 3/30/2013
signal Rx_FIFO_rd_ack : std_logic;
signal Data_To_Rx_FIFO : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal store_date_in_drr_fifo : std_logic;
--signal Rx_FIFO_Empty : std_logic;
signal Rx_FIFO_almost_Full : std_logic;
signal Rx_FIFO_almost_Empty : std_logic;
--signal pr_state_idle : std_logic;
signal spiXfer_done_frm_spi_clk: std_logic;
signal mst_modf_err_frm_spi_clk: std_logic;
signal wrap_around_frm_spi_clk : std_logic;
signal one_byte_xfer_frm_axi_clk : std_logic;
signal two_byte_xfer_frm_axi_clk : std_logic;
signal four_byte_xfer_frm_axi_clk : std_logic;
signal load_axi_data_frm_axi_clk : std_logic;
--signal Transmit_Addr_frm_axi_clk : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_Addr_frm_axi_clk : std_logic_vector(XIP_ADDR_BITS-1 downto 0);-- 3/30/2013
signal CPOL_frm_axi_clk : std_logic;
signal CPHA_frm_axi_clk : std_logic;
signal SS_frm_axi_clk : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst_frm_axi_clk : std_logic; -- _vector(1 downto 0);
signal type_of_burst_frm_axi : std_logic; -- _vector(1 downto 0);
signal axi_length_frm_axi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal dtr_length_frm_axi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal load_axi_data_to_spi_clk : std_logic;
--signal Transmit_Addr_to_spi_clk : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_Addr_to_spi_clk : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- 3/30/2013
signal last_7_addr_bits : std_logic_vector(7 downto 0);
signal CPOL_to_spi_clk : std_logic;
signal CPHA_to_spi_clk : std_logic;
signal SS_to_spi_clk : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst_to_spi : std_logic;
signal type_of_burst_to_spi_clk : std_logic;
signal axi_length_to_spi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal dtr_length_to_spi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
--signal wrap_around_to_axi_clk : std_logic;
signal spi_addr : std_logic_vector(31 downto 0);
signal spi_addr_i : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_int : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_wrap : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_wrap_1 : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
--signal Transmit_Addr_to_spi_clk : std_logic_vector(23 downto 0);
signal load_wrap_addr : std_logic;
signal wrap_two : std_logic;
signal wrap_four : std_logic;
signal wrap_eight : std_logic;
signal wrap_sixteen : std_logic;
signal SPIXfer_done_int : std_logic;
signal size_length_cntr : std_logic_vector(1 downto 0);
signal size_length_cntr_fixed : std_logic_vector(1 downto 0);
signal length_cntr : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal cmd_addr_sent : std_logic;
signal SR_5_Tx_Empty, SR_5_Tx_Empty_d1, SR_5_Tx_Empty_d2 : std_logic;
signal wrap_around : std_logic;
signal rst_wrap_around : std_logic;
--signal pr_state_idle : std_logic;
signal one_byte_xfer_to_spi_clk : std_logic;
signal two_byte_xfer_to_spi_clk : std_logic;
signal four_byte_xfer_to_spi_clk : std_logic;
--signal store_date_in_drr_fifo : std_logic;
signal Data_To_Rx_FIFO_int : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal receive_Data_int : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
--signal Data_To_Rx_FIFO : std_logic_vector(7 downto 0);
--signal load_axi_data_to_spi_clk : std_logic;
signal Tx_Data_d1 : std_logic_vector(31 downto 0);
signal Tx_Data_d2 : std_logic_vector(39 downto 0);
signal internal_count : std_logic_vector(3 downto 0);
signal SPI_cmd : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal Transmit_Data : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal Data_Dir : std_logic;
signal Data_Mode_1 : std_logic;
signal Data_Mode_0 : std_logic;
signal Data_Phase : std_logic;
signal Quad_Phase : std_logic;
signal Addr_Mode_1 : std_logic;
signal Addr_Mode_0 : std_logic;
signal Addr_Bit : std_logic;
signal Addr_Phase : std_logic;
signal CMD_Mode_1 : std_logic;
signal CMD_Mode_0 : std_logic;
--signal cmd_addr_cntr : std_logic_vector(2 downto 0);
--signal cmd_addr_sent : std_logic;
signal transfer_start : std_logic;
signal last_bt_one_data : std_logic;
--signal SPIXfer_done_int : std_logic;
signal actual_SPIXfer_done_int : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
--signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
--signal SPIXfer_done_int : std_logic;
signal mode_1 : std_logic;
signal mode_0 : std_logic;
signal Count : std_logic_vector(COUNT_WIDTH downto 0);
--signal receive_Data_int : std_logic_vector(7 downto 0);
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal sck_o_int : std_logic;
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_rising_edge : std_logic;
signal Shift_Reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal Serial_Dout_0 : std_logic;
signal Serial_Dout_1 : std_logic;
signal Serial_Dout_2 : std_logic;
signal Serial_Dout_3 : std_logic;
signal pr_state_cmd_ph : std_logic;
--signal qspi_cntrl_ps : std_logic;
signal stop_clock : std_logic;
signal stop_clock_reg : std_logic;
signal pr_state_data_receive : std_logic;
signal pr_state_non_idle : std_logic;
--signal pr_state_idle : std_logic;
--signal pr_state_cmd_ph : std_logic;
--signal SPIXfer_done_int_pulse : std_logic;
signal no_slave_selected : std_logic;
--signal rst_wrap_around : std_logic;
signal IO0_T_control : std_logic;
signal IO1_T_control : std_logic;
signal IO2_T_control : std_logic;
signal IO3_T_control : std_logic;
signal addr_cnt : std_logic_vector(2 downto 0);
signal addr_cnt1 : std_logic_vector(1 downto 0);
signal pr_state_addr_ph : std_logic;
signal SS_tri_state_en_control : std_logic;
signal SCK_tri_state_en_control : std_logic;
signal IO0_tri_state_en_control : std_logic;
signal IO1_tri_state_en_control : std_logic;
signal IO2_tri_state_en_control : std_logic;
signal IO3_tri_state_en_control : std_logic;
signal IO0_T_cntrl_spi : std_logic;
signal MODF_strobe_int : std_logic;
signal SPISEL_sync : std_logic;
signal spisel_d1 : std_logic;
signal MODF_strobe : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal sck_o_in : std_logic;
--signal SCK_O_reg : std_logic;
signal slave_mode : std_logic;
--signal pr_state_non_idle : std_logic;
signal mst_modf_err_to_axi_clk : std_logic;
signal mst_modf_err_to_axi4_clk : std_logic;
signal Rx_FIFO_Full_to_axi4_clk : std_logic;
signal Rx_FIFO_Full_to_axi_clk : std_logic;
signal Rx_FIFO_Full : std_logic;
signal one_byte_xfer : std_logic;
signal two_byte_xfer : std_logic;
signal four_byte_xfer : std_logic;
signal XIP_trans_error : std_logic;
signal XIP_trans_cdc_to_error : std_logic;
signal load_cmd : std_logic;
signal load_cmd_to_spi_clk : std_logic;
--signal load_axi_data_frm_axi_clk : std_logic;
signal load_cmd_frm_axi_clk : std_logic;
signal axi_len_two : std_logic;
signal axi_len_four : std_logic;
signal axi_len_eight : std_logic;
signal axi_len_sixteen : std_logic;
signal reset_inversion : std_logic;
signal new_tr : std_logic;
signal SR_5_Tx_Empty_int : std_logic;
signal only_last_count : std_logic;
signal rx_fifo_cntr_rst, rx_fifo_not_empty : std_logic;
signal store_date_in_drr_fifo_d1 : std_logic;
signal store_date_in_drr_fifo_d2 : std_logic;
signal store_date_in_drr_fifo_d3 : std_logic;
signal xip_ns_state_idle : std_logic;
signal wrap_around_d1 : std_logic;
signal wrap_ack : std_logic;
signal wrap_ack_1 : std_logic;
signal wrap_around_d2 : std_logic;
signal wrap_around_d3 : std_logic;
signal start_after_wrap : std_logic;
signal store_last_b4_wrap : std_logic;
signal wrp_addr_len_16_siz_32 : std_logic;
signal wrp_addr_len_8_siz_32 : std_logic;
signal wrp_addr_len_4_siz_32 : std_logic;
signal wrp_addr_len_2_siz_32 : std_logic;
signal wrp_addr_len_16_siz_16 : std_logic;
signal wrp_addr_len_8_siz_16 : std_logic;
signal wrp_addr_len_4_siz_16 : std_logic;
signal wrp_addr_len_2_siz_16, start_after_wrap_d1 : std_logic;
signal SS_O_1 : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal WB_wr_en_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_sr_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_sr_DATA : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_hpm_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal wb_wr_en_done : std_logic;
signal wb_wr_sr_done : std_logic;
signal wb_wr_sr_data_done : std_logic;
signal wb_wr_hpm_done : std_logic;
signal load_wr_en_cmd : std_logic;
signal load_wr_sr_cmd : std_logic;
signal load_wr_sr_d0 : std_logic;
signal load_wr_sr_d1 : std_logic;
signal load_rd_sr : std_logic;
signal load_wr_hpm : std_logic;
signal wb_hpm_done : std_logic;
signal wb_hpm_done_reg : std_logic;
signal dis_sr_5_empty_reg : std_logic;
signal dis_sr_5_empty : std_logic;
signal wb_hpm_done_frm_spi,wb_hpm_done_frm_spi_clk,wb_hpm_done_to_axi : std_logic;
signal hpm_under_process : std_logic;
signal hpm_under_process_d1 : std_logic;
signal s_axi_rlast_cmb : std_logic;
signal store_date_in_drr_fifo_en : std_logic;
signal XIP_trans_error_cmb, XIP_trans_error_d1, XIP_trans_error_d2, XIP_trans_error_d3 : std_logic;
signal axi4_tr_over_d1, axi4_tr_over_d2 : std_logic;
signal arready_d1, arready_d2, arready_d3 : std_logic;
signal XIPSR_CPHA_CPOL_ERR_d1, XIPSR_CPHA_CPOL_ERR_d2 : std_logic;
signal axi4_tr_over_d3 : std_logic;
signal last_data_acked_int_2 : std_logic;
signal XIP_trans_error_int_2 : std_logic;
signal s_axi_arready_int_2 : std_logic;
-- signal XIP_trans_error_cmb : std_logic;
-- signal axi4_tr_over_d1, axi4_tr_over_d2 : std_logic;
-- signal arready_d1, arready_d2, arready_d3 : std_logic;
-- signal XIPSR_CPHA_CPOL_ERR_d1, XIPSR_CPHA_CPOL_ERR_d2 : std_logic;
-- signal axi4_tr_over_d3 : std_logic;
-- signal last_data_acked_int_2 : std_logic;
-- signal XIP_trans_error_int_2 : std_logic;
-- signal s_axi_arready_int_2 : std_logic;
signal Rx_FIFO_Empty_d1, Rx_FIFO_Empty_d2 : std_logic;
signal XIPSR_CPHA_CPOL_ERR_4 : std_logic;
--signal mst_modf_err_to_axi4clk: std_logic;
signal xip_done : std_logic;
signal en_xip : std_logic;
signal new_tr_at_axi4 : std_logic;
signal axi4_tr_over : std_logic;
--attribute ASYNC_REG : string;
--attribute ASYNC_REG of XIP_TRANS_ERROR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of Rx_FIFO_Empty_AXI42AXI : label is "TRUE";
--attribute ASYNC_REG of CPHA_CPOL_ERR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of ARREADY_PULSE_AXI42AXI_CDC: label is "TRUE";
--attribute ASYNC_REG of AXI4_TR_OVER_AXI42AXI_CDC : label is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
constant MTBF_STAGES_AXI2AXILITE : integer range 0 to 6 := 4 ;
-----
begin
-----
S_AXI4_WREADY <= '0';
S_AXI4_BID <= (others => '0');
S_AXI4_BRESP <= (others => '0');
S_AXI4_BVALID <= '0';
S_AXI4_AWREADY<= '0';
valid_decode <= S_AXI4_ARVALID and xip_pr_state_idle;
reset_inversion <= not S_AXI4_ARESET;
-- address decoder and CS generation in AXI interface
I_DECODER : entity axi_quad_spi_v3_2.qspi_address_decoder
generic map
(
C_BUS_AWIDTH => XIP_ADDR_BITS, -- C_S_AXI4_ADDR_WIDTH,
C_S_AXI4_MIN_SIZE => XIP_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_XIP_FULL_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_XIP_FULL_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI4_ACLK, -- in std_logic;
Bus_rst => reset_inversion, -- in std_logic;
Address_In_Erly => S_AXI4_ARADDR(XIP_ADDR_BITS-1 downto 0), -- in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly => s_axi_arready_cmb, -- in std_logic;
Bus_RNW => valid_decode, -- in std_logic;
Bus_RNW_Erly => valid_decode, -- in std_logic;
CS_CE_ld_enable => s_axi_arready_cmb, -- in std_logic;
Clear_CS_CE_Reg => temp_i, -- in std_logic;
RW_CE_ld_enable => s_axi_arready_cmb, -- in std_logic;
CS_for_gaps => open, -- out std_logic;
-- Decode output signals
CS_Out => SS_frm_axi,
RdCE_Out => open,
WrCE_Out => open
);
-------------------------------------------------
STORE_AXI_ARBURST_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then -- S_AXI4_ARESET is already inverted and made active high
type_of_burst <= '0';-- "01"; -- default is INCR burst
elsif(s_axi_arready_cmb = '1')then
type_of_burst <= S_AXI4_ARBURST(1) ;
end if;
end if;
end process STORE_AXI_ARBURST_P;
-----------------------
S_AXI4_ARREADY_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_ARREADY <= '0';
else
S_AXI4_ARREADY <= s_axi_arready_cmb;
end if;
end if;
end process S_AXI4_ARREADY_P;
-- S_AXI4_ARREADY <= s_axi_arready_cmb;
STORE_AXI_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
axi_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
axi_length <= S_AXI4_ARLEN;
end if;
end if;
end process STORE_AXI_LENGTH_P;
---------------------------------------------------
STORE_AXI_SIZE_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
size_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
size_length <= S_AXI4_ARSIZE(1 downto 0);
end if;
end if;
end process STORE_AXI_SIZE_P;
-------------------------------------------------------------------------------
REG_RID_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_RID_reg <= (others=> '0');
elsif(s_axi_arready_cmb = '1')then
S_AXI4_RID_reg <= S_AXI4_ARID ;
end if;
end if;
end process REG_RID_P;
----------------------
S_AXI4_RID <= S_AXI4_RID_reg;
-----------------------------
OLD_LOGIC_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
STORE_AXI_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
XIP_ADDR <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
XIP_ADDR <= S_AXI4_ARADDR(23 downto 0);-- support for 24 bit address
end if;
end if;
end process STORE_AXI_ADDR_P;
end generate OLD_LOGIC_GEN;
---------------------------
NEW_LOGIC_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
STORE_AXI_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
XIP_ADDR <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
XIP_ADDR <= S_AXI4_ARADDR(C_SPI_MEM_ADDR_BITS-1 downto 0);-- support for 24 or 32 bit address
end if;
end if;
end process STORE_AXI_ADDR_P;
end generate NEW_LOGIC_GEN;
---------------------------
------------------------------------------------------------------------------
ONE_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
one_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
one_byte_xfer <= not(or_reduce(S_AXI4_ARSIZE(1 downto 0)));
end if;
end if;
end process ONE_BYTE_XFER_P;
TWO_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
two_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
two_byte_xfer <= S_AXI4_ARSIZE(0);
end if;
end if;
end process TWO_BYTE_XFER_P;
FOUR_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
four_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
four_byte_xfer <= S_AXI4_ARSIZE(1);
end if;
end if;
end process FOUR_BYTE_XFER_P;
---------------------------------------------------------------------------------
STORE_DTR_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
dtr_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
dtr_length <= S_AXI4_ARLEN;-- + "00000001";
-- elsif(S_AXI4_RREADY = '1' and s_axi_rvalid_i = '1') then
elsif(Rx_FIFO_rd_ack = '1') then
dtr_length <= dtr_length - '1';
end if;
end if;
end process STORE_DTR_LENGTH_P;
-----------------------------------------------------
STORE_WRITE_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then -- if(xip_sm_ps = IDLE)then
write_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
write_length <= S_AXI4_ARLEN + "00000001";
elsif(spiXfer_done_to_axi_1 = '1')then
write_length <= write_length - '1';
end if;
end if;
end process STORE_WRITE_LENGTH_P;
-----------------------------------------------------
--dtr_cntr_empty <= or_Reduce(dtr_length);
-----------------------------------------------------
last_bt_one_data_cmb <= not(or_reduce(dtr_length(C_NUM_TRANSFER_BITS-1 downto 1))) and
dtr_length(0) and
S_AXI4_RREADY;
last_data_cmb <= not(or_reduce(dtr_length(C_NUM_TRANSFER_BITS-1 downto 0)));
RX_FIFO_FULL_CNTR_I : entity axi_quad_spi_v3_2.counter_f
generic map(
C_NUM_BITS => RX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => S_AXI4_ACLK, -- in
Rst => S_AXI4_ARESET, -- '0', -- in
-- coverage off
Load_In => ALL_1, -- in
-- coverage on
Count_Enable => updown_cnt_en_rx, -- in
----------------
Count_Load => s_axi_arready_cmb,-- in
----------------
Count_Down => down_cnt_en_rx, -- in
Count_Out => rx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
updown_cnt_en_rx <= s_axi_arready_cmb or
spiXfer_done_to_axi_1 or
(down_cnt_en_rx); -- this is to make the counter enable for decreasing.
down_cnt_en_rx <= S_AXI4_RREADY and s_axi_rvalid_i;
only_last_count <= not(or_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto 0))) and
last_data_cmb;
rx_fifo_not_empty <= or_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto 0));
LAST_DATA_ACKED_P: process (S_AXI4_ACLK) is
-----------------
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
last_data_acked <= '0';
else
if(S_AXI4_RREADY = '1' and last_data_acked = '1') then -- AXI Ready and Rlast active
last_data_acked <= '0';
elsif(S_AXI4_RREADY = '0' and last_data_acked = '1')then-- AXI not Ready and Rlast active, then hold the RLAST signal
last_data_acked <= '1';
else
last_data_acked <=(last_data_cmb and
Rx_FIFO_rd_ack);
end if;
end if;
end if;
end process LAST_DATA_ACKED_P;
------------------------------
S_AXI4_RLAST <= last_data_acked;
--------------------------------
S_AXI4_RDATA_RESP_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_RRESP_i <= (others => '0');
S_AXI4_RDATA_i <= (others => '0');
else-- if(S_AXI4_RREADY = '1' )then -- and (Rx_FIFO_Empty = '0')then
S_AXI4_RRESP_i <= --(rd_error_int or mst_modf_err_to_axi_clk) & '0';
(mst_modf_err_to_axi4_clk) & '0';
S_AXI4_RDATA_i <= Data_From_Rx_FIFO;
end if;
end if;
end process S_AXI4_RDATA_RESP_P;
--------------------------------
S_AXI4_RRESP <= S_AXI4_RRESP_i;
S_AXI4_RDATA <= S_AXI4_RDATA_i;
-------------------------------
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
s_axi_rvalid_i <= '0';
elsif(S_AXI4_RREADY = '1') then -- and (s_axi_rvalid_i = '1') then -- AXI Ready and Rlast active
s_axi_rvalid_i <= Rx_FIFO_rd_ack; -- '0';
elsif(S_AXI4_RREADY = '0') and (s_axi_rvalid_i = '1') then
s_axi_rvalid_i <= s_axi_rvalid_i;
else
s_axi_rvalid_i <= Rx_FIFO_rd_ack;
end if;
end if;
end process S_AXI_RVALID_I_P;
-----------------------------
S_AXI4_RVALID <= s_axi_rvalid_i;
-- -----------------------------
xip_pr_state_idle <= '1' when xip_sm_ps = IDLE else '0';
xip_ns_state_idle <= '1' when xip_sm_ns = IDLE else '0';
rready_i <= S_AXI4_RREADY and not last_data_cmb;
------------------------------------------------------------------------------
XIP_trans_error_cmb <= not(or_reduce(S_AXI4_ARBURST)) and (S_AXI4_ARVALID);
-- XIP_TR_ERROR_PULSE_STRETCH_1: single pulse for AXI4 transaction error
LOGIC_GENERATION_FDR : if (Async_Clk = 0) generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of XIP_TRANS_ERROR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of Rx_FIFO_Empty_AXI42AXI : label is "TRUE";
attribute ASYNC_REG of CPHA_CPOL_ERR_AXI2AXI4_CDC : label is "TRUE";
attribute ASYNC_REG of ARREADY_PULSE_AXI42AXI_CDC: label is "TRUE";
attribute ASYNC_REG of AXI4_TR_OVER_AXI42AXI_CDC : label is "TRUE";
begin
XIP_TR_ERROR_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
XIP_trans_error_int_2 <= '0';
else
XIP_trans_error_int_2 <= XIP_trans_error_cmb xor
XIP_trans_error_int_2;
end if;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1;
-------------------------------------
XIP_TRANS_ERROR_AXI2AXI4_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d1,
C => S_AXI_ACLK,
D => XIP_trans_error_int_2,
R => S_AXI_ARESETN
);
XIP_TRANS_ERROR_AXI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d2,
C => S_AXI_ACLK,
D => XIP_trans_error_d1,
R => S_AXI_ARESETN
);
XIP_TRANS_ERROR_AXI2AXI4_2: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d3,
C => S_AXI_ACLK,
D => XIP_trans_error_d2,
R => S_AXI_ARESETN
);
XIP_trans_error <= XIP_trans_error_d2 xor XIP_trans_error_d3;
------------------------------------------------------------------------------
--mst_modf_err_to_axi <= mst_modf_err_d2;
-- TO XIP Status Register
-- LAST_DATA_PULSE_STRETCH_1: single pulse for AXI4 transaction completion
LAST_DATA_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
last_data_acked_int_2 <= '0';
else
last_data_acked_int_2 <= last_data_acked xor
last_data_acked_int_2;
end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1;
-------------------------------------
AXI4_TR_OVER_AXI42AXI_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d1,
C => S_AXI_ACLK,
D => last_data_acked_int_2,
R => S_AXI_ARESETN
);
AXI4_TR_OVER_AXI42AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d2,
C => S_AXI_ACLK,
D => axi4_tr_over_d1,
R => S_AXI_ARESETN
);
AXI4_TR_OVER_AXI42AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d3,
C => S_AXI_ACLK,
D => axi4_tr_over_d2,
R => S_AXI_ARESETN
);
axi4_tr_over <= axi4_tr_over_d2 xor axi4_tr_over_d3;
-------------------------------------------------------------
-- ARREADY_PULSE_STRETCH_1: single pulse for AXI4 transaction acceptance
ARREADY_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
s_axi_arready_int_2 <= '0';
else
s_axi_arready_int_2 <= s_axi_arready_cmb xor
s_axi_arready_int_2;
end if;
end if;
end process ARREADY_PULSE_STRETCH_1;
-------------------------------------
ARREADY_PULSE_AXI42AXI_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => arready_d1,
C => S_AXI_ACLK,
D => s_axi_arready_int_2,
R => S_AXI_ARESETN
);
ARREADY_PULSE_AXI42AXI_2: component FDR
generic map(INIT => '1'
)port map (
Q => arready_d2,
C => S_AXI_ACLK,
D => arready_d1,
R => S_AXI_ARESETN
);
ARREADY_PULSE_AXI42AXI_3: component FDR -- 2/21/2012
generic map(INIT => '1'
)port map (
Q => arready_d3,
C => S_AXI_ACLK,
D => arready_d2,
R => S_AXI_ARESETN
);
new_tr_at_axi4 <= arready_d2 xor arready_d3;
-------------------------------------
------------------------------------------------------------------------------
-- CPHA_CPOL_ERR_AXI2AXI4_CDC: CDC flop at cross clock boundary
CPHA_CPOL_ERR_AXI2AXI4_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => XIPSR_CPHA_CPOL_ERR_d1,
C => S_AXI4_ACLK,
D => XIPSR_CPHA_CPOL_ERR,
R => S_AXI4_ARESET
);
CPHA_CPOL_ERR_AXI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => XIPSR_CPHA_CPOL_ERR_d2,
C => S_AXI4_ACLK,
D => XIPSR_CPHA_CPOL_ERR_d1,
R => S_AXI4_ARESET
);
XIPSR_CPHA_CPOL_ERR_4 <= XIPSR_CPHA_CPOL_ERR_d2;
-------------------------------------------------------------------------------
end generate LOGIC_GENERATION_FDR;
LOGIC_GENERATION_CDC : if (Async_Clk = 1) generate
--=================================================================================
XIP_TR_ERROR_PULSE_STRETCH_1_P: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
XIP_trans_error_int_2 <= '0';
else
XIP_trans_error_int_2 <= XIP_trans_error_cmb xor
XIP_trans_error_int_2;
end if;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1_P;
XIP_TRANS_ERROR_AXI42AXI: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => XIP_trans_error_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => XIP_trans_error_d2
);
XIP_TR_ERROR_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
XIP_trans_error_d3 <= XIP_trans_error_d2 ;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1;
XIP_trans_cdc_to_error <= XIP_trans_error_d2 xor XIP_trans_error_d3;
XIP_trans_error <= XIP_trans_cdc_to_error;
--=================================================================================
LAST_DATA_PULSE_STRETCH_1_CDC: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
last_data_acked_int_2 <= '0';
--axi4_tr_over_d1 <= '0';
else
last_data_acked_int_2 <= last_data_acked xor
last_data_acked_int_2;
--axi4_tr_over_d1 <= last_data_acked_int_2;
end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1_CDC;
AXI4_TR_OVER_AXI42AXI: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => last_data_acked_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => axi4_tr_over_d2
);
LAST_DATA_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
axi4_tr_over_d3 <= axi4_tr_over_d2 ;
-- end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1;
axi4_tr_over <= axi4_tr_over_d2 xor axi4_tr_over_d3;
--=================================================================================
ARREADY_PULSE_STRETCH_1_CDC: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
s_axi_arready_int_2 <= '1';
--arready_d1 <= '0';
else
s_axi_arready_int_2 <= s_axi_arready_cmb xor
s_axi_arready_int_2;
--arready_d1 <= s_axi_arready_int_2;
end if;
end if;
end process ARREADY_PULSE_STRETCH_1_CDC;
ARREADY_PULSE_AXI42AXI: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => s_axi_arready_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => arready_d2
);
ARREADY_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
arready_d3 <= arready_d2;
-- end if;
end if;
end process ARREADY_PULSE_STRETCH_1;
new_tr_at_axi4 <= arready_d2 xor arready_d3;
--==================================================================================
CPHA_CPOL_ERR_AXI2AXI4: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => XIPSR_CPHA_CPOL_ERR ,
scndry_aclk => S_AXI4_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI4_ARESET ,
scndry_out => XIPSR_CPHA_CPOL_ERR_4
);
--==================================================================================
end generate LOGIC_GENERATION_CDC;
XIPSR_RX_EMPTY_P: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1')then
if(S_AXI_ARESETN = ACTIVE_HIGH_RESET) then
TO_XIPSR_axi_rx_empty <= '1';
elsif(axi4_tr_over = '1')then
TO_XIPSR_axi_rx_empty <= '1';
elsif(new_tr_at_axi4 = '1')then
TO_XIPSR_axi_rx_empty <= '0';
end if;
end if;
end process XIPSR_RX_EMPTY_P;
-------------------------------------
TO_XIPSR_trans_error <= XIP_trans_error;
TO_XIPSR_mst_modf_err <= mst_modf_err_to_axi_clk;
TO_XIPSR_axi_rx_full <= Rx_FIFO_Full_to_axi_clk;
-- XIP_PS_TO_NS_PROCESS: stores the next state memory
XIP_PS_TO_NS_PROCESS: process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
xip_sm_ps <= IDLE;
else
xip_sm_ps <= xip_sm_ns;
end if;
end if;
end process XIP_PS_TO_NS_PROCESS;
-----------------------------
-- XIP_SM_P: below state machine is AXI interface state machine and controls the
-- acceptance of new transaction as well as monitors data transaction
XIP_SM_P:process(
xip_sm_ps ,
S_AXI4_ARVALID ,
S_AXI4_RREADY ,
S_AXI4_ARBURST ,
XIP_trans_error_cmb ,
mst_modf_err_to_axi4_clk,
Rx_FIFO_Full_to_Axi4_clk,
XIPSR_CPHA_CPOL_ERR_4 ,
Rx_FIFO_Empty ,
wb_hpm_done_to_axi ,
spiXfer_done_to_axi_1 ,
last_data_cmb ,
Rx_FIFO_rd_ack ,--,
last_data_acked
--wrap_around_to_axi_clk ,
--last_bt_one_data_cmb ,
--Rx_FIFO_Empty ,
--only_last_count ,
--rx_fifo_not_empty ,
--rx_fifo_count ,
)is
begin
-----
s_axi_arready_cmb <= '0';
load_axi_data_frm_axi <= '0';
load_cmd <= '0';
s_axi_rlast_cmb <= '0';
s_axi_rvalid_cmb <= '0';
last_data <= '0';
--IO0_T_cntrl_axi <= '1';
--IO1_T_cntrl_axi <= '1';
--IO2_T_cntrl_axi <= '1';
--IO3_T_cntrl_axi <= '1';
--SCK_T_cntrl_axi <= '1';
temp_i <= '0';
case xip_sm_ps is
when IDLE => --if(XIP_cmd_error = '0') then
if(S_AXI4_ARVALID = '1') and
(XIP_trans_error_cmb = '0') and
(mst_modf_err_to_axi4_clk = '0') and
(Rx_FIFO_Full_to_axi4_clk = '0') and
(XIPSR_CPHA_CPOL_ERR_4 = '0') and
(Rx_FIFO_Empty = '1') and
(wb_hpm_done_to_axi = '1')
then
s_axi_arready_cmb <= S_AXI4_ARVALID;
load_axi_data_frm_axi <= S_AXI4_ARVALID;
load_cmd <= S_AXI4_ARVALID;
xip_sm_ns <= RD_BURST;
else
xip_sm_ns <= IDLE;
end if;
when RD_BURST =>
--if(last_data_cmb = '1') and (Rx_FIFO_rd_ack = '1') then--(rx_fifo_count = "000001") then
if (last_data_acked = '1') then
if(S_AXI4_RREADY = '1') then
temp_i <= '1';
xip_sm_ns <= IDLE;
else
xip_sm_ns <= RD_BURST;
end if;
else
xip_sm_ns <= RD_BURST;
end if;
-- coverage off
when others => xip_sm_ns <= IDLE;
-- coverage on
end case;
end process XIP_SM_P;
----------------------
-- AXI_24_BIT_ADDR_STORE_GEN: stores 24 bit axi address
AXI_24_BIT_ADDR_STORE_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
LOAD_TRANSMIT_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
Transmit_addr_int <= (others => '0');
elsif(load_axi_data_frm_axi = '1') then
Transmit_addr_int <= S_AXI4_ARADDR(23 downto 0);-- & XIPCR_7_0_CMD;
end if;
end if;
end process LOAD_TRANSMIT_ADDR_P;
end generate AXI_24_BIT_ADDR_STORE_GEN;
-----------------------------------------
-- AXI_32_BIT_ADDR_STORE_GEN: stores 32 bit axi address
AXI_32_BIT_ADDR_STORE_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate -- 3/30/2013 updated for 32 or 24 bit addressing modes
begin
LOAD_TRANSMIT_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
Transmit_addr_int <= (others => '0');
elsif(load_axi_data_frm_axi = '1') then
Transmit_addr_int <= S_AXI4_ARADDR(C_SPI_MEM_ADDR_BITS-1 downto 0);-- & XIPCR_7_0_CMD;
end if;
end if;
end process LOAD_TRANSMIT_ADDR_P;
end generate AXI_32_BIT_ADDR_STORE_GEN;
-----------------------------------------
-- 24/32-bit --
-- AXI Clk domain -- __________________ SPI clk domain
--Dout --|AXI clk |-- Din
--Rd_en --| |-- Wr_en
--Rd_clk --| |-- Wr_clk
--| |--
--Rx_FIFO_Empty --| Rx FIFO |-- Rx_FIFO_Full
--Rx_FIFO_almost_Empty --| |-- Rx_FIFO_almost_Full
--Rx_FIFO_occ_Reversed --| |--
--Rx_FIFO_rd_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
-------------------------------------------------------------------------------
XIP_RECEIVE_FIFO_II: entity lib_fifo_v1_0.async_fifo_fg
generic map(
-- 3/30/2013 starts
--C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
--C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- 3/30/2013 ends
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_S_AXI4_DATA_WIDTH , -- : integer := 16;
C_FIFO_DEPTH => C_XIP_FIFO_DEPTH , -- : integer := 256;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT, -- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT, -- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map(
Dout => Data_From_Rx_FIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => S_AXI4_RREADY , -- : in std_logic := '0';
Rd_clk => S_AXI4_ACLK , -- : in std_logic := '1';
Rd_ack => Rx_FIFO_rd_ack , -- : out std_logic;
------
Din => Data_To_Rx_FIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => store_date_in_drr_fifo_en , --SPIXfer_done_Rx_Wr_en, -- , -- : in std_logic := '1';
Wr_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Wr_ack => open, -- Rx_FIFO_wr_ack_open, -- : out std_logic;
------
Full => Rx_FIFO_Full, --Rx_FIFO_Full, -- : out std_logic;
Empty => Rx_FIFO_Empty , -- : out std_logic;
Almost_full => Rx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Rx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => open , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => Rst_to_spi ,--reset_RcFIFO_ptr_int, -- reset_RcFIFO_ptr_to_spi_clk ,--Rx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => open , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => rd_error_int , -- : out std_logic;
Wr_err => open -- : out std_logic
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- from SPI clock
spiXfer_done_frm_spi_clk <= store_date_in_drr_fifo_en; --spiXfer_done_int;
mst_modf_err_frm_spi_clk <= not SPISEL_sync; -- 9/7/2013 -- MODF_strobe; -- 9/7/2013
--wrap_around_frm_spi_clk <= wrap_around;
wb_hpm_done_frm_spi_clk <= wb_hpm_done;
-- from AXI clocks
--size_length_frm_axi_clk <= size_length;
one_byte_xfer_frm_axi_clk <= one_byte_xfer;
two_byte_xfer_frm_axi_clk <= two_byte_xfer;
four_byte_xfer_frm_axi_clk <= four_byte_xfer;
load_axi_data_frm_axi_clk <= load_axi_data_frm_Axi;-- 1 bit
Transmit_Addr_frm_axi_clk <= Transmit_addr_int; -- 24 bit
load_cmd_frm_axi_clk <= load_cmd;
CPOL_frm_axi_clk <= XIPCR_1_CPOL; -- 1 bit
CPHA_frm_axi_clk <= XIPCR_0_CPHA; -- 1 bit
SS_frm_axi_clk <= SS_frm_axi; -- _reg; -- based upon C_NUM_SS_BITS
type_of_burst_frm_axi_clk <= type_of_burst; -- 1 bit signal take MSB only to differentiate WRAP and INCR burst
axi_length_frm_axi_clk <= axi_length; -- 8 bit used for WRAP transfer
dtr_length_frm_axi_clk <= dtr_length; -- 8 bit used for internbal counter
XIP_CLK_DOMAIN_SIGNALS:entity axi_quad_spi_v3_2.xip_cross_clk_sync
generic map(
C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH ,
Async_Clk => Async_Clk ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_SPI_MEM_ADDR_BITS => XIP_ADDR_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK ,
S_AXI4_ACLK => S_AXI4_ACLK ,
S_AXI4_ARESET => S_AXI4_ARESET ,
S_AXI_ACLK => S_AXI_ACLK ,
S_AXI_ARESETN => S_AXI_ARESETN ,
Rst_from_axi_cdc_to_spi => Rst_to_spi ,
----------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk ,
spiXfer_done_cdc_to_axi_1 => spiXfer_done_to_axi_1 ,
----------------------------
mst_modf_err_cdc_from_spi => mst_modf_err_frm_spi_clk ,
mst_modf_err_cdc_to_axi => mst_modf_err_to_axi_clk ,
mst_modf_err_cdc_to_axi4 => mst_modf_err_to_axi4_clk ,
----------------------------
one_byte_xfer_cdc_from_axi => one_byte_xfer_frm_axi_clk ,
one_byte_xfer_cdc_to_spi => one_byte_xfer_to_spi_clk ,
----------------------------
two_byte_xfer_cdc_from_axi => two_byte_xfer_frm_axi_clk ,
two_byte_xfer_cdc_to_spi => two_byte_xfer_to_spi_clk ,
----------------------------
four_byte_xfer_cdc_from_axi => four_byte_xfer_frm_axi_clk ,
four_byte_xfer_cdc_to_spi => four_byte_xfer_to_spi_clk ,
----------------------------
load_axi_data_cdc_from_axi => load_axi_data_frm_axi_clk ,
load_axi_data_cdc_to_spi => load_axi_data_to_spi_clk ,
----------------------------
Transmit_Addr_cdc_from_axi => Transmit_Addr_frm_axi_clk ,
Transmit_Addr_cdc_to_spi => Transmit_Addr_to_spi_clk ,
----------------------------
load_cmd_cdc_from_axi => load_cmd_frm_axi_clk ,
load_cmd_cdc_to_spi => load_cmd_to_spi_clk ,
----------------------------
CPOL_cdc_from_axi => CPOL_frm_axi_clk ,
CPOL_cdc_to_spi => CPOL_to_spi_clk ,
----------------------------
CPHA_cdc_from_axi => CPHA_frm_axi_clk ,
CPHA_cdc_to_spi => CPHA_to_spi_clk ,
------------------------------
SS_cdc_from_axi => SS_frm_axi_clk ,
SS_cdc_to_spi => SS_to_spi_clk ,
----------------------------
type_of_burst_cdc_from_axi => type_of_burst_frm_axi_clk ,
type_of_burst_cdc_to_spi => type_of_burst_to_spi_clk ,
----------------------------
axi_length_cdc_from_axi => axi_length_frm_axi_clk ,
axi_length_cdc_to_spi => axi_length_to_spi_clk ,
----------------------------
dtr_length_cdc_from_axi => dtr_length_frm_axi_clk ,
dtr_length_cdc_to_spi => dtr_length_to_spi_clk , --,
----------------------------
Rx_FIFO_Full_cdc_from_spi => Rx_FIFO_Full ,
Rx_FIFO_Full_cdc_to_axi => Rx_FIFO_Full_to_axi_clk ,
Rx_FIFO_Full_cdc_to_axi4 => Rx_FIFO_Full_to_axi4_clk ,
----------------------------
wb_hpm_done_cdc_from_spi => wb_hpm_done_frm_spi_clk ,
wb_hpm_done_cdc_to_axi => wb_hpm_done_to_axi
);
-------------------------------------------------------------------------------
-- STORE_NEW_TR_P: This process is used in INCR and WRAP to check for any new transaction from AXI
STORE_NEW_TR_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
-------------------------------------
STORE_NEW_TR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
new_tr <= '0';
elsif( (load_axi_data_to_spi_clk = '1')
or (load_wr_hpm = '1') -- needed for enabling 32 bit addressing mode
or (load_wr_en = '1') -- needed for write enabling before enabling the 32 bit addressing mode
) then
new_tr <= '1';
elsif(SR_5_Tx_Empty_int = '1') then --(wrap_around = '0' and qspi_cntrl_ns = IDLE)then
new_tr <= '0';
end if;
end if;
end process STORE_NEW_TR_P;
-------------------------------------
end generate STORE_NEW_TR_32_BIT_ADDR_GEN;
---------------------------------------------
STORE_NEW_TR_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
-------------------------------------
STORE_NEW_TR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
new_tr <= '0';
elsif( (load_axi_data_to_spi_clk = '1')
or (load_wr_hpm = '1')
-- or (load_wr_en = '1')
) then
new_tr <= '1';
elsif(SR_5_Tx_Empty_int = '1') then --(wrap_around = '0' and qspi_cntrl_ns = IDLE)then
new_tr <= '0';
end if;
end if;
end process STORE_NEW_TR_P;
-------------------------------------
end generate STORE_NEW_TR_24_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
-- STORE_INITAL_ADDR_P: The address frm AXI should be stored in the SPI environment
-- as the address generation logic will work in this domain.
STORE_24_BIT_SPI_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
-------------------------------------
STORE_INITAL_ADDR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
spi_addr <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
spi_addr <= "00000000" & Transmit_Addr_to_spi_clk;-- (31 downto 8);
elsif(load_wrap_addr = '1')then -- and (type_of_burst_to_spi = '1') then
spi_addr <= "00000000" & spi_addr_wrap;
end if;
end if;
end process STORE_INITAL_ADDR_P;
-------------------------------------
end generate STORE_24_BIT_SPI_ADDR_GEN;
-----------------------------------------
STORE_32_BIT_SPI_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate -- 3/30/2013
begin
-----
----------------------------------
STORE_INITAL_ADDR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
spi_addr <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
spi_addr <= Transmit_Addr_to_spi_clk;-- (31 downto 0);
elsif(load_wrap_addr = '1')then -- and (type_of_burst_to_spi = '1') then
spi_addr <= spi_addr_wrap;
end if;
end if;
end process STORE_INITAL_ADDR_P;
----------------------------------
end generate STORE_32_BIT_SPI_ADDR_GEN;
---------------------------------------
-------------------------------------------------------------------------------
-- below signals will store the length of AXI transaction in the SPI domain
axi_len_two <= not(or_Reduce(axi_length_to_spi_clk(3 downto 1))) and
axi_length_to_spi_clk(0);
axi_len_four <= not(or_Reduce(axi_length_to_spi_clk(3 downto 2))) and
and_reduce(axi_length_to_spi_clk(1 downto 0));
axi_len_eight <= not(axi_length_to_spi_clk(3)) and
and_Reduce(axi_length_to_spi_clk(2 downto 0));
axi_len_sixteen <= and_reduce(axi_length_to_spi_clk(3 downto 0));
-------------------------------------------------------------------------------
-- below signals store the WRAP information in SPI domain
wrap_two <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_two = '1')
else
'0';
wrap_four <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_four = '1')
else
'0';
wrap_eight <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_eight = '1')
else
'0';
wrap_sixteen <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_sixteen = '1')
else
'0';
-------------------------------------------------------------------------------
-- SPI_ADDRESS_REG: This process stores the initial address coming from the AXI in
-- two registers. one register will store this address till the
-- transaction ends, while other will be updated based upon type of
-- transaction as well as at the end of each SPI transfer. this is
-- used for internal use only.
SPI_24_BIT_ADDRESS_REG_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
SPI_ADDRESS_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_i <= (others => '0');
spi_addr_int <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_i <= Transmit_Addr_to_spi_clk(23 downto 0);
spi_addr_int <= Transmit_Addr_to_spi_clk(23 downto 0);
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_int(23 downto 0) <= spi_addr_int(23 downto 0) + '1';
case size_length_cntr is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 1) <= spi_addr_i(23 downto 1);
spi_addr_i(0) <= not (spi_addr_i(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_i(23 downto 2) <= spi_addr_i(23 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0001";
else
spi_addr_i <= spi_addr_i + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 2) <= spi_addr_i(23 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_i(23 downto 5) <= spi_addr_i(23 downto 5);
spi_addr_i(4 downto 0) <= spi_addr_i(4 downto 0) + "00010";
else
spi_addr_i <= spi_addr_i + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <=spi_addr_i(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <=spi_addr_i(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_i(23 downto 5) <= spi_addr_i(23 downto 5);
spi_addr_i(4 downto 0) <=spi_addr_i(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_i(23 downto 6) <= spi_addr_i(23 downto 6);
spi_addr_i(5 downto 0) <=spi_addr_i(5 downto 0) + "000100";
else
spi_addr_i <= spi_addr_i + "0100";
end if;
-- coverage off
when others =>
spi_addr_i <= spi_addr_i;
-- coverage on
end case;
-- below is address generation for the INCR mode
elsif (type_of_burst_to_spi_clk = '0') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_i(23 downto 0) <= spi_addr_i(23 downto 0) + '1';
end if;
end if;
end if;
end process SPI_ADDRESS_REG;
----------------------------------
end generate SPI_24_BIT_ADDRESS_REG_GEN;
----------------------------------------
SPI_32_BIT_ADDRESS_REG_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
SPI_ADDRESS_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_i <= (others => '0');
spi_addr_int <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_i <= Transmit_Addr_to_spi_clk(31 downto 0);
spi_addr_int <= Transmit_Addr_to_spi_clk(31 downto 0);
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_int(31 downto 0) <= spi_addr_int(31 downto 0) + '1';
case size_length_cntr is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 1) <= spi_addr_i(31 downto 1);
spi_addr_i(0) <= not (spi_addr_i(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_i(31 downto 2) <= spi_addr_i(31 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0001";
else
spi_addr_i <= spi_addr_i + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 2) <= spi_addr_i(31 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_i(31 downto 5) <= spi_addr_i(31 downto 5);
spi_addr_i(4 downto 0) <= spi_addr_i(4 downto 0) + "00010";
else
spi_addr_i <= spi_addr_i + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <=spi_addr_i(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <=spi_addr_i(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_i(31 downto 5) <= spi_addr_i(31 downto 5);
spi_addr_i(4 downto 0) <=spi_addr_i(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_i(31 downto 6) <= spi_addr_i(31 downto 6);
spi_addr_i(5 downto 0) <=spi_addr_i(5 downto 0) + "000100";
else
spi_addr_i <= spi_addr_i + "0100";
end if;
-- coverage off
when others =>
spi_addr_i <= spi_addr_i;
-- coverage on
end case;
-- below is address generation for the INCR mode
elsif (type_of_burst_to_spi_clk = '0') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_i(31 downto 0) <= spi_addr_i(31 downto 0) + '1';
end if;
end if;
end if;
end process SPI_ADDRESS_REG;
end generate SPI_32_BIT_ADDRESS_REG_GEN;
----------------------------------------
-- SPI_WRAP_ADDR_REG: this is separate process used for WRAP address generation
SPI_24_WRAP_ADDR_REG_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_wrap <= Transmit_Addr_to_spi_clk(23 downto 0);
elsif(wrap_ack_1 = '1') then
spi_addr_wrap <= spi_addr_wrap_1;
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(store_date_in_drr_fifo = '1') and
(cmd_addr_sent = '1') then
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 1) <= spi_addr_wrap(23 downto 1);
spi_addr_wrap(0) <= not (spi_addr_wrap(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap(23 downto 2) <= spi_addr_wrap(23 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0001";
else
spi_addr_wrap <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 2) <= spi_addr_wrap(23 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(23 downto 5) <= spi_addr_wrap(23 downto 5);
spi_addr_wrap(4 downto 0) <= spi_addr_wrap(4 downto 0) + "00010";
else
spi_addr_wrap <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <=spi_addr_wrap(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <=spi_addr_wrap(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap(23 downto 5) <= spi_addr_wrap(23 downto 5);
spi_addr_wrap(4 downto 0) <=spi_addr_wrap(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(23 downto 6) <= spi_addr_wrap(23 downto 6);
spi_addr_wrap(5 downto 0) <=spi_addr_wrap(5 downto 0) + "000100";
else
spi_addr_wrap <= spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process SPI_WRAP_ADDR_REG;
end generate SPI_24_WRAP_ADDR_REG_GEN;
--------------------------------------
SPI_32_WRAP_ADDR_REG_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_wrap <= Transmit_Addr_to_spi_clk(31 downto 0);
elsif(wrap_ack_1 = '1') then
spi_addr_wrap <= spi_addr_wrap_1;
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(store_date_in_drr_fifo = '1') and
(cmd_addr_sent = '1') then
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 1) <= spi_addr_wrap(31 downto 1);
spi_addr_wrap(0) <= not (spi_addr_wrap(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap(31 downto 2) <= spi_addr_wrap(31 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0001";
else
spi_addr_wrap <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 2) <= spi_addr_wrap(31 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(31 downto 5) <= spi_addr_wrap(31 downto 5);
spi_addr_wrap(4 downto 0) <= spi_addr_wrap(4 downto 0) + "00010";
else
spi_addr_wrap <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <=spi_addr_wrap(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <=spi_addr_wrap(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap(31 downto 5) <= spi_addr_wrap(31 downto 5);
spi_addr_wrap(4 downto 0) <=spi_addr_wrap(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(31 downto 6) <= spi_addr_wrap(31 downto 6);
spi_addr_wrap(5 downto 0) <=spi_addr_wrap(5 downto 0) + "000100";
else
spi_addr_wrap <= spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process SPI_WRAP_ADDR_REG;
----------------------------------
end generate SPI_32_WRAP_ADDR_REG_GEN;
--------------------------------------
-------------------------------------------------------------------------------
-- SPI_WRAP_ADDR_REG: this is separate process used for WRAP address generation
LOAD_SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap_1 <= (others => '0');
else
if (wrap_around = '1') then
-- below is address generation for the WRAP mode
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + '1';
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap_1 <= spi_addr_wrap + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap_1 <= spi_addr_wrap + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap_1 <= spi_addr_wrap + "0001";
else
spi_addr_wrap_1 <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "10";
elsif(wrap_four = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "00010";
else
spi_addr_wrap_1 <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "100";
elsif(wrap_four = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "000100";
else
spi_addr_wrap_1 <=spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap_1 <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process LOAD_SPI_WRAP_ADDR_REG;
-------------------------------------------------------------------------------
-- WRAP_AROUND_GEN_P : WRAP boundary detection logic
WRAP_AROUND_GEN_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if( (Rst_to_spi = '1')
or(rst_wrap_around = '1')
) then
wrap_around <= '0';
elsif(type_of_burst_to_spi_clk = '1')then
case size_length_cntr_fixed is
when "00" => -- byte transfer
if(wrap_two = '1') and
(spi_addr_wrap(1) = '1') and
(store_date_in_drr_fifo = '1')then -- then
wrap_around <= --spi_addr_wrap(1) and
not SR_5_Tx_Empty;
elsif(wrap_four = '1') and
(spi_addr_wrap(1 downto 0) = "11") and
(store_date_in_drr_fifo = '1')then -- then -- the byte address increment will take 2 address bits
wrap_around <= --and_reduce(spi_addr_wrap(1 downto 0)) and
not SR_5_Tx_Empty;
elsif(wrap_eight = '1') and
(spi_addr_wrap(2 downto 0) = "111") and
(store_date_in_drr_fifo = '1')then -- then -- the byte address increment will take 3 address bits
wrap_around <= --and_reduce(spi_addr_wrap(2 downto 0)) and
not SR_5_Tx_Empty;
elsif(wrap_sixteen = '1') and
(spi_addr_wrap(3 downto 0) = "1111") and
(store_date_in_drr_fifo = '1')then -- the byte address increment will take 4 address bits for 16's wrap
wrap_around <= --and_reduce(spi_addr_wrap(3 downto 0)) and
not SR_5_Tx_Empty;
else
wrap_around <= '0';
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then -- and (spi_addr_wrap(1 downto 0) = "10") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_2_siz_16;
elsif(wrap_four = '1') then -- and (spi_addr_wrap(2 downto 0) = "110") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_4_siz_16;
elsif(wrap_eight = '1') then -- and (spi_addr_wrap(3 downto 0) = "1110") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_8_siz_16;
elsif(wrap_sixteen = '1') then -- and (spi_addr_wrap(4 downto 0) = "11110") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_16_siz_16;
else
wrap_around <= '0';
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then -- and (spi_addr_wrap(2 downto 0) = "100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_2_siz_32;
elsif(wrap_four = '1') then -- and (spi_addr_wrap(3 downto 0) = "1100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_4_siz_32;
elsif(wrap_eight = '1') then -- and (spi_addr_wrap(4 downto 0) = "11100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_8_siz_32;
elsif(wrap_sixteen = '1') then --and (spi_addr_wrap(5 downto 0) = "111100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_16_siz_32;
else
wrap_around <= '0';
end if;
-- coverage off
when others => wrap_around <= wrap_around;
-- coverage on
end case;
end if;
end if;
end process WRAP_AROUND_GEN_P;
-------------------------------------------------------------------------------
load_wrap_addr <= wrap_around;
wrp_addr_len_16_siz_32 <= '1' when (spi_addr_wrap(5 downto 0) = "111100") else '0';
wrp_addr_len_8_siz_32 <= '1' when (spi_addr_wrap(4 downto 0) = "11100") else '0';
wrp_addr_len_4_siz_32 <= '1' when (spi_addr_wrap(3 downto 0) = "1100") else '0';
wrp_addr_len_2_siz_32 <= '1' when (spi_addr_wrap(2 downto 0) = "100") else '0';
-----------------------------------------------------------------------------------
wrp_addr_len_16_siz_16 <= '1' when (spi_addr_wrap(4 downto 0) = "11110") else '0';
wrp_addr_len_8_siz_16 <= '1' when (spi_addr_wrap(3 downto 0) = "1110") else '0';
wrp_addr_len_4_siz_16 <= '1' when (spi_addr_wrap(2 downto 0) = "110") else '0';
wrp_addr_len_2_siz_16 <= '1' when (spi_addr_wrap(1 downto 0) = "10") else '0';
-----------------------------------------------------------------------------------
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytes are transferred from SPI.
LEN_CNTR_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
LEN_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
length_cntr <= (others => '0');
elsif(load_wr_hpm='1') then
length_cntr <= "00000011";
elsif(load_cmd_to_spi_clk = '1')then
length_cntr <= dtr_length_to_spi_clk;
elsif((SPIXfer_done_int = '1') and
(((size_length_cntr = "00") and
(cmd_addr_sent = '1')
)or
(hpm_under_process_d1 = '1'))
)then
length_cntr <= length_cntr - "00000001";
end if;
end if;
end process LEN_CNTR_P;
-----------------------
end generate LEN_CNTR_24_BIT_GEN;
---------------------------------
LEN_CNTR_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
LEN_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
length_cntr <= (others => '0');
elsif(load_wr_hpm='1') then
length_cntr <= "00000000";
elsif(load_cmd_to_spi_clk = '1')then
length_cntr <= dtr_length_to_spi_clk;
elsif((SPIXfer_done_int = '1') and
(((size_length_cntr = "00") and
(cmd_addr_sent = '1')
)or
(hpm_under_process_d1 = '1') or (wr_en_under_process_d1 = '1'))
)then
length_cntr <= length_cntr - "00000001";
end if;
end if;
end process LEN_CNTR_P;
-----------------------
end generate LEN_CNTR_32_BIT_GEN;
---------------------------------
-------------------------------------------------------------------------------
SR_5_TX_EMPTY_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SR_5_Tx_Empty_int<= (not(or_reduce(length_cntr)) and
store_date_in_drr_fifo and
cmd_addr_sent)
or
(-- (hpm_under_process_d1 or wr_en_under_process_d1) and
(hpm_under_process or wr_en_under_process) and
not(or_reduce(length_cntr)) and
SPIXfer_done_int_pulse);
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytesfor 24 bit addressing and 5 bytes for 32 bit addressing mode are transferred from SPI.
SR_5_TX_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty <= '1';
elsif(load_cmd_to_spi_clk = '1') or (load_wr_hpm = '1') or (load_wr_en = '1') then
SR_5_Tx_Empty <= '0';
elsif(SR_5_Tx_Empty_int = '1')then
SR_5_Tx_Empty <= '1';
end if;
end if;
end process SR_5_TX_EMPTY_P;
end generate SR_5_TX_EMPTY_32_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
SR_5_TX_EMPTY_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SR_5_Tx_Empty_int<= (not(or_reduce(length_cntr)) and
store_date_in_drr_fifo and
cmd_addr_sent)
or
(-- (hpm_under_process_d1 or wr_en_under_process_d1) and
(hpm_under_process
--or wr_en_under_process
)
and
not(
or_reduce(length_cntr))
and
SPIXfer_done_int_pulse
);
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytesfor 24 bit addressing and 5 bytes for 32 bit addressing mode are transferred from SPI.
SR_5_TX_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty <= '1';
elsif(load_cmd_to_spi_clk = '1') or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
SR_5_Tx_Empty <= '0';
elsif(SR_5_Tx_Empty_int = '1')then
SR_5_Tx_Empty <= '1';
end if;
end if;
end process SR_5_TX_EMPTY_P;
end generate SR_5_TX_EMPTY_24_BIT_ADDR_GEN;
-------------------------------------------
DELAY_FIFO_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty_d1 <= '1';
SR_5_Tx_Empty_d2 <= '1';
else
SR_5_Tx_Empty_d1 <= SR_5_Tx_Empty;
SR_5_Tx_Empty_d2 <= SR_5_Tx_Empty_d1;
end if;
end if;
end process DELAY_FIFO_EMPTY_P;
-------------------------------------------------------------------------------
last_bt_one_data <= not(or_reduce(length_cntr(7 downto 1))) and length_cntr(0);
-------------------------------------------------------------------------------
SIZE_CNTR_LD_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
size_length_cntr_fixed <= (others => '0');
size_length_cntr <= (others => '0');
elsif(
(pr_state_idle = '1') or ((SPIXfer_done_int = '1') and
(size_length_cntr = "00"))
)then
--if(one_byte_xfer_to_spi_clk = '1' )then
-- size_length_cntr_fixed <= "00";
-- size_length_cntr <= "00"; -- 1 byte
--els
if(two_byte_xfer_to_spi_clk = '1')then
size_length_cntr_fixed <= "01";
size_length_cntr <= "01"; -- half word
elsif(four_byte_xfer_to_spi_clk = '1') then
size_length_cntr_fixed <= "10";
size_length_cntr <= "11"; -- word
else
size_length_cntr_fixed <= "00";
size_length_cntr <= "00"; -- other and one_byte_xfer_to_spi_clk = '1' is merged here
end if;
elsif(SPIXfer_done_int = '1') and
(one_byte_xfer_to_spi_clk = '0')and
(cmd_addr_sent = '1') then -- (size_length_cntr /= "00") then
size_length_cntr <= size_length_cntr - "01";
end if;
end if;
end process SIZE_CNTR_LD_SPI_CLK_P;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
store_date_in_drr_fifo <= not(or_reduce(size_length_cntr)) and
SPIXfer_done_int and
cmd_addr_sent;
-------------------------------------------------------------------------------
STORE_STROBE_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
store_date_in_drr_fifo_d1 <= '0';
store_date_in_drr_fifo_d2 <= '0';
store_date_in_drr_fifo_d3 <= '0';
else
store_date_in_drr_fifo_d1 <= store_date_in_drr_fifo;
store_date_in_drr_fifo_d2 <= store_date_in_drr_fifo_d1;
store_date_in_drr_fifo_d3 <= store_date_in_drr_fifo_d2;
end if;
end if;
end process STORE_STROBE_SPI_CLK_P;
-------------------------------------------------------------------------------
MD_12_WR_EN_TO_FIFO_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
begin
-----
--------------------------------------------------------------------
WB_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 1 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate WB_FIFO_WR_EN_GEN;
--------------------------------------------------------------------
NM_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 2 generate
begin
-----
STORE_DATA_24_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_24_BIT_ADDRESS_GEN;
-------------------------------------------
STORE_DATA_32_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_32_BIT_ADDRESS_GEN;
-------------------------------------------
end generate NM_FIFO_WR_EN_GEN;
--------------------------------------------------------------------
SP_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 3 generate
begin
-----
STORE_DATA_24_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_24_BIT_ADDRESS_GEN;
-------------------------------------------
STORE_DATA_32_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_32_BIT_ADDRESS_GEN;
-------------------------------------------
end generate SP_FIFO_WR_EN_GEN;
--------------------------------------------------------------------
end generate MD_12_WR_EN_TO_FIFO_GEN;
MD_0_WR_EN_TO_FIFO_GEN: if C_SPI_MODE = 0 generate
begin
-----
WB_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 1 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo;
end generate WB_FIFO_WR_EN_GEN;
NM_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 2 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo;
end generate NM_FIFO_WR_EN_GEN;
SP_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 3 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo;
end generate SP_FIFO_WR_EN_GEN;
end generate MD_0_WR_EN_TO_FIFO_GEN;
-------------------------------------------------------------------------------
SHIFT_TX_REG_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SHIFT_TX_REG_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1')then
Tx_Data_d1 <= (others => '0');
elsif(load_wr_hpm = '1') then
Tx_Data_d1(31 downto 24) <= WB_wr_hpm_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
Tx_Data_d1 <= SPI_cmd & Transmit_Addr_to_spi_clk; -- & SPI_cmd;-- (31 downto 8);
elsif(wrap_around = '1') then
Tx_Data_d1 <= SPI_cmd & spi_addr_wrap;--spi_addr_i & SPI_cmd;
elsif(SPIXfer_done_int = '1')then
Tx_Data_d1 <= --"11111111" & -- Tx_Data_d1(7 downto 0) &
-- --Tx_Data_d1(31 downto 8);
-- Tx_Data_d1(31 downto 8);
Tx_Data_d1(23 downto 0) & "11111111";
end if;
end if;
end process SHIFT_TX_REG_SPI_CLK_P;
Transmit_Data <= Tx_Data_d1(31 downto 24);
end generate SHIFT_TX_REG_24_BIT_GEN;
-------------------------------------------------------
SHIFT_TX_REG_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SHIFT_TX_REG_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1')then
Tx_Data_d1 <= (others => '0');
--last_7_addr_bits <= (others => '0');
elsif(load_wr_en = '1') then
Tx_Data_d1(31 downto 24) <= "00000110"; ---nm_wr_en_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_wr_hpm = '1')then
Tx_Data_d1(31 downto 24) <= "10110111"; ---nm_4byte_addr_en_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
Tx_Data_d1 <= SPI_cmd & Transmit_Addr_to_spi_clk(31 downto 8); -- & SPI_cmd;-- (31 downto 8);
last_7_addr_bits <= Transmit_Addr_to_spi_clk(7 downto 0);
-- internal_count <= (others => '0');
elsif(wrap_around = '1') then
Tx_Data_d1 <= SPI_cmd & spi_addr_wrap(31 downto 8);--spi_addr_i & SPI_cmd;
last_7_addr_bits <= spi_addr_wrap(7 downto 0);
elsif(SPIXfer_done_int = '1') then -- and internal_count < "0101")then
Tx_Data_d1 <= --"11111111" & -- Tx_Data_d1(7 downto 0) &
-- --Tx_Data_d1(31 downto 8);
-- Tx_Data_d1(31 downto 8);
Tx_Data_d1(23 downto 0) & -- Transmit_Addr_to_spi_clk(7 downto 0);
-- spi_addr_wrap(7 downto 0);
last_7_addr_bits(7 downto 0);
-- internal_count <= internal_count + "0001";
--elsif(SPIXfer_done_int = '1' and internal_count = "0101") then
-- Tx_Data_d1 <= (others => '1');
end if;
end if;
end process SHIFT_TX_REG_SPI_CLK_P;
Transmit_Data <= Tx_Data_d1(31 downto 24);
-- STORE_INFO_P:process(EXT_SPI_CLK)is
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
-- if(Rst_to_spi = '1')then
-- data_loaded <= '0';
-- cmd_sent <= '0';
-- elsif(load_axi_data_to_spi_clk = '1' or wrap_around = '1) then
-- data_loaded <= '1';
-- elsif(data_loaded = '1' and SPIXfer_done_int = '1') then
-- cmd_sent <= '1';
-- end if;
-- end if;
-- end process STORE_INFO_P;
end generate SHIFT_TX_REG_32_BIT_GEN;
-------------------------------------------------------
-- Transmit_Data <= Tx_Data_d1(31 downto 24);
-------------------------------------------------------
-------------------------------------------------------------------------------
STD_MODE_CONTROL_GEN: if C_SPI_MODE = 0 generate
-----
begin
-----
WB_MEM_STD_MD_GEN: if C_SPI_MODE = 0 and C_SPI_MEMORY = 1 generate
-----------
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
wb_hpm_done <= '1';
load_wr_en <= '0';-- 4/12/2013 applicable only for Numonyx memories
---- Std mode command = 0x0B - Fast Read
SPI_cmd <= "00001011"; -- FAST_READ
-- |<---- cmd error
-- WB 000 000 0100 0<-cmd error
-- NM 000 000 0100 0
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 5 transactions are of
-- CMD, A0, A1, A2 and dummy. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is applicable only for Winbond memory.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
-- TWO_BIT_CNTR_P: This is specifically used for HW data storage
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (wrap_around = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-2) downto 0) &
IO1_I ; --MISO_I;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
-----------------------------------------
end generate WB_MEM_STD_MD_GEN;
------------------------
--------------------------------------------------------------------------
NM_MEM_STD_MD_GEN: if C_SPI_MODE = 0 and C_SPI_MEMORY = 2 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
---- Std mode command = 0x0B - Fast Read
STD_SPI_CMD_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "00001011";-- FAST_READ - 0x0Bh
-- |<---- cmd error
-- NM 000 000 0100 0
four_byte_en_done <= '1';
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg ) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
--case wb_hpm_done is
-- -- when "00"|"01" => -- write enable is under process
-- when '0' => -- write enable and/or Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- when "01" => -- Enable 4 byte addressing is under process
-- -- Data_Dir <= '0';
-- -- Data_Mode_1 <= '0';
-- -- Data_Mode_0 <= '0';
-- -- Data_Phase <= '0';
-- -- --------------------
-- -- Quad_Phase <= '0';-- permanent '0'
-- -- --------------------
-- -- Addr_Mode_1 <= '0';
-- -- Addr_Mode_0 <= '0';
-- -- Addr_Bit <= '0';
-- -- Addr_Phase <= '0';
-- -- --------------------
-- -- CMD_Mode_1 <= '0';
-- -- CMD_Mode_0 <= '0';
-- -- when "10" => -- write enable is done and enable 4 byte addressing is also done
-- when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- -- coverage off
-- when others =>
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- coverage on
--end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
end generate STD_SPI_CMD_NM_24_BIT_GEN;
STD_SPI_CMD_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "00001100";-- FAST_READ_4Byte - 0x0Ch
-- |<---- cmd error
-- NM 000 000 0100 0
--end generate STD_SPI_CMD_NM_32_BIT_GEN;
--NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
--begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
--end generate NM_EN_32_ADDR_MD_GEN;
end generate STD_SPI_CMD_NM_32_BIT_GEN;
---------------------------------------
-- wb_hpm_done <= four_byte_en_done;
--Data_Dir <= '0';
--Data_Mode_1 <= '0';
--Data_Mode_0 <= '0';
--Data_Phase <= '0';
----------------------
--Quad_Phase <= '0';-- permanent '0'
----------------------
--Addr_Mode_1 <= '0';
--Addr_Mode_0 <= '0';
--Addr_Bit <= '0';
--Addr_Phase <= '1';
----------------------
--CMD_Mode_1 <= '0';
--CMD_Mode_0 <= '0';
---------------------------
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int = '1') and (cmd_addr_cntr = "110")then
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-2) downto 0) &
IO1_I ; --MISO_I;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
CMD_ADDR_24_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 5 transactions are of
-- CMD, A0, A1, A2 and dummy. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. Tihs is for 24 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1') then -- and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_24_BIT_CNTR_GEN;
--------------------------------------
CMD_ADDR_32_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- * -- -----
-- * -- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- * -- -----
-- * -- begin
-- * -- -----
-- * -- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- * -- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- * -- receive_Data_int <= (others => '0');
-- * -- elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1') then -- and (cmd_addr_cntr = "111")then
-- * -- receive_Data_int <= rx_shft_reg_mode_0011;
-- * -- end if;
-- * -- end if;
-- * -- end process RECEIVE_DATA_STROBE_PROCESS;
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 6 transactions are of
-- CMD, A0, A1, A2, A3 and dummy. Total 6 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 6 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1' and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1' and wb_hpm_done = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_32_BIT_CNTR_GEN;
--------------------------------------
-- TWO_BIT_CNTR_P: This is specifically used for HW data storage
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (wrap_around = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate NM_MEM_STD_MD_GEN;
------------------------
SP_MEM_STD_MD_GEN: if C_SPI_MODE = 0 and C_SPI_MEMORY = 3 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
---- Std mode command = 0x0B - Fast Read
STD_SPI_CMD_SP_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "00001011";-- FAST_READ - 0x0Bh
-- |<---- cmd error
-- NM 000 000 0100 0
four_byte_en_done <= '1';
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
--case wb_hpm_done is
-- -- when "00"|"01" => -- write enable is under process
-- when '0' => -- write enable and/or Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- when "01" => -- Enable 4 byte addressing is under process
-- -- Data_Dir <= '0';
-- -- Data_Mode_1 <= '0';
-- -- Data_Mode_0 <= '0';
-- -- Data_Phase <= '0';
-- -- --------------------
-- -- Quad_Phase <= '0';-- permanent '0'
-- -- --------------------
-- -- Addr_Mode_1 <= '0';
-- -- Addr_Mode_0 <= '0';
-- -- Addr_Bit <= '0';
-- -- Addr_Phase <= '0';
-- -- --------------------
-- -- CMD_Mode_1 <= '0';
-- -- CMD_Mode_0 <= '0';
-- -- when "10" => -- write enable is done and enable 4 byte addressing is also done
-- when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- -- coverage off
-- when others =>
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- coverage on
--end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
end generate STD_SPI_CMD_SP_24_BIT_GEN;
STD_SPI_CMD_SP_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "00001100";-- FAST_READ_4Byte - 0x0Ch
-- |<---- cmd error
-- NM 000 000 0100 0
--end generate STD_SPI_CMD_NM_32_BIT_GEN;
--NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
--begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
SP_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process SP_PS_TO_NS_PROCESS;
----------------------------------
--
SP_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process SP_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
SP_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process SP_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
SP_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process SP_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
--end generate NM_EN_32_ADDR_MD_GEN;
end generate STD_SPI_CMD_SP_32_BIT_GEN;
---------------------------------------
-- wb_hpm_done <= four_byte_en_done;
--Data_Dir <= '0';
--Data_Mode_1 <= '0';
--Data_Mode_0 <= '0';
--Data_Phase <= '0';
----------------------
--Quad_Phase <= '0';-- permanent '0'
----------------------
--Addr_Mode_1 <= '0';
--Addr_Mode_0 <= '0';
--Addr_Bit <= '0';
--Addr_Phase <= '1';
----------------------
--CMD_Mode_1 <= '0';
--CMD_Mode_0 <= '0';
---------------------------
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int = '1') and (cmd_addr_cntr = "110")then
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-2) downto 0) &
IO1_I ; --MISO_I;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
CMD_ADDR_24_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 5 transactions are of
-- CMD, A0, A1, A2 and dummy. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. Tihs is for 24 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1') then -- and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_24_BIT_CNTR_GEN;
--------------------------------------
CMD_ADDR_32_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- * -- -----
-- * -- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- * -- -----
-- * -- begin
-- * -- -----
-- * -- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- * -- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- * -- receive_Data_int <= (others => '0');
-- * -- elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1') then -- and (cmd_addr_cntr = "111")then
-- * -- receive_Data_int <= rx_shft_reg_mode_0011;
-- * -- end if;
-- * -- end if;
-- * -- end process RECEIVE_DATA_STROBE_PROCESS;
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 6 transactions are of
-- CMD, A0, A1, A2, A3 and dummy. Total 6 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 6 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1' and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1' and wb_hpm_done = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_32_BIT_CNTR_GEN;
--------------------------------------
-- TWO_BIT_CNTR_P: This is specifically used for HW data storage
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (wrap_around = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate SP_MEM_STD_MD_GEN;
end generate STD_MODE_CONTROL_GEN;
-------------------------------------------------------------------------------
DUAL_MODE_CONTROL_GEN: if C_SPI_MODE = 1 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);-----
signal hw_wd_cntr : std_logic_vector(1 downto 0);
begin
-----
WB_MEM_DUAL_MD_GEN: if C_SPI_MEMORY = 1 generate
-----
begin
-----
wb_wr_hpm_CMD <= "10100011"; -- 0xA3 h HPM mode
--
----------------------------------------------------
WB_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
wb_cntrl_ps <= WB_IDLE;
hpm_under_process_d1 <= '0';
else
wb_cntrl_ps <= wb_cntrl_ns;
hpm_under_process_d1 <= hpm_under_process;
end if;
end if;
end process WB_PS_TO_NS_PROCESS;
----------------------------------
--
WB_DUAL_CNTRL_PROCESS: process(
wb_cntrl_ps ,
SPIXfer_done_int_pulse,
SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty
) is
-----
begin
-----
load_wr_en_cmd <= '0';
load_wr_sr_cmd <= '0';
load_wr_sr_d0 <= '0';
load_wr_sr_d1 <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
case wb_cntrl_ps is
when WB_IDLE => --load_wr_en_cmd <= '1';
load_wr_hpm <= '1';
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
when WB_WR_HPM => if (SR_5_Tx_Empty = '1')then
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
else
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
end if;
when WB_DONE => if (Rst_to_spi = '1') then
wb_cntrl_ns <= WB_IDLE;
else
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
end if;
end case;
end process WB_DUAL_CNTRL_PROCESS;
---- Dual mode command = 0x3B - DOFR
--SPI_cmd <= "00111011";
SPI_cmd <= "10111011"; -- 0xBB - DIOFR
-- WB 0011 000 100 0
-- NM 0011 000 100 0<-cmd error
-- NM 0011 010 100 0<-cmd error -- For 0xbbh DIOFR
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1'; -- <- '0' for DOFR, '1' for DIOFR
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------------------------------------------------
--RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-3) downto 0) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_WB_GEN;
---------------------------------------------------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "100")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (store_last_b4_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate WB_MEM_DUAL_MD_GEN;
---------------=============-------------------------------------------
NM_MEM_DUAL_MD_GEN: if C_SPI_MEMORY = 2 generate
-----
begin
-----
--wb_hpm_done <= '1';
---- Dual mode command = 0x3B - DOFR
--SPI_cmd <= "00111011";
--------------------------------------------------------
DUAL_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
-----
begin
-----
---------------------------
SPI_cmd <= "10111011"; -- 0xBB - DIOFR
wb_hpm_done <= '1';
---------------------------
Data_Dir <= '0';-- for BB
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------
end generate DUAL_SPI_CMD_NM_24_GEN;
------------------------------------
DUAL_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
-----
begin
-----
SPI_cmd <= "10111100"; -- 0xBCh - DIOFR_4Byte
end generate DUAL_SPI_CMD_NM_32_GEN;
------------------------------------
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
end generate NM_EN_32_ADDR_MD_GEN;
--------------------------------------
-- -- WB 0011 000 100 0
-- -- NM 0011 000 100 0<-cmd error
-- -- NM 0011 010 100 0<-cmd error -- For 0xbbh DIOFR
-- 0011 011 100 0
-- Data_Dir <= '0';<-- for BB -- '0';<-- for BC
-- Data_Mode_1 <= '0'; -- '0';
-- Data_Mode_0 <= '1'; -- '1';
-- Data_Phase <= '1'; -- '1';
-- -------------------- --
-- Quad_Phase <= '0';-- permanent '0' -- '0';
-- -------------------- --
-- Addr_Mode_1 <= '0'; -- '0';
-- Addr_Mode_0 <= '1'; -- '1';
-- Addr_Bit <= '0'; -- '1';
-- Addr_Phase <= '1'; -- '1';
-- -------------------- --
-- CMD_Mode_1 <= '0'; -- '0'
-- CMD_Mode_0 <= '0'; -- '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-3) downto 0) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is 4 byte addessing mode of NM memory.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "111")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (store_last_b4_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_32_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d3 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_32_BIT_ADDR;
STORE_RX_DATA_24_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_24_BIT_ADDR;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate NM_MEM_DUAL_MD_GEN;
SP_MEM_DUAL_MD_GEN: if C_SPI_MEMORY = 3 generate
-----
begin
-----
--wb_hpm_done <= '1';
---- Dual mode command = 0x3B - DOFR
--SPI_cmd <= "00111011";
--------------------------------------------------------
DUAL_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
-----
begin
-----
---------------------------
SPI_cmd <= "10111011"; -- 0xBB - DIOFR
wb_hpm_done <= '1';
---------------------------
Data_Dir <= '0';-- for BB
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------
end generate DUAL_SPI_CMD_NM_24_GEN;
------------------------------------
DUAL_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
-----
begin
-----
SPI_cmd <= "10111100"; -- 0xBCh - DIOFR_4Byte
end generate DUAL_SPI_CMD_NM_32_GEN;
------------------------------------
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
end generate NM_EN_32_ADDR_MD_GEN;
--------------------------------------
-- -- WB 0011 000 100 0
-- -- NM 0011 000 100 0<-cmd error
-- -- NM 0011 010 100 0<-cmd error -- For 0xbbh DIOFR
-- 0011 011 100 0
-- Data_Dir <= '0';<-- for BB -- '0';<-- for BC
-- Data_Mode_1 <= '0'; -- '0';
-- Data_Mode_0 <= '1'; -- '1';
-- Data_Phase <= '1'; -- '1';
-- -------------------- --
-- Quad_Phase <= '0';-- permanent '0' -- '0';
-- -------------------- --
-- Addr_Mode_1 <= '0'; -- '0';
-- Addr_Mode_0 <= '1'; -- '1';
-- Addr_Bit <= '0'; -- '1';
-- Addr_Phase <= '1'; -- '1';
-- -------------------- --
-- CMD_Mode_1 <= '0'; -- '0'
-- CMD_Mode_0 <= '0'; -- '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-3) downto 0) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "100")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is 4 byte addessing mode of NM memory.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (store_last_b4_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_32_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d3 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_32_BIT_ADDR;
STORE_RX_DATA_24_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_24_BIT_ADDR;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate SP_MEM_DUAL_MD_GEN;
end generate DUAL_MODE_CONTROL_GEN;
QUAD_MODE_CONTROL_GEN: if C_SPI_MODE = 2 generate
-----
begin
-----
-- WB 0011 0101 00 0<-cmd error
-- NM 001100101 00 0<-cmd error
WB_MEM_QUAD_MD_GEN:if C_SPI_MEMORY = 1 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
wb_wr_hpm_CMD <= "10100011"; -- 0xA3 h HPM mode
--
----------------------------------------------------
WB_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
wb_cntrl_ps <= WB_IDLE;
hpm_under_process_d1 <= '0';
else
wb_cntrl_ps <= wb_cntrl_ns;
hpm_under_process_d1 <= hpm_under_process;
end if;
end if;
end process WB_PS_TO_NS_PROCESS;
----------------------------------
--
WB_DUAL_CNTRL_PROCESS: process(
wb_cntrl_ps ,
SPIXfer_done_int_pulse,
SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty
) is
-----
begin
-----
load_wr_en_cmd <= '0';
load_wr_sr_cmd <= '0';
load_wr_sr_d0 <= '0';
load_wr_sr_d1 <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
case wb_cntrl_ps is
when WB_IDLE => load_wr_hpm <= '1';
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
when WB_WR_HPM => if (SR_5_Tx_Empty = '1')then
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
else
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
end if;
when WB_DONE => if (Rst_to_spi = '1') then
wb_cntrl_ns <= WB_IDLE;
else
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
end if;
end case;
end process WB_DUAL_CNTRL_PROCESS;
---- Quad mode command = 0x6B - QOFR Read
-- SPI_cmd <= "01101011";
-- 0101 000 100 0
---- Quad mode command = 0xEB - QIOFR Read
SPI_cmd <= "11101011";
-- 0101 100 100 0 -- QUAD_IO_FAST_RD
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';-- '0' for QOFR and '1' for QIOFR
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------------------------------------------------
--RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-5) downto 0) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_WB_GEN;
---------------------------------------------------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (load_axi_data_to_spi_clk = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (start_after_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
----------------------------
end generate WB_MEM_QUAD_MD_GEN;
-- NM 0011 0 0101 00 0<-cmd error
NM_MEM_QUAD_MD_GEN:if C_SPI_MEMORY = 2 generate
signal cmd_addr_cntr : std_logic_vector(3 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
begin
-----
--wb_hpm_done <= '1';
---- Quad mode command = 0x6B - QOFR Read - 0xEBh
--SPI_cmd <= -- "01101011";
-- 0101 1 000100 0
QUAD_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "11101011"; -- QIOFR
-- 0101 1 100100 0
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate QUAD_SPI_CMD_NM_24_GEN;
QUAD_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "11101100"; -- QIOFR_4Byte 0xECh
-- 0101 1 100100 0
end generate QUAD_SPI_CMD_NM_32_GEN;
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate NM_EN_32_ADDR_MD_GEN;
-------------------------------------
-- Data_Dir <= '0';
-- Data_Mode_1 <= '1';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '1';
-- --------------------
-- Quad_Phase <= '1';-- for NM this is 0
-- --------------------
-- Addr_Mode_1 <= '1';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '1';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-5) downto 0) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only. This is for 24 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "1000")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 6 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "1001")then -- note the differene in counter value
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (start_after_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
---------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
--------------------------------
end generate NM_MEM_QUAD_MD_GEN;
--------------------------------
SP_MEM_QUAD_MD_GEN:if C_SPI_MEMORY = 3 generate
signal cmd_addr_cntr : std_logic_vector(3 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
begin
-----
--wb_hpm_done <= '1';
---- Quad mode command = 0x6B - QOFR Read - 0xEBh
--SPI_cmd <= -- "01101011";
-- 0101 1 000100 0
QUAD_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "11101011"; -- QIOFR
-- 0101 1 100100 0
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate QUAD_SPI_CMD_NM_24_GEN;
QUAD_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "11101100"; -- QIOFR_4Byte 0xECh
-- 0101 1 100100 0
end generate QUAD_SPI_CMD_NM_32_GEN;
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate NM_EN_32_ADDR_MD_GEN;
-------------------------------------
-- Data_Dir <= '0';
-- Data_Mode_1 <= '1';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '1';
-- --------------------
-- Quad_Phase <= '1';-- for NM this is 0
-- --------------------
-- Addr_Mode_1 <= '1';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '1';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-5) downto 0) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only. This is for 24 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "0110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 6 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "0111")then -- note the differene in counter value
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (start_after_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
---------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
--------------------------------
end generate SP_MEM_QUAD_MD_GEN;
end generate QUAD_MODE_CONTROL_GEN;
WRAP_DELAY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
wrap_around_d1 <= '0';
wrap_around_d2 <= '0';
wrap_around_d3 <= '0';
--wrap_around_d4 <= '0';
else
wrap_around_d1 <= wrap_around;
wrap_around_d2 <= wrap_around_d1;
wrap_around_d3 <= wrap_around_d2;
--wrap_around_d4 <= wrap_around_d3;
end if;
end if;
end process WRAP_DELAY_P;
wrap_ack <= (not wrap_around_d2) and wrap_around_d1;
wrap_ack_1 <= (not wrap_around_d3) and wrap_around_d2;
start_after_wrap <= wrap_around_d2 and (not wrap_around_d1) and not SR_5_Tx_Empty;
store_last_b4_wrap <= wrap_around_d3 and (not wrap_around_d2);
--xsfer_start_aftr_wrap <= wrap_around_d4 and (not wrap_around_d3);
DELAY_START_AFTR_WRAP:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
start_after_wrap_d1 <= '0';
else
start_after_wrap_d1 <= start_after_wrap;
end if;
end if;
end process DELAY_START_AFTR_WRAP;
----------------------------------
TRANSFER_START_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
TRANSFER_START_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
transfer_start <= '0';
elsif(wrap_around = '1') then -- and (actual_SPIXfer_done_int = '1')then
transfer_start <= '0';
elsif(hpm_under_process_d1 = '1' and wb_hpm_done = '1')-- or
--(wr_en_under_process_d1 = '1' and wr_en_done = '1')
then
transfer_start <= '0';
elsif (load_axi_data_to_spi_clk = '1')
or (start_after_wrap_d1 = '1')
or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
transfer_start <= '1';
elsif(SR_5_Tx_Empty_int = '1') then
transfer_start <= '0';
end if;
end if;
end process TRANSFER_START_P;
end generate TRANSFER_START_24_BIT_ADDR_GEN;
TRANSFER_START_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
TRANSFER_START_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
transfer_start <= '0';
elsif(wrap_around = '1') then -- and (actual_SPIXfer_done_int = '1')then
transfer_start <= '0';
elsif(hpm_under_process_d1 = '1' and wb_hpm_done = '1') or
(wr_en_under_process_d1 = '1' and wr_en_done = '1')then
transfer_start <= '0';
elsif(load_axi_data_to_spi_clk = '1') or
(start_after_wrap_d1 = '1') or
(load_wr_hpm = '1') or
(load_wr_en = '1') then
transfer_start <= '1';
elsif(SR_5_Tx_Empty_int = '1') then
transfer_start <= '0';
end if;
end if;
end process TRANSFER_START_P;
end generate TRANSFER_START_32_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
transfer_start_pulse <= --transfer_start and (not transfer_start_d1);
--transfer_start_d2 and (not transfer_start_d3);
transfer_start and (not(transfer_start_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
--------------------------------------------
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
-- RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
-----
-- begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal. This will stop the SPI clock.
--------------------------
TRANSFER_DONE_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SPIXfer_done_int <= '0';
elsif(transfer_start_pulse = '1') then
SPIXfer_done_int <= '0';
else
if(mode_1 = '1' and mode_0 = '0')then
SPIXfer_done_int <= Count(1) and
not(Count(0));
elsif(mode_1 = '0' and mode_0 = '1')then
SPIXfer_done_int <= not(Count(0)) and
Count(2) and
Count(1);
else
SPIXfer_done_int <= --Count(COUNT_WIDTH);
Count(COUNT_WIDTH-1) and
Count(COUNT_WIDTH-2) and
Count(COUNT_WIDTH-3) and
not Count(COUNT_WIDTH-4);
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- -- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- -- data register
-- --------------------------------
-- -- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- -- due to the serial input being captured on the falling edge of the PLB
-- -- clock. this is purely required for dealing with the real SPI slave memories.
-- RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
-- begin
-- -----
-- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int_pulse_d1 = '1') then -- and (cmd_addr_sent = '1')then
-- receive_Data_int <= rx_shft_reg_mode_0011;
-- end if;
-- end if;
-- end process RECEIVE_DATA_STROBE_PROCESS;
-- end generate RECEIVE_DATA_NM_GEN;
-- -----------------------------------------------------------------------------
-- -----------------------------------------------------------------------------
-- RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
-- begin
-- -----
-- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
-- receive_Data_int <= rx_shft_reg_mode_0011;
-- end if;
-- end if;
-- end process RECEIVE_DATA_STROBE_PROCESS;
-- end generate RECEIVE_DATA_WB_GEN;
-----------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
attribute IOB : string;
attribute IOB of QSPI_SCK_T : label is "true";
attribute IOB of QSPI_IO0_T : label is "false";
attribute IOB of QSPI_IO1_T : label is "false";
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
RATIO_2_SCK_CYCLE_COUNT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (transfer_start = '0') or (store_last_b4_wrap = '1') then -- (wrap_ack_1 = '1')then
Count <= (others => '0');
elsif(SPIXfer_done_int = '1')then
Count <= (others => '0');
elsif((Count(COUNT_WIDTH) = '0') and
((CPOL_to_spi_clk and CPHA_to_spi_clk) = '0')) then
Count <= Count + 1;
elsif(transfer_start_d2 = '1') and (Count(COUNT_WIDTH) = '0') then
Count <= Count + 1;
end if;
end if;
end process RATIO_2_SCK_CYCLE_COUNT_PROCESS;
------------------------------------
SCK_SET_RESET_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
SPIXfer_done_int,
transfer_start_pulse,--,
load_axi_data_to_spi_clk,
wrap_ack_1,
load_wr_hpm,
load_wr_en
) is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1') or (load_wr_hpm = '1') or (load_wr_en = '1')then
Sync_Set <= (CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
transfer_start_pulse,
SPIXfer_done_int,
load_axi_data_to_spi_clk,
load_wr_hpm,
load_wr_en
)is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1')or(load_wr_hpm = '1') or (load_wr_en = '1') then
Sync_Reset <= not(CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
end generate SCK_SET_RESET_32_BIT_ADDR_GEN;
-------------------------------------------
SCK_SET_RESET_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
SPIXfer_done_int,
transfer_start_pulse,--,
load_axi_data_to_spi_clk,
wrap_ack_1,
load_wr_hpm--,
--load_wr_en
) is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1') or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
Sync_Set <= (CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
transfer_start_pulse,
SPIXfer_done_int,
load_axi_data_to_spi_clk,
load_wr_hpm--,
--load_wr_en
)is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1')or(load_wr_hpm = '1')
--or (load_wr_en = '1')
then
Sync_Reset <= not(CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
end generate SCK_SET_RESET_24_BIT_ADDR_GEN;
-------------------------------------------
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
RATIO_2_SCK_SET_RESET_PROCESS: process(EXT_SPI_CLK)
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if((Rst_to_spi = RESET_ACTIVE) or (Sync_Reset = '1') or
(new_tr = '0') or (wrap_ack_1 = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= (not sck_o_int);
end if;
end if;
end process RATIO_2_SCK_SET_RESET_PROCESS;
----------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
RATIO_2_DELAY_CLK: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process RATIO_2_DELAY_CLK;
------------------------------------
-- Rising egde pulse
sck_rising_edge <= sck_d2 and (not sck_d1);
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
RATIO_2_CAPT_RX_FE_MODE_00_11 : process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then -- SPIXfer_done_int_pulse_d2
if (Rst_to_spi = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_d2='0') and --(sck_rising_edge = '1') and
(Data_Dir='0') -- data direction = 0 is read mode
)then
-------
if(mode_1 = '0' and mode_0 = '0')then -- for Standard transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I ; --MISO_I;
elsif(mode_1 = '0' and mode_0 = '1')then -- for Dual transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
elsif(mode_1 = '1' and mode_0 = '0')then -- for Quad transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
-------
else
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011;
end if;
end if;
end process RATIO_2_CAPT_RX_FE_MODE_00_11;
----------------------------------
QSPI_NM_MEM_DATA_CAP_GEN: if (C_SPI_MODE = 0 and (C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 2))
or
(
( C_SPI_MODE = 1
or
C_SPI_MODE = 2
)
and
C_SPI_MEMORY = 2
)generate
--------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
--if(Load_tx_data_to_shift_reg_int = '1') then
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= Quad_Phase;--pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0')
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I ;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate QSPI_NM_MEM_DATA_CAP_GEN;
----------------------------------
QSPI_SP_MEM_DATA_CAP_GEN: if (C_SPI_MODE = 0 and (C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 3))
or
(
( C_SPI_MODE = 1
or
C_SPI_MODE = 2
)
and
C_SPI_MEMORY = 3
)generate
--------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
--if(Load_tx_data_to_shift_reg_int = '1') then
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= Quad_Phase;--pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0')
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I ;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate QSPI_SP_MEM_DATA_CAP_GEN;
----------------------------------
QSPI_WINBOND_MEM_DATA_CAP_GEN: if (
(C_SPI_MODE = 0 and (C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 1))
or
(
( C_SPI_MODE = 1
or
C_SPI_MODE = 2
)
and
C_SPI_MEMORY = 1
)) generate
-----------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0') --and
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate QSPI_WINBOND_MEM_DATA_CAP_GEN;
------------------------------------------------------
--------------------------------
XIP_STD_DUAL_MODE_WB_MEM_GEN: if (
(C_SPI_MODE = 0 or C_SPI_MODE = 1) and
(
(C_SPI_MEMORY = 1 or C_SPI_MEMORY = 0)
)
)generate
--------------------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
new_tr ,
CMD_Mode_1 ,
CMD_Mode_0 ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1 ,
wb_hpm_done ,
hpm_under_process_d1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
-------------
stop_clock <= '0';
-------------
rst_wrap_around <= '0';
-------------
case qspi_cntrl_ps is
when IDLE => if((SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SPIXfer_done_int_pulse = '1')then
if(hpm_under_process_d1 = '1')then
qspi_cntrl_ns <= HPM_DUMMY;
elsif(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when HPM_DUMMY => IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SR_5_Tx_Empty='1') then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= HPM_DUMMY;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
--stop_clock <= not SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
) or (wrap_ack_1 = '1') then
if (no_slave_selected = '1') or (wrap_ack_1 = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND =>
mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= '1';
if(no_slave_selected = '1') or
(wrap_around = '1')then
qspi_cntrl_ns <= IDLE;
stop_clock <= wrap_ack_1;
else
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when (qspi_cntrl_ps = ADDR_SEND) else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_STD_DUAL_MODE_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
XIP_STD_DUAL_MODE_NM_MEM_GEN: if ((C_SPI_MODE = 1 or C_SPI_MODE = 0) and
(C_SPI_MEMORY = 2 or C_SPI_MEMORY = 0)
)generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
---------------------
SR_5_Tx_Empty ,SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start ,
Quad_Phase ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
--------------
stop_clock <= '0';
--------------
rst_wrap_around <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if((SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_1;
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(((SR_5_Tx_Empty='1') and
(Data_Phase='0')) or (wrap_ack_1 = '1')
)then
if (no_slave_selected = '1') or (wrap_ack_1 = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and (Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND =>
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
if(no_slave_selected = '1') or (wrap_ack_1 = '1')then
stop_clock <= wrap_ack_1;
qspi_cntrl_ns <= IDLE;
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_STD_DUAL_MODE_NM_MEM_GEN;
--------------------------------
--------------------------------------------------
XIP_STD_DUAL_MODE_SP_MEM_GEN: if ((C_SPI_MODE = 1 or C_SPI_MODE = 0) and
(C_SPI_MEMORY = 3 or C_SPI_MEMORY = 0)
)generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
---------------------
SR_5_Tx_Empty ,SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
--------------
stop_clock <= '0';
--------------
rst_wrap_around <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if((SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_1;
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(((SR_5_Tx_Empty='1') and
(Data_Phase='0')) or (wrap_ack_1 = '1')
)then
if (no_slave_selected = '1') or (wrap_ack_1 = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and (Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND =>
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
if(no_slave_selected = '1') or (wrap_ack_1 = '1')then
stop_clock <= wrap_ack_1;
qspi_cntrl_ns <= IDLE;
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_STD_DUAL_MODE_SP_MEM_GEN;
--------------------------------------------------
XIP_QUAD_MODE_WB_MEM_GEN: if (
C_SPI_MODE = 2 and
C_SPI_MEMORY = 1
)
generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1 ,
wb_hpm_done ,
hpm_under_process_d1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
--------------
stop_clock <= '0';
--------------
rst_wrap_around <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if(--(CMD_decoded = '1') and
(SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
--(CMD_Error = '0') -- proceed only when there is no command error
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(hpm_under_process_d1 = '1')then
qspi_cntrl_ns <= HPM_DUMMY;
elsif(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when HPM_DUMMY => IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SR_5_Tx_Empty='1') then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= HPM_DUMMY;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only
IO3_T_control <= not (Data_Mode_1);-- active only
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
-- -- coverage off
-- -- below piece of code is for 32-bit address check, and left for future use
-- elsif(
-- (addr_cnt = "100") and -- 32 bit
-- (Addr_Bit = '1') and (Data_Phase='1')
-- )then
-- if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
-- else
-- qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
-- end if;
-- -- coverage on
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
-----------------------------------------------------------------------
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
if(no_slave_selected = '1')or (wrap_ack_1 = '1')then
stop_clock <= wrap_ack_1;
qspi_cntrl_ns <= IDLE;
else
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
------------------------------------------
end generate XIP_QUAD_MODE_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
XIP_QUAD_MODE_NM_MEM_GEN: if C_SPI_MODE = 2 and C_SPI_MEMORY = 2 generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start_d1 ,
transfer_start ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
-------------
stop_clock <= '0';
-------------
rst_wrap_around <= '0';
-------------
case qspi_cntrl_ps is
when IDLE => if(--(CMD_decoded = '1') and
(SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
--(CMD_Error = '0') -- proceed only when there is no command error
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;-- this is due to sending '1' on DQ3 line during command phase for Quad instructions only.
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and
(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and
(Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND=> mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
--if(no_slave_selected = '1') or (wrap_around = '1')then
stop_clock <= wrap_ack_1 or SR_5_Tx_Empty;
qspi_cntrl_ns <= IDLE;
--else
-- stop_clock <= SR_5_Tx_Empty;
-- qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
--end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
--else
-- stop_clock <= '0';
-- qspi_cntrl_ns <= DATA_RECEIVE;
--end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_QUAD_MODE_NM_MEM_GEN;
---------------------------------------
XIP_QUAD_MODE_SP_MEM_GEN: if C_SPI_MODE = 2 and C_SPI_MEMORY = 3 generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start_d1 ,
transfer_start ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
-------------
stop_clock <= '0';
-------------
rst_wrap_around <= '0';
-------------
case qspi_cntrl_ps is
when IDLE => if(--(CMD_decoded = '1') and
(SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
--(CMD_Error = '0') -- proceed only when there is no command error
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;-- this is due to sending '1' on DQ3 line during command phase for Quad instructions only.
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and
(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and
(Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND=> mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
--if(no_slave_selected = '1') or (wrap_around = '1')then
stop_clock <= wrap_ack_1 or SR_5_Tx_Empty;
qspi_cntrl_ns <= IDLE;
--else
-- stop_clock <= SR_5_Tx_Empty;
-- qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
--end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
--else
-- stop_clock <= '0';
-- qspi_cntrl_ns <= DATA_RECEIVE;
--end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_QUAD_MODE_SP_MEM_GEN;
---------------------------------------
IO0_O <= Serial_Dout_0;
IO1_O <= Serial_Dout_1;
IO2_O <= Serial_Dout_2;
IO3_O <= Serial_Dout_3;
--SCK_O <= SCK_O_reg;
--SS_O <= SS_to_spi_clk;
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
SS_tri_state_en_control <= '0' when
(
-- (SR_5_Tx_Empty_d1 = '0') and -- Length counter is not exited
(transfer_start = '1') and
(wrap_ack = '0') and -- no wrap around
--(MODF_strobe_int ='0') -- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
)
else
'1';
--QSPI_SS_T: tri-state register for SS,ideal state-deactive
QSPI_SS_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => EXT_SPI_CLK,
D => SS_tri_state_en_control
);
--QSPI_SCK_T : Tri-state register for SCK_T, ideal state-deactive
SCK_tri_state_en_control <= '0' when
(
-- (SR_5_Tx_Empty = '0') and -- Length counter is not exited
(transfer_start = '1') and -- 4/14/2013
(wrap_ack = '0') and -- no wrap around-- (pr_state_non_idle = '1') and -- CR#619275 - this is commented to operate the mode 3 with SW flow
--(MODF_strobe_int ='0') -- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
QSPI_SCK_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => EXT_SPI_CLK,
D => SCK_tri_state_en_control
);
IO0_tri_state_en_control <= '0' when
(
(IO0_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO0_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO0_T, -- MOSI_T,
C => EXT_SPI_CLK,
D => IO0_tri_state_en_control -- master_tri_state_en_control
);
IO1_tri_state_en_control <= '0' when
(
(IO1_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO1_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO1_T, -- MISO_T,
C => EXT_SPI_CLK,
D => IO1_tri_state_en_control
);
-------------------------------------------------------------------------------
QSPI_NO_MODE_2_T_CONTROL: if C_SPI_MODE = 1 or C_SPI_MODE = 0 generate
----------------------
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '1';
IO3_tri_state_en_control <= '1';
IO2_T <= '1';
IO3_T <= '1';
--------------------------------------
end generate QSPI_NO_MODE_2_T_CONTROL;
--------------------------------------
-------------------------------------------------------------------------------
QSPI_MODE_2_T_CONTROL: if C_SPI_MODE = 2 generate
----------------------
attribute IOB : string;
attribute IOB of QSPI_IO2_T : label is "false";
attribute IOB of QSPI_IO3_T : label is "false";
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '0' when
(
(IO2_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO2_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO2_T, -- MOSI_T,
C => EXT_SPI_CLK,
D => IO2_tri_state_en_control -- master_tri_state_en_control
);
--------------------------------------
IO3_tri_state_en_control <= '0' when
(
(IO3_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO3_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO3_T, -- MISO_T,
C => EXT_SPI_CLK,
D => IO3_tri_state_en_control
);
--------------------------------------
end generate QSPI_MODE_2_T_CONTROL;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- QSPI_SPISEL: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
QSPI_SPISEL: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => EXT_SPI_CLK,
D => SPISEL
);
-- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-----------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(EXT_SPI_CLK)
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
spisel_d1 <= '1';
else
spisel_d1 <= SPISEL_sync;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if((Rst_to_spi = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif(
(SPISEL_sync = '0') and
(Allow_MODF_Strobe = '1')
) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
SS_O_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SS_O <= (others => '1');
elsif(wrap_ack_1 = '1') or (store_last_b4_wrap = '1') or (SR_5_Tx_Empty ='1') then
SS_O <= (others => '1');
elsif(hpm_under_process_d1 = '1') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= (SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
elsif(store_last_b4_wrap = '0') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= not(SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
end if;
end if;
end process SELECT_OUT_PROCESS;
----------------------------
end generate SS_O_24_BIT_ADDR_GEN;
----------------------------------
SS_O_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SS_O <= (others => '1');
elsif(wrap_ack_1 = '1') or (store_last_b4_wrap = '1') or (transfer_start = '0' and SR_5_Tx_Empty_d1='1') then
SS_O <= (others => '1');
elsif(hpm_under_process = '1') or (wr_en_under_process = '1') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= (SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
elsif(store_last_b4_wrap = '0') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= not(SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
end if;
end if;
end process SELECT_OUT_PROCESS;
----------------------------
end generate SS_O_32_BIT_ADDR_GEN;
----------------------------------
no_slave_selected <= and_reduce(SS_to_spi_clk((C_NUM_SS_BITS-1) downto 0));
-------------------------------------------------------------------------------
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(--Mst_N_Slv ,-- in master mode
sck_o_int ,-- value driven on sck_int
CPOL_to_spi_clk ,-- CPOL mode thr SPICR
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH),
pr_state_non_idle -- State machine is in Non-idle state
)is
begin
if((transfer_start = '1') and
--(transfer_start_d1 = '1') and
--(Count(COUNT_WIDTH) = '0')and
(pr_state_non_idle = '1')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL_to_spi_clk;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
slave_mode <= '0'; -- create the reset condition by inverting the mst_n_slv signal. 1 - master mode, 0 - slave mode.
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk). during slave mode no clock should be generated from the core.
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => EXT_SPI_CLK, -- Clock input
CE => '1', -- Clock enable input
R => Rst_to_spi, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-------------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int ,
CPOL_to_spi_clk ,
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH)
)is
begin
if((transfer_start = '1') -- and
--(transfer_start_d1 = '1') --and
--(Count(COUNT_WIDTH) = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL_to_spi_clk;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Rst_to_spi = RESET_ACTIVE)
) then
SCK_O_reg <= '0';
elsif((pr_state_non_idle='0')-- or -- dont allow sck to go out when
--(Mst_N_Slv = '0')
)then -- SM is in IDLE state or core in slave mode
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
--end generate RATIO_NOT_EQUAL_4_GENERATE;
end generate RATIO_OF_2_GENERATE;
end architecture imp;
-------------------------------------------------------------------------------
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:54:20 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_lms_pcore_0_0_sim_netlist.vhdl
-- Design : ip_design_lms_pcore_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_LMS is
port (
mul_temp_16 : out STD_LOGIC_VECTOR ( 15 downto 0 );
filter_sum : out STD_LOGIC_VECTOR ( 15 downto 0 );
\write_reg_x_k_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
cop_dut_enable : in STD_LOGIC;
IPCORE_CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\write_reg_d_k_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
DI : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 14 downto 0 );
\write_reg_d_k_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_LMS;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_LMS is
signal \ARG__0_i_1_n_0\ : STD_LOGIC;
signal \ARG__0_n_100\ : STD_LOGIC;
signal \ARG__0_n_101\ : STD_LOGIC;
signal \ARG__0_n_102\ : STD_LOGIC;
signal \ARG__0_n_103\ : STD_LOGIC;
signal \ARG__0_n_104\ : STD_LOGIC;
signal \ARG__0_n_105\ : STD_LOGIC;
signal \ARG__0_n_92\ : STD_LOGIC;
signal \ARG__0_n_93\ : STD_LOGIC;
signal \ARG__0_n_94\ : STD_LOGIC;
signal \ARG__0_n_95\ : STD_LOGIC;
signal \ARG__0_n_96\ : STD_LOGIC;
signal \ARG__0_n_97\ : STD_LOGIC;
signal \ARG__0_n_98\ : STD_LOGIC;
signal \ARG__0_n_99\ : STD_LOGIC;
signal \ARG__10_i_1_n_0\ : STD_LOGIC;
signal \ARG__10_n_100\ : STD_LOGIC;
signal \ARG__10_n_101\ : STD_LOGIC;
signal \ARG__10_n_102\ : STD_LOGIC;
signal \ARG__10_n_103\ : STD_LOGIC;
signal \ARG__10_n_104\ : STD_LOGIC;
signal \ARG__10_n_105\ : STD_LOGIC;
signal \ARG__10_n_92\ : STD_LOGIC;
signal \ARG__10_n_93\ : STD_LOGIC;
signal \ARG__10_n_94\ : STD_LOGIC;
signal \ARG__10_n_95\ : STD_LOGIC;
signal \ARG__10_n_96\ : STD_LOGIC;
signal \ARG__10_n_97\ : STD_LOGIC;
signal \ARG__10_n_98\ : STD_LOGIC;
signal \ARG__10_n_99\ : STD_LOGIC;
signal \ARG__11_i_1_n_0\ : STD_LOGIC;
signal \ARG__11_n_100\ : STD_LOGIC;
signal \ARG__11_n_101\ : STD_LOGIC;
signal \ARG__11_n_102\ : STD_LOGIC;
signal \ARG__11_n_103\ : STD_LOGIC;
signal \ARG__11_n_104\ : STD_LOGIC;
signal \ARG__11_n_105\ : STD_LOGIC;
signal \ARG__11_n_76\ : STD_LOGIC;
signal \ARG__11_n_77\ : STD_LOGIC;
signal \ARG__11_n_78\ : STD_LOGIC;
signal \ARG__11_n_79\ : STD_LOGIC;
signal \ARG__11_n_80\ : STD_LOGIC;
signal \ARG__11_n_81\ : STD_LOGIC;
signal \ARG__11_n_82\ : STD_LOGIC;
signal \ARG__11_n_83\ : STD_LOGIC;
signal \ARG__11_n_84\ : STD_LOGIC;
signal \ARG__11_n_85\ : STD_LOGIC;
signal \ARG__11_n_86\ : STD_LOGIC;
signal \ARG__11_n_87\ : STD_LOGIC;
signal \ARG__11_n_88\ : STD_LOGIC;
signal \ARG__11_n_89\ : STD_LOGIC;
signal \ARG__11_n_90\ : STD_LOGIC;
signal \ARG__11_n_91\ : STD_LOGIC;
signal \ARG__11_n_92\ : STD_LOGIC;
signal \ARG__11_n_93\ : STD_LOGIC;
signal \ARG__11_n_94\ : STD_LOGIC;
signal \ARG__11_n_95\ : STD_LOGIC;
signal \ARG__11_n_96\ : STD_LOGIC;
signal \ARG__11_n_97\ : STD_LOGIC;
signal \ARG__11_n_98\ : STD_LOGIC;
signal \ARG__11_n_99\ : STD_LOGIC;
signal \ARG__12_i_1_n_0\ : STD_LOGIC;
signal \ARG__12_n_100\ : STD_LOGIC;
signal \ARG__12_n_101\ : STD_LOGIC;
signal \ARG__12_n_102\ : STD_LOGIC;
signal \ARG__12_n_103\ : STD_LOGIC;
signal \ARG__12_n_104\ : STD_LOGIC;
signal \ARG__12_n_105\ : STD_LOGIC;
signal \ARG__12_n_92\ : STD_LOGIC;
signal \ARG__12_n_93\ : STD_LOGIC;
signal \ARG__12_n_94\ : STD_LOGIC;
signal \ARG__12_n_95\ : STD_LOGIC;
signal \ARG__12_n_96\ : STD_LOGIC;
signal \ARG__12_n_97\ : STD_LOGIC;
signal \ARG__12_n_98\ : STD_LOGIC;
signal \ARG__12_n_99\ : STD_LOGIC;
signal \ARG__13_i_1_n_0\ : STD_LOGIC;
signal \ARG__13_n_100\ : STD_LOGIC;
signal \ARG__13_n_101\ : STD_LOGIC;
signal \ARG__13_n_102\ : STD_LOGIC;
signal \ARG__13_n_103\ : STD_LOGIC;
signal \ARG__13_n_104\ : STD_LOGIC;
signal \ARG__13_n_105\ : STD_LOGIC;
signal \ARG__13_n_76\ : STD_LOGIC;
signal \ARG__13_n_77\ : STD_LOGIC;
signal \ARG__13_n_78\ : STD_LOGIC;
signal \ARG__13_n_79\ : STD_LOGIC;
signal \ARG__13_n_80\ : STD_LOGIC;
signal \ARG__13_n_81\ : STD_LOGIC;
signal \ARG__13_n_82\ : STD_LOGIC;
signal \ARG__13_n_83\ : STD_LOGIC;
signal \ARG__13_n_84\ : STD_LOGIC;
signal \ARG__13_n_85\ : STD_LOGIC;
signal \ARG__13_n_86\ : STD_LOGIC;
signal \ARG__13_n_87\ : STD_LOGIC;
signal \ARG__13_n_88\ : STD_LOGIC;
signal \ARG__13_n_89\ : STD_LOGIC;
signal \ARG__13_n_90\ : STD_LOGIC;
signal \ARG__13_n_91\ : STD_LOGIC;
signal \ARG__13_n_92\ : STD_LOGIC;
signal \ARG__13_n_93\ : STD_LOGIC;
signal \ARG__13_n_94\ : STD_LOGIC;
signal \ARG__13_n_95\ : STD_LOGIC;
signal \ARG__13_n_96\ : STD_LOGIC;
signal \ARG__13_n_97\ : STD_LOGIC;
signal \ARG__13_n_98\ : STD_LOGIC;
signal \ARG__13_n_99\ : STD_LOGIC;
signal \ARG__14_i_1_n_0\ : STD_LOGIC;
signal \ARG__14_n_100\ : STD_LOGIC;
signal \ARG__14_n_101\ : STD_LOGIC;
signal \ARG__14_n_102\ : STD_LOGIC;
signal \ARG__14_n_103\ : STD_LOGIC;
signal \ARG__14_n_104\ : STD_LOGIC;
signal \ARG__14_n_105\ : STD_LOGIC;
signal \ARG__14_n_92\ : STD_LOGIC;
signal \ARG__14_n_93\ : STD_LOGIC;
signal \ARG__14_n_94\ : STD_LOGIC;
signal \ARG__14_n_95\ : STD_LOGIC;
signal \ARG__14_n_96\ : STD_LOGIC;
signal \ARG__14_n_97\ : STD_LOGIC;
signal \ARG__14_n_98\ : STD_LOGIC;
signal \ARG__14_n_99\ : STD_LOGIC;
signal \ARG__15_i_1_n_0\ : STD_LOGIC;
signal \ARG__15_n_100\ : STD_LOGIC;
signal \ARG__15_n_101\ : STD_LOGIC;
signal \ARG__15_n_102\ : STD_LOGIC;
signal \ARG__15_n_103\ : STD_LOGIC;
signal \ARG__15_n_104\ : STD_LOGIC;
signal \ARG__15_n_105\ : STD_LOGIC;
signal \ARG__15_n_76\ : STD_LOGIC;
signal \ARG__15_n_77\ : STD_LOGIC;
signal \ARG__15_n_78\ : STD_LOGIC;
signal \ARG__15_n_79\ : STD_LOGIC;
signal \ARG__15_n_80\ : STD_LOGIC;
signal \ARG__15_n_81\ : STD_LOGIC;
signal \ARG__15_n_82\ : STD_LOGIC;
signal \ARG__15_n_83\ : STD_LOGIC;
signal \ARG__15_n_84\ : STD_LOGIC;
signal \ARG__15_n_85\ : STD_LOGIC;
signal \ARG__15_n_86\ : STD_LOGIC;
signal \ARG__15_n_87\ : STD_LOGIC;
signal \ARG__15_n_88\ : STD_LOGIC;
signal \ARG__15_n_89\ : STD_LOGIC;
signal \ARG__15_n_90\ : STD_LOGIC;
signal \ARG__15_n_91\ : STD_LOGIC;
signal \ARG__15_n_92\ : STD_LOGIC;
signal \ARG__15_n_93\ : STD_LOGIC;
signal \ARG__15_n_94\ : STD_LOGIC;
signal \ARG__15_n_95\ : STD_LOGIC;
signal \ARG__15_n_96\ : STD_LOGIC;
signal \ARG__15_n_97\ : STD_LOGIC;
signal \ARG__15_n_98\ : STD_LOGIC;
signal \ARG__15_n_99\ : STD_LOGIC;
signal \ARG__16_i_1_n_0\ : STD_LOGIC;
signal \ARG__16_n_100\ : STD_LOGIC;
signal \ARG__16_n_101\ : STD_LOGIC;
signal \ARG__16_n_102\ : STD_LOGIC;
signal \ARG__16_n_103\ : STD_LOGIC;
signal \ARG__16_n_104\ : STD_LOGIC;
signal \ARG__16_n_105\ : STD_LOGIC;
signal \ARG__16_n_92\ : STD_LOGIC;
signal \ARG__16_n_93\ : STD_LOGIC;
signal \ARG__16_n_94\ : STD_LOGIC;
signal \ARG__16_n_95\ : STD_LOGIC;
signal \ARG__16_n_96\ : STD_LOGIC;
signal \ARG__16_n_97\ : STD_LOGIC;
signal \ARG__16_n_98\ : STD_LOGIC;
signal \ARG__16_n_99\ : STD_LOGIC;
signal \ARG__17_i_1_n_0\ : STD_LOGIC;
signal \ARG__17_n_100\ : STD_LOGIC;
signal \ARG__17_n_101\ : STD_LOGIC;
signal \ARG__17_n_102\ : STD_LOGIC;
signal \ARG__17_n_103\ : STD_LOGIC;
signal \ARG__17_n_104\ : STD_LOGIC;
signal \ARG__17_n_105\ : STD_LOGIC;
signal \ARG__17_n_76\ : STD_LOGIC;
signal \ARG__17_n_77\ : STD_LOGIC;
signal \ARG__17_n_78\ : STD_LOGIC;
signal \ARG__17_n_79\ : STD_LOGIC;
signal \ARG__17_n_80\ : STD_LOGIC;
signal \ARG__17_n_81\ : STD_LOGIC;
signal \ARG__17_n_82\ : STD_LOGIC;
signal \ARG__17_n_83\ : STD_LOGIC;
signal \ARG__17_n_84\ : STD_LOGIC;
signal \ARG__17_n_85\ : STD_LOGIC;
signal \ARG__17_n_86\ : STD_LOGIC;
signal \ARG__17_n_87\ : STD_LOGIC;
signal \ARG__17_n_88\ : STD_LOGIC;
signal \ARG__17_n_89\ : STD_LOGIC;
signal \ARG__17_n_90\ : STD_LOGIC;
signal \ARG__17_n_91\ : STD_LOGIC;
signal \ARG__17_n_92\ : STD_LOGIC;
signal \ARG__17_n_93\ : STD_LOGIC;
signal \ARG__17_n_94\ : STD_LOGIC;
signal \ARG__17_n_95\ : STD_LOGIC;
signal \ARG__17_n_96\ : STD_LOGIC;
signal \ARG__17_n_97\ : STD_LOGIC;
signal \ARG__17_n_98\ : STD_LOGIC;
signal \ARG__17_n_99\ : STD_LOGIC;
signal \ARG__18_i_1_n_0\ : STD_LOGIC;
signal \ARG__18_n_100\ : STD_LOGIC;
signal \ARG__18_n_101\ : STD_LOGIC;
signal \ARG__18_n_102\ : STD_LOGIC;
signal \ARG__18_n_103\ : STD_LOGIC;
signal \ARG__18_n_104\ : STD_LOGIC;
signal \ARG__18_n_105\ : STD_LOGIC;
signal \ARG__18_n_92\ : STD_LOGIC;
signal \ARG__18_n_93\ : STD_LOGIC;
signal \ARG__18_n_94\ : STD_LOGIC;
signal \ARG__18_n_95\ : STD_LOGIC;
signal \ARG__18_n_96\ : STD_LOGIC;
signal \ARG__18_n_97\ : STD_LOGIC;
signal \ARG__18_n_98\ : STD_LOGIC;
signal \ARG__18_n_99\ : STD_LOGIC;
signal \ARG__19_i_1_n_0\ : STD_LOGIC;
signal \ARG__19_n_100\ : STD_LOGIC;
signal \ARG__19_n_101\ : STD_LOGIC;
signal \ARG__19_n_102\ : STD_LOGIC;
signal \ARG__19_n_103\ : STD_LOGIC;
signal \ARG__19_n_104\ : STD_LOGIC;
signal \ARG__19_n_105\ : STD_LOGIC;
signal \ARG__19_n_76\ : STD_LOGIC;
signal \ARG__19_n_77\ : STD_LOGIC;
signal \ARG__19_n_78\ : STD_LOGIC;
signal \ARG__19_n_79\ : STD_LOGIC;
signal \ARG__19_n_80\ : STD_LOGIC;
signal \ARG__19_n_81\ : STD_LOGIC;
signal \ARG__19_n_82\ : STD_LOGIC;
signal \ARG__19_n_83\ : STD_LOGIC;
signal \ARG__19_n_84\ : STD_LOGIC;
signal \ARG__19_n_85\ : STD_LOGIC;
signal \ARG__19_n_86\ : STD_LOGIC;
signal \ARG__19_n_87\ : STD_LOGIC;
signal \ARG__19_n_88\ : STD_LOGIC;
signal \ARG__19_n_89\ : STD_LOGIC;
signal \ARG__19_n_90\ : STD_LOGIC;
signal \ARG__19_n_91\ : STD_LOGIC;
signal \ARG__19_n_92\ : STD_LOGIC;
signal \ARG__19_n_93\ : STD_LOGIC;
signal \ARG__19_n_94\ : STD_LOGIC;
signal \ARG__19_n_95\ : STD_LOGIC;
signal \ARG__19_n_96\ : STD_LOGIC;
signal \ARG__19_n_97\ : STD_LOGIC;
signal \ARG__19_n_98\ : STD_LOGIC;
signal \ARG__19_n_99\ : STD_LOGIC;
signal \ARG__1_i_1_n_0\ : STD_LOGIC;
signal \ARG__1_n_100\ : STD_LOGIC;
signal \ARG__1_n_101\ : STD_LOGIC;
signal \ARG__1_n_102\ : STD_LOGIC;
signal \ARG__1_n_103\ : STD_LOGIC;
signal \ARG__1_n_104\ : STD_LOGIC;
signal \ARG__1_n_105\ : STD_LOGIC;
signal \ARG__1_n_76\ : STD_LOGIC;
signal \ARG__1_n_77\ : STD_LOGIC;
signal \ARG__1_n_78\ : STD_LOGIC;
signal \ARG__1_n_79\ : STD_LOGIC;
signal \ARG__1_n_80\ : STD_LOGIC;
signal \ARG__1_n_81\ : STD_LOGIC;
signal \ARG__1_n_82\ : STD_LOGIC;
signal \ARG__1_n_83\ : STD_LOGIC;
signal \ARG__1_n_84\ : STD_LOGIC;
signal \ARG__1_n_85\ : STD_LOGIC;
signal \ARG__1_n_86\ : STD_LOGIC;
signal \ARG__1_n_87\ : STD_LOGIC;
signal \ARG__1_n_88\ : STD_LOGIC;
signal \ARG__1_n_89\ : STD_LOGIC;
signal \ARG__1_n_90\ : STD_LOGIC;
signal \ARG__1_n_91\ : STD_LOGIC;
signal \ARG__1_n_92\ : STD_LOGIC;
signal \ARG__1_n_93\ : STD_LOGIC;
signal \ARG__1_n_94\ : STD_LOGIC;
signal \ARG__1_n_95\ : STD_LOGIC;
signal \ARG__1_n_96\ : STD_LOGIC;
signal \ARG__1_n_97\ : STD_LOGIC;
signal \ARG__1_n_98\ : STD_LOGIC;
signal \ARG__1_n_99\ : STD_LOGIC;
signal \ARG__20_i_1_n_0\ : STD_LOGIC;
signal \ARG__20_n_100\ : STD_LOGIC;
signal \ARG__20_n_101\ : STD_LOGIC;
signal \ARG__20_n_102\ : STD_LOGIC;
signal \ARG__20_n_103\ : STD_LOGIC;
signal \ARG__20_n_104\ : STD_LOGIC;
signal \ARG__20_n_105\ : STD_LOGIC;
signal \ARG__20_n_92\ : STD_LOGIC;
signal \ARG__20_n_93\ : STD_LOGIC;
signal \ARG__20_n_94\ : STD_LOGIC;
signal \ARG__20_n_95\ : STD_LOGIC;
signal \ARG__20_n_96\ : STD_LOGIC;
signal \ARG__20_n_97\ : STD_LOGIC;
signal \ARG__20_n_98\ : STD_LOGIC;
signal \ARG__20_n_99\ : STD_LOGIC;
signal \ARG__21_i_1_n_0\ : STD_LOGIC;
signal \ARG__21_n_100\ : STD_LOGIC;
signal \ARG__21_n_101\ : STD_LOGIC;
signal \ARG__21_n_102\ : STD_LOGIC;
signal \ARG__21_n_103\ : STD_LOGIC;
signal \ARG__21_n_104\ : STD_LOGIC;
signal \ARG__21_n_105\ : STD_LOGIC;
signal \ARG__21_n_76\ : STD_LOGIC;
signal \ARG__21_n_77\ : STD_LOGIC;
signal \ARG__21_n_78\ : STD_LOGIC;
signal \ARG__21_n_79\ : STD_LOGIC;
signal \ARG__21_n_80\ : STD_LOGIC;
signal \ARG__21_n_81\ : STD_LOGIC;
signal \ARG__21_n_82\ : STD_LOGIC;
signal \ARG__21_n_83\ : STD_LOGIC;
signal \ARG__21_n_84\ : STD_LOGIC;
signal \ARG__21_n_85\ : STD_LOGIC;
signal \ARG__21_n_86\ : STD_LOGIC;
signal \ARG__21_n_87\ : STD_LOGIC;
signal \ARG__21_n_88\ : STD_LOGIC;
signal \ARG__21_n_89\ : STD_LOGIC;
signal \ARG__21_n_90\ : STD_LOGIC;
signal \ARG__21_n_91\ : STD_LOGIC;
signal \ARG__21_n_92\ : STD_LOGIC;
signal \ARG__21_n_93\ : STD_LOGIC;
signal \ARG__21_n_94\ : STD_LOGIC;
signal \ARG__21_n_95\ : STD_LOGIC;
signal \ARG__21_n_96\ : STD_LOGIC;
signal \ARG__21_n_97\ : STD_LOGIC;
signal \ARG__21_n_98\ : STD_LOGIC;
signal \ARG__21_n_99\ : STD_LOGIC;
signal \ARG__22_i_1_n_0\ : STD_LOGIC;
signal \ARG__22_n_100\ : STD_LOGIC;
signal \ARG__22_n_101\ : STD_LOGIC;
signal \ARG__22_n_102\ : STD_LOGIC;
signal \ARG__22_n_103\ : STD_LOGIC;
signal \ARG__22_n_104\ : STD_LOGIC;
signal \ARG__22_n_105\ : STD_LOGIC;
signal \ARG__22_n_92\ : STD_LOGIC;
signal \ARG__22_n_93\ : STD_LOGIC;
signal \ARG__22_n_94\ : STD_LOGIC;
signal \ARG__22_n_95\ : STD_LOGIC;
signal \ARG__22_n_96\ : STD_LOGIC;
signal \ARG__22_n_97\ : STD_LOGIC;
signal \ARG__22_n_98\ : STD_LOGIC;
signal \ARG__22_n_99\ : STD_LOGIC;
signal \ARG__23_i_1_n_0\ : STD_LOGIC;
signal \ARG__23_n_100\ : STD_LOGIC;
signal \ARG__23_n_101\ : STD_LOGIC;
signal \ARG__23_n_102\ : STD_LOGIC;
signal \ARG__23_n_103\ : STD_LOGIC;
signal \ARG__23_n_104\ : STD_LOGIC;
signal \ARG__23_n_105\ : STD_LOGIC;
signal \ARG__23_n_76\ : STD_LOGIC;
signal \ARG__23_n_77\ : STD_LOGIC;
signal \ARG__23_n_78\ : STD_LOGIC;
signal \ARG__23_n_79\ : STD_LOGIC;
signal \ARG__23_n_80\ : STD_LOGIC;
signal \ARG__23_n_81\ : STD_LOGIC;
signal \ARG__23_n_82\ : STD_LOGIC;
signal \ARG__23_n_83\ : STD_LOGIC;
signal \ARG__23_n_84\ : STD_LOGIC;
signal \ARG__23_n_85\ : STD_LOGIC;
signal \ARG__23_n_86\ : STD_LOGIC;
signal \ARG__23_n_87\ : STD_LOGIC;
signal \ARG__23_n_88\ : STD_LOGIC;
signal \ARG__23_n_89\ : STD_LOGIC;
signal \ARG__23_n_90\ : STD_LOGIC;
signal \ARG__23_n_91\ : STD_LOGIC;
signal \ARG__23_n_92\ : STD_LOGIC;
signal \ARG__23_n_93\ : STD_LOGIC;
signal \ARG__23_n_94\ : STD_LOGIC;
signal \ARG__23_n_95\ : STD_LOGIC;
signal \ARG__23_n_96\ : STD_LOGIC;
signal \ARG__23_n_97\ : STD_LOGIC;
signal \ARG__23_n_98\ : STD_LOGIC;
signal \ARG__23_n_99\ : STD_LOGIC;
signal \ARG__24_i_1_n_0\ : STD_LOGIC;
signal \ARG__24_n_100\ : STD_LOGIC;
signal \ARG__24_n_101\ : STD_LOGIC;
signal \ARG__24_n_102\ : STD_LOGIC;
signal \ARG__24_n_103\ : STD_LOGIC;
signal \ARG__24_n_104\ : STD_LOGIC;
signal \ARG__24_n_105\ : STD_LOGIC;
signal \ARG__24_n_92\ : STD_LOGIC;
signal \ARG__24_n_93\ : STD_LOGIC;
signal \ARG__24_n_94\ : STD_LOGIC;
signal \ARG__24_n_95\ : STD_LOGIC;
signal \ARG__24_n_96\ : STD_LOGIC;
signal \ARG__24_n_97\ : STD_LOGIC;
signal \ARG__24_n_98\ : STD_LOGIC;
signal \ARG__24_n_99\ : STD_LOGIC;
signal \ARG__25_i_1_n_0\ : STD_LOGIC;
signal \ARG__25_n_100\ : STD_LOGIC;
signal \ARG__25_n_101\ : STD_LOGIC;
signal \ARG__25_n_102\ : STD_LOGIC;
signal \ARG__25_n_103\ : STD_LOGIC;
signal \ARG__25_n_104\ : STD_LOGIC;
signal \ARG__25_n_105\ : STD_LOGIC;
signal \ARG__25_n_76\ : STD_LOGIC;
signal \ARG__25_n_77\ : STD_LOGIC;
signal \ARG__25_n_78\ : STD_LOGIC;
signal \ARG__25_n_79\ : STD_LOGIC;
signal \ARG__25_n_80\ : STD_LOGIC;
signal \ARG__25_n_81\ : STD_LOGIC;
signal \ARG__25_n_82\ : STD_LOGIC;
signal \ARG__25_n_83\ : STD_LOGIC;
signal \ARG__25_n_84\ : STD_LOGIC;
signal \ARG__25_n_85\ : STD_LOGIC;
signal \ARG__25_n_86\ : STD_LOGIC;
signal \ARG__25_n_87\ : STD_LOGIC;
signal \ARG__25_n_88\ : STD_LOGIC;
signal \ARG__25_n_89\ : STD_LOGIC;
signal \ARG__25_n_90\ : STD_LOGIC;
signal \ARG__25_n_91\ : STD_LOGIC;
signal \ARG__25_n_92\ : STD_LOGIC;
signal \ARG__25_n_93\ : STD_LOGIC;
signal \ARG__25_n_94\ : STD_LOGIC;
signal \ARG__25_n_95\ : STD_LOGIC;
signal \ARG__25_n_96\ : STD_LOGIC;
signal \ARG__25_n_97\ : STD_LOGIC;
signal \ARG__25_n_98\ : STD_LOGIC;
signal \ARG__25_n_99\ : STD_LOGIC;
signal \ARG__26_i_1_n_0\ : STD_LOGIC;
signal \ARG__26_n_100\ : STD_LOGIC;
signal \ARG__26_n_101\ : STD_LOGIC;
signal \ARG__26_n_102\ : STD_LOGIC;
signal \ARG__26_n_103\ : STD_LOGIC;
signal \ARG__26_n_104\ : STD_LOGIC;
signal \ARG__26_n_105\ : STD_LOGIC;
signal \ARG__26_n_92\ : STD_LOGIC;
signal \ARG__26_n_93\ : STD_LOGIC;
signal \ARG__26_n_94\ : STD_LOGIC;
signal \ARG__26_n_95\ : STD_LOGIC;
signal \ARG__26_n_96\ : STD_LOGIC;
signal \ARG__26_n_97\ : STD_LOGIC;
signal \ARG__26_n_98\ : STD_LOGIC;
signal \ARG__26_n_99\ : STD_LOGIC;
signal \ARG__27_i_1_n_0\ : STD_LOGIC;
signal \ARG__27_n_100\ : STD_LOGIC;
signal \ARG__27_n_101\ : STD_LOGIC;
signal \ARG__27_n_102\ : STD_LOGIC;
signal \ARG__27_n_103\ : STD_LOGIC;
signal \ARG__27_n_104\ : STD_LOGIC;
signal \ARG__27_n_105\ : STD_LOGIC;
signal \ARG__27_n_76\ : STD_LOGIC;
signal \ARG__27_n_77\ : STD_LOGIC;
signal \ARG__27_n_78\ : STD_LOGIC;
signal \ARG__27_n_79\ : STD_LOGIC;
signal \ARG__27_n_80\ : STD_LOGIC;
signal \ARG__27_n_81\ : STD_LOGIC;
signal \ARG__27_n_82\ : STD_LOGIC;
signal \ARG__27_n_83\ : STD_LOGIC;
signal \ARG__27_n_84\ : STD_LOGIC;
signal \ARG__27_n_85\ : STD_LOGIC;
signal \ARG__27_n_86\ : STD_LOGIC;
signal \ARG__27_n_87\ : STD_LOGIC;
signal \ARG__27_n_88\ : STD_LOGIC;
signal \ARG__27_n_89\ : STD_LOGIC;
signal \ARG__27_n_90\ : STD_LOGIC;
signal \ARG__27_n_91\ : STD_LOGIC;
signal \ARG__27_n_92\ : STD_LOGIC;
signal \ARG__27_n_93\ : STD_LOGIC;
signal \ARG__27_n_94\ : STD_LOGIC;
signal \ARG__27_n_95\ : STD_LOGIC;
signal \ARG__27_n_96\ : STD_LOGIC;
signal \ARG__27_n_97\ : STD_LOGIC;
signal \ARG__27_n_98\ : STD_LOGIC;
signal \ARG__27_n_99\ : STD_LOGIC;
signal \ARG__28_i_1_n_0\ : STD_LOGIC;
signal \ARG__28_n_100\ : STD_LOGIC;
signal \ARG__28_n_101\ : STD_LOGIC;
signal \ARG__28_n_102\ : STD_LOGIC;
signal \ARG__28_n_103\ : STD_LOGIC;
signal \ARG__28_n_104\ : STD_LOGIC;
signal \ARG__28_n_105\ : STD_LOGIC;
signal \ARG__28_n_92\ : STD_LOGIC;
signal \ARG__28_n_93\ : STD_LOGIC;
signal \ARG__28_n_94\ : STD_LOGIC;
signal \ARG__28_n_95\ : STD_LOGIC;
signal \ARG__28_n_96\ : STD_LOGIC;
signal \ARG__28_n_97\ : STD_LOGIC;
signal \ARG__28_n_98\ : STD_LOGIC;
signal \ARG__28_n_99\ : STD_LOGIC;
signal \ARG__29_i_1_n_0\ : STD_LOGIC;
signal \ARG__29_n_100\ : STD_LOGIC;
signal \ARG__29_n_101\ : STD_LOGIC;
signal \ARG__29_n_102\ : STD_LOGIC;
signal \ARG__29_n_103\ : STD_LOGIC;
signal \ARG__29_n_104\ : STD_LOGIC;
signal \ARG__29_n_105\ : STD_LOGIC;
signal \ARG__29_n_76\ : STD_LOGIC;
signal \ARG__29_n_77\ : STD_LOGIC;
signal \ARG__29_n_78\ : STD_LOGIC;
signal \ARG__29_n_79\ : STD_LOGIC;
signal \ARG__29_n_80\ : STD_LOGIC;
signal \ARG__29_n_81\ : STD_LOGIC;
signal \ARG__29_n_82\ : STD_LOGIC;
signal \ARG__29_n_83\ : STD_LOGIC;
signal \ARG__29_n_84\ : STD_LOGIC;
signal \ARG__29_n_85\ : STD_LOGIC;
signal \ARG__29_n_86\ : STD_LOGIC;
signal \ARG__29_n_87\ : STD_LOGIC;
signal \ARG__29_n_88\ : STD_LOGIC;
signal \ARG__29_n_89\ : STD_LOGIC;
signal \ARG__29_n_90\ : STD_LOGIC;
signal \ARG__29_n_91\ : STD_LOGIC;
signal \ARG__29_n_92\ : STD_LOGIC;
signal \ARG__29_n_93\ : STD_LOGIC;
signal \ARG__29_n_94\ : STD_LOGIC;
signal \ARG__29_n_95\ : STD_LOGIC;
signal \ARG__29_n_96\ : STD_LOGIC;
signal \ARG__29_n_97\ : STD_LOGIC;
signal \ARG__29_n_98\ : STD_LOGIC;
signal \ARG__29_n_99\ : STD_LOGIC;
signal \ARG__2_i_1_n_0\ : STD_LOGIC;
signal \ARG__2_n_100\ : STD_LOGIC;
signal \ARG__2_n_101\ : STD_LOGIC;
signal \ARG__2_n_102\ : STD_LOGIC;
signal \ARG__2_n_103\ : STD_LOGIC;
signal \ARG__2_n_104\ : STD_LOGIC;
signal \ARG__2_n_105\ : STD_LOGIC;
signal \ARG__2_n_92\ : STD_LOGIC;
signal \ARG__2_n_93\ : STD_LOGIC;
signal \ARG__2_n_94\ : STD_LOGIC;
signal \ARG__2_n_95\ : STD_LOGIC;
signal \ARG__2_n_96\ : STD_LOGIC;
signal \ARG__2_n_97\ : STD_LOGIC;
signal \ARG__2_n_98\ : STD_LOGIC;
signal \ARG__2_n_99\ : STD_LOGIC;
signal \ARG__30_i_1_n_0\ : STD_LOGIC;
signal \ARG__30_n_100\ : STD_LOGIC;
signal \ARG__30_n_101\ : STD_LOGIC;
signal \ARG__30_n_102\ : STD_LOGIC;
signal \ARG__30_n_103\ : STD_LOGIC;
signal \ARG__30_n_104\ : STD_LOGIC;
signal \ARG__30_n_105\ : STD_LOGIC;
signal \ARG__30_n_92\ : STD_LOGIC;
signal \ARG__30_n_93\ : STD_LOGIC;
signal \ARG__30_n_94\ : STD_LOGIC;
signal \ARG__30_n_95\ : STD_LOGIC;
signal \ARG__30_n_96\ : STD_LOGIC;
signal \ARG__30_n_97\ : STD_LOGIC;
signal \ARG__30_n_98\ : STD_LOGIC;
signal \ARG__30_n_99\ : STD_LOGIC;
signal \ARG__31\ : STD_LOGIC_VECTOR ( 32 downto 17 );
signal \ARG__3_i_1_n_0\ : STD_LOGIC;
signal \ARG__3_n_100\ : STD_LOGIC;
signal \ARG__3_n_101\ : STD_LOGIC;
signal \ARG__3_n_102\ : STD_LOGIC;
signal \ARG__3_n_103\ : STD_LOGIC;
signal \ARG__3_n_104\ : STD_LOGIC;
signal \ARG__3_n_105\ : STD_LOGIC;
signal \ARG__3_n_76\ : STD_LOGIC;
signal \ARG__3_n_77\ : STD_LOGIC;
signal \ARG__3_n_78\ : STD_LOGIC;
signal \ARG__3_n_79\ : STD_LOGIC;
signal \ARG__3_n_80\ : STD_LOGIC;
signal \ARG__3_n_81\ : STD_LOGIC;
signal \ARG__3_n_82\ : STD_LOGIC;
signal \ARG__3_n_83\ : STD_LOGIC;
signal \ARG__3_n_84\ : STD_LOGIC;
signal \ARG__3_n_85\ : STD_LOGIC;
signal \ARG__3_n_86\ : STD_LOGIC;
signal \ARG__3_n_87\ : STD_LOGIC;
signal \ARG__3_n_88\ : STD_LOGIC;
signal \ARG__3_n_89\ : STD_LOGIC;
signal \ARG__3_n_90\ : STD_LOGIC;
signal \ARG__3_n_91\ : STD_LOGIC;
signal \ARG__3_n_92\ : STD_LOGIC;
signal \ARG__3_n_93\ : STD_LOGIC;
signal \ARG__3_n_94\ : STD_LOGIC;
signal \ARG__3_n_95\ : STD_LOGIC;
signal \ARG__3_n_96\ : STD_LOGIC;
signal \ARG__3_n_97\ : STD_LOGIC;
signal \ARG__3_n_98\ : STD_LOGIC;
signal \ARG__3_n_99\ : STD_LOGIC;
signal \ARG__4_i_1_n_0\ : STD_LOGIC;
signal \ARG__4_n_100\ : STD_LOGIC;
signal \ARG__4_n_101\ : STD_LOGIC;
signal \ARG__4_n_102\ : STD_LOGIC;
signal \ARG__4_n_103\ : STD_LOGIC;
signal \ARG__4_n_104\ : STD_LOGIC;
signal \ARG__4_n_105\ : STD_LOGIC;
signal \ARG__4_n_92\ : STD_LOGIC;
signal \ARG__4_n_93\ : STD_LOGIC;
signal \ARG__4_n_94\ : STD_LOGIC;
signal \ARG__4_n_95\ : STD_LOGIC;
signal \ARG__4_n_96\ : STD_LOGIC;
signal \ARG__4_n_97\ : STD_LOGIC;
signal \ARG__4_n_98\ : STD_LOGIC;
signal \ARG__4_n_99\ : STD_LOGIC;
signal \ARG__5_i_1_n_0\ : STD_LOGIC;
signal \ARG__5_n_100\ : STD_LOGIC;
signal \ARG__5_n_101\ : STD_LOGIC;
signal \ARG__5_n_102\ : STD_LOGIC;
signal \ARG__5_n_103\ : STD_LOGIC;
signal \ARG__5_n_104\ : STD_LOGIC;
signal \ARG__5_n_105\ : STD_LOGIC;
signal \ARG__5_n_76\ : STD_LOGIC;
signal \ARG__5_n_77\ : STD_LOGIC;
signal \ARG__5_n_78\ : STD_LOGIC;
signal \ARG__5_n_79\ : STD_LOGIC;
signal \ARG__5_n_80\ : STD_LOGIC;
signal \ARG__5_n_81\ : STD_LOGIC;
signal \ARG__5_n_82\ : STD_LOGIC;
signal \ARG__5_n_83\ : STD_LOGIC;
signal \ARG__5_n_84\ : STD_LOGIC;
signal \ARG__5_n_85\ : STD_LOGIC;
signal \ARG__5_n_86\ : STD_LOGIC;
signal \ARG__5_n_87\ : STD_LOGIC;
signal \ARG__5_n_88\ : STD_LOGIC;
signal \ARG__5_n_89\ : STD_LOGIC;
signal \ARG__5_n_90\ : STD_LOGIC;
signal \ARG__5_n_91\ : STD_LOGIC;
signal \ARG__5_n_92\ : STD_LOGIC;
signal \ARG__5_n_93\ : STD_LOGIC;
signal \ARG__5_n_94\ : STD_LOGIC;
signal \ARG__5_n_95\ : STD_LOGIC;
signal \ARG__5_n_96\ : STD_LOGIC;
signal \ARG__5_n_97\ : STD_LOGIC;
signal \ARG__5_n_98\ : STD_LOGIC;
signal \ARG__5_n_99\ : STD_LOGIC;
signal \ARG__6_i_1_n_0\ : STD_LOGIC;
signal \ARG__6_n_100\ : STD_LOGIC;
signal \ARG__6_n_101\ : STD_LOGIC;
signal \ARG__6_n_102\ : STD_LOGIC;
signal \ARG__6_n_103\ : STD_LOGIC;
signal \ARG__6_n_104\ : STD_LOGIC;
signal \ARG__6_n_105\ : STD_LOGIC;
signal \ARG__6_n_92\ : STD_LOGIC;
signal \ARG__6_n_93\ : STD_LOGIC;
signal \ARG__6_n_94\ : STD_LOGIC;
signal \ARG__6_n_95\ : STD_LOGIC;
signal \ARG__6_n_96\ : STD_LOGIC;
signal \ARG__6_n_97\ : STD_LOGIC;
signal \ARG__6_n_98\ : STD_LOGIC;
signal \ARG__6_n_99\ : STD_LOGIC;
signal \ARG__7_i_1_n_0\ : STD_LOGIC;
signal \ARG__7_n_100\ : STD_LOGIC;
signal \ARG__7_n_101\ : STD_LOGIC;
signal \ARG__7_n_102\ : STD_LOGIC;
signal \ARG__7_n_103\ : STD_LOGIC;
signal \ARG__7_n_104\ : STD_LOGIC;
signal \ARG__7_n_105\ : STD_LOGIC;
signal \ARG__7_n_76\ : STD_LOGIC;
signal \ARG__7_n_77\ : STD_LOGIC;
signal \ARG__7_n_78\ : STD_LOGIC;
signal \ARG__7_n_79\ : STD_LOGIC;
signal \ARG__7_n_80\ : STD_LOGIC;
signal \ARG__7_n_81\ : STD_LOGIC;
signal \ARG__7_n_82\ : STD_LOGIC;
signal \ARG__7_n_83\ : STD_LOGIC;
signal \ARG__7_n_84\ : STD_LOGIC;
signal \ARG__7_n_85\ : STD_LOGIC;
signal \ARG__7_n_86\ : STD_LOGIC;
signal \ARG__7_n_87\ : STD_LOGIC;
signal \ARG__7_n_88\ : STD_LOGIC;
signal \ARG__7_n_89\ : STD_LOGIC;
signal \ARG__7_n_90\ : STD_LOGIC;
signal \ARG__7_n_91\ : STD_LOGIC;
signal \ARG__7_n_92\ : STD_LOGIC;
signal \ARG__7_n_93\ : STD_LOGIC;
signal \ARG__7_n_94\ : STD_LOGIC;
signal \ARG__7_n_95\ : STD_LOGIC;
signal \ARG__7_n_96\ : STD_LOGIC;
signal \ARG__7_n_97\ : STD_LOGIC;
signal \ARG__7_n_98\ : STD_LOGIC;
signal \ARG__7_n_99\ : STD_LOGIC;
signal \ARG__8_i_1_n_0\ : STD_LOGIC;
signal \ARG__8_n_100\ : STD_LOGIC;
signal \ARG__8_n_101\ : STD_LOGIC;
signal \ARG__8_n_102\ : STD_LOGIC;
signal \ARG__8_n_103\ : STD_LOGIC;
signal \ARG__8_n_104\ : STD_LOGIC;
signal \ARG__8_n_105\ : STD_LOGIC;
signal \ARG__8_n_92\ : STD_LOGIC;
signal \ARG__8_n_93\ : STD_LOGIC;
signal \ARG__8_n_94\ : STD_LOGIC;
signal \ARG__8_n_95\ : STD_LOGIC;
signal \ARG__8_n_96\ : STD_LOGIC;
signal \ARG__8_n_97\ : STD_LOGIC;
signal \ARG__8_n_98\ : STD_LOGIC;
signal \ARG__8_n_99\ : STD_LOGIC;
signal \ARG__9_i_1_n_0\ : STD_LOGIC;
signal \ARG__9_n_100\ : STD_LOGIC;
signal \ARG__9_n_101\ : STD_LOGIC;
signal \ARG__9_n_102\ : STD_LOGIC;
signal \ARG__9_n_103\ : STD_LOGIC;
signal \ARG__9_n_104\ : STD_LOGIC;
signal \ARG__9_n_105\ : STD_LOGIC;
signal \ARG__9_n_76\ : STD_LOGIC;
signal \ARG__9_n_77\ : STD_LOGIC;
signal \ARG__9_n_78\ : STD_LOGIC;
signal \ARG__9_n_79\ : STD_LOGIC;
signal \ARG__9_n_80\ : STD_LOGIC;
signal \ARG__9_n_81\ : STD_LOGIC;
signal \ARG__9_n_82\ : STD_LOGIC;
signal \ARG__9_n_83\ : STD_LOGIC;
signal \ARG__9_n_84\ : STD_LOGIC;
signal \ARG__9_n_85\ : STD_LOGIC;
signal \ARG__9_n_86\ : STD_LOGIC;
signal \ARG__9_n_87\ : STD_LOGIC;
signal \ARG__9_n_88\ : STD_LOGIC;
signal \ARG__9_n_89\ : STD_LOGIC;
signal \ARG__9_n_90\ : STD_LOGIC;
signal \ARG__9_n_91\ : STD_LOGIC;
signal \ARG__9_n_92\ : STD_LOGIC;
signal \ARG__9_n_93\ : STD_LOGIC;
signal \ARG__9_n_94\ : STD_LOGIC;
signal \ARG__9_n_95\ : STD_LOGIC;
signal \ARG__9_n_96\ : STD_LOGIC;
signal \ARG__9_n_97\ : STD_LOGIC;
signal \ARG__9_n_98\ : STD_LOGIC;
signal \ARG__9_n_99\ : STD_LOGIC;
signal \ARG_carry__0_i_2_n_0\ : STD_LOGIC;
signal \ARG_carry__0_i_3_n_0\ : STD_LOGIC;
signal \ARG_carry__0_i_4_n_0\ : STD_LOGIC;
signal \ARG_carry__0_n_0\ : STD_LOGIC;
signal \ARG_carry__0_n_1\ : STD_LOGIC;
signal \ARG_carry__0_n_2\ : STD_LOGIC;
signal \ARG_carry__0_n_3\ : STD_LOGIC;
signal \ARG_carry__1_i_1_n_0\ : STD_LOGIC;
signal \ARG_carry__1_i_2_n_0\ : STD_LOGIC;
signal \ARG_carry__1_i_3_n_0\ : STD_LOGIC;
signal \ARG_carry__1_i_4_n_0\ : STD_LOGIC;
signal \ARG_carry__1_n_0\ : STD_LOGIC;
signal \ARG_carry__1_n_1\ : STD_LOGIC;
signal \ARG_carry__1_n_2\ : STD_LOGIC;
signal \ARG_carry__1_n_3\ : STD_LOGIC;
signal \ARG_carry__2_i_1_n_0\ : STD_LOGIC;
signal \ARG_carry__2_i_2_n_0\ : STD_LOGIC;
signal \ARG_carry__2_i_3_n_0\ : STD_LOGIC;
signal \ARG_carry__2_i_4_n_0\ : STD_LOGIC;
signal \ARG_carry__2_n_0\ : STD_LOGIC;
signal \ARG_carry__2_n_1\ : STD_LOGIC;
signal \ARG_carry__2_n_2\ : STD_LOGIC;
signal \ARG_carry__2_n_3\ : STD_LOGIC;
signal \ARG_carry__3_i_1_n_0\ : STD_LOGIC;
signal \ARG_carry__3_n_3\ : STD_LOGIC;
signal ARG_carry_n_0 : STD_LOGIC;
signal ARG_carry_n_1 : STD_LOGIC;
signal ARG_carry_n_2 : STD_LOGIC;
signal ARG_carry_n_3 : STD_LOGIC;
signal ARG_i_1_n_0 : STD_LOGIC;
signal ARG_n_100 : STD_LOGIC;
signal ARG_n_101 : STD_LOGIC;
signal ARG_n_102 : STD_LOGIC;
signal ARG_n_103 : STD_LOGIC;
signal ARG_n_104 : STD_LOGIC;
signal ARG_n_105 : STD_LOGIC;
signal ARG_n_92 : STD_LOGIC;
signal ARG_n_93 : STD_LOGIC;
signal ARG_n_94 : STD_LOGIC;
signal ARG_n_95 : STD_LOGIC;
signal ARG_n_96 : STD_LOGIC;
signal ARG_n_97 : STD_LOGIC;
signal ARG_n_98 : STD_LOGIC;
signal ARG_n_99 : STD_LOGIC;
signal RESIZE15 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE16 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE18 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE20 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE22 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE24 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE26 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE28 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE30 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE32 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE34 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE36 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE38 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE40 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE42 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE44 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \add_temp_14__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_11_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_12_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_11_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_12_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_11_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_7\ : STD_LOGIC;
signal \data_pipeline_tmp_reg[0]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[10]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[11]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[12]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[13]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[14]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[1]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[2]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[3]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[4]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[5]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[6]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[7]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[8]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[9]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \in\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^mul_temp\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_1\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_10\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_10_n_100 : STD_LOGIC;
signal mul_temp_10_n_101 : STD_LOGIC;
signal mul_temp_10_n_102 : STD_LOGIC;
signal mul_temp_10_n_103 : STD_LOGIC;
signal mul_temp_10_n_104 : STD_LOGIC;
signal mul_temp_10_n_105 : STD_LOGIC;
signal mul_temp_10_n_74 : STD_LOGIC;
signal mul_temp_10_n_75 : STD_LOGIC;
signal mul_temp_10_n_76 : STD_LOGIC;
signal mul_temp_10_n_77 : STD_LOGIC;
signal mul_temp_10_n_78 : STD_LOGIC;
signal mul_temp_10_n_79 : STD_LOGIC;
signal mul_temp_10_n_80 : STD_LOGIC;
signal mul_temp_10_n_81 : STD_LOGIC;
signal mul_temp_10_n_82 : STD_LOGIC;
signal mul_temp_10_n_83 : STD_LOGIC;
signal mul_temp_10_n_84 : STD_LOGIC;
signal mul_temp_10_n_85 : STD_LOGIC;
signal mul_temp_10_n_86 : STD_LOGIC;
signal mul_temp_10_n_87 : STD_LOGIC;
signal mul_temp_10_n_88 : STD_LOGIC;
signal mul_temp_10_n_89 : STD_LOGIC;
signal mul_temp_10_n_90 : STD_LOGIC;
signal mul_temp_10_n_92 : STD_LOGIC;
signal mul_temp_10_n_93 : STD_LOGIC;
signal mul_temp_10_n_94 : STD_LOGIC;
signal mul_temp_10_n_95 : STD_LOGIC;
signal mul_temp_10_n_96 : STD_LOGIC;
signal mul_temp_10_n_97 : STD_LOGIC;
signal mul_temp_10_n_98 : STD_LOGIC;
signal mul_temp_10_n_99 : STD_LOGIC;
signal \^mul_temp_11\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_11_n_100 : STD_LOGIC;
signal mul_temp_11_n_101 : STD_LOGIC;
signal mul_temp_11_n_102 : STD_LOGIC;
signal mul_temp_11_n_103 : STD_LOGIC;
signal mul_temp_11_n_104 : STD_LOGIC;
signal mul_temp_11_n_105 : STD_LOGIC;
signal mul_temp_11_n_74 : STD_LOGIC;
signal mul_temp_11_n_75 : STD_LOGIC;
signal mul_temp_11_n_76 : STD_LOGIC;
signal mul_temp_11_n_77 : STD_LOGIC;
signal mul_temp_11_n_78 : STD_LOGIC;
signal mul_temp_11_n_79 : STD_LOGIC;
signal mul_temp_11_n_80 : STD_LOGIC;
signal mul_temp_11_n_81 : STD_LOGIC;
signal mul_temp_11_n_82 : STD_LOGIC;
signal mul_temp_11_n_83 : STD_LOGIC;
signal mul_temp_11_n_84 : STD_LOGIC;
signal mul_temp_11_n_85 : STD_LOGIC;
signal mul_temp_11_n_86 : STD_LOGIC;
signal mul_temp_11_n_87 : STD_LOGIC;
signal mul_temp_11_n_88 : STD_LOGIC;
signal mul_temp_11_n_89 : STD_LOGIC;
signal mul_temp_11_n_90 : STD_LOGIC;
signal mul_temp_11_n_92 : STD_LOGIC;
signal mul_temp_11_n_93 : STD_LOGIC;
signal mul_temp_11_n_94 : STD_LOGIC;
signal mul_temp_11_n_95 : STD_LOGIC;
signal mul_temp_11_n_96 : STD_LOGIC;
signal mul_temp_11_n_97 : STD_LOGIC;
signal mul_temp_11_n_98 : STD_LOGIC;
signal mul_temp_11_n_99 : STD_LOGIC;
signal \^mul_temp_12\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_12_n_100 : STD_LOGIC;
signal mul_temp_12_n_101 : STD_LOGIC;
signal mul_temp_12_n_102 : STD_LOGIC;
signal mul_temp_12_n_103 : STD_LOGIC;
signal mul_temp_12_n_104 : STD_LOGIC;
signal mul_temp_12_n_105 : STD_LOGIC;
signal mul_temp_12_n_74 : STD_LOGIC;
signal mul_temp_12_n_75 : STD_LOGIC;
signal mul_temp_12_n_76 : STD_LOGIC;
signal mul_temp_12_n_77 : STD_LOGIC;
signal mul_temp_12_n_78 : STD_LOGIC;
signal mul_temp_12_n_79 : STD_LOGIC;
signal mul_temp_12_n_80 : STD_LOGIC;
signal mul_temp_12_n_81 : STD_LOGIC;
signal mul_temp_12_n_82 : STD_LOGIC;
signal mul_temp_12_n_83 : STD_LOGIC;
signal mul_temp_12_n_84 : STD_LOGIC;
signal mul_temp_12_n_85 : STD_LOGIC;
signal mul_temp_12_n_86 : STD_LOGIC;
signal mul_temp_12_n_87 : STD_LOGIC;
signal mul_temp_12_n_88 : STD_LOGIC;
signal mul_temp_12_n_89 : STD_LOGIC;
signal mul_temp_12_n_90 : STD_LOGIC;
signal mul_temp_12_n_92 : STD_LOGIC;
signal mul_temp_12_n_93 : STD_LOGIC;
signal mul_temp_12_n_94 : STD_LOGIC;
signal mul_temp_12_n_95 : STD_LOGIC;
signal mul_temp_12_n_96 : STD_LOGIC;
signal mul_temp_12_n_97 : STD_LOGIC;
signal mul_temp_12_n_98 : STD_LOGIC;
signal mul_temp_12_n_99 : STD_LOGIC;
signal \^mul_temp_13\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_13_n_100 : STD_LOGIC;
signal mul_temp_13_n_101 : STD_LOGIC;
signal mul_temp_13_n_102 : STD_LOGIC;
signal mul_temp_13_n_103 : STD_LOGIC;
signal mul_temp_13_n_104 : STD_LOGIC;
signal mul_temp_13_n_105 : STD_LOGIC;
signal mul_temp_13_n_74 : STD_LOGIC;
signal mul_temp_13_n_75 : STD_LOGIC;
signal mul_temp_13_n_76 : STD_LOGIC;
signal mul_temp_13_n_77 : STD_LOGIC;
signal mul_temp_13_n_78 : STD_LOGIC;
signal mul_temp_13_n_79 : STD_LOGIC;
signal mul_temp_13_n_80 : STD_LOGIC;
signal mul_temp_13_n_81 : STD_LOGIC;
signal mul_temp_13_n_82 : STD_LOGIC;
signal mul_temp_13_n_83 : STD_LOGIC;
signal mul_temp_13_n_84 : STD_LOGIC;
signal mul_temp_13_n_85 : STD_LOGIC;
signal mul_temp_13_n_86 : STD_LOGIC;
signal mul_temp_13_n_87 : STD_LOGIC;
signal mul_temp_13_n_88 : STD_LOGIC;
signal mul_temp_13_n_89 : STD_LOGIC;
signal mul_temp_13_n_90 : STD_LOGIC;
signal mul_temp_13_n_92 : STD_LOGIC;
signal mul_temp_13_n_93 : STD_LOGIC;
signal mul_temp_13_n_94 : STD_LOGIC;
signal mul_temp_13_n_95 : STD_LOGIC;
signal mul_temp_13_n_96 : STD_LOGIC;
signal mul_temp_13_n_97 : STD_LOGIC;
signal mul_temp_13_n_98 : STD_LOGIC;
signal mul_temp_13_n_99 : STD_LOGIC;
signal \^mul_temp_14\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_14_n_100 : STD_LOGIC;
signal mul_temp_14_n_101 : STD_LOGIC;
signal mul_temp_14_n_102 : STD_LOGIC;
signal mul_temp_14_n_103 : STD_LOGIC;
signal mul_temp_14_n_104 : STD_LOGIC;
signal mul_temp_14_n_105 : STD_LOGIC;
signal mul_temp_14_n_74 : STD_LOGIC;
signal mul_temp_14_n_75 : STD_LOGIC;
signal mul_temp_14_n_76 : STD_LOGIC;
signal mul_temp_14_n_77 : STD_LOGIC;
signal mul_temp_14_n_78 : STD_LOGIC;
signal mul_temp_14_n_79 : STD_LOGIC;
signal mul_temp_14_n_80 : STD_LOGIC;
signal mul_temp_14_n_81 : STD_LOGIC;
signal mul_temp_14_n_82 : STD_LOGIC;
signal mul_temp_14_n_83 : STD_LOGIC;
signal mul_temp_14_n_84 : STD_LOGIC;
signal mul_temp_14_n_85 : STD_LOGIC;
signal mul_temp_14_n_86 : STD_LOGIC;
signal mul_temp_14_n_87 : STD_LOGIC;
signal mul_temp_14_n_88 : STD_LOGIC;
signal mul_temp_14_n_89 : STD_LOGIC;
signal mul_temp_14_n_90 : STD_LOGIC;
signal mul_temp_14_n_92 : STD_LOGIC;
signal mul_temp_14_n_93 : STD_LOGIC;
signal mul_temp_14_n_94 : STD_LOGIC;
signal mul_temp_14_n_95 : STD_LOGIC;
signal mul_temp_14_n_96 : STD_LOGIC;
signal mul_temp_14_n_97 : STD_LOGIC;
signal mul_temp_14_n_98 : STD_LOGIC;
signal mul_temp_14_n_99 : STD_LOGIC;
signal \^mul_temp_15\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_15_n_100 : STD_LOGIC;
signal mul_temp_15_n_101 : STD_LOGIC;
signal mul_temp_15_n_102 : STD_LOGIC;
signal mul_temp_15_n_103 : STD_LOGIC;
signal mul_temp_15_n_104 : STD_LOGIC;
signal mul_temp_15_n_105 : STD_LOGIC;
signal mul_temp_15_n_74 : STD_LOGIC;
signal mul_temp_15_n_75 : STD_LOGIC;
signal mul_temp_15_n_76 : STD_LOGIC;
signal mul_temp_15_n_77 : STD_LOGIC;
signal mul_temp_15_n_78 : STD_LOGIC;
signal mul_temp_15_n_79 : STD_LOGIC;
signal mul_temp_15_n_80 : STD_LOGIC;
signal mul_temp_15_n_81 : STD_LOGIC;
signal mul_temp_15_n_82 : STD_LOGIC;
signal mul_temp_15_n_83 : STD_LOGIC;
signal mul_temp_15_n_84 : STD_LOGIC;
signal mul_temp_15_n_85 : STD_LOGIC;
signal mul_temp_15_n_86 : STD_LOGIC;
signal mul_temp_15_n_87 : STD_LOGIC;
signal mul_temp_15_n_88 : STD_LOGIC;
signal mul_temp_15_n_89 : STD_LOGIC;
signal mul_temp_15_n_90 : STD_LOGIC;
signal mul_temp_15_n_92 : STD_LOGIC;
signal mul_temp_15_n_93 : STD_LOGIC;
signal mul_temp_15_n_94 : STD_LOGIC;
signal mul_temp_15_n_95 : STD_LOGIC;
signal mul_temp_15_n_96 : STD_LOGIC;
signal mul_temp_15_n_97 : STD_LOGIC;
signal mul_temp_15_n_98 : STD_LOGIC;
signal mul_temp_15_n_99 : STD_LOGIC;
signal \^mul_temp_16\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^mul_temp_17\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_17_n_100 : STD_LOGIC;
signal mul_temp_17_n_101 : STD_LOGIC;
signal mul_temp_17_n_102 : STD_LOGIC;
signal mul_temp_17_n_103 : STD_LOGIC;
signal mul_temp_17_n_104 : STD_LOGIC;
signal mul_temp_17_n_105 : STD_LOGIC;
signal mul_temp_17_n_74 : STD_LOGIC;
signal mul_temp_17_n_75 : STD_LOGIC;
signal mul_temp_17_n_76 : STD_LOGIC;
signal mul_temp_17_n_77 : STD_LOGIC;
signal mul_temp_17_n_78 : STD_LOGIC;
signal mul_temp_17_n_79 : STD_LOGIC;
signal mul_temp_17_n_80 : STD_LOGIC;
signal mul_temp_17_n_81 : STD_LOGIC;
signal mul_temp_17_n_82 : STD_LOGIC;
signal mul_temp_17_n_83 : STD_LOGIC;
signal mul_temp_17_n_84 : STD_LOGIC;
signal mul_temp_17_n_85 : STD_LOGIC;
signal mul_temp_17_n_86 : STD_LOGIC;
signal mul_temp_17_n_87 : STD_LOGIC;
signal mul_temp_17_n_88 : STD_LOGIC;
signal mul_temp_17_n_89 : STD_LOGIC;
signal mul_temp_17_n_90 : STD_LOGIC;
signal mul_temp_17_n_92 : STD_LOGIC;
signal mul_temp_17_n_93 : STD_LOGIC;
signal mul_temp_17_n_94 : STD_LOGIC;
signal mul_temp_17_n_95 : STD_LOGIC;
signal mul_temp_17_n_96 : STD_LOGIC;
signal mul_temp_17_n_97 : STD_LOGIC;
signal mul_temp_17_n_98 : STD_LOGIC;
signal mul_temp_17_n_99 : STD_LOGIC;
signal \^mul_temp_18\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_18_n_100 : STD_LOGIC;
signal mul_temp_18_n_101 : STD_LOGIC;
signal mul_temp_18_n_102 : STD_LOGIC;
signal mul_temp_18_n_103 : STD_LOGIC;
signal mul_temp_18_n_104 : STD_LOGIC;
signal mul_temp_18_n_105 : STD_LOGIC;
signal mul_temp_18_n_74 : STD_LOGIC;
signal mul_temp_18_n_75 : STD_LOGIC;
signal mul_temp_18_n_76 : STD_LOGIC;
signal mul_temp_18_n_77 : STD_LOGIC;
signal mul_temp_18_n_78 : STD_LOGIC;
signal mul_temp_18_n_79 : STD_LOGIC;
signal mul_temp_18_n_80 : STD_LOGIC;
signal mul_temp_18_n_81 : STD_LOGIC;
signal mul_temp_18_n_82 : STD_LOGIC;
signal mul_temp_18_n_83 : STD_LOGIC;
signal mul_temp_18_n_84 : STD_LOGIC;
signal mul_temp_18_n_85 : STD_LOGIC;
signal mul_temp_18_n_86 : STD_LOGIC;
signal mul_temp_18_n_87 : STD_LOGIC;
signal mul_temp_18_n_88 : STD_LOGIC;
signal mul_temp_18_n_89 : STD_LOGIC;
signal mul_temp_18_n_90 : STD_LOGIC;
signal mul_temp_18_n_92 : STD_LOGIC;
signal mul_temp_18_n_93 : STD_LOGIC;
signal mul_temp_18_n_94 : STD_LOGIC;
signal mul_temp_18_n_95 : STD_LOGIC;
signal mul_temp_18_n_96 : STD_LOGIC;
signal mul_temp_18_n_97 : STD_LOGIC;
signal mul_temp_18_n_98 : STD_LOGIC;
signal mul_temp_18_n_99 : STD_LOGIC;
signal \^mul_temp_19\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_19_n_100 : STD_LOGIC;
signal mul_temp_19_n_101 : STD_LOGIC;
signal mul_temp_19_n_102 : STD_LOGIC;
signal mul_temp_19_n_103 : STD_LOGIC;
signal mul_temp_19_n_104 : STD_LOGIC;
signal mul_temp_19_n_105 : STD_LOGIC;
signal mul_temp_19_n_74 : STD_LOGIC;
signal mul_temp_19_n_75 : STD_LOGIC;
signal mul_temp_19_n_76 : STD_LOGIC;
signal mul_temp_19_n_77 : STD_LOGIC;
signal mul_temp_19_n_78 : STD_LOGIC;
signal mul_temp_19_n_79 : STD_LOGIC;
signal mul_temp_19_n_80 : STD_LOGIC;
signal mul_temp_19_n_81 : STD_LOGIC;
signal mul_temp_19_n_82 : STD_LOGIC;
signal mul_temp_19_n_83 : STD_LOGIC;
signal mul_temp_19_n_84 : STD_LOGIC;
signal mul_temp_19_n_85 : STD_LOGIC;
signal mul_temp_19_n_86 : STD_LOGIC;
signal mul_temp_19_n_87 : STD_LOGIC;
signal mul_temp_19_n_88 : STD_LOGIC;
signal mul_temp_19_n_89 : STD_LOGIC;
signal mul_temp_19_n_90 : STD_LOGIC;
signal mul_temp_19_n_92 : STD_LOGIC;
signal mul_temp_19_n_93 : STD_LOGIC;
signal mul_temp_19_n_94 : STD_LOGIC;
signal mul_temp_19_n_95 : STD_LOGIC;
signal mul_temp_19_n_96 : STD_LOGIC;
signal mul_temp_19_n_97 : STD_LOGIC;
signal mul_temp_19_n_98 : STD_LOGIC;
signal mul_temp_19_n_99 : STD_LOGIC;
signal mul_temp_1_n_100 : STD_LOGIC;
signal mul_temp_1_n_101 : STD_LOGIC;
signal mul_temp_1_n_102 : STD_LOGIC;
signal mul_temp_1_n_103 : STD_LOGIC;
signal mul_temp_1_n_104 : STD_LOGIC;
signal mul_temp_1_n_105 : STD_LOGIC;
signal mul_temp_1_n_74 : STD_LOGIC;
signal mul_temp_1_n_75 : STD_LOGIC;
signal mul_temp_1_n_76 : STD_LOGIC;
signal mul_temp_1_n_77 : STD_LOGIC;
signal mul_temp_1_n_78 : STD_LOGIC;
signal mul_temp_1_n_79 : STD_LOGIC;
signal mul_temp_1_n_80 : STD_LOGIC;
signal mul_temp_1_n_81 : STD_LOGIC;
signal mul_temp_1_n_82 : STD_LOGIC;
signal mul_temp_1_n_83 : STD_LOGIC;
signal mul_temp_1_n_84 : STD_LOGIC;
signal mul_temp_1_n_85 : STD_LOGIC;
signal mul_temp_1_n_86 : STD_LOGIC;
signal mul_temp_1_n_87 : STD_LOGIC;
signal mul_temp_1_n_88 : STD_LOGIC;
signal mul_temp_1_n_89 : STD_LOGIC;
signal mul_temp_1_n_90 : STD_LOGIC;
signal mul_temp_1_n_92 : STD_LOGIC;
signal mul_temp_1_n_93 : STD_LOGIC;
signal mul_temp_1_n_94 : STD_LOGIC;
signal mul_temp_1_n_95 : STD_LOGIC;
signal mul_temp_1_n_96 : STD_LOGIC;
signal mul_temp_1_n_97 : STD_LOGIC;
signal mul_temp_1_n_98 : STD_LOGIC;
signal mul_temp_1_n_99 : STD_LOGIC;
signal \^mul_temp_2\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_20\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_20_n_100 : STD_LOGIC;
signal mul_temp_20_n_101 : STD_LOGIC;
signal mul_temp_20_n_102 : STD_LOGIC;
signal mul_temp_20_n_103 : STD_LOGIC;
signal mul_temp_20_n_104 : STD_LOGIC;
signal mul_temp_20_n_105 : STD_LOGIC;
signal mul_temp_20_n_74 : STD_LOGIC;
signal mul_temp_20_n_75 : STD_LOGIC;
signal mul_temp_20_n_76 : STD_LOGIC;
signal mul_temp_20_n_77 : STD_LOGIC;
signal mul_temp_20_n_78 : STD_LOGIC;
signal mul_temp_20_n_79 : STD_LOGIC;
signal mul_temp_20_n_80 : STD_LOGIC;
signal mul_temp_20_n_81 : STD_LOGIC;
signal mul_temp_20_n_82 : STD_LOGIC;
signal mul_temp_20_n_83 : STD_LOGIC;
signal mul_temp_20_n_84 : STD_LOGIC;
signal mul_temp_20_n_85 : STD_LOGIC;
signal mul_temp_20_n_86 : STD_LOGIC;
signal mul_temp_20_n_87 : STD_LOGIC;
signal mul_temp_20_n_88 : STD_LOGIC;
signal mul_temp_20_n_89 : STD_LOGIC;
signal mul_temp_20_n_90 : STD_LOGIC;
signal mul_temp_20_n_92 : STD_LOGIC;
signal mul_temp_20_n_93 : STD_LOGIC;
signal mul_temp_20_n_94 : STD_LOGIC;
signal mul_temp_20_n_95 : STD_LOGIC;
signal mul_temp_20_n_96 : STD_LOGIC;
signal mul_temp_20_n_97 : STD_LOGIC;
signal mul_temp_20_n_98 : STD_LOGIC;
signal mul_temp_20_n_99 : STD_LOGIC;
signal \^mul_temp_21\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_21_n_100 : STD_LOGIC;
signal mul_temp_21_n_101 : STD_LOGIC;
signal mul_temp_21_n_102 : STD_LOGIC;
signal mul_temp_21_n_103 : STD_LOGIC;
signal mul_temp_21_n_104 : STD_LOGIC;
signal mul_temp_21_n_105 : STD_LOGIC;
signal mul_temp_21_n_74 : STD_LOGIC;
signal mul_temp_21_n_75 : STD_LOGIC;
signal mul_temp_21_n_76 : STD_LOGIC;
signal mul_temp_21_n_77 : STD_LOGIC;
signal mul_temp_21_n_78 : STD_LOGIC;
signal mul_temp_21_n_79 : STD_LOGIC;
signal mul_temp_21_n_80 : STD_LOGIC;
signal mul_temp_21_n_81 : STD_LOGIC;
signal mul_temp_21_n_82 : STD_LOGIC;
signal mul_temp_21_n_83 : STD_LOGIC;
signal mul_temp_21_n_84 : STD_LOGIC;
signal mul_temp_21_n_85 : STD_LOGIC;
signal mul_temp_21_n_86 : STD_LOGIC;
signal mul_temp_21_n_87 : STD_LOGIC;
signal mul_temp_21_n_88 : STD_LOGIC;
signal mul_temp_21_n_89 : STD_LOGIC;
signal mul_temp_21_n_90 : STD_LOGIC;
signal mul_temp_21_n_92 : STD_LOGIC;
signal mul_temp_21_n_93 : STD_LOGIC;
signal mul_temp_21_n_94 : STD_LOGIC;
signal mul_temp_21_n_95 : STD_LOGIC;
signal mul_temp_21_n_96 : STD_LOGIC;
signal mul_temp_21_n_97 : STD_LOGIC;
signal mul_temp_21_n_98 : STD_LOGIC;
signal mul_temp_21_n_99 : STD_LOGIC;
signal \^mul_temp_22\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_22_n_100 : STD_LOGIC;
signal mul_temp_22_n_101 : STD_LOGIC;
signal mul_temp_22_n_102 : STD_LOGIC;
signal mul_temp_22_n_103 : STD_LOGIC;
signal mul_temp_22_n_104 : STD_LOGIC;
signal mul_temp_22_n_105 : STD_LOGIC;
signal mul_temp_22_n_74 : STD_LOGIC;
signal mul_temp_22_n_75 : STD_LOGIC;
signal mul_temp_22_n_76 : STD_LOGIC;
signal mul_temp_22_n_77 : STD_LOGIC;
signal mul_temp_22_n_78 : STD_LOGIC;
signal mul_temp_22_n_79 : STD_LOGIC;
signal mul_temp_22_n_80 : STD_LOGIC;
signal mul_temp_22_n_81 : STD_LOGIC;
signal mul_temp_22_n_82 : STD_LOGIC;
signal mul_temp_22_n_83 : STD_LOGIC;
signal mul_temp_22_n_84 : STD_LOGIC;
signal mul_temp_22_n_85 : STD_LOGIC;
signal mul_temp_22_n_86 : STD_LOGIC;
signal mul_temp_22_n_87 : STD_LOGIC;
signal mul_temp_22_n_88 : STD_LOGIC;
signal mul_temp_22_n_89 : STD_LOGIC;
signal mul_temp_22_n_90 : STD_LOGIC;
signal mul_temp_22_n_92 : STD_LOGIC;
signal mul_temp_22_n_93 : STD_LOGIC;
signal mul_temp_22_n_94 : STD_LOGIC;
signal mul_temp_22_n_95 : STD_LOGIC;
signal mul_temp_22_n_96 : STD_LOGIC;
signal mul_temp_22_n_97 : STD_LOGIC;
signal mul_temp_22_n_98 : STD_LOGIC;
signal mul_temp_22_n_99 : STD_LOGIC;
signal \^mul_temp_23\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_23_n_100 : STD_LOGIC;
signal mul_temp_23_n_101 : STD_LOGIC;
signal mul_temp_23_n_102 : STD_LOGIC;
signal mul_temp_23_n_103 : STD_LOGIC;
signal mul_temp_23_n_104 : STD_LOGIC;
signal mul_temp_23_n_105 : STD_LOGIC;
signal mul_temp_23_n_74 : STD_LOGIC;
signal mul_temp_23_n_75 : STD_LOGIC;
signal mul_temp_23_n_76 : STD_LOGIC;
signal mul_temp_23_n_77 : STD_LOGIC;
signal mul_temp_23_n_78 : STD_LOGIC;
signal mul_temp_23_n_79 : STD_LOGIC;
signal mul_temp_23_n_80 : STD_LOGIC;
signal mul_temp_23_n_81 : STD_LOGIC;
signal mul_temp_23_n_82 : STD_LOGIC;
signal mul_temp_23_n_83 : STD_LOGIC;
signal mul_temp_23_n_84 : STD_LOGIC;
signal mul_temp_23_n_85 : STD_LOGIC;
signal mul_temp_23_n_86 : STD_LOGIC;
signal mul_temp_23_n_87 : STD_LOGIC;
signal mul_temp_23_n_88 : STD_LOGIC;
signal mul_temp_23_n_89 : STD_LOGIC;
signal mul_temp_23_n_90 : STD_LOGIC;
signal mul_temp_23_n_92 : STD_LOGIC;
signal mul_temp_23_n_93 : STD_LOGIC;
signal mul_temp_23_n_94 : STD_LOGIC;
signal mul_temp_23_n_95 : STD_LOGIC;
signal mul_temp_23_n_96 : STD_LOGIC;
signal mul_temp_23_n_97 : STD_LOGIC;
signal mul_temp_23_n_98 : STD_LOGIC;
signal mul_temp_23_n_99 : STD_LOGIC;
signal \^mul_temp_24\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_24_n_100 : STD_LOGIC;
signal mul_temp_24_n_101 : STD_LOGIC;
signal mul_temp_24_n_102 : STD_LOGIC;
signal mul_temp_24_n_103 : STD_LOGIC;
signal mul_temp_24_n_104 : STD_LOGIC;
signal mul_temp_24_n_105 : STD_LOGIC;
signal mul_temp_24_n_74 : STD_LOGIC;
signal mul_temp_24_n_75 : STD_LOGIC;
signal mul_temp_24_n_76 : STD_LOGIC;
signal mul_temp_24_n_77 : STD_LOGIC;
signal mul_temp_24_n_78 : STD_LOGIC;
signal mul_temp_24_n_79 : STD_LOGIC;
signal mul_temp_24_n_80 : STD_LOGIC;
signal mul_temp_24_n_81 : STD_LOGIC;
signal mul_temp_24_n_82 : STD_LOGIC;
signal mul_temp_24_n_83 : STD_LOGIC;
signal mul_temp_24_n_84 : STD_LOGIC;
signal mul_temp_24_n_85 : STD_LOGIC;
signal mul_temp_24_n_86 : STD_LOGIC;
signal mul_temp_24_n_87 : STD_LOGIC;
signal mul_temp_24_n_88 : STD_LOGIC;
signal mul_temp_24_n_89 : STD_LOGIC;
signal mul_temp_24_n_90 : STD_LOGIC;
signal mul_temp_24_n_92 : STD_LOGIC;
signal mul_temp_24_n_93 : STD_LOGIC;
signal mul_temp_24_n_94 : STD_LOGIC;
signal mul_temp_24_n_95 : STD_LOGIC;
signal mul_temp_24_n_96 : STD_LOGIC;
signal mul_temp_24_n_97 : STD_LOGIC;
signal mul_temp_24_n_98 : STD_LOGIC;
signal mul_temp_24_n_99 : STD_LOGIC;
signal \^mul_temp_25\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_25_n_100 : STD_LOGIC;
signal mul_temp_25_n_101 : STD_LOGIC;
signal mul_temp_25_n_102 : STD_LOGIC;
signal mul_temp_25_n_103 : STD_LOGIC;
signal mul_temp_25_n_104 : STD_LOGIC;
signal mul_temp_25_n_105 : STD_LOGIC;
signal mul_temp_25_n_74 : STD_LOGIC;
signal mul_temp_25_n_75 : STD_LOGIC;
signal mul_temp_25_n_76 : STD_LOGIC;
signal mul_temp_25_n_77 : STD_LOGIC;
signal mul_temp_25_n_78 : STD_LOGIC;
signal mul_temp_25_n_79 : STD_LOGIC;
signal mul_temp_25_n_80 : STD_LOGIC;
signal mul_temp_25_n_81 : STD_LOGIC;
signal mul_temp_25_n_82 : STD_LOGIC;
signal mul_temp_25_n_83 : STD_LOGIC;
signal mul_temp_25_n_84 : STD_LOGIC;
signal mul_temp_25_n_85 : STD_LOGIC;
signal mul_temp_25_n_86 : STD_LOGIC;
signal mul_temp_25_n_87 : STD_LOGIC;
signal mul_temp_25_n_88 : STD_LOGIC;
signal mul_temp_25_n_89 : STD_LOGIC;
signal mul_temp_25_n_90 : STD_LOGIC;
signal mul_temp_25_n_92 : STD_LOGIC;
signal mul_temp_25_n_93 : STD_LOGIC;
signal mul_temp_25_n_94 : STD_LOGIC;
signal mul_temp_25_n_95 : STD_LOGIC;
signal mul_temp_25_n_96 : STD_LOGIC;
signal mul_temp_25_n_97 : STD_LOGIC;
signal mul_temp_25_n_98 : STD_LOGIC;
signal mul_temp_25_n_99 : STD_LOGIC;
signal \^mul_temp_26\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_26_n_100 : STD_LOGIC;
signal mul_temp_26_n_101 : STD_LOGIC;
signal mul_temp_26_n_102 : STD_LOGIC;
signal mul_temp_26_n_103 : STD_LOGIC;
signal mul_temp_26_n_104 : STD_LOGIC;
signal mul_temp_26_n_105 : STD_LOGIC;
signal mul_temp_26_n_74 : STD_LOGIC;
signal mul_temp_26_n_75 : STD_LOGIC;
signal mul_temp_26_n_76 : STD_LOGIC;
signal mul_temp_26_n_77 : STD_LOGIC;
signal mul_temp_26_n_78 : STD_LOGIC;
signal mul_temp_26_n_79 : STD_LOGIC;
signal mul_temp_26_n_80 : STD_LOGIC;
signal mul_temp_26_n_81 : STD_LOGIC;
signal mul_temp_26_n_82 : STD_LOGIC;
signal mul_temp_26_n_83 : STD_LOGIC;
signal mul_temp_26_n_84 : STD_LOGIC;
signal mul_temp_26_n_85 : STD_LOGIC;
signal mul_temp_26_n_86 : STD_LOGIC;
signal mul_temp_26_n_87 : STD_LOGIC;
signal mul_temp_26_n_88 : STD_LOGIC;
signal mul_temp_26_n_89 : STD_LOGIC;
signal mul_temp_26_n_90 : STD_LOGIC;
signal mul_temp_26_n_92 : STD_LOGIC;
signal mul_temp_26_n_93 : STD_LOGIC;
signal mul_temp_26_n_94 : STD_LOGIC;
signal mul_temp_26_n_95 : STD_LOGIC;
signal mul_temp_26_n_96 : STD_LOGIC;
signal mul_temp_26_n_97 : STD_LOGIC;
signal mul_temp_26_n_98 : STD_LOGIC;
signal mul_temp_26_n_99 : STD_LOGIC;
signal \^mul_temp_27\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_27_n_100 : STD_LOGIC;
signal mul_temp_27_n_101 : STD_LOGIC;
signal mul_temp_27_n_102 : STD_LOGIC;
signal mul_temp_27_n_103 : STD_LOGIC;
signal mul_temp_27_n_104 : STD_LOGIC;
signal mul_temp_27_n_105 : STD_LOGIC;
signal mul_temp_27_n_74 : STD_LOGIC;
signal mul_temp_27_n_75 : STD_LOGIC;
signal mul_temp_27_n_76 : STD_LOGIC;
signal mul_temp_27_n_77 : STD_LOGIC;
signal mul_temp_27_n_78 : STD_LOGIC;
signal mul_temp_27_n_79 : STD_LOGIC;
signal mul_temp_27_n_80 : STD_LOGIC;
signal mul_temp_27_n_81 : STD_LOGIC;
signal mul_temp_27_n_82 : STD_LOGIC;
signal mul_temp_27_n_83 : STD_LOGIC;
signal mul_temp_27_n_84 : STD_LOGIC;
signal mul_temp_27_n_85 : STD_LOGIC;
signal mul_temp_27_n_86 : STD_LOGIC;
signal mul_temp_27_n_87 : STD_LOGIC;
signal mul_temp_27_n_88 : STD_LOGIC;
signal mul_temp_27_n_89 : STD_LOGIC;
signal mul_temp_27_n_90 : STD_LOGIC;
signal mul_temp_27_n_92 : STD_LOGIC;
signal mul_temp_27_n_93 : STD_LOGIC;
signal mul_temp_27_n_94 : STD_LOGIC;
signal mul_temp_27_n_95 : STD_LOGIC;
signal mul_temp_27_n_96 : STD_LOGIC;
signal mul_temp_27_n_97 : STD_LOGIC;
signal mul_temp_27_n_98 : STD_LOGIC;
signal mul_temp_27_n_99 : STD_LOGIC;
signal \^mul_temp_28\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_28_n_100 : STD_LOGIC;
signal mul_temp_28_n_101 : STD_LOGIC;
signal mul_temp_28_n_102 : STD_LOGIC;
signal mul_temp_28_n_103 : STD_LOGIC;
signal mul_temp_28_n_104 : STD_LOGIC;
signal mul_temp_28_n_105 : STD_LOGIC;
signal mul_temp_28_n_74 : STD_LOGIC;
signal mul_temp_28_n_75 : STD_LOGIC;
signal mul_temp_28_n_76 : STD_LOGIC;
signal mul_temp_28_n_77 : STD_LOGIC;
signal mul_temp_28_n_78 : STD_LOGIC;
signal mul_temp_28_n_79 : STD_LOGIC;
signal mul_temp_28_n_80 : STD_LOGIC;
signal mul_temp_28_n_81 : STD_LOGIC;
signal mul_temp_28_n_82 : STD_LOGIC;
signal mul_temp_28_n_83 : STD_LOGIC;
signal mul_temp_28_n_84 : STD_LOGIC;
signal mul_temp_28_n_85 : STD_LOGIC;
signal mul_temp_28_n_86 : STD_LOGIC;
signal mul_temp_28_n_87 : STD_LOGIC;
signal mul_temp_28_n_88 : STD_LOGIC;
signal mul_temp_28_n_89 : STD_LOGIC;
signal mul_temp_28_n_90 : STD_LOGIC;
signal mul_temp_28_n_92 : STD_LOGIC;
signal mul_temp_28_n_93 : STD_LOGIC;
signal mul_temp_28_n_94 : STD_LOGIC;
signal mul_temp_28_n_95 : STD_LOGIC;
signal mul_temp_28_n_96 : STD_LOGIC;
signal mul_temp_28_n_97 : STD_LOGIC;
signal mul_temp_28_n_98 : STD_LOGIC;
signal mul_temp_28_n_99 : STD_LOGIC;
signal \^mul_temp_29\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_29_n_100 : STD_LOGIC;
signal mul_temp_29_n_101 : STD_LOGIC;
signal mul_temp_29_n_102 : STD_LOGIC;
signal mul_temp_29_n_103 : STD_LOGIC;
signal mul_temp_29_n_104 : STD_LOGIC;
signal mul_temp_29_n_105 : STD_LOGIC;
signal mul_temp_29_n_74 : STD_LOGIC;
signal mul_temp_29_n_75 : STD_LOGIC;
signal mul_temp_29_n_76 : STD_LOGIC;
signal mul_temp_29_n_77 : STD_LOGIC;
signal mul_temp_29_n_78 : STD_LOGIC;
signal mul_temp_29_n_79 : STD_LOGIC;
signal mul_temp_29_n_80 : STD_LOGIC;
signal mul_temp_29_n_81 : STD_LOGIC;
signal mul_temp_29_n_82 : STD_LOGIC;
signal mul_temp_29_n_83 : STD_LOGIC;
signal mul_temp_29_n_84 : STD_LOGIC;
signal mul_temp_29_n_85 : STD_LOGIC;
signal mul_temp_29_n_86 : STD_LOGIC;
signal mul_temp_29_n_87 : STD_LOGIC;
signal mul_temp_29_n_88 : STD_LOGIC;
signal mul_temp_29_n_89 : STD_LOGIC;
signal mul_temp_29_n_90 : STD_LOGIC;
signal mul_temp_29_n_92 : STD_LOGIC;
signal mul_temp_29_n_93 : STD_LOGIC;
signal mul_temp_29_n_94 : STD_LOGIC;
signal mul_temp_29_n_95 : STD_LOGIC;
signal mul_temp_29_n_96 : STD_LOGIC;
signal mul_temp_29_n_97 : STD_LOGIC;
signal mul_temp_29_n_98 : STD_LOGIC;
signal mul_temp_29_n_99 : STD_LOGIC;
signal mul_temp_2_n_100 : STD_LOGIC;
signal mul_temp_2_n_101 : STD_LOGIC;
signal mul_temp_2_n_102 : STD_LOGIC;
signal mul_temp_2_n_103 : STD_LOGIC;
signal mul_temp_2_n_104 : STD_LOGIC;
signal mul_temp_2_n_105 : STD_LOGIC;
signal mul_temp_2_n_74 : STD_LOGIC;
signal mul_temp_2_n_75 : STD_LOGIC;
signal mul_temp_2_n_76 : STD_LOGIC;
signal mul_temp_2_n_77 : STD_LOGIC;
signal mul_temp_2_n_78 : STD_LOGIC;
signal mul_temp_2_n_79 : STD_LOGIC;
signal mul_temp_2_n_80 : STD_LOGIC;
signal mul_temp_2_n_81 : STD_LOGIC;
signal mul_temp_2_n_82 : STD_LOGIC;
signal mul_temp_2_n_83 : STD_LOGIC;
signal mul_temp_2_n_84 : STD_LOGIC;
signal mul_temp_2_n_85 : STD_LOGIC;
signal mul_temp_2_n_86 : STD_LOGIC;
signal mul_temp_2_n_87 : STD_LOGIC;
signal mul_temp_2_n_88 : STD_LOGIC;
signal mul_temp_2_n_89 : STD_LOGIC;
signal mul_temp_2_n_90 : STD_LOGIC;
signal mul_temp_2_n_92 : STD_LOGIC;
signal mul_temp_2_n_93 : STD_LOGIC;
signal mul_temp_2_n_94 : STD_LOGIC;
signal mul_temp_2_n_95 : STD_LOGIC;
signal mul_temp_2_n_96 : STD_LOGIC;
signal mul_temp_2_n_97 : STD_LOGIC;
signal mul_temp_2_n_98 : STD_LOGIC;
signal mul_temp_2_n_99 : STD_LOGIC;
signal \^mul_temp_3\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_30\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_30_n_100 : STD_LOGIC;
signal mul_temp_30_n_101 : STD_LOGIC;
signal mul_temp_30_n_102 : STD_LOGIC;
signal mul_temp_30_n_103 : STD_LOGIC;
signal mul_temp_30_n_104 : STD_LOGIC;
signal mul_temp_30_n_105 : STD_LOGIC;
signal mul_temp_30_n_74 : STD_LOGIC;
signal mul_temp_30_n_75 : STD_LOGIC;
signal mul_temp_30_n_76 : STD_LOGIC;
signal mul_temp_30_n_77 : STD_LOGIC;
signal mul_temp_30_n_78 : STD_LOGIC;
signal mul_temp_30_n_79 : STD_LOGIC;
signal mul_temp_30_n_80 : STD_LOGIC;
signal mul_temp_30_n_81 : STD_LOGIC;
signal mul_temp_30_n_82 : STD_LOGIC;
signal mul_temp_30_n_83 : STD_LOGIC;
signal mul_temp_30_n_84 : STD_LOGIC;
signal mul_temp_30_n_85 : STD_LOGIC;
signal mul_temp_30_n_86 : STD_LOGIC;
signal mul_temp_30_n_87 : STD_LOGIC;
signal mul_temp_30_n_88 : STD_LOGIC;
signal mul_temp_30_n_89 : STD_LOGIC;
signal mul_temp_30_n_90 : STD_LOGIC;
signal mul_temp_30_n_92 : STD_LOGIC;
signal mul_temp_30_n_93 : STD_LOGIC;
signal mul_temp_30_n_94 : STD_LOGIC;
signal mul_temp_30_n_95 : STD_LOGIC;
signal mul_temp_30_n_96 : STD_LOGIC;
signal mul_temp_30_n_97 : STD_LOGIC;
signal mul_temp_30_n_98 : STD_LOGIC;
signal mul_temp_30_n_99 : STD_LOGIC;
signal \^mul_temp_31\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_31_n_100 : STD_LOGIC;
signal mul_temp_31_n_101 : STD_LOGIC;
signal mul_temp_31_n_102 : STD_LOGIC;
signal mul_temp_31_n_103 : STD_LOGIC;
signal mul_temp_31_n_104 : STD_LOGIC;
signal mul_temp_31_n_105 : STD_LOGIC;
signal mul_temp_31_n_74 : STD_LOGIC;
signal mul_temp_31_n_75 : STD_LOGIC;
signal mul_temp_31_n_76 : STD_LOGIC;
signal mul_temp_31_n_77 : STD_LOGIC;
signal mul_temp_31_n_78 : STD_LOGIC;
signal mul_temp_31_n_79 : STD_LOGIC;
signal mul_temp_31_n_80 : STD_LOGIC;
signal mul_temp_31_n_81 : STD_LOGIC;
signal mul_temp_31_n_82 : STD_LOGIC;
signal mul_temp_31_n_83 : STD_LOGIC;
signal mul_temp_31_n_84 : STD_LOGIC;
signal mul_temp_31_n_85 : STD_LOGIC;
signal mul_temp_31_n_86 : STD_LOGIC;
signal mul_temp_31_n_87 : STD_LOGIC;
signal mul_temp_31_n_88 : STD_LOGIC;
signal mul_temp_31_n_89 : STD_LOGIC;
signal mul_temp_31_n_90 : STD_LOGIC;
signal mul_temp_31_n_92 : STD_LOGIC;
signal mul_temp_31_n_93 : STD_LOGIC;
signal mul_temp_31_n_94 : STD_LOGIC;
signal mul_temp_31_n_95 : STD_LOGIC;
signal mul_temp_31_n_96 : STD_LOGIC;
signal mul_temp_31_n_97 : STD_LOGIC;
signal mul_temp_31_n_98 : STD_LOGIC;
signal mul_temp_31_n_99 : STD_LOGIC;
signal \^mul_temp_32\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_32_n_100 : STD_LOGIC;
signal mul_temp_32_n_101 : STD_LOGIC;
signal mul_temp_32_n_102 : STD_LOGIC;
signal mul_temp_32_n_103 : STD_LOGIC;
signal mul_temp_32_n_104 : STD_LOGIC;
signal mul_temp_32_n_105 : STD_LOGIC;
signal mul_temp_32_n_74 : STD_LOGIC;
signal mul_temp_32_n_75 : STD_LOGIC;
signal mul_temp_32_n_76 : STD_LOGIC;
signal mul_temp_32_n_77 : STD_LOGIC;
signal mul_temp_32_n_78 : STD_LOGIC;
signal mul_temp_32_n_79 : STD_LOGIC;
signal mul_temp_32_n_80 : STD_LOGIC;
signal mul_temp_32_n_81 : STD_LOGIC;
signal mul_temp_32_n_82 : STD_LOGIC;
signal mul_temp_32_n_83 : STD_LOGIC;
signal mul_temp_32_n_84 : STD_LOGIC;
signal mul_temp_32_n_85 : STD_LOGIC;
signal mul_temp_32_n_86 : STD_LOGIC;
signal mul_temp_32_n_87 : STD_LOGIC;
signal mul_temp_32_n_88 : STD_LOGIC;
signal mul_temp_32_n_89 : STD_LOGIC;
signal mul_temp_32_n_90 : STD_LOGIC;
signal mul_temp_32_n_92 : STD_LOGIC;
signal mul_temp_32_n_93 : STD_LOGIC;
signal mul_temp_32_n_94 : STD_LOGIC;
signal mul_temp_32_n_95 : STD_LOGIC;
signal mul_temp_32_n_96 : STD_LOGIC;
signal mul_temp_32_n_97 : STD_LOGIC;
signal mul_temp_32_n_98 : STD_LOGIC;
signal mul_temp_32_n_99 : STD_LOGIC;
signal mul_temp_3_n_100 : STD_LOGIC;
signal mul_temp_3_n_101 : STD_LOGIC;
signal mul_temp_3_n_102 : STD_LOGIC;
signal mul_temp_3_n_103 : STD_LOGIC;
signal mul_temp_3_n_104 : STD_LOGIC;
signal mul_temp_3_n_105 : STD_LOGIC;
signal mul_temp_3_n_74 : STD_LOGIC;
signal mul_temp_3_n_75 : STD_LOGIC;
signal mul_temp_3_n_76 : STD_LOGIC;
signal mul_temp_3_n_77 : STD_LOGIC;
signal mul_temp_3_n_78 : STD_LOGIC;
signal mul_temp_3_n_79 : STD_LOGIC;
signal mul_temp_3_n_80 : STD_LOGIC;
signal mul_temp_3_n_81 : STD_LOGIC;
signal mul_temp_3_n_82 : STD_LOGIC;
signal mul_temp_3_n_83 : STD_LOGIC;
signal mul_temp_3_n_84 : STD_LOGIC;
signal mul_temp_3_n_85 : STD_LOGIC;
signal mul_temp_3_n_86 : STD_LOGIC;
signal mul_temp_3_n_87 : STD_LOGIC;
signal mul_temp_3_n_88 : STD_LOGIC;
signal mul_temp_3_n_89 : STD_LOGIC;
signal mul_temp_3_n_90 : STD_LOGIC;
signal mul_temp_3_n_92 : STD_LOGIC;
signal mul_temp_3_n_93 : STD_LOGIC;
signal mul_temp_3_n_94 : STD_LOGIC;
signal mul_temp_3_n_95 : STD_LOGIC;
signal mul_temp_3_n_96 : STD_LOGIC;
signal mul_temp_3_n_97 : STD_LOGIC;
signal mul_temp_3_n_98 : STD_LOGIC;
signal mul_temp_3_n_99 : STD_LOGIC;
signal \^mul_temp_4\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_4_n_100 : STD_LOGIC;
signal mul_temp_4_n_101 : STD_LOGIC;
signal mul_temp_4_n_102 : STD_LOGIC;
signal mul_temp_4_n_103 : STD_LOGIC;
signal mul_temp_4_n_104 : STD_LOGIC;
signal mul_temp_4_n_105 : STD_LOGIC;
signal mul_temp_4_n_74 : STD_LOGIC;
signal mul_temp_4_n_75 : STD_LOGIC;
signal mul_temp_4_n_76 : STD_LOGIC;
signal mul_temp_4_n_77 : STD_LOGIC;
signal mul_temp_4_n_78 : STD_LOGIC;
signal mul_temp_4_n_79 : STD_LOGIC;
signal mul_temp_4_n_80 : STD_LOGIC;
signal mul_temp_4_n_81 : STD_LOGIC;
signal mul_temp_4_n_82 : STD_LOGIC;
signal mul_temp_4_n_83 : STD_LOGIC;
signal mul_temp_4_n_84 : STD_LOGIC;
signal mul_temp_4_n_85 : STD_LOGIC;
signal mul_temp_4_n_86 : STD_LOGIC;
signal mul_temp_4_n_87 : STD_LOGIC;
signal mul_temp_4_n_88 : STD_LOGIC;
signal mul_temp_4_n_89 : STD_LOGIC;
signal mul_temp_4_n_90 : STD_LOGIC;
signal mul_temp_4_n_92 : STD_LOGIC;
signal mul_temp_4_n_93 : STD_LOGIC;
signal mul_temp_4_n_94 : STD_LOGIC;
signal mul_temp_4_n_95 : STD_LOGIC;
signal mul_temp_4_n_96 : STD_LOGIC;
signal mul_temp_4_n_97 : STD_LOGIC;
signal mul_temp_4_n_98 : STD_LOGIC;
signal mul_temp_4_n_99 : STD_LOGIC;
signal \^mul_temp_5\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_5_n_100 : STD_LOGIC;
signal mul_temp_5_n_101 : STD_LOGIC;
signal mul_temp_5_n_102 : STD_LOGIC;
signal mul_temp_5_n_103 : STD_LOGIC;
signal mul_temp_5_n_104 : STD_LOGIC;
signal mul_temp_5_n_105 : STD_LOGIC;
signal mul_temp_5_n_74 : STD_LOGIC;
signal mul_temp_5_n_75 : STD_LOGIC;
signal mul_temp_5_n_76 : STD_LOGIC;
signal mul_temp_5_n_77 : STD_LOGIC;
signal mul_temp_5_n_78 : STD_LOGIC;
signal mul_temp_5_n_79 : STD_LOGIC;
signal mul_temp_5_n_80 : STD_LOGIC;
signal mul_temp_5_n_81 : STD_LOGIC;
signal mul_temp_5_n_82 : STD_LOGIC;
signal mul_temp_5_n_83 : STD_LOGIC;
signal mul_temp_5_n_84 : STD_LOGIC;
signal mul_temp_5_n_85 : STD_LOGIC;
signal mul_temp_5_n_86 : STD_LOGIC;
signal mul_temp_5_n_87 : STD_LOGIC;
signal mul_temp_5_n_88 : STD_LOGIC;
signal mul_temp_5_n_89 : STD_LOGIC;
signal mul_temp_5_n_90 : STD_LOGIC;
signal mul_temp_5_n_92 : STD_LOGIC;
signal mul_temp_5_n_93 : STD_LOGIC;
signal mul_temp_5_n_94 : STD_LOGIC;
signal mul_temp_5_n_95 : STD_LOGIC;
signal mul_temp_5_n_96 : STD_LOGIC;
signal mul_temp_5_n_97 : STD_LOGIC;
signal mul_temp_5_n_98 : STD_LOGIC;
signal mul_temp_5_n_99 : STD_LOGIC;
signal \^mul_temp_6\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_6_n_100 : STD_LOGIC;
signal mul_temp_6_n_101 : STD_LOGIC;
signal mul_temp_6_n_102 : STD_LOGIC;
signal mul_temp_6_n_103 : STD_LOGIC;
signal mul_temp_6_n_104 : STD_LOGIC;
signal mul_temp_6_n_105 : STD_LOGIC;
signal mul_temp_6_n_74 : STD_LOGIC;
signal mul_temp_6_n_75 : STD_LOGIC;
signal mul_temp_6_n_76 : STD_LOGIC;
signal mul_temp_6_n_77 : STD_LOGIC;
signal mul_temp_6_n_78 : STD_LOGIC;
signal mul_temp_6_n_79 : STD_LOGIC;
signal mul_temp_6_n_80 : STD_LOGIC;
signal mul_temp_6_n_81 : STD_LOGIC;
signal mul_temp_6_n_82 : STD_LOGIC;
signal mul_temp_6_n_83 : STD_LOGIC;
signal mul_temp_6_n_84 : STD_LOGIC;
signal mul_temp_6_n_85 : STD_LOGIC;
signal mul_temp_6_n_86 : STD_LOGIC;
signal mul_temp_6_n_87 : STD_LOGIC;
signal mul_temp_6_n_88 : STD_LOGIC;
signal mul_temp_6_n_89 : STD_LOGIC;
signal mul_temp_6_n_90 : STD_LOGIC;
signal mul_temp_6_n_92 : STD_LOGIC;
signal mul_temp_6_n_93 : STD_LOGIC;
signal mul_temp_6_n_94 : STD_LOGIC;
signal mul_temp_6_n_95 : STD_LOGIC;
signal mul_temp_6_n_96 : STD_LOGIC;
signal mul_temp_6_n_97 : STD_LOGIC;
signal mul_temp_6_n_98 : STD_LOGIC;
signal mul_temp_6_n_99 : STD_LOGIC;
signal \^mul_temp_7\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_7_n_100 : STD_LOGIC;
signal mul_temp_7_n_101 : STD_LOGIC;
signal mul_temp_7_n_102 : STD_LOGIC;
signal mul_temp_7_n_103 : STD_LOGIC;
signal mul_temp_7_n_104 : STD_LOGIC;
signal mul_temp_7_n_105 : STD_LOGIC;
signal mul_temp_7_n_74 : STD_LOGIC;
signal mul_temp_7_n_75 : STD_LOGIC;
signal mul_temp_7_n_76 : STD_LOGIC;
signal mul_temp_7_n_77 : STD_LOGIC;
signal mul_temp_7_n_78 : STD_LOGIC;
signal mul_temp_7_n_79 : STD_LOGIC;
signal mul_temp_7_n_80 : STD_LOGIC;
signal mul_temp_7_n_81 : STD_LOGIC;
signal mul_temp_7_n_82 : STD_LOGIC;
signal mul_temp_7_n_83 : STD_LOGIC;
signal mul_temp_7_n_84 : STD_LOGIC;
signal mul_temp_7_n_85 : STD_LOGIC;
signal mul_temp_7_n_86 : STD_LOGIC;
signal mul_temp_7_n_87 : STD_LOGIC;
signal mul_temp_7_n_88 : STD_LOGIC;
signal mul_temp_7_n_89 : STD_LOGIC;
signal mul_temp_7_n_90 : STD_LOGIC;
signal mul_temp_7_n_92 : STD_LOGIC;
signal mul_temp_7_n_93 : STD_LOGIC;
signal mul_temp_7_n_94 : STD_LOGIC;
signal mul_temp_7_n_95 : STD_LOGIC;
signal mul_temp_7_n_96 : STD_LOGIC;
signal mul_temp_7_n_97 : STD_LOGIC;
signal mul_temp_7_n_98 : STD_LOGIC;
signal mul_temp_7_n_99 : STD_LOGIC;
signal \^mul_temp_8\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_8_n_100 : STD_LOGIC;
signal mul_temp_8_n_101 : STD_LOGIC;
signal mul_temp_8_n_102 : STD_LOGIC;
signal mul_temp_8_n_103 : STD_LOGIC;
signal mul_temp_8_n_104 : STD_LOGIC;
signal mul_temp_8_n_105 : STD_LOGIC;
signal mul_temp_8_n_74 : STD_LOGIC;
signal mul_temp_8_n_75 : STD_LOGIC;
signal mul_temp_8_n_76 : STD_LOGIC;
signal mul_temp_8_n_77 : STD_LOGIC;
signal mul_temp_8_n_78 : STD_LOGIC;
signal mul_temp_8_n_79 : STD_LOGIC;
signal mul_temp_8_n_80 : STD_LOGIC;
signal mul_temp_8_n_81 : STD_LOGIC;
signal mul_temp_8_n_82 : STD_LOGIC;
signal mul_temp_8_n_83 : STD_LOGIC;
signal mul_temp_8_n_84 : STD_LOGIC;
signal mul_temp_8_n_85 : STD_LOGIC;
signal mul_temp_8_n_86 : STD_LOGIC;
signal mul_temp_8_n_87 : STD_LOGIC;
signal mul_temp_8_n_88 : STD_LOGIC;
signal mul_temp_8_n_89 : STD_LOGIC;
signal mul_temp_8_n_90 : STD_LOGIC;
signal mul_temp_8_n_92 : STD_LOGIC;
signal mul_temp_8_n_93 : STD_LOGIC;
signal mul_temp_8_n_94 : STD_LOGIC;
signal mul_temp_8_n_95 : STD_LOGIC;
signal mul_temp_8_n_96 : STD_LOGIC;
signal mul_temp_8_n_97 : STD_LOGIC;
signal mul_temp_8_n_98 : STD_LOGIC;
signal mul_temp_8_n_99 : STD_LOGIC;
signal \^mul_temp_9\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_9_n_100 : STD_LOGIC;
signal mul_temp_9_n_101 : STD_LOGIC;
signal mul_temp_9_n_102 : STD_LOGIC;
signal mul_temp_9_n_103 : STD_LOGIC;
signal mul_temp_9_n_104 : STD_LOGIC;
signal mul_temp_9_n_105 : STD_LOGIC;
signal mul_temp_9_n_74 : STD_LOGIC;
signal mul_temp_9_n_75 : STD_LOGIC;
signal mul_temp_9_n_76 : STD_LOGIC;
signal mul_temp_9_n_77 : STD_LOGIC;
signal mul_temp_9_n_78 : STD_LOGIC;
signal mul_temp_9_n_79 : STD_LOGIC;
signal mul_temp_9_n_80 : STD_LOGIC;
signal mul_temp_9_n_81 : STD_LOGIC;
signal mul_temp_9_n_82 : STD_LOGIC;
signal mul_temp_9_n_83 : STD_LOGIC;
signal mul_temp_9_n_84 : STD_LOGIC;
signal mul_temp_9_n_85 : STD_LOGIC;
signal mul_temp_9_n_86 : STD_LOGIC;
signal mul_temp_9_n_87 : STD_LOGIC;
signal mul_temp_9_n_88 : STD_LOGIC;
signal mul_temp_9_n_89 : STD_LOGIC;
signal mul_temp_9_n_90 : STD_LOGIC;
signal mul_temp_9_n_92 : STD_LOGIC;
signal mul_temp_9_n_93 : STD_LOGIC;
signal mul_temp_9_n_94 : STD_LOGIC;
signal mul_temp_9_n_95 : STD_LOGIC;
signal mul_temp_9_n_96 : STD_LOGIC;
signal mul_temp_9_n_97 : STD_LOGIC;
signal mul_temp_9_n_98 : STD_LOGIC;
signal mul_temp_9_n_99 : STD_LOGIC;
signal mul_temp_n_100 : STD_LOGIC;
signal mul_temp_n_101 : STD_LOGIC;
signal mul_temp_n_102 : STD_LOGIC;
signal mul_temp_n_103 : STD_LOGIC;
signal mul_temp_n_104 : STD_LOGIC;
signal mul_temp_n_105 : STD_LOGIC;
signal mul_temp_n_74 : STD_LOGIC;
signal mul_temp_n_75 : STD_LOGIC;
signal mul_temp_n_76 : STD_LOGIC;
signal mul_temp_n_77 : STD_LOGIC;
signal mul_temp_n_78 : STD_LOGIC;
signal mul_temp_n_79 : STD_LOGIC;
signal mul_temp_n_80 : STD_LOGIC;
signal mul_temp_n_81 : STD_LOGIC;
signal mul_temp_n_82 : STD_LOGIC;
signal mul_temp_n_83 : STD_LOGIC;
signal mul_temp_n_84 : STD_LOGIC;
signal mul_temp_n_85 : STD_LOGIC;
signal mul_temp_n_86 : STD_LOGIC;
signal mul_temp_n_87 : STD_LOGIC;
signal mul_temp_n_88 : STD_LOGIC;
signal mul_temp_n_89 : STD_LOGIC;
signal mul_temp_n_90 : STD_LOGIC;
signal mul_temp_n_92 : STD_LOGIC;
signal mul_temp_n_93 : STD_LOGIC;
signal mul_temp_n_94 : STD_LOGIC;
signal mul_temp_n_95 : STD_LOGIC;
signal mul_temp_n_96 : STD_LOGIC;
signal mul_temp_n_97 : STD_LOGIC;
signal mul_temp_n_98 : STD_LOGIC;
signal mul_temp_n_99 : STD_LOGIC;
signal \sub_temp_carry__0_n_0\ : STD_LOGIC;
signal \sub_temp_carry__0_n_1\ : STD_LOGIC;
signal \sub_temp_carry__0_n_2\ : STD_LOGIC;
signal \sub_temp_carry__0_n_3\ : STD_LOGIC;
signal \sub_temp_carry__1_n_0\ : STD_LOGIC;
signal \sub_temp_carry__1_n_1\ : STD_LOGIC;
signal \sub_temp_carry__1_n_2\ : STD_LOGIC;
signal \sub_temp_carry__1_n_3\ : STD_LOGIC;
signal \sub_temp_carry__2_n_1\ : STD_LOGIC;
signal \sub_temp_carry__2_n_2\ : STD_LOGIC;
signal \sub_temp_carry__2_n_3\ : STD_LOGIC;
signal sub_temp_carry_n_0 : STD_LOGIC;
signal sub_temp_carry_n_1 : STD_LOGIC;
signal sub_temp_carry_n_2 : STD_LOGIC;
signal sub_temp_carry_n_3 : STD_LOGIC;
signal \weight[0][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_5_n_0\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0]_15\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[10][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10]_9\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[11][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11]_10\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[12][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12]_11\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[13][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13]_12\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[14][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14]_13\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[15][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15]_14\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[1][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[2][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2]_1\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[3][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3]_2\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[4][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4]_3\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[5][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5]_4\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[6][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6]_5\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[7][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7]_6\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[8][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8]_7\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[9][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9]_8\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_ARG_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_ARG_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_ARG_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_ARG_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 30 );
signal NLW_ARG_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__0_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__1_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__1_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__1_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__1_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__1_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__10_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__10_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__10_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__10_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__10_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__11_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__11_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__11_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__11_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__11_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__12_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__12_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__12_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__12_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__12_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__13_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__13_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__13_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__13_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__13_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__14_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__14_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__14_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__14_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__14_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__15_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__15_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__15_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__15_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__15_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__16_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__16_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__16_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__16_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__16_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__17_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__17_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__17_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__17_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__17_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__18_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__18_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__18_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__18_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__18_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__19_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__19_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__19_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__19_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__19_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__2_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__2_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__2_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__2_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__2_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__20_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__20_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__20_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__20_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__20_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__21_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__21_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__21_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__21_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__21_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__22_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__22_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__22_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__22_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__22_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__23_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__23_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__23_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__23_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__23_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__24_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__24_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__24_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__24_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__24_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__25_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__25_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__25_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__25_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__25_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__26_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__26_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__26_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__26_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__26_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__27_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__27_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__27_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__27_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__27_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__28_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__28_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__28_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__28_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__28_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__29_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__29_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__29_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__29_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__29_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__3_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__3_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__3_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__3_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__3_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__30_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__30_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__30_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__30_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__30_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__4_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__4_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__4_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__4_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__4_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__5_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__5_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__5_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__5_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__5_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__6_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__6_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__6_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__6_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__6_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__7_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__7_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__7_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__7_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__7_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__8_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__8_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__8_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__8_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__8_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__9_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__9_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__9_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__9_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__9_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_ARG_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG_carry__3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_ARG_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_add_temp_14__0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__138_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__184_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__230_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__278_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__46_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__92_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_mul_temp_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_1_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_1_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_1_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_1_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_1_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_10_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_10_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_10_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_10_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_10_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_11_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_11_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_11_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_11_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_11_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_12_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_12_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_12_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_12_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_12_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_13_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_13_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_13_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_13_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_13_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_14_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_14_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_14_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_14_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_14_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_15_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_15_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_15_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_15_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_15_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_17_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_17_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_17_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_17_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_17_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_18_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_18_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_18_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_18_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_18_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_19_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_19_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_19_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_19_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_19_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_2_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_2_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_2_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_2_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_2_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_20_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_20_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_20_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_20_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_20_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_21_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_21_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_21_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_21_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_21_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_22_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_22_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_22_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_22_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_22_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_23_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_23_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_23_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_23_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_23_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_24_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_24_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_24_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_24_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_24_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_25_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_25_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_25_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_25_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_25_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_26_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_26_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_26_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_26_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_26_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_27_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_27_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_27_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_27_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_27_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_28_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_28_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_28_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_28_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_28_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_29_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_29_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_29_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_29_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_29_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_3_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_3_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_3_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_3_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_3_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_30_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_30_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_30_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_30_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_30_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_31_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_31_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_31_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_31_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_31_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_32_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_32_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_32_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_32_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_32_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_4_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_4_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_4_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_4_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_4_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_5_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_5_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_5_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_5_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_5_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_6_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_6_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_6_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_6_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_6_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_7_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_7_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_7_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_7_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_7_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_8_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_8_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_8_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_8_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_8_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_9_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_9_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_9_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_9_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_9_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_sub_temp_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[0][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[10][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[11][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[12][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[13][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[14][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[15][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[1][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[2][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[3][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[4][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[5][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[6][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[7][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[8][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[9][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of ARG : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__0\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__1\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__10\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__11\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__12\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__13\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__14\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__15\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__16\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__17\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__18\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__19\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__2\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__20\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__21\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__22\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__23\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__24\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__25\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__26\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__27\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__28\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__29\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__3\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__30\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__4\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__5\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__6\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__7\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__8\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__9\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute HLUTNM : string;
attribute HLUTNM of \add_temp_14__0_carry__0_i_1\ : label is "lutpair6";
attribute HLUTNM of \add_temp_14__0_carry__0_i_2\ : label is "lutpair5";
attribute HLUTNM of \add_temp_14__0_carry__0_i_3\ : label is "lutpair4";
attribute HLUTNM of \add_temp_14__0_carry__0_i_4\ : label is "lutpair3";
attribute HLUTNM of \add_temp_14__0_carry__0_i_5\ : label is "lutpair7";
attribute HLUTNM of \add_temp_14__0_carry__0_i_6\ : label is "lutpair6";
attribute HLUTNM of \add_temp_14__0_carry__0_i_7\ : label is "lutpair5";
attribute HLUTNM of \add_temp_14__0_carry__0_i_8\ : label is "lutpair4";
attribute HLUTNM of \add_temp_14__0_carry__1_i_1\ : label is "lutpair10";
attribute HLUTNM of \add_temp_14__0_carry__1_i_2\ : label is "lutpair9";
attribute HLUTNM of \add_temp_14__0_carry__1_i_3\ : label is "lutpair8";
attribute HLUTNM of \add_temp_14__0_carry__1_i_4\ : label is "lutpair7";
attribute HLUTNM of \add_temp_14__0_carry__1_i_5\ : label is "lutpair11";
attribute HLUTNM of \add_temp_14__0_carry__1_i_6\ : label is "lutpair10";
attribute HLUTNM of \add_temp_14__0_carry__1_i_7\ : label is "lutpair9";
attribute HLUTNM of \add_temp_14__0_carry__1_i_8\ : label is "lutpair8";
attribute HLUTNM of \add_temp_14__0_carry__2_i_1\ : label is "lutpair13";
attribute HLUTNM of \add_temp_14__0_carry__2_i_2\ : label is "lutpair12";
attribute HLUTNM of \add_temp_14__0_carry__2_i_3\ : label is "lutpair11";
attribute HLUTNM of \add_temp_14__0_carry__2_i_6\ : label is "lutpair13";
attribute HLUTNM of \add_temp_14__0_carry__2_i_7\ : label is "lutpair12";
attribute HLUTNM of \add_temp_14__0_carry_i_1\ : label is "lutpair2";
attribute HLUTNM of \add_temp_14__0_carry_i_2\ : label is "lutpair1";
attribute HLUTNM of \add_temp_14__0_carry_i_3\ : label is "lutpair0";
attribute HLUTNM of \add_temp_14__0_carry_i_4\ : label is "lutpair3";
attribute HLUTNM of \add_temp_14__0_carry_i_5\ : label is "lutpair2";
attribute HLUTNM of \add_temp_14__0_carry_i_6\ : label is "lutpair1";
attribute HLUTNM of \add_temp_14__0_carry_i_7\ : label is "lutpair0";
attribute HLUTNM of \add_temp_14__138_carry__0_i_1\ : label is "lutpair48";
attribute HLUTNM of \add_temp_14__138_carry__0_i_2\ : label is "lutpair47";
attribute HLUTNM of \add_temp_14__138_carry__0_i_3\ : label is "lutpair46";
attribute HLUTNM of \add_temp_14__138_carry__0_i_4\ : label is "lutpair45";
attribute HLUTNM of \add_temp_14__138_carry__0_i_5\ : label is "lutpair49";
attribute HLUTNM of \add_temp_14__138_carry__0_i_6\ : label is "lutpair48";
attribute HLUTNM of \add_temp_14__138_carry__0_i_7\ : label is "lutpair47";
attribute HLUTNM of \add_temp_14__138_carry__0_i_8\ : label is "lutpair46";
attribute HLUTNM of \add_temp_14__138_carry__1_i_1\ : label is "lutpair52";
attribute HLUTNM of \add_temp_14__138_carry__1_i_2\ : label is "lutpair51";
attribute HLUTNM of \add_temp_14__138_carry__1_i_3\ : label is "lutpair50";
attribute HLUTNM of \add_temp_14__138_carry__1_i_4\ : label is "lutpair49";
attribute HLUTNM of \add_temp_14__138_carry__1_i_5\ : label is "lutpair53";
attribute HLUTNM of \add_temp_14__138_carry__1_i_6\ : label is "lutpair52";
attribute HLUTNM of \add_temp_14__138_carry__1_i_7\ : label is "lutpair51";
attribute HLUTNM of \add_temp_14__138_carry__1_i_8\ : label is "lutpair50";
attribute HLUTNM of \add_temp_14__138_carry__2_i_1\ : label is "lutpair55";
attribute HLUTNM of \add_temp_14__138_carry__2_i_2\ : label is "lutpair54";
attribute HLUTNM of \add_temp_14__138_carry__2_i_3\ : label is "lutpair53";
attribute HLUTNM of \add_temp_14__138_carry__2_i_6\ : label is "lutpair55";
attribute HLUTNM of \add_temp_14__138_carry__2_i_7\ : label is "lutpair54";
attribute HLUTNM of \add_temp_14__138_carry_i_1\ : label is "lutpair44";
attribute HLUTNM of \add_temp_14__138_carry_i_2\ : label is "lutpair43";
attribute HLUTNM of \add_temp_14__138_carry_i_3\ : label is "lutpair42";
attribute HLUTNM of \add_temp_14__138_carry_i_4\ : label is "lutpair45";
attribute HLUTNM of \add_temp_14__138_carry_i_5\ : label is "lutpair44";
attribute HLUTNM of \add_temp_14__138_carry_i_6\ : label is "lutpair43";
attribute HLUTNM of \add_temp_14__138_carry_i_7\ : label is "lutpair42";
attribute HLUTNM of \add_temp_14__184_carry__0_i_1\ : label is "lutpair62";
attribute HLUTNM of \add_temp_14__184_carry__0_i_2\ : label is "lutpair61";
attribute HLUTNM of \add_temp_14__184_carry__0_i_3\ : label is "lutpair60";
attribute HLUTNM of \add_temp_14__184_carry__0_i_4\ : label is "lutpair59";
attribute HLUTNM of \add_temp_14__184_carry__0_i_5\ : label is "lutpair63";
attribute HLUTNM of \add_temp_14__184_carry__0_i_6\ : label is "lutpair62";
attribute HLUTNM of \add_temp_14__184_carry__0_i_7\ : label is "lutpair61";
attribute HLUTNM of \add_temp_14__184_carry__0_i_8\ : label is "lutpair60";
attribute HLUTNM of \add_temp_14__184_carry__1_i_1\ : label is "lutpair66";
attribute HLUTNM of \add_temp_14__184_carry__1_i_2\ : label is "lutpair65";
attribute HLUTNM of \add_temp_14__184_carry__1_i_3\ : label is "lutpair64";
attribute HLUTNM of \add_temp_14__184_carry__1_i_4\ : label is "lutpair63";
attribute HLUTNM of \add_temp_14__184_carry__1_i_5\ : label is "lutpair67";
attribute HLUTNM of \add_temp_14__184_carry__1_i_6\ : label is "lutpair66";
attribute HLUTNM of \add_temp_14__184_carry__1_i_7\ : label is "lutpair65";
attribute HLUTNM of \add_temp_14__184_carry__1_i_8\ : label is "lutpair64";
attribute HLUTNM of \add_temp_14__184_carry__2_i_1\ : label is "lutpair69";
attribute HLUTNM of \add_temp_14__184_carry__2_i_2\ : label is "lutpair68";
attribute HLUTNM of \add_temp_14__184_carry__2_i_3\ : label is "lutpair67";
attribute HLUTNM of \add_temp_14__184_carry__2_i_6\ : label is "lutpair69";
attribute HLUTNM of \add_temp_14__184_carry__2_i_7\ : label is "lutpair68";
attribute HLUTNM of \add_temp_14__184_carry_i_1\ : label is "lutpair58";
attribute HLUTNM of \add_temp_14__184_carry_i_2\ : label is "lutpair57";
attribute HLUTNM of \add_temp_14__184_carry_i_3\ : label is "lutpair56";
attribute HLUTNM of \add_temp_14__184_carry_i_4\ : label is "lutpair59";
attribute HLUTNM of \add_temp_14__184_carry_i_5\ : label is "lutpair58";
attribute HLUTNM of \add_temp_14__184_carry_i_6\ : label is "lutpair57";
attribute HLUTNM of \add_temp_14__184_carry_i_7\ : label is "lutpair56";
attribute HLUTNM of \add_temp_14__230_carry__0_i_1\ : label is "lutpair76";
attribute HLUTNM of \add_temp_14__230_carry__0_i_2\ : label is "lutpair75";
attribute HLUTNM of \add_temp_14__230_carry__0_i_3\ : label is "lutpair74";
attribute HLUTNM of \add_temp_14__230_carry__0_i_4\ : label is "lutpair73";
attribute HLUTNM of \add_temp_14__230_carry__0_i_5\ : label is "lutpair77";
attribute HLUTNM of \add_temp_14__230_carry__0_i_6\ : label is "lutpair76";
attribute HLUTNM of \add_temp_14__230_carry__0_i_7\ : label is "lutpair75";
attribute HLUTNM of \add_temp_14__230_carry__0_i_8\ : label is "lutpair74";
attribute HLUTNM of \add_temp_14__230_carry__1_i_1\ : label is "lutpair80";
attribute HLUTNM of \add_temp_14__230_carry__1_i_2\ : label is "lutpair79";
attribute HLUTNM of \add_temp_14__230_carry__1_i_3\ : label is "lutpair78";
attribute HLUTNM of \add_temp_14__230_carry__1_i_4\ : label is "lutpair77";
attribute HLUTNM of \add_temp_14__230_carry__1_i_5\ : label is "lutpair81";
attribute HLUTNM of \add_temp_14__230_carry__1_i_6\ : label is "lutpair80";
attribute HLUTNM of \add_temp_14__230_carry__1_i_7\ : label is "lutpair79";
attribute HLUTNM of \add_temp_14__230_carry__1_i_8\ : label is "lutpair78";
attribute HLUTNM of \add_temp_14__230_carry__2_i_1\ : label is "lutpair83";
attribute HLUTNM of \add_temp_14__230_carry__2_i_2\ : label is "lutpair82";
attribute HLUTNM of \add_temp_14__230_carry__2_i_3\ : label is "lutpair81";
attribute HLUTNM of \add_temp_14__230_carry__2_i_6\ : label is "lutpair83";
attribute HLUTNM of \add_temp_14__230_carry__2_i_7\ : label is "lutpair82";
attribute HLUTNM of \add_temp_14__230_carry_i_1\ : label is "lutpair72";
attribute HLUTNM of \add_temp_14__230_carry_i_2\ : label is "lutpair71";
attribute HLUTNM of \add_temp_14__230_carry_i_3\ : label is "lutpair70";
attribute HLUTNM of \add_temp_14__230_carry_i_4\ : label is "lutpair73";
attribute HLUTNM of \add_temp_14__230_carry_i_5\ : label is "lutpair72";
attribute HLUTNM of \add_temp_14__230_carry_i_6\ : label is "lutpair71";
attribute HLUTNM of \add_temp_14__230_carry_i_7\ : label is "lutpair70";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \add_temp_14__278_carry__1_i_10\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \add_temp_14__278_carry__1_i_11\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \add_temp_14__278_carry__2_i_8\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \add_temp_14__278_carry__2_i_9\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \add_temp_14__278_carry_i_10\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \add_temp_14__278_carry_i_9\ : label is "soft_lutpair6";
attribute HLUTNM of \add_temp_14__46_carry__0_i_1\ : label is "lutpair20";
attribute HLUTNM of \add_temp_14__46_carry__0_i_2\ : label is "lutpair19";
attribute HLUTNM of \add_temp_14__46_carry__0_i_3\ : label is "lutpair18";
attribute HLUTNM of \add_temp_14__46_carry__0_i_4\ : label is "lutpair17";
attribute HLUTNM of \add_temp_14__46_carry__0_i_5\ : label is "lutpair21";
attribute HLUTNM of \add_temp_14__46_carry__0_i_6\ : label is "lutpair20";
attribute HLUTNM of \add_temp_14__46_carry__0_i_7\ : label is "lutpair19";
attribute HLUTNM of \add_temp_14__46_carry__0_i_8\ : label is "lutpair18";
attribute HLUTNM of \add_temp_14__46_carry__1_i_1\ : label is "lutpair24";
attribute HLUTNM of \add_temp_14__46_carry__1_i_2\ : label is "lutpair23";
attribute HLUTNM of \add_temp_14__46_carry__1_i_3\ : label is "lutpair22";
attribute HLUTNM of \add_temp_14__46_carry__1_i_4\ : label is "lutpair21";
attribute HLUTNM of \add_temp_14__46_carry__1_i_5\ : label is "lutpair25";
attribute HLUTNM of \add_temp_14__46_carry__1_i_6\ : label is "lutpair24";
attribute HLUTNM of \add_temp_14__46_carry__1_i_7\ : label is "lutpair23";
attribute HLUTNM of \add_temp_14__46_carry__1_i_8\ : label is "lutpair22";
attribute HLUTNM of \add_temp_14__46_carry__2_i_1\ : label is "lutpair27";
attribute HLUTNM of \add_temp_14__46_carry__2_i_2\ : label is "lutpair26";
attribute HLUTNM of \add_temp_14__46_carry__2_i_3\ : label is "lutpair25";
attribute HLUTNM of \add_temp_14__46_carry__2_i_6\ : label is "lutpair27";
attribute HLUTNM of \add_temp_14__46_carry__2_i_7\ : label is "lutpair26";
attribute HLUTNM of \add_temp_14__46_carry_i_1\ : label is "lutpair16";
attribute HLUTNM of \add_temp_14__46_carry_i_2\ : label is "lutpair15";
attribute HLUTNM of \add_temp_14__46_carry_i_3\ : label is "lutpair14";
attribute HLUTNM of \add_temp_14__46_carry_i_4\ : label is "lutpair17";
attribute HLUTNM of \add_temp_14__46_carry_i_5\ : label is "lutpair16";
attribute HLUTNM of \add_temp_14__46_carry_i_6\ : label is "lutpair15";
attribute HLUTNM of \add_temp_14__46_carry_i_7\ : label is "lutpair14";
attribute HLUTNM of \add_temp_14__92_carry__0_i_1\ : label is "lutpair34";
attribute HLUTNM of \add_temp_14__92_carry__0_i_2\ : label is "lutpair33";
attribute HLUTNM of \add_temp_14__92_carry__0_i_3\ : label is "lutpair32";
attribute HLUTNM of \add_temp_14__92_carry__0_i_4\ : label is "lutpair31";
attribute HLUTNM of \add_temp_14__92_carry__0_i_5\ : label is "lutpair35";
attribute HLUTNM of \add_temp_14__92_carry__0_i_6\ : label is "lutpair34";
attribute HLUTNM of \add_temp_14__92_carry__0_i_7\ : label is "lutpair33";
attribute HLUTNM of \add_temp_14__92_carry__0_i_8\ : label is "lutpair32";
attribute HLUTNM of \add_temp_14__92_carry__1_i_1\ : label is "lutpair38";
attribute HLUTNM of \add_temp_14__92_carry__1_i_2\ : label is "lutpair37";
attribute HLUTNM of \add_temp_14__92_carry__1_i_3\ : label is "lutpair36";
attribute HLUTNM of \add_temp_14__92_carry__1_i_4\ : label is "lutpair35";
attribute HLUTNM of \add_temp_14__92_carry__1_i_5\ : label is "lutpair39";
attribute HLUTNM of \add_temp_14__92_carry__1_i_6\ : label is "lutpair38";
attribute HLUTNM of \add_temp_14__92_carry__1_i_7\ : label is "lutpair37";
attribute HLUTNM of \add_temp_14__92_carry__1_i_8\ : label is "lutpair36";
attribute HLUTNM of \add_temp_14__92_carry__2_i_1\ : label is "lutpair41";
attribute HLUTNM of \add_temp_14__92_carry__2_i_2\ : label is "lutpair40";
attribute HLUTNM of \add_temp_14__92_carry__2_i_3\ : label is "lutpair39";
attribute HLUTNM of \add_temp_14__92_carry__2_i_6\ : label is "lutpair41";
attribute HLUTNM of \add_temp_14__92_carry__2_i_7\ : label is "lutpair40";
attribute HLUTNM of \add_temp_14__92_carry_i_1\ : label is "lutpair30";
attribute HLUTNM of \add_temp_14__92_carry_i_2\ : label is "lutpair29";
attribute HLUTNM of \add_temp_14__92_carry_i_3\ : label is "lutpair28";
attribute HLUTNM of \add_temp_14__92_carry_i_4\ : label is "lutpair31";
attribute HLUTNM of \add_temp_14__92_carry_i_5\ : label is "lutpair30";
attribute HLUTNM of \add_temp_14__92_carry_i_6\ : label is "lutpair29";
attribute HLUTNM of \add_temp_14__92_carry_i_7\ : label is "lutpair28";
attribute METHODOLOGY_DRC_VIOS of mul_temp : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_1 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_10 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_11 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_12 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_13 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_14 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_15 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_17 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_18 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_19 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_2 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_20 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_21 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_22 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_23 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_24 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_25 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_26 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_27 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_28 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_29 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_3 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_30 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_31 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_32 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_4 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_5 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_6 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_7 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_8 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_9 : label is "{SYNTH-13 {cell *THIS*}}";
begin
mul_temp_16(15 downto 0) <= \^mul_temp_16\(15 downto 0);
ARG: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_ARG_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_ARG_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_18\(14),
C(12) => ARG_i_1_n_0,
C(11) => ARG_i_1_n_0,
C(10) => ARG_i_1_n_0,
C(9) => ARG_i_1_n_0,
C(8) => ARG_i_1_n_0,
C(7) => ARG_i_1_n_0,
C(6) => ARG_i_1_n_0,
C(5) => ARG_i_1_n_0,
C(4) => ARG_i_1_n_0,
C(3) => ARG_i_1_n_0,
C(2) => ARG_i_1_n_0,
C(1) => ARG_i_1_n_0,
C(0) => ARG_i_1_n_0,
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_ARG_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_ARG_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_ARG_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => NLW_ARG_OVERFLOW_UNCONNECTED,
P(47 downto 30) => NLW_ARG_P_UNCONNECTED(47 downto 30),
P(29 downto 14) => \in\(15 downto 0),
P(13) => ARG_n_92,
P(12) => ARG_n_93,
P(11) => ARG_n_94,
P(10) => ARG_n_95,
P(9) => ARG_n_96,
P(8) => ARG_n_97,
P(7) => ARG_n_98,
P(6) => ARG_n_99,
P(5) => ARG_n_100,
P(4) => ARG_n_101,
P(3) => ARG_n_102,
P(2) => ARG_n_103,
P(1) => ARG_n_104,
P(0) => ARG_n_105,
PATTERNBDETECT => NLW_ARG_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_ARG_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_ARG_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_ARG_UNDERFLOW_UNCONNECTED
);
\ARG__0\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__0_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[1]_0\(15),
B(16) => \weight_reg[1]_0\(15),
B(15 downto 0) => \weight_reg[1]_0\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__0_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_1\(14),
C(12) => \ARG__0_i_1_n_0\,
C(11) => \ARG__0_i_1_n_0\,
C(10) => \ARG__0_i_1_n_0\,
C(9) => \ARG__0_i_1_n_0\,
C(8) => \ARG__0_i_1_n_0\,
C(7) => \ARG__0_i_1_n_0\,
C(6) => \ARG__0_i_1_n_0\,
C(5) => \ARG__0_i_1_n_0\,
C(4) => \ARG__0_i_1_n_0\,
C(3) => \ARG__0_i_1_n_0\,
C(2) => \ARG__0_i_1_n_0\,
C(1) => \ARG__0_i_1_n_0\,
C(0) => \ARG__0_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__0_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__0_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__0_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__0_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__0_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE16(15 downto 0),
P(13) => \ARG__0_n_92\,
P(12) => \ARG__0_n_93\,
P(11) => \ARG__0_n_94\,
P(10) => \ARG__0_n_95\,
P(9) => \ARG__0_n_96\,
P(8) => \ARG__0_n_97\,
P(7) => \ARG__0_n_98\,
P(6) => \ARG__0_n_99\,
P(5) => \ARG__0_n_100\,
P(4) => \ARG__0_n_101\,
P(3) => \ARG__0_n_102\,
P(2) => \ARG__0_n_103\,
P(1) => \ARG__0_n_104\,
P(0) => \ARG__0_n_105\,
PATTERNBDETECT => \NLW_ARG__0_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__0_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__0_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__0_UNDERFLOW_UNCONNECTED\
);
\ARG__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_1\(14),
O => \ARG__0_i_1_n_0\
);
\ARG__1\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__1_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__1_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_19\(14),
C(12) => \ARG__1_i_1_n_0\,
C(11) => \ARG__1_i_1_n_0\,
C(10) => \ARG__1_i_1_n_0\,
C(9) => \ARG__1_i_1_n_0\,
C(8) => \ARG__1_i_1_n_0\,
C(7) => \ARG__1_i_1_n_0\,
C(6) => \ARG__1_i_1_n_0\,
C(5) => \ARG__1_i_1_n_0\,
C(4) => \ARG__1_i_1_n_0\,
C(3) => \ARG__1_i_1_n_0\,
C(2) => \ARG__1_i_1_n_0\,
C(1) => \ARG__1_i_1_n_0\,
C(0) => \ARG__1_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__1_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__1_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__1_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__1_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__1_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__1_n_76\,
P(28) => \ARG__1_n_77\,
P(27) => \ARG__1_n_78\,
P(26) => \ARG__1_n_79\,
P(25) => \ARG__1_n_80\,
P(24) => \ARG__1_n_81\,
P(23) => \ARG__1_n_82\,
P(22) => \ARG__1_n_83\,
P(21) => \ARG__1_n_84\,
P(20) => \ARG__1_n_85\,
P(19) => \ARG__1_n_86\,
P(18) => \ARG__1_n_87\,
P(17) => \ARG__1_n_88\,
P(16) => \ARG__1_n_89\,
P(15) => \ARG__1_n_90\,
P(14) => \ARG__1_n_91\,
P(13) => \ARG__1_n_92\,
P(12) => \ARG__1_n_93\,
P(11) => \ARG__1_n_94\,
P(10) => \ARG__1_n_95\,
P(9) => \ARG__1_n_96\,
P(8) => \ARG__1_n_97\,
P(7) => \ARG__1_n_98\,
P(6) => \ARG__1_n_99\,
P(5) => \ARG__1_n_100\,
P(4) => \ARG__1_n_101\,
P(3) => \ARG__1_n_102\,
P(2) => \ARG__1_n_103\,
P(1) => \ARG__1_n_104\,
P(0) => \ARG__1_n_105\,
PATTERNBDETECT => \NLW_ARG__1_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__1_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__1_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__1_UNDERFLOW_UNCONNECTED\
);
\ARG__10\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__10_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[6]_5\(15),
B(16) => \weight_reg[6]_5\(15),
B(15 downto 0) => \weight_reg[6]_5\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__10_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_6\(14),
C(12) => \ARG__10_i_1_n_0\,
C(11) => \ARG__10_i_1_n_0\,
C(10) => \ARG__10_i_1_n_0\,
C(9) => \ARG__10_i_1_n_0\,
C(8) => \ARG__10_i_1_n_0\,
C(7) => \ARG__10_i_1_n_0\,
C(6) => \ARG__10_i_1_n_0\,
C(5) => \ARG__10_i_1_n_0\,
C(4) => \ARG__10_i_1_n_0\,
C(3) => \ARG__10_i_1_n_0\,
C(2) => \ARG__10_i_1_n_0\,
C(1) => \ARG__10_i_1_n_0\,
C(0) => \ARG__10_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__10_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__10_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__10_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__10_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__10_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE26(15 downto 0),
P(13) => \ARG__10_n_92\,
P(12) => \ARG__10_n_93\,
P(11) => \ARG__10_n_94\,
P(10) => \ARG__10_n_95\,
P(9) => \ARG__10_n_96\,
P(8) => \ARG__10_n_97\,
P(7) => \ARG__10_n_98\,
P(6) => \ARG__10_n_99\,
P(5) => \ARG__10_n_100\,
P(4) => \ARG__10_n_101\,
P(3) => \ARG__10_n_102\,
P(2) => \ARG__10_n_103\,
P(1) => \ARG__10_n_104\,
P(0) => \ARG__10_n_105\,
PATTERNBDETECT => \NLW_ARG__10_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__10_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__10_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__10_UNDERFLOW_UNCONNECTED\
);
\ARG__10_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_6\(14),
O => \ARG__10_i_1_n_0\
);
\ARG__11\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__11_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__11_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_24\(14),
C(12) => \ARG__11_i_1_n_0\,
C(11) => \ARG__11_i_1_n_0\,
C(10) => \ARG__11_i_1_n_0\,
C(9) => \ARG__11_i_1_n_0\,
C(8) => \ARG__11_i_1_n_0\,
C(7) => \ARG__11_i_1_n_0\,
C(6) => \ARG__11_i_1_n_0\,
C(5) => \ARG__11_i_1_n_0\,
C(4) => \ARG__11_i_1_n_0\,
C(3) => \ARG__11_i_1_n_0\,
C(2) => \ARG__11_i_1_n_0\,
C(1) => \ARG__11_i_1_n_0\,
C(0) => \ARG__11_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__11_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__11_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__11_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__11_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__11_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__11_n_76\,
P(28) => \ARG__11_n_77\,
P(27) => \ARG__11_n_78\,
P(26) => \ARG__11_n_79\,
P(25) => \ARG__11_n_80\,
P(24) => \ARG__11_n_81\,
P(23) => \ARG__11_n_82\,
P(22) => \ARG__11_n_83\,
P(21) => \ARG__11_n_84\,
P(20) => \ARG__11_n_85\,
P(19) => \ARG__11_n_86\,
P(18) => \ARG__11_n_87\,
P(17) => \ARG__11_n_88\,
P(16) => \ARG__11_n_89\,
P(15) => \ARG__11_n_90\,
P(14) => \ARG__11_n_91\,
P(13) => \ARG__11_n_92\,
P(12) => \ARG__11_n_93\,
P(11) => \ARG__11_n_94\,
P(10) => \ARG__11_n_95\,
P(9) => \ARG__11_n_96\,
P(8) => \ARG__11_n_97\,
P(7) => \ARG__11_n_98\,
P(6) => \ARG__11_n_99\,
P(5) => \ARG__11_n_100\,
P(4) => \ARG__11_n_101\,
P(3) => \ARG__11_n_102\,
P(2) => \ARG__11_n_103\,
P(1) => \ARG__11_n_104\,
P(0) => \ARG__11_n_105\,
PATTERNBDETECT => \NLW_ARG__11_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__11_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__11_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__11_UNDERFLOW_UNCONNECTED\
);
\ARG__11_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_24\(14),
O => \ARG__11_i_1_n_0\
);
\ARG__12\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__12_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[7]_6\(15),
B(16) => \weight_reg[7]_6\(15),
B(15 downto 0) => \weight_reg[7]_6\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__12_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_7\(14),
C(12) => \ARG__12_i_1_n_0\,
C(11) => \ARG__12_i_1_n_0\,
C(10) => \ARG__12_i_1_n_0\,
C(9) => \ARG__12_i_1_n_0\,
C(8) => \ARG__12_i_1_n_0\,
C(7) => \ARG__12_i_1_n_0\,
C(6) => \ARG__12_i_1_n_0\,
C(5) => \ARG__12_i_1_n_0\,
C(4) => \ARG__12_i_1_n_0\,
C(3) => \ARG__12_i_1_n_0\,
C(2) => \ARG__12_i_1_n_0\,
C(1) => \ARG__12_i_1_n_0\,
C(0) => \ARG__12_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__12_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__12_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__12_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__12_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__12_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE28(15 downto 0),
P(13) => \ARG__12_n_92\,
P(12) => \ARG__12_n_93\,
P(11) => \ARG__12_n_94\,
P(10) => \ARG__12_n_95\,
P(9) => \ARG__12_n_96\,
P(8) => \ARG__12_n_97\,
P(7) => \ARG__12_n_98\,
P(6) => \ARG__12_n_99\,
P(5) => \ARG__12_n_100\,
P(4) => \ARG__12_n_101\,
P(3) => \ARG__12_n_102\,
P(2) => \ARG__12_n_103\,
P(1) => \ARG__12_n_104\,
P(0) => \ARG__12_n_105\,
PATTERNBDETECT => \NLW_ARG__12_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__12_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__12_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__12_UNDERFLOW_UNCONNECTED\
);
\ARG__12_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_7\(14),
O => \ARG__12_i_1_n_0\
);
\ARG__13\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__13_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__13_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_25\(14),
C(12) => \ARG__13_i_1_n_0\,
C(11) => \ARG__13_i_1_n_0\,
C(10) => \ARG__13_i_1_n_0\,
C(9) => \ARG__13_i_1_n_0\,
C(8) => \ARG__13_i_1_n_0\,
C(7) => \ARG__13_i_1_n_0\,
C(6) => \ARG__13_i_1_n_0\,
C(5) => \ARG__13_i_1_n_0\,
C(4) => \ARG__13_i_1_n_0\,
C(3) => \ARG__13_i_1_n_0\,
C(2) => \ARG__13_i_1_n_0\,
C(1) => \ARG__13_i_1_n_0\,
C(0) => \ARG__13_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__13_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__13_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__13_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__13_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__13_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__13_n_76\,
P(28) => \ARG__13_n_77\,
P(27) => \ARG__13_n_78\,
P(26) => \ARG__13_n_79\,
P(25) => \ARG__13_n_80\,
P(24) => \ARG__13_n_81\,
P(23) => \ARG__13_n_82\,
P(22) => \ARG__13_n_83\,
P(21) => \ARG__13_n_84\,
P(20) => \ARG__13_n_85\,
P(19) => \ARG__13_n_86\,
P(18) => \ARG__13_n_87\,
P(17) => \ARG__13_n_88\,
P(16) => \ARG__13_n_89\,
P(15) => \ARG__13_n_90\,
P(14) => \ARG__13_n_91\,
P(13) => \ARG__13_n_92\,
P(12) => \ARG__13_n_93\,
P(11) => \ARG__13_n_94\,
P(10) => \ARG__13_n_95\,
P(9) => \ARG__13_n_96\,
P(8) => \ARG__13_n_97\,
P(7) => \ARG__13_n_98\,
P(6) => \ARG__13_n_99\,
P(5) => \ARG__13_n_100\,
P(4) => \ARG__13_n_101\,
P(3) => \ARG__13_n_102\,
P(2) => \ARG__13_n_103\,
P(1) => \ARG__13_n_104\,
P(0) => \ARG__13_n_105\,
PATTERNBDETECT => \NLW_ARG__13_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__13_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__13_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__13_UNDERFLOW_UNCONNECTED\
);
\ARG__13_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_25\(14),
O => \ARG__13_i_1_n_0\
);
\ARG__14\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__14_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[8]_7\(15),
B(16) => \weight_reg[8]_7\(15),
B(15 downto 0) => \weight_reg[8]_7\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__14_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_8\(14),
C(12) => \ARG__14_i_1_n_0\,
C(11) => \ARG__14_i_1_n_0\,
C(10) => \ARG__14_i_1_n_0\,
C(9) => \ARG__14_i_1_n_0\,
C(8) => \ARG__14_i_1_n_0\,
C(7) => \ARG__14_i_1_n_0\,
C(6) => \ARG__14_i_1_n_0\,
C(5) => \ARG__14_i_1_n_0\,
C(4) => \ARG__14_i_1_n_0\,
C(3) => \ARG__14_i_1_n_0\,
C(2) => \ARG__14_i_1_n_0\,
C(1) => \ARG__14_i_1_n_0\,
C(0) => \ARG__14_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__14_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__14_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__14_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__14_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__14_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE30(15 downto 0),
P(13) => \ARG__14_n_92\,
P(12) => \ARG__14_n_93\,
P(11) => \ARG__14_n_94\,
P(10) => \ARG__14_n_95\,
P(9) => \ARG__14_n_96\,
P(8) => \ARG__14_n_97\,
P(7) => \ARG__14_n_98\,
P(6) => \ARG__14_n_99\,
P(5) => \ARG__14_n_100\,
P(4) => \ARG__14_n_101\,
P(3) => \ARG__14_n_102\,
P(2) => \ARG__14_n_103\,
P(1) => \ARG__14_n_104\,
P(0) => \ARG__14_n_105\,
PATTERNBDETECT => \NLW_ARG__14_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__14_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__14_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__14_UNDERFLOW_UNCONNECTED\
);
\ARG__14_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_8\(14),
O => \ARG__14_i_1_n_0\
);
\ARG__15\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__15_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__15_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_26\(14),
C(12) => \ARG__15_i_1_n_0\,
C(11) => \ARG__15_i_1_n_0\,
C(10) => \ARG__15_i_1_n_0\,
C(9) => \ARG__15_i_1_n_0\,
C(8) => \ARG__15_i_1_n_0\,
C(7) => \ARG__15_i_1_n_0\,
C(6) => \ARG__15_i_1_n_0\,
C(5) => \ARG__15_i_1_n_0\,
C(4) => \ARG__15_i_1_n_0\,
C(3) => \ARG__15_i_1_n_0\,
C(2) => \ARG__15_i_1_n_0\,
C(1) => \ARG__15_i_1_n_0\,
C(0) => \ARG__15_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__15_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__15_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__15_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__15_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__15_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__15_n_76\,
P(28) => \ARG__15_n_77\,
P(27) => \ARG__15_n_78\,
P(26) => \ARG__15_n_79\,
P(25) => \ARG__15_n_80\,
P(24) => \ARG__15_n_81\,
P(23) => \ARG__15_n_82\,
P(22) => \ARG__15_n_83\,
P(21) => \ARG__15_n_84\,
P(20) => \ARG__15_n_85\,
P(19) => \ARG__15_n_86\,
P(18) => \ARG__15_n_87\,
P(17) => \ARG__15_n_88\,
P(16) => \ARG__15_n_89\,
P(15) => \ARG__15_n_90\,
P(14) => \ARG__15_n_91\,
P(13) => \ARG__15_n_92\,
P(12) => \ARG__15_n_93\,
P(11) => \ARG__15_n_94\,
P(10) => \ARG__15_n_95\,
P(9) => \ARG__15_n_96\,
P(8) => \ARG__15_n_97\,
P(7) => \ARG__15_n_98\,
P(6) => \ARG__15_n_99\,
P(5) => \ARG__15_n_100\,
P(4) => \ARG__15_n_101\,
P(3) => \ARG__15_n_102\,
P(2) => \ARG__15_n_103\,
P(1) => \ARG__15_n_104\,
P(0) => \ARG__15_n_105\,
PATTERNBDETECT => \NLW_ARG__15_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__15_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__15_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__15_UNDERFLOW_UNCONNECTED\
);
\ARG__15_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_26\(14),
O => \ARG__15_i_1_n_0\
);
\ARG__16\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__16_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[9]_8\(15),
B(16) => \weight_reg[9]_8\(15),
B(15 downto 0) => \weight_reg[9]_8\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__16_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_9\(14),
C(12) => \ARG__16_i_1_n_0\,
C(11) => \ARG__16_i_1_n_0\,
C(10) => \ARG__16_i_1_n_0\,
C(9) => \ARG__16_i_1_n_0\,
C(8) => \ARG__16_i_1_n_0\,
C(7) => \ARG__16_i_1_n_0\,
C(6) => \ARG__16_i_1_n_0\,
C(5) => \ARG__16_i_1_n_0\,
C(4) => \ARG__16_i_1_n_0\,
C(3) => \ARG__16_i_1_n_0\,
C(2) => \ARG__16_i_1_n_0\,
C(1) => \ARG__16_i_1_n_0\,
C(0) => \ARG__16_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__16_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__16_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__16_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__16_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__16_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE32(15 downto 0),
P(13) => \ARG__16_n_92\,
P(12) => \ARG__16_n_93\,
P(11) => \ARG__16_n_94\,
P(10) => \ARG__16_n_95\,
P(9) => \ARG__16_n_96\,
P(8) => \ARG__16_n_97\,
P(7) => \ARG__16_n_98\,
P(6) => \ARG__16_n_99\,
P(5) => \ARG__16_n_100\,
P(4) => \ARG__16_n_101\,
P(3) => \ARG__16_n_102\,
P(2) => \ARG__16_n_103\,
P(1) => \ARG__16_n_104\,
P(0) => \ARG__16_n_105\,
PATTERNBDETECT => \NLW_ARG__16_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__16_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__16_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__16_UNDERFLOW_UNCONNECTED\
);
\ARG__16_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_9\(14),
O => \ARG__16_i_1_n_0\
);
\ARG__17\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__17_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__17_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_27\(14),
C(12) => \ARG__17_i_1_n_0\,
C(11) => \ARG__17_i_1_n_0\,
C(10) => \ARG__17_i_1_n_0\,
C(9) => \ARG__17_i_1_n_0\,
C(8) => \ARG__17_i_1_n_0\,
C(7) => \ARG__17_i_1_n_0\,
C(6) => \ARG__17_i_1_n_0\,
C(5) => \ARG__17_i_1_n_0\,
C(4) => \ARG__17_i_1_n_0\,
C(3) => \ARG__17_i_1_n_0\,
C(2) => \ARG__17_i_1_n_0\,
C(1) => \ARG__17_i_1_n_0\,
C(0) => \ARG__17_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__17_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__17_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__17_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__17_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__17_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__17_n_76\,
P(28) => \ARG__17_n_77\,
P(27) => \ARG__17_n_78\,
P(26) => \ARG__17_n_79\,
P(25) => \ARG__17_n_80\,
P(24) => \ARG__17_n_81\,
P(23) => \ARG__17_n_82\,
P(22) => \ARG__17_n_83\,
P(21) => \ARG__17_n_84\,
P(20) => \ARG__17_n_85\,
P(19) => \ARG__17_n_86\,
P(18) => \ARG__17_n_87\,
P(17) => \ARG__17_n_88\,
P(16) => \ARG__17_n_89\,
P(15) => \ARG__17_n_90\,
P(14) => \ARG__17_n_91\,
P(13) => \ARG__17_n_92\,
P(12) => \ARG__17_n_93\,
P(11) => \ARG__17_n_94\,
P(10) => \ARG__17_n_95\,
P(9) => \ARG__17_n_96\,
P(8) => \ARG__17_n_97\,
P(7) => \ARG__17_n_98\,
P(6) => \ARG__17_n_99\,
P(5) => \ARG__17_n_100\,
P(4) => \ARG__17_n_101\,
P(3) => \ARG__17_n_102\,
P(2) => \ARG__17_n_103\,
P(1) => \ARG__17_n_104\,
P(0) => \ARG__17_n_105\,
PATTERNBDETECT => \NLW_ARG__17_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__17_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__17_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__17_UNDERFLOW_UNCONNECTED\
);
\ARG__17_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_27\(14),
O => \ARG__17_i_1_n_0\
);
\ARG__18\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__18_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[10]_9\(15),
B(16) => \weight_reg[10]_9\(15),
B(15 downto 0) => \weight_reg[10]_9\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__18_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_10\(14),
C(12) => \ARG__18_i_1_n_0\,
C(11) => \ARG__18_i_1_n_0\,
C(10) => \ARG__18_i_1_n_0\,
C(9) => \ARG__18_i_1_n_0\,
C(8) => \ARG__18_i_1_n_0\,
C(7) => \ARG__18_i_1_n_0\,
C(6) => \ARG__18_i_1_n_0\,
C(5) => \ARG__18_i_1_n_0\,
C(4) => \ARG__18_i_1_n_0\,
C(3) => \ARG__18_i_1_n_0\,
C(2) => \ARG__18_i_1_n_0\,
C(1) => \ARG__18_i_1_n_0\,
C(0) => \ARG__18_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__18_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__18_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__18_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__18_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__18_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE34(15 downto 0),
P(13) => \ARG__18_n_92\,
P(12) => \ARG__18_n_93\,
P(11) => \ARG__18_n_94\,
P(10) => \ARG__18_n_95\,
P(9) => \ARG__18_n_96\,
P(8) => \ARG__18_n_97\,
P(7) => \ARG__18_n_98\,
P(6) => \ARG__18_n_99\,
P(5) => \ARG__18_n_100\,
P(4) => \ARG__18_n_101\,
P(3) => \ARG__18_n_102\,
P(2) => \ARG__18_n_103\,
P(1) => \ARG__18_n_104\,
P(0) => \ARG__18_n_105\,
PATTERNBDETECT => \NLW_ARG__18_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__18_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__18_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__18_UNDERFLOW_UNCONNECTED\
);
\ARG__18_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_10\(14),
O => \ARG__18_i_1_n_0\
);
\ARG__19\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__19_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__19_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_28\(14),
C(12) => \ARG__19_i_1_n_0\,
C(11) => \ARG__19_i_1_n_0\,
C(10) => \ARG__19_i_1_n_0\,
C(9) => \ARG__19_i_1_n_0\,
C(8) => \ARG__19_i_1_n_0\,
C(7) => \ARG__19_i_1_n_0\,
C(6) => \ARG__19_i_1_n_0\,
C(5) => \ARG__19_i_1_n_0\,
C(4) => \ARG__19_i_1_n_0\,
C(3) => \ARG__19_i_1_n_0\,
C(2) => \ARG__19_i_1_n_0\,
C(1) => \ARG__19_i_1_n_0\,
C(0) => \ARG__19_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__19_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__19_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__19_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__19_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__19_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__19_n_76\,
P(28) => \ARG__19_n_77\,
P(27) => \ARG__19_n_78\,
P(26) => \ARG__19_n_79\,
P(25) => \ARG__19_n_80\,
P(24) => \ARG__19_n_81\,
P(23) => \ARG__19_n_82\,
P(22) => \ARG__19_n_83\,
P(21) => \ARG__19_n_84\,
P(20) => \ARG__19_n_85\,
P(19) => \ARG__19_n_86\,
P(18) => \ARG__19_n_87\,
P(17) => \ARG__19_n_88\,
P(16) => \ARG__19_n_89\,
P(15) => \ARG__19_n_90\,
P(14) => \ARG__19_n_91\,
P(13) => \ARG__19_n_92\,
P(12) => \ARG__19_n_93\,
P(11) => \ARG__19_n_94\,
P(10) => \ARG__19_n_95\,
P(9) => \ARG__19_n_96\,
P(8) => \ARG__19_n_97\,
P(7) => \ARG__19_n_98\,
P(6) => \ARG__19_n_99\,
P(5) => \ARG__19_n_100\,
P(4) => \ARG__19_n_101\,
P(3) => \ARG__19_n_102\,
P(2) => \ARG__19_n_103\,
P(1) => \ARG__19_n_104\,
P(0) => \ARG__19_n_105\,
PATTERNBDETECT => \NLW_ARG__19_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__19_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__19_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__19_UNDERFLOW_UNCONNECTED\
);
\ARG__19_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_28\(14),
O => \ARG__19_i_1_n_0\
);
\ARG__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_19\(14),
O => \ARG__1_i_1_n_0\
);
\ARG__2\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__2_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[2]_1\(15),
B(16) => \weight_reg[2]_1\(15),
B(15 downto 0) => \weight_reg[2]_1\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__2_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_2\(14),
C(12) => \ARG__2_i_1_n_0\,
C(11) => \ARG__2_i_1_n_0\,
C(10) => \ARG__2_i_1_n_0\,
C(9) => \ARG__2_i_1_n_0\,
C(8) => \ARG__2_i_1_n_0\,
C(7) => \ARG__2_i_1_n_0\,
C(6) => \ARG__2_i_1_n_0\,
C(5) => \ARG__2_i_1_n_0\,
C(4) => \ARG__2_i_1_n_0\,
C(3) => \ARG__2_i_1_n_0\,
C(2) => \ARG__2_i_1_n_0\,
C(1) => \ARG__2_i_1_n_0\,
C(0) => \ARG__2_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__2_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__2_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__2_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__2_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__2_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE18(15 downto 0),
P(13) => \ARG__2_n_92\,
P(12) => \ARG__2_n_93\,
P(11) => \ARG__2_n_94\,
P(10) => \ARG__2_n_95\,
P(9) => \ARG__2_n_96\,
P(8) => \ARG__2_n_97\,
P(7) => \ARG__2_n_98\,
P(6) => \ARG__2_n_99\,
P(5) => \ARG__2_n_100\,
P(4) => \ARG__2_n_101\,
P(3) => \ARG__2_n_102\,
P(2) => \ARG__2_n_103\,
P(1) => \ARG__2_n_104\,
P(0) => \ARG__2_n_105\,
PATTERNBDETECT => \NLW_ARG__2_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__2_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__2_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__2_UNDERFLOW_UNCONNECTED\
);
\ARG__20\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__20_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[11]_10\(15),
B(16) => \weight_reg[11]_10\(15),
B(15 downto 0) => \weight_reg[11]_10\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__20_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_11\(14),
C(12) => \ARG__20_i_1_n_0\,
C(11) => \ARG__20_i_1_n_0\,
C(10) => \ARG__20_i_1_n_0\,
C(9) => \ARG__20_i_1_n_0\,
C(8) => \ARG__20_i_1_n_0\,
C(7) => \ARG__20_i_1_n_0\,
C(6) => \ARG__20_i_1_n_0\,
C(5) => \ARG__20_i_1_n_0\,
C(4) => \ARG__20_i_1_n_0\,
C(3) => \ARG__20_i_1_n_0\,
C(2) => \ARG__20_i_1_n_0\,
C(1) => \ARG__20_i_1_n_0\,
C(0) => \ARG__20_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__20_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__20_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__20_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__20_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__20_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE36(15 downto 0),
P(13) => \ARG__20_n_92\,
P(12) => \ARG__20_n_93\,
P(11) => \ARG__20_n_94\,
P(10) => \ARG__20_n_95\,
P(9) => \ARG__20_n_96\,
P(8) => \ARG__20_n_97\,
P(7) => \ARG__20_n_98\,
P(6) => \ARG__20_n_99\,
P(5) => \ARG__20_n_100\,
P(4) => \ARG__20_n_101\,
P(3) => \ARG__20_n_102\,
P(2) => \ARG__20_n_103\,
P(1) => \ARG__20_n_104\,
P(0) => \ARG__20_n_105\,
PATTERNBDETECT => \NLW_ARG__20_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__20_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__20_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__20_UNDERFLOW_UNCONNECTED\
);
\ARG__20_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_11\(14),
O => \ARG__20_i_1_n_0\
);
\ARG__21\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__21_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__21_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_29\(14),
C(12) => \ARG__21_i_1_n_0\,
C(11) => \ARG__21_i_1_n_0\,
C(10) => \ARG__21_i_1_n_0\,
C(9) => \ARG__21_i_1_n_0\,
C(8) => \ARG__21_i_1_n_0\,
C(7) => \ARG__21_i_1_n_0\,
C(6) => \ARG__21_i_1_n_0\,
C(5) => \ARG__21_i_1_n_0\,
C(4) => \ARG__21_i_1_n_0\,
C(3) => \ARG__21_i_1_n_0\,
C(2) => \ARG__21_i_1_n_0\,
C(1) => \ARG__21_i_1_n_0\,
C(0) => \ARG__21_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__21_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__21_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__21_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__21_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__21_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__21_n_76\,
P(28) => \ARG__21_n_77\,
P(27) => \ARG__21_n_78\,
P(26) => \ARG__21_n_79\,
P(25) => \ARG__21_n_80\,
P(24) => \ARG__21_n_81\,
P(23) => \ARG__21_n_82\,
P(22) => \ARG__21_n_83\,
P(21) => \ARG__21_n_84\,
P(20) => \ARG__21_n_85\,
P(19) => \ARG__21_n_86\,
P(18) => \ARG__21_n_87\,
P(17) => \ARG__21_n_88\,
P(16) => \ARG__21_n_89\,
P(15) => \ARG__21_n_90\,
P(14) => \ARG__21_n_91\,
P(13) => \ARG__21_n_92\,
P(12) => \ARG__21_n_93\,
P(11) => \ARG__21_n_94\,
P(10) => \ARG__21_n_95\,
P(9) => \ARG__21_n_96\,
P(8) => \ARG__21_n_97\,
P(7) => \ARG__21_n_98\,
P(6) => \ARG__21_n_99\,
P(5) => \ARG__21_n_100\,
P(4) => \ARG__21_n_101\,
P(3) => \ARG__21_n_102\,
P(2) => \ARG__21_n_103\,
P(1) => \ARG__21_n_104\,
P(0) => \ARG__21_n_105\,
PATTERNBDETECT => \NLW_ARG__21_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__21_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__21_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__21_UNDERFLOW_UNCONNECTED\
);
\ARG__21_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_29\(14),
O => \ARG__21_i_1_n_0\
);
\ARG__22\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__22_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[12]_11\(15),
B(16) => \weight_reg[12]_11\(15),
B(15 downto 0) => \weight_reg[12]_11\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__22_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_12\(14),
C(12) => \ARG__22_i_1_n_0\,
C(11) => \ARG__22_i_1_n_0\,
C(10) => \ARG__22_i_1_n_0\,
C(9) => \ARG__22_i_1_n_0\,
C(8) => \ARG__22_i_1_n_0\,
C(7) => \ARG__22_i_1_n_0\,
C(6) => \ARG__22_i_1_n_0\,
C(5) => \ARG__22_i_1_n_0\,
C(4) => \ARG__22_i_1_n_0\,
C(3) => \ARG__22_i_1_n_0\,
C(2) => \ARG__22_i_1_n_0\,
C(1) => \ARG__22_i_1_n_0\,
C(0) => \ARG__22_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__22_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__22_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__22_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__22_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__22_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE38(15 downto 0),
P(13) => \ARG__22_n_92\,
P(12) => \ARG__22_n_93\,
P(11) => \ARG__22_n_94\,
P(10) => \ARG__22_n_95\,
P(9) => \ARG__22_n_96\,
P(8) => \ARG__22_n_97\,
P(7) => \ARG__22_n_98\,
P(6) => \ARG__22_n_99\,
P(5) => \ARG__22_n_100\,
P(4) => \ARG__22_n_101\,
P(3) => \ARG__22_n_102\,
P(2) => \ARG__22_n_103\,
P(1) => \ARG__22_n_104\,
P(0) => \ARG__22_n_105\,
PATTERNBDETECT => \NLW_ARG__22_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__22_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__22_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__22_UNDERFLOW_UNCONNECTED\
);
\ARG__22_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_12\(14),
O => \ARG__22_i_1_n_0\
);
\ARG__23\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__23_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__23_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_30\(14),
C(12) => \ARG__23_i_1_n_0\,
C(11) => \ARG__23_i_1_n_0\,
C(10) => \ARG__23_i_1_n_0\,
C(9) => \ARG__23_i_1_n_0\,
C(8) => \ARG__23_i_1_n_0\,
C(7) => \ARG__23_i_1_n_0\,
C(6) => \ARG__23_i_1_n_0\,
C(5) => \ARG__23_i_1_n_0\,
C(4) => \ARG__23_i_1_n_0\,
C(3) => \ARG__23_i_1_n_0\,
C(2) => \ARG__23_i_1_n_0\,
C(1) => \ARG__23_i_1_n_0\,
C(0) => \ARG__23_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__23_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__23_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__23_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__23_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__23_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__23_n_76\,
P(28) => \ARG__23_n_77\,
P(27) => \ARG__23_n_78\,
P(26) => \ARG__23_n_79\,
P(25) => \ARG__23_n_80\,
P(24) => \ARG__23_n_81\,
P(23) => \ARG__23_n_82\,
P(22) => \ARG__23_n_83\,
P(21) => \ARG__23_n_84\,
P(20) => \ARG__23_n_85\,
P(19) => \ARG__23_n_86\,
P(18) => \ARG__23_n_87\,
P(17) => \ARG__23_n_88\,
P(16) => \ARG__23_n_89\,
P(15) => \ARG__23_n_90\,
P(14) => \ARG__23_n_91\,
P(13) => \ARG__23_n_92\,
P(12) => \ARG__23_n_93\,
P(11) => \ARG__23_n_94\,
P(10) => \ARG__23_n_95\,
P(9) => \ARG__23_n_96\,
P(8) => \ARG__23_n_97\,
P(7) => \ARG__23_n_98\,
P(6) => \ARG__23_n_99\,
P(5) => \ARG__23_n_100\,
P(4) => \ARG__23_n_101\,
P(3) => \ARG__23_n_102\,
P(2) => \ARG__23_n_103\,
P(1) => \ARG__23_n_104\,
P(0) => \ARG__23_n_105\,
PATTERNBDETECT => \NLW_ARG__23_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__23_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__23_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__23_UNDERFLOW_UNCONNECTED\
);
\ARG__23_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_30\(14),
O => \ARG__23_i_1_n_0\
);
\ARG__24\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__24_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[13]_12\(15),
B(16) => \weight_reg[13]_12\(15),
B(15 downto 0) => \weight_reg[13]_12\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__24_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_13\(14),
C(12) => \ARG__24_i_1_n_0\,
C(11) => \ARG__24_i_1_n_0\,
C(10) => \ARG__24_i_1_n_0\,
C(9) => \ARG__24_i_1_n_0\,
C(8) => \ARG__24_i_1_n_0\,
C(7) => \ARG__24_i_1_n_0\,
C(6) => \ARG__24_i_1_n_0\,
C(5) => \ARG__24_i_1_n_0\,
C(4) => \ARG__24_i_1_n_0\,
C(3) => \ARG__24_i_1_n_0\,
C(2) => \ARG__24_i_1_n_0\,
C(1) => \ARG__24_i_1_n_0\,
C(0) => \ARG__24_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__24_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__24_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__24_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__24_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__24_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE40(15 downto 0),
P(13) => \ARG__24_n_92\,
P(12) => \ARG__24_n_93\,
P(11) => \ARG__24_n_94\,
P(10) => \ARG__24_n_95\,
P(9) => \ARG__24_n_96\,
P(8) => \ARG__24_n_97\,
P(7) => \ARG__24_n_98\,
P(6) => \ARG__24_n_99\,
P(5) => \ARG__24_n_100\,
P(4) => \ARG__24_n_101\,
P(3) => \ARG__24_n_102\,
P(2) => \ARG__24_n_103\,
P(1) => \ARG__24_n_104\,
P(0) => \ARG__24_n_105\,
PATTERNBDETECT => \NLW_ARG__24_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__24_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__24_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__24_UNDERFLOW_UNCONNECTED\
);
\ARG__24_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_13\(14),
O => \ARG__24_i_1_n_0\
);
\ARG__25\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__25_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__25_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_31\(14),
C(12) => \ARG__25_i_1_n_0\,
C(11) => \ARG__25_i_1_n_0\,
C(10) => \ARG__25_i_1_n_0\,
C(9) => \ARG__25_i_1_n_0\,
C(8) => \ARG__25_i_1_n_0\,
C(7) => \ARG__25_i_1_n_0\,
C(6) => \ARG__25_i_1_n_0\,
C(5) => \ARG__25_i_1_n_0\,
C(4) => \ARG__25_i_1_n_0\,
C(3) => \ARG__25_i_1_n_0\,
C(2) => \ARG__25_i_1_n_0\,
C(1) => \ARG__25_i_1_n_0\,
C(0) => \ARG__25_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__25_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__25_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__25_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__25_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__25_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__25_n_76\,
P(28) => \ARG__25_n_77\,
P(27) => \ARG__25_n_78\,
P(26) => \ARG__25_n_79\,
P(25) => \ARG__25_n_80\,
P(24) => \ARG__25_n_81\,
P(23) => \ARG__25_n_82\,
P(22) => \ARG__25_n_83\,
P(21) => \ARG__25_n_84\,
P(20) => \ARG__25_n_85\,
P(19) => \ARG__25_n_86\,
P(18) => \ARG__25_n_87\,
P(17) => \ARG__25_n_88\,
P(16) => \ARG__25_n_89\,
P(15) => \ARG__25_n_90\,
P(14) => \ARG__25_n_91\,
P(13) => \ARG__25_n_92\,
P(12) => \ARG__25_n_93\,
P(11) => \ARG__25_n_94\,
P(10) => \ARG__25_n_95\,
P(9) => \ARG__25_n_96\,
P(8) => \ARG__25_n_97\,
P(7) => \ARG__25_n_98\,
P(6) => \ARG__25_n_99\,
P(5) => \ARG__25_n_100\,
P(4) => \ARG__25_n_101\,
P(3) => \ARG__25_n_102\,
P(2) => \ARG__25_n_103\,
P(1) => \ARG__25_n_104\,
P(0) => \ARG__25_n_105\,
PATTERNBDETECT => \NLW_ARG__25_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__25_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__25_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__25_UNDERFLOW_UNCONNECTED\
);
\ARG__25_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_31\(14),
O => \ARG__25_i_1_n_0\
);
\ARG__26\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__26_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[14]_13\(15),
B(16) => \weight_reg[14]_13\(15),
B(15 downto 0) => \weight_reg[14]_13\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__26_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_14\(14),
C(12) => \ARG__26_i_1_n_0\,
C(11) => \ARG__26_i_1_n_0\,
C(10) => \ARG__26_i_1_n_0\,
C(9) => \ARG__26_i_1_n_0\,
C(8) => \ARG__26_i_1_n_0\,
C(7) => \ARG__26_i_1_n_0\,
C(6) => \ARG__26_i_1_n_0\,
C(5) => \ARG__26_i_1_n_0\,
C(4) => \ARG__26_i_1_n_0\,
C(3) => \ARG__26_i_1_n_0\,
C(2) => \ARG__26_i_1_n_0\,
C(1) => \ARG__26_i_1_n_0\,
C(0) => \ARG__26_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__26_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__26_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__26_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__26_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__26_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE42(15 downto 0),
P(13) => \ARG__26_n_92\,
P(12) => \ARG__26_n_93\,
P(11) => \ARG__26_n_94\,
P(10) => \ARG__26_n_95\,
P(9) => \ARG__26_n_96\,
P(8) => \ARG__26_n_97\,
P(7) => \ARG__26_n_98\,
P(6) => \ARG__26_n_99\,
P(5) => \ARG__26_n_100\,
P(4) => \ARG__26_n_101\,
P(3) => \ARG__26_n_102\,
P(2) => \ARG__26_n_103\,
P(1) => \ARG__26_n_104\,
P(0) => \ARG__26_n_105\,
PATTERNBDETECT => \NLW_ARG__26_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__26_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__26_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__26_UNDERFLOW_UNCONNECTED\
);
\ARG__26_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_14\(14),
O => \ARG__26_i_1_n_0\
);
\ARG__27\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__27_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__27_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_32\(14),
C(12) => \ARG__27_i_1_n_0\,
C(11) => \ARG__27_i_1_n_0\,
C(10) => \ARG__27_i_1_n_0\,
C(9) => \ARG__27_i_1_n_0\,
C(8) => \ARG__27_i_1_n_0\,
C(7) => \ARG__27_i_1_n_0\,
C(6) => \ARG__27_i_1_n_0\,
C(5) => \ARG__27_i_1_n_0\,
C(4) => \ARG__27_i_1_n_0\,
C(3) => \ARG__27_i_1_n_0\,
C(2) => \ARG__27_i_1_n_0\,
C(1) => \ARG__27_i_1_n_0\,
C(0) => \ARG__27_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__27_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__27_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__27_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__27_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__27_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__27_n_76\,
P(28) => \ARG__27_n_77\,
P(27) => \ARG__27_n_78\,
P(26) => \ARG__27_n_79\,
P(25) => \ARG__27_n_80\,
P(24) => \ARG__27_n_81\,
P(23) => \ARG__27_n_82\,
P(22) => \ARG__27_n_83\,
P(21) => \ARG__27_n_84\,
P(20) => \ARG__27_n_85\,
P(19) => \ARG__27_n_86\,
P(18) => \ARG__27_n_87\,
P(17) => \ARG__27_n_88\,
P(16) => \ARG__27_n_89\,
P(15) => \ARG__27_n_90\,
P(14) => \ARG__27_n_91\,
P(13) => \ARG__27_n_92\,
P(12) => \ARG__27_n_93\,
P(11) => \ARG__27_n_94\,
P(10) => \ARG__27_n_95\,
P(9) => \ARG__27_n_96\,
P(8) => \ARG__27_n_97\,
P(7) => \ARG__27_n_98\,
P(6) => \ARG__27_n_99\,
P(5) => \ARG__27_n_100\,
P(4) => \ARG__27_n_101\,
P(3) => \ARG__27_n_102\,
P(2) => \ARG__27_n_103\,
P(1) => \ARG__27_n_104\,
P(0) => \ARG__27_n_105\,
PATTERNBDETECT => \NLW_ARG__27_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__27_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__27_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__27_UNDERFLOW_UNCONNECTED\
);
\ARG__27_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_32\(14),
O => \ARG__27_i_1_n_0\
);
\ARG__28\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__28_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[15]_14\(15),
B(16) => \weight_reg[15]_14\(15),
B(15 downto 0) => \weight_reg[15]_14\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__28_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_15\(14),
C(12) => \ARG__28_i_1_n_0\,
C(11) => \ARG__28_i_1_n_0\,
C(10) => \ARG__28_i_1_n_0\,
C(9) => \ARG__28_i_1_n_0\,
C(8) => \ARG__28_i_1_n_0\,
C(7) => \ARG__28_i_1_n_0\,
C(6) => \ARG__28_i_1_n_0\,
C(5) => \ARG__28_i_1_n_0\,
C(4) => \ARG__28_i_1_n_0\,
C(3) => \ARG__28_i_1_n_0\,
C(2) => \ARG__28_i_1_n_0\,
C(1) => \ARG__28_i_1_n_0\,
C(0) => \ARG__28_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__28_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__28_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__28_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__28_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__28_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE44(15 downto 0),
P(13) => \ARG__28_n_92\,
P(12) => \ARG__28_n_93\,
P(11) => \ARG__28_n_94\,
P(10) => \ARG__28_n_95\,
P(9) => \ARG__28_n_96\,
P(8) => \ARG__28_n_97\,
P(7) => \ARG__28_n_98\,
P(6) => \ARG__28_n_99\,
P(5) => \ARG__28_n_100\,
P(4) => \ARG__28_n_101\,
P(3) => \ARG__28_n_102\,
P(2) => \ARG__28_n_103\,
P(1) => \ARG__28_n_104\,
P(0) => \ARG__28_n_105\,
PATTERNBDETECT => \NLW_ARG__28_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__28_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__28_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__28_UNDERFLOW_UNCONNECTED\
);
\ARG__28_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_15\(14),
O => \ARG__28_i_1_n_0\
);
\ARG__29\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__29_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__29_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_17\(14),
C(12) => \ARG__29_i_1_n_0\,
C(11) => \ARG__29_i_1_n_0\,
C(10) => \ARG__29_i_1_n_0\,
C(9) => \ARG__29_i_1_n_0\,
C(8) => \ARG__29_i_1_n_0\,
C(7) => \ARG__29_i_1_n_0\,
C(6) => \ARG__29_i_1_n_0\,
C(5) => \ARG__29_i_1_n_0\,
C(4) => \ARG__29_i_1_n_0\,
C(3) => \ARG__29_i_1_n_0\,
C(2) => \ARG__29_i_1_n_0\,
C(1) => \ARG__29_i_1_n_0\,
C(0) => \ARG__29_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__29_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__29_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__29_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__29_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__29_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__29_n_76\,
P(28) => \ARG__29_n_77\,
P(27) => \ARG__29_n_78\,
P(26) => \ARG__29_n_79\,
P(25) => \ARG__29_n_80\,
P(24) => \ARG__29_n_81\,
P(23) => \ARG__29_n_82\,
P(22) => \ARG__29_n_83\,
P(21) => \ARG__29_n_84\,
P(20) => \ARG__29_n_85\,
P(19) => \ARG__29_n_86\,
P(18) => \ARG__29_n_87\,
P(17) => \ARG__29_n_88\,
P(16) => \ARG__29_n_89\,
P(15) => \ARG__29_n_90\,
P(14) => \ARG__29_n_91\,
P(13) => \ARG__29_n_92\,
P(12) => \ARG__29_n_93\,
P(11) => \ARG__29_n_94\,
P(10) => \ARG__29_n_95\,
P(9) => \ARG__29_n_96\,
P(8) => \ARG__29_n_97\,
P(7) => \ARG__29_n_98\,
P(6) => \ARG__29_n_99\,
P(5) => \ARG__29_n_100\,
P(4) => \ARG__29_n_101\,
P(3) => \ARG__29_n_102\,
P(2) => \ARG__29_n_103\,
P(1) => \ARG__29_n_104\,
P(0) => \ARG__29_n_105\,
PATTERNBDETECT => \NLW_ARG__29_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__29_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__29_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__29_UNDERFLOW_UNCONNECTED\
);
\ARG__29_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_17\(14),
O => \ARG__29_i_1_n_0\
);
\ARG__2_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_2\(14),
O => \ARG__2_i_1_n_0\
);
\ARG__3\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__3_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__3_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_20\(14),
C(12) => \ARG__3_i_1_n_0\,
C(11) => \ARG__3_i_1_n_0\,
C(10) => \ARG__3_i_1_n_0\,
C(9) => \ARG__3_i_1_n_0\,
C(8) => \ARG__3_i_1_n_0\,
C(7) => \ARG__3_i_1_n_0\,
C(6) => \ARG__3_i_1_n_0\,
C(5) => \ARG__3_i_1_n_0\,
C(4) => \ARG__3_i_1_n_0\,
C(3) => \ARG__3_i_1_n_0\,
C(2) => \ARG__3_i_1_n_0\,
C(1) => \ARG__3_i_1_n_0\,
C(0) => \ARG__3_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__3_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__3_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__3_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__3_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__3_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__3_n_76\,
P(28) => \ARG__3_n_77\,
P(27) => \ARG__3_n_78\,
P(26) => \ARG__3_n_79\,
P(25) => \ARG__3_n_80\,
P(24) => \ARG__3_n_81\,
P(23) => \ARG__3_n_82\,
P(22) => \ARG__3_n_83\,
P(21) => \ARG__3_n_84\,
P(20) => \ARG__3_n_85\,
P(19) => \ARG__3_n_86\,
P(18) => \ARG__3_n_87\,
P(17) => \ARG__3_n_88\,
P(16) => \ARG__3_n_89\,
P(15) => \ARG__3_n_90\,
P(14) => \ARG__3_n_91\,
P(13) => \ARG__3_n_92\,
P(12) => \ARG__3_n_93\,
P(11) => \ARG__3_n_94\,
P(10) => \ARG__3_n_95\,
P(9) => \ARG__3_n_96\,
P(8) => \ARG__3_n_97\,
P(7) => \ARG__3_n_98\,
P(6) => \ARG__3_n_99\,
P(5) => \ARG__3_n_100\,
P(4) => \ARG__3_n_101\,
P(3) => \ARG__3_n_102\,
P(2) => \ARG__3_n_103\,
P(1) => \ARG__3_n_104\,
P(0) => \ARG__3_n_105\,
PATTERNBDETECT => \NLW_ARG__3_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__3_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__3_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__3_UNDERFLOW_UNCONNECTED\
);
\ARG__30\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__30_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[0]_15\(15),
B(16) => \weight_reg[0]_15\(15),
B(15 downto 0) => \weight_reg[0]_15\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__30_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp\(14),
C(12) => \ARG__30_i_1_n_0\,
C(11) => \ARG__30_i_1_n_0\,
C(10) => \ARG__30_i_1_n_0\,
C(9) => \ARG__30_i_1_n_0\,
C(8) => \ARG__30_i_1_n_0\,
C(7) => \ARG__30_i_1_n_0\,
C(6) => \ARG__30_i_1_n_0\,
C(5) => \ARG__30_i_1_n_0\,
C(4) => \ARG__30_i_1_n_0\,
C(3) => \ARG__30_i_1_n_0\,
C(2) => \ARG__30_i_1_n_0\,
C(1) => \ARG__30_i_1_n_0\,
C(0) => \ARG__30_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__30_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__30_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__30_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__30_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__30_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE15(15 downto 0),
P(13) => \ARG__30_n_92\,
P(12) => \ARG__30_n_93\,
P(11) => \ARG__30_n_94\,
P(10) => \ARG__30_n_95\,
P(9) => \ARG__30_n_96\,
P(8) => \ARG__30_n_97\,
P(7) => \ARG__30_n_98\,
P(6) => \ARG__30_n_99\,
P(5) => \ARG__30_n_100\,
P(4) => \ARG__30_n_101\,
P(3) => \ARG__30_n_102\,
P(2) => \ARG__30_n_103\,
P(1) => \ARG__30_n_104\,
P(0) => \ARG__30_n_105\,
PATTERNBDETECT => \NLW_ARG__30_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__30_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__30_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__30_UNDERFLOW_UNCONNECTED\
);
\ARG__30_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp\(14),
O => \ARG__30_i_1_n_0\
);
\ARG__3_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_20\(14),
O => \ARG__3_i_1_n_0\
);
\ARG__4\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__4_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[3]_2\(15),
B(16) => \weight_reg[3]_2\(15),
B(15 downto 0) => \weight_reg[3]_2\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__4_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_3\(14),
C(12) => \ARG__4_i_1_n_0\,
C(11) => \ARG__4_i_1_n_0\,
C(10) => \ARG__4_i_1_n_0\,
C(9) => \ARG__4_i_1_n_0\,
C(8) => \ARG__4_i_1_n_0\,
C(7) => \ARG__4_i_1_n_0\,
C(6) => \ARG__4_i_1_n_0\,
C(5) => \ARG__4_i_1_n_0\,
C(4) => \ARG__4_i_1_n_0\,
C(3) => \ARG__4_i_1_n_0\,
C(2) => \ARG__4_i_1_n_0\,
C(1) => \ARG__4_i_1_n_0\,
C(0) => \ARG__4_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__4_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__4_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__4_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__4_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__4_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE20(15 downto 0),
P(13) => \ARG__4_n_92\,
P(12) => \ARG__4_n_93\,
P(11) => \ARG__4_n_94\,
P(10) => \ARG__4_n_95\,
P(9) => \ARG__4_n_96\,
P(8) => \ARG__4_n_97\,
P(7) => \ARG__4_n_98\,
P(6) => \ARG__4_n_99\,
P(5) => \ARG__4_n_100\,
P(4) => \ARG__4_n_101\,
P(3) => \ARG__4_n_102\,
P(2) => \ARG__4_n_103\,
P(1) => \ARG__4_n_104\,
P(0) => \ARG__4_n_105\,
PATTERNBDETECT => \NLW_ARG__4_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__4_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__4_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__4_UNDERFLOW_UNCONNECTED\
);
\ARG__4_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_3\(14),
O => \ARG__4_i_1_n_0\
);
\ARG__5\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__5_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__5_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_21\(14),
C(12) => \ARG__5_i_1_n_0\,
C(11) => \ARG__5_i_1_n_0\,
C(10) => \ARG__5_i_1_n_0\,
C(9) => \ARG__5_i_1_n_0\,
C(8) => \ARG__5_i_1_n_0\,
C(7) => \ARG__5_i_1_n_0\,
C(6) => \ARG__5_i_1_n_0\,
C(5) => \ARG__5_i_1_n_0\,
C(4) => \ARG__5_i_1_n_0\,
C(3) => \ARG__5_i_1_n_0\,
C(2) => \ARG__5_i_1_n_0\,
C(1) => \ARG__5_i_1_n_0\,
C(0) => \ARG__5_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__5_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__5_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__5_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__5_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__5_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__5_n_76\,
P(28) => \ARG__5_n_77\,
P(27) => \ARG__5_n_78\,
P(26) => \ARG__5_n_79\,
P(25) => \ARG__5_n_80\,
P(24) => \ARG__5_n_81\,
P(23) => \ARG__5_n_82\,
P(22) => \ARG__5_n_83\,
P(21) => \ARG__5_n_84\,
P(20) => \ARG__5_n_85\,
P(19) => \ARG__5_n_86\,
P(18) => \ARG__5_n_87\,
P(17) => \ARG__5_n_88\,
P(16) => \ARG__5_n_89\,
P(15) => \ARG__5_n_90\,
P(14) => \ARG__5_n_91\,
P(13) => \ARG__5_n_92\,
P(12) => \ARG__5_n_93\,
P(11) => \ARG__5_n_94\,
P(10) => \ARG__5_n_95\,
P(9) => \ARG__5_n_96\,
P(8) => \ARG__5_n_97\,
P(7) => \ARG__5_n_98\,
P(6) => \ARG__5_n_99\,
P(5) => \ARG__5_n_100\,
P(4) => \ARG__5_n_101\,
P(3) => \ARG__5_n_102\,
P(2) => \ARG__5_n_103\,
P(1) => \ARG__5_n_104\,
P(0) => \ARG__5_n_105\,
PATTERNBDETECT => \NLW_ARG__5_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__5_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__5_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__5_UNDERFLOW_UNCONNECTED\
);
\ARG__5_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_21\(14),
O => \ARG__5_i_1_n_0\
);
\ARG__6\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__6_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[4]_3\(15),
B(16) => \weight_reg[4]_3\(15),
B(15 downto 0) => \weight_reg[4]_3\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__6_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_4\(14),
C(12) => \ARG__6_i_1_n_0\,
C(11) => \ARG__6_i_1_n_0\,
C(10) => \ARG__6_i_1_n_0\,
C(9) => \ARG__6_i_1_n_0\,
C(8) => \ARG__6_i_1_n_0\,
C(7) => \ARG__6_i_1_n_0\,
C(6) => \ARG__6_i_1_n_0\,
C(5) => \ARG__6_i_1_n_0\,
C(4) => \ARG__6_i_1_n_0\,
C(3) => \ARG__6_i_1_n_0\,
C(2) => \ARG__6_i_1_n_0\,
C(1) => \ARG__6_i_1_n_0\,
C(0) => \ARG__6_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__6_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__6_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__6_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__6_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__6_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE22(15 downto 0),
P(13) => \ARG__6_n_92\,
P(12) => \ARG__6_n_93\,
P(11) => \ARG__6_n_94\,
P(10) => \ARG__6_n_95\,
P(9) => \ARG__6_n_96\,
P(8) => \ARG__6_n_97\,
P(7) => \ARG__6_n_98\,
P(6) => \ARG__6_n_99\,
P(5) => \ARG__6_n_100\,
P(4) => \ARG__6_n_101\,
P(3) => \ARG__6_n_102\,
P(2) => \ARG__6_n_103\,
P(1) => \ARG__6_n_104\,
P(0) => \ARG__6_n_105\,
PATTERNBDETECT => \NLW_ARG__6_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__6_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__6_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__6_UNDERFLOW_UNCONNECTED\
);
\ARG__6_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_4\(14),
O => \ARG__6_i_1_n_0\
);
\ARG__7\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__7_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__7_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_22\(14),
C(12) => \ARG__7_i_1_n_0\,
C(11) => \ARG__7_i_1_n_0\,
C(10) => \ARG__7_i_1_n_0\,
C(9) => \ARG__7_i_1_n_0\,
C(8) => \ARG__7_i_1_n_0\,
C(7) => \ARG__7_i_1_n_0\,
C(6) => \ARG__7_i_1_n_0\,
C(5) => \ARG__7_i_1_n_0\,
C(4) => \ARG__7_i_1_n_0\,
C(3) => \ARG__7_i_1_n_0\,
C(2) => \ARG__7_i_1_n_0\,
C(1) => \ARG__7_i_1_n_0\,
C(0) => \ARG__7_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__7_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__7_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__7_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__7_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__7_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__7_n_76\,
P(28) => \ARG__7_n_77\,
P(27) => \ARG__7_n_78\,
P(26) => \ARG__7_n_79\,
P(25) => \ARG__7_n_80\,
P(24) => \ARG__7_n_81\,
P(23) => \ARG__7_n_82\,
P(22) => \ARG__7_n_83\,
P(21) => \ARG__7_n_84\,
P(20) => \ARG__7_n_85\,
P(19) => \ARG__7_n_86\,
P(18) => \ARG__7_n_87\,
P(17) => \ARG__7_n_88\,
P(16) => \ARG__7_n_89\,
P(15) => \ARG__7_n_90\,
P(14) => \ARG__7_n_91\,
P(13) => \ARG__7_n_92\,
P(12) => \ARG__7_n_93\,
P(11) => \ARG__7_n_94\,
P(10) => \ARG__7_n_95\,
P(9) => \ARG__7_n_96\,
P(8) => \ARG__7_n_97\,
P(7) => \ARG__7_n_98\,
P(6) => \ARG__7_n_99\,
P(5) => \ARG__7_n_100\,
P(4) => \ARG__7_n_101\,
P(3) => \ARG__7_n_102\,
P(2) => \ARG__7_n_103\,
P(1) => \ARG__7_n_104\,
P(0) => \ARG__7_n_105\,
PATTERNBDETECT => \NLW_ARG__7_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__7_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__7_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__7_UNDERFLOW_UNCONNECTED\
);
\ARG__7_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_22\(14),
O => \ARG__7_i_1_n_0\
);
\ARG__8\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__8_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[5]_4\(15),
B(16) => \weight_reg[5]_4\(15),
B(15 downto 0) => \weight_reg[5]_4\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__8_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_5\(14),
C(12) => \ARG__8_i_1_n_0\,
C(11) => \ARG__8_i_1_n_0\,
C(10) => \ARG__8_i_1_n_0\,
C(9) => \ARG__8_i_1_n_0\,
C(8) => \ARG__8_i_1_n_0\,
C(7) => \ARG__8_i_1_n_0\,
C(6) => \ARG__8_i_1_n_0\,
C(5) => \ARG__8_i_1_n_0\,
C(4) => \ARG__8_i_1_n_0\,
C(3) => \ARG__8_i_1_n_0\,
C(2) => \ARG__8_i_1_n_0\,
C(1) => \ARG__8_i_1_n_0\,
C(0) => \ARG__8_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__8_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__8_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__8_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__8_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__8_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE24(15 downto 0),
P(13) => \ARG__8_n_92\,
P(12) => \ARG__8_n_93\,
P(11) => \ARG__8_n_94\,
P(10) => \ARG__8_n_95\,
P(9) => \ARG__8_n_96\,
P(8) => \ARG__8_n_97\,
P(7) => \ARG__8_n_98\,
P(6) => \ARG__8_n_99\,
P(5) => \ARG__8_n_100\,
P(4) => \ARG__8_n_101\,
P(3) => \ARG__8_n_102\,
P(2) => \ARG__8_n_103\,
P(1) => \ARG__8_n_104\,
P(0) => \ARG__8_n_105\,
PATTERNBDETECT => \NLW_ARG__8_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__8_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__8_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__8_UNDERFLOW_UNCONNECTED\
);
\ARG__8_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_5\(14),
O => \ARG__8_i_1_n_0\
);
\ARG__9\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__9_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__9_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_23\(14),
C(12) => \ARG__9_i_1_n_0\,
C(11) => \ARG__9_i_1_n_0\,
C(10) => \ARG__9_i_1_n_0\,
C(9) => \ARG__9_i_1_n_0\,
C(8) => \ARG__9_i_1_n_0\,
C(7) => \ARG__9_i_1_n_0\,
C(6) => \ARG__9_i_1_n_0\,
C(5) => \ARG__9_i_1_n_0\,
C(4) => \ARG__9_i_1_n_0\,
C(3) => \ARG__9_i_1_n_0\,
C(2) => \ARG__9_i_1_n_0\,
C(1) => \ARG__9_i_1_n_0\,
C(0) => \ARG__9_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__9_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__9_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__9_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__9_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__9_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__9_n_76\,
P(28) => \ARG__9_n_77\,
P(27) => \ARG__9_n_78\,
P(26) => \ARG__9_n_79\,
P(25) => \ARG__9_n_80\,
P(24) => \ARG__9_n_81\,
P(23) => \ARG__9_n_82\,
P(22) => \ARG__9_n_83\,
P(21) => \ARG__9_n_84\,
P(20) => \ARG__9_n_85\,
P(19) => \ARG__9_n_86\,
P(18) => \ARG__9_n_87\,
P(17) => \ARG__9_n_88\,
P(16) => \ARG__9_n_89\,
P(15) => \ARG__9_n_90\,
P(14) => \ARG__9_n_91\,
P(13) => \ARG__9_n_92\,
P(12) => \ARG__9_n_93\,
P(11) => \ARG__9_n_94\,
P(10) => \ARG__9_n_95\,
P(9) => \ARG__9_n_96\,
P(8) => \ARG__9_n_97\,
P(7) => \ARG__9_n_98\,
P(6) => \ARG__9_n_99\,
P(5) => \ARG__9_n_100\,
P(4) => \ARG__9_n_101\,
P(3) => \ARG__9_n_102\,
P(2) => \ARG__9_n_103\,
P(1) => \ARG__9_n_104\,
P(0) => \ARG__9_n_105\,
PATTERNBDETECT => \NLW_ARG__9_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__9_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__9_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__9_UNDERFLOW_UNCONNECTED\
);
\ARG__9_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_23\(14),
O => \ARG__9_i_1_n_0\
);
ARG_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => ARG_carry_n_0,
CO(2) => ARG_carry_n_1,
CO(1) => ARG_carry_n_2,
CO(0) => ARG_carry_n_3,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 1) => \^mul_temp_16\(1 downto 0),
DI(0) => '1',
O(3 downto 0) => NLW_ARG_carry_O_UNCONNECTED(3 downto 0),
S(3) => \^mul_temp_16\(2),
S(2 downto 0) => \write_reg_d_k_reg[3]\(2 downto 0)
);
\ARG_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => ARG_carry_n_0,
CO(3) => \ARG_carry__0_n_0\,
CO(2) => \ARG_carry__0_n_1\,
CO(1) => \ARG_carry__0_n_2\,
CO(0) => \ARG_carry__0_n_3\,
CYINIT => '0',
DI(3) => \^mul_temp_16\(5),
DI(2) => \^mul_temp_16\(3),
DI(1) => \^mul_temp_16\(4),
DI(0) => DI(0),
O(3 downto 0) => \ARG__31\(20 downto 17),
S(3) => \ARG_carry__0_i_2_n_0\,
S(2) => \ARG_carry__0_i_3_n_0\,
S(1) => \ARG_carry__0_i_4_n_0\,
S(0) => \^mul_temp_16\(3)
);
\ARG_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(5),
I1 => \^mul_temp_16\(6),
O => \ARG_carry__0_i_2_n_0\
);
\ARG_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(3),
I1 => \^mul_temp_16\(5),
O => \ARG_carry__0_i_3_n_0\
);
\ARG_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(3),
I1 => \^mul_temp_16\(4),
O => \ARG_carry__0_i_4_n_0\
);
\ARG_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \ARG_carry__0_n_0\,
CO(3) => \ARG_carry__1_n_0\,
CO(2) => \ARG_carry__1_n_1\,
CO(1) => \ARG_carry__1_n_2\,
CO(0) => \ARG_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^mul_temp_16\(9 downto 6),
O(3 downto 0) => \ARG__31\(24 downto 21),
S(3) => \ARG_carry__1_i_1_n_0\,
S(2) => \ARG_carry__1_i_2_n_0\,
S(1) => \ARG_carry__1_i_3_n_0\,
S(0) => \ARG_carry__1_i_4_n_0\
);
\ARG_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(9),
I1 => \^mul_temp_16\(10),
O => \ARG_carry__1_i_1_n_0\
);
\ARG_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(8),
I1 => \^mul_temp_16\(9),
O => \ARG_carry__1_i_2_n_0\
);
\ARG_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(7),
I1 => \^mul_temp_16\(8),
O => \ARG_carry__1_i_3_n_0\
);
\ARG_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(6),
I1 => \^mul_temp_16\(7),
O => \ARG_carry__1_i_4_n_0\
);
\ARG_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \ARG_carry__1_n_0\,
CO(3) => \ARG_carry__2_n_0\,
CO(2) => \ARG_carry__2_n_1\,
CO(1) => \ARG_carry__2_n_2\,
CO(0) => \ARG_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^mul_temp_16\(13 downto 10),
O(3 downto 0) => \ARG__31\(28 downto 25),
S(3) => \ARG_carry__2_i_1_n_0\,
S(2) => \ARG_carry__2_i_2_n_0\,
S(1) => \ARG_carry__2_i_3_n_0\,
S(0) => \ARG_carry__2_i_4_n_0\
);
\ARG_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(13),
I1 => \^mul_temp_16\(14),
O => \ARG_carry__2_i_1_n_0\
);
\ARG_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(12),
I1 => \^mul_temp_16\(13),
O => \ARG_carry__2_i_2_n_0\
);
\ARG_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(11),
I1 => \^mul_temp_16\(12),
O => \ARG_carry__2_i_3_n_0\
);
\ARG_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(10),
I1 => \^mul_temp_16\(11),
O => \ARG_carry__2_i_4_n_0\
);
\ARG_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \ARG_carry__2_n_0\,
CO(3 downto 1) => \NLW_ARG_carry__3_CO_UNCONNECTED\(3 downto 1),
CO(0) => \ARG_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \^mul_temp_16\(14),
O(3 downto 2) => \NLW_ARG_carry__3_O_UNCONNECTED\(3 downto 2),
O(1) => \ARG__31\(32),
O(0) => \ARG__31\(29),
S(3 downto 1) => B"001",
S(0) => \ARG_carry__3_i_1_n_0\
);
\ARG_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(14),
I1 => \^mul_temp_16\(15),
O => \ARG_carry__3_i_1_n_0\
);
ARG_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_18\(14),
O => ARG_i_1_n_0
);
\add_temp_14__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__0_carry_n_0\,
CO(2) => \add_temp_14__0_carry_n_1\,
CO(1) => \add_temp_14__0_carry_n_2\,
CO(0) => \add_temp_14__0_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__0_carry_i_1_n_0\,
DI(2) => \add_temp_14__0_carry_i_2_n_0\,
DI(1) => \add_temp_14__0_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__0_carry_n_4\,
O(2) => \add_temp_14__0_carry_n_5\,
O(1) => \add_temp_14__0_carry_n_6\,
O(0) => \add_temp_14__0_carry_n_7\,
S(3) => \add_temp_14__0_carry_i_4_n_0\,
S(2) => \add_temp_14__0_carry_i_5_n_0\,
S(1) => \add_temp_14__0_carry_i_6_n_0\,
S(0) => \add_temp_14__0_carry_i_7_n_0\
);
\add_temp_14__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__0_carry_n_0\,
CO(3) => \add_temp_14__0_carry__0_n_0\,
CO(2) => \add_temp_14__0_carry__0_n_1\,
CO(1) => \add_temp_14__0_carry__0_n_2\,
CO(0) => \add_temp_14__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__0_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__0_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__0_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__0_carry__0_i_4_n_0\,
O(3) => \add_temp_14__0_carry__0_n_4\,
O(2) => \add_temp_14__0_carry__0_n_5\,
O(1) => \add_temp_14__0_carry__0_n_6\,
O(0) => \add_temp_14__0_carry__0_n_7\,
S(3) => \add_temp_14__0_carry__0_i_5_n_0\,
S(2) => \add_temp_14__0_carry__0_i_6_n_0\,
S(1) => \add_temp_14__0_carry__0_i_7_n_0\,
S(0) => \add_temp_14__0_carry__0_i_8_n_0\
);
\add_temp_14__0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(6),
I1 => RESIZE15(6),
I2 => RESIZE42(6),
O => \add_temp_14__0_carry__0_i_1_n_0\
);
\add_temp_14__0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(5),
I1 => RESIZE15(5),
I2 => RESIZE42(5),
O => \add_temp_14__0_carry__0_i_2_n_0\
);
\add_temp_14__0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(4),
I1 => RESIZE15(4),
I2 => RESIZE42(4),
O => \add_temp_14__0_carry__0_i_3_n_0\
);
\add_temp_14__0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(3),
I1 => RESIZE15(3),
I2 => RESIZE42(3),
O => \add_temp_14__0_carry__0_i_4_n_0\
);
\add_temp_14__0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(7),
I1 => RESIZE15(7),
I2 => RESIZE42(7),
I3 => \add_temp_14__0_carry__0_i_1_n_0\,
O => \add_temp_14__0_carry__0_i_5_n_0\
);
\add_temp_14__0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(6),
I1 => RESIZE15(6),
I2 => RESIZE42(6),
I3 => \add_temp_14__0_carry__0_i_2_n_0\,
O => \add_temp_14__0_carry__0_i_6_n_0\
);
\add_temp_14__0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(5),
I1 => RESIZE15(5),
I2 => RESIZE42(5),
I3 => \add_temp_14__0_carry__0_i_3_n_0\,
O => \add_temp_14__0_carry__0_i_7_n_0\
);
\add_temp_14__0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(4),
I1 => RESIZE15(4),
I2 => RESIZE42(4),
I3 => \add_temp_14__0_carry__0_i_4_n_0\,
O => \add_temp_14__0_carry__0_i_8_n_0\
);
\add_temp_14__0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__0_carry__0_n_0\,
CO(3) => \add_temp_14__0_carry__1_n_0\,
CO(2) => \add_temp_14__0_carry__1_n_1\,
CO(1) => \add_temp_14__0_carry__1_n_2\,
CO(0) => \add_temp_14__0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__0_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__0_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__0_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__0_carry__1_i_4_n_0\,
O(3) => \add_temp_14__0_carry__1_n_4\,
O(2) => \add_temp_14__0_carry__1_n_5\,
O(1) => \add_temp_14__0_carry__1_n_6\,
O(0) => \add_temp_14__0_carry__1_n_7\,
S(3) => \add_temp_14__0_carry__1_i_5_n_0\,
S(2) => \add_temp_14__0_carry__1_i_6_n_0\,
S(1) => \add_temp_14__0_carry__1_i_7_n_0\,
S(0) => \add_temp_14__0_carry__1_i_8_n_0\
);
\add_temp_14__0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(10),
I1 => RESIZE42(10),
I2 => RESIZE15(10),
O => \add_temp_14__0_carry__1_i_1_n_0\
);
\add_temp_14__0_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(9),
I1 => RESIZE42(9),
I2 => RESIZE15(9),
O => \add_temp_14__0_carry__1_i_2_n_0\
);
\add_temp_14__0_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(8),
I1 => RESIZE15(8),
I2 => RESIZE42(8),
O => \add_temp_14__0_carry__1_i_3_n_0\
);
\add_temp_14__0_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(7),
I1 => RESIZE15(7),
I2 => RESIZE42(7),
O => \add_temp_14__0_carry__1_i_4_n_0\
);
\add_temp_14__0_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(11),
I1 => RESIZE15(11),
I2 => RESIZE42(11),
I3 => \add_temp_14__0_carry__1_i_1_n_0\,
O => \add_temp_14__0_carry__1_i_5_n_0\
);
\add_temp_14__0_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(10),
I1 => RESIZE42(10),
I2 => RESIZE15(10),
I3 => \add_temp_14__0_carry__1_i_2_n_0\,
O => \add_temp_14__0_carry__1_i_6_n_0\
);
\add_temp_14__0_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(9),
I1 => RESIZE42(9),
I2 => RESIZE15(9),
I3 => \add_temp_14__0_carry__1_i_3_n_0\,
O => \add_temp_14__0_carry__1_i_7_n_0\
);
\add_temp_14__0_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(8),
I1 => RESIZE15(8),
I2 => RESIZE42(8),
I3 => \add_temp_14__0_carry__1_i_4_n_0\,
O => \add_temp_14__0_carry__1_i_8_n_0\
);
\add_temp_14__0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__0_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__0_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__0_carry__2_n_1\,
CO(1) => \add_temp_14__0_carry__2_n_2\,
CO(0) => \add_temp_14__0_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__0_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__0_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__0_carry__2_i_3_n_0\,
O(3) => \add_temp_14__0_carry__2_n_4\,
O(2) => \add_temp_14__0_carry__2_n_5\,
O(1) => \add_temp_14__0_carry__2_n_6\,
O(0) => \add_temp_14__0_carry__2_n_7\,
S(3) => \add_temp_14__0_carry__2_i_4_n_0\,
S(2) => \add_temp_14__0_carry__2_i_5_n_0\,
S(1) => \add_temp_14__0_carry__2_i_6_n_0\,
S(0) => \add_temp_14__0_carry__2_i_7_n_0\
);
\add_temp_14__0_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE15(13),
I1 => RESIZE42(13),
I2 => RESIZE44(13),
O => \add_temp_14__0_carry__2_i_1_n_0\
);
\add_temp_14__0_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(12),
I1 => RESIZE15(12),
I2 => RESIZE42(12),
O => \add_temp_14__0_carry__2_i_2_n_0\
);
\add_temp_14__0_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(11),
I1 => RESIZE15(11),
I2 => RESIZE42(11),
O => \add_temp_14__0_carry__2_i_3_n_0\
);
\add_temp_14__0_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE15(14),
I1 => RESIZE44(14),
I2 => RESIZE42(14),
I3 => RESIZE44(15),
I4 => RESIZE42(15),
I5 => RESIZE15(15),
O => \add_temp_14__0_carry__2_i_4_n_0\
);
\add_temp_14__0_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__2_i_1_n_0\,
I1 => RESIZE44(14),
I2 => RESIZE42(14),
I3 => RESIZE15(14),
O => \add_temp_14__0_carry__2_i_5_n_0\
);
\add_temp_14__0_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE15(13),
I1 => RESIZE42(13),
I2 => RESIZE44(13),
I3 => \add_temp_14__0_carry__2_i_2_n_0\,
O => \add_temp_14__0_carry__2_i_6_n_0\
);
\add_temp_14__0_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(12),
I1 => RESIZE15(12),
I2 => RESIZE42(12),
I3 => \add_temp_14__0_carry__2_i_3_n_0\,
O => \add_temp_14__0_carry__2_i_7_n_0\
);
\add_temp_14__0_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(2),
I1 => RESIZE15(2),
I2 => RESIZE42(2),
O => \add_temp_14__0_carry_i_1_n_0\
);
\add_temp_14__0_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(1),
I1 => RESIZE15(1),
I2 => RESIZE42(1),
O => \add_temp_14__0_carry_i_2_n_0\
);
\add_temp_14__0_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(0),
I1 => RESIZE15(0),
I2 => RESIZE42(0),
O => \add_temp_14__0_carry_i_3_n_0\
);
\add_temp_14__0_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(3),
I1 => RESIZE15(3),
I2 => RESIZE42(3),
I3 => \add_temp_14__0_carry_i_1_n_0\,
O => \add_temp_14__0_carry_i_4_n_0\
);
\add_temp_14__0_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(2),
I1 => RESIZE15(2),
I2 => RESIZE42(2),
I3 => \add_temp_14__0_carry_i_2_n_0\,
O => \add_temp_14__0_carry_i_5_n_0\
);
\add_temp_14__0_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(1),
I1 => RESIZE15(1),
I2 => RESIZE42(1),
I3 => \add_temp_14__0_carry_i_3_n_0\,
O => \add_temp_14__0_carry_i_6_n_0\
);
\add_temp_14__0_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE44(0),
I1 => RESIZE15(0),
I2 => RESIZE42(0),
O => \add_temp_14__0_carry_i_7_n_0\
);
\add_temp_14__138_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__138_carry_n_0\,
CO(2) => \add_temp_14__138_carry_n_1\,
CO(1) => \add_temp_14__138_carry_n_2\,
CO(0) => \add_temp_14__138_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__138_carry_i_1_n_0\,
DI(2) => \add_temp_14__138_carry_i_2_n_0\,
DI(1) => \add_temp_14__138_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__138_carry_n_4\,
O(2) => \add_temp_14__138_carry_n_5\,
O(1) => \add_temp_14__138_carry_n_6\,
O(0) => \add_temp_14__138_carry_n_7\,
S(3) => \add_temp_14__138_carry_i_4_n_0\,
S(2) => \add_temp_14__138_carry_i_5_n_0\,
S(1) => \add_temp_14__138_carry_i_6_n_0\,
S(0) => \add_temp_14__138_carry_i_7_n_0\
);
\add_temp_14__138_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__138_carry_n_0\,
CO(3) => \add_temp_14__138_carry__0_n_0\,
CO(2) => \add_temp_14__138_carry__0_n_1\,
CO(1) => \add_temp_14__138_carry__0_n_2\,
CO(0) => \add_temp_14__138_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__138_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__138_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__138_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__138_carry__0_i_4_n_0\,
O(3) => \add_temp_14__138_carry__0_n_4\,
O(2) => \add_temp_14__138_carry__0_n_5\,
O(1) => \add_temp_14__138_carry__0_n_6\,
O(0) => \add_temp_14__138_carry__0_n_7\,
S(3) => \add_temp_14__138_carry__0_i_5_n_0\,
S(2) => \add_temp_14__138_carry__0_i_6_n_0\,
S(1) => \add_temp_14__138_carry__0_i_7_n_0\,
S(0) => \add_temp_14__138_carry__0_i_8_n_0\
);
\add_temp_14__138_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(6),
I1 => RESIZE26(6),
I2 => RESIZE28(6),
O => \add_temp_14__138_carry__0_i_1_n_0\
);
\add_temp_14__138_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE28(5),
I1 => RESIZE24(5),
I2 => RESIZE26(5),
O => \add_temp_14__138_carry__0_i_2_n_0\
);
\add_temp_14__138_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(4),
I1 => RESIZE24(4),
I2 => RESIZE28(4),
O => \add_temp_14__138_carry__0_i_3_n_0\
);
\add_temp_14__138_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(3),
I1 => RESIZE28(3),
I2 => RESIZE24(3),
O => \add_temp_14__138_carry__0_i_4_n_0\
);
\add_temp_14__138_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(7),
I1 => RESIZE26(7),
I2 => RESIZE28(7),
I3 => \add_temp_14__138_carry__0_i_1_n_0\,
O => \add_temp_14__138_carry__0_i_5_n_0\
);
\add_temp_14__138_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(6),
I1 => RESIZE26(6),
I2 => RESIZE28(6),
I3 => \add_temp_14__138_carry__0_i_2_n_0\,
O => \add_temp_14__138_carry__0_i_6_n_0\
);
\add_temp_14__138_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE28(5),
I1 => RESIZE24(5),
I2 => RESIZE26(5),
I3 => \add_temp_14__138_carry__0_i_3_n_0\,
O => \add_temp_14__138_carry__0_i_7_n_0\
);
\add_temp_14__138_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(4),
I1 => RESIZE24(4),
I2 => RESIZE28(4),
I3 => \add_temp_14__138_carry__0_i_4_n_0\,
O => \add_temp_14__138_carry__0_i_8_n_0\
);
\add_temp_14__138_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__138_carry__0_n_0\,
CO(3) => \add_temp_14__138_carry__1_n_0\,
CO(2) => \add_temp_14__138_carry__1_n_1\,
CO(1) => \add_temp_14__138_carry__1_n_2\,
CO(0) => \add_temp_14__138_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__138_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__138_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__138_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__138_carry__1_i_4_n_0\,
O(3) => \add_temp_14__138_carry__1_n_4\,
O(2) => \add_temp_14__138_carry__1_n_5\,
O(1) => \add_temp_14__138_carry__1_n_6\,
O(0) => \add_temp_14__138_carry__1_n_7\,
S(3) => \add_temp_14__138_carry__1_i_5_n_0\,
S(2) => \add_temp_14__138_carry__1_i_6_n_0\,
S(1) => \add_temp_14__138_carry__1_i_7_n_0\,
S(0) => \add_temp_14__138_carry__1_i_8_n_0\
);
\add_temp_14__138_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(10),
I1 => RESIZE26(10),
I2 => RESIZE28(10),
O => \add_temp_14__138_carry__1_i_1_n_0\
);
\add_temp_14__138_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(9),
I1 => RESIZE26(9),
I2 => RESIZE28(9),
O => \add_temp_14__138_carry__1_i_2_n_0\
);
\add_temp_14__138_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(8),
I1 => RESIZE26(8),
I2 => RESIZE28(8),
O => \add_temp_14__138_carry__1_i_3_n_0\
);
\add_temp_14__138_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(7),
I1 => RESIZE26(7),
I2 => RESIZE28(7),
O => \add_temp_14__138_carry__1_i_4_n_0\
);
\add_temp_14__138_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(11),
I1 => RESIZE26(11),
I2 => RESIZE28(11),
I3 => \add_temp_14__138_carry__1_i_1_n_0\,
O => \add_temp_14__138_carry__1_i_5_n_0\
);
\add_temp_14__138_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(10),
I1 => RESIZE26(10),
I2 => RESIZE28(10),
I3 => \add_temp_14__138_carry__1_i_2_n_0\,
O => \add_temp_14__138_carry__1_i_6_n_0\
);
\add_temp_14__138_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(9),
I1 => RESIZE26(9),
I2 => RESIZE28(9),
I3 => \add_temp_14__138_carry__1_i_3_n_0\,
O => \add_temp_14__138_carry__1_i_7_n_0\
);
\add_temp_14__138_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(8),
I1 => RESIZE26(8),
I2 => RESIZE28(8),
I3 => \add_temp_14__138_carry__1_i_4_n_0\,
O => \add_temp_14__138_carry__1_i_8_n_0\
);
\add_temp_14__138_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__138_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__138_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__138_carry__2_n_1\,
CO(1) => \add_temp_14__138_carry__2_n_2\,
CO(0) => \add_temp_14__138_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__138_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__138_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__138_carry__2_i_3_n_0\,
O(3) => \add_temp_14__138_carry__2_n_4\,
O(2) => \add_temp_14__138_carry__2_n_5\,
O(1) => \add_temp_14__138_carry__2_n_6\,
O(0) => \add_temp_14__138_carry__2_n_7\,
S(3) => \add_temp_14__138_carry__2_i_4_n_0\,
S(2) => \add_temp_14__138_carry__2_i_5_n_0\,
S(1) => \add_temp_14__138_carry__2_i_6_n_0\,
S(0) => \add_temp_14__138_carry__2_i_7_n_0\
);
\add_temp_14__138_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(13),
I1 => RESIZE26(13),
I2 => RESIZE28(13),
O => \add_temp_14__138_carry__2_i_1_n_0\
);
\add_temp_14__138_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(12),
I1 => RESIZE26(12),
I2 => RESIZE28(12),
O => \add_temp_14__138_carry__2_i_2_n_0\
);
\add_temp_14__138_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(11),
I1 => RESIZE26(11),
I2 => RESIZE28(11),
O => \add_temp_14__138_carry__2_i_3_n_0\
);
\add_temp_14__138_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE28(14),
I1 => RESIZE26(14),
I2 => RESIZE24(14),
I3 => RESIZE26(15),
I4 => RESIZE24(15),
I5 => RESIZE28(15),
O => \add_temp_14__138_carry__2_i_4_n_0\
);
\add_temp_14__138_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__138_carry__2_i_1_n_0\,
I1 => RESIZE26(14),
I2 => RESIZE24(14),
I3 => RESIZE28(14),
O => \add_temp_14__138_carry__2_i_5_n_0\
);
\add_temp_14__138_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(13),
I1 => RESIZE26(13),
I2 => RESIZE28(13),
I3 => \add_temp_14__138_carry__2_i_2_n_0\,
O => \add_temp_14__138_carry__2_i_6_n_0\
);
\add_temp_14__138_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(12),
I1 => RESIZE26(12),
I2 => RESIZE28(12),
I3 => \add_temp_14__138_carry__2_i_3_n_0\,
O => \add_temp_14__138_carry__2_i_7_n_0\
);
\add_temp_14__138_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(2),
I1 => RESIZE28(2),
I2 => RESIZE24(2),
O => \add_temp_14__138_carry_i_1_n_0\
);
\add_temp_14__138_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(1),
I1 => RESIZE28(1),
I2 => RESIZE24(1),
O => \add_temp_14__138_carry_i_2_n_0\
);
\add_temp_14__138_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(0),
I1 => RESIZE28(0),
I2 => RESIZE24(0),
O => \add_temp_14__138_carry_i_3_n_0\
);
\add_temp_14__138_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(3),
I1 => RESIZE28(3),
I2 => RESIZE24(3),
I3 => \add_temp_14__138_carry_i_1_n_0\,
O => \add_temp_14__138_carry_i_4_n_0\
);
\add_temp_14__138_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(2),
I1 => RESIZE28(2),
I2 => RESIZE24(2),
I3 => \add_temp_14__138_carry_i_2_n_0\,
O => \add_temp_14__138_carry_i_5_n_0\
);
\add_temp_14__138_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(1),
I1 => RESIZE28(1),
I2 => RESIZE24(1),
I3 => \add_temp_14__138_carry_i_3_n_0\,
O => \add_temp_14__138_carry_i_6_n_0\
);
\add_temp_14__138_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE26(0),
I1 => RESIZE28(0),
I2 => RESIZE24(0),
O => \add_temp_14__138_carry_i_7_n_0\
);
\add_temp_14__184_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__184_carry_n_0\,
CO(2) => \add_temp_14__184_carry_n_1\,
CO(1) => \add_temp_14__184_carry_n_2\,
CO(0) => \add_temp_14__184_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__184_carry_i_1_n_0\,
DI(2) => \add_temp_14__184_carry_i_2_n_0\,
DI(1) => \add_temp_14__184_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__184_carry_n_4\,
O(2) => \add_temp_14__184_carry_n_5\,
O(1) => \add_temp_14__184_carry_n_6\,
O(0) => \add_temp_14__184_carry_n_7\,
S(3) => \add_temp_14__184_carry_i_4_n_0\,
S(2) => \add_temp_14__184_carry_i_5_n_0\,
S(1) => \add_temp_14__184_carry_i_6_n_0\,
S(0) => \add_temp_14__184_carry_i_7_n_0\
);
\add_temp_14__184_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__184_carry_n_0\,
CO(3) => \add_temp_14__184_carry__0_n_0\,
CO(2) => \add_temp_14__184_carry__0_n_1\,
CO(1) => \add_temp_14__184_carry__0_n_2\,
CO(0) => \add_temp_14__184_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__184_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__184_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__184_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__184_carry__0_i_4_n_0\,
O(3) => \add_temp_14__184_carry__0_n_4\,
O(2) => \add_temp_14__184_carry__0_n_5\,
O(1) => \add_temp_14__184_carry__0_n_6\,
O(0) => \add_temp_14__184_carry__0_n_7\,
S(3) => \add_temp_14__184_carry__0_i_5_n_0\,
S(2) => \add_temp_14__184_carry__0_i_6_n_0\,
S(1) => \add_temp_14__184_carry__0_i_7_n_0\,
S(0) => \add_temp_14__184_carry__0_i_8_n_0\
);
\add_temp_14__184_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(6),
I1 => RESIZE18(6),
I2 => RESIZE22(6),
O => \add_temp_14__184_carry__0_i_1_n_0\
);
\add_temp_14__184_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(5),
I1 => RESIZE18(5),
I2 => RESIZE22(5),
O => \add_temp_14__184_carry__0_i_2_n_0\
);
\add_temp_14__184_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(4),
I1 => RESIZE18(4),
I2 => RESIZE22(4),
O => \add_temp_14__184_carry__0_i_3_n_0\
);
\add_temp_14__184_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(3),
I1 => RESIZE22(3),
I2 => RESIZE20(3),
O => \add_temp_14__184_carry__0_i_4_n_0\
);
\add_temp_14__184_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(7),
I1 => RESIZE18(7),
I2 => RESIZE22(7),
I3 => \add_temp_14__184_carry__0_i_1_n_0\,
O => \add_temp_14__184_carry__0_i_5_n_0\
);
\add_temp_14__184_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(6),
I1 => RESIZE18(6),
I2 => RESIZE22(6),
I3 => \add_temp_14__184_carry__0_i_2_n_0\,
O => \add_temp_14__184_carry__0_i_6_n_0\
);
\add_temp_14__184_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(5),
I1 => RESIZE18(5),
I2 => RESIZE22(5),
I3 => \add_temp_14__184_carry__0_i_3_n_0\,
O => \add_temp_14__184_carry__0_i_7_n_0\
);
\add_temp_14__184_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(4),
I1 => RESIZE18(4),
I2 => RESIZE22(4),
I3 => \add_temp_14__184_carry__0_i_4_n_0\,
O => \add_temp_14__184_carry__0_i_8_n_0\
);
\add_temp_14__184_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__184_carry__0_n_0\,
CO(3) => \add_temp_14__184_carry__1_n_0\,
CO(2) => \add_temp_14__184_carry__1_n_1\,
CO(1) => \add_temp_14__184_carry__1_n_2\,
CO(0) => \add_temp_14__184_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__184_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__184_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__184_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__184_carry__1_i_4_n_0\,
O(3) => \add_temp_14__184_carry__1_n_4\,
O(2) => \add_temp_14__184_carry__1_n_5\,
O(1) => \add_temp_14__184_carry__1_n_6\,
O(0) => \add_temp_14__184_carry__1_n_7\,
S(3) => \add_temp_14__184_carry__1_i_5_n_0\,
S(2) => \add_temp_14__184_carry__1_i_6_n_0\,
S(1) => \add_temp_14__184_carry__1_i_7_n_0\,
S(0) => \add_temp_14__184_carry__1_i_8_n_0\
);
\add_temp_14__184_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(10),
I1 => RESIZE22(10),
I2 => RESIZE20(10),
O => \add_temp_14__184_carry__1_i_1_n_0\
);
\add_temp_14__184_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(9),
I1 => RESIZE22(9),
I2 => RESIZE20(9),
O => \add_temp_14__184_carry__1_i_2_n_0\
);
\add_temp_14__184_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(8),
I1 => RESIZE22(8),
I2 => RESIZE20(8),
O => \add_temp_14__184_carry__1_i_3_n_0\
);
\add_temp_14__184_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(7),
I1 => RESIZE18(7),
I2 => RESIZE22(7),
O => \add_temp_14__184_carry__1_i_4_n_0\
);
\add_temp_14__184_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(11),
I1 => RESIZE22(11),
I2 => RESIZE20(11),
I3 => \add_temp_14__184_carry__1_i_1_n_0\,
O => \add_temp_14__184_carry__1_i_5_n_0\
);
\add_temp_14__184_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(10),
I1 => RESIZE22(10),
I2 => RESIZE20(10),
I3 => \add_temp_14__184_carry__1_i_2_n_0\,
O => \add_temp_14__184_carry__1_i_6_n_0\
);
\add_temp_14__184_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(9),
I1 => RESIZE22(9),
I2 => RESIZE20(9),
I3 => \add_temp_14__184_carry__1_i_3_n_0\,
O => \add_temp_14__184_carry__1_i_7_n_0\
);
\add_temp_14__184_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(8),
I1 => RESIZE22(8),
I2 => RESIZE20(8),
I3 => \add_temp_14__184_carry__1_i_4_n_0\,
O => \add_temp_14__184_carry__1_i_8_n_0\
);
\add_temp_14__184_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__184_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__184_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__184_carry__2_n_1\,
CO(1) => \add_temp_14__184_carry__2_n_2\,
CO(0) => \add_temp_14__184_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__184_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__184_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__184_carry__2_i_3_n_0\,
O(3) => \add_temp_14__184_carry__2_n_4\,
O(2) => \add_temp_14__184_carry__2_n_5\,
O(1) => \add_temp_14__184_carry__2_n_6\,
O(0) => \add_temp_14__184_carry__2_n_7\,
S(3) => \add_temp_14__184_carry__2_i_4_n_0\,
S(2) => \add_temp_14__184_carry__2_i_5_n_0\,
S(1) => \add_temp_14__184_carry__2_i_6_n_0\,
S(0) => \add_temp_14__184_carry__2_i_7_n_0\
);
\add_temp_14__184_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(13),
I1 => RESIZE22(13),
I2 => RESIZE20(13),
O => \add_temp_14__184_carry__2_i_1_n_0\
);
\add_temp_14__184_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(12),
I1 => RESIZE22(12),
I2 => RESIZE20(12),
O => \add_temp_14__184_carry__2_i_2_n_0\
);
\add_temp_14__184_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(11),
I1 => RESIZE22(11),
I2 => RESIZE20(11),
O => \add_temp_14__184_carry__2_i_3_n_0\
);
\add_temp_14__184_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE20(14),
I1 => RESIZE22(14),
I2 => RESIZE18(14),
I3 => RESIZE20(15),
I4 => RESIZE18(15),
I5 => RESIZE22(15),
O => \add_temp_14__184_carry__2_i_4_n_0\
);
\add_temp_14__184_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry__2_i_1_n_0\,
I1 => RESIZE20(14),
I2 => RESIZE18(14),
I3 => RESIZE22(14),
O => \add_temp_14__184_carry__2_i_5_n_0\
);
\add_temp_14__184_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(13),
I1 => RESIZE22(13),
I2 => RESIZE20(13),
I3 => \add_temp_14__184_carry__2_i_2_n_0\,
O => \add_temp_14__184_carry__2_i_6_n_0\
);
\add_temp_14__184_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(12),
I1 => RESIZE22(12),
I2 => RESIZE20(12),
I3 => \add_temp_14__184_carry__2_i_3_n_0\,
O => \add_temp_14__184_carry__2_i_7_n_0\
);
\add_temp_14__184_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE22(2),
I1 => RESIZE18(2),
I2 => RESIZE20(2),
O => \add_temp_14__184_carry_i_1_n_0\
);
\add_temp_14__184_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(1),
I1 => RESIZE18(1),
I2 => RESIZE22(1),
O => \add_temp_14__184_carry_i_2_n_0\
);
\add_temp_14__184_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(0),
I1 => RESIZE22(0),
I2 => RESIZE20(0),
O => \add_temp_14__184_carry_i_3_n_0\
);
\add_temp_14__184_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(3),
I1 => RESIZE22(3),
I2 => RESIZE20(3),
I3 => \add_temp_14__184_carry_i_1_n_0\,
O => \add_temp_14__184_carry_i_4_n_0\
);
\add_temp_14__184_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE22(2),
I1 => RESIZE18(2),
I2 => RESIZE20(2),
I3 => \add_temp_14__184_carry_i_2_n_0\,
O => \add_temp_14__184_carry_i_5_n_0\
);
\add_temp_14__184_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(1),
I1 => RESIZE18(1),
I2 => RESIZE22(1),
I3 => \add_temp_14__184_carry_i_3_n_0\,
O => \add_temp_14__184_carry_i_6_n_0\
);
\add_temp_14__184_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE18(0),
I1 => RESIZE22(0),
I2 => RESIZE20(0),
O => \add_temp_14__184_carry_i_7_n_0\
);
\add_temp_14__230_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__230_carry_n_0\,
CO(2) => \add_temp_14__230_carry_n_1\,
CO(1) => \add_temp_14__230_carry_n_2\,
CO(0) => \add_temp_14__230_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__230_carry_i_1_n_0\,
DI(2) => \add_temp_14__230_carry_i_2_n_0\,
DI(1) => \add_temp_14__230_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__230_carry_n_4\,
O(2) => \add_temp_14__230_carry_n_5\,
O(1) => \add_temp_14__230_carry_n_6\,
O(0) => \add_temp_14__230_carry_n_7\,
S(3) => \add_temp_14__230_carry_i_4_n_0\,
S(2) => \add_temp_14__230_carry_i_5_n_0\,
S(1) => \add_temp_14__230_carry_i_6_n_0\,
S(0) => \add_temp_14__230_carry_i_7_n_0\
);
\add_temp_14__230_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__230_carry_n_0\,
CO(3) => \add_temp_14__230_carry__0_n_0\,
CO(2) => \add_temp_14__230_carry__0_n_1\,
CO(1) => \add_temp_14__230_carry__0_n_2\,
CO(0) => \add_temp_14__230_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__230_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__230_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__230_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__230_carry__0_i_4_n_0\,
O(3) => \add_temp_14__230_carry__0_n_4\,
O(2) => \add_temp_14__230_carry__0_n_5\,
O(1) => \add_temp_14__230_carry__0_n_6\,
O(0) => \add_temp_14__230_carry__0_n_7\,
S(3) => \add_temp_14__230_carry__0_i_5_n_0\,
S(2) => \add_temp_14__230_carry__0_i_6_n_0\,
S(1) => \add_temp_14__230_carry__0_i_7_n_0\,
S(0) => \add_temp_14__230_carry__0_i_8_n_0\
);
\add_temp_14__230_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(6),
I1 => \add_temp_14__0_carry__0_n_5\,
I2 => \add_temp_14__46_carry__0_n_5\,
O => \add_temp_14__230_carry__0_i_1_n_0\
);
\add_temp_14__230_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(5),
I1 => \add_temp_14__46_carry__0_n_6\,
I2 => \add_temp_14__0_carry__0_n_6\,
O => \add_temp_14__230_carry__0_i_2_n_0\
);
\add_temp_14__230_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__0_n_7\,
I1 => \add_temp_14__46_carry__0_n_7\,
I2 => RESIZE16(4),
O => \add_temp_14__230_carry__0_i_3_n_0\
);
\add_temp_14__230_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry_n_4\,
I1 => \add_temp_14__46_carry_n_4\,
I2 => RESIZE16(3),
O => \add_temp_14__230_carry__0_i_4_n_0\
);
\add_temp_14__230_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__0_n_4\,
I1 => \add_temp_14__46_carry__0_n_4\,
I2 => RESIZE16(7),
I3 => \add_temp_14__230_carry__0_i_1_n_0\,
O => \add_temp_14__230_carry__0_i_5_n_0\
);
\add_temp_14__230_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(6),
I1 => \add_temp_14__0_carry__0_n_5\,
I2 => \add_temp_14__46_carry__0_n_5\,
I3 => \add_temp_14__230_carry__0_i_2_n_0\,
O => \add_temp_14__230_carry__0_i_6_n_0\
);
\add_temp_14__230_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(5),
I1 => \add_temp_14__46_carry__0_n_6\,
I2 => \add_temp_14__0_carry__0_n_6\,
I3 => \add_temp_14__230_carry__0_i_3_n_0\,
O => \add_temp_14__230_carry__0_i_7_n_0\
);
\add_temp_14__230_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__0_n_7\,
I1 => \add_temp_14__46_carry__0_n_7\,
I2 => RESIZE16(4),
I3 => \add_temp_14__230_carry__0_i_4_n_0\,
O => \add_temp_14__230_carry__0_i_8_n_0\
);
\add_temp_14__230_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__230_carry__0_n_0\,
CO(3) => \add_temp_14__230_carry__1_n_0\,
CO(2) => \add_temp_14__230_carry__1_n_1\,
CO(1) => \add_temp_14__230_carry__1_n_2\,
CO(0) => \add_temp_14__230_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__230_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__230_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__230_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__230_carry__1_i_4_n_0\,
O(3) => \add_temp_14__230_carry__1_n_4\,
O(2) => \add_temp_14__230_carry__1_n_5\,
O(1) => \add_temp_14__230_carry__1_n_6\,
O(0) => \add_temp_14__230_carry__1_n_7\,
S(3) => \add_temp_14__230_carry__1_i_5_n_0\,
S(2) => \add_temp_14__230_carry__1_i_6_n_0\,
S(1) => \add_temp_14__230_carry__1_i_7_n_0\,
S(0) => \add_temp_14__230_carry__1_i_8_n_0\
);
\add_temp_14__230_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(10),
I1 => \add_temp_14__0_carry__1_n_5\,
I2 => \add_temp_14__46_carry__1_n_5\,
O => \add_temp_14__230_carry__1_i_1_n_0\
);
\add_temp_14__230_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__1_n_6\,
I1 => \add_temp_14__46_carry__1_n_6\,
I2 => RESIZE16(9),
O => \add_temp_14__230_carry__1_i_2_n_0\
);
\add_temp_14__230_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__1_n_7\,
I1 => RESIZE16(8),
I2 => \add_temp_14__46_carry__1_n_7\,
O => \add_temp_14__230_carry__1_i_3_n_0\
);
\add_temp_14__230_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__0_n_4\,
I1 => \add_temp_14__46_carry__0_n_4\,
I2 => RESIZE16(7),
O => \add_temp_14__230_carry__1_i_4_n_0\
);
\add_temp_14__230_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(11),
I1 => \add_temp_14__0_carry__1_n_4\,
I2 => \add_temp_14__46_carry__1_n_4\,
I3 => \add_temp_14__230_carry__1_i_1_n_0\,
O => \add_temp_14__230_carry__1_i_5_n_0\
);
\add_temp_14__230_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(10),
I1 => \add_temp_14__0_carry__1_n_5\,
I2 => \add_temp_14__46_carry__1_n_5\,
I3 => \add_temp_14__230_carry__1_i_2_n_0\,
O => \add_temp_14__230_carry__1_i_6_n_0\
);
\add_temp_14__230_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__1_n_6\,
I1 => \add_temp_14__46_carry__1_n_6\,
I2 => RESIZE16(9),
I3 => \add_temp_14__230_carry__1_i_3_n_0\,
O => \add_temp_14__230_carry__1_i_7_n_0\
);
\add_temp_14__230_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__1_n_7\,
I1 => RESIZE16(8),
I2 => \add_temp_14__46_carry__1_n_7\,
I3 => \add_temp_14__230_carry__1_i_4_n_0\,
O => \add_temp_14__230_carry__1_i_8_n_0\
);
\add_temp_14__230_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__230_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__230_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__230_carry__2_n_1\,
CO(1) => \add_temp_14__230_carry__2_n_2\,
CO(0) => \add_temp_14__230_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__230_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__230_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__230_carry__2_i_3_n_0\,
O(3) => \add_temp_14__230_carry__2_n_4\,
O(2) => \add_temp_14__230_carry__2_n_5\,
O(1) => \add_temp_14__230_carry__2_n_6\,
O(0) => \add_temp_14__230_carry__2_n_7\,
S(3) => \add_temp_14__230_carry__2_i_4_n_0\,
S(2) => \add_temp_14__230_carry__2_i_5_n_0\,
S(1) => \add_temp_14__230_carry__2_i_6_n_0\,
S(0) => \add_temp_14__230_carry__2_i_7_n_0\
);
\add_temp_14__230_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(13),
I1 => \add_temp_14__0_carry__2_n_6\,
I2 => \add_temp_14__46_carry__2_n_6\,
O => \add_temp_14__230_carry__2_i_1_n_0\
);
\add_temp_14__230_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(12),
I1 => \add_temp_14__0_carry__2_n_7\,
I2 => \add_temp_14__46_carry__2_n_7\,
O => \add_temp_14__230_carry__2_i_2_n_0\
);
\add_temp_14__230_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(11),
I1 => \add_temp_14__0_carry__1_n_4\,
I2 => \add_temp_14__46_carry__1_n_4\,
O => \add_temp_14__230_carry__2_i_3_n_0\
);
\add_temp_14__230_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => \add_temp_14__46_carry__2_n_5\,
I1 => \add_temp_14__0_carry__2_n_5\,
I2 => RESIZE16(14),
I3 => \add_temp_14__0_carry__2_n_4\,
I4 => \add_temp_14__46_carry__2_n_4\,
I5 => RESIZE16(15),
O => \add_temp_14__230_carry__2_i_4_n_0\
);
\add_temp_14__230_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__230_carry__2_i_1_n_0\,
I1 => \add_temp_14__0_carry__2_n_5\,
I2 => \add_temp_14__46_carry__2_n_5\,
I3 => RESIZE16(14),
O => \add_temp_14__230_carry__2_i_5_n_0\
);
\add_temp_14__230_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(13),
I1 => \add_temp_14__0_carry__2_n_6\,
I2 => \add_temp_14__46_carry__2_n_6\,
I3 => \add_temp_14__230_carry__2_i_2_n_0\,
O => \add_temp_14__230_carry__2_i_6_n_0\
);
\add_temp_14__230_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(12),
I1 => \add_temp_14__0_carry__2_n_7\,
I2 => \add_temp_14__46_carry__2_n_7\,
I3 => \add_temp_14__230_carry__2_i_3_n_0\,
O => \add_temp_14__230_carry__2_i_7_n_0\
);
\add_temp_14__230_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__46_carry_n_5\,
I1 => \add_temp_14__0_carry_n_5\,
I2 => RESIZE16(2),
O => \add_temp_14__230_carry_i_1_n_0\
);
\add_temp_14__230_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry_n_6\,
I1 => RESIZE16(1),
I2 => \add_temp_14__46_carry_n_6\,
O => \add_temp_14__230_carry_i_2_n_0\
);
\add_temp_14__230_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__46_carry_n_7\,
I1 => \add_temp_14__0_carry_n_7\,
I2 => RESIZE16(0),
O => \add_temp_14__230_carry_i_3_n_0\
);
\add_temp_14__230_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry_n_4\,
I1 => \add_temp_14__46_carry_n_4\,
I2 => RESIZE16(3),
I3 => \add_temp_14__230_carry_i_1_n_0\,
O => \add_temp_14__230_carry_i_4_n_0\
);
\add_temp_14__230_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__46_carry_n_5\,
I1 => \add_temp_14__0_carry_n_5\,
I2 => RESIZE16(2),
I3 => \add_temp_14__230_carry_i_2_n_0\,
O => \add_temp_14__230_carry_i_5_n_0\
);
\add_temp_14__230_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry_n_6\,
I1 => RESIZE16(1),
I2 => \add_temp_14__46_carry_n_6\,
I3 => \add_temp_14__230_carry_i_3_n_0\,
O => \add_temp_14__230_carry_i_6_n_0\
);
\add_temp_14__230_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__46_carry_n_7\,
I1 => \add_temp_14__0_carry_n_7\,
I2 => RESIZE16(0),
O => \add_temp_14__230_carry_i_7_n_0\
);
\add_temp_14__278_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__278_carry_n_0\,
CO(2) => \add_temp_14__278_carry_n_1\,
CO(1) => \add_temp_14__278_carry_n_2\,
CO(0) => \add_temp_14__278_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__278_carry_i_1_n_0\,
DI(2) => \add_temp_14__278_carry_i_2_n_0\,
DI(1) => \add_temp_14__278_carry_i_3_n_0\,
DI(0) => \add_temp_14__92_carry_n_7\,
O(3 downto 0) => filter_sum(3 downto 0),
S(3) => \add_temp_14__278_carry_i_4_n_0\,
S(2) => \add_temp_14__278_carry_i_5_n_0\,
S(1) => \add_temp_14__278_carry_i_6_n_0\,
S(0) => \add_temp_14__278_carry_i_7_n_0\
);
\add_temp_14__278_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__278_carry_n_0\,
CO(3) => \add_temp_14__278_carry__0_n_0\,
CO(2) => \add_temp_14__278_carry__0_n_1\,
CO(1) => \add_temp_14__278_carry__0_n_2\,
CO(0) => \add_temp_14__278_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__278_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__278_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__278_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__278_carry__0_i_4_n_0\,
O(3 downto 0) => filter_sum(7 downto 4),
S(3) => \add_temp_14__278_carry__0_i_5_n_0\,
S(2) => \add_temp_14__278_carry__0_i_6_n_0\,
S(1) => \add_temp_14__278_carry__0_i_7_n_0\,
S(0) => \add_temp_14__278_carry__0_i_8_n_0\
);
\add_temp_14__278_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__0_n_5\,
I1 => \add_temp_14__230_carry__0_n_5\,
I2 => \add_temp_14__184_carry__0_n_5\,
I3 => \add_temp_14__278_carry__0_i_9_n_0\,
I4 => \add_temp_14__92_carry__0_n_5\,
O => \add_temp_14__278_carry__0_i_1_n_0\
);
\add_temp_14__278_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__230_carry__0_n_7\,
I1 => \add_temp_14__184_carry__0_n_7\,
I2 => \add_temp_14__138_carry__0_n_7\,
O => \add_temp_14__278_carry__0_i_10_n_0\
);
\add_temp_14__278_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__230_carry_n_4\,
I1 => \add_temp_14__184_carry_n_4\,
I2 => \add_temp_14__138_carry_n_4\,
O => \add_temp_14__278_carry__0_i_11_n_0\
);
\add_temp_14__278_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__0_n_4\,
I1 => \add_temp_14__230_carry__0_n_4\,
I2 => \add_temp_14__184_carry__0_n_4\,
O => \add_temp_14__278_carry__0_i_12_n_0\
);
\add_temp_14__278_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__0_n_6\,
I1 => \add_temp_14__230_carry__0_n_6\,
I2 => \add_temp_14__184_carry__0_n_6\,
I3 => \add_temp_14__278_carry__0_i_10_n_0\,
I4 => \add_temp_14__92_carry__0_n_6\,
O => \add_temp_14__278_carry__0_i_2_n_0\
);
\add_temp_14__278_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__0_n_7\,
I1 => \add_temp_14__230_carry__0_n_7\,
I2 => \add_temp_14__184_carry__0_n_7\,
I3 => \add_temp_14__278_carry__0_i_11_n_0\,
I4 => \add_temp_14__92_carry__0_n_7\,
O => \add_temp_14__278_carry__0_i_3_n_0\
);
\add_temp_14__278_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry_n_4\,
I1 => \add_temp_14__230_carry_n_4\,
I2 => \add_temp_14__184_carry_n_4\,
I3 => \add_temp_14__278_carry_i_9_n_0\,
I4 => \add_temp_14__92_carry_n_4\,
O => \add_temp_14__278_carry__0_i_4_n_0\
);
\add_temp_14__278_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__0_i_1_n_0\,
I1 => \add_temp_14__278_carry__0_i_12_n_0\,
I2 => \add_temp_14__92_carry__0_n_4\,
I3 => \add_temp_14__138_carry__0_n_5\,
I4 => \add_temp_14__184_carry__0_n_5\,
I5 => \add_temp_14__230_carry__0_n_5\,
O => \add_temp_14__278_carry__0_i_5_n_0\
);
\add_temp_14__278_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__0_i_2_n_0\,
I1 => \add_temp_14__184_carry__0_n_5\,
I2 => \add_temp_14__230_carry__0_n_5\,
I3 => \add_temp_14__138_carry__0_n_5\,
I4 => \add_temp_14__92_carry__0_n_5\,
I5 => \add_temp_14__278_carry__0_i_9_n_0\,
O => \add_temp_14__278_carry__0_i_6_n_0\
);
\add_temp_14__278_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__0_i_3_n_0\,
I1 => \add_temp_14__184_carry__0_n_6\,
I2 => \add_temp_14__230_carry__0_n_6\,
I3 => \add_temp_14__138_carry__0_n_6\,
I4 => \add_temp_14__92_carry__0_n_6\,
I5 => \add_temp_14__278_carry__0_i_10_n_0\,
O => \add_temp_14__278_carry__0_i_7_n_0\
);
\add_temp_14__278_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__0_i_4_n_0\,
I1 => \add_temp_14__184_carry__0_n_7\,
I2 => \add_temp_14__230_carry__0_n_7\,
I3 => \add_temp_14__138_carry__0_n_7\,
I4 => \add_temp_14__92_carry__0_n_7\,
I5 => \add_temp_14__278_carry__0_i_11_n_0\,
O => \add_temp_14__278_carry__0_i_8_n_0\
);
\add_temp_14__278_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__138_carry__0_n_6\,
I1 => \add_temp_14__184_carry__0_n_6\,
I2 => \add_temp_14__230_carry__0_n_6\,
O => \add_temp_14__278_carry__0_i_9_n_0\
);
\add_temp_14__278_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__278_carry__0_n_0\,
CO(3) => \add_temp_14__278_carry__1_n_0\,
CO(2) => \add_temp_14__278_carry__1_n_1\,
CO(1) => \add_temp_14__278_carry__1_n_2\,
CO(0) => \add_temp_14__278_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__278_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__278_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__278_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__278_carry__1_i_4_n_0\,
O(3 downto 0) => filter_sum(11 downto 8),
S(3) => \add_temp_14__278_carry__1_i_5_n_0\,
S(2) => \add_temp_14__278_carry__1_i_6_n_0\,
S(1) => \add_temp_14__278_carry__1_i_7_n_0\,
S(0) => \add_temp_14__278_carry__1_i_8_n_0\
);
\add_temp_14__278_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__1_n_5\,
I1 => \add_temp_14__230_carry__1_n_5\,
I2 => \add_temp_14__184_carry__1_n_5\,
I3 => \add_temp_14__278_carry__1_i_9_n_0\,
I4 => \add_temp_14__92_carry__1_n_5\,
O => \add_temp_14__278_carry__1_i_1_n_0\
);
\add_temp_14__278_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__1_n_7\,
I1 => \add_temp_14__138_carry__1_n_7\,
I2 => \add_temp_14__230_carry__1_n_7\,
O => \add_temp_14__278_carry__1_i_10_n_0\
);
\add_temp_14__278_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__1_n_7\,
I1 => \add_temp_14__230_carry__1_n_7\,
I2 => \add_temp_14__184_carry__1_n_7\,
O => \add_temp_14__278_carry__1_i_11_n_0\
);
\add_temp_14__278_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__1_n_4\,
I1 => \add_temp_14__230_carry__1_n_4\,
I2 => \add_temp_14__184_carry__1_n_4\,
O => \add_temp_14__278_carry__1_i_12_n_0\
);
\add_temp_14__278_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__1_n_6\,
I1 => \add_temp_14__230_carry__1_n_6\,
I2 => \add_temp_14__184_carry__1_n_6\,
I3 => \add_temp_14__278_carry__1_i_10_n_0\,
I4 => \add_temp_14__92_carry__1_n_6\,
O => \add_temp_14__278_carry__1_i_2_n_0\
);
\add_temp_14__278_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__1_n_7\,
I1 => \add_temp_14__138_carry__0_n_4\,
I2 => \add_temp_14__184_carry__0_n_4\,
I3 => \add_temp_14__230_carry__0_n_4\,
I4 => \add_temp_14__278_carry__1_i_11_n_0\,
O => \add_temp_14__278_carry__1_i_3_n_0\
);
\add_temp_14__278_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__0_n_4\,
I1 => \add_temp_14__230_carry__0_n_5\,
I2 => \add_temp_14__184_carry__0_n_5\,
I3 => \add_temp_14__138_carry__0_n_5\,
I4 => \add_temp_14__278_carry__0_i_12_n_0\,
O => \add_temp_14__278_carry__1_i_4_n_0\
);
\add_temp_14__278_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__1_i_1_n_0\,
I1 => \add_temp_14__278_carry__1_i_12_n_0\,
I2 => \add_temp_14__92_carry__1_n_4\,
I3 => \add_temp_14__230_carry__1_n_5\,
I4 => \add_temp_14__184_carry__1_n_5\,
I5 => \add_temp_14__138_carry__1_n_5\,
O => \add_temp_14__278_carry__1_i_5_n_0\
);
\add_temp_14__278_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__1_i_2_n_0\,
I1 => \add_temp_14__184_carry__1_n_5\,
I2 => \add_temp_14__230_carry__1_n_5\,
I3 => \add_temp_14__138_carry__1_n_5\,
I4 => \add_temp_14__92_carry__1_n_5\,
I5 => \add_temp_14__278_carry__1_i_9_n_0\,
O => \add_temp_14__278_carry__1_i_6_n_0\
);
\add_temp_14__278_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__1_i_3_n_0\,
I1 => \add_temp_14__184_carry__1_n_6\,
I2 => \add_temp_14__230_carry__1_n_6\,
I3 => \add_temp_14__138_carry__1_n_6\,
I4 => \add_temp_14__92_carry__1_n_6\,
I5 => \add_temp_14__278_carry__1_i_10_n_0\,
O => \add_temp_14__278_carry__1_i_7_n_0\
);
\add_temp_14__278_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__1_i_4_n_0\,
I1 => \add_temp_14__278_carry__1_i_11_n_0\,
I2 => \add_temp_14__92_carry__1_n_7\,
I3 => \add_temp_14__230_carry__0_n_4\,
I4 => \add_temp_14__184_carry__0_n_4\,
I5 => \add_temp_14__138_carry__0_n_4\,
O => \add_temp_14__278_carry__1_i_8_n_0\
);
\add_temp_14__278_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__1_n_6\,
I1 => \add_temp_14__230_carry__1_n_6\,
I2 => \add_temp_14__138_carry__1_n_6\,
O => \add_temp_14__278_carry__1_i_9_n_0\
);
\add_temp_14__278_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__278_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__278_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__278_carry__2_n_1\,
CO(1) => \add_temp_14__278_carry__2_n_2\,
CO(0) => \add_temp_14__278_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__278_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__278_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__278_carry__2_i_3_n_0\,
O(3 downto 0) => filter_sum(15 downto 12),
S(3) => \add_temp_14__278_carry__2_i_4_n_0\,
S(2) => \add_temp_14__278_carry__2_i_5_n_0\,
S(1) => \add_temp_14__278_carry__2_i_6_n_0\,
S(0) => \add_temp_14__278_carry__2_i_7_n_0\
);
\add_temp_14__278_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__2_n_6\,
I1 => \add_temp_14__230_carry__2_n_6\,
I2 => \add_temp_14__184_carry__2_n_6\,
I3 => \add_temp_14__278_carry__2_i_8_n_0\,
I4 => \add_temp_14__92_carry__2_n_6\,
O => \add_temp_14__278_carry__2_i_1_n_0\
);
\add_temp_14__278_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__2_n_6\,
I1 => \add_temp_14__230_carry__2_n_6\,
I2 => \add_temp_14__138_carry__2_n_6\,
O => \add_temp_14__278_carry__2_i_10_n_0\
);
\add_temp_14__278_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry__2_n_4\,
I1 => \add_temp_14__230_carry__2_n_4\,
I2 => \add_temp_14__138_carry__2_n_4\,
I3 => \add_temp_14__92_carry__2_n_4\,
O => \add_temp_14__278_carry__2_i_11_n_0\
);
\add_temp_14__278_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__2_n_7\,
I1 => \add_temp_14__138_carry__1_n_4\,
I2 => \add_temp_14__184_carry__1_n_4\,
I3 => \add_temp_14__230_carry__1_n_4\,
I4 => \add_temp_14__278_carry__2_i_9_n_0\,
O => \add_temp_14__278_carry__2_i_2_n_0\
);
\add_temp_14__278_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__1_n_4\,
I1 => \add_temp_14__138_carry__1_n_5\,
I2 => \add_temp_14__184_carry__1_n_5\,
I3 => \add_temp_14__230_carry__1_n_5\,
I4 => \add_temp_14__278_carry__1_i_12_n_0\,
O => \add_temp_14__278_carry__2_i_3_n_0\
);
\add_temp_14__278_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"E187871E871E1E78"
)
port map (
I0 => \add_temp_14__92_carry__2_n_5\,
I1 => \add_temp_14__278_carry__2_i_10_n_0\,
I2 => \add_temp_14__278_carry__2_i_11_n_0\,
I3 => \add_temp_14__138_carry__2_n_5\,
I4 => \add_temp_14__184_carry__2_n_5\,
I5 => \add_temp_14__230_carry__2_n_5\,
O => \add_temp_14__278_carry__2_i_4_n_0\
);
\add_temp_14__278_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__2_i_1_n_0\,
I1 => \add_temp_14__184_carry__2_n_5\,
I2 => \add_temp_14__230_carry__2_n_5\,
I3 => \add_temp_14__138_carry__2_n_5\,
I4 => \add_temp_14__92_carry__2_n_5\,
I5 => \add_temp_14__278_carry__2_i_10_n_0\,
O => \add_temp_14__278_carry__2_i_5_n_0\
);
\add_temp_14__278_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__2_i_2_n_0\,
I1 => \add_temp_14__184_carry__2_n_6\,
I2 => \add_temp_14__230_carry__2_n_6\,
I3 => \add_temp_14__138_carry__2_n_6\,
I4 => \add_temp_14__92_carry__2_n_6\,
I5 => \add_temp_14__278_carry__2_i_8_n_0\,
O => \add_temp_14__278_carry__2_i_6_n_0\
);
\add_temp_14__278_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__2_i_3_n_0\,
I1 => \add_temp_14__278_carry__2_i_9_n_0\,
I2 => \add_temp_14__92_carry__2_n_7\,
I3 => \add_temp_14__230_carry__1_n_4\,
I4 => \add_temp_14__184_carry__1_n_4\,
I5 => \add_temp_14__138_carry__1_n_4\,
O => \add_temp_14__278_carry__2_i_7_n_0\
);
\add_temp_14__278_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__2_n_7\,
I1 => \add_temp_14__138_carry__2_n_7\,
I2 => \add_temp_14__230_carry__2_n_7\,
O => \add_temp_14__278_carry__2_i_8_n_0\
);
\add_temp_14__278_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__2_n_7\,
I1 => \add_temp_14__230_carry__2_n_7\,
I2 => \add_temp_14__184_carry__2_n_7\,
O => \add_temp_14__278_carry__2_i_9_n_0\
);
\add_temp_14__278_carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry_n_5\,
I1 => \add_temp_14__230_carry_n_5\,
I2 => \add_temp_14__184_carry_n_5\,
I3 => \add_temp_14__278_carry_i_8_n_0\,
I4 => \add_temp_14__92_carry_n_5\,
O => \add_temp_14__278_carry_i_1_n_0\
);
\add_temp_14__278_carry_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry_n_5\,
I1 => \add_temp_14__230_carry_n_5\,
I2 => \add_temp_14__184_carry_n_5\,
O => \add_temp_14__278_carry_i_10_n_0\
);
\add_temp_14__278_carry_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \add_temp_14__278_carry_i_8_n_0\,
I1 => \add_temp_14__92_carry_n_5\,
I2 => \add_temp_14__138_carry_n_5\,
I3 => \add_temp_14__230_carry_n_5\,
I4 => \add_temp_14__184_carry_n_5\,
O => \add_temp_14__278_carry_i_2_n_0\
);
\add_temp_14__278_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry_n_6\,
I1 => \add_temp_14__230_carry_n_6\,
I2 => \add_temp_14__138_carry_n_6\,
I3 => \add_temp_14__92_carry_n_6\,
O => \add_temp_14__278_carry_i_3_n_0\
);
\add_temp_14__278_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry_i_1_n_0\,
I1 => \add_temp_14__184_carry_n_4\,
I2 => \add_temp_14__230_carry_n_4\,
I3 => \add_temp_14__138_carry_n_4\,
I4 => \add_temp_14__92_carry_n_4\,
I5 => \add_temp_14__278_carry_i_9_n_0\,
O => \add_temp_14__278_carry_i_4_n_0\
);
\add_temp_14__278_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6999999699969666"
)
port map (
I0 => \add_temp_14__278_carry_i_10_n_0\,
I1 => \add_temp_14__92_carry_n_5\,
I2 => \add_temp_14__138_carry_n_6\,
I3 => \add_temp_14__230_carry_n_6\,
I4 => \add_temp_14__184_carry_n_6\,
I5 => \add_temp_14__92_carry_n_6\,
O => \add_temp_14__278_carry_i_5_n_0\
);
\add_temp_14__278_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"566A"
)
port map (
I0 => \add_temp_14__278_carry_i_3_n_0\,
I1 => \add_temp_14__230_carry_n_7\,
I2 => \add_temp_14__184_carry_n_7\,
I3 => \add_temp_14__138_carry_n_7\,
O => \add_temp_14__278_carry_i_6_n_0\
);
\add_temp_14__278_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry_n_7\,
I1 => \add_temp_14__230_carry_n_7\,
I2 => \add_temp_14__138_carry_n_7\,
I3 => \add_temp_14__92_carry_n_7\,
O => \add_temp_14__278_carry_i_7_n_0\
);
\add_temp_14__278_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__138_carry_n_6\,
I1 => \add_temp_14__230_carry_n_6\,
I2 => \add_temp_14__184_carry_n_6\,
O => \add_temp_14__278_carry_i_8_n_0\
);
\add_temp_14__278_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry_n_5\,
I1 => \add_temp_14__138_carry_n_5\,
I2 => \add_temp_14__230_carry_n_5\,
O => \add_temp_14__278_carry_i_9_n_0\
);
\add_temp_14__46_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__46_carry_n_0\,
CO(2) => \add_temp_14__46_carry_n_1\,
CO(1) => \add_temp_14__46_carry_n_2\,
CO(0) => \add_temp_14__46_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__46_carry_i_1_n_0\,
DI(2) => \add_temp_14__46_carry_i_2_n_0\,
DI(1) => \add_temp_14__46_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__46_carry_n_4\,
O(2) => \add_temp_14__46_carry_n_5\,
O(1) => \add_temp_14__46_carry_n_6\,
O(0) => \add_temp_14__46_carry_n_7\,
S(3) => \add_temp_14__46_carry_i_4_n_0\,
S(2) => \add_temp_14__46_carry_i_5_n_0\,
S(1) => \add_temp_14__46_carry_i_6_n_0\,
S(0) => \add_temp_14__46_carry_i_7_n_0\
);
\add_temp_14__46_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__46_carry_n_0\,
CO(3) => \add_temp_14__46_carry__0_n_0\,
CO(2) => \add_temp_14__46_carry__0_n_1\,
CO(1) => \add_temp_14__46_carry__0_n_2\,
CO(0) => \add_temp_14__46_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__46_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__46_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__46_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__46_carry__0_i_4_n_0\,
O(3) => \add_temp_14__46_carry__0_n_4\,
O(2) => \add_temp_14__46_carry__0_n_5\,
O(1) => \add_temp_14__46_carry__0_n_6\,
O(0) => \add_temp_14__46_carry__0_n_7\,
S(3) => \add_temp_14__46_carry__0_i_5_n_0\,
S(2) => \add_temp_14__46_carry__0_i_6_n_0\,
S(1) => \add_temp_14__46_carry__0_i_7_n_0\,
S(0) => \add_temp_14__46_carry__0_i_8_n_0\
);
\add_temp_14__46_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(6),
I1 => RESIZE40(6),
I2 => RESIZE36(6),
O => \add_temp_14__46_carry__0_i_1_n_0\
);
\add_temp_14__46_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(5),
I1 => RESIZE40(5),
I2 => RESIZE36(5),
O => \add_temp_14__46_carry__0_i_2_n_0\
);
\add_temp_14__46_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(4),
I1 => RESIZE40(4),
I2 => RESIZE36(4),
O => \add_temp_14__46_carry__0_i_3_n_0\
);
\add_temp_14__46_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(3),
I1 => RESIZE40(3),
I2 => RESIZE36(3),
O => \add_temp_14__46_carry__0_i_4_n_0\
);
\add_temp_14__46_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(7),
I1 => RESIZE40(7),
I2 => RESIZE36(7),
I3 => \add_temp_14__46_carry__0_i_1_n_0\,
O => \add_temp_14__46_carry__0_i_5_n_0\
);
\add_temp_14__46_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(6),
I1 => RESIZE40(6),
I2 => RESIZE36(6),
I3 => \add_temp_14__46_carry__0_i_2_n_0\,
O => \add_temp_14__46_carry__0_i_6_n_0\
);
\add_temp_14__46_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(5),
I1 => RESIZE40(5),
I2 => RESIZE36(5),
I3 => \add_temp_14__46_carry__0_i_3_n_0\,
O => \add_temp_14__46_carry__0_i_7_n_0\
);
\add_temp_14__46_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(4),
I1 => RESIZE40(4),
I2 => RESIZE36(4),
I3 => \add_temp_14__46_carry__0_i_4_n_0\,
O => \add_temp_14__46_carry__0_i_8_n_0\
);
\add_temp_14__46_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__46_carry__0_n_0\,
CO(3) => \add_temp_14__46_carry__1_n_0\,
CO(2) => \add_temp_14__46_carry__1_n_1\,
CO(1) => \add_temp_14__46_carry__1_n_2\,
CO(0) => \add_temp_14__46_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__46_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__46_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__46_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__46_carry__1_i_4_n_0\,
O(3) => \add_temp_14__46_carry__1_n_4\,
O(2) => \add_temp_14__46_carry__1_n_5\,
O(1) => \add_temp_14__46_carry__1_n_6\,
O(0) => \add_temp_14__46_carry__1_n_7\,
S(3) => \add_temp_14__46_carry__1_i_5_n_0\,
S(2) => \add_temp_14__46_carry__1_i_6_n_0\,
S(1) => \add_temp_14__46_carry__1_i_7_n_0\,
S(0) => \add_temp_14__46_carry__1_i_8_n_0\
);
\add_temp_14__46_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE40(10),
I1 => RESIZE36(10),
I2 => RESIZE38(10),
O => \add_temp_14__46_carry__1_i_1_n_0\
);
\add_temp_14__46_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(9),
I1 => RESIZE40(9),
I2 => RESIZE36(9),
O => \add_temp_14__46_carry__1_i_2_n_0\
);
\add_temp_14__46_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(8),
I1 => RESIZE40(8),
I2 => RESIZE36(8),
O => \add_temp_14__46_carry__1_i_3_n_0\
);
\add_temp_14__46_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(7),
I1 => RESIZE40(7),
I2 => RESIZE36(7),
O => \add_temp_14__46_carry__1_i_4_n_0\
);
\add_temp_14__46_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE36(11),
I1 => RESIZE38(11),
I2 => RESIZE40(11),
I3 => \add_temp_14__46_carry__1_i_1_n_0\,
O => \add_temp_14__46_carry__1_i_5_n_0\
);
\add_temp_14__46_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE40(10),
I1 => RESIZE36(10),
I2 => RESIZE38(10),
I3 => \add_temp_14__46_carry__1_i_2_n_0\,
O => \add_temp_14__46_carry__1_i_6_n_0\
);
\add_temp_14__46_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(9),
I1 => RESIZE40(9),
I2 => RESIZE36(9),
I3 => \add_temp_14__46_carry__1_i_3_n_0\,
O => \add_temp_14__46_carry__1_i_7_n_0\
);
\add_temp_14__46_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(8),
I1 => RESIZE40(8),
I2 => RESIZE36(8),
I3 => \add_temp_14__46_carry__1_i_4_n_0\,
O => \add_temp_14__46_carry__1_i_8_n_0\
);
\add_temp_14__46_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__46_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__46_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__46_carry__2_n_1\,
CO(1) => \add_temp_14__46_carry__2_n_2\,
CO(0) => \add_temp_14__46_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__46_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__46_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__46_carry__2_i_3_n_0\,
O(3) => \add_temp_14__46_carry__2_n_4\,
O(2) => \add_temp_14__46_carry__2_n_5\,
O(1) => \add_temp_14__46_carry__2_n_6\,
O(0) => \add_temp_14__46_carry__2_n_7\,
S(3) => \add_temp_14__46_carry__2_i_4_n_0\,
S(2) => \add_temp_14__46_carry__2_i_5_n_0\,
S(1) => \add_temp_14__46_carry__2_i_6_n_0\,
S(0) => \add_temp_14__46_carry__2_i_7_n_0\
);
\add_temp_14__46_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE36(13),
I1 => RESIZE38(13),
I2 => RESIZE40(13),
O => \add_temp_14__46_carry__2_i_1_n_0\
);
\add_temp_14__46_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE36(12),
I1 => RESIZE38(12),
I2 => RESIZE40(12),
O => \add_temp_14__46_carry__2_i_2_n_0\
);
\add_temp_14__46_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE36(11),
I1 => RESIZE38(11),
I2 => RESIZE40(11),
O => \add_temp_14__46_carry__2_i_3_n_0\
);
\add_temp_14__46_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE40(14),
I1 => RESIZE38(14),
I2 => RESIZE36(14),
I3 => RESIZE38(15),
I4 => RESIZE36(15),
I5 => RESIZE40(15),
O => \add_temp_14__46_carry__2_i_4_n_0\
);
\add_temp_14__46_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__46_carry__2_i_1_n_0\,
I1 => RESIZE38(14),
I2 => RESIZE36(14),
I3 => RESIZE40(14),
O => \add_temp_14__46_carry__2_i_5_n_0\
);
\add_temp_14__46_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE36(13),
I1 => RESIZE38(13),
I2 => RESIZE40(13),
I3 => \add_temp_14__46_carry__2_i_2_n_0\,
O => \add_temp_14__46_carry__2_i_6_n_0\
);
\add_temp_14__46_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE36(12),
I1 => RESIZE38(12),
I2 => RESIZE40(12),
I3 => \add_temp_14__46_carry__2_i_3_n_0\,
O => \add_temp_14__46_carry__2_i_7_n_0\
);
\add_temp_14__46_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(2),
I1 => RESIZE40(2),
I2 => RESIZE36(2),
O => \add_temp_14__46_carry_i_1_n_0\
);
\add_temp_14__46_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(1),
I1 => RESIZE40(1),
I2 => RESIZE36(1),
O => \add_temp_14__46_carry_i_2_n_0\
);
\add_temp_14__46_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(0),
I1 => RESIZE40(0),
I2 => RESIZE36(0),
O => \add_temp_14__46_carry_i_3_n_0\
);
\add_temp_14__46_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(3),
I1 => RESIZE40(3),
I2 => RESIZE36(3),
I3 => \add_temp_14__46_carry_i_1_n_0\,
O => \add_temp_14__46_carry_i_4_n_0\
);
\add_temp_14__46_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(2),
I1 => RESIZE40(2),
I2 => RESIZE36(2),
I3 => \add_temp_14__46_carry_i_2_n_0\,
O => \add_temp_14__46_carry_i_5_n_0\
);
\add_temp_14__46_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(1),
I1 => RESIZE40(1),
I2 => RESIZE36(1),
I3 => \add_temp_14__46_carry_i_3_n_0\,
O => \add_temp_14__46_carry_i_6_n_0\
);
\add_temp_14__46_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE38(0),
I1 => RESIZE40(0),
I2 => RESIZE36(0),
O => \add_temp_14__46_carry_i_7_n_0\
);
\add_temp_14__92_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__92_carry_n_0\,
CO(2) => \add_temp_14__92_carry_n_1\,
CO(1) => \add_temp_14__92_carry_n_2\,
CO(0) => \add_temp_14__92_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__92_carry_i_1_n_0\,
DI(2) => \add_temp_14__92_carry_i_2_n_0\,
DI(1) => \add_temp_14__92_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__92_carry_n_4\,
O(2) => \add_temp_14__92_carry_n_5\,
O(1) => \add_temp_14__92_carry_n_6\,
O(0) => \add_temp_14__92_carry_n_7\,
S(3) => \add_temp_14__92_carry_i_4_n_0\,
S(2) => \add_temp_14__92_carry_i_5_n_0\,
S(1) => \add_temp_14__92_carry_i_6_n_0\,
S(0) => \add_temp_14__92_carry_i_7_n_0\
);
\add_temp_14__92_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__92_carry_n_0\,
CO(3) => \add_temp_14__92_carry__0_n_0\,
CO(2) => \add_temp_14__92_carry__0_n_1\,
CO(1) => \add_temp_14__92_carry__0_n_2\,
CO(0) => \add_temp_14__92_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__92_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__92_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__92_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__92_carry__0_i_4_n_0\,
O(3) => \add_temp_14__92_carry__0_n_4\,
O(2) => \add_temp_14__92_carry__0_n_5\,
O(1) => \add_temp_14__92_carry__0_n_6\,
O(0) => \add_temp_14__92_carry__0_n_7\,
S(3) => \add_temp_14__92_carry__0_i_5_n_0\,
S(2) => \add_temp_14__92_carry__0_i_6_n_0\,
S(1) => \add_temp_14__92_carry__0_i_7_n_0\,
S(0) => \add_temp_14__92_carry__0_i_8_n_0\
);
\add_temp_14__92_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(6),
I1 => RESIZE34(6),
I2 => RESIZE30(6),
O => \add_temp_14__92_carry__0_i_1_n_0\
);
\add_temp_14__92_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(5),
I1 => RESIZE34(5),
I2 => RESIZE30(5),
O => \add_temp_14__92_carry__0_i_2_n_0\
);
\add_temp_14__92_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(4),
I1 => RESIZE34(4),
I2 => RESIZE30(4),
O => \add_temp_14__92_carry__0_i_3_n_0\
);
\add_temp_14__92_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(3),
I1 => RESIZE34(3),
I2 => RESIZE30(3),
O => \add_temp_14__92_carry__0_i_4_n_0\
);
\add_temp_14__92_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE34(7),
I1 => RESIZE30(7),
I2 => RESIZE32(7),
I3 => \add_temp_14__92_carry__0_i_1_n_0\,
O => \add_temp_14__92_carry__0_i_5_n_0\
);
\add_temp_14__92_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(6),
I1 => RESIZE34(6),
I2 => RESIZE30(6),
I3 => \add_temp_14__92_carry__0_i_2_n_0\,
O => \add_temp_14__92_carry__0_i_6_n_0\
);
\add_temp_14__92_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(5),
I1 => RESIZE34(5),
I2 => RESIZE30(5),
I3 => \add_temp_14__92_carry__0_i_3_n_0\,
O => \add_temp_14__92_carry__0_i_7_n_0\
);
\add_temp_14__92_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(4),
I1 => RESIZE34(4),
I2 => RESIZE30(4),
I3 => \add_temp_14__92_carry__0_i_4_n_0\,
O => \add_temp_14__92_carry__0_i_8_n_0\
);
\add_temp_14__92_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__92_carry__0_n_0\,
CO(3) => \add_temp_14__92_carry__1_n_0\,
CO(2) => \add_temp_14__92_carry__1_n_1\,
CO(1) => \add_temp_14__92_carry__1_n_2\,
CO(0) => \add_temp_14__92_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__92_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__92_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__92_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__92_carry__1_i_4_n_0\,
O(3) => \add_temp_14__92_carry__1_n_4\,
O(2) => \add_temp_14__92_carry__1_n_5\,
O(1) => \add_temp_14__92_carry__1_n_6\,
O(0) => \add_temp_14__92_carry__1_n_7\,
S(3) => \add_temp_14__92_carry__1_i_5_n_0\,
S(2) => \add_temp_14__92_carry__1_i_6_n_0\,
S(1) => \add_temp_14__92_carry__1_i_7_n_0\,
S(0) => \add_temp_14__92_carry__1_i_8_n_0\
);
\add_temp_14__92_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(10),
I1 => RESIZE32(10),
I2 => RESIZE34(10),
O => \add_temp_14__92_carry__1_i_1_n_0\
);
\add_temp_14__92_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(9),
I1 => RESIZE32(9),
I2 => RESIZE34(9),
O => \add_temp_14__92_carry__1_i_2_n_0\
);
\add_temp_14__92_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(8),
I1 => RESIZE32(8),
I2 => RESIZE34(8),
O => \add_temp_14__92_carry__1_i_3_n_0\
);
\add_temp_14__92_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE34(7),
I1 => RESIZE30(7),
I2 => RESIZE32(7),
O => \add_temp_14__92_carry__1_i_4_n_0\
);
\add_temp_14__92_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(11),
I1 => RESIZE32(11),
I2 => RESIZE34(11),
I3 => \add_temp_14__92_carry__1_i_1_n_0\,
O => \add_temp_14__92_carry__1_i_5_n_0\
);
\add_temp_14__92_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(10),
I1 => RESIZE32(10),
I2 => RESIZE34(10),
I3 => \add_temp_14__92_carry__1_i_2_n_0\,
O => \add_temp_14__92_carry__1_i_6_n_0\
);
\add_temp_14__92_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(9),
I1 => RESIZE32(9),
I2 => RESIZE34(9),
I3 => \add_temp_14__92_carry__1_i_3_n_0\,
O => \add_temp_14__92_carry__1_i_7_n_0\
);
\add_temp_14__92_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(8),
I1 => RESIZE32(8),
I2 => RESIZE34(8),
I3 => \add_temp_14__92_carry__1_i_4_n_0\,
O => \add_temp_14__92_carry__1_i_8_n_0\
);
\add_temp_14__92_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__92_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__92_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__92_carry__2_n_1\,
CO(1) => \add_temp_14__92_carry__2_n_2\,
CO(0) => \add_temp_14__92_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__92_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__92_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__92_carry__2_i_3_n_0\,
O(3) => \add_temp_14__92_carry__2_n_4\,
O(2) => \add_temp_14__92_carry__2_n_5\,
O(1) => \add_temp_14__92_carry__2_n_6\,
O(0) => \add_temp_14__92_carry__2_n_7\,
S(3) => \add_temp_14__92_carry__2_i_4_n_0\,
S(2) => \add_temp_14__92_carry__2_i_5_n_0\,
S(1) => \add_temp_14__92_carry__2_i_6_n_0\,
S(0) => \add_temp_14__92_carry__2_i_7_n_0\
);
\add_temp_14__92_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(13),
I1 => RESIZE32(13),
I2 => RESIZE34(13),
O => \add_temp_14__92_carry__2_i_1_n_0\
);
\add_temp_14__92_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(12),
I1 => RESIZE32(12),
I2 => RESIZE34(12),
O => \add_temp_14__92_carry__2_i_2_n_0\
);
\add_temp_14__92_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(11),
I1 => RESIZE32(11),
I2 => RESIZE34(11),
O => \add_temp_14__92_carry__2_i_3_n_0\
);
\add_temp_14__92_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE34(14),
I1 => RESIZE32(14),
I2 => RESIZE30(14),
I3 => RESIZE32(15),
I4 => RESIZE30(15),
I5 => RESIZE34(15),
O => \add_temp_14__92_carry__2_i_4_n_0\
);
\add_temp_14__92_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__92_carry__2_i_1_n_0\,
I1 => RESIZE32(14),
I2 => RESIZE30(14),
I3 => RESIZE34(14),
O => \add_temp_14__92_carry__2_i_5_n_0\
);
\add_temp_14__92_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(13),
I1 => RESIZE32(13),
I2 => RESIZE34(13),
I3 => \add_temp_14__92_carry__2_i_2_n_0\,
O => \add_temp_14__92_carry__2_i_6_n_0\
);
\add_temp_14__92_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(12),
I1 => RESIZE32(12),
I2 => RESIZE34(12),
I3 => \add_temp_14__92_carry__2_i_3_n_0\,
O => \add_temp_14__92_carry__2_i_7_n_0\
);
\add_temp_14__92_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(2),
I1 => RESIZE34(2),
I2 => RESIZE30(2),
O => \add_temp_14__92_carry_i_1_n_0\
);
\add_temp_14__92_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(1),
I1 => RESIZE34(1),
I2 => RESIZE30(1),
O => \add_temp_14__92_carry_i_2_n_0\
);
\add_temp_14__92_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(0),
I1 => RESIZE34(0),
I2 => RESIZE30(0),
O => \add_temp_14__92_carry_i_3_n_0\
);
\add_temp_14__92_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(3),
I1 => RESIZE34(3),
I2 => RESIZE30(3),
I3 => \add_temp_14__92_carry_i_1_n_0\,
O => \add_temp_14__92_carry_i_4_n_0\
);
\add_temp_14__92_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(2),
I1 => RESIZE34(2),
I2 => RESIZE30(2),
I3 => \add_temp_14__92_carry_i_2_n_0\,
O => \add_temp_14__92_carry_i_5_n_0\
);
\add_temp_14__92_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(1),
I1 => RESIZE34(1),
I2 => RESIZE30(1),
I3 => \add_temp_14__92_carry_i_3_n_0\,
O => \add_temp_14__92_carry_i_6_n_0\
);
\add_temp_14__92_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE32(0),
I1 => RESIZE34(0),
I2 => RESIZE30(0),
O => \add_temp_14__92_carry_i_7_n_0\
);
\data_pipeline_tmp_reg[0][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(0),
Q => \data_pipeline_tmp_reg[0]\(0)
);
\data_pipeline_tmp_reg[0][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(10),
Q => \data_pipeline_tmp_reg[0]\(10)
);
\data_pipeline_tmp_reg[0][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(11),
Q => \data_pipeline_tmp_reg[0]\(11)
);
\data_pipeline_tmp_reg[0][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(12),
Q => \data_pipeline_tmp_reg[0]\(12)
);
\data_pipeline_tmp_reg[0][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(13),
Q => \data_pipeline_tmp_reg[0]\(13)
);
\data_pipeline_tmp_reg[0][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(14),
Q => \data_pipeline_tmp_reg[0]\(14)
);
\data_pipeline_tmp_reg[0][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(15),
Q => \data_pipeline_tmp_reg[0]\(15)
);
\data_pipeline_tmp_reg[0][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(1),
Q => \data_pipeline_tmp_reg[0]\(1)
);
\data_pipeline_tmp_reg[0][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(2),
Q => \data_pipeline_tmp_reg[0]\(2)
);
\data_pipeline_tmp_reg[0][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(3),
Q => \data_pipeline_tmp_reg[0]\(3)
);
\data_pipeline_tmp_reg[0][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(4),
Q => \data_pipeline_tmp_reg[0]\(4)
);
\data_pipeline_tmp_reg[0][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(5),
Q => \data_pipeline_tmp_reg[0]\(5)
);
\data_pipeline_tmp_reg[0][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(6),
Q => \data_pipeline_tmp_reg[0]\(6)
);
\data_pipeline_tmp_reg[0][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(7),
Q => \data_pipeline_tmp_reg[0]\(7)
);
\data_pipeline_tmp_reg[0][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(8),
Q => \data_pipeline_tmp_reg[0]\(8)
);
\data_pipeline_tmp_reg[0][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(9),
Q => \data_pipeline_tmp_reg[0]\(9)
);
\data_pipeline_tmp_reg[10][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(0),
Q => \data_pipeline_tmp_reg[10]\(0)
);
\data_pipeline_tmp_reg[10][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(10),
Q => \data_pipeline_tmp_reg[10]\(10)
);
\data_pipeline_tmp_reg[10][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(11),
Q => \data_pipeline_tmp_reg[10]\(11)
);
\data_pipeline_tmp_reg[10][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(12),
Q => \data_pipeline_tmp_reg[10]\(12)
);
\data_pipeline_tmp_reg[10][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(13),
Q => \data_pipeline_tmp_reg[10]\(13)
);
\data_pipeline_tmp_reg[10][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(14),
Q => \data_pipeline_tmp_reg[10]\(14)
);
\data_pipeline_tmp_reg[10][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(15),
Q => \data_pipeline_tmp_reg[10]\(15)
);
\data_pipeline_tmp_reg[10][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(1),
Q => \data_pipeline_tmp_reg[10]\(1)
);
\data_pipeline_tmp_reg[10][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(2),
Q => \data_pipeline_tmp_reg[10]\(2)
);
\data_pipeline_tmp_reg[10][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(3),
Q => \data_pipeline_tmp_reg[10]\(3)
);
\data_pipeline_tmp_reg[10][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(4),
Q => \data_pipeline_tmp_reg[10]\(4)
);
\data_pipeline_tmp_reg[10][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(5),
Q => \data_pipeline_tmp_reg[10]\(5)
);
\data_pipeline_tmp_reg[10][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(6),
Q => \data_pipeline_tmp_reg[10]\(6)
);
\data_pipeline_tmp_reg[10][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(7),
Q => \data_pipeline_tmp_reg[10]\(7)
);
\data_pipeline_tmp_reg[10][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(8),
Q => \data_pipeline_tmp_reg[10]\(8)
);
\data_pipeline_tmp_reg[10][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(9),
Q => \data_pipeline_tmp_reg[10]\(9)
);
\data_pipeline_tmp_reg[11][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(0),
Q => \data_pipeline_tmp_reg[11]\(0)
);
\data_pipeline_tmp_reg[11][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(10),
Q => \data_pipeline_tmp_reg[11]\(10)
);
\data_pipeline_tmp_reg[11][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(11),
Q => \data_pipeline_tmp_reg[11]\(11)
);
\data_pipeline_tmp_reg[11][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(12),
Q => \data_pipeline_tmp_reg[11]\(12)
);
\data_pipeline_tmp_reg[11][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(13),
Q => \data_pipeline_tmp_reg[11]\(13)
);
\data_pipeline_tmp_reg[11][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(14),
Q => \data_pipeline_tmp_reg[11]\(14)
);
\data_pipeline_tmp_reg[11][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(15),
Q => \data_pipeline_tmp_reg[11]\(15)
);
\data_pipeline_tmp_reg[11][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(1),
Q => \data_pipeline_tmp_reg[11]\(1)
);
\data_pipeline_tmp_reg[11][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(2),
Q => \data_pipeline_tmp_reg[11]\(2)
);
\data_pipeline_tmp_reg[11][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(3),
Q => \data_pipeline_tmp_reg[11]\(3)
);
\data_pipeline_tmp_reg[11][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(4),
Q => \data_pipeline_tmp_reg[11]\(4)
);
\data_pipeline_tmp_reg[11][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(5),
Q => \data_pipeline_tmp_reg[11]\(5)
);
\data_pipeline_tmp_reg[11][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(6),
Q => \data_pipeline_tmp_reg[11]\(6)
);
\data_pipeline_tmp_reg[11][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(7),
Q => \data_pipeline_tmp_reg[11]\(7)
);
\data_pipeline_tmp_reg[11][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(8),
Q => \data_pipeline_tmp_reg[11]\(8)
);
\data_pipeline_tmp_reg[11][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(9),
Q => \data_pipeline_tmp_reg[11]\(9)
);
\data_pipeline_tmp_reg[12][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(0),
Q => \data_pipeline_tmp_reg[12]\(0)
);
\data_pipeline_tmp_reg[12][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(10),
Q => \data_pipeline_tmp_reg[12]\(10)
);
\data_pipeline_tmp_reg[12][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(11),
Q => \data_pipeline_tmp_reg[12]\(11)
);
\data_pipeline_tmp_reg[12][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(12),
Q => \data_pipeline_tmp_reg[12]\(12)
);
\data_pipeline_tmp_reg[12][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(13),
Q => \data_pipeline_tmp_reg[12]\(13)
);
\data_pipeline_tmp_reg[12][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(14),
Q => \data_pipeline_tmp_reg[12]\(14)
);
\data_pipeline_tmp_reg[12][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(15),
Q => \data_pipeline_tmp_reg[12]\(15)
);
\data_pipeline_tmp_reg[12][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(1),
Q => \data_pipeline_tmp_reg[12]\(1)
);
\data_pipeline_tmp_reg[12][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(2),
Q => \data_pipeline_tmp_reg[12]\(2)
);
\data_pipeline_tmp_reg[12][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(3),
Q => \data_pipeline_tmp_reg[12]\(3)
);
\data_pipeline_tmp_reg[12][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(4),
Q => \data_pipeline_tmp_reg[12]\(4)
);
\data_pipeline_tmp_reg[12][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(5),
Q => \data_pipeline_tmp_reg[12]\(5)
);
\data_pipeline_tmp_reg[12][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(6),
Q => \data_pipeline_tmp_reg[12]\(6)
);
\data_pipeline_tmp_reg[12][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(7),
Q => \data_pipeline_tmp_reg[12]\(7)
);
\data_pipeline_tmp_reg[12][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(8),
Q => \data_pipeline_tmp_reg[12]\(8)
);
\data_pipeline_tmp_reg[12][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(9),
Q => \data_pipeline_tmp_reg[12]\(9)
);
\data_pipeline_tmp_reg[13][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(0),
Q => \data_pipeline_tmp_reg[13]\(0)
);
\data_pipeline_tmp_reg[13][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(10),
Q => \data_pipeline_tmp_reg[13]\(10)
);
\data_pipeline_tmp_reg[13][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(11),
Q => \data_pipeline_tmp_reg[13]\(11)
);
\data_pipeline_tmp_reg[13][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(12),
Q => \data_pipeline_tmp_reg[13]\(12)
);
\data_pipeline_tmp_reg[13][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(13),
Q => \data_pipeline_tmp_reg[13]\(13)
);
\data_pipeline_tmp_reg[13][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(14),
Q => \data_pipeline_tmp_reg[13]\(14)
);
\data_pipeline_tmp_reg[13][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(15),
Q => \data_pipeline_tmp_reg[13]\(15)
);
\data_pipeline_tmp_reg[13][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(1),
Q => \data_pipeline_tmp_reg[13]\(1)
);
\data_pipeline_tmp_reg[13][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(2),
Q => \data_pipeline_tmp_reg[13]\(2)
);
\data_pipeline_tmp_reg[13][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(3),
Q => \data_pipeline_tmp_reg[13]\(3)
);
\data_pipeline_tmp_reg[13][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(4),
Q => \data_pipeline_tmp_reg[13]\(4)
);
\data_pipeline_tmp_reg[13][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(5),
Q => \data_pipeline_tmp_reg[13]\(5)
);
\data_pipeline_tmp_reg[13][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(6),
Q => \data_pipeline_tmp_reg[13]\(6)
);
\data_pipeline_tmp_reg[13][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(7),
Q => \data_pipeline_tmp_reg[13]\(7)
);
\data_pipeline_tmp_reg[13][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(8),
Q => \data_pipeline_tmp_reg[13]\(8)
);
\data_pipeline_tmp_reg[13][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(9),
Q => \data_pipeline_tmp_reg[13]\(9)
);
\data_pipeline_tmp_reg[14][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(0),
Q => \data_pipeline_tmp_reg[14]\(0)
);
\data_pipeline_tmp_reg[14][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(10),
Q => \data_pipeline_tmp_reg[14]\(10)
);
\data_pipeline_tmp_reg[14][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(11),
Q => \data_pipeline_tmp_reg[14]\(11)
);
\data_pipeline_tmp_reg[14][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(12),
Q => \data_pipeline_tmp_reg[14]\(12)
);
\data_pipeline_tmp_reg[14][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(13),
Q => \data_pipeline_tmp_reg[14]\(13)
);
\data_pipeline_tmp_reg[14][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(14),
Q => \data_pipeline_tmp_reg[14]\(14)
);
\data_pipeline_tmp_reg[14][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(15),
Q => \data_pipeline_tmp_reg[14]\(15)
);
\data_pipeline_tmp_reg[14][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(1),
Q => \data_pipeline_tmp_reg[14]\(1)
);
\data_pipeline_tmp_reg[14][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(2),
Q => \data_pipeline_tmp_reg[14]\(2)
);
\data_pipeline_tmp_reg[14][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(3),
Q => \data_pipeline_tmp_reg[14]\(3)
);
\data_pipeline_tmp_reg[14][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(4),
Q => \data_pipeline_tmp_reg[14]\(4)
);
\data_pipeline_tmp_reg[14][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(5),
Q => \data_pipeline_tmp_reg[14]\(5)
);
\data_pipeline_tmp_reg[14][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(6),
Q => \data_pipeline_tmp_reg[14]\(6)
);
\data_pipeline_tmp_reg[14][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(7),
Q => \data_pipeline_tmp_reg[14]\(7)
);
\data_pipeline_tmp_reg[14][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(8),
Q => \data_pipeline_tmp_reg[14]\(8)
);
\data_pipeline_tmp_reg[14][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(9),
Q => \data_pipeline_tmp_reg[14]\(9)
);
\data_pipeline_tmp_reg[1][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(0),
Q => \data_pipeline_tmp_reg[1]\(0)
);
\data_pipeline_tmp_reg[1][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(10),
Q => \data_pipeline_tmp_reg[1]\(10)
);
\data_pipeline_tmp_reg[1][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(11),
Q => \data_pipeline_tmp_reg[1]\(11)
);
\data_pipeline_tmp_reg[1][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(12),
Q => \data_pipeline_tmp_reg[1]\(12)
);
\data_pipeline_tmp_reg[1][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(13),
Q => \data_pipeline_tmp_reg[1]\(13)
);
\data_pipeline_tmp_reg[1][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(14),
Q => \data_pipeline_tmp_reg[1]\(14)
);
\data_pipeline_tmp_reg[1][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(15),
Q => \data_pipeline_tmp_reg[1]\(15)
);
\data_pipeline_tmp_reg[1][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(1),
Q => \data_pipeline_tmp_reg[1]\(1)
);
\data_pipeline_tmp_reg[1][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(2),
Q => \data_pipeline_tmp_reg[1]\(2)
);
\data_pipeline_tmp_reg[1][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(3),
Q => \data_pipeline_tmp_reg[1]\(3)
);
\data_pipeline_tmp_reg[1][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(4),
Q => \data_pipeline_tmp_reg[1]\(4)
);
\data_pipeline_tmp_reg[1][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(5),
Q => \data_pipeline_tmp_reg[1]\(5)
);
\data_pipeline_tmp_reg[1][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(6),
Q => \data_pipeline_tmp_reg[1]\(6)
);
\data_pipeline_tmp_reg[1][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(7),
Q => \data_pipeline_tmp_reg[1]\(7)
);
\data_pipeline_tmp_reg[1][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(8),
Q => \data_pipeline_tmp_reg[1]\(8)
);
\data_pipeline_tmp_reg[1][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(9),
Q => \data_pipeline_tmp_reg[1]\(9)
);
\data_pipeline_tmp_reg[2][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(0),
Q => \data_pipeline_tmp_reg[2]\(0)
);
\data_pipeline_tmp_reg[2][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(10),
Q => \data_pipeline_tmp_reg[2]\(10)
);
\data_pipeline_tmp_reg[2][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(11),
Q => \data_pipeline_tmp_reg[2]\(11)
);
\data_pipeline_tmp_reg[2][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(12),
Q => \data_pipeline_tmp_reg[2]\(12)
);
\data_pipeline_tmp_reg[2][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(13),
Q => \data_pipeline_tmp_reg[2]\(13)
);
\data_pipeline_tmp_reg[2][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(14),
Q => \data_pipeline_tmp_reg[2]\(14)
);
\data_pipeline_tmp_reg[2][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(15),
Q => \data_pipeline_tmp_reg[2]\(15)
);
\data_pipeline_tmp_reg[2][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(1),
Q => \data_pipeline_tmp_reg[2]\(1)
);
\data_pipeline_tmp_reg[2][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(2),
Q => \data_pipeline_tmp_reg[2]\(2)
);
\data_pipeline_tmp_reg[2][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(3),
Q => \data_pipeline_tmp_reg[2]\(3)
);
\data_pipeline_tmp_reg[2][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(4),
Q => \data_pipeline_tmp_reg[2]\(4)
);
\data_pipeline_tmp_reg[2][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(5),
Q => \data_pipeline_tmp_reg[2]\(5)
);
\data_pipeline_tmp_reg[2][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(6),
Q => \data_pipeline_tmp_reg[2]\(6)
);
\data_pipeline_tmp_reg[2][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(7),
Q => \data_pipeline_tmp_reg[2]\(7)
);
\data_pipeline_tmp_reg[2][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(8),
Q => \data_pipeline_tmp_reg[2]\(8)
);
\data_pipeline_tmp_reg[2][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(9),
Q => \data_pipeline_tmp_reg[2]\(9)
);
\data_pipeline_tmp_reg[3][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(0),
Q => \data_pipeline_tmp_reg[3]\(0)
);
\data_pipeline_tmp_reg[3][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(10),
Q => \data_pipeline_tmp_reg[3]\(10)
);
\data_pipeline_tmp_reg[3][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(11),
Q => \data_pipeline_tmp_reg[3]\(11)
);
\data_pipeline_tmp_reg[3][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(12),
Q => \data_pipeline_tmp_reg[3]\(12)
);
\data_pipeline_tmp_reg[3][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(13),
Q => \data_pipeline_tmp_reg[3]\(13)
);
\data_pipeline_tmp_reg[3][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(14),
Q => \data_pipeline_tmp_reg[3]\(14)
);
\data_pipeline_tmp_reg[3][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(15),
Q => \data_pipeline_tmp_reg[3]\(15)
);
\data_pipeline_tmp_reg[3][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(1),
Q => \data_pipeline_tmp_reg[3]\(1)
);
\data_pipeline_tmp_reg[3][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(2),
Q => \data_pipeline_tmp_reg[3]\(2)
);
\data_pipeline_tmp_reg[3][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(3),
Q => \data_pipeline_tmp_reg[3]\(3)
);
\data_pipeline_tmp_reg[3][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(4),
Q => \data_pipeline_tmp_reg[3]\(4)
);
\data_pipeline_tmp_reg[3][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(5),
Q => \data_pipeline_tmp_reg[3]\(5)
);
\data_pipeline_tmp_reg[3][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(6),
Q => \data_pipeline_tmp_reg[3]\(6)
);
\data_pipeline_tmp_reg[3][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(7),
Q => \data_pipeline_tmp_reg[3]\(7)
);
\data_pipeline_tmp_reg[3][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(8),
Q => \data_pipeline_tmp_reg[3]\(8)
);
\data_pipeline_tmp_reg[3][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(9),
Q => \data_pipeline_tmp_reg[3]\(9)
);
\data_pipeline_tmp_reg[4][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(0),
Q => \data_pipeline_tmp_reg[4]\(0)
);
\data_pipeline_tmp_reg[4][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(10),
Q => \data_pipeline_tmp_reg[4]\(10)
);
\data_pipeline_tmp_reg[4][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(11),
Q => \data_pipeline_tmp_reg[4]\(11)
);
\data_pipeline_tmp_reg[4][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(12),
Q => \data_pipeline_tmp_reg[4]\(12)
);
\data_pipeline_tmp_reg[4][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(13),
Q => \data_pipeline_tmp_reg[4]\(13)
);
\data_pipeline_tmp_reg[4][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(14),
Q => \data_pipeline_tmp_reg[4]\(14)
);
\data_pipeline_tmp_reg[4][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(15),
Q => \data_pipeline_tmp_reg[4]\(15)
);
\data_pipeline_tmp_reg[4][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(1),
Q => \data_pipeline_tmp_reg[4]\(1)
);
\data_pipeline_tmp_reg[4][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(2),
Q => \data_pipeline_tmp_reg[4]\(2)
);
\data_pipeline_tmp_reg[4][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(3),
Q => \data_pipeline_tmp_reg[4]\(3)
);
\data_pipeline_tmp_reg[4][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(4),
Q => \data_pipeline_tmp_reg[4]\(4)
);
\data_pipeline_tmp_reg[4][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(5),
Q => \data_pipeline_tmp_reg[4]\(5)
);
\data_pipeline_tmp_reg[4][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(6),
Q => \data_pipeline_tmp_reg[4]\(6)
);
\data_pipeline_tmp_reg[4][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(7),
Q => \data_pipeline_tmp_reg[4]\(7)
);
\data_pipeline_tmp_reg[4][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(8),
Q => \data_pipeline_tmp_reg[4]\(8)
);
\data_pipeline_tmp_reg[4][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(9),
Q => \data_pipeline_tmp_reg[4]\(9)
);
\data_pipeline_tmp_reg[5][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(0),
Q => \data_pipeline_tmp_reg[5]\(0)
);
\data_pipeline_tmp_reg[5][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(10),
Q => \data_pipeline_tmp_reg[5]\(10)
);
\data_pipeline_tmp_reg[5][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(11),
Q => \data_pipeline_tmp_reg[5]\(11)
);
\data_pipeline_tmp_reg[5][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(12),
Q => \data_pipeline_tmp_reg[5]\(12)
);
\data_pipeline_tmp_reg[5][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(13),
Q => \data_pipeline_tmp_reg[5]\(13)
);
\data_pipeline_tmp_reg[5][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(14),
Q => \data_pipeline_tmp_reg[5]\(14)
);
\data_pipeline_tmp_reg[5][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(15),
Q => \data_pipeline_tmp_reg[5]\(15)
);
\data_pipeline_tmp_reg[5][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(1),
Q => \data_pipeline_tmp_reg[5]\(1)
);
\data_pipeline_tmp_reg[5][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(2),
Q => \data_pipeline_tmp_reg[5]\(2)
);
\data_pipeline_tmp_reg[5][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(3),
Q => \data_pipeline_tmp_reg[5]\(3)
);
\data_pipeline_tmp_reg[5][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(4),
Q => \data_pipeline_tmp_reg[5]\(4)
);
\data_pipeline_tmp_reg[5][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(5),
Q => \data_pipeline_tmp_reg[5]\(5)
);
\data_pipeline_tmp_reg[5][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(6),
Q => \data_pipeline_tmp_reg[5]\(6)
);
\data_pipeline_tmp_reg[5][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(7),
Q => \data_pipeline_tmp_reg[5]\(7)
);
\data_pipeline_tmp_reg[5][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(8),
Q => \data_pipeline_tmp_reg[5]\(8)
);
\data_pipeline_tmp_reg[5][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(9),
Q => \data_pipeline_tmp_reg[5]\(9)
);
\data_pipeline_tmp_reg[6][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(0),
Q => \data_pipeline_tmp_reg[6]\(0)
);
\data_pipeline_tmp_reg[6][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(10),
Q => \data_pipeline_tmp_reg[6]\(10)
);
\data_pipeline_tmp_reg[6][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(11),
Q => \data_pipeline_tmp_reg[6]\(11)
);
\data_pipeline_tmp_reg[6][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(12),
Q => \data_pipeline_tmp_reg[6]\(12)
);
\data_pipeline_tmp_reg[6][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(13),
Q => \data_pipeline_tmp_reg[6]\(13)
);
\data_pipeline_tmp_reg[6][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(14),
Q => \data_pipeline_tmp_reg[6]\(14)
);
\data_pipeline_tmp_reg[6][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(15),
Q => \data_pipeline_tmp_reg[6]\(15)
);
\data_pipeline_tmp_reg[6][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(1),
Q => \data_pipeline_tmp_reg[6]\(1)
);
\data_pipeline_tmp_reg[6][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(2),
Q => \data_pipeline_tmp_reg[6]\(2)
);
\data_pipeline_tmp_reg[6][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(3),
Q => \data_pipeline_tmp_reg[6]\(3)
);
\data_pipeline_tmp_reg[6][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(4),
Q => \data_pipeline_tmp_reg[6]\(4)
);
\data_pipeline_tmp_reg[6][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(5),
Q => \data_pipeline_tmp_reg[6]\(5)
);
\data_pipeline_tmp_reg[6][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(6),
Q => \data_pipeline_tmp_reg[6]\(6)
);
\data_pipeline_tmp_reg[6][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(7),
Q => \data_pipeline_tmp_reg[6]\(7)
);
\data_pipeline_tmp_reg[6][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(8),
Q => \data_pipeline_tmp_reg[6]\(8)
);
\data_pipeline_tmp_reg[6][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(9),
Q => \data_pipeline_tmp_reg[6]\(9)
);
\data_pipeline_tmp_reg[7][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(0),
Q => \data_pipeline_tmp_reg[7]\(0)
);
\data_pipeline_tmp_reg[7][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(10),
Q => \data_pipeline_tmp_reg[7]\(10)
);
\data_pipeline_tmp_reg[7][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(11),
Q => \data_pipeline_tmp_reg[7]\(11)
);
\data_pipeline_tmp_reg[7][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(12),
Q => \data_pipeline_tmp_reg[7]\(12)
);
\data_pipeline_tmp_reg[7][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(13),
Q => \data_pipeline_tmp_reg[7]\(13)
);
\data_pipeline_tmp_reg[7][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(14),
Q => \data_pipeline_tmp_reg[7]\(14)
);
\data_pipeline_tmp_reg[7][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(15),
Q => \data_pipeline_tmp_reg[7]\(15)
);
\data_pipeline_tmp_reg[7][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(1),
Q => \data_pipeline_tmp_reg[7]\(1)
);
\data_pipeline_tmp_reg[7][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(2),
Q => \data_pipeline_tmp_reg[7]\(2)
);
\data_pipeline_tmp_reg[7][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(3),
Q => \data_pipeline_tmp_reg[7]\(3)
);
\data_pipeline_tmp_reg[7][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(4),
Q => \data_pipeline_tmp_reg[7]\(4)
);
\data_pipeline_tmp_reg[7][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(5),
Q => \data_pipeline_tmp_reg[7]\(5)
);
\data_pipeline_tmp_reg[7][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(6),
Q => \data_pipeline_tmp_reg[7]\(6)
);
\data_pipeline_tmp_reg[7][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(7),
Q => \data_pipeline_tmp_reg[7]\(7)
);
\data_pipeline_tmp_reg[7][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(8),
Q => \data_pipeline_tmp_reg[7]\(8)
);
\data_pipeline_tmp_reg[7][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(9),
Q => \data_pipeline_tmp_reg[7]\(9)
);
\data_pipeline_tmp_reg[8][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(0),
Q => \data_pipeline_tmp_reg[8]\(0)
);
\data_pipeline_tmp_reg[8][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(10),
Q => \data_pipeline_tmp_reg[8]\(10)
);
\data_pipeline_tmp_reg[8][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(11),
Q => \data_pipeline_tmp_reg[8]\(11)
);
\data_pipeline_tmp_reg[8][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(12),
Q => \data_pipeline_tmp_reg[8]\(12)
);
\data_pipeline_tmp_reg[8][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(13),
Q => \data_pipeline_tmp_reg[8]\(13)
);
\data_pipeline_tmp_reg[8][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(14),
Q => \data_pipeline_tmp_reg[8]\(14)
);
\data_pipeline_tmp_reg[8][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(15),
Q => \data_pipeline_tmp_reg[8]\(15)
);
\data_pipeline_tmp_reg[8][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(1),
Q => \data_pipeline_tmp_reg[8]\(1)
);
\data_pipeline_tmp_reg[8][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(2),
Q => \data_pipeline_tmp_reg[8]\(2)
);
\data_pipeline_tmp_reg[8][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(3),
Q => \data_pipeline_tmp_reg[8]\(3)
);
\data_pipeline_tmp_reg[8][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(4),
Q => \data_pipeline_tmp_reg[8]\(4)
);
\data_pipeline_tmp_reg[8][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(5),
Q => \data_pipeline_tmp_reg[8]\(5)
);
\data_pipeline_tmp_reg[8][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(6),
Q => \data_pipeline_tmp_reg[8]\(6)
);
\data_pipeline_tmp_reg[8][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(7),
Q => \data_pipeline_tmp_reg[8]\(7)
);
\data_pipeline_tmp_reg[8][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(8),
Q => \data_pipeline_tmp_reg[8]\(8)
);
\data_pipeline_tmp_reg[8][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(9),
Q => \data_pipeline_tmp_reg[8]\(9)
);
\data_pipeline_tmp_reg[9][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(0),
Q => \data_pipeline_tmp_reg[9]\(0)
);
\data_pipeline_tmp_reg[9][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(10),
Q => \data_pipeline_tmp_reg[9]\(10)
);
\data_pipeline_tmp_reg[9][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(11),
Q => \data_pipeline_tmp_reg[9]\(11)
);
\data_pipeline_tmp_reg[9][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(12),
Q => \data_pipeline_tmp_reg[9]\(12)
);
\data_pipeline_tmp_reg[9][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(13),
Q => \data_pipeline_tmp_reg[9]\(13)
);
\data_pipeline_tmp_reg[9][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(14),
Q => \data_pipeline_tmp_reg[9]\(14)
);
\data_pipeline_tmp_reg[9][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(15),
Q => \data_pipeline_tmp_reg[9]\(15)
);
\data_pipeline_tmp_reg[9][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(1),
Q => \data_pipeline_tmp_reg[9]\(1)
);
\data_pipeline_tmp_reg[9][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(2),
Q => \data_pipeline_tmp_reg[9]\(2)
);
\data_pipeline_tmp_reg[9][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(3),
Q => \data_pipeline_tmp_reg[9]\(3)
);
\data_pipeline_tmp_reg[9][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(4),
Q => \data_pipeline_tmp_reg[9]\(4)
);
\data_pipeline_tmp_reg[9][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(5),
Q => \data_pipeline_tmp_reg[9]\(5)
);
\data_pipeline_tmp_reg[9][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(6),
Q => \data_pipeline_tmp_reg[9]\(6)
);
\data_pipeline_tmp_reg[9][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(7),
Q => \data_pipeline_tmp_reg[9]\(7)
);
\data_pipeline_tmp_reg[9][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(8),
Q => \data_pipeline_tmp_reg[9]\(8)
);
\data_pipeline_tmp_reg[9][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(9),
Q => \data_pipeline_tmp_reg[9]\(9)
);
mul_temp: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[0]_15\(15),
B(16) => \weight_reg[0]_15\(15),
B(15 downto 0) => \weight_reg[0]_15\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_n_74,
P(30) => mul_temp_n_75,
P(29) => mul_temp_n_76,
P(28) => mul_temp_n_77,
P(27) => mul_temp_n_78,
P(26) => mul_temp_n_79,
P(25) => mul_temp_n_80,
P(24) => mul_temp_n_81,
P(23) => mul_temp_n_82,
P(22) => mul_temp_n_83,
P(21) => mul_temp_n_84,
P(20) => mul_temp_n_85,
P(19) => mul_temp_n_86,
P(18) => mul_temp_n_87,
P(17) => mul_temp_n_88,
P(16) => mul_temp_n_89,
P(15) => mul_temp_n_90,
P(14) => \^mul_temp\(14),
P(13) => mul_temp_n_92,
P(12) => mul_temp_n_93,
P(11) => mul_temp_n_94,
P(10) => mul_temp_n_95,
P(9) => mul_temp_n_96,
P(8) => mul_temp_n_97,
P(7) => mul_temp_n_98,
P(6) => mul_temp_n_99,
P(5) => mul_temp_n_100,
P(4) => mul_temp_n_101,
P(3) => mul_temp_n_102,
P(2) => mul_temp_n_103,
P(1) => mul_temp_n_104,
P(0) => mul_temp_n_105,
PATTERNBDETECT => NLW_mul_temp_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_UNDERFLOW_UNCONNECTED
);
mul_temp_1: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_1_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[1]_0\(15),
B(16) => \weight_reg[1]_0\(15),
B(15 downto 0) => \weight_reg[1]_0\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_1_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_1_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_1_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_1_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_1_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_1_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_1_n_74,
P(30) => mul_temp_1_n_75,
P(29) => mul_temp_1_n_76,
P(28) => mul_temp_1_n_77,
P(27) => mul_temp_1_n_78,
P(26) => mul_temp_1_n_79,
P(25) => mul_temp_1_n_80,
P(24) => mul_temp_1_n_81,
P(23) => mul_temp_1_n_82,
P(22) => mul_temp_1_n_83,
P(21) => mul_temp_1_n_84,
P(20) => mul_temp_1_n_85,
P(19) => mul_temp_1_n_86,
P(18) => mul_temp_1_n_87,
P(17) => mul_temp_1_n_88,
P(16) => mul_temp_1_n_89,
P(15) => mul_temp_1_n_90,
P(14) => \^mul_temp_1\(14),
P(13) => mul_temp_1_n_92,
P(12) => mul_temp_1_n_93,
P(11) => mul_temp_1_n_94,
P(10) => mul_temp_1_n_95,
P(9) => mul_temp_1_n_96,
P(8) => mul_temp_1_n_97,
P(7) => mul_temp_1_n_98,
P(6) => mul_temp_1_n_99,
P(5) => mul_temp_1_n_100,
P(4) => mul_temp_1_n_101,
P(3) => mul_temp_1_n_102,
P(2) => mul_temp_1_n_103,
P(1) => mul_temp_1_n_104,
P(0) => mul_temp_1_n_105,
PATTERNBDETECT => NLW_mul_temp_1_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_1_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_1_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_1_UNDERFLOW_UNCONNECTED
);
mul_temp_10: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_10_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[10]_9\(15),
B(16) => \weight_reg[10]_9\(15),
B(15 downto 0) => \weight_reg[10]_9\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_10_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_10_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_10_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_10_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_10_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_10_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_10_n_74,
P(30) => mul_temp_10_n_75,
P(29) => mul_temp_10_n_76,
P(28) => mul_temp_10_n_77,
P(27) => mul_temp_10_n_78,
P(26) => mul_temp_10_n_79,
P(25) => mul_temp_10_n_80,
P(24) => mul_temp_10_n_81,
P(23) => mul_temp_10_n_82,
P(22) => mul_temp_10_n_83,
P(21) => mul_temp_10_n_84,
P(20) => mul_temp_10_n_85,
P(19) => mul_temp_10_n_86,
P(18) => mul_temp_10_n_87,
P(17) => mul_temp_10_n_88,
P(16) => mul_temp_10_n_89,
P(15) => mul_temp_10_n_90,
P(14) => \^mul_temp_10\(14),
P(13) => mul_temp_10_n_92,
P(12) => mul_temp_10_n_93,
P(11) => mul_temp_10_n_94,
P(10) => mul_temp_10_n_95,
P(9) => mul_temp_10_n_96,
P(8) => mul_temp_10_n_97,
P(7) => mul_temp_10_n_98,
P(6) => mul_temp_10_n_99,
P(5) => mul_temp_10_n_100,
P(4) => mul_temp_10_n_101,
P(3) => mul_temp_10_n_102,
P(2) => mul_temp_10_n_103,
P(1) => mul_temp_10_n_104,
P(0) => mul_temp_10_n_105,
PATTERNBDETECT => NLW_mul_temp_10_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_10_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_10_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_10_UNDERFLOW_UNCONNECTED
);
mul_temp_11: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_11_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[11]_10\(15),
B(16) => \weight_reg[11]_10\(15),
B(15 downto 0) => \weight_reg[11]_10\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_11_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_11_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_11_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_11_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_11_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_11_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_11_n_74,
P(30) => mul_temp_11_n_75,
P(29) => mul_temp_11_n_76,
P(28) => mul_temp_11_n_77,
P(27) => mul_temp_11_n_78,
P(26) => mul_temp_11_n_79,
P(25) => mul_temp_11_n_80,
P(24) => mul_temp_11_n_81,
P(23) => mul_temp_11_n_82,
P(22) => mul_temp_11_n_83,
P(21) => mul_temp_11_n_84,
P(20) => mul_temp_11_n_85,
P(19) => mul_temp_11_n_86,
P(18) => mul_temp_11_n_87,
P(17) => mul_temp_11_n_88,
P(16) => mul_temp_11_n_89,
P(15) => mul_temp_11_n_90,
P(14) => \^mul_temp_11\(14),
P(13) => mul_temp_11_n_92,
P(12) => mul_temp_11_n_93,
P(11) => mul_temp_11_n_94,
P(10) => mul_temp_11_n_95,
P(9) => mul_temp_11_n_96,
P(8) => mul_temp_11_n_97,
P(7) => mul_temp_11_n_98,
P(6) => mul_temp_11_n_99,
P(5) => mul_temp_11_n_100,
P(4) => mul_temp_11_n_101,
P(3) => mul_temp_11_n_102,
P(2) => mul_temp_11_n_103,
P(1) => mul_temp_11_n_104,
P(0) => mul_temp_11_n_105,
PATTERNBDETECT => NLW_mul_temp_11_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_11_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_11_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_11_UNDERFLOW_UNCONNECTED
);
mul_temp_12: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_12_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[12]_11\(15),
B(16) => \weight_reg[12]_11\(15),
B(15 downto 0) => \weight_reg[12]_11\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_12_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_12_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_12_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_12_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_12_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_12_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_12_n_74,
P(30) => mul_temp_12_n_75,
P(29) => mul_temp_12_n_76,
P(28) => mul_temp_12_n_77,
P(27) => mul_temp_12_n_78,
P(26) => mul_temp_12_n_79,
P(25) => mul_temp_12_n_80,
P(24) => mul_temp_12_n_81,
P(23) => mul_temp_12_n_82,
P(22) => mul_temp_12_n_83,
P(21) => mul_temp_12_n_84,
P(20) => mul_temp_12_n_85,
P(19) => mul_temp_12_n_86,
P(18) => mul_temp_12_n_87,
P(17) => mul_temp_12_n_88,
P(16) => mul_temp_12_n_89,
P(15) => mul_temp_12_n_90,
P(14) => \^mul_temp_12\(14),
P(13) => mul_temp_12_n_92,
P(12) => mul_temp_12_n_93,
P(11) => mul_temp_12_n_94,
P(10) => mul_temp_12_n_95,
P(9) => mul_temp_12_n_96,
P(8) => mul_temp_12_n_97,
P(7) => mul_temp_12_n_98,
P(6) => mul_temp_12_n_99,
P(5) => mul_temp_12_n_100,
P(4) => mul_temp_12_n_101,
P(3) => mul_temp_12_n_102,
P(2) => mul_temp_12_n_103,
P(1) => mul_temp_12_n_104,
P(0) => mul_temp_12_n_105,
PATTERNBDETECT => NLW_mul_temp_12_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_12_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_12_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_12_UNDERFLOW_UNCONNECTED
);
mul_temp_13: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_13_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[13]_12\(15),
B(16) => \weight_reg[13]_12\(15),
B(15 downto 0) => \weight_reg[13]_12\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_13_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_13_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_13_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_13_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_13_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_13_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_13_n_74,
P(30) => mul_temp_13_n_75,
P(29) => mul_temp_13_n_76,
P(28) => mul_temp_13_n_77,
P(27) => mul_temp_13_n_78,
P(26) => mul_temp_13_n_79,
P(25) => mul_temp_13_n_80,
P(24) => mul_temp_13_n_81,
P(23) => mul_temp_13_n_82,
P(22) => mul_temp_13_n_83,
P(21) => mul_temp_13_n_84,
P(20) => mul_temp_13_n_85,
P(19) => mul_temp_13_n_86,
P(18) => mul_temp_13_n_87,
P(17) => mul_temp_13_n_88,
P(16) => mul_temp_13_n_89,
P(15) => mul_temp_13_n_90,
P(14) => \^mul_temp_13\(14),
P(13) => mul_temp_13_n_92,
P(12) => mul_temp_13_n_93,
P(11) => mul_temp_13_n_94,
P(10) => mul_temp_13_n_95,
P(9) => mul_temp_13_n_96,
P(8) => mul_temp_13_n_97,
P(7) => mul_temp_13_n_98,
P(6) => mul_temp_13_n_99,
P(5) => mul_temp_13_n_100,
P(4) => mul_temp_13_n_101,
P(3) => mul_temp_13_n_102,
P(2) => mul_temp_13_n_103,
P(1) => mul_temp_13_n_104,
P(0) => mul_temp_13_n_105,
PATTERNBDETECT => NLW_mul_temp_13_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_13_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_13_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_13_UNDERFLOW_UNCONNECTED
);
mul_temp_14: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_14_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[14]_13\(15),
B(16) => \weight_reg[14]_13\(15),
B(15 downto 0) => \weight_reg[14]_13\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_14_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_14_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_14_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_14_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_14_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_14_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_14_n_74,
P(30) => mul_temp_14_n_75,
P(29) => mul_temp_14_n_76,
P(28) => mul_temp_14_n_77,
P(27) => mul_temp_14_n_78,
P(26) => mul_temp_14_n_79,
P(25) => mul_temp_14_n_80,
P(24) => mul_temp_14_n_81,
P(23) => mul_temp_14_n_82,
P(22) => mul_temp_14_n_83,
P(21) => mul_temp_14_n_84,
P(20) => mul_temp_14_n_85,
P(19) => mul_temp_14_n_86,
P(18) => mul_temp_14_n_87,
P(17) => mul_temp_14_n_88,
P(16) => mul_temp_14_n_89,
P(15) => mul_temp_14_n_90,
P(14) => \^mul_temp_14\(14),
P(13) => mul_temp_14_n_92,
P(12) => mul_temp_14_n_93,
P(11) => mul_temp_14_n_94,
P(10) => mul_temp_14_n_95,
P(9) => mul_temp_14_n_96,
P(8) => mul_temp_14_n_97,
P(7) => mul_temp_14_n_98,
P(6) => mul_temp_14_n_99,
P(5) => mul_temp_14_n_100,
P(4) => mul_temp_14_n_101,
P(3) => mul_temp_14_n_102,
P(2) => mul_temp_14_n_103,
P(1) => mul_temp_14_n_104,
P(0) => mul_temp_14_n_105,
PATTERNBDETECT => NLW_mul_temp_14_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_14_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_14_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_14_UNDERFLOW_UNCONNECTED
);
mul_temp_15: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_15_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[15]_14\(15),
B(16) => \weight_reg[15]_14\(15),
B(15 downto 0) => \weight_reg[15]_14\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_15_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_15_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_15_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_15_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_15_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_15_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_15_n_74,
P(30) => mul_temp_15_n_75,
P(29) => mul_temp_15_n_76,
P(28) => mul_temp_15_n_77,
P(27) => mul_temp_15_n_78,
P(26) => mul_temp_15_n_79,
P(25) => mul_temp_15_n_80,
P(24) => mul_temp_15_n_81,
P(23) => mul_temp_15_n_82,
P(22) => mul_temp_15_n_83,
P(21) => mul_temp_15_n_84,
P(20) => mul_temp_15_n_85,
P(19) => mul_temp_15_n_86,
P(18) => mul_temp_15_n_87,
P(17) => mul_temp_15_n_88,
P(16) => mul_temp_15_n_89,
P(15) => mul_temp_15_n_90,
P(14) => \^mul_temp_15\(14),
P(13) => mul_temp_15_n_92,
P(12) => mul_temp_15_n_93,
P(11) => mul_temp_15_n_94,
P(10) => mul_temp_15_n_95,
P(9) => mul_temp_15_n_96,
P(8) => mul_temp_15_n_97,
P(7) => mul_temp_15_n_98,
P(6) => mul_temp_15_n_99,
P(5) => mul_temp_15_n_100,
P(4) => mul_temp_15_n_101,
P(3) => mul_temp_15_n_102,
P(2) => mul_temp_15_n_103,
P(1) => mul_temp_15_n_104,
P(0) => mul_temp_15_n_105,
PATTERNBDETECT => NLW_mul_temp_15_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_15_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_15_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_15_UNDERFLOW_UNCONNECTED
);
mul_temp_17: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_17_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_17_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_17_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_17_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_17_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_17_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_17_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_17_n_74,
P(30) => mul_temp_17_n_75,
P(29) => mul_temp_17_n_76,
P(28) => mul_temp_17_n_77,
P(27) => mul_temp_17_n_78,
P(26) => mul_temp_17_n_79,
P(25) => mul_temp_17_n_80,
P(24) => mul_temp_17_n_81,
P(23) => mul_temp_17_n_82,
P(22) => mul_temp_17_n_83,
P(21) => mul_temp_17_n_84,
P(20) => mul_temp_17_n_85,
P(19) => mul_temp_17_n_86,
P(18) => mul_temp_17_n_87,
P(17) => mul_temp_17_n_88,
P(16) => mul_temp_17_n_89,
P(15) => mul_temp_17_n_90,
P(14) => \^mul_temp_17\(14),
P(13) => mul_temp_17_n_92,
P(12) => mul_temp_17_n_93,
P(11) => mul_temp_17_n_94,
P(10) => mul_temp_17_n_95,
P(9) => mul_temp_17_n_96,
P(8) => mul_temp_17_n_97,
P(7) => mul_temp_17_n_98,
P(6) => mul_temp_17_n_99,
P(5) => mul_temp_17_n_100,
P(4) => mul_temp_17_n_101,
P(3) => mul_temp_17_n_102,
P(2) => mul_temp_17_n_103,
P(1) => mul_temp_17_n_104,
P(0) => mul_temp_17_n_105,
PATTERNBDETECT => NLW_mul_temp_17_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_17_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_17_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_17_UNDERFLOW_UNCONNECTED
);
mul_temp_18: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_18_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_18_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_18_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_18_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_18_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_18_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_18_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_18_n_74,
P(30) => mul_temp_18_n_75,
P(29) => mul_temp_18_n_76,
P(28) => mul_temp_18_n_77,
P(27) => mul_temp_18_n_78,
P(26) => mul_temp_18_n_79,
P(25) => mul_temp_18_n_80,
P(24) => mul_temp_18_n_81,
P(23) => mul_temp_18_n_82,
P(22) => mul_temp_18_n_83,
P(21) => mul_temp_18_n_84,
P(20) => mul_temp_18_n_85,
P(19) => mul_temp_18_n_86,
P(18) => mul_temp_18_n_87,
P(17) => mul_temp_18_n_88,
P(16) => mul_temp_18_n_89,
P(15) => mul_temp_18_n_90,
P(14) => \^mul_temp_18\(14),
P(13) => mul_temp_18_n_92,
P(12) => mul_temp_18_n_93,
P(11) => mul_temp_18_n_94,
P(10) => mul_temp_18_n_95,
P(9) => mul_temp_18_n_96,
P(8) => mul_temp_18_n_97,
P(7) => mul_temp_18_n_98,
P(6) => mul_temp_18_n_99,
P(5) => mul_temp_18_n_100,
P(4) => mul_temp_18_n_101,
P(3) => mul_temp_18_n_102,
P(2) => mul_temp_18_n_103,
P(1) => mul_temp_18_n_104,
P(0) => mul_temp_18_n_105,
PATTERNBDETECT => NLW_mul_temp_18_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_18_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_18_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_18_UNDERFLOW_UNCONNECTED
);
mul_temp_19: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_19_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_19_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_19_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_19_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_19_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_19_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_19_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_19_n_74,
P(30) => mul_temp_19_n_75,
P(29) => mul_temp_19_n_76,
P(28) => mul_temp_19_n_77,
P(27) => mul_temp_19_n_78,
P(26) => mul_temp_19_n_79,
P(25) => mul_temp_19_n_80,
P(24) => mul_temp_19_n_81,
P(23) => mul_temp_19_n_82,
P(22) => mul_temp_19_n_83,
P(21) => mul_temp_19_n_84,
P(20) => mul_temp_19_n_85,
P(19) => mul_temp_19_n_86,
P(18) => mul_temp_19_n_87,
P(17) => mul_temp_19_n_88,
P(16) => mul_temp_19_n_89,
P(15) => mul_temp_19_n_90,
P(14) => \^mul_temp_19\(14),
P(13) => mul_temp_19_n_92,
P(12) => mul_temp_19_n_93,
P(11) => mul_temp_19_n_94,
P(10) => mul_temp_19_n_95,
P(9) => mul_temp_19_n_96,
P(8) => mul_temp_19_n_97,
P(7) => mul_temp_19_n_98,
P(6) => mul_temp_19_n_99,
P(5) => mul_temp_19_n_100,
P(4) => mul_temp_19_n_101,
P(3) => mul_temp_19_n_102,
P(2) => mul_temp_19_n_103,
P(1) => mul_temp_19_n_104,
P(0) => mul_temp_19_n_105,
PATTERNBDETECT => NLW_mul_temp_19_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_19_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_19_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_19_UNDERFLOW_UNCONNECTED
);
mul_temp_2: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_2_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[2]_1\(15),
B(16) => \weight_reg[2]_1\(15),
B(15 downto 0) => \weight_reg[2]_1\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_2_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_2_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_2_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_2_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_2_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_2_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_2_n_74,
P(30) => mul_temp_2_n_75,
P(29) => mul_temp_2_n_76,
P(28) => mul_temp_2_n_77,
P(27) => mul_temp_2_n_78,
P(26) => mul_temp_2_n_79,
P(25) => mul_temp_2_n_80,
P(24) => mul_temp_2_n_81,
P(23) => mul_temp_2_n_82,
P(22) => mul_temp_2_n_83,
P(21) => mul_temp_2_n_84,
P(20) => mul_temp_2_n_85,
P(19) => mul_temp_2_n_86,
P(18) => mul_temp_2_n_87,
P(17) => mul_temp_2_n_88,
P(16) => mul_temp_2_n_89,
P(15) => mul_temp_2_n_90,
P(14) => \^mul_temp_2\(14),
P(13) => mul_temp_2_n_92,
P(12) => mul_temp_2_n_93,
P(11) => mul_temp_2_n_94,
P(10) => mul_temp_2_n_95,
P(9) => mul_temp_2_n_96,
P(8) => mul_temp_2_n_97,
P(7) => mul_temp_2_n_98,
P(6) => mul_temp_2_n_99,
P(5) => mul_temp_2_n_100,
P(4) => mul_temp_2_n_101,
P(3) => mul_temp_2_n_102,
P(2) => mul_temp_2_n_103,
P(1) => mul_temp_2_n_104,
P(0) => mul_temp_2_n_105,
PATTERNBDETECT => NLW_mul_temp_2_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_2_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_2_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_2_UNDERFLOW_UNCONNECTED
);
mul_temp_20: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_20_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_20_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_20_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_20_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_20_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_20_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_20_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_20_n_74,
P(30) => mul_temp_20_n_75,
P(29) => mul_temp_20_n_76,
P(28) => mul_temp_20_n_77,
P(27) => mul_temp_20_n_78,
P(26) => mul_temp_20_n_79,
P(25) => mul_temp_20_n_80,
P(24) => mul_temp_20_n_81,
P(23) => mul_temp_20_n_82,
P(22) => mul_temp_20_n_83,
P(21) => mul_temp_20_n_84,
P(20) => mul_temp_20_n_85,
P(19) => mul_temp_20_n_86,
P(18) => mul_temp_20_n_87,
P(17) => mul_temp_20_n_88,
P(16) => mul_temp_20_n_89,
P(15) => mul_temp_20_n_90,
P(14) => \^mul_temp_20\(14),
P(13) => mul_temp_20_n_92,
P(12) => mul_temp_20_n_93,
P(11) => mul_temp_20_n_94,
P(10) => mul_temp_20_n_95,
P(9) => mul_temp_20_n_96,
P(8) => mul_temp_20_n_97,
P(7) => mul_temp_20_n_98,
P(6) => mul_temp_20_n_99,
P(5) => mul_temp_20_n_100,
P(4) => mul_temp_20_n_101,
P(3) => mul_temp_20_n_102,
P(2) => mul_temp_20_n_103,
P(1) => mul_temp_20_n_104,
P(0) => mul_temp_20_n_105,
PATTERNBDETECT => NLW_mul_temp_20_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_20_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_20_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_20_UNDERFLOW_UNCONNECTED
);
mul_temp_21: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_21_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_21_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_21_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_21_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_21_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_21_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_21_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_21_n_74,
P(30) => mul_temp_21_n_75,
P(29) => mul_temp_21_n_76,
P(28) => mul_temp_21_n_77,
P(27) => mul_temp_21_n_78,
P(26) => mul_temp_21_n_79,
P(25) => mul_temp_21_n_80,
P(24) => mul_temp_21_n_81,
P(23) => mul_temp_21_n_82,
P(22) => mul_temp_21_n_83,
P(21) => mul_temp_21_n_84,
P(20) => mul_temp_21_n_85,
P(19) => mul_temp_21_n_86,
P(18) => mul_temp_21_n_87,
P(17) => mul_temp_21_n_88,
P(16) => mul_temp_21_n_89,
P(15) => mul_temp_21_n_90,
P(14) => \^mul_temp_21\(14),
P(13) => mul_temp_21_n_92,
P(12) => mul_temp_21_n_93,
P(11) => mul_temp_21_n_94,
P(10) => mul_temp_21_n_95,
P(9) => mul_temp_21_n_96,
P(8) => mul_temp_21_n_97,
P(7) => mul_temp_21_n_98,
P(6) => mul_temp_21_n_99,
P(5) => mul_temp_21_n_100,
P(4) => mul_temp_21_n_101,
P(3) => mul_temp_21_n_102,
P(2) => mul_temp_21_n_103,
P(1) => mul_temp_21_n_104,
P(0) => mul_temp_21_n_105,
PATTERNBDETECT => NLW_mul_temp_21_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_21_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_21_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_21_UNDERFLOW_UNCONNECTED
);
mul_temp_22: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_22_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_22_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_22_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_22_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_22_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_22_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_22_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_22_n_74,
P(30) => mul_temp_22_n_75,
P(29) => mul_temp_22_n_76,
P(28) => mul_temp_22_n_77,
P(27) => mul_temp_22_n_78,
P(26) => mul_temp_22_n_79,
P(25) => mul_temp_22_n_80,
P(24) => mul_temp_22_n_81,
P(23) => mul_temp_22_n_82,
P(22) => mul_temp_22_n_83,
P(21) => mul_temp_22_n_84,
P(20) => mul_temp_22_n_85,
P(19) => mul_temp_22_n_86,
P(18) => mul_temp_22_n_87,
P(17) => mul_temp_22_n_88,
P(16) => mul_temp_22_n_89,
P(15) => mul_temp_22_n_90,
P(14) => \^mul_temp_22\(14),
P(13) => mul_temp_22_n_92,
P(12) => mul_temp_22_n_93,
P(11) => mul_temp_22_n_94,
P(10) => mul_temp_22_n_95,
P(9) => mul_temp_22_n_96,
P(8) => mul_temp_22_n_97,
P(7) => mul_temp_22_n_98,
P(6) => mul_temp_22_n_99,
P(5) => mul_temp_22_n_100,
P(4) => mul_temp_22_n_101,
P(3) => mul_temp_22_n_102,
P(2) => mul_temp_22_n_103,
P(1) => mul_temp_22_n_104,
P(0) => mul_temp_22_n_105,
PATTERNBDETECT => NLW_mul_temp_22_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_22_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_22_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_22_UNDERFLOW_UNCONNECTED
);
mul_temp_23: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_23_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_23_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_23_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_23_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_23_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_23_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_23_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_23_n_74,
P(30) => mul_temp_23_n_75,
P(29) => mul_temp_23_n_76,
P(28) => mul_temp_23_n_77,
P(27) => mul_temp_23_n_78,
P(26) => mul_temp_23_n_79,
P(25) => mul_temp_23_n_80,
P(24) => mul_temp_23_n_81,
P(23) => mul_temp_23_n_82,
P(22) => mul_temp_23_n_83,
P(21) => mul_temp_23_n_84,
P(20) => mul_temp_23_n_85,
P(19) => mul_temp_23_n_86,
P(18) => mul_temp_23_n_87,
P(17) => mul_temp_23_n_88,
P(16) => mul_temp_23_n_89,
P(15) => mul_temp_23_n_90,
P(14) => \^mul_temp_23\(14),
P(13) => mul_temp_23_n_92,
P(12) => mul_temp_23_n_93,
P(11) => mul_temp_23_n_94,
P(10) => mul_temp_23_n_95,
P(9) => mul_temp_23_n_96,
P(8) => mul_temp_23_n_97,
P(7) => mul_temp_23_n_98,
P(6) => mul_temp_23_n_99,
P(5) => mul_temp_23_n_100,
P(4) => mul_temp_23_n_101,
P(3) => mul_temp_23_n_102,
P(2) => mul_temp_23_n_103,
P(1) => mul_temp_23_n_104,
P(0) => mul_temp_23_n_105,
PATTERNBDETECT => NLW_mul_temp_23_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_23_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_23_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_23_UNDERFLOW_UNCONNECTED
);
mul_temp_24: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_24_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_24_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_24_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_24_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_24_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_24_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_24_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_24_n_74,
P(30) => mul_temp_24_n_75,
P(29) => mul_temp_24_n_76,
P(28) => mul_temp_24_n_77,
P(27) => mul_temp_24_n_78,
P(26) => mul_temp_24_n_79,
P(25) => mul_temp_24_n_80,
P(24) => mul_temp_24_n_81,
P(23) => mul_temp_24_n_82,
P(22) => mul_temp_24_n_83,
P(21) => mul_temp_24_n_84,
P(20) => mul_temp_24_n_85,
P(19) => mul_temp_24_n_86,
P(18) => mul_temp_24_n_87,
P(17) => mul_temp_24_n_88,
P(16) => mul_temp_24_n_89,
P(15) => mul_temp_24_n_90,
P(14) => \^mul_temp_24\(14),
P(13) => mul_temp_24_n_92,
P(12) => mul_temp_24_n_93,
P(11) => mul_temp_24_n_94,
P(10) => mul_temp_24_n_95,
P(9) => mul_temp_24_n_96,
P(8) => mul_temp_24_n_97,
P(7) => mul_temp_24_n_98,
P(6) => mul_temp_24_n_99,
P(5) => mul_temp_24_n_100,
P(4) => mul_temp_24_n_101,
P(3) => mul_temp_24_n_102,
P(2) => mul_temp_24_n_103,
P(1) => mul_temp_24_n_104,
P(0) => mul_temp_24_n_105,
PATTERNBDETECT => NLW_mul_temp_24_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_24_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_24_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_24_UNDERFLOW_UNCONNECTED
);
mul_temp_25: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_25_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_25_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_25_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_25_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_25_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_25_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_25_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_25_n_74,
P(30) => mul_temp_25_n_75,
P(29) => mul_temp_25_n_76,
P(28) => mul_temp_25_n_77,
P(27) => mul_temp_25_n_78,
P(26) => mul_temp_25_n_79,
P(25) => mul_temp_25_n_80,
P(24) => mul_temp_25_n_81,
P(23) => mul_temp_25_n_82,
P(22) => mul_temp_25_n_83,
P(21) => mul_temp_25_n_84,
P(20) => mul_temp_25_n_85,
P(19) => mul_temp_25_n_86,
P(18) => mul_temp_25_n_87,
P(17) => mul_temp_25_n_88,
P(16) => mul_temp_25_n_89,
P(15) => mul_temp_25_n_90,
P(14) => \^mul_temp_25\(14),
P(13) => mul_temp_25_n_92,
P(12) => mul_temp_25_n_93,
P(11) => mul_temp_25_n_94,
P(10) => mul_temp_25_n_95,
P(9) => mul_temp_25_n_96,
P(8) => mul_temp_25_n_97,
P(7) => mul_temp_25_n_98,
P(6) => mul_temp_25_n_99,
P(5) => mul_temp_25_n_100,
P(4) => mul_temp_25_n_101,
P(3) => mul_temp_25_n_102,
P(2) => mul_temp_25_n_103,
P(1) => mul_temp_25_n_104,
P(0) => mul_temp_25_n_105,
PATTERNBDETECT => NLW_mul_temp_25_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_25_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_25_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_25_UNDERFLOW_UNCONNECTED
);
mul_temp_26: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_26_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_26_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_26_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_26_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_26_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_26_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_26_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_26_n_74,
P(30) => mul_temp_26_n_75,
P(29) => mul_temp_26_n_76,
P(28) => mul_temp_26_n_77,
P(27) => mul_temp_26_n_78,
P(26) => mul_temp_26_n_79,
P(25) => mul_temp_26_n_80,
P(24) => mul_temp_26_n_81,
P(23) => mul_temp_26_n_82,
P(22) => mul_temp_26_n_83,
P(21) => mul_temp_26_n_84,
P(20) => mul_temp_26_n_85,
P(19) => mul_temp_26_n_86,
P(18) => mul_temp_26_n_87,
P(17) => mul_temp_26_n_88,
P(16) => mul_temp_26_n_89,
P(15) => mul_temp_26_n_90,
P(14) => \^mul_temp_26\(14),
P(13) => mul_temp_26_n_92,
P(12) => mul_temp_26_n_93,
P(11) => mul_temp_26_n_94,
P(10) => mul_temp_26_n_95,
P(9) => mul_temp_26_n_96,
P(8) => mul_temp_26_n_97,
P(7) => mul_temp_26_n_98,
P(6) => mul_temp_26_n_99,
P(5) => mul_temp_26_n_100,
P(4) => mul_temp_26_n_101,
P(3) => mul_temp_26_n_102,
P(2) => mul_temp_26_n_103,
P(1) => mul_temp_26_n_104,
P(0) => mul_temp_26_n_105,
PATTERNBDETECT => NLW_mul_temp_26_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_26_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_26_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_26_UNDERFLOW_UNCONNECTED
);
mul_temp_27: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_27_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_27_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_27_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_27_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_27_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_27_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_27_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_27_n_74,
P(30) => mul_temp_27_n_75,
P(29) => mul_temp_27_n_76,
P(28) => mul_temp_27_n_77,
P(27) => mul_temp_27_n_78,
P(26) => mul_temp_27_n_79,
P(25) => mul_temp_27_n_80,
P(24) => mul_temp_27_n_81,
P(23) => mul_temp_27_n_82,
P(22) => mul_temp_27_n_83,
P(21) => mul_temp_27_n_84,
P(20) => mul_temp_27_n_85,
P(19) => mul_temp_27_n_86,
P(18) => mul_temp_27_n_87,
P(17) => mul_temp_27_n_88,
P(16) => mul_temp_27_n_89,
P(15) => mul_temp_27_n_90,
P(14) => \^mul_temp_27\(14),
P(13) => mul_temp_27_n_92,
P(12) => mul_temp_27_n_93,
P(11) => mul_temp_27_n_94,
P(10) => mul_temp_27_n_95,
P(9) => mul_temp_27_n_96,
P(8) => mul_temp_27_n_97,
P(7) => mul_temp_27_n_98,
P(6) => mul_temp_27_n_99,
P(5) => mul_temp_27_n_100,
P(4) => mul_temp_27_n_101,
P(3) => mul_temp_27_n_102,
P(2) => mul_temp_27_n_103,
P(1) => mul_temp_27_n_104,
P(0) => mul_temp_27_n_105,
PATTERNBDETECT => NLW_mul_temp_27_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_27_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_27_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_27_UNDERFLOW_UNCONNECTED
);
mul_temp_28: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_28_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_28_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_28_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_28_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_28_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_28_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_28_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_28_n_74,
P(30) => mul_temp_28_n_75,
P(29) => mul_temp_28_n_76,
P(28) => mul_temp_28_n_77,
P(27) => mul_temp_28_n_78,
P(26) => mul_temp_28_n_79,
P(25) => mul_temp_28_n_80,
P(24) => mul_temp_28_n_81,
P(23) => mul_temp_28_n_82,
P(22) => mul_temp_28_n_83,
P(21) => mul_temp_28_n_84,
P(20) => mul_temp_28_n_85,
P(19) => mul_temp_28_n_86,
P(18) => mul_temp_28_n_87,
P(17) => mul_temp_28_n_88,
P(16) => mul_temp_28_n_89,
P(15) => mul_temp_28_n_90,
P(14) => \^mul_temp_28\(14),
P(13) => mul_temp_28_n_92,
P(12) => mul_temp_28_n_93,
P(11) => mul_temp_28_n_94,
P(10) => mul_temp_28_n_95,
P(9) => mul_temp_28_n_96,
P(8) => mul_temp_28_n_97,
P(7) => mul_temp_28_n_98,
P(6) => mul_temp_28_n_99,
P(5) => mul_temp_28_n_100,
P(4) => mul_temp_28_n_101,
P(3) => mul_temp_28_n_102,
P(2) => mul_temp_28_n_103,
P(1) => mul_temp_28_n_104,
P(0) => mul_temp_28_n_105,
PATTERNBDETECT => NLW_mul_temp_28_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_28_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_28_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_28_UNDERFLOW_UNCONNECTED
);
mul_temp_29: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_29_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_29_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_29_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_29_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_29_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_29_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_29_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_29_n_74,
P(30) => mul_temp_29_n_75,
P(29) => mul_temp_29_n_76,
P(28) => mul_temp_29_n_77,
P(27) => mul_temp_29_n_78,
P(26) => mul_temp_29_n_79,
P(25) => mul_temp_29_n_80,
P(24) => mul_temp_29_n_81,
P(23) => mul_temp_29_n_82,
P(22) => mul_temp_29_n_83,
P(21) => mul_temp_29_n_84,
P(20) => mul_temp_29_n_85,
P(19) => mul_temp_29_n_86,
P(18) => mul_temp_29_n_87,
P(17) => mul_temp_29_n_88,
P(16) => mul_temp_29_n_89,
P(15) => mul_temp_29_n_90,
P(14) => \^mul_temp_29\(14),
P(13) => mul_temp_29_n_92,
P(12) => mul_temp_29_n_93,
P(11) => mul_temp_29_n_94,
P(10) => mul_temp_29_n_95,
P(9) => mul_temp_29_n_96,
P(8) => mul_temp_29_n_97,
P(7) => mul_temp_29_n_98,
P(6) => mul_temp_29_n_99,
P(5) => mul_temp_29_n_100,
P(4) => mul_temp_29_n_101,
P(3) => mul_temp_29_n_102,
P(2) => mul_temp_29_n_103,
P(1) => mul_temp_29_n_104,
P(0) => mul_temp_29_n_105,
PATTERNBDETECT => NLW_mul_temp_29_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_29_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_29_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_29_UNDERFLOW_UNCONNECTED
);
mul_temp_3: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_3_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[3]_2\(15),
B(16) => \weight_reg[3]_2\(15),
B(15 downto 0) => \weight_reg[3]_2\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_3_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_3_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_3_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_3_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_3_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_3_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_3_n_74,
P(30) => mul_temp_3_n_75,
P(29) => mul_temp_3_n_76,
P(28) => mul_temp_3_n_77,
P(27) => mul_temp_3_n_78,
P(26) => mul_temp_3_n_79,
P(25) => mul_temp_3_n_80,
P(24) => mul_temp_3_n_81,
P(23) => mul_temp_3_n_82,
P(22) => mul_temp_3_n_83,
P(21) => mul_temp_3_n_84,
P(20) => mul_temp_3_n_85,
P(19) => mul_temp_3_n_86,
P(18) => mul_temp_3_n_87,
P(17) => mul_temp_3_n_88,
P(16) => mul_temp_3_n_89,
P(15) => mul_temp_3_n_90,
P(14) => \^mul_temp_3\(14),
P(13) => mul_temp_3_n_92,
P(12) => mul_temp_3_n_93,
P(11) => mul_temp_3_n_94,
P(10) => mul_temp_3_n_95,
P(9) => mul_temp_3_n_96,
P(8) => mul_temp_3_n_97,
P(7) => mul_temp_3_n_98,
P(6) => mul_temp_3_n_99,
P(5) => mul_temp_3_n_100,
P(4) => mul_temp_3_n_101,
P(3) => mul_temp_3_n_102,
P(2) => mul_temp_3_n_103,
P(1) => mul_temp_3_n_104,
P(0) => mul_temp_3_n_105,
PATTERNBDETECT => NLW_mul_temp_3_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_3_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_3_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_3_UNDERFLOW_UNCONNECTED
);
mul_temp_30: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_30_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_30_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_30_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_30_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_30_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_30_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_30_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_30_n_74,
P(30) => mul_temp_30_n_75,
P(29) => mul_temp_30_n_76,
P(28) => mul_temp_30_n_77,
P(27) => mul_temp_30_n_78,
P(26) => mul_temp_30_n_79,
P(25) => mul_temp_30_n_80,
P(24) => mul_temp_30_n_81,
P(23) => mul_temp_30_n_82,
P(22) => mul_temp_30_n_83,
P(21) => mul_temp_30_n_84,
P(20) => mul_temp_30_n_85,
P(19) => mul_temp_30_n_86,
P(18) => mul_temp_30_n_87,
P(17) => mul_temp_30_n_88,
P(16) => mul_temp_30_n_89,
P(15) => mul_temp_30_n_90,
P(14) => \^mul_temp_30\(14),
P(13) => mul_temp_30_n_92,
P(12) => mul_temp_30_n_93,
P(11) => mul_temp_30_n_94,
P(10) => mul_temp_30_n_95,
P(9) => mul_temp_30_n_96,
P(8) => mul_temp_30_n_97,
P(7) => mul_temp_30_n_98,
P(6) => mul_temp_30_n_99,
P(5) => mul_temp_30_n_100,
P(4) => mul_temp_30_n_101,
P(3) => mul_temp_30_n_102,
P(2) => mul_temp_30_n_103,
P(1) => mul_temp_30_n_104,
P(0) => mul_temp_30_n_105,
PATTERNBDETECT => NLW_mul_temp_30_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_30_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_30_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_30_UNDERFLOW_UNCONNECTED
);
mul_temp_31: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_31_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_31_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_31_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_31_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_31_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_31_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_31_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_31_n_74,
P(30) => mul_temp_31_n_75,
P(29) => mul_temp_31_n_76,
P(28) => mul_temp_31_n_77,
P(27) => mul_temp_31_n_78,
P(26) => mul_temp_31_n_79,
P(25) => mul_temp_31_n_80,
P(24) => mul_temp_31_n_81,
P(23) => mul_temp_31_n_82,
P(22) => mul_temp_31_n_83,
P(21) => mul_temp_31_n_84,
P(20) => mul_temp_31_n_85,
P(19) => mul_temp_31_n_86,
P(18) => mul_temp_31_n_87,
P(17) => mul_temp_31_n_88,
P(16) => mul_temp_31_n_89,
P(15) => mul_temp_31_n_90,
P(14) => \^mul_temp_31\(14),
P(13) => mul_temp_31_n_92,
P(12) => mul_temp_31_n_93,
P(11) => mul_temp_31_n_94,
P(10) => mul_temp_31_n_95,
P(9) => mul_temp_31_n_96,
P(8) => mul_temp_31_n_97,
P(7) => mul_temp_31_n_98,
P(6) => mul_temp_31_n_99,
P(5) => mul_temp_31_n_100,
P(4) => mul_temp_31_n_101,
P(3) => mul_temp_31_n_102,
P(2) => mul_temp_31_n_103,
P(1) => mul_temp_31_n_104,
P(0) => mul_temp_31_n_105,
PATTERNBDETECT => NLW_mul_temp_31_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_31_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_31_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_31_UNDERFLOW_UNCONNECTED
);
mul_temp_32: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_32_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_32_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_32_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_32_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_32_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_32_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_32_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_32_n_74,
P(30) => mul_temp_32_n_75,
P(29) => mul_temp_32_n_76,
P(28) => mul_temp_32_n_77,
P(27) => mul_temp_32_n_78,
P(26) => mul_temp_32_n_79,
P(25) => mul_temp_32_n_80,
P(24) => mul_temp_32_n_81,
P(23) => mul_temp_32_n_82,
P(22) => mul_temp_32_n_83,
P(21) => mul_temp_32_n_84,
P(20) => mul_temp_32_n_85,
P(19) => mul_temp_32_n_86,
P(18) => mul_temp_32_n_87,
P(17) => mul_temp_32_n_88,
P(16) => mul_temp_32_n_89,
P(15) => mul_temp_32_n_90,
P(14) => \^mul_temp_32\(14),
P(13) => mul_temp_32_n_92,
P(12) => mul_temp_32_n_93,
P(11) => mul_temp_32_n_94,
P(10) => mul_temp_32_n_95,
P(9) => mul_temp_32_n_96,
P(8) => mul_temp_32_n_97,
P(7) => mul_temp_32_n_98,
P(6) => mul_temp_32_n_99,
P(5) => mul_temp_32_n_100,
P(4) => mul_temp_32_n_101,
P(3) => mul_temp_32_n_102,
P(2) => mul_temp_32_n_103,
P(1) => mul_temp_32_n_104,
P(0) => mul_temp_32_n_105,
PATTERNBDETECT => NLW_mul_temp_32_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_32_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_32_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_32_UNDERFLOW_UNCONNECTED
);
mul_temp_4: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_4_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[4]_3\(15),
B(16) => \weight_reg[4]_3\(15),
B(15 downto 0) => \weight_reg[4]_3\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_4_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_4_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_4_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_4_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_4_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_4_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_4_n_74,
P(30) => mul_temp_4_n_75,
P(29) => mul_temp_4_n_76,
P(28) => mul_temp_4_n_77,
P(27) => mul_temp_4_n_78,
P(26) => mul_temp_4_n_79,
P(25) => mul_temp_4_n_80,
P(24) => mul_temp_4_n_81,
P(23) => mul_temp_4_n_82,
P(22) => mul_temp_4_n_83,
P(21) => mul_temp_4_n_84,
P(20) => mul_temp_4_n_85,
P(19) => mul_temp_4_n_86,
P(18) => mul_temp_4_n_87,
P(17) => mul_temp_4_n_88,
P(16) => mul_temp_4_n_89,
P(15) => mul_temp_4_n_90,
P(14) => \^mul_temp_4\(14),
P(13) => mul_temp_4_n_92,
P(12) => mul_temp_4_n_93,
P(11) => mul_temp_4_n_94,
P(10) => mul_temp_4_n_95,
P(9) => mul_temp_4_n_96,
P(8) => mul_temp_4_n_97,
P(7) => mul_temp_4_n_98,
P(6) => mul_temp_4_n_99,
P(5) => mul_temp_4_n_100,
P(4) => mul_temp_4_n_101,
P(3) => mul_temp_4_n_102,
P(2) => mul_temp_4_n_103,
P(1) => mul_temp_4_n_104,
P(0) => mul_temp_4_n_105,
PATTERNBDETECT => NLW_mul_temp_4_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_4_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_4_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_4_UNDERFLOW_UNCONNECTED
);
mul_temp_5: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_5_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[5]_4\(15),
B(16) => \weight_reg[5]_4\(15),
B(15 downto 0) => \weight_reg[5]_4\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_5_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_5_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_5_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_5_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_5_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_5_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_5_n_74,
P(30) => mul_temp_5_n_75,
P(29) => mul_temp_5_n_76,
P(28) => mul_temp_5_n_77,
P(27) => mul_temp_5_n_78,
P(26) => mul_temp_5_n_79,
P(25) => mul_temp_5_n_80,
P(24) => mul_temp_5_n_81,
P(23) => mul_temp_5_n_82,
P(22) => mul_temp_5_n_83,
P(21) => mul_temp_5_n_84,
P(20) => mul_temp_5_n_85,
P(19) => mul_temp_5_n_86,
P(18) => mul_temp_5_n_87,
P(17) => mul_temp_5_n_88,
P(16) => mul_temp_5_n_89,
P(15) => mul_temp_5_n_90,
P(14) => \^mul_temp_5\(14),
P(13) => mul_temp_5_n_92,
P(12) => mul_temp_5_n_93,
P(11) => mul_temp_5_n_94,
P(10) => mul_temp_5_n_95,
P(9) => mul_temp_5_n_96,
P(8) => mul_temp_5_n_97,
P(7) => mul_temp_5_n_98,
P(6) => mul_temp_5_n_99,
P(5) => mul_temp_5_n_100,
P(4) => mul_temp_5_n_101,
P(3) => mul_temp_5_n_102,
P(2) => mul_temp_5_n_103,
P(1) => mul_temp_5_n_104,
P(0) => mul_temp_5_n_105,
PATTERNBDETECT => NLW_mul_temp_5_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_5_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_5_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_5_UNDERFLOW_UNCONNECTED
);
mul_temp_6: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_6_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[6]_5\(15),
B(16) => \weight_reg[6]_5\(15),
B(15 downto 0) => \weight_reg[6]_5\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_6_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_6_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_6_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_6_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_6_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_6_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_6_n_74,
P(30) => mul_temp_6_n_75,
P(29) => mul_temp_6_n_76,
P(28) => mul_temp_6_n_77,
P(27) => mul_temp_6_n_78,
P(26) => mul_temp_6_n_79,
P(25) => mul_temp_6_n_80,
P(24) => mul_temp_6_n_81,
P(23) => mul_temp_6_n_82,
P(22) => mul_temp_6_n_83,
P(21) => mul_temp_6_n_84,
P(20) => mul_temp_6_n_85,
P(19) => mul_temp_6_n_86,
P(18) => mul_temp_6_n_87,
P(17) => mul_temp_6_n_88,
P(16) => mul_temp_6_n_89,
P(15) => mul_temp_6_n_90,
P(14) => \^mul_temp_6\(14),
P(13) => mul_temp_6_n_92,
P(12) => mul_temp_6_n_93,
P(11) => mul_temp_6_n_94,
P(10) => mul_temp_6_n_95,
P(9) => mul_temp_6_n_96,
P(8) => mul_temp_6_n_97,
P(7) => mul_temp_6_n_98,
P(6) => mul_temp_6_n_99,
P(5) => mul_temp_6_n_100,
P(4) => mul_temp_6_n_101,
P(3) => mul_temp_6_n_102,
P(2) => mul_temp_6_n_103,
P(1) => mul_temp_6_n_104,
P(0) => mul_temp_6_n_105,
PATTERNBDETECT => NLW_mul_temp_6_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_6_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_6_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_6_UNDERFLOW_UNCONNECTED
);
mul_temp_7: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_7_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[7]_6\(15),
B(16) => \weight_reg[7]_6\(15),
B(15 downto 0) => \weight_reg[7]_6\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_7_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_7_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_7_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_7_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_7_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_7_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_7_n_74,
P(30) => mul_temp_7_n_75,
P(29) => mul_temp_7_n_76,
P(28) => mul_temp_7_n_77,
P(27) => mul_temp_7_n_78,
P(26) => mul_temp_7_n_79,
P(25) => mul_temp_7_n_80,
P(24) => mul_temp_7_n_81,
P(23) => mul_temp_7_n_82,
P(22) => mul_temp_7_n_83,
P(21) => mul_temp_7_n_84,
P(20) => mul_temp_7_n_85,
P(19) => mul_temp_7_n_86,
P(18) => mul_temp_7_n_87,
P(17) => mul_temp_7_n_88,
P(16) => mul_temp_7_n_89,
P(15) => mul_temp_7_n_90,
P(14) => \^mul_temp_7\(14),
P(13) => mul_temp_7_n_92,
P(12) => mul_temp_7_n_93,
P(11) => mul_temp_7_n_94,
P(10) => mul_temp_7_n_95,
P(9) => mul_temp_7_n_96,
P(8) => mul_temp_7_n_97,
P(7) => mul_temp_7_n_98,
P(6) => mul_temp_7_n_99,
P(5) => mul_temp_7_n_100,
P(4) => mul_temp_7_n_101,
P(3) => mul_temp_7_n_102,
P(2) => mul_temp_7_n_103,
P(1) => mul_temp_7_n_104,
P(0) => mul_temp_7_n_105,
PATTERNBDETECT => NLW_mul_temp_7_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_7_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_7_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_7_UNDERFLOW_UNCONNECTED
);
mul_temp_8: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_8_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[8]_7\(15),
B(16) => \weight_reg[8]_7\(15),
B(15 downto 0) => \weight_reg[8]_7\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_8_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_8_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_8_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_8_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_8_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_8_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_8_n_74,
P(30) => mul_temp_8_n_75,
P(29) => mul_temp_8_n_76,
P(28) => mul_temp_8_n_77,
P(27) => mul_temp_8_n_78,
P(26) => mul_temp_8_n_79,
P(25) => mul_temp_8_n_80,
P(24) => mul_temp_8_n_81,
P(23) => mul_temp_8_n_82,
P(22) => mul_temp_8_n_83,
P(21) => mul_temp_8_n_84,
P(20) => mul_temp_8_n_85,
P(19) => mul_temp_8_n_86,
P(18) => mul_temp_8_n_87,
P(17) => mul_temp_8_n_88,
P(16) => mul_temp_8_n_89,
P(15) => mul_temp_8_n_90,
P(14) => \^mul_temp_8\(14),
P(13) => mul_temp_8_n_92,
P(12) => mul_temp_8_n_93,
P(11) => mul_temp_8_n_94,
P(10) => mul_temp_8_n_95,
P(9) => mul_temp_8_n_96,
P(8) => mul_temp_8_n_97,
P(7) => mul_temp_8_n_98,
P(6) => mul_temp_8_n_99,
P(5) => mul_temp_8_n_100,
P(4) => mul_temp_8_n_101,
P(3) => mul_temp_8_n_102,
P(2) => mul_temp_8_n_103,
P(1) => mul_temp_8_n_104,
P(0) => mul_temp_8_n_105,
PATTERNBDETECT => NLW_mul_temp_8_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_8_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_8_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_8_UNDERFLOW_UNCONNECTED
);
mul_temp_9: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_9_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[9]_8\(15),
B(16) => \weight_reg[9]_8\(15),
B(15 downto 0) => \weight_reg[9]_8\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_9_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_9_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_9_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_9_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_9_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_9_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_9_n_74,
P(30) => mul_temp_9_n_75,
P(29) => mul_temp_9_n_76,
P(28) => mul_temp_9_n_77,
P(27) => mul_temp_9_n_78,
P(26) => mul_temp_9_n_79,
P(25) => mul_temp_9_n_80,
P(24) => mul_temp_9_n_81,
P(23) => mul_temp_9_n_82,
P(22) => mul_temp_9_n_83,
P(21) => mul_temp_9_n_84,
P(20) => mul_temp_9_n_85,
P(19) => mul_temp_9_n_86,
P(18) => mul_temp_9_n_87,
P(17) => mul_temp_9_n_88,
P(16) => mul_temp_9_n_89,
P(15) => mul_temp_9_n_90,
P(14) => \^mul_temp_9\(14),
P(13) => mul_temp_9_n_92,
P(12) => mul_temp_9_n_93,
P(11) => mul_temp_9_n_94,
P(10) => mul_temp_9_n_95,
P(9) => mul_temp_9_n_96,
P(8) => mul_temp_9_n_97,
P(7) => mul_temp_9_n_98,
P(6) => mul_temp_9_n_99,
P(5) => mul_temp_9_n_100,
P(4) => mul_temp_9_n_101,
P(3) => mul_temp_9_n_102,
P(2) => mul_temp_9_n_103,
P(1) => mul_temp_9_n_104,
P(0) => mul_temp_9_n_105,
PATTERNBDETECT => NLW_mul_temp_9_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_9_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_9_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_9_UNDERFLOW_UNCONNECTED
);
sub_temp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => sub_temp_carry_n_0,
CO(2) => sub_temp_carry_n_1,
CO(1) => sub_temp_carry_n_2,
CO(0) => sub_temp_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => Q(3 downto 0),
O(3 downto 0) => \^mul_temp_16\(3 downto 0),
S(3 downto 0) => \write_reg_d_k_reg[3]_0\(3 downto 0)
);
\sub_temp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => sub_temp_carry_n_0,
CO(3) => \sub_temp_carry__0_n_0\,
CO(2) => \sub_temp_carry__0_n_1\,
CO(1) => \sub_temp_carry__0_n_2\,
CO(0) => \sub_temp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(7 downto 4),
O(3 downto 0) => \^mul_temp_16\(7 downto 4),
S(3 downto 0) => \write_reg_d_k_reg[7]\(3 downto 0)
);
\sub_temp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \sub_temp_carry__0_n_0\,
CO(3) => \sub_temp_carry__1_n_0\,
CO(2) => \sub_temp_carry__1_n_1\,
CO(1) => \sub_temp_carry__1_n_2\,
CO(0) => \sub_temp_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(11 downto 8),
O(3 downto 0) => \^mul_temp_16\(11 downto 8),
S(3 downto 0) => \write_reg_d_k_reg[11]\(3 downto 0)
);
\sub_temp_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \sub_temp_carry__1_n_0\,
CO(3) => \NLW_sub_temp_carry__2_CO_UNCONNECTED\(3),
CO(2) => \sub_temp_carry__2_n_1\,
CO(1) => \sub_temp_carry__2_n_2\,
CO(0) => \sub_temp_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => Q(14 downto 12),
O(3 downto 0) => \^mul_temp_16\(15 downto 12),
S(3 downto 0) => S(3 downto 0)
);
\weight[0][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_88\,
I1 => \weight_reg[0]_15\(3),
O => \weight[0][0]_i_2_n_0\
);
\weight[0][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_89\,
I1 => \weight_reg[0]_15\(2),
O => \weight[0][0]_i_3_n_0\
);
\weight[0][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_90\,
I1 => \weight_reg[0]_15\(1),
O => \weight[0][0]_i_4_n_0\
);
\weight[0][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_91\,
I1 => \weight_reg[0]_15\(0),
O => \weight[0][0]_i_5_n_0\
);
\weight[0][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_76\,
I1 => \weight_reg[0]_15\(15),
O => \weight[0][12]_i_2_n_0\
);
\weight[0][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_77\,
I1 => \weight_reg[0]_15\(14),
O => \weight[0][12]_i_3_n_0\
);
\weight[0][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_78\,
I1 => \weight_reg[0]_15\(13),
O => \weight[0][12]_i_4_n_0\
);
\weight[0][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_79\,
I1 => \weight_reg[0]_15\(12),
O => \weight[0][12]_i_5_n_0\
);
\weight[0][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_84\,
I1 => \weight_reg[0]_15\(7),
O => \weight[0][4]_i_2_n_0\
);
\weight[0][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_85\,
I1 => \weight_reg[0]_15\(6),
O => \weight[0][4]_i_3_n_0\
);
\weight[0][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_86\,
I1 => \weight_reg[0]_15\(5),
O => \weight[0][4]_i_4_n_0\
);
\weight[0][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_87\,
I1 => \weight_reg[0]_15\(4),
O => \weight[0][4]_i_5_n_0\
);
\weight[0][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_80\,
I1 => \weight_reg[0]_15\(11),
O => \weight[0][8]_i_2_n_0\
);
\weight[0][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_81\,
I1 => \weight_reg[0]_15\(10),
O => \weight[0][8]_i_3_n_0\
);
\weight[0][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_82\,
I1 => \weight_reg[0]_15\(9),
O => \weight[0][8]_i_4_n_0\
);
\weight[0][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_83\,
I1 => \weight_reg[0]_15\(8),
O => \weight[0][8]_i_5_n_0\
);
\weight[10][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_88\,
I1 => \weight_reg[10]_9\(3),
O => \weight[10][0]_i_2_n_0\
);
\weight[10][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_89\,
I1 => \weight_reg[10]_9\(2),
O => \weight[10][0]_i_3_n_0\
);
\weight[10][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_90\,
I1 => \weight_reg[10]_9\(1),
O => \weight[10][0]_i_4_n_0\
);
\weight[10][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_91\,
I1 => \weight_reg[10]_9\(0),
O => \weight[10][0]_i_5_n_0\
);
\weight[10][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_76\,
I1 => \weight_reg[10]_9\(15),
O => \weight[10][12]_i_2_n_0\
);
\weight[10][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_77\,
I1 => \weight_reg[10]_9\(14),
O => \weight[10][12]_i_3_n_0\
);
\weight[10][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_78\,
I1 => \weight_reg[10]_9\(13),
O => \weight[10][12]_i_4_n_0\
);
\weight[10][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_79\,
I1 => \weight_reg[10]_9\(12),
O => \weight[10][12]_i_5_n_0\
);
\weight[10][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_84\,
I1 => \weight_reg[10]_9\(7),
O => \weight[10][4]_i_2_n_0\
);
\weight[10][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_85\,
I1 => \weight_reg[10]_9\(6),
O => \weight[10][4]_i_3_n_0\
);
\weight[10][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_86\,
I1 => \weight_reg[10]_9\(5),
O => \weight[10][4]_i_4_n_0\
);
\weight[10][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_87\,
I1 => \weight_reg[10]_9\(4),
O => \weight[10][4]_i_5_n_0\
);
\weight[10][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_80\,
I1 => \weight_reg[10]_9\(11),
O => \weight[10][8]_i_2_n_0\
);
\weight[10][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_81\,
I1 => \weight_reg[10]_9\(10),
O => \weight[10][8]_i_3_n_0\
);
\weight[10][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_82\,
I1 => \weight_reg[10]_9\(9),
O => \weight[10][8]_i_4_n_0\
);
\weight[10][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_83\,
I1 => \weight_reg[10]_9\(8),
O => \weight[10][8]_i_5_n_0\
);
\weight[11][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_88\,
I1 => \weight_reg[11]_10\(3),
O => \weight[11][0]_i_2_n_0\
);
\weight[11][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_89\,
I1 => \weight_reg[11]_10\(2),
O => \weight[11][0]_i_3_n_0\
);
\weight[11][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_90\,
I1 => \weight_reg[11]_10\(1),
O => \weight[11][0]_i_4_n_0\
);
\weight[11][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_91\,
I1 => \weight_reg[11]_10\(0),
O => \weight[11][0]_i_5_n_0\
);
\weight[11][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_76\,
I1 => \weight_reg[11]_10\(15),
O => \weight[11][12]_i_2_n_0\
);
\weight[11][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_77\,
I1 => \weight_reg[11]_10\(14),
O => \weight[11][12]_i_3_n_0\
);
\weight[11][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_78\,
I1 => \weight_reg[11]_10\(13),
O => \weight[11][12]_i_4_n_0\
);
\weight[11][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_79\,
I1 => \weight_reg[11]_10\(12),
O => \weight[11][12]_i_5_n_0\
);
\weight[11][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_84\,
I1 => \weight_reg[11]_10\(7),
O => \weight[11][4]_i_2_n_0\
);
\weight[11][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_85\,
I1 => \weight_reg[11]_10\(6),
O => \weight[11][4]_i_3_n_0\
);
\weight[11][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_86\,
I1 => \weight_reg[11]_10\(5),
O => \weight[11][4]_i_4_n_0\
);
\weight[11][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_87\,
I1 => \weight_reg[11]_10\(4),
O => \weight[11][4]_i_5_n_0\
);
\weight[11][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_80\,
I1 => \weight_reg[11]_10\(11),
O => \weight[11][8]_i_2_n_0\
);
\weight[11][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_81\,
I1 => \weight_reg[11]_10\(10),
O => \weight[11][8]_i_3_n_0\
);
\weight[11][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_82\,
I1 => \weight_reg[11]_10\(9),
O => \weight[11][8]_i_4_n_0\
);
\weight[11][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_83\,
I1 => \weight_reg[11]_10\(8),
O => \weight[11][8]_i_5_n_0\
);
\weight[12][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_88\,
I1 => \weight_reg[12]_11\(3),
O => \weight[12][0]_i_2_n_0\
);
\weight[12][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_89\,
I1 => \weight_reg[12]_11\(2),
O => \weight[12][0]_i_3_n_0\
);
\weight[12][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_90\,
I1 => \weight_reg[12]_11\(1),
O => \weight[12][0]_i_4_n_0\
);
\weight[12][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_91\,
I1 => \weight_reg[12]_11\(0),
O => \weight[12][0]_i_5_n_0\
);
\weight[12][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_76\,
I1 => \weight_reg[12]_11\(15),
O => \weight[12][12]_i_2_n_0\
);
\weight[12][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_77\,
I1 => \weight_reg[12]_11\(14),
O => \weight[12][12]_i_3_n_0\
);
\weight[12][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_78\,
I1 => \weight_reg[12]_11\(13),
O => \weight[12][12]_i_4_n_0\
);
\weight[12][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_79\,
I1 => \weight_reg[12]_11\(12),
O => \weight[12][12]_i_5_n_0\
);
\weight[12][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_84\,
I1 => \weight_reg[12]_11\(7),
O => \weight[12][4]_i_2_n_0\
);
\weight[12][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_85\,
I1 => \weight_reg[12]_11\(6),
O => \weight[12][4]_i_3_n_0\
);
\weight[12][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_86\,
I1 => \weight_reg[12]_11\(5),
O => \weight[12][4]_i_4_n_0\
);
\weight[12][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_87\,
I1 => \weight_reg[12]_11\(4),
O => \weight[12][4]_i_5_n_0\
);
\weight[12][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_80\,
I1 => \weight_reg[12]_11\(11),
O => \weight[12][8]_i_2_n_0\
);
\weight[12][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_81\,
I1 => \weight_reg[12]_11\(10),
O => \weight[12][8]_i_3_n_0\
);
\weight[12][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_82\,
I1 => \weight_reg[12]_11\(9),
O => \weight[12][8]_i_4_n_0\
);
\weight[12][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_83\,
I1 => \weight_reg[12]_11\(8),
O => \weight[12][8]_i_5_n_0\
);
\weight[13][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_88\,
I1 => \weight_reg[13]_12\(3),
O => \weight[13][0]_i_2_n_0\
);
\weight[13][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_89\,
I1 => \weight_reg[13]_12\(2),
O => \weight[13][0]_i_3_n_0\
);
\weight[13][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_90\,
I1 => \weight_reg[13]_12\(1),
O => \weight[13][0]_i_4_n_0\
);
\weight[13][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_91\,
I1 => \weight_reg[13]_12\(0),
O => \weight[13][0]_i_5_n_0\
);
\weight[13][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_76\,
I1 => \weight_reg[13]_12\(15),
O => \weight[13][12]_i_2_n_0\
);
\weight[13][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_77\,
I1 => \weight_reg[13]_12\(14),
O => \weight[13][12]_i_3_n_0\
);
\weight[13][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_78\,
I1 => \weight_reg[13]_12\(13),
O => \weight[13][12]_i_4_n_0\
);
\weight[13][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_79\,
I1 => \weight_reg[13]_12\(12),
O => \weight[13][12]_i_5_n_0\
);
\weight[13][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_84\,
I1 => \weight_reg[13]_12\(7),
O => \weight[13][4]_i_2_n_0\
);
\weight[13][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_85\,
I1 => \weight_reg[13]_12\(6),
O => \weight[13][4]_i_3_n_0\
);
\weight[13][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_86\,
I1 => \weight_reg[13]_12\(5),
O => \weight[13][4]_i_4_n_0\
);
\weight[13][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_87\,
I1 => \weight_reg[13]_12\(4),
O => \weight[13][4]_i_5_n_0\
);
\weight[13][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_80\,
I1 => \weight_reg[13]_12\(11),
O => \weight[13][8]_i_2_n_0\
);
\weight[13][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_81\,
I1 => \weight_reg[13]_12\(10),
O => \weight[13][8]_i_3_n_0\
);
\weight[13][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_82\,
I1 => \weight_reg[13]_12\(9),
O => \weight[13][8]_i_4_n_0\
);
\weight[13][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_83\,
I1 => \weight_reg[13]_12\(8),
O => \weight[13][8]_i_5_n_0\
);
\weight[14][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_88\,
I1 => \weight_reg[14]_13\(3),
O => \weight[14][0]_i_2_n_0\
);
\weight[14][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_89\,
I1 => \weight_reg[14]_13\(2),
O => \weight[14][0]_i_3_n_0\
);
\weight[14][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_90\,
I1 => \weight_reg[14]_13\(1),
O => \weight[14][0]_i_4_n_0\
);
\weight[14][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_91\,
I1 => \weight_reg[14]_13\(0),
O => \weight[14][0]_i_5_n_0\
);
\weight[14][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_76\,
I1 => \weight_reg[14]_13\(15),
O => \weight[14][12]_i_2_n_0\
);
\weight[14][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_77\,
I1 => \weight_reg[14]_13\(14),
O => \weight[14][12]_i_3_n_0\
);
\weight[14][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_78\,
I1 => \weight_reg[14]_13\(13),
O => \weight[14][12]_i_4_n_0\
);
\weight[14][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_79\,
I1 => \weight_reg[14]_13\(12),
O => \weight[14][12]_i_5_n_0\
);
\weight[14][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_84\,
I1 => \weight_reg[14]_13\(7),
O => \weight[14][4]_i_2_n_0\
);
\weight[14][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_85\,
I1 => \weight_reg[14]_13\(6),
O => \weight[14][4]_i_3_n_0\
);
\weight[14][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_86\,
I1 => \weight_reg[14]_13\(5),
O => \weight[14][4]_i_4_n_0\
);
\weight[14][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_87\,
I1 => \weight_reg[14]_13\(4),
O => \weight[14][4]_i_5_n_0\
);
\weight[14][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_80\,
I1 => \weight_reg[14]_13\(11),
O => \weight[14][8]_i_2_n_0\
);
\weight[14][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_81\,
I1 => \weight_reg[14]_13\(10),
O => \weight[14][8]_i_3_n_0\
);
\weight[14][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_82\,
I1 => \weight_reg[14]_13\(9),
O => \weight[14][8]_i_4_n_0\
);
\weight[14][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_83\,
I1 => \weight_reg[14]_13\(8),
O => \weight[14][8]_i_5_n_0\
);
\weight[15][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_88\,
I1 => \weight_reg[15]_14\(3),
O => \weight[15][0]_i_2_n_0\
);
\weight[15][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_89\,
I1 => \weight_reg[15]_14\(2),
O => \weight[15][0]_i_3_n_0\
);
\weight[15][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_90\,
I1 => \weight_reg[15]_14\(1),
O => \weight[15][0]_i_4_n_0\
);
\weight[15][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_91\,
I1 => \weight_reg[15]_14\(0),
O => \weight[15][0]_i_5_n_0\
);
\weight[15][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_76\,
I1 => \weight_reg[15]_14\(15),
O => \weight[15][12]_i_2_n_0\
);
\weight[15][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_77\,
I1 => \weight_reg[15]_14\(14),
O => \weight[15][12]_i_3_n_0\
);
\weight[15][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_78\,
I1 => \weight_reg[15]_14\(13),
O => \weight[15][12]_i_4_n_0\
);
\weight[15][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_79\,
I1 => \weight_reg[15]_14\(12),
O => \weight[15][12]_i_5_n_0\
);
\weight[15][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_84\,
I1 => \weight_reg[15]_14\(7),
O => \weight[15][4]_i_2_n_0\
);
\weight[15][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_85\,
I1 => \weight_reg[15]_14\(6),
O => \weight[15][4]_i_3_n_0\
);
\weight[15][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_86\,
I1 => \weight_reg[15]_14\(5),
O => \weight[15][4]_i_4_n_0\
);
\weight[15][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_87\,
I1 => \weight_reg[15]_14\(4),
O => \weight[15][4]_i_5_n_0\
);
\weight[15][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_80\,
I1 => \weight_reg[15]_14\(11),
O => \weight[15][8]_i_2_n_0\
);
\weight[15][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_81\,
I1 => \weight_reg[15]_14\(10),
O => \weight[15][8]_i_3_n_0\
);
\weight[15][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_82\,
I1 => \weight_reg[15]_14\(9),
O => \weight[15][8]_i_4_n_0\
);
\weight[15][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_83\,
I1 => \weight_reg[15]_14\(8),
O => \weight[15][8]_i_5_n_0\
);
\weight[1][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(3),
I1 => \weight_reg[1]_0\(3),
O => \weight[1][0]_i_2_n_0\
);
\weight[1][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(2),
I1 => \weight_reg[1]_0\(2),
O => \weight[1][0]_i_3_n_0\
);
\weight[1][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(1),
I1 => \weight_reg[1]_0\(1),
O => \weight[1][0]_i_4_n_0\
);
\weight[1][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(0),
I1 => \weight_reg[1]_0\(0),
O => \weight[1][0]_i_5_n_0\
);
\weight[1][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(15),
I1 => \weight_reg[1]_0\(15),
O => \weight[1][12]_i_2_n_0\
);
\weight[1][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(14),
I1 => \weight_reg[1]_0\(14),
O => \weight[1][12]_i_3_n_0\
);
\weight[1][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(13),
I1 => \weight_reg[1]_0\(13),
O => \weight[1][12]_i_4_n_0\
);
\weight[1][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(12),
I1 => \weight_reg[1]_0\(12),
O => \weight[1][12]_i_5_n_0\
);
\weight[1][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(7),
I1 => \weight_reg[1]_0\(7),
O => \weight[1][4]_i_2_n_0\
);
\weight[1][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(6),
I1 => \weight_reg[1]_0\(6),
O => \weight[1][4]_i_3_n_0\
);
\weight[1][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(5),
I1 => \weight_reg[1]_0\(5),
O => \weight[1][4]_i_4_n_0\
);
\weight[1][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(4),
I1 => \weight_reg[1]_0\(4),
O => \weight[1][4]_i_5_n_0\
);
\weight[1][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(11),
I1 => \weight_reg[1]_0\(11),
O => \weight[1][8]_i_2_n_0\
);
\weight[1][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(10),
I1 => \weight_reg[1]_0\(10),
O => \weight[1][8]_i_3_n_0\
);
\weight[1][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(9),
I1 => \weight_reg[1]_0\(9),
O => \weight[1][8]_i_4_n_0\
);
\weight[1][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(8),
I1 => \weight_reg[1]_0\(8),
O => \weight[1][8]_i_5_n_0\
);
\weight[2][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_88\,
I1 => \weight_reg[2]_1\(3),
O => \weight[2][0]_i_2_n_0\
);
\weight[2][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_89\,
I1 => \weight_reg[2]_1\(2),
O => \weight[2][0]_i_3_n_0\
);
\weight[2][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_90\,
I1 => \weight_reg[2]_1\(1),
O => \weight[2][0]_i_4_n_0\
);
\weight[2][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_91\,
I1 => \weight_reg[2]_1\(0),
O => \weight[2][0]_i_5_n_0\
);
\weight[2][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_76\,
I1 => \weight_reg[2]_1\(15),
O => \weight[2][12]_i_2_n_0\
);
\weight[2][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_77\,
I1 => \weight_reg[2]_1\(14),
O => \weight[2][12]_i_3_n_0\
);
\weight[2][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_78\,
I1 => \weight_reg[2]_1\(13),
O => \weight[2][12]_i_4_n_0\
);
\weight[2][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_79\,
I1 => \weight_reg[2]_1\(12),
O => \weight[2][12]_i_5_n_0\
);
\weight[2][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_84\,
I1 => \weight_reg[2]_1\(7),
O => \weight[2][4]_i_2_n_0\
);
\weight[2][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_85\,
I1 => \weight_reg[2]_1\(6),
O => \weight[2][4]_i_3_n_0\
);
\weight[2][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_86\,
I1 => \weight_reg[2]_1\(5),
O => \weight[2][4]_i_4_n_0\
);
\weight[2][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_87\,
I1 => \weight_reg[2]_1\(4),
O => \weight[2][4]_i_5_n_0\
);
\weight[2][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_80\,
I1 => \weight_reg[2]_1\(11),
O => \weight[2][8]_i_2_n_0\
);
\weight[2][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_81\,
I1 => \weight_reg[2]_1\(10),
O => \weight[2][8]_i_3_n_0\
);
\weight[2][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_82\,
I1 => \weight_reg[2]_1\(9),
O => \weight[2][8]_i_4_n_0\
);
\weight[2][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_83\,
I1 => \weight_reg[2]_1\(8),
O => \weight[2][8]_i_5_n_0\
);
\weight[3][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_88\,
I1 => \weight_reg[3]_2\(3),
O => \weight[3][0]_i_2_n_0\
);
\weight[3][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_89\,
I1 => \weight_reg[3]_2\(2),
O => \weight[3][0]_i_3_n_0\
);
\weight[3][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_90\,
I1 => \weight_reg[3]_2\(1),
O => \weight[3][0]_i_4_n_0\
);
\weight[3][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_91\,
I1 => \weight_reg[3]_2\(0),
O => \weight[3][0]_i_5_n_0\
);
\weight[3][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_76\,
I1 => \weight_reg[3]_2\(15),
O => \weight[3][12]_i_2_n_0\
);
\weight[3][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_77\,
I1 => \weight_reg[3]_2\(14),
O => \weight[3][12]_i_3_n_0\
);
\weight[3][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_78\,
I1 => \weight_reg[3]_2\(13),
O => \weight[3][12]_i_4_n_0\
);
\weight[3][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_79\,
I1 => \weight_reg[3]_2\(12),
O => \weight[3][12]_i_5_n_0\
);
\weight[3][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_84\,
I1 => \weight_reg[3]_2\(7),
O => \weight[3][4]_i_2_n_0\
);
\weight[3][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_85\,
I1 => \weight_reg[3]_2\(6),
O => \weight[3][4]_i_3_n_0\
);
\weight[3][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_86\,
I1 => \weight_reg[3]_2\(5),
O => \weight[3][4]_i_4_n_0\
);
\weight[3][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_87\,
I1 => \weight_reg[3]_2\(4),
O => \weight[3][4]_i_5_n_0\
);
\weight[3][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_80\,
I1 => \weight_reg[3]_2\(11),
O => \weight[3][8]_i_2_n_0\
);
\weight[3][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_81\,
I1 => \weight_reg[3]_2\(10),
O => \weight[3][8]_i_3_n_0\
);
\weight[3][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_82\,
I1 => \weight_reg[3]_2\(9),
O => \weight[3][8]_i_4_n_0\
);
\weight[3][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_83\,
I1 => \weight_reg[3]_2\(8),
O => \weight[3][8]_i_5_n_0\
);
\weight[4][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_88\,
I1 => \weight_reg[4]_3\(3),
O => \weight[4][0]_i_2_n_0\
);
\weight[4][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_89\,
I1 => \weight_reg[4]_3\(2),
O => \weight[4][0]_i_3_n_0\
);
\weight[4][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_90\,
I1 => \weight_reg[4]_3\(1),
O => \weight[4][0]_i_4_n_0\
);
\weight[4][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_91\,
I1 => \weight_reg[4]_3\(0),
O => \weight[4][0]_i_5_n_0\
);
\weight[4][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_76\,
I1 => \weight_reg[4]_3\(15),
O => \weight[4][12]_i_2_n_0\
);
\weight[4][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_77\,
I1 => \weight_reg[4]_3\(14),
O => \weight[4][12]_i_3_n_0\
);
\weight[4][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_78\,
I1 => \weight_reg[4]_3\(13),
O => \weight[4][12]_i_4_n_0\
);
\weight[4][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_79\,
I1 => \weight_reg[4]_3\(12),
O => \weight[4][12]_i_5_n_0\
);
\weight[4][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_84\,
I1 => \weight_reg[4]_3\(7),
O => \weight[4][4]_i_2_n_0\
);
\weight[4][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_85\,
I1 => \weight_reg[4]_3\(6),
O => \weight[4][4]_i_3_n_0\
);
\weight[4][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_86\,
I1 => \weight_reg[4]_3\(5),
O => \weight[4][4]_i_4_n_0\
);
\weight[4][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_87\,
I1 => \weight_reg[4]_3\(4),
O => \weight[4][4]_i_5_n_0\
);
\weight[4][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_80\,
I1 => \weight_reg[4]_3\(11),
O => \weight[4][8]_i_2_n_0\
);
\weight[4][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_81\,
I1 => \weight_reg[4]_3\(10),
O => \weight[4][8]_i_3_n_0\
);
\weight[4][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_82\,
I1 => \weight_reg[4]_3\(9),
O => \weight[4][8]_i_4_n_0\
);
\weight[4][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_83\,
I1 => \weight_reg[4]_3\(8),
O => \weight[4][8]_i_5_n_0\
);
\weight[5][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_88\,
I1 => \weight_reg[5]_4\(3),
O => \weight[5][0]_i_2_n_0\
);
\weight[5][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_89\,
I1 => \weight_reg[5]_4\(2),
O => \weight[5][0]_i_3_n_0\
);
\weight[5][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_90\,
I1 => \weight_reg[5]_4\(1),
O => \weight[5][0]_i_4_n_0\
);
\weight[5][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_91\,
I1 => \weight_reg[5]_4\(0),
O => \weight[5][0]_i_5_n_0\
);
\weight[5][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_76\,
I1 => \weight_reg[5]_4\(15),
O => \weight[5][12]_i_2_n_0\
);
\weight[5][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_77\,
I1 => \weight_reg[5]_4\(14),
O => \weight[5][12]_i_3_n_0\
);
\weight[5][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_78\,
I1 => \weight_reg[5]_4\(13),
O => \weight[5][12]_i_4_n_0\
);
\weight[5][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_79\,
I1 => \weight_reg[5]_4\(12),
O => \weight[5][12]_i_5_n_0\
);
\weight[5][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_84\,
I1 => \weight_reg[5]_4\(7),
O => \weight[5][4]_i_2_n_0\
);
\weight[5][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_85\,
I1 => \weight_reg[5]_4\(6),
O => \weight[5][4]_i_3_n_0\
);
\weight[5][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_86\,
I1 => \weight_reg[5]_4\(5),
O => \weight[5][4]_i_4_n_0\
);
\weight[5][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_87\,
I1 => \weight_reg[5]_4\(4),
O => \weight[5][4]_i_5_n_0\
);
\weight[5][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_80\,
I1 => \weight_reg[5]_4\(11),
O => \weight[5][8]_i_2_n_0\
);
\weight[5][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_81\,
I1 => \weight_reg[5]_4\(10),
O => \weight[5][8]_i_3_n_0\
);
\weight[5][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_82\,
I1 => \weight_reg[5]_4\(9),
O => \weight[5][8]_i_4_n_0\
);
\weight[5][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_83\,
I1 => \weight_reg[5]_4\(8),
O => \weight[5][8]_i_5_n_0\
);
\weight[6][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_88\,
I1 => \weight_reg[6]_5\(3),
O => \weight[6][0]_i_2_n_0\
);
\weight[6][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_89\,
I1 => \weight_reg[6]_5\(2),
O => \weight[6][0]_i_3_n_0\
);
\weight[6][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_90\,
I1 => \weight_reg[6]_5\(1),
O => \weight[6][0]_i_4_n_0\
);
\weight[6][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_91\,
I1 => \weight_reg[6]_5\(0),
O => \weight[6][0]_i_5_n_0\
);
\weight[6][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_76\,
I1 => \weight_reg[6]_5\(15),
O => \weight[6][12]_i_2_n_0\
);
\weight[6][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_77\,
I1 => \weight_reg[6]_5\(14),
O => \weight[6][12]_i_3_n_0\
);
\weight[6][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_78\,
I1 => \weight_reg[6]_5\(13),
O => \weight[6][12]_i_4_n_0\
);
\weight[6][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_79\,
I1 => \weight_reg[6]_5\(12),
O => \weight[6][12]_i_5_n_0\
);
\weight[6][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_84\,
I1 => \weight_reg[6]_5\(7),
O => \weight[6][4]_i_2_n_0\
);
\weight[6][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_85\,
I1 => \weight_reg[6]_5\(6),
O => \weight[6][4]_i_3_n_0\
);
\weight[6][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_86\,
I1 => \weight_reg[6]_5\(5),
O => \weight[6][4]_i_4_n_0\
);
\weight[6][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_87\,
I1 => \weight_reg[6]_5\(4),
O => \weight[6][4]_i_5_n_0\
);
\weight[6][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_80\,
I1 => \weight_reg[6]_5\(11),
O => \weight[6][8]_i_2_n_0\
);
\weight[6][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_81\,
I1 => \weight_reg[6]_5\(10),
O => \weight[6][8]_i_3_n_0\
);
\weight[6][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_82\,
I1 => \weight_reg[6]_5\(9),
O => \weight[6][8]_i_4_n_0\
);
\weight[6][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_83\,
I1 => \weight_reg[6]_5\(8),
O => \weight[6][8]_i_5_n_0\
);
\weight[7][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_88\,
I1 => \weight_reg[7]_6\(3),
O => \weight[7][0]_i_2_n_0\
);
\weight[7][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_89\,
I1 => \weight_reg[7]_6\(2),
O => \weight[7][0]_i_3_n_0\
);
\weight[7][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_90\,
I1 => \weight_reg[7]_6\(1),
O => \weight[7][0]_i_4_n_0\
);
\weight[7][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_91\,
I1 => \weight_reg[7]_6\(0),
O => \weight[7][0]_i_5_n_0\
);
\weight[7][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_76\,
I1 => \weight_reg[7]_6\(15),
O => \weight[7][12]_i_2_n_0\
);
\weight[7][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_77\,
I1 => \weight_reg[7]_6\(14),
O => \weight[7][12]_i_3_n_0\
);
\weight[7][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_78\,
I1 => \weight_reg[7]_6\(13),
O => \weight[7][12]_i_4_n_0\
);
\weight[7][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_79\,
I1 => \weight_reg[7]_6\(12),
O => \weight[7][12]_i_5_n_0\
);
\weight[7][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_84\,
I1 => \weight_reg[7]_6\(7),
O => \weight[7][4]_i_2_n_0\
);
\weight[7][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_85\,
I1 => \weight_reg[7]_6\(6),
O => \weight[7][4]_i_3_n_0\
);
\weight[7][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_86\,
I1 => \weight_reg[7]_6\(5),
O => \weight[7][4]_i_4_n_0\
);
\weight[7][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_87\,
I1 => \weight_reg[7]_6\(4),
O => \weight[7][4]_i_5_n_0\
);
\weight[7][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_80\,
I1 => \weight_reg[7]_6\(11),
O => \weight[7][8]_i_2_n_0\
);
\weight[7][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_81\,
I1 => \weight_reg[7]_6\(10),
O => \weight[7][8]_i_3_n_0\
);
\weight[7][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_82\,
I1 => \weight_reg[7]_6\(9),
O => \weight[7][8]_i_4_n_0\
);
\weight[7][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_83\,
I1 => \weight_reg[7]_6\(8),
O => \weight[7][8]_i_5_n_0\
);
\weight[8][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_88\,
I1 => \weight_reg[8]_7\(3),
O => \weight[8][0]_i_2_n_0\
);
\weight[8][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_89\,
I1 => \weight_reg[8]_7\(2),
O => \weight[8][0]_i_3_n_0\
);
\weight[8][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_90\,
I1 => \weight_reg[8]_7\(1),
O => \weight[8][0]_i_4_n_0\
);
\weight[8][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_91\,
I1 => \weight_reg[8]_7\(0),
O => \weight[8][0]_i_5_n_0\
);
\weight[8][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_76\,
I1 => \weight_reg[8]_7\(15),
O => \weight[8][12]_i_2_n_0\
);
\weight[8][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_77\,
I1 => \weight_reg[8]_7\(14),
O => \weight[8][12]_i_3_n_0\
);
\weight[8][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_78\,
I1 => \weight_reg[8]_7\(13),
O => \weight[8][12]_i_4_n_0\
);
\weight[8][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_79\,
I1 => \weight_reg[8]_7\(12),
O => \weight[8][12]_i_5_n_0\
);
\weight[8][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_84\,
I1 => \weight_reg[8]_7\(7),
O => \weight[8][4]_i_2_n_0\
);
\weight[8][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_85\,
I1 => \weight_reg[8]_7\(6),
O => \weight[8][4]_i_3_n_0\
);
\weight[8][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_86\,
I1 => \weight_reg[8]_7\(5),
O => \weight[8][4]_i_4_n_0\
);
\weight[8][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_87\,
I1 => \weight_reg[8]_7\(4),
O => \weight[8][4]_i_5_n_0\
);
\weight[8][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_80\,
I1 => \weight_reg[8]_7\(11),
O => \weight[8][8]_i_2_n_0\
);
\weight[8][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_81\,
I1 => \weight_reg[8]_7\(10),
O => \weight[8][8]_i_3_n_0\
);
\weight[8][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_82\,
I1 => \weight_reg[8]_7\(9),
O => \weight[8][8]_i_4_n_0\
);
\weight[8][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_83\,
I1 => \weight_reg[8]_7\(8),
O => \weight[8][8]_i_5_n_0\
);
\weight[9][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_88\,
I1 => \weight_reg[9]_8\(3),
O => \weight[9][0]_i_2_n_0\
);
\weight[9][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_89\,
I1 => \weight_reg[9]_8\(2),
O => \weight[9][0]_i_3_n_0\
);
\weight[9][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_90\,
I1 => \weight_reg[9]_8\(1),
O => \weight[9][0]_i_4_n_0\
);
\weight[9][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_91\,
I1 => \weight_reg[9]_8\(0),
O => \weight[9][0]_i_5_n_0\
);
\weight[9][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_76\,
I1 => \weight_reg[9]_8\(15),
O => \weight[9][12]_i_2_n_0\
);
\weight[9][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_77\,
I1 => \weight_reg[9]_8\(14),
O => \weight[9][12]_i_3_n_0\
);
\weight[9][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_78\,
I1 => \weight_reg[9]_8\(13),
O => \weight[9][12]_i_4_n_0\
);
\weight[9][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_79\,
I1 => \weight_reg[9]_8\(12),
O => \weight[9][12]_i_5_n_0\
);
\weight[9][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_84\,
I1 => \weight_reg[9]_8\(7),
O => \weight[9][4]_i_2_n_0\
);
\weight[9][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_85\,
I1 => \weight_reg[9]_8\(6),
O => \weight[9][4]_i_3_n_0\
);
\weight[9][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_86\,
I1 => \weight_reg[9]_8\(5),
O => \weight[9][4]_i_4_n_0\
);
\weight[9][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_87\,
I1 => \weight_reg[9]_8\(4),
O => \weight[9][4]_i_5_n_0\
);
\weight[9][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_80\,
I1 => \weight_reg[9]_8\(11),
O => \weight[9][8]_i_2_n_0\
);
\weight[9][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_81\,
I1 => \weight_reg[9]_8\(10),
O => \weight[9][8]_i_3_n_0\
);
\weight[9][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_82\,
I1 => \weight_reg[9]_8\(9),
O => \weight[9][8]_i_4_n_0\
);
\weight[9][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_83\,
I1 => \weight_reg[9]_8\(8),
O => \weight[9][8]_i_5_n_0\
);
\weight_reg[0][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_7\,
Q => \weight_reg[0]_15\(0)
);
\weight_reg[0][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[0][0]_i_1_n_0\,
CO(2) => \weight_reg[0][0]_i_1_n_1\,
CO(1) => \weight_reg[0][0]_i_1_n_2\,
CO(0) => \weight_reg[0][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__29_n_88\,
DI(2) => \ARG__29_n_89\,
DI(1) => \ARG__29_n_90\,
DI(0) => \ARG__29_n_91\,
O(3) => \weight_reg[0][0]_i_1_n_4\,
O(2) => \weight_reg[0][0]_i_1_n_5\,
O(1) => \weight_reg[0][0]_i_1_n_6\,
O(0) => \weight_reg[0][0]_i_1_n_7\,
S(3) => \weight[0][0]_i_2_n_0\,
S(2) => \weight[0][0]_i_3_n_0\,
S(1) => \weight[0][0]_i_4_n_0\,
S(0) => \weight[0][0]_i_5_n_0\
);
\weight_reg[0][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_5\,
Q => \weight_reg[0]_15\(10)
);
\weight_reg[0][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_4\,
Q => \weight_reg[0]_15\(11)
);
\weight_reg[0][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_7\,
Q => \weight_reg[0]_15\(12)
);
\weight_reg[0][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[0][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[0][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[0][12]_i_1_n_1\,
CO(1) => \weight_reg[0][12]_i_1_n_2\,
CO(0) => \weight_reg[0][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__29_n_77\,
DI(1) => \ARG__29_n_78\,
DI(0) => \ARG__29_n_79\,
O(3) => \weight_reg[0][12]_i_1_n_4\,
O(2) => \weight_reg[0][12]_i_1_n_5\,
O(1) => \weight_reg[0][12]_i_1_n_6\,
O(0) => \weight_reg[0][12]_i_1_n_7\,
S(3) => \weight[0][12]_i_2_n_0\,
S(2) => \weight[0][12]_i_3_n_0\,
S(1) => \weight[0][12]_i_4_n_0\,
S(0) => \weight[0][12]_i_5_n_0\
);
\weight_reg[0][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_6\,
Q => \weight_reg[0]_15\(13)
);
\weight_reg[0][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_5\,
Q => \weight_reg[0]_15\(14)
);
\weight_reg[0][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_4\,
Q => \weight_reg[0]_15\(15)
);
\weight_reg[0][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_6\,
Q => \weight_reg[0]_15\(1)
);
\weight_reg[0][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_5\,
Q => \weight_reg[0]_15\(2)
);
\weight_reg[0][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_4\,
Q => \weight_reg[0]_15\(3)
);
\weight_reg[0][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_7\,
Q => \weight_reg[0]_15\(4)
);
\weight_reg[0][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[0][0]_i_1_n_0\,
CO(3) => \weight_reg[0][4]_i_1_n_0\,
CO(2) => \weight_reg[0][4]_i_1_n_1\,
CO(1) => \weight_reg[0][4]_i_1_n_2\,
CO(0) => \weight_reg[0][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__29_n_84\,
DI(2) => \ARG__29_n_85\,
DI(1) => \ARG__29_n_86\,
DI(0) => \ARG__29_n_87\,
O(3) => \weight_reg[0][4]_i_1_n_4\,
O(2) => \weight_reg[0][4]_i_1_n_5\,
O(1) => \weight_reg[0][4]_i_1_n_6\,
O(0) => \weight_reg[0][4]_i_1_n_7\,
S(3) => \weight[0][4]_i_2_n_0\,
S(2) => \weight[0][4]_i_3_n_0\,
S(1) => \weight[0][4]_i_4_n_0\,
S(0) => \weight[0][4]_i_5_n_0\
);
\weight_reg[0][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_6\,
Q => \weight_reg[0]_15\(5)
);
\weight_reg[0][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_5\,
Q => \weight_reg[0]_15\(6)
);
\weight_reg[0][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_4\,
Q => \weight_reg[0]_15\(7)
);
\weight_reg[0][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_7\,
Q => \weight_reg[0]_15\(8)
);
\weight_reg[0][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[0][4]_i_1_n_0\,
CO(3) => \weight_reg[0][8]_i_1_n_0\,
CO(2) => \weight_reg[0][8]_i_1_n_1\,
CO(1) => \weight_reg[0][8]_i_1_n_2\,
CO(0) => \weight_reg[0][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__29_n_80\,
DI(2) => \ARG__29_n_81\,
DI(1) => \ARG__29_n_82\,
DI(0) => \ARG__29_n_83\,
O(3) => \weight_reg[0][8]_i_1_n_4\,
O(2) => \weight_reg[0][8]_i_1_n_5\,
O(1) => \weight_reg[0][8]_i_1_n_6\,
O(0) => \weight_reg[0][8]_i_1_n_7\,
S(3) => \weight[0][8]_i_2_n_0\,
S(2) => \weight[0][8]_i_3_n_0\,
S(1) => \weight[0][8]_i_4_n_0\,
S(0) => \weight[0][8]_i_5_n_0\
);
\weight_reg[0][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_6\,
Q => \weight_reg[0]_15\(9)
);
\weight_reg[10][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_7\,
Q => \weight_reg[10]_9\(0)
);
\weight_reg[10][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[10][0]_i_1_n_0\,
CO(2) => \weight_reg[10][0]_i_1_n_1\,
CO(1) => \weight_reg[10][0]_i_1_n_2\,
CO(0) => \weight_reg[10][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__17_n_88\,
DI(2) => \ARG__17_n_89\,
DI(1) => \ARG__17_n_90\,
DI(0) => \ARG__17_n_91\,
O(3) => \weight_reg[10][0]_i_1_n_4\,
O(2) => \weight_reg[10][0]_i_1_n_5\,
O(1) => \weight_reg[10][0]_i_1_n_6\,
O(0) => \weight_reg[10][0]_i_1_n_7\,
S(3) => \weight[10][0]_i_2_n_0\,
S(2) => \weight[10][0]_i_3_n_0\,
S(1) => \weight[10][0]_i_4_n_0\,
S(0) => \weight[10][0]_i_5_n_0\
);
\weight_reg[10][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_5\,
Q => \weight_reg[10]_9\(10)
);
\weight_reg[10][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_4\,
Q => \weight_reg[10]_9\(11)
);
\weight_reg[10][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_7\,
Q => \weight_reg[10]_9\(12)
);
\weight_reg[10][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[10][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[10][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[10][12]_i_1_n_1\,
CO(1) => \weight_reg[10][12]_i_1_n_2\,
CO(0) => \weight_reg[10][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__17_n_77\,
DI(1) => \ARG__17_n_78\,
DI(0) => \ARG__17_n_79\,
O(3) => \weight_reg[10][12]_i_1_n_4\,
O(2) => \weight_reg[10][12]_i_1_n_5\,
O(1) => \weight_reg[10][12]_i_1_n_6\,
O(0) => \weight_reg[10][12]_i_1_n_7\,
S(3) => \weight[10][12]_i_2_n_0\,
S(2) => \weight[10][12]_i_3_n_0\,
S(1) => \weight[10][12]_i_4_n_0\,
S(0) => \weight[10][12]_i_5_n_0\
);
\weight_reg[10][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_6\,
Q => \weight_reg[10]_9\(13)
);
\weight_reg[10][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_5\,
Q => \weight_reg[10]_9\(14)
);
\weight_reg[10][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_4\,
Q => \weight_reg[10]_9\(15)
);
\weight_reg[10][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_6\,
Q => \weight_reg[10]_9\(1)
);
\weight_reg[10][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_5\,
Q => \weight_reg[10]_9\(2)
);
\weight_reg[10][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_4\,
Q => \weight_reg[10]_9\(3)
);
\weight_reg[10][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_7\,
Q => \weight_reg[10]_9\(4)
);
\weight_reg[10][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[10][0]_i_1_n_0\,
CO(3) => \weight_reg[10][4]_i_1_n_0\,
CO(2) => \weight_reg[10][4]_i_1_n_1\,
CO(1) => \weight_reg[10][4]_i_1_n_2\,
CO(0) => \weight_reg[10][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__17_n_84\,
DI(2) => \ARG__17_n_85\,
DI(1) => \ARG__17_n_86\,
DI(0) => \ARG__17_n_87\,
O(3) => \weight_reg[10][4]_i_1_n_4\,
O(2) => \weight_reg[10][4]_i_1_n_5\,
O(1) => \weight_reg[10][4]_i_1_n_6\,
O(0) => \weight_reg[10][4]_i_1_n_7\,
S(3) => \weight[10][4]_i_2_n_0\,
S(2) => \weight[10][4]_i_3_n_0\,
S(1) => \weight[10][4]_i_4_n_0\,
S(0) => \weight[10][4]_i_5_n_0\
);
\weight_reg[10][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_6\,
Q => \weight_reg[10]_9\(5)
);
\weight_reg[10][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_5\,
Q => \weight_reg[10]_9\(6)
);
\weight_reg[10][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_4\,
Q => \weight_reg[10]_9\(7)
);
\weight_reg[10][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_7\,
Q => \weight_reg[10]_9\(8)
);
\weight_reg[10][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[10][4]_i_1_n_0\,
CO(3) => \weight_reg[10][8]_i_1_n_0\,
CO(2) => \weight_reg[10][8]_i_1_n_1\,
CO(1) => \weight_reg[10][8]_i_1_n_2\,
CO(0) => \weight_reg[10][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__17_n_80\,
DI(2) => \ARG__17_n_81\,
DI(1) => \ARG__17_n_82\,
DI(0) => \ARG__17_n_83\,
O(3) => \weight_reg[10][8]_i_1_n_4\,
O(2) => \weight_reg[10][8]_i_1_n_5\,
O(1) => \weight_reg[10][8]_i_1_n_6\,
O(0) => \weight_reg[10][8]_i_1_n_7\,
S(3) => \weight[10][8]_i_2_n_0\,
S(2) => \weight[10][8]_i_3_n_0\,
S(1) => \weight[10][8]_i_4_n_0\,
S(0) => \weight[10][8]_i_5_n_0\
);
\weight_reg[10][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_6\,
Q => \weight_reg[10]_9\(9)
);
\weight_reg[11][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_7\,
Q => \weight_reg[11]_10\(0)
);
\weight_reg[11][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[11][0]_i_1_n_0\,
CO(2) => \weight_reg[11][0]_i_1_n_1\,
CO(1) => \weight_reg[11][0]_i_1_n_2\,
CO(0) => \weight_reg[11][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__19_n_88\,
DI(2) => \ARG__19_n_89\,
DI(1) => \ARG__19_n_90\,
DI(0) => \ARG__19_n_91\,
O(3) => \weight_reg[11][0]_i_1_n_4\,
O(2) => \weight_reg[11][0]_i_1_n_5\,
O(1) => \weight_reg[11][0]_i_1_n_6\,
O(0) => \weight_reg[11][0]_i_1_n_7\,
S(3) => \weight[11][0]_i_2_n_0\,
S(2) => \weight[11][0]_i_3_n_0\,
S(1) => \weight[11][0]_i_4_n_0\,
S(0) => \weight[11][0]_i_5_n_0\
);
\weight_reg[11][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_5\,
Q => \weight_reg[11]_10\(10)
);
\weight_reg[11][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_4\,
Q => \weight_reg[11]_10\(11)
);
\weight_reg[11][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_7\,
Q => \weight_reg[11]_10\(12)
);
\weight_reg[11][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[11][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[11][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[11][12]_i_1_n_1\,
CO(1) => \weight_reg[11][12]_i_1_n_2\,
CO(0) => \weight_reg[11][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__19_n_77\,
DI(1) => \ARG__19_n_78\,
DI(0) => \ARG__19_n_79\,
O(3) => \weight_reg[11][12]_i_1_n_4\,
O(2) => \weight_reg[11][12]_i_1_n_5\,
O(1) => \weight_reg[11][12]_i_1_n_6\,
O(0) => \weight_reg[11][12]_i_1_n_7\,
S(3) => \weight[11][12]_i_2_n_0\,
S(2) => \weight[11][12]_i_3_n_0\,
S(1) => \weight[11][12]_i_4_n_0\,
S(0) => \weight[11][12]_i_5_n_0\
);
\weight_reg[11][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_6\,
Q => \weight_reg[11]_10\(13)
);
\weight_reg[11][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_5\,
Q => \weight_reg[11]_10\(14)
);
\weight_reg[11][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_4\,
Q => \weight_reg[11]_10\(15)
);
\weight_reg[11][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_6\,
Q => \weight_reg[11]_10\(1)
);
\weight_reg[11][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_5\,
Q => \weight_reg[11]_10\(2)
);
\weight_reg[11][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_4\,
Q => \weight_reg[11]_10\(3)
);
\weight_reg[11][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_7\,
Q => \weight_reg[11]_10\(4)
);
\weight_reg[11][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[11][0]_i_1_n_0\,
CO(3) => \weight_reg[11][4]_i_1_n_0\,
CO(2) => \weight_reg[11][4]_i_1_n_1\,
CO(1) => \weight_reg[11][4]_i_1_n_2\,
CO(0) => \weight_reg[11][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__19_n_84\,
DI(2) => \ARG__19_n_85\,
DI(1) => \ARG__19_n_86\,
DI(0) => \ARG__19_n_87\,
O(3) => \weight_reg[11][4]_i_1_n_4\,
O(2) => \weight_reg[11][4]_i_1_n_5\,
O(1) => \weight_reg[11][4]_i_1_n_6\,
O(0) => \weight_reg[11][4]_i_1_n_7\,
S(3) => \weight[11][4]_i_2_n_0\,
S(2) => \weight[11][4]_i_3_n_0\,
S(1) => \weight[11][4]_i_4_n_0\,
S(0) => \weight[11][4]_i_5_n_0\
);
\weight_reg[11][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_6\,
Q => \weight_reg[11]_10\(5)
);
\weight_reg[11][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_5\,
Q => \weight_reg[11]_10\(6)
);
\weight_reg[11][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_4\,
Q => \weight_reg[11]_10\(7)
);
\weight_reg[11][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_7\,
Q => \weight_reg[11]_10\(8)
);
\weight_reg[11][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[11][4]_i_1_n_0\,
CO(3) => \weight_reg[11][8]_i_1_n_0\,
CO(2) => \weight_reg[11][8]_i_1_n_1\,
CO(1) => \weight_reg[11][8]_i_1_n_2\,
CO(0) => \weight_reg[11][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__19_n_80\,
DI(2) => \ARG__19_n_81\,
DI(1) => \ARG__19_n_82\,
DI(0) => \ARG__19_n_83\,
O(3) => \weight_reg[11][8]_i_1_n_4\,
O(2) => \weight_reg[11][8]_i_1_n_5\,
O(1) => \weight_reg[11][8]_i_1_n_6\,
O(0) => \weight_reg[11][8]_i_1_n_7\,
S(3) => \weight[11][8]_i_2_n_0\,
S(2) => \weight[11][8]_i_3_n_0\,
S(1) => \weight[11][8]_i_4_n_0\,
S(0) => \weight[11][8]_i_5_n_0\
);
\weight_reg[11][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_6\,
Q => \weight_reg[11]_10\(9)
);
\weight_reg[12][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_7\,
Q => \weight_reg[12]_11\(0)
);
\weight_reg[12][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[12][0]_i_1_n_0\,
CO(2) => \weight_reg[12][0]_i_1_n_1\,
CO(1) => \weight_reg[12][0]_i_1_n_2\,
CO(0) => \weight_reg[12][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__21_n_88\,
DI(2) => \ARG__21_n_89\,
DI(1) => \ARG__21_n_90\,
DI(0) => \ARG__21_n_91\,
O(3) => \weight_reg[12][0]_i_1_n_4\,
O(2) => \weight_reg[12][0]_i_1_n_5\,
O(1) => \weight_reg[12][0]_i_1_n_6\,
O(0) => \weight_reg[12][0]_i_1_n_7\,
S(3) => \weight[12][0]_i_2_n_0\,
S(2) => \weight[12][0]_i_3_n_0\,
S(1) => \weight[12][0]_i_4_n_0\,
S(0) => \weight[12][0]_i_5_n_0\
);
\weight_reg[12][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_5\,
Q => \weight_reg[12]_11\(10)
);
\weight_reg[12][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_4\,
Q => \weight_reg[12]_11\(11)
);
\weight_reg[12][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_7\,
Q => \weight_reg[12]_11\(12)
);
\weight_reg[12][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[12][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[12][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[12][12]_i_1_n_1\,
CO(1) => \weight_reg[12][12]_i_1_n_2\,
CO(0) => \weight_reg[12][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__21_n_77\,
DI(1) => \ARG__21_n_78\,
DI(0) => \ARG__21_n_79\,
O(3) => \weight_reg[12][12]_i_1_n_4\,
O(2) => \weight_reg[12][12]_i_1_n_5\,
O(1) => \weight_reg[12][12]_i_1_n_6\,
O(0) => \weight_reg[12][12]_i_1_n_7\,
S(3) => \weight[12][12]_i_2_n_0\,
S(2) => \weight[12][12]_i_3_n_0\,
S(1) => \weight[12][12]_i_4_n_0\,
S(0) => \weight[12][12]_i_5_n_0\
);
\weight_reg[12][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_6\,
Q => \weight_reg[12]_11\(13)
);
\weight_reg[12][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_5\,
Q => \weight_reg[12]_11\(14)
);
\weight_reg[12][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_4\,
Q => \weight_reg[12]_11\(15)
);
\weight_reg[12][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_6\,
Q => \weight_reg[12]_11\(1)
);
\weight_reg[12][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_5\,
Q => \weight_reg[12]_11\(2)
);
\weight_reg[12][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_4\,
Q => \weight_reg[12]_11\(3)
);
\weight_reg[12][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_7\,
Q => \weight_reg[12]_11\(4)
);
\weight_reg[12][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[12][0]_i_1_n_0\,
CO(3) => \weight_reg[12][4]_i_1_n_0\,
CO(2) => \weight_reg[12][4]_i_1_n_1\,
CO(1) => \weight_reg[12][4]_i_1_n_2\,
CO(0) => \weight_reg[12][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__21_n_84\,
DI(2) => \ARG__21_n_85\,
DI(1) => \ARG__21_n_86\,
DI(0) => \ARG__21_n_87\,
O(3) => \weight_reg[12][4]_i_1_n_4\,
O(2) => \weight_reg[12][4]_i_1_n_5\,
O(1) => \weight_reg[12][4]_i_1_n_6\,
O(0) => \weight_reg[12][4]_i_1_n_7\,
S(3) => \weight[12][4]_i_2_n_0\,
S(2) => \weight[12][4]_i_3_n_0\,
S(1) => \weight[12][4]_i_4_n_0\,
S(0) => \weight[12][4]_i_5_n_0\
);
\weight_reg[12][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_6\,
Q => \weight_reg[12]_11\(5)
);
\weight_reg[12][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_5\,
Q => \weight_reg[12]_11\(6)
);
\weight_reg[12][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_4\,
Q => \weight_reg[12]_11\(7)
);
\weight_reg[12][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_7\,
Q => \weight_reg[12]_11\(8)
);
\weight_reg[12][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[12][4]_i_1_n_0\,
CO(3) => \weight_reg[12][8]_i_1_n_0\,
CO(2) => \weight_reg[12][8]_i_1_n_1\,
CO(1) => \weight_reg[12][8]_i_1_n_2\,
CO(0) => \weight_reg[12][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__21_n_80\,
DI(2) => \ARG__21_n_81\,
DI(1) => \ARG__21_n_82\,
DI(0) => \ARG__21_n_83\,
O(3) => \weight_reg[12][8]_i_1_n_4\,
O(2) => \weight_reg[12][8]_i_1_n_5\,
O(1) => \weight_reg[12][8]_i_1_n_6\,
O(0) => \weight_reg[12][8]_i_1_n_7\,
S(3) => \weight[12][8]_i_2_n_0\,
S(2) => \weight[12][8]_i_3_n_0\,
S(1) => \weight[12][8]_i_4_n_0\,
S(0) => \weight[12][8]_i_5_n_0\
);
\weight_reg[12][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_6\,
Q => \weight_reg[12]_11\(9)
);
\weight_reg[13][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_7\,
Q => \weight_reg[13]_12\(0)
);
\weight_reg[13][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[13][0]_i_1_n_0\,
CO(2) => \weight_reg[13][0]_i_1_n_1\,
CO(1) => \weight_reg[13][0]_i_1_n_2\,
CO(0) => \weight_reg[13][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__23_n_88\,
DI(2) => \ARG__23_n_89\,
DI(1) => \ARG__23_n_90\,
DI(0) => \ARG__23_n_91\,
O(3) => \weight_reg[13][0]_i_1_n_4\,
O(2) => \weight_reg[13][0]_i_1_n_5\,
O(1) => \weight_reg[13][0]_i_1_n_6\,
O(0) => \weight_reg[13][0]_i_1_n_7\,
S(3) => \weight[13][0]_i_2_n_0\,
S(2) => \weight[13][0]_i_3_n_0\,
S(1) => \weight[13][0]_i_4_n_0\,
S(0) => \weight[13][0]_i_5_n_0\
);
\weight_reg[13][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_5\,
Q => \weight_reg[13]_12\(10)
);
\weight_reg[13][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_4\,
Q => \weight_reg[13]_12\(11)
);
\weight_reg[13][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_7\,
Q => \weight_reg[13]_12\(12)
);
\weight_reg[13][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[13][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[13][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[13][12]_i_1_n_1\,
CO(1) => \weight_reg[13][12]_i_1_n_2\,
CO(0) => \weight_reg[13][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__23_n_77\,
DI(1) => \ARG__23_n_78\,
DI(0) => \ARG__23_n_79\,
O(3) => \weight_reg[13][12]_i_1_n_4\,
O(2) => \weight_reg[13][12]_i_1_n_5\,
O(1) => \weight_reg[13][12]_i_1_n_6\,
O(0) => \weight_reg[13][12]_i_1_n_7\,
S(3) => \weight[13][12]_i_2_n_0\,
S(2) => \weight[13][12]_i_3_n_0\,
S(1) => \weight[13][12]_i_4_n_0\,
S(0) => \weight[13][12]_i_5_n_0\
);
\weight_reg[13][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_6\,
Q => \weight_reg[13]_12\(13)
);
\weight_reg[13][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_5\,
Q => \weight_reg[13]_12\(14)
);
\weight_reg[13][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_4\,
Q => \weight_reg[13]_12\(15)
);
\weight_reg[13][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_6\,
Q => \weight_reg[13]_12\(1)
);
\weight_reg[13][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_5\,
Q => \weight_reg[13]_12\(2)
);
\weight_reg[13][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_4\,
Q => \weight_reg[13]_12\(3)
);
\weight_reg[13][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_7\,
Q => \weight_reg[13]_12\(4)
);
\weight_reg[13][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[13][0]_i_1_n_0\,
CO(3) => \weight_reg[13][4]_i_1_n_0\,
CO(2) => \weight_reg[13][4]_i_1_n_1\,
CO(1) => \weight_reg[13][4]_i_1_n_2\,
CO(0) => \weight_reg[13][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__23_n_84\,
DI(2) => \ARG__23_n_85\,
DI(1) => \ARG__23_n_86\,
DI(0) => \ARG__23_n_87\,
O(3) => \weight_reg[13][4]_i_1_n_4\,
O(2) => \weight_reg[13][4]_i_1_n_5\,
O(1) => \weight_reg[13][4]_i_1_n_6\,
O(0) => \weight_reg[13][4]_i_1_n_7\,
S(3) => \weight[13][4]_i_2_n_0\,
S(2) => \weight[13][4]_i_3_n_0\,
S(1) => \weight[13][4]_i_4_n_0\,
S(0) => \weight[13][4]_i_5_n_0\
);
\weight_reg[13][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_6\,
Q => \weight_reg[13]_12\(5)
);
\weight_reg[13][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_5\,
Q => \weight_reg[13]_12\(6)
);
\weight_reg[13][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_4\,
Q => \weight_reg[13]_12\(7)
);
\weight_reg[13][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_7\,
Q => \weight_reg[13]_12\(8)
);
\weight_reg[13][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[13][4]_i_1_n_0\,
CO(3) => \weight_reg[13][8]_i_1_n_0\,
CO(2) => \weight_reg[13][8]_i_1_n_1\,
CO(1) => \weight_reg[13][8]_i_1_n_2\,
CO(0) => \weight_reg[13][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__23_n_80\,
DI(2) => \ARG__23_n_81\,
DI(1) => \ARG__23_n_82\,
DI(0) => \ARG__23_n_83\,
O(3) => \weight_reg[13][8]_i_1_n_4\,
O(2) => \weight_reg[13][8]_i_1_n_5\,
O(1) => \weight_reg[13][8]_i_1_n_6\,
O(0) => \weight_reg[13][8]_i_1_n_7\,
S(3) => \weight[13][8]_i_2_n_0\,
S(2) => \weight[13][8]_i_3_n_0\,
S(1) => \weight[13][8]_i_4_n_0\,
S(0) => \weight[13][8]_i_5_n_0\
);
\weight_reg[13][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_6\,
Q => \weight_reg[13]_12\(9)
);
\weight_reg[14][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_7\,
Q => \weight_reg[14]_13\(0)
);
\weight_reg[14][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[14][0]_i_1_n_0\,
CO(2) => \weight_reg[14][0]_i_1_n_1\,
CO(1) => \weight_reg[14][0]_i_1_n_2\,
CO(0) => \weight_reg[14][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__25_n_88\,
DI(2) => \ARG__25_n_89\,
DI(1) => \ARG__25_n_90\,
DI(0) => \ARG__25_n_91\,
O(3) => \weight_reg[14][0]_i_1_n_4\,
O(2) => \weight_reg[14][0]_i_1_n_5\,
O(1) => \weight_reg[14][0]_i_1_n_6\,
O(0) => \weight_reg[14][0]_i_1_n_7\,
S(3) => \weight[14][0]_i_2_n_0\,
S(2) => \weight[14][0]_i_3_n_0\,
S(1) => \weight[14][0]_i_4_n_0\,
S(0) => \weight[14][0]_i_5_n_0\
);
\weight_reg[14][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_5\,
Q => \weight_reg[14]_13\(10)
);
\weight_reg[14][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_4\,
Q => \weight_reg[14]_13\(11)
);
\weight_reg[14][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_7\,
Q => \weight_reg[14]_13\(12)
);
\weight_reg[14][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[14][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[14][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[14][12]_i_1_n_1\,
CO(1) => \weight_reg[14][12]_i_1_n_2\,
CO(0) => \weight_reg[14][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__25_n_77\,
DI(1) => \ARG__25_n_78\,
DI(0) => \ARG__25_n_79\,
O(3) => \weight_reg[14][12]_i_1_n_4\,
O(2) => \weight_reg[14][12]_i_1_n_5\,
O(1) => \weight_reg[14][12]_i_1_n_6\,
O(0) => \weight_reg[14][12]_i_1_n_7\,
S(3) => \weight[14][12]_i_2_n_0\,
S(2) => \weight[14][12]_i_3_n_0\,
S(1) => \weight[14][12]_i_4_n_0\,
S(0) => \weight[14][12]_i_5_n_0\
);
\weight_reg[14][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_6\,
Q => \weight_reg[14]_13\(13)
);
\weight_reg[14][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_5\,
Q => \weight_reg[14]_13\(14)
);
\weight_reg[14][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_4\,
Q => \weight_reg[14]_13\(15)
);
\weight_reg[14][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_6\,
Q => \weight_reg[14]_13\(1)
);
\weight_reg[14][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_5\,
Q => \weight_reg[14]_13\(2)
);
\weight_reg[14][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_4\,
Q => \weight_reg[14]_13\(3)
);
\weight_reg[14][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_7\,
Q => \weight_reg[14]_13\(4)
);
\weight_reg[14][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[14][0]_i_1_n_0\,
CO(3) => \weight_reg[14][4]_i_1_n_0\,
CO(2) => \weight_reg[14][4]_i_1_n_1\,
CO(1) => \weight_reg[14][4]_i_1_n_2\,
CO(0) => \weight_reg[14][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__25_n_84\,
DI(2) => \ARG__25_n_85\,
DI(1) => \ARG__25_n_86\,
DI(0) => \ARG__25_n_87\,
O(3) => \weight_reg[14][4]_i_1_n_4\,
O(2) => \weight_reg[14][4]_i_1_n_5\,
O(1) => \weight_reg[14][4]_i_1_n_6\,
O(0) => \weight_reg[14][4]_i_1_n_7\,
S(3) => \weight[14][4]_i_2_n_0\,
S(2) => \weight[14][4]_i_3_n_0\,
S(1) => \weight[14][4]_i_4_n_0\,
S(0) => \weight[14][4]_i_5_n_0\
);
\weight_reg[14][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_6\,
Q => \weight_reg[14]_13\(5)
);
\weight_reg[14][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_5\,
Q => \weight_reg[14]_13\(6)
);
\weight_reg[14][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_4\,
Q => \weight_reg[14]_13\(7)
);
\weight_reg[14][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_7\,
Q => \weight_reg[14]_13\(8)
);
\weight_reg[14][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[14][4]_i_1_n_0\,
CO(3) => \weight_reg[14][8]_i_1_n_0\,
CO(2) => \weight_reg[14][8]_i_1_n_1\,
CO(1) => \weight_reg[14][8]_i_1_n_2\,
CO(0) => \weight_reg[14][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__25_n_80\,
DI(2) => \ARG__25_n_81\,
DI(1) => \ARG__25_n_82\,
DI(0) => \ARG__25_n_83\,
O(3) => \weight_reg[14][8]_i_1_n_4\,
O(2) => \weight_reg[14][8]_i_1_n_5\,
O(1) => \weight_reg[14][8]_i_1_n_6\,
O(0) => \weight_reg[14][8]_i_1_n_7\,
S(3) => \weight[14][8]_i_2_n_0\,
S(2) => \weight[14][8]_i_3_n_0\,
S(1) => \weight[14][8]_i_4_n_0\,
S(0) => \weight[14][8]_i_5_n_0\
);
\weight_reg[14][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_6\,
Q => \weight_reg[14]_13\(9)
);
\weight_reg[15][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_7\,
Q => \weight_reg[15]_14\(0)
);
\weight_reg[15][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[15][0]_i_1_n_0\,
CO(2) => \weight_reg[15][0]_i_1_n_1\,
CO(1) => \weight_reg[15][0]_i_1_n_2\,
CO(0) => \weight_reg[15][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__27_n_88\,
DI(2) => \ARG__27_n_89\,
DI(1) => \ARG__27_n_90\,
DI(0) => \ARG__27_n_91\,
O(3) => \weight_reg[15][0]_i_1_n_4\,
O(2) => \weight_reg[15][0]_i_1_n_5\,
O(1) => \weight_reg[15][0]_i_1_n_6\,
O(0) => \weight_reg[15][0]_i_1_n_7\,
S(3) => \weight[15][0]_i_2_n_0\,
S(2) => \weight[15][0]_i_3_n_0\,
S(1) => \weight[15][0]_i_4_n_0\,
S(0) => \weight[15][0]_i_5_n_0\
);
\weight_reg[15][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_5\,
Q => \weight_reg[15]_14\(10)
);
\weight_reg[15][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_4\,
Q => \weight_reg[15]_14\(11)
);
\weight_reg[15][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_7\,
Q => \weight_reg[15]_14\(12)
);
\weight_reg[15][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[15][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[15][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[15][12]_i_1_n_1\,
CO(1) => \weight_reg[15][12]_i_1_n_2\,
CO(0) => \weight_reg[15][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__27_n_77\,
DI(1) => \ARG__27_n_78\,
DI(0) => \ARG__27_n_79\,
O(3) => \weight_reg[15][12]_i_1_n_4\,
O(2) => \weight_reg[15][12]_i_1_n_5\,
O(1) => \weight_reg[15][12]_i_1_n_6\,
O(0) => \weight_reg[15][12]_i_1_n_7\,
S(3) => \weight[15][12]_i_2_n_0\,
S(2) => \weight[15][12]_i_3_n_0\,
S(1) => \weight[15][12]_i_4_n_0\,
S(0) => \weight[15][12]_i_5_n_0\
);
\weight_reg[15][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_6\,
Q => \weight_reg[15]_14\(13)
);
\weight_reg[15][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_5\,
Q => \weight_reg[15]_14\(14)
);
\weight_reg[15][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_4\,
Q => \weight_reg[15]_14\(15)
);
\weight_reg[15][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_6\,
Q => \weight_reg[15]_14\(1)
);
\weight_reg[15][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_5\,
Q => \weight_reg[15]_14\(2)
);
\weight_reg[15][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_4\,
Q => \weight_reg[15]_14\(3)
);
\weight_reg[15][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_7\,
Q => \weight_reg[15]_14\(4)
);
\weight_reg[15][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[15][0]_i_1_n_0\,
CO(3) => \weight_reg[15][4]_i_1_n_0\,
CO(2) => \weight_reg[15][4]_i_1_n_1\,
CO(1) => \weight_reg[15][4]_i_1_n_2\,
CO(0) => \weight_reg[15][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__27_n_84\,
DI(2) => \ARG__27_n_85\,
DI(1) => \ARG__27_n_86\,
DI(0) => \ARG__27_n_87\,
O(3) => \weight_reg[15][4]_i_1_n_4\,
O(2) => \weight_reg[15][4]_i_1_n_5\,
O(1) => \weight_reg[15][4]_i_1_n_6\,
O(0) => \weight_reg[15][4]_i_1_n_7\,
S(3) => \weight[15][4]_i_2_n_0\,
S(2) => \weight[15][4]_i_3_n_0\,
S(1) => \weight[15][4]_i_4_n_0\,
S(0) => \weight[15][4]_i_5_n_0\
);
\weight_reg[15][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_6\,
Q => \weight_reg[15]_14\(5)
);
\weight_reg[15][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_5\,
Q => \weight_reg[15]_14\(6)
);
\weight_reg[15][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_4\,
Q => \weight_reg[15]_14\(7)
);
\weight_reg[15][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_7\,
Q => \weight_reg[15]_14\(8)
);
\weight_reg[15][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[15][4]_i_1_n_0\,
CO(3) => \weight_reg[15][8]_i_1_n_0\,
CO(2) => \weight_reg[15][8]_i_1_n_1\,
CO(1) => \weight_reg[15][8]_i_1_n_2\,
CO(0) => \weight_reg[15][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__27_n_80\,
DI(2) => \ARG__27_n_81\,
DI(1) => \ARG__27_n_82\,
DI(0) => \ARG__27_n_83\,
O(3) => \weight_reg[15][8]_i_1_n_4\,
O(2) => \weight_reg[15][8]_i_1_n_5\,
O(1) => \weight_reg[15][8]_i_1_n_6\,
O(0) => \weight_reg[15][8]_i_1_n_7\,
S(3) => \weight[15][8]_i_2_n_0\,
S(2) => \weight[15][8]_i_3_n_0\,
S(1) => \weight[15][8]_i_4_n_0\,
S(0) => \weight[15][8]_i_5_n_0\
);
\weight_reg[15][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_6\,
Q => \weight_reg[15]_14\(9)
);
\weight_reg[1][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_7\,
Q => \weight_reg[1]_0\(0)
);
\weight_reg[1][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[1][0]_i_1_n_0\,
CO(2) => \weight_reg[1][0]_i_1_n_1\,
CO(1) => \weight_reg[1][0]_i_1_n_2\,
CO(0) => \weight_reg[1][0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \in\(3 downto 0),
O(3) => \weight_reg[1][0]_i_1_n_4\,
O(2) => \weight_reg[1][0]_i_1_n_5\,
O(1) => \weight_reg[1][0]_i_1_n_6\,
O(0) => \weight_reg[1][0]_i_1_n_7\,
S(3) => \weight[1][0]_i_2_n_0\,
S(2) => \weight[1][0]_i_3_n_0\,
S(1) => \weight[1][0]_i_4_n_0\,
S(0) => \weight[1][0]_i_5_n_0\
);
\weight_reg[1][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_5\,
Q => \weight_reg[1]_0\(10)
);
\weight_reg[1][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_4\,
Q => \weight_reg[1]_0\(11)
);
\weight_reg[1][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_7\,
Q => \weight_reg[1]_0\(12)
);
\weight_reg[1][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[1][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[1][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[1][12]_i_1_n_1\,
CO(1) => \weight_reg[1][12]_i_1_n_2\,
CO(0) => \weight_reg[1][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \in\(14 downto 12),
O(3) => \weight_reg[1][12]_i_1_n_4\,
O(2) => \weight_reg[1][12]_i_1_n_5\,
O(1) => \weight_reg[1][12]_i_1_n_6\,
O(0) => \weight_reg[1][12]_i_1_n_7\,
S(3) => \weight[1][12]_i_2_n_0\,
S(2) => \weight[1][12]_i_3_n_0\,
S(1) => \weight[1][12]_i_4_n_0\,
S(0) => \weight[1][12]_i_5_n_0\
);
\weight_reg[1][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_6\,
Q => \weight_reg[1]_0\(13)
);
\weight_reg[1][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_5\,
Q => \weight_reg[1]_0\(14)
);
\weight_reg[1][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_4\,
Q => \weight_reg[1]_0\(15)
);
\weight_reg[1][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_6\,
Q => \weight_reg[1]_0\(1)
);
\weight_reg[1][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_5\,
Q => \weight_reg[1]_0\(2)
);
\weight_reg[1][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_4\,
Q => \weight_reg[1]_0\(3)
);
\weight_reg[1][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_7\,
Q => \weight_reg[1]_0\(4)
);
\weight_reg[1][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[1][0]_i_1_n_0\,
CO(3) => \weight_reg[1][4]_i_1_n_0\,
CO(2) => \weight_reg[1][4]_i_1_n_1\,
CO(1) => \weight_reg[1][4]_i_1_n_2\,
CO(0) => \weight_reg[1][4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \in\(7 downto 4),
O(3) => \weight_reg[1][4]_i_1_n_4\,
O(2) => \weight_reg[1][4]_i_1_n_5\,
O(1) => \weight_reg[1][4]_i_1_n_6\,
O(0) => \weight_reg[1][4]_i_1_n_7\,
S(3) => \weight[1][4]_i_2_n_0\,
S(2) => \weight[1][4]_i_3_n_0\,
S(1) => \weight[1][4]_i_4_n_0\,
S(0) => \weight[1][4]_i_5_n_0\
);
\weight_reg[1][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_6\,
Q => \weight_reg[1]_0\(5)
);
\weight_reg[1][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_5\,
Q => \weight_reg[1]_0\(6)
);
\weight_reg[1][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_4\,
Q => \weight_reg[1]_0\(7)
);
\weight_reg[1][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_7\,
Q => \weight_reg[1]_0\(8)
);
\weight_reg[1][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[1][4]_i_1_n_0\,
CO(3) => \weight_reg[1][8]_i_1_n_0\,
CO(2) => \weight_reg[1][8]_i_1_n_1\,
CO(1) => \weight_reg[1][8]_i_1_n_2\,
CO(0) => \weight_reg[1][8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \in\(11 downto 8),
O(3) => \weight_reg[1][8]_i_1_n_4\,
O(2) => \weight_reg[1][8]_i_1_n_5\,
O(1) => \weight_reg[1][8]_i_1_n_6\,
O(0) => \weight_reg[1][8]_i_1_n_7\,
S(3) => \weight[1][8]_i_2_n_0\,
S(2) => \weight[1][8]_i_3_n_0\,
S(1) => \weight[1][8]_i_4_n_0\,
S(0) => \weight[1][8]_i_5_n_0\
);
\weight_reg[1][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_6\,
Q => \weight_reg[1]_0\(9)
);
\weight_reg[2][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_7\,
Q => \weight_reg[2]_1\(0)
);
\weight_reg[2][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[2][0]_i_1_n_0\,
CO(2) => \weight_reg[2][0]_i_1_n_1\,
CO(1) => \weight_reg[2][0]_i_1_n_2\,
CO(0) => \weight_reg[2][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__1_n_88\,
DI(2) => \ARG__1_n_89\,
DI(1) => \ARG__1_n_90\,
DI(0) => \ARG__1_n_91\,
O(3) => \weight_reg[2][0]_i_1_n_4\,
O(2) => \weight_reg[2][0]_i_1_n_5\,
O(1) => \weight_reg[2][0]_i_1_n_6\,
O(0) => \weight_reg[2][0]_i_1_n_7\,
S(3) => \weight[2][0]_i_2_n_0\,
S(2) => \weight[2][0]_i_3_n_0\,
S(1) => \weight[2][0]_i_4_n_0\,
S(0) => \weight[2][0]_i_5_n_0\
);
\weight_reg[2][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_5\,
Q => \weight_reg[2]_1\(10)
);
\weight_reg[2][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_4\,
Q => \weight_reg[2]_1\(11)
);
\weight_reg[2][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_7\,
Q => \weight_reg[2]_1\(12)
);
\weight_reg[2][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[2][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[2][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[2][12]_i_1_n_1\,
CO(1) => \weight_reg[2][12]_i_1_n_2\,
CO(0) => \weight_reg[2][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__1_n_77\,
DI(1) => \ARG__1_n_78\,
DI(0) => \ARG__1_n_79\,
O(3) => \weight_reg[2][12]_i_1_n_4\,
O(2) => \weight_reg[2][12]_i_1_n_5\,
O(1) => \weight_reg[2][12]_i_1_n_6\,
O(0) => \weight_reg[2][12]_i_1_n_7\,
S(3) => \weight[2][12]_i_2_n_0\,
S(2) => \weight[2][12]_i_3_n_0\,
S(1) => \weight[2][12]_i_4_n_0\,
S(0) => \weight[2][12]_i_5_n_0\
);
\weight_reg[2][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_6\,
Q => \weight_reg[2]_1\(13)
);
\weight_reg[2][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_5\,
Q => \weight_reg[2]_1\(14)
);
\weight_reg[2][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_4\,
Q => \weight_reg[2]_1\(15)
);
\weight_reg[2][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_6\,
Q => \weight_reg[2]_1\(1)
);
\weight_reg[2][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_5\,
Q => \weight_reg[2]_1\(2)
);
\weight_reg[2][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_4\,
Q => \weight_reg[2]_1\(3)
);
\weight_reg[2][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_7\,
Q => \weight_reg[2]_1\(4)
);
\weight_reg[2][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[2][0]_i_1_n_0\,
CO(3) => \weight_reg[2][4]_i_1_n_0\,
CO(2) => \weight_reg[2][4]_i_1_n_1\,
CO(1) => \weight_reg[2][4]_i_1_n_2\,
CO(0) => \weight_reg[2][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__1_n_84\,
DI(2) => \ARG__1_n_85\,
DI(1) => \ARG__1_n_86\,
DI(0) => \ARG__1_n_87\,
O(3) => \weight_reg[2][4]_i_1_n_4\,
O(2) => \weight_reg[2][4]_i_1_n_5\,
O(1) => \weight_reg[2][4]_i_1_n_6\,
O(0) => \weight_reg[2][4]_i_1_n_7\,
S(3) => \weight[2][4]_i_2_n_0\,
S(2) => \weight[2][4]_i_3_n_0\,
S(1) => \weight[2][4]_i_4_n_0\,
S(0) => \weight[2][4]_i_5_n_0\
);
\weight_reg[2][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_6\,
Q => \weight_reg[2]_1\(5)
);
\weight_reg[2][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_5\,
Q => \weight_reg[2]_1\(6)
);
\weight_reg[2][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_4\,
Q => \weight_reg[2]_1\(7)
);
\weight_reg[2][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_7\,
Q => \weight_reg[2]_1\(8)
);
\weight_reg[2][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[2][4]_i_1_n_0\,
CO(3) => \weight_reg[2][8]_i_1_n_0\,
CO(2) => \weight_reg[2][8]_i_1_n_1\,
CO(1) => \weight_reg[2][8]_i_1_n_2\,
CO(0) => \weight_reg[2][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__1_n_80\,
DI(2) => \ARG__1_n_81\,
DI(1) => \ARG__1_n_82\,
DI(0) => \ARG__1_n_83\,
O(3) => \weight_reg[2][8]_i_1_n_4\,
O(2) => \weight_reg[2][8]_i_1_n_5\,
O(1) => \weight_reg[2][8]_i_1_n_6\,
O(0) => \weight_reg[2][8]_i_1_n_7\,
S(3) => \weight[2][8]_i_2_n_0\,
S(2) => \weight[2][8]_i_3_n_0\,
S(1) => \weight[2][8]_i_4_n_0\,
S(0) => \weight[2][8]_i_5_n_0\
);
\weight_reg[2][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_6\,
Q => \weight_reg[2]_1\(9)
);
\weight_reg[3][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_7\,
Q => \weight_reg[3]_2\(0)
);
\weight_reg[3][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[3][0]_i_1_n_0\,
CO(2) => \weight_reg[3][0]_i_1_n_1\,
CO(1) => \weight_reg[3][0]_i_1_n_2\,
CO(0) => \weight_reg[3][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__3_n_88\,
DI(2) => \ARG__3_n_89\,
DI(1) => \ARG__3_n_90\,
DI(0) => \ARG__3_n_91\,
O(3) => \weight_reg[3][0]_i_1_n_4\,
O(2) => \weight_reg[3][0]_i_1_n_5\,
O(1) => \weight_reg[3][0]_i_1_n_6\,
O(0) => \weight_reg[3][0]_i_1_n_7\,
S(3) => \weight[3][0]_i_2_n_0\,
S(2) => \weight[3][0]_i_3_n_0\,
S(1) => \weight[3][0]_i_4_n_0\,
S(0) => \weight[3][0]_i_5_n_0\
);
\weight_reg[3][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_5\,
Q => \weight_reg[3]_2\(10)
);
\weight_reg[3][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_4\,
Q => \weight_reg[3]_2\(11)
);
\weight_reg[3][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_7\,
Q => \weight_reg[3]_2\(12)
);
\weight_reg[3][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[3][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[3][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[3][12]_i_1_n_1\,
CO(1) => \weight_reg[3][12]_i_1_n_2\,
CO(0) => \weight_reg[3][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__3_n_77\,
DI(1) => \ARG__3_n_78\,
DI(0) => \ARG__3_n_79\,
O(3) => \weight_reg[3][12]_i_1_n_4\,
O(2) => \weight_reg[3][12]_i_1_n_5\,
O(1) => \weight_reg[3][12]_i_1_n_6\,
O(0) => \weight_reg[3][12]_i_1_n_7\,
S(3) => \weight[3][12]_i_2_n_0\,
S(2) => \weight[3][12]_i_3_n_0\,
S(1) => \weight[3][12]_i_4_n_0\,
S(0) => \weight[3][12]_i_5_n_0\
);
\weight_reg[3][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_6\,
Q => \weight_reg[3]_2\(13)
);
\weight_reg[3][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_5\,
Q => \weight_reg[3]_2\(14)
);
\weight_reg[3][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_4\,
Q => \weight_reg[3]_2\(15)
);
\weight_reg[3][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_6\,
Q => \weight_reg[3]_2\(1)
);
\weight_reg[3][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_5\,
Q => \weight_reg[3]_2\(2)
);
\weight_reg[3][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_4\,
Q => \weight_reg[3]_2\(3)
);
\weight_reg[3][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_7\,
Q => \weight_reg[3]_2\(4)
);
\weight_reg[3][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[3][0]_i_1_n_0\,
CO(3) => \weight_reg[3][4]_i_1_n_0\,
CO(2) => \weight_reg[3][4]_i_1_n_1\,
CO(1) => \weight_reg[3][4]_i_1_n_2\,
CO(0) => \weight_reg[3][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__3_n_84\,
DI(2) => \ARG__3_n_85\,
DI(1) => \ARG__3_n_86\,
DI(0) => \ARG__3_n_87\,
O(3) => \weight_reg[3][4]_i_1_n_4\,
O(2) => \weight_reg[3][4]_i_1_n_5\,
O(1) => \weight_reg[3][4]_i_1_n_6\,
O(0) => \weight_reg[3][4]_i_1_n_7\,
S(3) => \weight[3][4]_i_2_n_0\,
S(2) => \weight[3][4]_i_3_n_0\,
S(1) => \weight[3][4]_i_4_n_0\,
S(0) => \weight[3][4]_i_5_n_0\
);
\weight_reg[3][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_6\,
Q => \weight_reg[3]_2\(5)
);
\weight_reg[3][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_5\,
Q => \weight_reg[3]_2\(6)
);
\weight_reg[3][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_4\,
Q => \weight_reg[3]_2\(7)
);
\weight_reg[3][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_7\,
Q => \weight_reg[3]_2\(8)
);
\weight_reg[3][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[3][4]_i_1_n_0\,
CO(3) => \weight_reg[3][8]_i_1_n_0\,
CO(2) => \weight_reg[3][8]_i_1_n_1\,
CO(1) => \weight_reg[3][8]_i_1_n_2\,
CO(0) => \weight_reg[3][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__3_n_80\,
DI(2) => \ARG__3_n_81\,
DI(1) => \ARG__3_n_82\,
DI(0) => \ARG__3_n_83\,
O(3) => \weight_reg[3][8]_i_1_n_4\,
O(2) => \weight_reg[3][8]_i_1_n_5\,
O(1) => \weight_reg[3][8]_i_1_n_6\,
O(0) => \weight_reg[3][8]_i_1_n_7\,
S(3) => \weight[3][8]_i_2_n_0\,
S(2) => \weight[3][8]_i_3_n_0\,
S(1) => \weight[3][8]_i_4_n_0\,
S(0) => \weight[3][8]_i_5_n_0\
);
\weight_reg[3][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_6\,
Q => \weight_reg[3]_2\(9)
);
\weight_reg[4][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_7\,
Q => \weight_reg[4]_3\(0)
);
\weight_reg[4][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[4][0]_i_1_n_0\,
CO(2) => \weight_reg[4][0]_i_1_n_1\,
CO(1) => \weight_reg[4][0]_i_1_n_2\,
CO(0) => \weight_reg[4][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__5_n_88\,
DI(2) => \ARG__5_n_89\,
DI(1) => \ARG__5_n_90\,
DI(0) => \ARG__5_n_91\,
O(3) => \weight_reg[4][0]_i_1_n_4\,
O(2) => \weight_reg[4][0]_i_1_n_5\,
O(1) => \weight_reg[4][0]_i_1_n_6\,
O(0) => \weight_reg[4][0]_i_1_n_7\,
S(3) => \weight[4][0]_i_2_n_0\,
S(2) => \weight[4][0]_i_3_n_0\,
S(1) => \weight[4][0]_i_4_n_0\,
S(0) => \weight[4][0]_i_5_n_0\
);
\weight_reg[4][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_5\,
Q => \weight_reg[4]_3\(10)
);
\weight_reg[4][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_4\,
Q => \weight_reg[4]_3\(11)
);
\weight_reg[4][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_7\,
Q => \weight_reg[4]_3\(12)
);
\weight_reg[4][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[4][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[4][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[4][12]_i_1_n_1\,
CO(1) => \weight_reg[4][12]_i_1_n_2\,
CO(0) => \weight_reg[4][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__5_n_77\,
DI(1) => \ARG__5_n_78\,
DI(0) => \ARG__5_n_79\,
O(3) => \weight_reg[4][12]_i_1_n_4\,
O(2) => \weight_reg[4][12]_i_1_n_5\,
O(1) => \weight_reg[4][12]_i_1_n_6\,
O(0) => \weight_reg[4][12]_i_1_n_7\,
S(3) => \weight[4][12]_i_2_n_0\,
S(2) => \weight[4][12]_i_3_n_0\,
S(1) => \weight[4][12]_i_4_n_0\,
S(0) => \weight[4][12]_i_5_n_0\
);
\weight_reg[4][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_6\,
Q => \weight_reg[4]_3\(13)
);
\weight_reg[4][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_5\,
Q => \weight_reg[4]_3\(14)
);
\weight_reg[4][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_4\,
Q => \weight_reg[4]_3\(15)
);
\weight_reg[4][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_6\,
Q => \weight_reg[4]_3\(1)
);
\weight_reg[4][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_5\,
Q => \weight_reg[4]_3\(2)
);
\weight_reg[4][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_4\,
Q => \weight_reg[4]_3\(3)
);
\weight_reg[4][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_7\,
Q => \weight_reg[4]_3\(4)
);
\weight_reg[4][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[4][0]_i_1_n_0\,
CO(3) => \weight_reg[4][4]_i_1_n_0\,
CO(2) => \weight_reg[4][4]_i_1_n_1\,
CO(1) => \weight_reg[4][4]_i_1_n_2\,
CO(0) => \weight_reg[4][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__5_n_84\,
DI(2) => \ARG__5_n_85\,
DI(1) => \ARG__5_n_86\,
DI(0) => \ARG__5_n_87\,
O(3) => \weight_reg[4][4]_i_1_n_4\,
O(2) => \weight_reg[4][4]_i_1_n_5\,
O(1) => \weight_reg[4][4]_i_1_n_6\,
O(0) => \weight_reg[4][4]_i_1_n_7\,
S(3) => \weight[4][4]_i_2_n_0\,
S(2) => \weight[4][4]_i_3_n_0\,
S(1) => \weight[4][4]_i_4_n_0\,
S(0) => \weight[4][4]_i_5_n_0\
);
\weight_reg[4][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_6\,
Q => \weight_reg[4]_3\(5)
);
\weight_reg[4][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_5\,
Q => \weight_reg[4]_3\(6)
);
\weight_reg[4][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_4\,
Q => \weight_reg[4]_3\(7)
);
\weight_reg[4][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_7\,
Q => \weight_reg[4]_3\(8)
);
\weight_reg[4][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[4][4]_i_1_n_0\,
CO(3) => \weight_reg[4][8]_i_1_n_0\,
CO(2) => \weight_reg[4][8]_i_1_n_1\,
CO(1) => \weight_reg[4][8]_i_1_n_2\,
CO(0) => \weight_reg[4][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__5_n_80\,
DI(2) => \ARG__5_n_81\,
DI(1) => \ARG__5_n_82\,
DI(0) => \ARG__5_n_83\,
O(3) => \weight_reg[4][8]_i_1_n_4\,
O(2) => \weight_reg[4][8]_i_1_n_5\,
O(1) => \weight_reg[4][8]_i_1_n_6\,
O(0) => \weight_reg[4][8]_i_1_n_7\,
S(3) => \weight[4][8]_i_2_n_0\,
S(2) => \weight[4][8]_i_3_n_0\,
S(1) => \weight[4][8]_i_4_n_0\,
S(0) => \weight[4][8]_i_5_n_0\
);
\weight_reg[4][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_6\,
Q => \weight_reg[4]_3\(9)
);
\weight_reg[5][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_7\,
Q => \weight_reg[5]_4\(0)
);
\weight_reg[5][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[5][0]_i_1_n_0\,
CO(2) => \weight_reg[5][0]_i_1_n_1\,
CO(1) => \weight_reg[5][0]_i_1_n_2\,
CO(0) => \weight_reg[5][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__7_n_88\,
DI(2) => \ARG__7_n_89\,
DI(1) => \ARG__7_n_90\,
DI(0) => \ARG__7_n_91\,
O(3) => \weight_reg[5][0]_i_1_n_4\,
O(2) => \weight_reg[5][0]_i_1_n_5\,
O(1) => \weight_reg[5][0]_i_1_n_6\,
O(0) => \weight_reg[5][0]_i_1_n_7\,
S(3) => \weight[5][0]_i_2_n_0\,
S(2) => \weight[5][0]_i_3_n_0\,
S(1) => \weight[5][0]_i_4_n_0\,
S(0) => \weight[5][0]_i_5_n_0\
);
\weight_reg[5][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_5\,
Q => \weight_reg[5]_4\(10)
);
\weight_reg[5][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_4\,
Q => \weight_reg[5]_4\(11)
);
\weight_reg[5][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_7\,
Q => \weight_reg[5]_4\(12)
);
\weight_reg[5][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[5][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[5][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[5][12]_i_1_n_1\,
CO(1) => \weight_reg[5][12]_i_1_n_2\,
CO(0) => \weight_reg[5][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__7_n_77\,
DI(1) => \ARG__7_n_78\,
DI(0) => \ARG__7_n_79\,
O(3) => \weight_reg[5][12]_i_1_n_4\,
O(2) => \weight_reg[5][12]_i_1_n_5\,
O(1) => \weight_reg[5][12]_i_1_n_6\,
O(0) => \weight_reg[5][12]_i_1_n_7\,
S(3) => \weight[5][12]_i_2_n_0\,
S(2) => \weight[5][12]_i_3_n_0\,
S(1) => \weight[5][12]_i_4_n_0\,
S(0) => \weight[5][12]_i_5_n_0\
);
\weight_reg[5][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_6\,
Q => \weight_reg[5]_4\(13)
);
\weight_reg[5][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_5\,
Q => \weight_reg[5]_4\(14)
);
\weight_reg[5][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_4\,
Q => \weight_reg[5]_4\(15)
);
\weight_reg[5][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_6\,
Q => \weight_reg[5]_4\(1)
);
\weight_reg[5][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_5\,
Q => \weight_reg[5]_4\(2)
);
\weight_reg[5][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_4\,
Q => \weight_reg[5]_4\(3)
);
\weight_reg[5][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_7\,
Q => \weight_reg[5]_4\(4)
);
\weight_reg[5][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[5][0]_i_1_n_0\,
CO(3) => \weight_reg[5][4]_i_1_n_0\,
CO(2) => \weight_reg[5][4]_i_1_n_1\,
CO(1) => \weight_reg[5][4]_i_1_n_2\,
CO(0) => \weight_reg[5][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__7_n_84\,
DI(2) => \ARG__7_n_85\,
DI(1) => \ARG__7_n_86\,
DI(0) => \ARG__7_n_87\,
O(3) => \weight_reg[5][4]_i_1_n_4\,
O(2) => \weight_reg[5][4]_i_1_n_5\,
O(1) => \weight_reg[5][4]_i_1_n_6\,
O(0) => \weight_reg[5][4]_i_1_n_7\,
S(3) => \weight[5][4]_i_2_n_0\,
S(2) => \weight[5][4]_i_3_n_0\,
S(1) => \weight[5][4]_i_4_n_0\,
S(0) => \weight[5][4]_i_5_n_0\
);
\weight_reg[5][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_6\,
Q => \weight_reg[5]_4\(5)
);
\weight_reg[5][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_5\,
Q => \weight_reg[5]_4\(6)
);
\weight_reg[5][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_4\,
Q => \weight_reg[5]_4\(7)
);
\weight_reg[5][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_7\,
Q => \weight_reg[5]_4\(8)
);
\weight_reg[5][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[5][4]_i_1_n_0\,
CO(3) => \weight_reg[5][8]_i_1_n_0\,
CO(2) => \weight_reg[5][8]_i_1_n_1\,
CO(1) => \weight_reg[5][8]_i_1_n_2\,
CO(0) => \weight_reg[5][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__7_n_80\,
DI(2) => \ARG__7_n_81\,
DI(1) => \ARG__7_n_82\,
DI(0) => \ARG__7_n_83\,
O(3) => \weight_reg[5][8]_i_1_n_4\,
O(2) => \weight_reg[5][8]_i_1_n_5\,
O(1) => \weight_reg[5][8]_i_1_n_6\,
O(0) => \weight_reg[5][8]_i_1_n_7\,
S(3) => \weight[5][8]_i_2_n_0\,
S(2) => \weight[5][8]_i_3_n_0\,
S(1) => \weight[5][8]_i_4_n_0\,
S(0) => \weight[5][8]_i_5_n_0\
);
\weight_reg[5][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_6\,
Q => \weight_reg[5]_4\(9)
);
\weight_reg[6][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_7\,
Q => \weight_reg[6]_5\(0)
);
\weight_reg[6][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[6][0]_i_1_n_0\,
CO(2) => \weight_reg[6][0]_i_1_n_1\,
CO(1) => \weight_reg[6][0]_i_1_n_2\,
CO(0) => \weight_reg[6][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__9_n_88\,
DI(2) => \ARG__9_n_89\,
DI(1) => \ARG__9_n_90\,
DI(0) => \ARG__9_n_91\,
O(3) => \weight_reg[6][0]_i_1_n_4\,
O(2) => \weight_reg[6][0]_i_1_n_5\,
O(1) => \weight_reg[6][0]_i_1_n_6\,
O(0) => \weight_reg[6][0]_i_1_n_7\,
S(3) => \weight[6][0]_i_2_n_0\,
S(2) => \weight[6][0]_i_3_n_0\,
S(1) => \weight[6][0]_i_4_n_0\,
S(0) => \weight[6][0]_i_5_n_0\
);
\weight_reg[6][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_5\,
Q => \weight_reg[6]_5\(10)
);
\weight_reg[6][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_4\,
Q => \weight_reg[6]_5\(11)
);
\weight_reg[6][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_7\,
Q => \weight_reg[6]_5\(12)
);
\weight_reg[6][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[6][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[6][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[6][12]_i_1_n_1\,
CO(1) => \weight_reg[6][12]_i_1_n_2\,
CO(0) => \weight_reg[6][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__9_n_77\,
DI(1) => \ARG__9_n_78\,
DI(0) => \ARG__9_n_79\,
O(3) => \weight_reg[6][12]_i_1_n_4\,
O(2) => \weight_reg[6][12]_i_1_n_5\,
O(1) => \weight_reg[6][12]_i_1_n_6\,
O(0) => \weight_reg[6][12]_i_1_n_7\,
S(3) => \weight[6][12]_i_2_n_0\,
S(2) => \weight[6][12]_i_3_n_0\,
S(1) => \weight[6][12]_i_4_n_0\,
S(0) => \weight[6][12]_i_5_n_0\
);
\weight_reg[6][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_6\,
Q => \weight_reg[6]_5\(13)
);
\weight_reg[6][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_5\,
Q => \weight_reg[6]_5\(14)
);
\weight_reg[6][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_4\,
Q => \weight_reg[6]_5\(15)
);
\weight_reg[6][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_6\,
Q => \weight_reg[6]_5\(1)
);
\weight_reg[6][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_5\,
Q => \weight_reg[6]_5\(2)
);
\weight_reg[6][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_4\,
Q => \weight_reg[6]_5\(3)
);
\weight_reg[6][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_7\,
Q => \weight_reg[6]_5\(4)
);
\weight_reg[6][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[6][0]_i_1_n_0\,
CO(3) => \weight_reg[6][4]_i_1_n_0\,
CO(2) => \weight_reg[6][4]_i_1_n_1\,
CO(1) => \weight_reg[6][4]_i_1_n_2\,
CO(0) => \weight_reg[6][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__9_n_84\,
DI(2) => \ARG__9_n_85\,
DI(1) => \ARG__9_n_86\,
DI(0) => \ARG__9_n_87\,
O(3) => \weight_reg[6][4]_i_1_n_4\,
O(2) => \weight_reg[6][4]_i_1_n_5\,
O(1) => \weight_reg[6][4]_i_1_n_6\,
O(0) => \weight_reg[6][4]_i_1_n_7\,
S(3) => \weight[6][4]_i_2_n_0\,
S(2) => \weight[6][4]_i_3_n_0\,
S(1) => \weight[6][4]_i_4_n_0\,
S(0) => \weight[6][4]_i_5_n_0\
);
\weight_reg[6][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_6\,
Q => \weight_reg[6]_5\(5)
);
\weight_reg[6][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_5\,
Q => \weight_reg[6]_5\(6)
);
\weight_reg[6][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_4\,
Q => \weight_reg[6]_5\(7)
);
\weight_reg[6][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_7\,
Q => \weight_reg[6]_5\(8)
);
\weight_reg[6][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[6][4]_i_1_n_0\,
CO(3) => \weight_reg[6][8]_i_1_n_0\,
CO(2) => \weight_reg[6][8]_i_1_n_1\,
CO(1) => \weight_reg[6][8]_i_1_n_2\,
CO(0) => \weight_reg[6][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__9_n_80\,
DI(2) => \ARG__9_n_81\,
DI(1) => \ARG__9_n_82\,
DI(0) => \ARG__9_n_83\,
O(3) => \weight_reg[6][8]_i_1_n_4\,
O(2) => \weight_reg[6][8]_i_1_n_5\,
O(1) => \weight_reg[6][8]_i_1_n_6\,
O(0) => \weight_reg[6][8]_i_1_n_7\,
S(3) => \weight[6][8]_i_2_n_0\,
S(2) => \weight[6][8]_i_3_n_0\,
S(1) => \weight[6][8]_i_4_n_0\,
S(0) => \weight[6][8]_i_5_n_0\
);
\weight_reg[6][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_6\,
Q => \weight_reg[6]_5\(9)
);
\weight_reg[7][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_7\,
Q => \weight_reg[7]_6\(0)
);
\weight_reg[7][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[7][0]_i_1_n_0\,
CO(2) => \weight_reg[7][0]_i_1_n_1\,
CO(1) => \weight_reg[7][0]_i_1_n_2\,
CO(0) => \weight_reg[7][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__11_n_88\,
DI(2) => \ARG__11_n_89\,
DI(1) => \ARG__11_n_90\,
DI(0) => \ARG__11_n_91\,
O(3) => \weight_reg[7][0]_i_1_n_4\,
O(2) => \weight_reg[7][0]_i_1_n_5\,
O(1) => \weight_reg[7][0]_i_1_n_6\,
O(0) => \weight_reg[7][0]_i_1_n_7\,
S(3) => \weight[7][0]_i_2_n_0\,
S(2) => \weight[7][0]_i_3_n_0\,
S(1) => \weight[7][0]_i_4_n_0\,
S(0) => \weight[7][0]_i_5_n_0\
);
\weight_reg[7][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_5\,
Q => \weight_reg[7]_6\(10)
);
\weight_reg[7][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_4\,
Q => \weight_reg[7]_6\(11)
);
\weight_reg[7][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_7\,
Q => \weight_reg[7]_6\(12)
);
\weight_reg[7][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[7][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[7][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[7][12]_i_1_n_1\,
CO(1) => \weight_reg[7][12]_i_1_n_2\,
CO(0) => \weight_reg[7][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__11_n_77\,
DI(1) => \ARG__11_n_78\,
DI(0) => \ARG__11_n_79\,
O(3) => \weight_reg[7][12]_i_1_n_4\,
O(2) => \weight_reg[7][12]_i_1_n_5\,
O(1) => \weight_reg[7][12]_i_1_n_6\,
O(0) => \weight_reg[7][12]_i_1_n_7\,
S(3) => \weight[7][12]_i_2_n_0\,
S(2) => \weight[7][12]_i_3_n_0\,
S(1) => \weight[7][12]_i_4_n_0\,
S(0) => \weight[7][12]_i_5_n_0\
);
\weight_reg[7][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_6\,
Q => \weight_reg[7]_6\(13)
);
\weight_reg[7][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_5\,
Q => \weight_reg[7]_6\(14)
);
\weight_reg[7][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_4\,
Q => \weight_reg[7]_6\(15)
);
\weight_reg[7][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_6\,
Q => \weight_reg[7]_6\(1)
);
\weight_reg[7][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_5\,
Q => \weight_reg[7]_6\(2)
);
\weight_reg[7][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_4\,
Q => \weight_reg[7]_6\(3)
);
\weight_reg[7][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_7\,
Q => \weight_reg[7]_6\(4)
);
\weight_reg[7][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[7][0]_i_1_n_0\,
CO(3) => \weight_reg[7][4]_i_1_n_0\,
CO(2) => \weight_reg[7][4]_i_1_n_1\,
CO(1) => \weight_reg[7][4]_i_1_n_2\,
CO(0) => \weight_reg[7][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__11_n_84\,
DI(2) => \ARG__11_n_85\,
DI(1) => \ARG__11_n_86\,
DI(0) => \ARG__11_n_87\,
O(3) => \weight_reg[7][4]_i_1_n_4\,
O(2) => \weight_reg[7][4]_i_1_n_5\,
O(1) => \weight_reg[7][4]_i_1_n_6\,
O(0) => \weight_reg[7][4]_i_1_n_7\,
S(3) => \weight[7][4]_i_2_n_0\,
S(2) => \weight[7][4]_i_3_n_0\,
S(1) => \weight[7][4]_i_4_n_0\,
S(0) => \weight[7][4]_i_5_n_0\
);
\weight_reg[7][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_6\,
Q => \weight_reg[7]_6\(5)
);
\weight_reg[7][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_5\,
Q => \weight_reg[7]_6\(6)
);
\weight_reg[7][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_4\,
Q => \weight_reg[7]_6\(7)
);
\weight_reg[7][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_7\,
Q => \weight_reg[7]_6\(8)
);
\weight_reg[7][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[7][4]_i_1_n_0\,
CO(3) => \weight_reg[7][8]_i_1_n_0\,
CO(2) => \weight_reg[7][8]_i_1_n_1\,
CO(1) => \weight_reg[7][8]_i_1_n_2\,
CO(0) => \weight_reg[7][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__11_n_80\,
DI(2) => \ARG__11_n_81\,
DI(1) => \ARG__11_n_82\,
DI(0) => \ARG__11_n_83\,
O(3) => \weight_reg[7][8]_i_1_n_4\,
O(2) => \weight_reg[7][8]_i_1_n_5\,
O(1) => \weight_reg[7][8]_i_1_n_6\,
O(0) => \weight_reg[7][8]_i_1_n_7\,
S(3) => \weight[7][8]_i_2_n_0\,
S(2) => \weight[7][8]_i_3_n_0\,
S(1) => \weight[7][8]_i_4_n_0\,
S(0) => \weight[7][8]_i_5_n_0\
);
\weight_reg[7][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_6\,
Q => \weight_reg[7]_6\(9)
);
\weight_reg[8][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_7\,
Q => \weight_reg[8]_7\(0)
);
\weight_reg[8][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[8][0]_i_1_n_0\,
CO(2) => \weight_reg[8][0]_i_1_n_1\,
CO(1) => \weight_reg[8][0]_i_1_n_2\,
CO(0) => \weight_reg[8][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__13_n_88\,
DI(2) => \ARG__13_n_89\,
DI(1) => \ARG__13_n_90\,
DI(0) => \ARG__13_n_91\,
O(3) => \weight_reg[8][0]_i_1_n_4\,
O(2) => \weight_reg[8][0]_i_1_n_5\,
O(1) => \weight_reg[8][0]_i_1_n_6\,
O(0) => \weight_reg[8][0]_i_1_n_7\,
S(3) => \weight[8][0]_i_2_n_0\,
S(2) => \weight[8][0]_i_3_n_0\,
S(1) => \weight[8][0]_i_4_n_0\,
S(0) => \weight[8][0]_i_5_n_0\
);
\weight_reg[8][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_5\,
Q => \weight_reg[8]_7\(10)
);
\weight_reg[8][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_4\,
Q => \weight_reg[8]_7\(11)
);
\weight_reg[8][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_7\,
Q => \weight_reg[8]_7\(12)
);
\weight_reg[8][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[8][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[8][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[8][12]_i_1_n_1\,
CO(1) => \weight_reg[8][12]_i_1_n_2\,
CO(0) => \weight_reg[8][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__13_n_77\,
DI(1) => \ARG__13_n_78\,
DI(0) => \ARG__13_n_79\,
O(3) => \weight_reg[8][12]_i_1_n_4\,
O(2) => \weight_reg[8][12]_i_1_n_5\,
O(1) => \weight_reg[8][12]_i_1_n_6\,
O(0) => \weight_reg[8][12]_i_1_n_7\,
S(3) => \weight[8][12]_i_2_n_0\,
S(2) => \weight[8][12]_i_3_n_0\,
S(1) => \weight[8][12]_i_4_n_0\,
S(0) => \weight[8][12]_i_5_n_0\
);
\weight_reg[8][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_6\,
Q => \weight_reg[8]_7\(13)
);
\weight_reg[8][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_5\,
Q => \weight_reg[8]_7\(14)
);
\weight_reg[8][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_4\,
Q => \weight_reg[8]_7\(15)
);
\weight_reg[8][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_6\,
Q => \weight_reg[8]_7\(1)
);
\weight_reg[8][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_5\,
Q => \weight_reg[8]_7\(2)
);
\weight_reg[8][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_4\,
Q => \weight_reg[8]_7\(3)
);
\weight_reg[8][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_7\,
Q => \weight_reg[8]_7\(4)
);
\weight_reg[8][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[8][0]_i_1_n_0\,
CO(3) => \weight_reg[8][4]_i_1_n_0\,
CO(2) => \weight_reg[8][4]_i_1_n_1\,
CO(1) => \weight_reg[8][4]_i_1_n_2\,
CO(0) => \weight_reg[8][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__13_n_84\,
DI(2) => \ARG__13_n_85\,
DI(1) => \ARG__13_n_86\,
DI(0) => \ARG__13_n_87\,
O(3) => \weight_reg[8][4]_i_1_n_4\,
O(2) => \weight_reg[8][4]_i_1_n_5\,
O(1) => \weight_reg[8][4]_i_1_n_6\,
O(0) => \weight_reg[8][4]_i_1_n_7\,
S(3) => \weight[8][4]_i_2_n_0\,
S(2) => \weight[8][4]_i_3_n_0\,
S(1) => \weight[8][4]_i_4_n_0\,
S(0) => \weight[8][4]_i_5_n_0\
);
\weight_reg[8][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_6\,
Q => \weight_reg[8]_7\(5)
);
\weight_reg[8][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_5\,
Q => \weight_reg[8]_7\(6)
);
\weight_reg[8][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_4\,
Q => \weight_reg[8]_7\(7)
);
\weight_reg[8][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_7\,
Q => \weight_reg[8]_7\(8)
);
\weight_reg[8][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[8][4]_i_1_n_0\,
CO(3) => \weight_reg[8][8]_i_1_n_0\,
CO(2) => \weight_reg[8][8]_i_1_n_1\,
CO(1) => \weight_reg[8][8]_i_1_n_2\,
CO(0) => \weight_reg[8][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__13_n_80\,
DI(2) => \ARG__13_n_81\,
DI(1) => \ARG__13_n_82\,
DI(0) => \ARG__13_n_83\,
O(3) => \weight_reg[8][8]_i_1_n_4\,
O(2) => \weight_reg[8][8]_i_1_n_5\,
O(1) => \weight_reg[8][8]_i_1_n_6\,
O(0) => \weight_reg[8][8]_i_1_n_7\,
S(3) => \weight[8][8]_i_2_n_0\,
S(2) => \weight[8][8]_i_3_n_0\,
S(1) => \weight[8][8]_i_4_n_0\,
S(0) => \weight[8][8]_i_5_n_0\
);
\weight_reg[8][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_6\,
Q => \weight_reg[8]_7\(9)
);
\weight_reg[9][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_7\,
Q => \weight_reg[9]_8\(0)
);
\weight_reg[9][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[9][0]_i_1_n_0\,
CO(2) => \weight_reg[9][0]_i_1_n_1\,
CO(1) => \weight_reg[9][0]_i_1_n_2\,
CO(0) => \weight_reg[9][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__15_n_88\,
DI(2) => \ARG__15_n_89\,
DI(1) => \ARG__15_n_90\,
DI(0) => \ARG__15_n_91\,
O(3) => \weight_reg[9][0]_i_1_n_4\,
O(2) => \weight_reg[9][0]_i_1_n_5\,
O(1) => \weight_reg[9][0]_i_1_n_6\,
O(0) => \weight_reg[9][0]_i_1_n_7\,
S(3) => \weight[9][0]_i_2_n_0\,
S(2) => \weight[9][0]_i_3_n_0\,
S(1) => \weight[9][0]_i_4_n_0\,
S(0) => \weight[9][0]_i_5_n_0\
);
\weight_reg[9][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_5\,
Q => \weight_reg[9]_8\(10)
);
\weight_reg[9][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_4\,
Q => \weight_reg[9]_8\(11)
);
\weight_reg[9][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_7\,
Q => \weight_reg[9]_8\(12)
);
\weight_reg[9][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[9][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[9][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[9][12]_i_1_n_1\,
CO(1) => \weight_reg[9][12]_i_1_n_2\,
CO(0) => \weight_reg[9][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__15_n_77\,
DI(1) => \ARG__15_n_78\,
DI(0) => \ARG__15_n_79\,
O(3) => \weight_reg[9][12]_i_1_n_4\,
O(2) => \weight_reg[9][12]_i_1_n_5\,
O(1) => \weight_reg[9][12]_i_1_n_6\,
O(0) => \weight_reg[9][12]_i_1_n_7\,
S(3) => \weight[9][12]_i_2_n_0\,
S(2) => \weight[9][12]_i_3_n_0\,
S(1) => \weight[9][12]_i_4_n_0\,
S(0) => \weight[9][12]_i_5_n_0\
);
\weight_reg[9][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_6\,
Q => \weight_reg[9]_8\(13)
);
\weight_reg[9][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_5\,
Q => \weight_reg[9]_8\(14)
);
\weight_reg[9][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_4\,
Q => \weight_reg[9]_8\(15)
);
\weight_reg[9][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_6\,
Q => \weight_reg[9]_8\(1)
);
\weight_reg[9][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_5\,
Q => \weight_reg[9]_8\(2)
);
\weight_reg[9][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_4\,
Q => \weight_reg[9]_8\(3)
);
\weight_reg[9][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_7\,
Q => \weight_reg[9]_8\(4)
);
\weight_reg[9][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[9][0]_i_1_n_0\,
CO(3) => \weight_reg[9][4]_i_1_n_0\,
CO(2) => \weight_reg[9][4]_i_1_n_1\,
CO(1) => \weight_reg[9][4]_i_1_n_2\,
CO(0) => \weight_reg[9][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__15_n_84\,
DI(2) => \ARG__15_n_85\,
DI(1) => \ARG__15_n_86\,
DI(0) => \ARG__15_n_87\,
O(3) => \weight_reg[9][4]_i_1_n_4\,
O(2) => \weight_reg[9][4]_i_1_n_5\,
O(1) => \weight_reg[9][4]_i_1_n_6\,
O(0) => \weight_reg[9][4]_i_1_n_7\,
S(3) => \weight[9][4]_i_2_n_0\,
S(2) => \weight[9][4]_i_3_n_0\,
S(1) => \weight[9][4]_i_4_n_0\,
S(0) => \weight[9][4]_i_5_n_0\
);
\weight_reg[9][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_6\,
Q => \weight_reg[9]_8\(5)
);
\weight_reg[9][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_5\,
Q => \weight_reg[9]_8\(6)
);
\weight_reg[9][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_4\,
Q => \weight_reg[9]_8\(7)
);
\weight_reg[9][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_7\,
Q => \weight_reg[9]_8\(8)
);
\weight_reg[9][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[9][4]_i_1_n_0\,
CO(3) => \weight_reg[9][8]_i_1_n_0\,
CO(2) => \weight_reg[9][8]_i_1_n_1\,
CO(1) => \weight_reg[9][8]_i_1_n_2\,
CO(0) => \weight_reg[9][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__15_n_80\,
DI(2) => \ARG__15_n_81\,
DI(1) => \ARG__15_n_82\,
DI(0) => \ARG__15_n_83\,
O(3) => \weight_reg[9][8]_i_1_n_4\,
O(2) => \weight_reg[9][8]_i_1_n_5\,
O(1) => \weight_reg[9][8]_i_1_n_6\,
O(0) => \weight_reg[9][8]_i_1_n_7\,
S(3) => \weight[9][8]_i_2_n_0\,
S(2) => \weight[9][8]_i_3_n_0\,
S(1) => \weight[9][8]_i_4_n_0\,
S(0) => \weight[9][8]_i_5_n_0\
);
\weight_reg[9][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_6\,
Q => \weight_reg[9]_8\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_addr_decoder is
port (
read_reg_cop_out_ready : out STD_LOGIC;
write_reg_axi_enable : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
\sync_reg_e_k_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\ARG__29\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\cp_controller_cpstate_reg[0]\ : out STD_LOGIC;
\ARG__28\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
\AXI4_Lite_RDATA_tmp_reg[31]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
strobe_sw_cop_in_strobe : in STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
cop_out_ready : in STD_LOGIC;
\wdata_reg[0]\ : in STD_LOGIC;
filter_sum : in STD_LOGIC_VECTOR ( 15 downto 0 );
mul_temp_16 : in STD_LOGIC_VECTOR ( 15 downto 0 );
cp_controller_cpstate : in STD_LOGIC_VECTOR ( 1 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\wdata_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
wr_enb_1_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_addr_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_addr_decoder is
signal \^q\ : STD_LOGIC_VECTOR ( 14 downto 0 );
signal in_strobe : STD_LOGIC;
signal \^write_reg_axi_enable\ : STD_LOGIC;
signal write_reg_d_k : STD_LOGIC_VECTOR ( 15 to 15 );
begin
Q(14 downto 0) <= \^q\(14 downto 0);
write_reg_axi_enable <= \^write_reg_axi_enable\;
\ARG_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(3),
O => DI(0)
);
ARG_carry_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(1),
O => \ARG__29\(2)
);
ARG_carry_i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(0),
O => \ARG__29\(1)
);
ARG_carry_i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(3),
O => \ARG__29\(0)
);
\cp_controller_cpstate[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0F20"
)
port map (
I0 => in_strobe,
I1 => cp_controller_cpstate(1),
I2 => \^write_reg_axi_enable\,
I3 => cp_controller_cpstate(0),
O => \cp_controller_cpstate_reg[0]\
);
read_reg_cop_out_ready_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => AR(0),
D => cop_out_ready,
Q => read_reg_cop_out_ready
);
strobe_reg_cop_in_strobe_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => AR(0),
D => strobe_sw_cop_in_strobe,
Q => in_strobe
);
\sub_temp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => filter_sum(7),
O => \sync_reg_e_k_reg[7]_0\(3)
);
\sub_temp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => filter_sum(6),
O => \sync_reg_e_k_reg[7]_0\(2)
);
\sub_temp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => filter_sum(5),
O => \sync_reg_e_k_reg[7]_0\(1)
);
\sub_temp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => filter_sum(4),
O => \sync_reg_e_k_reg[7]_0\(0)
);
\sub_temp_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(11),
I1 => filter_sum(11),
O => \sync_reg_e_k_reg[11]_0\(3)
);
\sub_temp_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(10),
I1 => filter_sum(10),
O => \sync_reg_e_k_reg[11]_0\(2)
);
\sub_temp_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(9),
I1 => filter_sum(9),
O => \sync_reg_e_k_reg[11]_0\(1)
);
\sub_temp_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => filter_sum(8),
O => \sync_reg_e_k_reg[11]_0\(0)
);
\sub_temp_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => write_reg_d_k(15),
I1 => filter_sum(15),
O => S(3)
);
\sub_temp_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(14),
I1 => filter_sum(14),
O => S(2)
);
\sub_temp_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(13),
I1 => filter_sum(13),
O => S(1)
);
\sub_temp_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(12),
I1 => filter_sum(12),
O => S(0)
);
sub_temp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => filter_sum(3),
O => \sync_reg_e_k_reg[3]_0\(3)
);
sub_temp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => filter_sum(2),
O => \sync_reg_e_k_reg[3]_0\(2)
);
sub_temp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => filter_sum(1),
O => \sync_reg_e_k_reg[3]_0\(1)
);
sub_temp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => filter_sum(0),
O => \sync_reg_e_k_reg[3]_0\(0)
);
\sync_reg_e_k_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(0),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(0)
);
\sync_reg_e_k_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(10),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(10)
);
\sync_reg_e_k_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(11),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(11)
);
\sync_reg_e_k_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(12),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(12)
);
\sync_reg_e_k_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(13),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(13)
);
\sync_reg_e_k_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(14),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(14)
);
\sync_reg_e_k_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(15),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(15)
);
\sync_reg_e_k_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(1),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(1)
);
\sync_reg_e_k_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(2),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(2)
);
\sync_reg_e_k_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(3),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(3)
);
\sync_reg_e_k_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(4),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(4)
);
\sync_reg_e_k_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(5),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(5)
);
\sync_reg_e_k_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(6),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(6)
);
\sync_reg_e_k_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(7),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(7)
);
\sync_reg_e_k_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(8),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(8)
);
\sync_reg_e_k_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(9),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(9)
);
write_reg_axi_enable_reg: unisim.vcomponents.FDPE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
D => \wdata_reg[0]\,
PRE => AR(0),
Q => \^write_reg_axi_enable\
);
\write_reg_d_k_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(0),
Q => \^q\(0)
);
\write_reg_d_k_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(10),
Q => \^q\(10)
);
\write_reg_d_k_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(11),
Q => \^q\(11)
);
\write_reg_d_k_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(12),
Q => \^q\(12)
);
\write_reg_d_k_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(13),
Q => \^q\(13)
);
\write_reg_d_k_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(14),
Q => \^q\(14)
);
\write_reg_d_k_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(15),
Q => write_reg_d_k(15)
);
\write_reg_d_k_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(1),
Q => \^q\(1)
);
\write_reg_d_k_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(2),
Q => \^q\(2)
);
\write_reg_d_k_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(3),
Q => \^q\(3)
);
\write_reg_d_k_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(4),
Q => \^q\(4)
);
\write_reg_d_k_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(5),
Q => \^q\(5)
);
\write_reg_d_k_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(6),
Q => \^q\(6)
);
\write_reg_d_k_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(7),
Q => \^q\(7)
);
\write_reg_d_k_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(8),
Q => \^q\(8)
);
\write_reg_d_k_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(9),
Q => \^q\(9)
);
\write_reg_x_k_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(0),
Q => \ARG__28\(0)
);
\write_reg_x_k_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(10),
Q => \ARG__28\(10)
);
\write_reg_x_k_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(11),
Q => \ARG__28\(11)
);
\write_reg_x_k_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(12),
Q => \ARG__28\(12)
);
\write_reg_x_k_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(13),
Q => \ARG__28\(13)
);
\write_reg_x_k_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(14),
Q => \ARG__28\(14)
);
\write_reg_x_k_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(15),
Q => \ARG__28\(15)
);
\write_reg_x_k_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(1),
Q => \ARG__28\(1)
);
\write_reg_x_k_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(2),
Q => \ARG__28\(2)
);
\write_reg_x_k_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(3),
Q => \ARG__28\(3)
);
\write_reg_x_k_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(4),
Q => \ARG__28\(4)
);
\write_reg_x_k_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(5),
Q => \ARG__28\(5)
);
\write_reg_x_k_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(6),
Q => \ARG__28\(6)
);
\write_reg_x_k_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(7),
Q => \ARG__28\(7)
);
\write_reg_x_k_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(8),
Q => \ARG__28\(8)
);
\write_reg_x_k_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(9),
Q => \ARG__28\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite_module is
port (
AXI4_Lite_RVALID : out STD_LOGIC;
write_reg_axi_enable_reg : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BVALID : out STD_LOGIC;
write_reg_axi_enable_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWREADY : out STD_LOGIC;
strobe_sw_cop_in_strobe : out STD_LOGIC;
\write_reg_d_k_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
write_reg_axi_enable : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_BREADY : in STD_LOGIC;
\sync_reg_e_k_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
read_reg_cop_out_ready : in STD_LOGIC;
AXI4_Lite_RREADY : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite_module;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite_module is
signal \AXI4_Lite_RDATA_tmp[0]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[0]_i_3_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_10_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_11_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_12_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_9_n_0\ : STD_LOGIC;
signal \^axi4_lite_rvalid\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal aw_transfer : STD_LOGIC;
signal \axi_lite_rstate[0]_i_1_n_0\ : STD_LOGIC;
signal axi_lite_wstate : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axi_lite_wstate[0]_i_1_n_0\ : STD_LOGIC;
signal \axi_lite_wstate_next_inferred__1/i__n_0\ : STD_LOGIC;
signal data_read : STD_LOGIC_VECTOR ( 31 downto 0 );
signal reset : STD_LOGIC;
signal sel0 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal soft_reset : STD_LOGIC;
signal soft_reset_i_2_n_0 : STD_LOGIC;
signal soft_reset_i_3_n_0 : STD_LOGIC;
signal soft_reset_i_4_n_0 : STD_LOGIC;
signal strobe_reg_cop_in_strobe_i_3_n_0 : STD_LOGIC;
signal strobe_sw : STD_LOGIC;
signal top_rd_enb : STD_LOGIC;
signal top_wr_enb : STD_LOGIC;
signal w_transfer : STD_LOGIC;
signal write_reg_axi_enable_i_2_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of AXI4_Lite_BVALID_INST_0 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[31]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[31]_i_6\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[31]_i_7\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of AXI4_Lite_WREADY_INST_0 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axi_lite_rstate[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axi_lite_wstate[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \axi_lite_wstate_next_inferred__1/i_\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of strobe_reg_cop_in_strobe_i_3 : label is "soft_lutpair1";
begin
AXI4_Lite_RVALID <= \^axi4_lite_rvalid\;
Q(15 downto 0) <= \^q\(15 downto 0);
AXI4_Lite_ARREADY_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axi4_lite_rvalid\,
O => AXI4_Lite_ARREADY
);
AXI4_Lite_AWREADY_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_lite_wstate(0),
I1 => axi_lite_wstate(1),
O => AXI4_Lite_AWREADY
);
AXI4_Lite_BVALID_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_lite_wstate(1),
I1 => axi_lite_wstate(0),
O => AXI4_Lite_BVALID
);
\AXI4_Lite_RDATA_tmp[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008CCC00008000"
)
port map (
I0 => \sync_reg_e_k_reg[15]\(0),
I1 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[0]_i_2_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I5 => \AXI4_Lite_RDATA_tmp[0]_i_3_n_0\,
O => data_read(0)
);
\AXI4_Lite_RDATA_tmp[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => sel0(6),
I1 => AXI4_Lite_ARADDR(6),
I2 => sel0(0),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(0),
O => \AXI4_Lite_RDATA_tmp[0]_i_2_n_0\
);
\AXI4_Lite_RDATA_tmp[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000B80000000000"
)
port map (
I0 => AXI4_Lite_ARADDR(0),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(0),
I3 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I5 => read_reg_cop_out_ready,
O => \AXI4_Lite_RDATA_tmp[0]_i_3_n_0\
);
\AXI4_Lite_RDATA_tmp[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(10),
O => data_read(10)
);
\AXI4_Lite_RDATA_tmp[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(11),
O => data_read(11)
);
\AXI4_Lite_RDATA_tmp[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(12),
O => data_read(12)
);
\AXI4_Lite_RDATA_tmp[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(13),
O => data_read(13)
);
\AXI4_Lite_RDATA_tmp[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(14),
O => data_read(14)
);
\AXI4_Lite_RDATA_tmp[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(1),
O => data_read(1)
);
\AXI4_Lite_RDATA_tmp[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(2),
O => data_read(2)
);
\AXI4_Lite_RDATA_tmp[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => AXI4_Lite_ARVALID,
I1 => \^axi4_lite_rvalid\,
O => top_rd_enb
);
\AXI4_Lite_RDATA_tmp[31]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEEF0EE"
)
port map (
I0 => sel0(5),
I1 => sel0(4),
I2 => AXI4_Lite_ARADDR(5),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(4),
O => \AXI4_Lite_RDATA_tmp[31]_i_10_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEEF0EE"
)
port map (
I0 => sel0(3),
I1 => sel0(2),
I2 => AXI4_Lite_ARADDR(3),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(2),
O => \AXI4_Lite_RDATA_tmp[31]_i_11_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEEF0EE"
)
port map (
I0 => sel0(9),
I1 => sel0(8),
I2 => AXI4_Lite_ARADDR(9),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(8),
O => \AXI4_Lite_RDATA_tmp[31]_i_12_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(15),
O => data_read(31)
);
\AXI4_Lite_RDATA_tmp[31]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => AXI4_Lite_ARESETN,
O => reset
);
\AXI4_Lite_RDATA_tmp[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEFEFFFFAEFEA"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_9_n_0\,
I1 => AXI4_Lite_ARADDR(10),
I2 => AXI4_Lite_ARVALID,
I3 => sel0(10),
I4 => AXI4_Lite_ARADDR(11),
I5 => sel0(11),
O => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => AXI4_Lite_ARADDR(1),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(1),
O => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => AXI4_Lite_ARADDR(6),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(6),
O => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => AXI4_Lite_ARADDR(0),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(0),
O => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"00011101"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_10_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_11_n_0\,
I2 => sel0(7),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(7),
O => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFBBFCB8"
)
port map (
I0 => AXI4_Lite_ARADDR(13),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(13),
I3 => AXI4_Lite_ARADDR(12),
I4 => sel0(12),
I5 => \AXI4_Lite_RDATA_tmp[31]_i_12_n_0\,
O => \AXI4_Lite_RDATA_tmp[31]_i_9_n_0\
);
\AXI4_Lite_RDATA_tmp[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(3),
O => data_read(3)
);
\AXI4_Lite_RDATA_tmp[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(4),
O => data_read(4)
);
\AXI4_Lite_RDATA_tmp[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(5),
O => data_read(5)
);
\AXI4_Lite_RDATA_tmp[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(6),
O => data_read(6)
);
\AXI4_Lite_RDATA_tmp[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(7),
O => data_read(7)
);
\AXI4_Lite_RDATA_tmp[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(8),
O => data_read(8)
);
\AXI4_Lite_RDATA_tmp[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(9),
O => data_read(9)
);
\AXI4_Lite_RDATA_tmp_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(0),
Q => AXI4_Lite_RDATA(0)
);
\AXI4_Lite_RDATA_tmp_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(10),
Q => AXI4_Lite_RDATA(10)
);
\AXI4_Lite_RDATA_tmp_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(11),
Q => AXI4_Lite_RDATA(11)
);
\AXI4_Lite_RDATA_tmp_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(12),
Q => AXI4_Lite_RDATA(12)
);
\AXI4_Lite_RDATA_tmp_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(13),
Q => AXI4_Lite_RDATA(13)
);
\AXI4_Lite_RDATA_tmp_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(14),
Q => AXI4_Lite_RDATA(14)
);
\AXI4_Lite_RDATA_tmp_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(1),
Q => AXI4_Lite_RDATA(1)
);
\AXI4_Lite_RDATA_tmp_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(2),
Q => AXI4_Lite_RDATA(2)
);
\AXI4_Lite_RDATA_tmp_reg[31]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(31),
Q => AXI4_Lite_RDATA(15)
);
\AXI4_Lite_RDATA_tmp_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(3),
Q => AXI4_Lite_RDATA(3)
);
\AXI4_Lite_RDATA_tmp_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(4),
Q => AXI4_Lite_RDATA(4)
);
\AXI4_Lite_RDATA_tmp_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(5),
Q => AXI4_Lite_RDATA(5)
);
\AXI4_Lite_RDATA_tmp_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(6),
Q => AXI4_Lite_RDATA(6)
);
\AXI4_Lite_RDATA_tmp_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(7),
Q => AXI4_Lite_RDATA(7)
);
\AXI4_Lite_RDATA_tmp_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(8),
Q => AXI4_Lite_RDATA(8)
);
\AXI4_Lite_RDATA_tmp_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(9),
Q => AXI4_Lite_RDATA(9)
);
AXI4_Lite_WREADY_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_lite_wstate(0),
I1 => axi_lite_wstate(1),
O => AXI4_Lite_WREADY
);
\axi_lite_rstate[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => AXI4_Lite_RREADY,
I1 => \^axi4_lite_rvalid\,
I2 => AXI4_Lite_ARVALID,
O => \axi_lite_rstate[0]_i_1_n_0\
);
\axi_lite_rstate_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => \axi_lite_rstate[0]_i_1_n_0\,
Q => \^axi4_lite_rvalid\
);
\axi_lite_wstate[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"002E"
)
port map (
I0 => AXI4_Lite_AWVALID,
I1 => axi_lite_wstate(0),
I2 => AXI4_Lite_WVALID,
I3 => axi_lite_wstate(1),
O => \axi_lite_wstate[0]_i_1_n_0\
);
\axi_lite_wstate_next_inferred__1/i_\: unisim.vcomponents.LUT4
generic map(
INIT => X"0838"
)
port map (
I0 => AXI4_Lite_WVALID,
I1 => axi_lite_wstate(0),
I2 => axi_lite_wstate(1),
I3 => AXI4_Lite_BREADY,
O => \axi_lite_wstate_next_inferred__1/i__n_0\
);
\axi_lite_wstate_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => \axi_lite_wstate[0]_i_1_n_0\,
Q => axi_lite_wstate(0)
);
\axi_lite_wstate_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => \axi_lite_wstate_next_inferred__1/i__n_0\,
Q => axi_lite_wstate(1)
);
soft_reset_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => soft_reset_i_2_n_0,
I1 => sel0(1),
I2 => sel0(0),
I3 => sel0(7),
I4 => sel0(6),
I5 => soft_reset_i_3_n_0,
O => strobe_sw
);
soft_reset_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => sel0(13),
I1 => sel0(12),
I2 => sel0(11),
I3 => sel0(10),
O => soft_reset_i_2_n_0
);
soft_reset_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => sel0(2),
I1 => sel0(3),
I2 => sel0(8),
I3 => sel0(9),
I4 => soft_reset_i_4_n_0,
O => soft_reset_i_3_n_0
);
soft_reset_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => top_wr_enb,
I1 => \^q\(0),
I2 => sel0(5),
I3 => sel0(4),
O => soft_reset_i_4_n_0
);
soft_reset_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => strobe_sw,
Q => soft_reset
);
strobe_reg_cop_in_strobe_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020000000"
)
port map (
I0 => \^q\(0),
I1 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I2 => strobe_reg_cop_in_strobe_i_3_n_0,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I4 => top_wr_enb,
I5 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
O => strobe_sw_cop_in_strobe
);
strobe_reg_cop_in_strobe_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => AXI4_Lite_ARESETN,
I1 => soft_reset,
I2 => IPCORE_RESETN,
O => write_reg_axi_enable_reg
);
strobe_reg_cop_in_strobe_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => sel0(1),
I1 => AXI4_Lite_ARADDR(1),
I2 => sel0(0),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(0),
O => strobe_reg_cop_in_strobe_i_3_n_0
);
\waddr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => AXI4_Lite_AWVALID,
I1 => axi_lite_wstate(1),
I2 => axi_lite_wstate(0),
O => aw_transfer
);
\waddr_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(8),
Q => sel0(8)
);
\waddr_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(9),
Q => sel0(9)
);
\waddr_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(10),
Q => sel0(10)
);
\waddr_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(11),
Q => sel0(11)
);
\waddr_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(12),
Q => sel0(12)
);
\waddr_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(13),
Q => sel0(13)
);
\waddr_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(0),
Q => sel0(0)
);
\waddr_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(1),
Q => sel0(1)
);
\waddr_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(2),
Q => sel0(2)
);
\waddr_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(3),
Q => sel0(3)
);
\waddr_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(4),
Q => sel0(4)
);
\waddr_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(5),
Q => sel0(5)
);
\waddr_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(6),
Q => sel0(6)
);
\waddr_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(7),
Q => sel0(7)
);
\wdata[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => AXI4_Lite_WVALID,
I1 => axi_lite_wstate(1),
I2 => axi_lite_wstate(0),
O => w_transfer
);
\wdata_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(0),
Q => \^q\(0)
);
\wdata_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(10),
Q => \^q\(10)
);
\wdata_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(11),
Q => \^q\(11)
);
\wdata_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(12),
Q => \^q\(12)
);
\wdata_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(13),
Q => \^q\(13)
);
\wdata_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(14),
Q => \^q\(14)
);
\wdata_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(15),
Q => \^q\(15)
);
\wdata_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(1),
Q => \^q\(1)
);
\wdata_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(2),
Q => \^q\(2)
);
\wdata_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(3),
Q => \^q\(3)
);
\wdata_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(4),
Q => \^q\(4)
);
\wdata_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(5),
Q => \^q\(5)
);
\wdata_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(6),
Q => \^q\(6)
);
\wdata_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(7),
Q => \^q\(7)
);
\wdata_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(8),
Q => \^q\(8)
);
\wdata_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(9),
Q => \^q\(9)
);
wr_enb_1_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => w_transfer,
Q => top_wr_enb
);
write_reg_axi_enable_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFFF00008000"
)
port map (
I0 => \^q\(0),
I1 => write_reg_axi_enable_i_2_n_0,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I3 => top_wr_enb,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I5 => write_reg_axi_enable,
O => write_reg_axi_enable_reg_0
);
write_reg_axi_enable_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => AXI4_Lite_ARADDR(6),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(6),
I3 => AXI4_Lite_ARADDR(0),
I4 => sel0(0),
I5 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
O => write_reg_axi_enable_i_2_n_0
);
\write_reg_d_k[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I4 => top_wr_enb,
I5 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
O => \write_reg_d_k_reg[15]\(0)
);
\write_reg_x_k[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I4 => top_wr_enb,
I5 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
O => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_cop is
port (
cp_controller_cpstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
cop_out_ready : out STD_LOGIC;
cop_dut_enable : out STD_LOGIC;
strobe_reg_cop_in_strobe_reg : in STD_LOGIC;
IPCORE_CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
write_reg_axi_enable : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_cop;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_cop is
signal \^cp_controller_cpstate\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cp_controller_cpstate[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cp_controller_cpstate[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of read_reg_cop_out_ready_i_1 : label is "soft_lutpair5";
begin
cp_controller_cpstate(1 downto 0) <= \^cp_controller_cpstate\(1 downto 0);
\cp_controller_cpstate[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"38"
)
port map (
I0 => \^cp_controller_cpstate\(0),
I1 => write_reg_axi_enable,
I2 => \^cp_controller_cpstate\(1),
O => \cp_controller_cpstate[1]_i_1_n_0\
);
\cp_controller_cpstate_reg[0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => '1',
CLR => AR(0),
D => strobe_reg_cop_in_strobe_reg,
Q => \^cp_controller_cpstate\(0)
);
\cp_controller_cpstate_reg[1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => '1',
CLR => AR(0),
D => \cp_controller_cpstate[1]_i_1_n_0\,
Q => \^cp_controller_cpstate\(1)
);
\data_pipeline_tmp[14][15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^cp_controller_cpstate\(0),
I1 => \^cp_controller_cpstate\(1),
O => cop_dut_enable
);
read_reg_cop_out_ready_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cp_controller_cpstate\(0),
I1 => \^cp_controller_cpstate\(1),
O => cop_out_ready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite is
port (
write_reg_axi_enable_reg : out STD_LOGIC;
AXI4_Lite_RVALID : out STD_LOGIC;
write_reg_axi_enable : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BVALID : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
\sync_reg_e_k_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\ARG__29\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\cp_controller_cpstate_reg[0]\ : out STD_LOGIC;
\ARG__28\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
cop_out_ready : in STD_LOGIC;
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
filter_sum : in STD_LOGIC_VECTOR ( 15 downto 0 );
mul_temp_16 : in STD_LOGIC_VECTOR ( 15 downto 0 );
cp_controller_cpstate : in STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_BREADY : in STD_LOGIC;
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_RREADY : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite is
signal read_reg_cop_out_ready : STD_LOGIC;
signal reg_enb_d_k : STD_LOGIC;
signal reg_enb_x_k : STD_LOGIC;
signal strobe_sw_cop_in_strobe : STD_LOGIC;
signal sync_reg_e_k : STD_LOGIC_VECTOR ( 15 downto 0 );
signal top_data_write : STD_LOGIC_VECTOR ( 0 to 0 );
signal u_lms_pcore_axi_lite_module_inst_n_10 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_11 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_12 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_13 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_14 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_15 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_16 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_17 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_18 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_19 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_4 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_5 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_6 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_7 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_8 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_9 : STD_LOGIC;
signal \^write_reg_axi_enable\ : STD_LOGIC;
signal \^write_reg_axi_enable_reg\ : STD_LOGIC;
begin
write_reg_axi_enable <= \^write_reg_axi_enable\;
write_reg_axi_enable_reg <= \^write_reg_axi_enable_reg\;
u_lms_pcore_addr_decoder_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_addr_decoder
port map (
AR(0) => \^write_reg_axi_enable_reg\,
\ARG__28\(15 downto 0) => \ARG__28\(15 downto 0),
\ARG__29\(2 downto 0) => \ARG__29\(2 downto 0),
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
\AXI4_Lite_RDATA_tmp_reg[31]\(15 downto 0) => sync_reg_e_k(15 downto 0),
DI(0) => DI(0),
E(0) => reg_enb_x_k,
Q(14 downto 0) => Q(14 downto 0),
S(3 downto 0) => S(3 downto 0),
cop_out_ready => cop_out_ready,
cp_controller_cpstate(1 downto 0) => cp_controller_cpstate(1 downto 0),
\cp_controller_cpstate_reg[0]\ => \cp_controller_cpstate_reg[0]\,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => mul_temp_16(15 downto 0),
read_reg_cop_out_ready => read_reg_cop_out_ready,
strobe_sw_cop_in_strobe => strobe_sw_cop_in_strobe,
\sync_reg_e_k_reg[11]_0\(3 downto 0) => \sync_reg_e_k_reg[11]\(3 downto 0),
\sync_reg_e_k_reg[3]_0\(3 downto 0) => \sync_reg_e_k_reg[3]\(3 downto 0),
\sync_reg_e_k_reg[7]_0\(3 downto 0) => \sync_reg_e_k_reg[7]\(3 downto 0),
\wdata_reg[0]\ => u_lms_pcore_axi_lite_module_inst_n_4,
\wdata_reg[15]\(15) => u_lms_pcore_axi_lite_module_inst_n_5,
\wdata_reg[15]\(14) => u_lms_pcore_axi_lite_module_inst_n_6,
\wdata_reg[15]\(13) => u_lms_pcore_axi_lite_module_inst_n_7,
\wdata_reg[15]\(12) => u_lms_pcore_axi_lite_module_inst_n_8,
\wdata_reg[15]\(11) => u_lms_pcore_axi_lite_module_inst_n_9,
\wdata_reg[15]\(10) => u_lms_pcore_axi_lite_module_inst_n_10,
\wdata_reg[15]\(9) => u_lms_pcore_axi_lite_module_inst_n_11,
\wdata_reg[15]\(8) => u_lms_pcore_axi_lite_module_inst_n_12,
\wdata_reg[15]\(7) => u_lms_pcore_axi_lite_module_inst_n_13,
\wdata_reg[15]\(6) => u_lms_pcore_axi_lite_module_inst_n_14,
\wdata_reg[15]\(5) => u_lms_pcore_axi_lite_module_inst_n_15,
\wdata_reg[15]\(4) => u_lms_pcore_axi_lite_module_inst_n_16,
\wdata_reg[15]\(3) => u_lms_pcore_axi_lite_module_inst_n_17,
\wdata_reg[15]\(2) => u_lms_pcore_axi_lite_module_inst_n_18,
\wdata_reg[15]\(1) => u_lms_pcore_axi_lite_module_inst_n_19,
\wdata_reg[15]\(0) => top_data_write(0),
wr_enb_1_reg(0) => reg_enb_d_k,
write_reg_axi_enable => \^write_reg_axi_enable\
);
u_lms_pcore_axi_lite_module_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite_module
port map (
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
AXI4_Lite_ARADDR(13 downto 0) => AXI4_Lite_ARADDR(13 downto 0),
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN,
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY,
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID,
AXI4_Lite_AWADDR(13 downto 0) => AXI4_Lite_AWADDR(13 downto 0),
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY,
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID,
AXI4_Lite_BREADY => AXI4_Lite_BREADY,
AXI4_Lite_BVALID => AXI4_Lite_BVALID,
AXI4_Lite_RDATA(15 downto 0) => AXI4_Lite_RDATA(15 downto 0),
AXI4_Lite_RREADY => AXI4_Lite_RREADY,
AXI4_Lite_RVALID => AXI4_Lite_RVALID,
AXI4_Lite_WDATA(15 downto 0) => AXI4_Lite_WDATA(15 downto 0),
AXI4_Lite_WREADY => AXI4_Lite_WREADY,
AXI4_Lite_WVALID => AXI4_Lite_WVALID,
E(0) => reg_enb_x_k,
IPCORE_RESETN => IPCORE_RESETN,
Q(15) => u_lms_pcore_axi_lite_module_inst_n_5,
Q(14) => u_lms_pcore_axi_lite_module_inst_n_6,
Q(13) => u_lms_pcore_axi_lite_module_inst_n_7,
Q(12) => u_lms_pcore_axi_lite_module_inst_n_8,
Q(11) => u_lms_pcore_axi_lite_module_inst_n_9,
Q(10) => u_lms_pcore_axi_lite_module_inst_n_10,
Q(9) => u_lms_pcore_axi_lite_module_inst_n_11,
Q(8) => u_lms_pcore_axi_lite_module_inst_n_12,
Q(7) => u_lms_pcore_axi_lite_module_inst_n_13,
Q(6) => u_lms_pcore_axi_lite_module_inst_n_14,
Q(5) => u_lms_pcore_axi_lite_module_inst_n_15,
Q(4) => u_lms_pcore_axi_lite_module_inst_n_16,
Q(3) => u_lms_pcore_axi_lite_module_inst_n_17,
Q(2) => u_lms_pcore_axi_lite_module_inst_n_18,
Q(1) => u_lms_pcore_axi_lite_module_inst_n_19,
Q(0) => top_data_write(0),
read_reg_cop_out_ready => read_reg_cop_out_ready,
strobe_sw_cop_in_strobe => strobe_sw_cop_in_strobe,
\sync_reg_e_k_reg[15]\(15 downto 0) => sync_reg_e_k(15 downto 0),
write_reg_axi_enable => \^write_reg_axi_enable\,
write_reg_axi_enable_reg => \^write_reg_axi_enable_reg\,
write_reg_axi_enable_reg_0 => u_lms_pcore_axi_lite_module_inst_n_4,
\write_reg_d_k_reg[15]\(0) => reg_enb_d_k
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_dut is
port (
mul_temp_16 : out STD_LOGIC_VECTOR ( 15 downto 0 );
filter_sum : out STD_LOGIC_VECTOR ( 15 downto 0 );
\write_reg_x_k_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
cop_dut_enable : in STD_LOGIC;
IPCORE_CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\write_reg_d_k_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
DI : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 14 downto 0 );
\write_reg_d_k_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_dut;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_dut is
begin
u_LMS: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_LMS
port map (
AR(0) => AR(0),
DI(0) => DI(0),
IPCORE_CLK => IPCORE_CLK,
Q(14 downto 0) => Q(14 downto 0),
S(3 downto 0) => S(3 downto 0),
cop_dut_enable => cop_dut_enable,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => mul_temp_16(15 downto 0),
\write_reg_d_k_reg[11]\(3 downto 0) => \write_reg_d_k_reg[11]\(3 downto 0),
\write_reg_d_k_reg[3]\(2 downto 0) => \write_reg_d_k_reg[3]\(2 downto 0),
\write_reg_d_k_reg[3]_0\(3 downto 0) => \write_reg_d_k_reg[3]_0\(3 downto 0),
\write_reg_d_k_reg[7]\(3 downto 0) => \write_reg_d_k_reg[7]\(3 downto 0),
\write_reg_x_k_reg[15]\(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore is
port (
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BVALID : out STD_LOGIC;
AXI4_Lite_RVALID : out STD_LOGIC;
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
IPCORE_CLK : in STD_LOGIC;
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_RREADY : in STD_LOGIC;
AXI4_Lite_BREADY : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore is
signal cop_dut_enable : STD_LOGIC;
signal cop_out_ready : STD_LOGIC;
signal cp_controller_cpstate : STD_LOGIC_VECTOR ( 1 downto 0 );
signal filter_sum : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \u_LMS/mul_temp_16\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal u_lms_pcore_axi_lite_inst_n_0 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_24 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_25 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_26 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_27 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_28 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_29 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_30 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_31 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_32 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_33 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_34 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_35 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_36 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_37 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_38 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_39 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_40 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_5 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_6 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_7 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_8 : STD_LOGIC;
signal write_reg_axi_enable : STD_LOGIC;
signal write_reg_d_k : STD_LOGIC_VECTOR ( 14 downto 0 );
signal write_reg_x_k : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
u_lms_pcore_axi_lite_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite
port map (
\ARG__28\(15 downto 0) => write_reg_x_k(15 downto 0),
\ARG__29\(2) => u_lms_pcore_axi_lite_inst_n_37,
\ARG__29\(1) => u_lms_pcore_axi_lite_inst_n_38,
\ARG__29\(0) => u_lms_pcore_axi_lite_inst_n_39,
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
AXI4_Lite_ARADDR(13 downto 0) => AXI4_Lite_ARADDR(13 downto 0),
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN,
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY,
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID,
AXI4_Lite_AWADDR(13 downto 0) => AXI4_Lite_AWADDR(13 downto 0),
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY,
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID,
AXI4_Lite_BREADY => AXI4_Lite_BREADY,
AXI4_Lite_BVALID => AXI4_Lite_BVALID,
AXI4_Lite_RDATA(15 downto 0) => AXI4_Lite_RDATA(15 downto 0),
AXI4_Lite_RREADY => AXI4_Lite_RREADY,
AXI4_Lite_RVALID => AXI4_Lite_RVALID,
AXI4_Lite_WDATA(15 downto 0) => AXI4_Lite_WDATA(15 downto 0),
AXI4_Lite_WREADY => AXI4_Lite_WREADY,
AXI4_Lite_WVALID => AXI4_Lite_WVALID,
DI(0) => u_lms_pcore_axi_lite_inst_n_36,
IPCORE_RESETN => IPCORE_RESETN,
Q(14 downto 0) => write_reg_d_k(14 downto 0),
S(3) => u_lms_pcore_axi_lite_inst_n_5,
S(2) => u_lms_pcore_axi_lite_inst_n_6,
S(1) => u_lms_pcore_axi_lite_inst_n_7,
S(0) => u_lms_pcore_axi_lite_inst_n_8,
cop_out_ready => cop_out_ready,
cp_controller_cpstate(1 downto 0) => cp_controller_cpstate(1 downto 0),
\cp_controller_cpstate_reg[0]\ => u_lms_pcore_axi_lite_inst_n_40,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => \u_LMS/mul_temp_16\(15 downto 0),
\sync_reg_e_k_reg[11]\(3) => u_lms_pcore_axi_lite_inst_n_24,
\sync_reg_e_k_reg[11]\(2) => u_lms_pcore_axi_lite_inst_n_25,
\sync_reg_e_k_reg[11]\(1) => u_lms_pcore_axi_lite_inst_n_26,
\sync_reg_e_k_reg[11]\(0) => u_lms_pcore_axi_lite_inst_n_27,
\sync_reg_e_k_reg[3]\(3) => u_lms_pcore_axi_lite_inst_n_32,
\sync_reg_e_k_reg[3]\(2) => u_lms_pcore_axi_lite_inst_n_33,
\sync_reg_e_k_reg[3]\(1) => u_lms_pcore_axi_lite_inst_n_34,
\sync_reg_e_k_reg[3]\(0) => u_lms_pcore_axi_lite_inst_n_35,
\sync_reg_e_k_reg[7]\(3) => u_lms_pcore_axi_lite_inst_n_28,
\sync_reg_e_k_reg[7]\(2) => u_lms_pcore_axi_lite_inst_n_29,
\sync_reg_e_k_reg[7]\(1) => u_lms_pcore_axi_lite_inst_n_30,
\sync_reg_e_k_reg[7]\(0) => u_lms_pcore_axi_lite_inst_n_31,
write_reg_axi_enable => write_reg_axi_enable,
write_reg_axi_enable_reg => u_lms_pcore_axi_lite_inst_n_0
);
u_lms_pcore_cop_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_cop
port map (
AR(0) => u_lms_pcore_axi_lite_inst_n_0,
IPCORE_CLK => IPCORE_CLK,
cop_dut_enable => cop_dut_enable,
cop_out_ready => cop_out_ready,
cp_controller_cpstate(1 downto 0) => cp_controller_cpstate(1 downto 0),
strobe_reg_cop_in_strobe_reg => u_lms_pcore_axi_lite_inst_n_40,
write_reg_axi_enable => write_reg_axi_enable
);
u_lms_pcore_dut_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_dut
port map (
AR(0) => u_lms_pcore_axi_lite_inst_n_0,
DI(0) => u_lms_pcore_axi_lite_inst_n_36,
IPCORE_CLK => IPCORE_CLK,
Q(14 downto 0) => write_reg_d_k(14 downto 0),
S(3) => u_lms_pcore_axi_lite_inst_n_5,
S(2) => u_lms_pcore_axi_lite_inst_n_6,
S(1) => u_lms_pcore_axi_lite_inst_n_7,
S(0) => u_lms_pcore_axi_lite_inst_n_8,
cop_dut_enable => cop_dut_enable,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => \u_LMS/mul_temp_16\(15 downto 0),
\write_reg_d_k_reg[11]\(3) => u_lms_pcore_axi_lite_inst_n_24,
\write_reg_d_k_reg[11]\(2) => u_lms_pcore_axi_lite_inst_n_25,
\write_reg_d_k_reg[11]\(1) => u_lms_pcore_axi_lite_inst_n_26,
\write_reg_d_k_reg[11]\(0) => u_lms_pcore_axi_lite_inst_n_27,
\write_reg_d_k_reg[3]\(2) => u_lms_pcore_axi_lite_inst_n_37,
\write_reg_d_k_reg[3]\(1) => u_lms_pcore_axi_lite_inst_n_38,
\write_reg_d_k_reg[3]\(0) => u_lms_pcore_axi_lite_inst_n_39,
\write_reg_d_k_reg[3]_0\(3) => u_lms_pcore_axi_lite_inst_n_32,
\write_reg_d_k_reg[3]_0\(2) => u_lms_pcore_axi_lite_inst_n_33,
\write_reg_d_k_reg[3]_0\(1) => u_lms_pcore_axi_lite_inst_n_34,
\write_reg_d_k_reg[3]_0\(0) => u_lms_pcore_axi_lite_inst_n_35,
\write_reg_d_k_reg[7]\(3) => u_lms_pcore_axi_lite_inst_n_28,
\write_reg_d_k_reg[7]\(2) => u_lms_pcore_axi_lite_inst_n_29,
\write_reg_d_k_reg[7]\(1) => u_lms_pcore_axi_lite_inst_n_30,
\write_reg_d_k_reg[7]\(0) => u_lms_pcore_axi_lite_inst_n_31,
\write_reg_x_k_reg[15]\(15 downto 0) => write_reg_x_k(15 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
IPCORE_CLK : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_BREADY : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_RREADY : in STD_LOGIC;
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_BVALID : out STD_LOGIC;
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_RVALID : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_lms_pcore_0_0,lms_pcore,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "lms_pcore,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal \<const0>\ : STD_LOGIC;
signal \^axi4_lite_rdata\ : STD_LOGIC_VECTOR ( 30 downto 0 );
attribute x_interface_info : string;
attribute x_interface_info of AXI4_Lite_ACLK : signal is "xilinx.com:signal:clock:1.0 AXI4_Lite_ACLK CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of AXI4_Lite_ACLK : signal is "XIL_INTERFACENAME AXI4_Lite_ACLK, ASSOCIATED_RESET AXI4_Lite_ARESETN, ASSOCIATED_BUSIF AXI4_Lite, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of AXI4_Lite_ARESETN : signal is "xilinx.com:signal:reset:1.0 AXI4_Lite_ARESETN RST";
attribute x_interface_parameter of AXI4_Lite_ARESETN : signal is "XIL_INTERFACENAME AXI4_Lite_ARESETN, POLARITY ACTIVE_LOW";
attribute x_interface_info of AXI4_Lite_ARREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite ARREADY";
attribute x_interface_info of AXI4_Lite_ARVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite ARVALID";
attribute x_interface_info of AXI4_Lite_AWREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite AWREADY";
attribute x_interface_info of AXI4_Lite_AWVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite AWVALID";
attribute x_interface_info of AXI4_Lite_BREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite BREADY";
attribute x_interface_info of AXI4_Lite_BVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite BVALID";
attribute x_interface_info of AXI4_Lite_RREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RREADY";
attribute x_interface_info of AXI4_Lite_RVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RVALID";
attribute x_interface_info of AXI4_Lite_WREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WREADY";
attribute x_interface_info of AXI4_Lite_WVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WVALID";
attribute x_interface_info of IPCORE_CLK : signal is "xilinx.com:signal:clock:1.0 IPCORE_CLK CLK";
attribute x_interface_parameter of IPCORE_CLK : signal is "XIL_INTERFACENAME IPCORE_CLK, ASSOCIATED_RESET IPCORE_RESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of IPCORE_RESETN : signal is "xilinx.com:signal:reset:1.0 IPCORE_RESETN RST";
attribute x_interface_parameter of IPCORE_RESETN : signal is "XIL_INTERFACENAME IPCORE_RESETN, POLARITY ACTIVE_LOW";
attribute x_interface_info of AXI4_Lite_ARADDR : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite ARADDR";
attribute x_interface_info of AXI4_Lite_AWADDR : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite AWADDR";
attribute x_interface_parameter of AXI4_Lite_AWADDR : signal is "XIL_INTERFACENAME AXI4_Lite, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute x_interface_info of AXI4_Lite_BRESP : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite BRESP";
attribute x_interface_info of AXI4_Lite_RDATA : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RDATA";
attribute x_interface_info of AXI4_Lite_RRESP : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RRESP";
attribute x_interface_info of AXI4_Lite_WDATA : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WDATA";
attribute x_interface_info of AXI4_Lite_WSTRB : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WSTRB";
begin
AXI4_Lite_BRESP(1) <= \<const0>\;
AXI4_Lite_BRESP(0) <= \<const0>\;
AXI4_Lite_RDATA(31) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(30) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(29) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(28) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(27) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(26) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(25) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(24) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(23) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(22) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(21) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(20) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(19) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(18) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(17) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(16) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(15) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(14 downto 0) <= \^axi4_lite_rdata\(14 downto 0);
AXI4_Lite_RRESP(1) <= \<const0>\;
AXI4_Lite_RRESP(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore
port map (
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
AXI4_Lite_ARADDR(13 downto 0) => AXI4_Lite_ARADDR(15 downto 2),
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN,
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY,
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID,
AXI4_Lite_AWADDR(13 downto 0) => AXI4_Lite_AWADDR(15 downto 2),
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY,
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID,
AXI4_Lite_BREADY => AXI4_Lite_BREADY,
AXI4_Lite_BVALID => AXI4_Lite_BVALID,
AXI4_Lite_RDATA(15) => \^axi4_lite_rdata\(30),
AXI4_Lite_RDATA(14 downto 0) => \^axi4_lite_rdata\(14 downto 0),
AXI4_Lite_RREADY => AXI4_Lite_RREADY,
AXI4_Lite_RVALID => AXI4_Lite_RVALID,
AXI4_Lite_WDATA(15 downto 0) => AXI4_Lite_WDATA(15 downto 0),
AXI4_Lite_WREADY => AXI4_Lite_WREADY,
AXI4_Lite_WVALID => AXI4_Lite_WVALID,
IPCORE_CLK => IPCORE_CLK,
IPCORE_RESETN => IPCORE_RESETN
);
end STRUCTURE;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu Jun 01 02:26:48 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/examples/test_cdma/test_cdma.srcs/sources_1/bd/system/ip/system_axi_datamover_0_0/system_axi_datamover_0_0_stub.vhdl
-- Design : system_axi_datamover_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_axi_datamover_0_0 is
Port (
m_axi_mm2s_aclk : in STD_LOGIC;
m_axi_mm2s_aresetn : in STD_LOGIC;
mm2s_err : out STD_LOGIC;
m_axis_mm2s_cmdsts_aclk : in STD_LOGIC;
m_axis_mm2s_cmdsts_aresetn : in STD_LOGIC;
s_axis_mm2s_cmd_tvalid : in STD_LOGIC;
s_axis_mm2s_cmd_tready : out STD_LOGIC;
s_axis_mm2s_cmd_tdata : in STD_LOGIC_VECTOR ( 71 downto 0 );
m_axis_mm2s_sts_tvalid : out STD_LOGIC;
m_axis_mm2s_sts_tready : in STD_LOGIC;
m_axis_mm2s_sts_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_mm2s_sts_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_mm2s_sts_tlast : out STD_LOGIC;
m_axi_mm2s_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_aruser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tlast : out STD_LOGIC;
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axi_s2mm_aclk : in STD_LOGIC;
m_axi_s2mm_aresetn : in STD_LOGIC;
s2mm_err : out STD_LOGIC;
m_axis_s2mm_cmdsts_awclk : in STD_LOGIC;
m_axis_s2mm_cmdsts_aresetn : in STD_LOGIC;
s_axis_s2mm_cmd_tvalid : in STD_LOGIC;
s_axis_s2mm_cmd_tready : out STD_LOGIC;
s_axis_s2mm_cmd_tdata : in STD_LOGIC_VECTOR ( 71 downto 0 );
m_axis_s2mm_sts_tvalid : out STD_LOGIC;
m_axis_s2mm_sts_tready : in STD_LOGIC;
m_axis_s2mm_sts_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_s2mm_sts_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_s2mm_sts_tlast : out STD_LOGIC;
m_axi_s2mm_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awvalid : out STD_LOGIC;
m_axi_s2mm_awready : in STD_LOGIC;
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_wlast : out STD_LOGIC;
m_axi_s2mm_wvalid : out STD_LOGIC;
m_axi_s2mm_wready : in STD_LOGIC;
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_bvalid : in STD_LOGIC;
m_axi_s2mm_bready : out STD_LOGIC;
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_s2mm_tlast : in STD_LOGIC;
s_axis_s2mm_tvalid : in STD_LOGIC;
s_axis_s2mm_tready : out STD_LOGIC
);
end system_axi_datamover_0_0;
architecture stub of system_axi_datamover_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "m_axi_mm2s_aclk,m_axi_mm2s_aresetn,mm2s_err,m_axis_mm2s_cmdsts_aclk,m_axis_mm2s_cmdsts_aresetn,s_axis_mm2s_cmd_tvalid,s_axis_mm2s_cmd_tready,s_axis_mm2s_cmd_tdata[71:0],m_axis_mm2s_sts_tvalid,m_axis_mm2s_sts_tready,m_axis_mm2s_sts_tdata[7:0],m_axis_mm2s_sts_tkeep[0:0],m_axis_mm2s_sts_tlast,m_axi_mm2s_arid[3:0],m_axi_mm2s_araddr[31:0],m_axi_mm2s_arlen[7:0],m_axi_mm2s_arsize[2:0],m_axi_mm2s_arburst[1:0],m_axi_mm2s_arprot[2:0],m_axi_mm2s_arcache[3:0],m_axi_mm2s_aruser[3:0],m_axi_mm2s_arvalid,m_axi_mm2s_arready,m_axi_mm2s_rdata[31:0],m_axi_mm2s_rresp[1:0],m_axi_mm2s_rlast,m_axi_mm2s_rvalid,m_axi_mm2s_rready,m_axis_mm2s_tdata[31:0],m_axis_mm2s_tkeep[3:0],m_axis_mm2s_tlast,m_axis_mm2s_tvalid,m_axis_mm2s_tready,m_axi_s2mm_aclk,m_axi_s2mm_aresetn,s2mm_err,m_axis_s2mm_cmdsts_awclk,m_axis_s2mm_cmdsts_aresetn,s_axis_s2mm_cmd_tvalid,s_axis_s2mm_cmd_tready,s_axis_s2mm_cmd_tdata[71:0],m_axis_s2mm_sts_tvalid,m_axis_s2mm_sts_tready,m_axis_s2mm_sts_tdata[7:0],m_axis_s2mm_sts_tkeep[0:0],m_axis_s2mm_sts_tlast,m_axi_s2mm_awid[3:0],m_axi_s2mm_awaddr[31:0],m_axi_s2mm_awlen[7:0],m_axi_s2mm_awsize[2:0],m_axi_s2mm_awburst[1:0],m_axi_s2mm_awprot[2:0],m_axi_s2mm_awcache[3:0],m_axi_s2mm_awuser[3:0],m_axi_s2mm_awvalid,m_axi_s2mm_awready,m_axi_s2mm_wdata[31:0],m_axi_s2mm_wstrb[3:0],m_axi_s2mm_wlast,m_axi_s2mm_wvalid,m_axi_s2mm_wready,m_axi_s2mm_bresp[1:0],m_axi_s2mm_bvalid,m_axi_s2mm_bready,s_axis_s2mm_tdata[31:0],s_axis_s2mm_tkeep[3:0],s_axis_s2mm_tlast,s_axis_s2mm_tvalid,s_axis_s2mm_tready";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_datamover,Vivado 2016.4";
begin
end;
|
--*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 4.0
-- \ \ Application : MIG
-- / / Filename : ddr_mig.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Top-level module. This module can be instantiated in the
-- system and interconnect as shown in user design wrapper file (user top module).
-- In addition to the memory controller, the module instantiates:
-- 1. Clock generation/distribution, reset logic
-- 2. IDELAY control block
-- 3. Debug logic
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ddr_mig is
generic (
RST_ACT_LOW : integer := 1;
-- =1 for active low reset,
-- =0 for active high.
--***************************************************************************
-- The following parameters refer to width of various ports
--***************************************************************************
BANK_WIDTH : integer := 3;
-- # of memory Bank Address bits.
CK_WIDTH : integer := 1;
-- # of CK/CK# outputs to memory.
COL_WIDTH : integer := 10;
-- # of memory Column Address bits.
CS_WIDTH : integer := 1;
-- # of unique CS outputs to memory.
nCS_PER_RANK : integer := 1;
-- # of unique CS outputs per rank for phy
CKE_WIDTH : integer := 1;
-- # of CKE outputs to memory.
DATA_BUF_ADDR_WIDTH : integer := 4;
DQ_CNT_WIDTH : integer := 4;
-- = ceil(log2(DQ_WIDTH))
DQ_PER_DM : integer := 8;
DM_WIDTH : integer := 2;
-- # of DM (data mask)
DQ_WIDTH : integer := 16;
-- # of DQ (data)
DQS_WIDTH : integer := 2;
DQS_CNT_WIDTH : integer := 1;
-- = ceil(log2(DQS_WIDTH))
DRAM_WIDTH : integer := 8;
-- # of DQ per DQS
ECC : string := "OFF";
ECC_TEST : string := "OFF";
PAYLOAD_WIDTH : integer := 16;
MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
--Possible Parameters
--1.BANK_ROW_COLUMN : Address mapping is
-- in form of Bank Row Column.
--2.ROW_BANK_COLUMN : Address mapping is
-- in the form of Row Bank Column.
--3.TG_TEST : Scrambles Address bits
-- for distributed Addressing.
--nBANK_MACHS : integer := 4;
nBANK_MACHS : integer := 4;
RANKS : integer := 1;
-- # of Ranks.
ODT_WIDTH : integer := 1;
-- # of ODT outputs to memory.
ROW_WIDTH : integer := 13;
-- # of memory Row Address bits.
ADDR_WIDTH : integer := 27;
-- # = RANK_WIDTH + BANK_WIDTH
-- + ROW_WIDTH + COL_WIDTH;
-- Chip Select is always tied to low for
-- single rank devices
USE_CS_PORT : integer := 1;
-- # = 1, When Chip Select (CS#) output is enabled
-- = 0, When Chip Select (CS#) output is disabled
-- If CS_N disabled, user must connect
-- DRAM CS_N input(s) to ground
USE_DM_PORT : integer := 1;
-- # = 1, When Data Mask option is enabled
-- = 0, When Data Mask option is disbaled
-- When Data Mask option is disabled in
-- MIG Controller Options page, the logic
-- related to Data Mask should not get
-- synthesized
USE_ODT_PORT : integer := 1;
-- # = 1, When ODT output is enabled
-- = 0, When ODT output is disabled
PHY_CONTROL_MASTER_BANK : integer := 0;
-- The bank index where master PHY_CONTROL resides,
-- equal to the PLL residing bank
MEM_DENSITY : string := "1Gb";
-- Indicates the density of the Memory part
-- Added for the sake of Vivado simulations
MEM_SPEEDGRADE : string := "25E";
-- Indicates the Speed grade of Memory Part
-- Added for the sake of Vivado simulations
MEM_DEVICE_WIDTH : integer := 16;
-- Indicates the device width of the Memory Part
-- Added for the sake of Vivado simulations
--***************************************************************************
-- The following parameters are mode register settings
--***************************************************************************
AL : string := "0";
-- DDR3 SDRAM:
-- Additive Latency (Mode Register 1).
-- # = "0", "CL-1", "CL-2".
-- DDR2 SDRAM:
-- Additive Latency (Extended Mode Register).
nAL : integer := 0;
-- # Additive Latency in number of clock
-- cycles.
BURST_MODE : string := "8";
-- DDR3 SDRAM:
-- Burst Length (Mode Register 0).
-- # = "8", "4", "OTF".
-- DDR2 SDRAM:
-- Burst Length (Mode Register).
-- # = "8", "4".
BURST_TYPE : string := "SEQ";
-- DDR3 SDRAM: Burst Type (Mode Register 0).
-- DDR2 SDRAM: Burst Type (Mode Register).
-- # = "SEQ" - (Sequential),
-- = "INT" - (Interleaved).
CL : integer := 5;
-- in number of clock cycles
-- DDR3 SDRAM: CAS Latency (Mode Register 0).
-- DDR2 SDRAM: CAS Latency (Mode Register).
OUTPUT_DRV : string := "HIGH";
-- Output Drive Strength (Extended Mode Register).
-- # = "HIGH" - FULL,
-- = "LOW" - REDUCED.
RTT_NOM : string := "50";
-- RTT (Nominal) (Extended Mode Register).
-- = "150" - 150 Ohms,
-- = "75" - 75 Ohms,
-- = "50" - 50 Ohms.
ADDR_CMD_MODE : string := "1T" ;
-- # = "1T", "2T".
REG_CTRL : string := "OFF";
-- # = "ON" - RDIMMs,
-- = "OFF" - Components, SODIMMs, UDIMMs.
--***************************************************************************
-- The following parameters are multiplier and divisor factors for PLLE2.
-- Based on the selected design frequency these parameters vary.
--***************************************************************************
CLKIN_PERIOD : integer := 4999;
-- Input Clock Period
CLKFBOUT_MULT : integer := 6;
-- write PLL VCO multiplier
DIVCLK_DIVIDE : integer := 1;
-- write PLL VCO divisor
CLKOUT0_PHASE : real := 0.0;
-- Phase for PLL output clock (CLKOUT0)
CLKOUT0_DIVIDE : integer := 2;
-- VCO output divisor for PLL output clock (CLKOUT0)
CLKOUT1_DIVIDE : integer := 4;
-- VCO output divisor for PLL output clock (CLKOUT1)
CLKOUT2_DIVIDE : integer := 64;
-- VCO output divisor for PLL output clock (CLKOUT2)
CLKOUT3_DIVIDE : integer := 8;
-- VCO output divisor for PLL output clock (CLKOUT3)
MMCM_VCO : integer := 1200;
-- Max Freq (MHz) of MMCM VCO
MMCM_MULT_F : integer := 7;
-- write MMCM VCO multiplier
MMCM_DIVCLK_DIVIDE : integer := 1;
-- write MMCM VCO divisor
--***************************************************************************
-- Memory Timing Parameters. These parameters varies based on the selected
-- memory part.
--***************************************************************************
tCKE : integer := 7500;
-- memory tCKE paramter in pS
tFAW : integer := 45000;
-- memory tRAW paramter in pS.
tPRDI : integer := 1000000;
-- memory tPRDI paramter in pS.
tRAS : integer := 40000;
-- memory tRAS paramter in pS.
tRCD : integer := 15000;
-- memory tRCD paramter in pS.
tREFI : integer := 7800000;
-- memory tREFI paramter in pS.
tRFC : integer := 127500;
-- memory tRFC paramter in pS.
tRP : integer := 12500;
-- memory tRP paramter in pS.
tRRD : integer := 10000;
-- memory tRRD paramter in pS.
tRTP : integer := 7500;
-- memory tRTP paramter in pS.
tWTR : integer := 7500;
-- memory tWTR paramter in pS.
tZQI : integer := 128000000;
-- memory tZQI paramter in nS.
tZQCS : integer := 64;
-- memory tZQCS paramter in clock cycles.
--***************************************************************************
-- Simulation parameters
--***************************************************************************
SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
--***************************************************************************
-- The following parameters varies based on the pin out entered in MIG GUI.
-- Do not change any of these parameters directly by editing the RTL.
-- Any changes required should be done through GUI and the design regenerated.
--***************************************************************************
BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "1111";
-- Byte lanes used in an IO column.
BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
DATA_CTL_B0 : std_logic_vector(3 downto 0) := "0101";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B1 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B2 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B3 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B4 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"FFC3F7FFF3FE";
PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
-- control/address/data pin mapping parameters
CK_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000003";
ADDR_MAP
: std_logic_vector(191 downto 0) := X"00000000001003301A01903203A034018036012011017015";
BANK_MAP : std_logic_vector(35 downto 0) := X"01301601B";
CAS_MAP : std_logic_vector(11 downto 0) := X"039";
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00";
CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000038";
ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000035";
CS_MAP : std_logic_vector(119 downto 0) := X"000000000000000000000000000037";
PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
RAS_MAP : std_logic_vector(11 downto 0) := X"014";
WE_MAP : std_logic_vector(11 downto 0) := X"03B";
DQS_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000200";
DATA0_MAP : std_logic_vector(95 downto 0) := X"008004009007005001006003";
DATA1_MAP : std_logic_vector(95 downto 0) := X"022028020024027025026021";
DATA2_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA3_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000029002";
MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
SLOT_0_CONFIG : std_logic_vector(7 downto 0) := "00000001";
-- Mapping of Ranks.
SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000";
-- Mapping of Ranks.
--***************************************************************************
-- IODELAY and PHY related parameters
--***************************************************************************
IBUF_LPWR_MODE : string := "OFF";
-- to phy_top
DATA_IO_IDLE_PWRDWN : string := "ON";
-- # = "ON", "OFF"
BANK_TYPE : string := "HR_IO";
-- # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
DATA_IO_PRIM_TYPE : string := "HR_LP";
-- # = "HP_LP", "HR_LP", "DEFAULT"
CKE_ODT_AUX : string := "FALSE";
USER_REFRESH : string := "OFF";
WRLVL : string := "OFF";
-- # = "ON" - DDR3 SDRAM
-- = "OFF" - DDR2 SDRAM.
ORDERING : string := "STRICT";
-- # = "NORM", "STRICT", "RELAXED".
CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000";
-- Calibration row address will be used for
-- calibration read and write operations
CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000";
-- Calibration column address will be used for
-- calibration read and write operations
CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000";
-- Calibration bank address will be used for
-- calibration read and write operations
TCQ : integer := 100;
IODELAY_GRP0 : string := "DDR_IODELAY_MIG0";
-- It is associated to a set of IODELAYs with
-- an IDELAYCTRL that have same IODELAY CONTROLLER
-- clock frequency (200MHz).
IODELAY_GRP1 : string := "DDR_IODELAY_MIG1";
-- It is associated to a set of IODELAYs with
-- an IDELAYCTRL that have same IODELAY CONTROLLER
-- clock frequency (300MHz/400MHz).
SYSCLK_TYPE : string := "NO_BUFFER";
-- System clock type DIFFERENTIAL, SINGLE_ENDED,
-- NO_BUFFER
REFCLK_TYPE : string := "USE_SYSTEM_CLOCK";
-- Reference clock type DIFFERENTIAL, SINGLE_ENDED
-- NO_BUFFER, USE_SYSTEM_CLOCK
SYS_RST_PORT : string := "FALSE";
-- "TRUE" - if pin is selected for sys_rst
-- and IBUF will be instantiated.
-- "FALSE" - if pin is not selected for sys_rst
FPGA_SPEED_GRADE : integer := 1;
-- FPGA speed grade
REF_CLK_MMCM_IODELAY_CTRL : string := "FALSE";
CMD_PIPE_PLUS1 : string := "ON";
-- add pipeline stage between MC and PHY
DRAM_TYPE : string := "DDR2";
CAL_WIDTH : string := "HALF";
STARVE_LIMIT : integer := 2;
-- # = 2,3,4.
--***************************************************************************
-- Referece clock frequency parameters
--***************************************************************************
REFCLK_FREQ : real := 200.0;
-- IODELAYCTRL reference clock frequency
DIFF_TERM_REFCLK : string := "TRUE";
-- Differential Termination for idelay
-- reference clock input pins
--***************************************************************************
-- System clock frequency parameters
--***************************************************************************
tCK : integer := 3333;
-- memory tCK paramter.
-- # = Clock Period in pS.
nCK_PER_CLK : integer := 2;
-- # of memory CKs per fabric CLK
DIFF_TERM_SYSCLK : string := "TRUE";
-- Differential Termination for System
-- clock input pins
--***************************************************************************
-- Debug parameters
--***************************************************************************
DEBUG_PORT : string := "OFF";
-- # = "ON" Enable debug signals/controls.
-- = "OFF" Disable debug signals/controls.
--***************************************************************************
-- Temparature monitor parameter
--***************************************************************************
TEMP_MON_CONTROL : string := "INTERNAL"
-- # = "INTERNAL", "EXTERNAL"
-- RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
);
port (
-- Inouts
ddr2_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr2_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr2_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr2_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr2_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr2_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr2_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
-- Inputs
-- Single-ended system clock
sys_clk_i : in std_logic;
-- user interface signals
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH/8)-1 downto 0) ;
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System reset - Default polarity of sys_rst pin is Active Low.
-- System reset polarity will change based on the option
-- selected in GUI.
sys_rst : in std_logic
);
end entity ddr_mig;
architecture arch_ddr_mig of ddr_mig is
-- clogb2 function - ceiling of log base 2
function clogb2 (size : integer) return integer is
variable base : integer := 1;
variable inp : integer := 0;
begin
inp := size - 1;
while (inp > 1) loop
inp := inp/2 ;
base := base + 1;
end loop;
return base;
end function;
constant DATA_WIDTH : integer := 16;
function ECCWIDTH return integer is
begin
if(ECC = "OFF") then
return 0;
else
if(DATA_WIDTH <= 4) then
return 4;
elsif(DATA_WIDTH <= 10) then
return 5;
elsif(DATA_WIDTH <= 26) then
return 6;
elsif(DATA_WIDTH <= 57) then
return 7;
elsif(DATA_WIDTH <= 120) then
return 8;
elsif(DATA_WIDTH <= 247) then
return 9;
else
return 10;
end if;
end if;
end function;
constant RANK_WIDTH : integer := clogb2(RANKS);
function XWIDTH return integer is
begin
if(CS_WIDTH = 1) then
return 0;
else
return RANK_WIDTH;
end if;
end function;
constant TAPSPERKCLK : integer := 56;
function TEMP_MON return string is
begin
if(SIMULATION = "TRUE") then
return "ON";
else
return "OFF";
end if;
end function;
constant BM_CNT_WIDTH : integer := clogb2(nBANK_MACHS);
constant ECC_WIDTH : integer := ECCWIDTH;
constant DATA_BUF_OFFSET_WIDTH : integer := 1;
constant MC_ERR_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH
+ COL_WIDTH + DATA_BUF_OFFSET_WIDTH;
constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
constant TEMP_MON_EN : string := TEMP_MON;
-- Enable or disable the temp monitor module
constant tTEMPSAMPLE : integer := 10000000; -- sample every 10 us
constant XADC_CLK_PERIOD : integer := 5000; -- Use 200 MHz IODELAYCTRL clock
component mig_7series_v4_0_iodelay_ctrl is
generic(
TCQ : integer;
IODELAY_GRP0 : string;
IODELAY_GRP1 : string;
REFCLK_TYPE : string;
SYSCLK_TYPE : string;
SYS_RST_PORT : string;
RST_ACT_LOW : integer;
DIFF_TERM_REFCLK : string;
FPGA_SPEED_GRADE : integer;
REF_CLK_MMCM_IODELAY_CTRL : string
);
port (
clk_ref_p : in std_logic;
clk_ref_n : in std_logic;
clk_ref_i : in std_logic;
sys_rst : in std_logic;
clk_ref : out std_logic_vector(1 downto 0);
sys_rst_o : out std_logic;
iodelay_ctrl_rdy : out std_logic_vector(1 downto 0)
);
end component mig_7series_v4_0_iodelay_ctrl;
component mig_7series_v4_0_clk_ibuf is
generic (
SYSCLK_TYPE : string;
DIFF_TERM_SYSCLK : string
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk_i : in std_logic;
mmcm_clk : out std_logic
);
end component mig_7series_v4_0_clk_ibuf;
component mig_7series_v4_0_infrastructure is
generic (
SIMULATION : string := "TRUE";
TCQ : integer;
CLKIN_PERIOD : integer;
nCK_PER_CLK : integer;
SYSCLK_TYPE : string;
UI_EXTRA_CLOCKS : string := "FALSE";
CLKFBOUT_MULT : integer;
DIVCLK_DIVIDE : integer;
CLKOUT0_PHASE : real;
CLKOUT0_DIVIDE : integer;
CLKOUT1_DIVIDE : integer;
CLKOUT2_DIVIDE : integer;
CLKOUT3_DIVIDE : integer;
MMCM_VCO : integer;
MMCM_MULT_F : integer;
MMCM_DIVCLK_DIVIDE : integer;
MMCM_CLKOUT0_EN : string := "FALSE";
MMCM_CLKOUT1_EN : string := "FALSE";
MMCM_CLKOUT2_EN : string := "FALSE";
MMCM_CLKOUT3_EN : string := "FALSE";
MMCM_CLKOUT4_EN : string := "FALSE";
MMCM_CLKOUT0_DIVIDE : integer := 1;
MMCM_CLKOUT1_DIVIDE : integer := 1;
MMCM_CLKOUT2_DIVIDE : integer := 1;
MMCM_CLKOUT3_DIVIDE : integer := 1;
MMCM_CLKOUT4_DIVIDE : integer := 1;
RST_ACT_LOW : integer;
tCK : integer;
MEM_TYPE : string
);
port (
mmcm_clk : in std_logic;
sys_rst : in std_logic;
iodelay_ctrl_rdy : in std_logic_vector(1 downto 0);
psen : in std_logic;
psincdec : in std_logic;
clk : out std_logic;
clk_div2 : out std_logic;
rst_div2 : out std_logic;
mem_refclk : out std_logic;
freq_refclk : out std_logic;
sync_pulse : out std_logic;
mmcm_ps_clk : out std_logic;
poc_sample_pd : out std_logic;
iddr_rst : out std_logic;
psdone : out std_logic;
-- auxout_clk : out std_logic;
ui_addn_clk_0 : out std_logic;
ui_addn_clk_1 : out std_logic;
ui_addn_clk_2 : out std_logic;
ui_addn_clk_3 : out std_logic;
ui_addn_clk_4 : out std_logic;
pll_locked : out std_logic;
mmcm_locked : out std_logic;
rstdiv0 : out std_logic;
rst_phaser_ref : out std_logic;
ref_dll_lock : in std_logic
);
end component mig_7series_v4_0_infrastructure;
component mig_7series_v4_0_tempmon is
generic (
TCQ : integer;
TEMP_MON_CONTROL : string;
XADC_CLK_PERIOD : integer;
tTEMPSAMPLE : integer
);
port (
clk : in std_logic;
xadc_clk : in std_logic;
rst : in std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
device_temp : out std_logic_vector(11 downto 0)
);
end component mig_7series_v4_0_tempmon;
component mig_7series_v4_0_memc_ui_top_std is
generic (
TCQ : integer;
DDR3_VDD_OP_VOLT : string := "135";
PAYLOAD_WIDTH : integer;
ADDR_CMD_MODE : string;
AL : string;
BANK_WIDTH : integer;
BM_CNT_WIDTH : integer;
BURST_MODE : string;
BURST_TYPE : string;
CA_MIRROR : string := "FALSE";
CK_WIDTH : integer;
CL : integer;
COL_WIDTH : integer;
CMD_PIPE_PLUS1 : string;
CS_WIDTH : integer;
CKE_WIDTH : integer;
CWL : integer := 5;
DATA_WIDTH : integer;
DATA_BUF_ADDR_WIDTH : integer;
DATA_BUF_OFFSET_WIDTH : integer := 1;
DDR2_DQSN_ENABLE : string := "YES";
DM_WIDTH : integer;
DQ_CNT_WIDTH : integer;
DQ_WIDTH : integer;
DQS_CNT_WIDTH : integer;
DQS_WIDTH : integer;
DRAM_TYPE : string;
DRAM_WIDTH : integer;
ECC : string;
ECC_WIDTH : integer;
ECC_TEST : string;
MC_ERR_ADDR_WIDTH : integer;
MASTER_PHY_CTL : integer;
nAL : integer;
nBANK_MACHS : integer;
nCK_PER_CLK : integer;
nCS_PER_RANK : integer;
ORDERING : string;
IBUF_LPWR_MODE : string;
BANK_TYPE : string;
DATA_IO_PRIM_TYPE : string;
DATA_IO_IDLE_PWRDWN : string;
IODELAY_GRP0 : string;
IODELAY_GRP1 : string;
FPGA_SPEED_GRADE : integer;
OUTPUT_DRV : string;
REG_CTRL : string;
RTT_NOM : string;
RTT_WR : string := "120";
STARVE_LIMIT : integer;
tCK : integer;
tCKE : integer;
tFAW : integer;
tPRDI : integer;
tRAS : integer;
tRCD : integer;
tREFI : integer;
tRFC : integer;
tRP : integer;
tRRD : integer;
tRTP : integer;
tWTR : integer;
tZQI : integer;
tZQCS : integer;
USER_REFRESH : string;
TEMP_MON_EN : string;
WRLVL : string;
DEBUG_PORT : string;
CAL_WIDTH : string;
RANK_WIDTH : integer;
RANKS : integer;
ODT_WIDTH : integer;
ROW_WIDTH : integer;
ADDR_WIDTH : integer;
APP_MASK_WIDTH : integer;
APP_DATA_WIDTH : integer;
BYTE_LANES_B0 : std_logic_vector(3 downto 0);
BYTE_LANES_B1 : std_logic_vector(3 downto 0);
BYTE_LANES_B2 : std_logic_vector(3 downto 0);
BYTE_LANES_B3 : std_logic_vector(3 downto 0);
BYTE_LANES_B4 : std_logic_vector(3 downto 0);
DATA_CTL_B0 : std_logic_vector(3 downto 0);
DATA_CTL_B1 : std_logic_vector(3 downto 0);
DATA_CTL_B2 : std_logic_vector(3 downto 0);
DATA_CTL_B3 : std_logic_vector(3 downto 0);
DATA_CTL_B4 : std_logic_vector(3 downto 0);
PHY_0_BITLANES : std_logic_vector(47 downto 0);
PHY_1_BITLANES : std_logic_vector(47 downto 0);
PHY_2_BITLANES : std_logic_vector(47 downto 0);
CK_BYTE_MAP : std_logic_vector(143 downto 0);
ADDR_MAP : std_logic_vector(191 downto 0);
BANK_MAP : std_logic_vector(35 downto 0);
CAS_MAP : std_logic_vector(11 downto 0);
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0);
CKE_MAP : std_logic_vector(95 downto 0);
ODT_MAP : std_logic_vector(95 downto 0);
CKE_ODT_AUX : string;
CS_MAP : std_logic_vector(119 downto 0);
PARITY_MAP : std_logic_vector(11 downto 0);
RAS_MAP : std_logic_vector(11 downto 0);
WE_MAP : std_logic_vector(11 downto 0);
DQS_BYTE_MAP : std_logic_vector(143 downto 0);
DATA0_MAP : std_logic_vector(95 downto 0);
DATA1_MAP : std_logic_vector(95 downto 0);
DATA2_MAP : std_logic_vector(95 downto 0);
DATA3_MAP : std_logic_vector(95 downto 0);
DATA4_MAP : std_logic_vector(95 downto 0);
DATA5_MAP : std_logic_vector(95 downto 0);
DATA6_MAP : std_logic_vector(95 downto 0);
DATA7_MAP : std_logic_vector(95 downto 0);
DATA8_MAP : std_logic_vector(95 downto 0);
DATA9_MAP : std_logic_vector(95 downto 0);
DATA10_MAP : std_logic_vector(95 downto 0);
DATA11_MAP : std_logic_vector(95 downto 0);
DATA12_MAP : std_logic_vector(95 downto 0);
DATA13_MAP : std_logic_vector(95 downto 0);
DATA14_MAP : std_logic_vector(95 downto 0);
DATA15_MAP : std_logic_vector(95 downto 0);
DATA16_MAP : std_logic_vector(95 downto 0);
DATA17_MAP : std_logic_vector(95 downto 0);
MASK0_MAP : std_logic_vector(107 downto 0);
MASK1_MAP : std_logic_vector(107 downto 0);
SLOT_0_CONFIG : std_logic_vector(7 downto 0);
SLOT_1_CONFIG : std_logic_vector(7 downto 0);
MEM_ADDR_ORDER : string;
CALIB_ROW_ADD : std_logic_vector(15 downto 0);
CALIB_COL_ADD : std_logic_vector(11 downto 0);
CALIB_BA_ADD : std_logic_vector(2 downto 0);
SIM_BYPASS_INIT_CAL : string;
REFCLK_FREQ : real;
USE_CS_PORT : integer;
USE_DM_PORT : integer;
USE_ODT_PORT : integer;
IDELAY_ADJ : string;
FINE_PER_BIT : string;
CENTER_COMP_MODE : string;
PI_VAL_ADJ : string;
TAPSPERKCLK : integer := 56;
SKIP_CALIB : string;
FPGA_VOLT_TYPE : string
);
port (
clk : in std_logic;
clk_div2 : in std_logic;
rst_div2 : in std_logic;
clk_ref : in std_logic_vector(1 downto 0);
mem_refclk : in std_logic;
freq_refclk : in std_logic;
pll_lock : in std_logic;
sync_pulse : in std_logic;
mmcm_ps_clk : in std_logic;
poc_sample_pd : in std_logic;
rst : in std_logic;
ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr_cas_n : out std_logic;
ddr_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_ck : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
ddr_ras_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_parity : out std_logic;
ddr_we_n : out std_logic;
bank_mach_next : out std_logic_vector(BM_CNT_WIDTH-1 downto 0);
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_hi_pri : in std_logic;
app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8)-1 downto 0);
app_wdf_wren : in std_logic;
app_correct_en_i : in std_logic;
app_raw_not_ecc : in std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
app_ecc_multiple_err : out std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
app_ecc_single_err : out std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
calib_tap_req : out std_logic;
calib_tap_addr : in std_logic_vector(6 downto 0);
calib_tap_load : in std_logic;
calib_tap_val : in std_logic_vector(7 downto 0);
calib_tap_load_done : in std_logic;
device_temp : in std_logic_vector(11 downto 0);
psen : out std_logic;
psincdec : out std_logic;
psdone : in std_logic;
dbg_idel_down_all : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_idel_up_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_sel_all_idel_cpt : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
dbg_cpt_first_edge_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_rddata : out std_logic_vector((2*nCK_PER_CLK*DQ_WIDTH)-1 downto 0);
dbg_rdlvl_done : out std_logic_vector(1 downto 0);
dbg_rdlvl_err : out std_logic_vector(1 downto 0);
dbg_rdlvl_start : out std_logic_vector(1 downto 0);
dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
dbg_wl_edge_detect_valid : out std_logic;
dbg_wrlvl_done : out std_logic;
dbg_wrlvl_err : out std_logic;
dbg_wrlvl_start : out std_logic;
dbg_final_po_fine_tap_cnt : out std_logic_vector((6*DQS_WIDTH)-1 downto 0);
dbg_final_po_coarse_tap_cnt : out std_logic_vector((3*DQS_WIDTH)-1 downto 0);
init_calib_complete : out std_logic;
dbg_sel_pi_incdec : in std_logic;
dbg_sel_po_incdec : in std_logic;
dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
dbg_pi_f_inc : in std_logic;
dbg_pi_f_dec : in std_logic;
dbg_po_f_inc : in std_logic;
dbg_po_f_stg23_sel : in std_logic;
dbg_po_f_dec : in std_logic;
dbg_cpt_tap_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_dq_idelay_tap_cnt : out std_logic_vector((5*DQS_WIDTH*RANKS)-1 downto 0);
dbg_rddata_valid : out std_logic;
dbg_wrlvl_fine_tap_cnt : out std_logic_vector((6*DQS_WIDTH)-1 downto 0);
dbg_wrlvl_coarse_tap_cnt : out std_logic_vector((3*DQS_WIDTH)-1 downto 0);
rst_phaser_ref : in std_logic;
ref_dll_lock : out std_logic;
iddr_rst : in std_logic;
dbg_rd_data_offset : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_calib_top : out std_logic_vector(255 downto 0);
dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
dbg_phy_wrcal : out std_logic_vector(99 downto 0);
dbg_phy_init : out std_logic_vector(255 downto 0);
dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
dbg_pi_counter_read_val : out std_logic_vector(5 downto 0);
dbg_po_counter_read_val : out std_logic_vector(8 downto 0);
dbg_pi_phaselock_start : out std_logic;
dbg_pi_phaselocked_done : out std_logic;
dbg_pi_phaselock_err : out std_logic;
dbg_pi_dqsfound_start : out std_logic;
dbg_pi_dqsfound_done : out std_logic;
dbg_pi_dqsfound_err : out std_logic;
dbg_wrcal_start : out std_logic;
dbg_wrcal_done : out std_logic;
dbg_wrcal_err : out std_logic;
dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0);
dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
dbg_calib_rd_data_offset_1 : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_calib_rd_data_offset_2 : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_data_offset : out std_logic_vector(5 downto 0);
dbg_data_offset_1 : out std_logic_vector(5 downto 0);
dbg_data_offset_2 : out std_logic_vector(5 downto 0);
dbg_oclkdelay_calib_start : out std_logic;
dbg_oclkdelay_calib_done : out std_logic;
dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
dbg_oclkdelay_rd_data : out std_logic_vector((DRAM_WIDTH*16)-1 downto 0);
dbg_prbs_final_dqs_tap_cnt_r : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_prbs_first_edge_taps : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_prbs_second_edge_taps : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_poc : out std_logic_vector (1023 downto 0)
);
end component mig_7series_v4_0_memc_ui_top_std;
-- Signal declarations
signal bank_mach_next : std_logic_vector(BM_CNT_WIDTH-1 downto 0);
signal clk : std_logic;
signal clk_ref : std_logic_vector(1 downto 0);
signal iodelay_ctrl_rdy : std_logic_vector(1 downto 0);
signal clk_ref_in : std_logic;
signal sys_rst_o : std_logic;
signal clk_div2 : std_logic;
signal rst_div2 : std_logic;
signal freq_refclk : std_logic;
signal mem_refclk : std_logic;
signal pll_locked : std_logic;
signal sync_pulse : std_logic;
signal mmcm_ps_clk : std_logic;
signal poc_sample_pd : std_logic;
signal psen : std_logic;
signal psincdec : std_logic;
signal psdone : std_logic;
signal iddr_rst : std_logic;
signal ref_dll_lock : std_logic;
signal rst_phaser_ref : std_logic;
signal rst : std_logic;
signal app_ecc_multiple_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
signal app_ecc_single_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
signal ddr2_reset_n : std_logic;
signal ddr2_parity : std_logic;
signal init_calib_complete_i : std_logic;
signal sys_clk_p : std_logic;
signal sys_clk_n : std_logic;
signal mmcm_clk : std_logic;
signal clk_ref_p : std_logic;
signal clk_ref_n : std_logic;
signal clk_ref_i : std_logic;
signal device_temp : std_logic_vector(11 downto 0);
signal device_temp_i : std_logic_vector(11 downto 0);
-- Debug port signals
signal dbg_idel_down_all : std_logic;
signal dbg_idel_down_cpt : std_logic;
signal dbg_idel_up_all : std_logic;
signal dbg_idel_up_cpt : std_logic;
signal dbg_sel_all_idel_cpt : std_logic;
signal dbg_sel_idel_cpt : std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
signal dbg_po_f_stg23_sel : std_logic;
signal dbg_sel_pi_incdec : std_logic;
signal dbg_sel_po_incdec : std_logic;
signal dbg_byte_sel : std_logic_vector(DQS_CNT_WIDTH downto 0);
signal dbg_pi_f_inc : std_logic;
signal dbg_po_f_inc : std_logic;
signal dbg_pi_f_dec : std_logic;
signal dbg_po_f_dec : std_logic;
signal dbg_pi_counter_read_val : std_logic_vector(5 downto 0);
signal dbg_po_counter_read_val : std_logic_vector(8 downto 0);
signal dbg_prbs_final_dqs_tap_cnt_r : std_logic_vector(11 downto 0);
signal dbg_prbs_first_edge_taps : std_logic_vector(11 downto 0);
signal dbg_prbs_second_edge_taps : std_logic_vector(11 downto 0);
signal dbg_cpt_tap_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_dq_idelay_tap_cnt : std_logic_vector((5*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_calib_top : std_logic_vector(255 downto 0);
signal dbg_cpt_first_edge_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_cpt_second_edge_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_rd_data_offset : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_phy_rdlvl : std_logic_vector(255 downto 0);
signal dbg_phy_wrcal : std_logic_vector(99 downto 0);
signal dbg_final_po_fine_tap_cnt : std_logic_vector((6*DQS_WIDTH)-1 downto 0);
signal dbg_final_po_coarse_tap_cnt : std_logic_vector((3*DQS_WIDTH)-1 downto 0);
signal dbg_phy_wrlvl : std_logic_vector(255 downto 0);
signal dbg_phy_init : std_logic_vector(255 downto 0);
signal dbg_prbs_rdlvl : std_logic_vector(255 downto 0);
signal dbg_dqs_found_cal : std_logic_vector(255 downto 0);
signal dbg_pi_phaselock_start : std_logic;
signal dbg_pi_phaselocked_done : std_logic;
signal dbg_pi_phaselock_err : std_logic;
signal dbg_pi_dqsfound_start : std_logic;
signal dbg_pi_dqsfound_done : std_logic;
signal dbg_pi_dqsfound_err : std_logic;
signal dbg_wrcal_start : std_logic;
signal dbg_wrcal_done : std_logic;
signal dbg_wrcal_err : std_logic;
signal dbg_pi_dqs_found_lanes_phy4lanes : std_logic_vector(11 downto 0);
signal dbg_pi_phase_locked_phy4lanes : std_logic_vector(11 downto 0);
signal dbg_oclkdelay_calib_start : std_logic;
signal dbg_oclkdelay_calib_done : std_logic;
signal dbg_phy_oclkdelay_cal : std_logic_vector(255 downto 0);
signal dbg_oclkdelay_rd_data : std_logic_vector((DRAM_WIDTH*16)-1 downto 0);
signal dbg_rd_data_edge_detect : std_logic_vector(DQS_WIDTH-1 downto 0);
signal dbg_rddata : std_logic_vector((2*nCK_PER_CLK*DQ_WIDTH)-1 downto 0);
signal dbg_rddata_valid : std_logic;
signal dbg_rdlvl_done : std_logic_vector(1 downto 0);
signal dbg_rdlvl_err : std_logic_vector(1 downto 0);
signal dbg_rdlvl_start : std_logic_vector(1 downto 0);
signal dbg_wrlvl_fine_tap_cnt : std_logic_vector((6*DQS_WIDTH)-1 downto 0);
signal dbg_wrlvl_coarse_tap_cnt : std_logic_vector((3*DQS_WIDTH)-1 downto 0);
signal dbg_tap_cnt_during_wrlvl : std_logic_vector(5 downto 0);
signal dbg_wl_edge_detect_valid : std_logic;
signal dbg_wrlvl_done : std_logic;
signal dbg_wrlvl_err : std_logic;
signal dbg_wrlvl_start : std_logic;
signal dbg_rddata_r : std_logic_vector(63 downto 0);
signal dbg_rddata_valid_r : std_logic;
signal ocal_tap_cnt : std_logic_vector(53 downto 0);
signal dbg_dqs : std_logic_vector(4 downto 0);
signal dbg_bit : std_logic_vector(8 downto 0);
signal rd_data_edge_detect_r : std_logic_vector(8 downto 0);
signal wl_po_fine_cnt : std_logic_vector(53 downto 0);
signal wl_po_coarse_cnt : std_logic_vector(26 downto 0);
signal dbg_calib_rd_data_offset_1 : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_calib_rd_data_offset_2 : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_data_offset : std_logic_vector(5 downto 0);
signal dbg_data_offset_1 : std_logic_vector(5 downto 0);
signal dbg_data_offset_2 : std_logic_vector(5 downto 0);
signal all_zeros : std_logic_vector((2*nCK_PER_CLK)-1 downto 0) := (others => '0');
signal ddr2_ila_basic_int : std_logic_vector(119 downto 0);
signal ddr2_ila_wrpath_int : std_logic_vector(390 downto 0);
signal ddr2_ila_rdpath_int : std_logic_vector(1023 downto 0);
signal dbg_prbs_final_dqs_tap_cnt_r_int : std_logic_vector(11 downto 0);
signal dbg_prbs_first_edge_taps_int : std_logic_vector(11 downto 0);
signal dbg_prbs_second_edge_taps_int : std_logic_vector(11 downto 0);
begin
--***************************************************************************
ui_clk <= clk;
ui_clk_sync_rst <= rst;
sys_clk_p <= '0';
sys_clk_n <= '0';
clk_ref_i <= '0';
init_calib_complete <= init_calib_complete_i;
clk_ref_in_use_sys_clk : if (REFCLK_TYPE = "USE_SYSTEM_CLOCK") generate
clk_ref_in <= mmcm_clk;
end generate;
clk_ref_in_others : if (REFCLK_TYPE /= "USE_SYSTEM_CLOCK") generate
clk_ref_in <= clk_ref_i;
end generate;
u_iodelay_ctrl : mig_7series_v4_0_iodelay_ctrl
generic map
(
TCQ => TCQ,
IODELAY_GRP0 => IODELAY_GRP0,
IODELAY_GRP1 => IODELAY_GRP1,
REFCLK_TYPE => REFCLK_TYPE,
SYSCLK_TYPE => SYSCLK_TYPE,
SYS_RST_PORT => SYS_RST_PORT,
RST_ACT_LOW => RST_ACT_LOW,
DIFF_TERM_REFCLK => DIFF_TERM_REFCLK,
FPGA_SPEED_GRADE => FPGA_SPEED_GRADE,
REF_CLK_MMCM_IODELAY_CTRL => REF_CLK_MMCM_IODELAY_CTRL
)
port map
(
-- Outputs
iodelay_ctrl_rdy => iodelay_ctrl_rdy,
sys_rst_o => sys_rst_o,
clk_ref => clk_ref,
-- Inputs
clk_ref_p => clk_ref_p,
clk_ref_n => clk_ref_n,
clk_ref_i => clk_ref_in,
sys_rst => sys_rst
);
u_ddr2_clk_ibuf : mig_7series_v4_0_clk_ibuf
generic map
(
SYSCLK_TYPE => SYSCLK_TYPE,
DIFF_TERM_SYSCLK => DIFF_TERM_SYSCLK
)
port map
(
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_clk_i => sys_clk_i,
mmcm_clk => mmcm_clk
);
-- Temperature monitoring logic
temp_mon_enabled : if (TEMP_MON_EN = "ON") generate
u_tempmon : mig_7series_v4_0_tempmon
generic map
(
TCQ => TCQ,
TEMP_MON_CONTROL => TEMP_MON_CONTROL,
XADC_CLK_PERIOD => XADC_CLK_PERIOD,
tTEMPSAMPLE => tTEMPSAMPLE
)
port map
(
clk => clk,
xadc_clk => clk_ref(0),
rst => rst,
device_temp_i => device_temp_i,
device_temp => device_temp
);
end generate;
temp_mon_disabled : if (TEMP_MON_EN /= "ON") generate
device_temp <= (others => '0');
end generate;
u_ddr2_infrastructure : mig_7series_v4_0_infrastructure
generic map
(
TCQ => TCQ,
nCK_PER_CLK => nCK_PER_CLK,
CLKIN_PERIOD => CLKIN_PERIOD,
SYSCLK_TYPE => SYSCLK_TYPE,
CLKFBOUT_MULT => CLKFBOUT_MULT,
DIVCLK_DIVIDE => DIVCLK_DIVIDE,
CLKOUT0_PHASE => CLKOUT0_PHASE,
CLKOUT0_DIVIDE => CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => CLKOUT3_DIVIDE,
MMCM_VCO => MMCM_VCO,
MMCM_MULT_F => MMCM_MULT_F,
MMCM_DIVCLK_DIVIDE => MMCM_DIVCLK_DIVIDE,
RST_ACT_LOW => RST_ACT_LOW,
tCK => tCK,
MEM_TYPE => DRAM_TYPE
)
port map
(
-- Outputs
rstdiv0 => rst,
clk => clk,
clk_div2 => clk_div2,
rst_div2 => rst_div2,
mem_refclk => mem_refclk,
freq_refclk => freq_refclk,
sync_pulse => sync_pulse,
psen => psen,
psincdec => psincdec,
mmcm_ps_clk => mmcm_ps_clk,
poc_sample_pd => poc_sample_pd,
iddr_rst => iddr_rst,
psdone => psdone,
-- auxout_clk => open,
ui_addn_clk_0 => open,
ui_addn_clk_1 => open,
ui_addn_clk_2 => open,
ui_addn_clk_3 => open,
ui_addn_clk_4 => open,
pll_locked => pll_locked,
mmcm_locked => open,
rst_phaser_ref => rst_phaser_ref,
-- Inputs
mmcm_clk => mmcm_clk,
sys_rst => sys_rst_o,
iodelay_ctrl_rdy => iodelay_ctrl_rdy,
ref_dll_lock => ref_dll_lock
);
u_memc_ui_top_std : mig_7series_v4_0_memc_ui_top_std
generic map (
TCQ => TCQ,
ADDR_CMD_MODE => ADDR_CMD_MODE,
AL => AL,
PAYLOAD_WIDTH => PAYLOAD_WIDTH,
BANK_WIDTH => BANK_WIDTH,
BM_CNT_WIDTH => BM_CNT_WIDTH,
BURST_MODE => BURST_MODE,
BURST_TYPE => BURST_TYPE,
CK_WIDTH => CK_WIDTH,
COL_WIDTH => COL_WIDTH,
CMD_PIPE_PLUS1 => CMD_PIPE_PLUS1,
CS_WIDTH => CS_WIDTH,
nCS_PER_RANK => nCS_PER_RANK,
CKE_WIDTH => CKE_WIDTH,
DATA_WIDTH => DATA_WIDTH,
DATA_BUF_ADDR_WIDTH => DATA_BUF_ADDR_WIDTH,
DM_WIDTH => DM_WIDTH,
DQ_CNT_WIDTH => DQ_CNT_WIDTH,
DQ_WIDTH => DQ_WIDTH,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_TYPE => DRAM_TYPE,
DRAM_WIDTH => DRAM_WIDTH,
ECC => ECC,
ECC_WIDTH => ECC_WIDTH,
ECC_TEST => ECC_TEST,
MC_ERR_ADDR_WIDTH => MC_ERR_ADDR_WIDTH,
REFCLK_FREQ => REFCLK_FREQ,
nAL => nAL,
nBANK_MACHS => nBANK_MACHS,
CKE_ODT_AUX => CKE_ODT_AUX,
nCK_PER_CLK => nCK_PER_CLK,
ORDERING => ORDERING,
OUTPUT_DRV => OUTPUT_DRV,
IBUF_LPWR_MODE => IBUF_LPWR_MODE,
DATA_IO_IDLE_PWRDWN => DATA_IO_IDLE_PWRDWN,
BANK_TYPE => BANK_TYPE,
DATA_IO_PRIM_TYPE => DATA_IO_PRIM_TYPE,
IODELAY_GRP0 => IODELAY_GRP0,
IODELAY_GRP1 => IODELAY_GRP1,
FPGA_SPEED_GRADE => FPGA_SPEED_GRADE,
REG_CTRL => REG_CTRL,
RTT_NOM => RTT_NOM,
CL => CL,
tCK => tCK,
tCKE => tCKE,
tFAW => tFAW,
tPRDI => tPRDI,
tRAS => tRAS,
tRCD => tRCD,
tREFI => tREFI,
tRFC => tRFC,
tRP => tRP,
tRRD => tRRD,
tRTP => tRTP,
tWTR => tWTR,
tZQI => tZQI,
tZQCS => tZQCS,
USER_REFRESH => USER_REFRESH,
TEMP_MON_EN => TEMP_MON_EN,
WRLVL => WRLVL,
DEBUG_PORT => DEBUG_PORT,
CAL_WIDTH => CAL_WIDTH,
RANK_WIDTH => RANK_WIDTH,
RANKS => RANKS,
ODT_WIDTH => ODT_WIDTH,
ROW_WIDTH => ROW_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
APP_DATA_WIDTH => APP_DATA_WIDTH,
APP_MASK_WIDTH => APP_MASK_WIDTH,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
BYTE_LANES_B0 => BYTE_LANES_B0,
BYTE_LANES_B1 => BYTE_LANES_B1,
BYTE_LANES_B2 => BYTE_LANES_B2,
BYTE_LANES_B3 => BYTE_LANES_B3,
BYTE_LANES_B4 => BYTE_LANES_B4,
DATA_CTL_B0 => DATA_CTL_B0,
DATA_CTL_B1 => DATA_CTL_B1,
DATA_CTL_B2 => DATA_CTL_B2,
DATA_CTL_B3 => DATA_CTL_B3,
DATA_CTL_B4 => DATA_CTL_B4,
PHY_0_BITLANES => PHY_0_BITLANES,
PHY_1_BITLANES => PHY_1_BITLANES,
PHY_2_BITLANES => PHY_2_BITLANES,
CK_BYTE_MAP => CK_BYTE_MAP,
ADDR_MAP => ADDR_MAP,
BANK_MAP => BANK_MAP,
CAS_MAP => CAS_MAP,
CKE_ODT_BYTE_MAP => CKE_ODT_BYTE_MAP,
CKE_MAP => CKE_MAP,
ODT_MAP => ODT_MAP,
CS_MAP => CS_MAP,
PARITY_MAP => PARITY_MAP,
RAS_MAP => RAS_MAP,
WE_MAP => WE_MAP,
DQS_BYTE_MAP => DQS_BYTE_MAP,
DATA0_MAP => DATA0_MAP,
DATA1_MAP => DATA1_MAP,
DATA2_MAP => DATA2_MAP,
DATA3_MAP => DATA3_MAP,
DATA4_MAP => DATA4_MAP,
DATA5_MAP => DATA5_MAP,
DATA6_MAP => DATA6_MAP,
DATA7_MAP => DATA7_MAP,
DATA8_MAP => DATA8_MAP,
DATA9_MAP => DATA9_MAP,
DATA10_MAP => DATA10_MAP,
DATA11_MAP => DATA11_MAP,
DATA12_MAP => DATA12_MAP,
DATA13_MAP => DATA13_MAP,
DATA14_MAP => DATA14_MAP,
DATA15_MAP => DATA15_MAP,
DATA16_MAP => DATA16_MAP,
DATA17_MAP => DATA17_MAP,
MASK0_MAP => MASK0_MAP,
MASK1_MAP => MASK1_MAP,
CALIB_ROW_ADD => CALIB_ROW_ADD,
CALIB_COL_ADD => CALIB_COL_ADD,
CALIB_BA_ADD => CALIB_BA_ADD,
SLOT_0_CONFIG => SLOT_0_CONFIG,
SLOT_1_CONFIG => SLOT_1_CONFIG,
MEM_ADDR_ORDER => MEM_ADDR_ORDER,
STARVE_LIMIT => STARVE_LIMIT,
USE_CS_PORT => USE_CS_PORT,
USE_DM_PORT => USE_DM_PORT,
USE_ODT_PORT => USE_ODT_PORT,
IDELAY_ADJ => "OFF",
FINE_PER_BIT => "OFF",
CENTER_COMP_MODE => "OFF",
PI_VAL_ADJ => "OFF",
MASTER_PHY_CTL => PHY_CONTROL_MASTER_BANK,
TAPSPERKCLK => TAPSPERKCLK,
SKIP_CALIB => "FALSE",
FPGA_VOLT_TYPE => "N"
)
port map (
clk => clk,
clk_div2 => clk_div2,
rst_div2 => rst_div2,
clk_ref => clk_ref,
mem_refclk => mem_refclk, --memory clock
freq_refclk => freq_refclk,
pll_lock => pll_locked,
sync_pulse => sync_pulse,
rst => rst,
rst_phaser_ref => rst_phaser_ref,
ref_dll_lock => ref_dll_lock,
iddr_rst => iddr_rst,
mmcm_ps_clk => mmcm_ps_clk,
poc_sample_pd => poc_sample_pd,
-- Memory interface ports
ddr_dq => ddr2_dq,
ddr_dqs_n => ddr2_dqs_n,
ddr_dqs => ddr2_dqs_p,
ddr_addr => ddr2_addr,
ddr_ba => ddr2_ba,
ddr_cas_n => ddr2_cas_n,
ddr_ck_n => ddr2_ck_n,
ddr_ck => ddr2_ck_p,
ddr_cke => ddr2_cke,
ddr_cs_n => ddr2_cs_n,
ddr_dm => ddr2_dm,
ddr_odt => ddr2_odt,
ddr_ras_n => ddr2_ras_n,
ddr_reset_n => ddr2_reset_n,
ddr_parity => ddr2_parity,
ddr_we_n => ddr2_we_n,
bank_mach_next => bank_mach_next,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_hi_pri => '0',
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_mask => app_wdf_mask,
app_wdf_wren => app_wdf_wren,
app_ecc_multiple_err => app_ecc_multiple_err,
app_ecc_single_err => app_ecc_single_err,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => app_sr_req,
app_sr_active => app_sr_active,
app_ref_req => app_ref_req,
app_ref_ack => app_ref_ack,
app_zq_req => app_zq_req,
app_zq_ack => app_zq_ack,
app_raw_not_ecc => all_zeros,
app_correct_en_i => '1',
psen => psen,
psincdec => psincdec,
psdone => psdone,
device_temp => device_temp,
-- Ports to be used when SKIP_CALIB="TRUE"
calib_tap_req => open,
calib_tap_addr => (others => '0'),
calib_tap_load => '0',
calib_tap_val => (others => '0'),
calib_tap_load_done => '0',
-- Debug logic ports
dbg_idel_up_all => dbg_idel_up_all,
dbg_idel_down_all => dbg_idel_down_all,
dbg_idel_up_cpt => dbg_idel_up_cpt,
dbg_idel_down_cpt => dbg_idel_down_cpt,
dbg_sel_idel_cpt => dbg_sel_idel_cpt,
dbg_sel_all_idel_cpt => dbg_sel_all_idel_cpt,
dbg_sel_pi_incdec => dbg_sel_pi_incdec,
dbg_sel_po_incdec => dbg_sel_po_incdec,
dbg_byte_sel => dbg_byte_sel,
dbg_pi_f_inc => dbg_pi_f_inc,
dbg_pi_f_dec => dbg_pi_f_dec,
dbg_po_f_inc => dbg_po_f_inc,
dbg_po_f_stg23_sel => dbg_po_f_stg23_sel,
dbg_po_f_dec => dbg_po_f_dec,
dbg_cpt_tap_cnt => dbg_cpt_tap_cnt,
dbg_dq_idelay_tap_cnt => dbg_dq_idelay_tap_cnt,
dbg_calib_top => dbg_calib_top,
dbg_cpt_first_edge_cnt => dbg_cpt_first_edge_cnt,
dbg_cpt_second_edge_cnt => dbg_cpt_second_edge_cnt,
dbg_rd_data_offset => dbg_rd_data_offset,
dbg_phy_rdlvl => dbg_phy_rdlvl,
dbg_phy_wrcal => dbg_phy_wrcal,
dbg_final_po_fine_tap_cnt => dbg_final_po_fine_tap_cnt,
dbg_final_po_coarse_tap_cnt => dbg_final_po_coarse_tap_cnt,
dbg_rd_data_edge_detect => dbg_rd_data_edge_detect,
dbg_rddata => dbg_rddata,
dbg_rddata_valid => dbg_rddata_valid,
dbg_rdlvl_done => dbg_rdlvl_done,
dbg_rdlvl_err => dbg_rdlvl_err,
dbg_rdlvl_start => dbg_rdlvl_start,
dbg_wrlvl_fine_tap_cnt => dbg_wrlvl_fine_tap_cnt,
dbg_wrlvl_coarse_tap_cnt => dbg_wrlvl_coarse_tap_cnt,
dbg_tap_cnt_during_wrlvl => dbg_tap_cnt_during_wrlvl,
dbg_wl_edge_detect_valid => dbg_wl_edge_detect_valid,
dbg_wrlvl_done => dbg_wrlvl_done,
dbg_wrlvl_err => dbg_wrlvl_err,
dbg_wrlvl_start => dbg_wrlvl_start,
dbg_phy_wrlvl => dbg_phy_wrlvl,
dbg_phy_init => dbg_phy_init,
dbg_prbs_rdlvl => dbg_prbs_rdlvl,
dbg_dqs_found_cal => dbg_dqs_found_cal,
dbg_pi_counter_read_val => dbg_pi_counter_read_val,
dbg_po_counter_read_val => dbg_po_counter_read_val,
dbg_pi_phaselock_start => dbg_pi_phaselock_start,
dbg_pi_phaselocked_done => dbg_pi_phaselocked_done,
dbg_pi_phaselock_err => dbg_pi_phaselock_err,
dbg_pi_phase_locked_phy4lanes => dbg_pi_phase_locked_phy4lanes,
dbg_pi_dqsfound_start => dbg_pi_dqsfound_start,
dbg_pi_dqsfound_done => dbg_pi_dqsfound_done,
dbg_pi_dqsfound_err => dbg_pi_dqsfound_err,
dbg_pi_dqs_found_lanes_phy4lanes => dbg_pi_dqs_found_lanes_phy4lanes,
dbg_calib_rd_data_offset_1 => dbg_calib_rd_data_offset_1,
dbg_calib_rd_data_offset_2 => dbg_calib_rd_data_offset_2,
dbg_data_offset => dbg_data_offset,
dbg_data_offset_1 => dbg_data_offset_1,
dbg_data_offset_2 => dbg_data_offset_2,
dbg_wrcal_start => dbg_wrcal_start,
dbg_wrcal_done => dbg_wrcal_done,
dbg_wrcal_err => dbg_wrcal_err,
dbg_phy_oclkdelay_cal => dbg_phy_oclkdelay_cal,
dbg_oclkdelay_rd_data => dbg_oclkdelay_rd_data,
dbg_oclkdelay_calib_start => dbg_oclkdelay_calib_start,
dbg_oclkdelay_calib_done => dbg_oclkdelay_calib_done,
dbg_prbs_final_dqs_tap_cnt_r => dbg_prbs_final_dqs_tap_cnt_r_int,
dbg_prbs_first_edge_taps => dbg_prbs_first_edge_taps_int,
dbg_prbs_second_edge_taps => dbg_prbs_second_edge_taps_int,
init_calib_complete => init_calib_complete_i,
dbg_poc => open
);
--*********************************************************************
-- Resetting all RTL debug inputs as the debug ports are not enabled
--*********************************************************************
dbg_idel_down_all <= '0';
dbg_idel_down_cpt <= '0';
dbg_idel_up_all <= '0';
dbg_idel_up_cpt <= '0';
dbg_sel_all_idel_cpt <= '0';
dbg_sel_idel_cpt <= (others => '0');
dbg_byte_sel <= (others => '0');
dbg_sel_pi_incdec <= '0';
dbg_pi_f_inc <= '0';
dbg_pi_f_dec <= '0';
dbg_po_f_inc <= '0';
dbg_po_f_dec <= '0';
dbg_po_f_stg23_sel <= '0';
dbg_sel_po_incdec <= '0';
end architecture arch_ddr_mig;
|
-- $Id: tb_rlink.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_rlink - sim
-- Description: Test bench for rlink_core
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- genlib/clkdivce
-- rbus/tbd_tester
-- rbus/rb_mon
-- rlink/rlink_mon
-- tbd_rlink_gen [UUT]
--
-- To test: rlink_core (via tbd_rlink_direct)
-- rlink_base (via tbd_rlink_serport)
-- rlink_serport (via tbd_rlink_serport)
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 use new simclk/simclkcnt
-- 2011-11-19 427 3.0.7 fix crc8_update_tbl usage; now numeric_std clean
-- 2010-12-29 351 3.0.6 use new rbd_tester addr 111100xx (from 111101xx)
-- 2010-12-26 348 3.0.5 use simbus to export clkcycle (for tbd_..serport)
-- 2010-12-23 347 3.0.4 use rb_mon, rlink_mon directly; rename CP_*->RL_*
-- 2010-12-22 346 3.0.3 add .rlmon and .rbmon commands
-- 2010-12-21 345 3.0.2 rename commands .[rt]x... to [rt]x...;
-- add .[rt]x(idle|attn) cmds; remove 'bbbbbbbb' cmd
-- 2010-12-12 344 3.0.1 add .attn again; add .txbad, .txoof; ren oob->oof
-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol;
-- use rbd_tester instead of sim target;
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-03 299 2.2.2 new init encoding (WE=0/1 int/ext);use sv_ prefix
-- for shared variables
-- 2010-05-02 287 2.2.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-03 274 2.2 add CE_USEC in tbd_rri_gen interface
-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2008-03-24 129 1.1.2 CLK_CYCLE now 31 bits
-- 2008-01-20 112 1.1.1 rename clkgen->clkdivce
-- 2007-11-24 98 1.1 add RP_IINT support, add checkmiss_tx to test
-- for missing responses
-- 2007-10-26 92 1.0.2 add DONE timestamp at end of execution
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
-- command set:
-- .reset assert RESET for 1 clk
-- .rlmon ien enable rlink monitor
-- .rbmon ien enable rbus monitor
-- .wait n wait n clks
-- .iowt n wait n clks for rlink i/o; auto-extend
-- .attn dat(16) pulse attn lines with dat
-- txsop send <sop>
-- txeop send <eop>
-- txnak send <nak>
-- txidle send <idle>
-- txattn send <attn>
-- tx8 dat(8) send 8 bit value
-- tx16 dat(16) send 16 bit value
-- txcrc send crc
-- txbad send bad (inverted) crc
-- txc cmd(8) send cmd - crc
-- txca cmd(8) addr(8) send cmd - addr - crc
-- txcad cmd(8) addr(8) dat(16) send cmd - addr - dl dh - crc
-- txcac cmd(8) addr(8) cnt(8) send cmd - addr - cnt - crc
-- txoof dat(9) send out-of-frame symbol
-- rxsop reset rx list; expect sop
-- rxeop expect <eop>
-- rxnak expect <nak>
-- rxidle expect <idle>
-- rxattn expect <attn>
-- rx8 dat(8) expect 8 bit value
-- rx16 dat(16) expect 16 bit value
-- rxcrc expect crc
-- rxcs cmd(8) stat(8) expect cmd - stat - crc
-- rxcds cmd(8) dat(16) stat(8) expect cmd - dl dh - stat - crc
-- rxccd cmd(8) ccmd(8) dat(16) stat(8) expect cmd - ccmd - dl dh - stat - crc
-- rxoof dat(9) expect out-of-frame symbol
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.genlib.all;
use work.comlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.simlib.all;
entity tb_rlink is
end tb_rlink;
architecture sim of tb_rlink is
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RESET : slbit := '0';
signal RL_DI : slv9 := (others=>'0');
signal RL_ENA : slbit := '0';
signal RL_BUSY : slbit := '0';
signal RL_DO : slv9 := (others=>'0');
signal RL_VAL : slbit := '0';
signal RL_HOLD : slbit := '0';
signal RB_MREQ_aval : slbit := '0';
signal RB_MREQ_re : slbit := '0';
signal RB_MREQ_we : slbit := '0';
signal RB_MREQ_initt: slbit := '0';
signal RB_MREQ_addr : slv8 := (others=>'0');
signal RB_MREQ_din : slv16 := (others=>'0');
signal RB_SRES_ack : slbit := '0';
signal RB_SRES_busy : slbit := '0';
signal RB_SRES_err : slbit := '0';
signal RB_SRES_dout : slv16 := (others=>'0');
signal RB_LAM_TBENCH : slv16 := (others=>'0');
signal RB_LAM_TESTER : slv16 := (others=>'0');
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal TXRXACT : slbit := '0';
signal RLMON_EN : slbit := '0';
signal RBMON_EN : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
constant slv9_zero : slv9 := (others=>'0');
constant slv16_zero : slv16 := (others=>'0');
type slv9_array_type is array (0 to 255) of slv9;
type slv16_array_type is array (0 to 255) of slv16;
shared variable sv_rxlist : slv9_array_type := (others=>slv9_zero);
shared variable sv_nrxlist : natural := 0;
shared variable sv_rxind : natural := 0;
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
component tbd_rlink_gen is -- rlink, generic tb design interface
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : out slbit; -- rlink: data busy
RL_DO : out slv9; -- rlink: data out
RL_VAL : out slbit; -- rlink: data valid
RL_HOLD : in slbit; -- rlink: data hold
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt: out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv8; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
TXRXACT : out slbit -- txrx active flag
);
end component;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 4,
MSECDIV => 5)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
RB_MREQ.aval <= RB_MREQ_aval;
RB_MREQ.re <= RB_MREQ_re;
RB_MREQ.we <= RB_MREQ_we;
RB_MREQ.init <= RB_MREQ_initt;
RB_MREQ.addr <= RB_MREQ_addr;
RB_MREQ.din <= RB_MREQ_din;
RB_SRES_ack <= RB_SRES.ack;
RB_SRES_busy <= RB_SRES.busy;
RB_SRES_err <= RB_SRES.err;
RB_SRES_dout <= RB_SRES.dout;
RBTEST : rbd_tester
generic map (
RB_ADDR => slv(to_unsigned(2#11110000#,8)))
port map (
CLK => CLK,
RESET => '0',
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM_TESTER,
RB_STAT => RB_STAT
);
RB_LAM <= RB_LAM_TESTER or RB_LAM_TBENCH;
RLMON : rlink_mon
generic map (
DWIDTH => RL_DI'length)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
ENA => RLMON_EN,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD
);
RBMON : rb_mon
generic map (
DBASE => 2)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
ENA => RBMON_EN,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
UUT : tbd_rlink_gen
port map (
CLK => CLK,
CE_INT => CE_MSEC,
CE_USEC => CE_USEC,
RESET => RESET,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD,
RB_MREQ_aval => RB_MREQ_aval,
RB_MREQ_re => RB_MREQ_re,
RB_MREQ_we => RB_MREQ_we,
RB_MREQ_initt=> RB_MREQ_initt,
RB_MREQ_addr => RB_MREQ_addr,
RB_MREQ_din => RB_MREQ_din,
RB_SRES_ack => RB_SRES_ack,
RB_SRES_busy => RB_SRES_busy,
RB_SRES_err => RB_SRES_err,
RB_SRES_dout => RB_SRES_dout,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
TXRXACT => TXRXACT
);
proc_stim: process
file fstim : text open read_mode is "tb_rlink_stim";
variable iline : line;
variable oline : line;
variable ien : slbit := '0';
variable icmd : slv8 := (others=>'0');
variable iaddr : slv8 := (others=>'0');
variable icnt : slv8 := (others=>'0');
variable istat : slv3 := (others=>'0');
variable iattn : slv16 := (others=>'0');
variable idata : slv16 := (others=>'0');
variable ioof : slv9 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable iowait : integer := 0;
variable txcrc,rxcrc : slv8 := (others=>'0');
variable txlist : slv9_array_type := (others=>slv9_zero);
variable ntxlist : natural := 0;
procedure do_tx8 (data : inout slv8) is
begin
txlist(ntxlist) := '0' & data;
ntxlist := ntxlist + 1;
txcrc := crc8_update_tbl(txcrc, data);
end procedure do_tx8;
procedure do_tx16 (data : inout slv16) is
begin
do_tx8(data( 7 downto 0));
do_tx8(data(15 downto 8));
end procedure do_tx16;
procedure do_rx8 (data : inout slv8) is
begin
sv_rxlist(sv_nrxlist) := '0' & data;
sv_nrxlist := sv_nrxlist + 1;
rxcrc := crc8_update_tbl(rxcrc, data);
end procedure do_rx8;
procedure do_rx16 (data : inout slv16) is
begin
do_rx8(data( 7 downto 0));
do_rx8(data(15 downto 8));
end procedure do_rx16;
procedure checkmiss_rx is
begin
if sv_rxind < sv_nrxlist then
for i in sv_rxind to sv_nrxlist-1 loop
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, string'(" FAIL MISSING DATA="));
write(oline, sv_rxlist(i)(8));
write(oline, string'(" "));
write(oline, sv_rxlist(i)(7 downto 0));
writeline(output, oline);
end loop;
end if;
end procedure checkmiss_rx;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".rlmon" => -- .rlmon
read_ea(iline, ien);
RLMON_EN <= ien;
wait for 2*clock_period; -- wait for monitor to start
when ".rbmon" => -- .rbmon
read_ea(iline, ien);
RBMON_EN <= ien;
wait for 2*clock_period; -- wait for monitor to start
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".iowt " => -- .iowt
read_ea(iline, iowait);
idelta := iowait;
while idelta > 0 loop -- until time has expired
if TXRXACT = '1' then -- if any io activity
idelta := iowait; -- restart timer
else
idelta := idelta - 1; -- otherwise count down time
end if;
wait for clock_period;
end loop;
when ".attn " => -- .attn
read_ea(iline, iattn);
RB_LAM_TBENCH <= iattn; -- pulse attn lines
wait for clock_period; -- for 1 clock
RB_LAM_TBENCH <= (others=>'0');
when "txsop " => -- txsop send sop
txlist(0) := c_rlink_dat_sop;
ntxlist := 1;
txcrc := (others=>'0');
when "txeop " => -- txeop send eop
txlist(0) := c_rlink_dat_eop;
ntxlist := 1;
txcrc := (others=>'0');
when "txnak " => -- txnak send nak
txlist(0) := c_rlink_dat_nak;
ntxlist := 1;
txcrc := (others=>'0');
when "txidle" => -- txidle send idle
txlist(0) := c_rlink_dat_idle;
ntxlist := 1;
when "txattn" => -- txattn send attn
txlist(0) := c_rlink_dat_attn;
ntxlist := 1;
when "tx8 " => -- tx8 send 8 bit value
read_ea(iline, iaddr);
ntxlist := 0;
do_tx8(iaddr);
when "tx16 " => -- tx16 send 16 bit value
read_ea(iline, idata);
ntxlist := 0;
do_tx16(idata);
when "txcrc " => -- txcrc send crc
txlist(0) := '0' & txcrc;
ntxlist := 1;
when "txbad " => -- txbad send bad crc
txlist(0) := '0' & (not txcrc);
ntxlist := 1;
when "txc " => -- txc send: cmd crc
read_ea(iline, icmd);
ntxlist := 0;
do_tx8(icmd);
txlist(ntxlist) := '0' & txcrc;
ntxlist := ntxlist + 1;
when "txca " => -- txc send: cmd addr crc
read_ea(iline, icmd);
read_ea(iline, iaddr);
ntxlist := 0;
do_tx8(icmd);
do_tx8(iaddr);
txlist(ntxlist) := '0' & txcrc;
ntxlist := ntxlist + 1;
when "txcad " => -- txc send: cmd addr data crc
read_ea(iline, icmd);
read_ea(iline, iaddr);
read_ea(iline, idata);
ntxlist := 0;
do_tx8(icmd);
do_tx8(iaddr);
do_tx16(idata);
txlist(ntxlist) := '0' & txcrc;
ntxlist := ntxlist + 1;
when "txcac " => -- txc send: cmd addr cnt crc
read_ea(iline, icmd);
read_ea(iline, iaddr);
read_ea(iline, icnt);
ntxlist := 0;
do_tx8(icmd);
do_tx8(iaddr);
do_tx8(icnt);
txlist(ntxlist) := '0' & txcrc;
ntxlist := ntxlist + 1;
when "txoof " => -- txoof send out-of-frame symbol
read_ea(iline, txlist(0));
ntxlist := 1;
when "rxsop " => -- rxsop expect sop
checkmiss_rx;
sv_rxlist(0) := c_rlink_dat_sop;
sv_nrxlist := 1;
sv_rxind := 0;
rxcrc := (others=>'0');
when "rxeop " => -- rxeop expect eop
sv_rxlist(sv_nrxlist) := c_rlink_dat_eop;
sv_nrxlist := sv_nrxlist + 1;
when "rxnak " => -- rxnak expect nak
sv_rxlist(sv_nrxlist) := c_rlink_dat_nak;
sv_nrxlist := sv_nrxlist + 1;
when "rxidle" => -- rxidle expect idle
sv_rxlist(sv_nrxlist) := c_rlink_dat_idle;
sv_nrxlist := sv_nrxlist + 1;
when "rxattn" => -- rxattn expect attn
sv_rxlist(sv_nrxlist) := c_rlink_dat_attn;
sv_nrxlist := sv_nrxlist + 1;
when "rx8 " => -- rx8 expect 8 bit value
read_ea(iline, iaddr);
do_rx8(iaddr);
when "rx16 " => -- rx16 expect 16 bit value
read_ea(iline, idata);
do_rx16(idata);
when "rxcrc " => -- rxcrc expect crc
sv_rxlist(sv_nrxlist) := '0' & rxcrc;
sv_nrxlist := sv_nrxlist+1;
when "rxcs " => -- rxcs expect: cmd stat crc
read_ea(iline, icmd);
read_ea(iline, iaddr);
do_rx8(icmd);
do_rx8(iaddr);
sv_rxlist(sv_nrxlist) := '0' & rxcrc;
sv_nrxlist := sv_nrxlist + 1;
when "rxcds " => -- rxcsd expect: cmd data stat crc
read_ea(iline, icmd);
read_ea(iline, idata);
read_ea(iline, iaddr);
do_rx8(icmd);
do_rx16(idata);
do_rx8(iaddr);
sv_rxlist(sv_nrxlist) := '0' & rxcrc;
sv_nrxlist := sv_nrxlist + 1;
when "rxccd " => -- rxccd expect: cmd ccmd dat stat crc
read_ea(iline, icmd);
read_ea(iline, icnt);
read_ea(iline, idata);
read_ea(iline, iaddr);
do_rx8(icmd);
do_rx8(icnt);
do_rx16(idata);
do_rx8(iaddr);
sv_rxlist(sv_nrxlist) := '0' & rxcrc;
sv_nrxlist := sv_nrxlist + 1;
when "rxoof " => -- rxoof expect: out-of-frame symbol
read_ea(iline, ioof);
sv_rxlist(sv_nrxlist) := ioof;
sv_nrxlist := sv_nrxlist + 1;
when others => -- bad command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
next file_loop when ntxlist=0;
for i in 0 to ntxlist-1 loop
RL_DI <= txlist(i);
RL_ENA <= '1';
writetimestamp(oline, CLK_CYCLE, ": stim");
write(oline, txlist(i)(8), right, 3);
write(oline, txlist(i)(7 downto 0), right, 9);
if txlist(i)(8) = '1' then
case txlist(i) is
when c_rlink_dat_idle =>
write(oline, string'(" (idle)"));
when c_rlink_dat_sop =>
write(oline, string'(" (sop) "));
when c_rlink_dat_eop =>
write(oline, string'(" (eop) "));
when c_rlink_dat_nak =>
write(oline, string'(" (nak) "));
when c_rlink_dat_attn =>
write(oline, string'(" (attn)"));
when others =>
write(oline, string'(" (????)"));
end case;
end if;
writeline(output, oline);
wait for clock_period;
while RL_BUSY = '1' loop
wait for clock_period;
end loop;
RL_ENA <= '0';
end loop; -- i
ntxlist := 0;
end loop; -- file fstim
wait for 50*clock_period;
checkmiss_rx;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
wait for c2out_time;
if RL_VAL = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni");
write(oline, RL_DO(8), right, 3);
write(oline, RL_DO(7 downto 0), right, 9);
if RL_DO(8) = '1' then
case RL_DO is
when c_rlink_dat_idle =>
write(oline, string'(" (idle)"));
when c_rlink_dat_sop =>
write(oline, string'(" (sop) "));
when c_rlink_dat_eop =>
write(oline, string'(" (eop) "));
when c_rlink_dat_nak =>
write(oline, string'(" (nak) "));
when c_rlink_dat_attn =>
write(oline, string'(" (attn)"));
when others =>
write(oline, string'(" (????)"));
end case;
end if;
if sv_nrxlist > 0 then
write(oline, string'(" CHECK"));
if sv_rxind < sv_nrxlist then
if RL_DO = sv_rxlist(sv_rxind) then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
write(oline, sv_rxlist(sv_rxind)(8), right, 2);
write(oline, sv_rxlist(sv_rxind)(7 downto 0), right, 9);
end if;
sv_rxind := sv_rxind + 1;
else
write(oline, string'(" FAIL, UNEXPECTED"));
end if;
end if;
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:audio_to_AXI:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY week1_audio_to_AXI_0_1 IS
PORT (
audio_in_l : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_in_r : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_in_valid : IN STD_LOGIC;
audio_out_valid_irq : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END week1_audio_to_AXI_0_1;
ARCHITECTURE week1_audio_to_AXI_0_1_arch OF week1_audio_to_AXI_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF week1_audio_to_AXI_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT audio_to_AXI_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER -- Width of S_AXI address bus
);
PORT (
audio_in_l : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_in_r : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_in_valid : IN STD_LOGIC;
audio_out_valid_irq : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT audio_to_AXI_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF week1_audio_to_AXI_0_1_arch: ARCHITECTURE IS "audio_to_AXI_v1_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF week1_audio_to_AXI_0_1_arch : ARCHITECTURE IS "week1_audio_to_AXI_0_1,audio_to_AXI_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF audio_out_valid_irq: SIGNAL IS "xilinx.com:signal:interrupt:1.0 audio_out_valid_irq INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
BEGIN
U0 : audio_to_AXI_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4
)
PORT MAP (
audio_in_l => audio_in_l,
audio_in_r => audio_in_r,
audio_in_valid => audio_in_valid,
audio_out_valid_irq => audio_out_valid_irq,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END week1_audio_to_AXI_0_1_arch;
|
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity mux2 is
port(
b : in std_logic;
notb : in std_logic;
S : in std_logic;
R : out std_logic
);
end mux2;
architecture Behavioural of mux2 is
begin
with S select
R <= b when '0',
notb when others;
end Behavioural;
|
--
-- USB Full-Speed/Hi-Speed Device Controller core - blk_ep_in_ctl.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.USBCore.all;
use work.USBExtra.all;
entity blk_ep_in_ctl is
generic (
USE_ASYNC_FIFO : boolean := false
);
port (
rst : in std_logic;
usb_clk : in std_logic;
axis_clk : in std_logic;
blk_in_xfer : in std_logic;
blk_xfer_in_has_data : out std_logic;
blk_xfer_in_data : out std_logic_vector(7 downto 0);
blk_xfer_in_data_valid : out std_logic;
blk_xfer_in_data_ready : in std_logic;
blk_xfer_in_data_last : out std_logic;
axis_tdata : in std_logic_vector(7 downto 0);
axis_tvalid : in std_logic;
axis_tready : out std_logic;
axis_tlast : in std_logic
);
end blk_ep_in_ctl;
architecture blk_ep_in_ctl of blk_ep_in_ctl is
component blk_in_fifo
port (
m_aclk : in std_logic;
s_aclk : in std_logic;
s_aresetn : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(7 downto 0);
s_axis_tlast : in std_logic;
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
m_axis_tlast : in std_logic;
axis_prog_full : out std_logic
);
end component;
type MACHINE is (S_Idle, S_Xfer);
signal state : MACHINE := S_Idle;
signal s_axis_tvalid : std_logic;
signal s_axis_tready : std_logic;
signal s_axis_tdata : std_logic_vector(7 downto 0);
signal s_axis_tlast : std_logic;
signal m_axis_tvalid : std_logic;
signal m_axis_tready : std_logic;
signal m_axis_tdata : std_logic_vector(7 downto 0);
signal m_axis_tlast : std_logic;
signal prog_full : std_logic;
signal was_last_usb : std_logic;
signal was_last : std_logic;
signal was_last_d : std_logic;
signal was_last_dd : std_logic;
begin
FSM: process(usb_clk) is
begin
if rst = '1' then
state <= S_Idle;
blk_xfer_in_has_data <= '0';
elsif rising_edge(usb_clk) then
case state is
when S_Idle =>
if was_last_usb = '1' OR prog_full = '1' then
blk_xfer_in_has_data <= '1';
end if;
if blk_in_xfer = '1' then
state <= S_Xfer;
end if;
when S_Xfer =>
if blk_in_xfer = '0' then
blk_xfer_in_has_data <= '0';
state <= S_Idle;
end if;
end case;
end if;
end process;
ASYNC: if USE_ASYNC_FIFO generate
-- 3 of data clk => axis_clk < 180 MHz if usb_clk = 60 MHz
was_last_usb <= was_last OR was_last_d OR was_last_dd;
FIFO: blk_in_fifo
port map (
m_aclk => usb_clk,
s_aclk => axis_clk,
s_aresetn => NOT rst,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tlast => s_axis_tlast,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tlast => m_axis_tlast,
axis_prog_full => prog_full
);
end generate;
SYNC: if not USE_ASYNC_FIFO generate
was_last_usb <= was_last;
FIFO: sync_fifo
generic map (
FIFO_WIDTH => 8,
FIFO_DEPTH => 1024,
PROG_FULL_VALUE => 64
)
port map (
clk => usb_clk,
rst => rst,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tlast => s_axis_tlast,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tlast => m_axis_tlast,
prog_full => prog_full
);
end generate;
WAS_LAST_LATCHER: process(axis_clk) is
begin
if rst = '1' then
was_last <= '0';
was_last_d <= '0';
was_last_dd <= '0';
elsif rising_edge(axis_clk) then
if s_axis_tvalid = '1' AND s_axis_tready = '1' AND s_axis_tlast = '1' then
was_last <= '1';
elsif s_axis_tvalid = '1' AND s_axis_tready = '1' AND s_axis_tlast = '0' then
was_last <= '0';
end if;
was_last_d <= was_last;
was_last_dd <= was_last_d;
end if;
end process;
s_axis_tdata <= axis_tdata;
s_axis_tvalid <= axis_tvalid;
axis_tready <= s_axis_tready;
s_axis_tlast <= axis_tlast;
blk_xfer_in_data <= m_axis_tdata;
blk_xfer_in_data_valid <= m_axis_tvalid;
m_axis_tready <= blk_xfer_in_data_ready;
blk_xfer_in_data_last <= m_axis_tlast;
end blk_ep_in_ctl; |
-------------------------------------------------------------------------------
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dpSRAM_5128 is
port (
clk_i : in std_logic;
-- Port 0
porta0_addr_i : in std_logic_vector(18 downto 0);
porta0_ce_i : in std_logic;
porta0_oe_i : in std_logic;
porta0_we_i : in std_logic;
porta0_data_i : in std_logic_vector(7 downto 0);
porta0_data_o : out std_logic_vector(7 downto 0);
-- Port 1
porta1_addr_i : in std_logic_vector(18 downto 0);
porta1_ce_i : in std_logic;
porta1_oe_i : in std_logic;
porta1_we_i : in std_logic;
porta1_data_i : in std_logic_vector(7 downto 0);
porta1_data_o : out std_logic_vector(7 downto 0);
-- SRAM in board
sram_addr_o : out std_logic_vector(18 downto 0);
sram_data_io : inout std_logic_vector(7 downto 0);
sram_ce_n_o : out std_logic := '1';
sram_oe_n_o : out std_logic := '1';
sram_we_n_o : out std_logic := '1'
);
end entity;
architecture Behavior of dpSRAM_5128 is
signal sram_we_s : std_logic;
signal sram_oe_s : std_logic;
begin
sram_ce_n_o <= '0'; -- sempre ativa
sram_we_n_o <= sram_we_s;
sram_oe_n_o <= sram_oe_s;
process (clk_i)
variable state_v : std_logic := '0';
variable p0_ce_v : std_logic_vector(1 downto 0);
variable p1_ce_v : std_logic_vector(1 downto 0);
variable acesso0_v : std_logic;
variable acesso1_v : std_logic;
variable p0_req_v : std_logic := '0';
variable p1_req_v : std_logic := '0';
variable p0_we_v : std_logic := '0';
variable p1_we_v : std_logic := '0';
variable p0_addr_v : std_logic_vector(18 downto 0);
variable p1_addr_v : std_logic_vector(18 downto 0);
variable p0_data_v : std_logic_vector(7 downto 0);
variable p1_data_v : std_logic_vector(7 downto 0);
begin
if rising_edge(clk_i) then
acesso0_v := porta0_ce_i and (porta0_oe_i or porta0_we_i);
acesso1_v := porta1_ce_i and (porta1_oe_i or porta1_we_i);
p0_ce_v := p0_ce_v(0) & acesso0_v;
p1_ce_v := p1_ce_v(0) & acesso1_v;
if p0_ce_v = "01" then -- detecta rising edge do pedido da porta0
p0_req_v := '1'; -- marca que porta0 pediu acesso
p0_we_v := '0'; -- por enquanto eh leitura
p0_addr_v := porta0_addr_i; -- pegamos endereco
if porta0_we_i = '1' then -- se foi gravacao que a porta0 pediu
p0_we_v := '1'; -- marcamos que eh gravacao
p0_data_v := porta0_data_i; -- pegamos dado
end if;
end if;
if p1_ce_v = "01" then -- detecta rising edge do pedido da porta1
p1_req_v := '1'; -- marca que porta1 pediu acesso
p1_we_v := '0'; -- por enquanto eh leitura
p1_addr_v := porta1_addr_i; -- pegamos endereco
if porta1_we_i = '1' then -- se foi gravacao que a porta1 pediu
p1_we_v := '1'; -- marcamos que eh gravacao
p1_data_v := porta1_data_i; -- pegamos dado
end if;
end if;
if state_v = '0' then -- Estado 0
sram_data_io <= (others => 'Z'); -- desconectar bus da SRAM
if p0_req_v = '1' then -- pedido da porta0 pendente
sram_addr_o <= p0_addr_v; -- colocamos o endereco pedido na SRAM
sram_we_s <= '1';
-- sram_ce_n <= '0';
sram_oe_s <= '0';
if p0_we_v = '1' then -- se for gravacao
sram_data_io <= p0_data_v; -- damos o dado para a SRAM
sram_we_s <= '0'; -- e dizemos para ela gravar
sram_oe_s <= '1';
end if;
state_v := '1';
elsif p1_req_v = '1' then -- pedido da porta1 pendente
sram_addr_o <= p1_addr_v; -- colocamos o endereco pedido na SRAM
sram_we_s <= '1';
-- sram_ce_n <= '0';
sram_oe_s <= '0';
if p1_we_v = '1' then -- se for gravacao
sram_data_io <= p1_data_v; -- damos o dado para a SRAM
sram_we_s <= '0'; -- e dizemos para ela gravar
sram_oe_s <= '1';
end if;
state_v := '1'; -- proximo rising do clock vamos para segundo estado
end if;
elsif state_v = '1' then -- Estado 1
if p0_req_v = '1' then -- pedido da porta0 pendente
sram_we_s <= '1';
sram_data_io <= (others => 'Z'); -- desconectar bus da SRAM
if p0_we_v = '0' then -- se for leitura
porta0_data_o <= sram_data_io; -- pegamos o dado que a SRAM devolveu
end if;
p0_req_v := '0'; -- limpamos a flag de requisicao da porta0
state_v := '0'; -- voltar para estado 0
sram_oe_s <= '1';
-- sram_ce_n <= '1';
elsif p1_req_v = '1' then -- pedido da porta1 pendente
sram_we_s <= '1';
sram_data_io <= (others => 'Z'); -- desconectar bus da SRAM
if p1_we_v = '0' then -- se for leitura
porta1_data_o <= sram_data_io; -- pegamos o dado que a SRAM devolveu
end if;
p1_req_v := '0'; -- limpamos a flag de requisicao da porta1
state_v := '0'; -- voltar para estado 0
sram_oe_s <= '1';
-- sram_ce_n <= '1';
end if;
end if;
end if;
end process;
end; |
-------------------------------------------------------------------------------
-- Process Data Interface (PDI) ap irq generator
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity apIrqGen is
generic (
genOnePdiClkDomain_g : boolean := false
);
port (
--CLOCK DOMAIN PCP
clkA : in std_logic;
rstA : in std_logic;
irqA : in std_logic; --toggle from MAC
enableA : in std_logic; --APIRQ_CONTROL / IRQ_En
modeA : in std_logic; --APIRQ_CONTROL / IRQ_MODE
setA : in std_logic; --APIRQ_CONTROL / IRQ_SET
--CLOCK DOMAIN AP
clkB : in std_logic;
rstB : in std_logic;
ackB : in std_logic; --APIRQ_CONTROL / IRQ_ACK
irqB : out std_logic
);
end entity apIrqGen;
architecture rtl of apIrqGen is
type fsm_t is (wait4event, setIrq, wait4ack);
signal fsm : fsm_t;
signal enable, mode, irq, toggle, set : std_logic;
begin
--everything is done in clkB domain!
theFsm : process(clkB, rstB)
begin
if rstB = '1' then
irqB <= '0';
fsm <= wait4event;
elsif clkB = '1' and clkB'event then
if enable = '1' then
case fsm is
when wait4event =>
if mode = '0' and set = '1' then
fsm <= setIrq;
elsif mode = '1' and irq = '1' then
fsm <= setIrq;
else
fsm <= wait4event;
end if;
when setIrq =>
irqB <= '1';
fsm <= wait4ack;
when wait4ack =>
if ackB = '1' then
irqB <= '0';
fsm <= wait4event;
else
fsm <= wait4ack;
end if;
end case;
else
irqB <= '0';
fsm <= wait4event;
end if;
end if;
end process;
syncEnable : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => enableA,
dout => enable,
clk => clkB,
rst => rstB
);
syncSet : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
dataSrc => setA,
dataDst => set,
clkSrc => clkA,
rstSrc => rstA,
clkDst => clkB,
rstDst => rstB
);
syncMode : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => modeA,
dout => mode,
clk => clkB,
rst => rstB
);
syncToggle : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => irqA,
dout => toggle,
clk => clkB,
rst => rstB
);
toggleEdgeDet : entity work.edgeDet
port map (
din => toggle,
rising => open,
falling => open,
any => irq,
clk => clkB,
rst => rstB
);
end architecture rtl; |
-------------------------------------------------------------------------------
-- Process Data Interface (PDI) ap irq generator
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity apIrqGen is
generic (
genOnePdiClkDomain_g : boolean := false
);
port (
--CLOCK DOMAIN PCP
clkA : in std_logic;
rstA : in std_logic;
irqA : in std_logic; --toggle from MAC
enableA : in std_logic; --APIRQ_CONTROL / IRQ_En
modeA : in std_logic; --APIRQ_CONTROL / IRQ_MODE
setA : in std_logic; --APIRQ_CONTROL / IRQ_SET
--CLOCK DOMAIN AP
clkB : in std_logic;
rstB : in std_logic;
ackB : in std_logic; --APIRQ_CONTROL / IRQ_ACK
irqB : out std_logic
);
end entity apIrqGen;
architecture rtl of apIrqGen is
type fsm_t is (wait4event, setIrq, wait4ack);
signal fsm : fsm_t;
signal enable, mode, irq, toggle, set : std_logic;
begin
--everything is done in clkB domain!
theFsm : process(clkB, rstB)
begin
if rstB = '1' then
irqB <= '0';
fsm <= wait4event;
elsif clkB = '1' and clkB'event then
if enable = '1' then
case fsm is
when wait4event =>
if mode = '0' and set = '1' then
fsm <= setIrq;
elsif mode = '1' and irq = '1' then
fsm <= setIrq;
else
fsm <= wait4event;
end if;
when setIrq =>
irqB <= '1';
fsm <= wait4ack;
when wait4ack =>
if ackB = '1' then
irqB <= '0';
fsm <= wait4event;
else
fsm <= wait4ack;
end if;
end case;
else
irqB <= '0';
fsm <= wait4event;
end if;
end if;
end process;
syncEnable : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => enableA,
dout => enable,
clk => clkB,
rst => rstB
);
syncSet : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
dataSrc => setA,
dataDst => set,
clkSrc => clkA,
rstSrc => rstA,
clkDst => clkB,
rstDst => rstB
);
syncMode : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => modeA,
dout => mode,
clk => clkB,
rst => rstB
);
syncToggle : entity work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
din => irqA,
dout => toggle,
clk => clkB,
rst => rstB
);
toggleEdgeDet : entity work.edgeDet
port map (
din => toggle,
rising => open,
falling => open,
any => irq,
clk => clkB,
rst => rstB
);
end architecture rtl; |
--Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.all;
entity onchip_memory2_0 is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal clken : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity onchip_memory2_0;
architecture europa of onchip_memory2_0 is
--synthesis translate_off
component altsyncram is
GENERIC (
byte_size : NATURAL;
lpm_type : STRING;
maximum_depth : NATURAL;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_reg_a : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
width_a : NATURAL;
width_byteena_a : NATURAL;
widthad_a : NATURAL
);
PORT (
signal q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal clock0 : IN STD_LOGIC;
signal address_a : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
signal clocken0 : IN STD_LOGIC;
signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component altsyncram;
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- component altsyncram is
--GENERIC (
-- byte_size : NATURAL;
-- init_file : STRING;
-- lpm_type : STRING;
-- maximum_depth : NATURAL;
-- numwords_a : NATURAL;
-- operation_mode : STRING;
-- outdata_reg_a : STRING;
-- ram_block_type : STRING;
-- read_during_write_mode_mixed_ports : STRING;
-- width_a : NATURAL;
-- width_byteena_a : NATURAL;
-- widthad_a : NATURAL
-- );
-- PORT (
-- signal q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
-- signal wren_a : IN STD_LOGIC;
-- signal byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
-- signal clock0 : IN STD_LOGIC;
-- signal address_a : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
-- signal clocken0 : IN STD_LOGIC;
-- signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
-- );
-- end component altsyncram;
--synthesis read_comments_as_HDL off
signal internal_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren : STD_LOGIC;
begin
wren <= chipselect AND write;
--s1, which is an e_avalon_slave
--s2, which is an e_avalon_slave
--vhdl renameroo for output signals
readdata <= internal_readdata;
--synthesis translate_off
the_altsyncram : altsyncram
generic map(
byte_size => 8,
lpm_type => "altsyncram",
maximum_depth => 10240,
numwords_a => 10240,
operation_mode => "SINGLE_PORT",
outdata_reg_a => "UNREGISTERED",
ram_block_type => "AUTO",
read_during_write_mode_mixed_ports => "DONT_CARE",
width_a => 32,
width_byteena_a => 4,
widthad_a => 14
)
port map(
address_a => address,
byteena_a => byteenable,
clock0 => clk,
clocken0 => clken,
data_a => writedata,
q_a => internal_readdata,
wren_a => wren
);
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- the_altsyncram : altsyncram
-- generic map(
-- byte_size => 8,
-- init_file => "onchip_memory2_0.hex",
-- lpm_type => "altsyncram",
-- maximum_depth => 10240,
-- numwords_a => 10240,
-- operation_mode => "SINGLE_PORT",
-- outdata_reg_a => "UNREGISTERED",
-- ram_block_type => "AUTO",
-- read_during_write_mode_mixed_ports => "DONT_CARE",
-- width_a => 32,
-- width_byteena_a => 4,
-- widthad_a => 14
-- )
-- port map(
-- address_a => address,
-- byteena_a => byteenable,
-- clock0 => clk,
-- clocken0 => clken,
-- data_a => writedata,
-- q_a => internal_readdata,
-- wren_a => wren
-- );
--
--synthesis read_comments_as_HDL off
end europa;
|
-- $Id: tb_nexys2_fusp.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys2_fusp - sim
-- Description: Test bench for nexys2 (base+fusp)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- rlink/tbcore/tbcore_rlink
-- tb_nexys2_core
-- serport/tb/serport_master_tb
-- nexys2_fusp_aif [UUT]
--
-- To test: generic, any nexys2_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 3.3.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 3.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 3.3.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 3.3 use serport_master instead of serport_uart_rxtx
-- 2011-12-23 444 3.2 new system clock scheme, new tbcore_rlink iface
-- 2011-11-26 433 3.1.1 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 3.1 update O_FLA_CE_N usage
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-29 351 3.0 use rlink/tb now
-- 2010-11-13 338 1.0.2 now dcm aware: add O_CLKSYS, use rritb_core_dcm
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0 Initial version (derived from tb_s3board_fusp)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys2lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys2_fusp is
end tb_nexys2_fusp;
architecture sim of tb_nexys2_fusp is
signal CLKOSC : slbit := '0';
signal CLKCOM : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal RX_HOLD : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_FLA_CE_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
RX_HOLD <= TXBUSY or RTS_N; -- back pressure for data flow to tb
N2CORE : entity work.tb_nexys2_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys2_fusp_aif
port map (
I_CLK50 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_FLA_CE_N => O_FLA_CE_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => UART_RXD,
TXSD => UART_TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
|
-------------------------------------------------------------------------------
--
-- Title : clz
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\clz.vhd
-- Generated : Mon Dec 5 18:25:30 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {clz} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity clz is
port(
rs1: in std_logic_vector(63 downto 0);
rd: out std_logic_vector (63 downto 0)
);
end clz;
--}} End of automatically maintained section
architecture behavioral of clz is
begin
process (rs1)
variable counter: integer range 0 to 32;
begin
for i in 32 to 63 loop
if (rs1(95-i) = '1') then
exit;
else
counter := counter + 1;
end if;
end loop;
rd(63 downto 32) <= std_logic_vector(to_unsigned(counter,32));
counter := 0;
for i in 0 to 31 loop
if (rs1(31-i) = '1') then
exit;
else
counter := counter + 1;
end if;
end loop;
rd(31 downto 0) <= std_logic_vector(to_unsigned(counter,32));
counter := 0;
end process;
end behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.cart_slot_pkg.all;
entity cart_slot_registers is
generic (
g_cartreset_init: std_logic := '0';
g_boot_stop : boolean := false;
g_kernal_repl : boolean := true;
g_ram_expansion : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_cart_control;
status : in t_cart_status );
end entity;
architecture rtl of cart_slot_registers is
signal control_i : t_cart_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
control_i.cartridge_kill <= '0';
control_i.cartridge_force <= '0';
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cart_c64_mode =>
if io_req.data(2)='1' then
control_i.c64_reset <= '1';
elsif io_req.data(3)='1' then
control_i.c64_reset <= '0';
else
control_i.c64_ultimax <= io_req.data(1);
control_i.c64_nmi <= io_req.data(4);
end if;
when c_cart_c64_stop =>
control_i.c64_stop <= io_req.data(0);
when c_cart_c64_stop_mode =>
control_i.c64_stop_mode <= io_req.data(1 downto 0);
when c_cart_cartridge_type =>
control_i.cartridge_type <= io_req.data(4 downto 0);
control_i.cartridge_variant <= io_req.data(7 downto 5);
when c_cart_cartridge_kill =>
control_i.cartridge_kill <= io_req.data(0);
control_i.cartridge_force <= io_req.data(1);
when c_cart_kernal_enable =>
if g_kernal_repl then
control_i.kernal_enable <= io_req.data(0);
control_i.kernal_16k <= io_req.data(1);
end if;
when c_cart_reu_enable =>
control_i.reu_enable <= io_req.data(0);
when c_cart_reu_size =>
control_i.reu_size <= io_req.data(2 downto 0);
when c_cart_serve_control =>
control_i.serve_while_stopped <= io_req.data(0);
when c_cart_timing =>
control_i.timing_addr_valid <= unsigned(io_req.data(2 downto 0));
when c_cart_phi2_recover =>
control_i.phi2_edge_recover <= io_req.data(0);
when c_cart_swap_buttons =>
control_i.swap_buttons <= io_req.data(0);
when c_cart_sampler_enable =>
control_i.sampler_enable <= io_req.data(0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cart_c64_mode =>
io_resp.data(1) <= control_i.c64_ultimax;
io_resp.data(2) <= control_i.c64_reset;
io_resp.data(4) <= control_i.c64_nmi;
when c_cart_c64_stop =>
io_resp.data(0) <= control_i.c64_stop;
io_resp.data(1) <= status.c64_stopped;
when c_cart_c64_stop_mode =>
io_resp.data(1 downto 0) <= control_i.c64_stop_mode;
when c_cart_c64_clock_detect =>
io_resp.data(0) <= status.clock_detect;
io_resp.data(1) <= status.c64_vcc;
io_resp.data(2) <= status.exrom;
io_resp.data(3) <= status.game;
io_resp.data(4) <= status.reset_in;
io_resp.data(5) <= status.nmi;
when c_cart_cartridge_type =>
io_resp.data(4 downto 0) <= control_i.cartridge_type;
io_resp.data(7 downto 5) <= control_i.cartridge_variant;
when c_cart_cartridge_active =>
io_resp.data(0) <= status.cart_active;
when c_cart_kernal_enable =>
io_resp.data(0) <= control_i.kernal_enable;
io_resp.data(1) <= control_i.kernal_16k;
when c_cart_reu_enable =>
io_resp.data(0) <= control_i.reu_enable;
when c_cart_reu_size =>
io_resp.data(2 downto 0) <= control_i.reu_size;
when c_cart_serve_control =>
io_resp.data(0) <= control_i.serve_while_stopped;
when c_cart_sampler_enable =>
io_resp.data(0) <= control_i.sampler_enable;
when c_cart_timing =>
io_resp.data(2 downto 0) <= std_logic_vector(control_i.timing_addr_valid);
when c_cart_phi2_recover =>
io_resp.data(0) <= control_i.phi2_edge_recover;
when c_cart_swap_buttons =>
io_resp.data(0) <= control_i.swap_buttons;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_cart_control_init;
control_i.c64_reset <= g_cartreset_init;
if g_boot_stop then
control_i.c64_stop <= '1';
control_i.c64_stop_mode <= "10";
end if;
end if;
end if;
end process;
end architecture;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: dataMemory_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY dataMemory_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE dataMemory_synth_ARCH OF dataMemory_synth IS
COMPONENT dataMemory_exdes
PORT (
--Inputs - Port A
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ENA: STD_LOGIC := '0';
SIGNAL ENA_R: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_SHIFT: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_SHIFT_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 32,
READ_WIDTH => 32 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
ENA => ENA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
ADDRA_SHIFT(31 DOWNTO 2) <= ADDRA(29 DOWNTO 0) ;
ADDRA_SHIFT(1 DOWNTO 0) <= (OTHERS=> '0' );
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ENA_R <= '0' AFTER 50 ns;
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
ENA_R <= ENA AFTER 50 ns;
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_SHIFT_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
ADDRA_SHIFT_R <= ADDRA_SHIFT AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: dataMemory_exdes PORT MAP (
--Port A
RSTA => RSTA,
ENA => ENA_R,
WEA => WEA_R,
ADDRA => ADDRA_SHIFT_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_std_logic_to_analog is
end tb_std_logic_to_analog;
architecture TB_std_logic2analog of tb_std_logic_to_analog is
-- Component declarations
-- Signal declarations
terminal ana_out : electrical ;
signal ina : std_logic ;
begin
-- Signal assignments
-- Component instances
d2a1 : entity work.std_logic_to_analog(ideal)
port map(
d => ina, -- bit type pin
a => ana_out
);
clk1 : entity work.clock_duty(ideal)
generic map(
off_time => 2 ms,
on_time => 1 ms
)
port map(
CLOCK_OUT => ina -- std_logic type pin
);
R1 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ana_out,
p2 => electrical_ref
);
end TB_std_logic2analog;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_std_logic_to_analog is
end tb_std_logic_to_analog;
architecture TB_std_logic2analog of tb_std_logic_to_analog is
-- Component declarations
-- Signal declarations
terminal ana_out : electrical ;
signal ina : std_logic ;
begin
-- Signal assignments
-- Component instances
d2a1 : entity work.std_logic_to_analog(ideal)
port map(
d => ina, -- bit type pin
a => ana_out
);
clk1 : entity work.clock_duty(ideal)
generic map(
off_time => 2 ms,
on_time => 1 ms
)
port map(
CLOCK_OUT => ina -- std_logic type pin
);
R1 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ana_out,
p2 => electrical_ref
);
end TB_std_logic2analog;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_std_logic_to_analog is
end tb_std_logic_to_analog;
architecture TB_std_logic2analog of tb_std_logic_to_analog is
-- Component declarations
-- Signal declarations
terminal ana_out : electrical ;
signal ina : std_logic ;
begin
-- Signal assignments
-- Component instances
d2a1 : entity work.std_logic_to_analog(ideal)
port map(
d => ina, -- bit type pin
a => ana_out
);
clk1 : entity work.clock_duty(ideal)
generic map(
off_time => 2 ms,
on_time => 1 ms
)
port map(
CLOCK_OUT => ina -- std_logic type pin
);
R1 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ana_out,
p2 => electrical_ref
);
end TB_std_logic2analog;
|
entity sub is
end entity;
architecture test of sub is
type rec is record
x : integer;
end record;
constant c : rec := (x => 2);
signal s : rec := c;
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : rec := c;
begin
r.x := add1(s.x);
assert r.x = 3;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity record9 is
end entity;
architecture test of record9 is
type rec is record
x : bit_vector(1 to 3);
end record;
constant c : rec := (x => "101");
signal s : rec := c;
begin
uut: entity work.sub;
s.x <= "111";
process is
begin
assert s = c;
wait for 1 ns;
assert s = (x => "111");
wait;
end process;
end architecture;
|
entity sub is
end entity;
architecture test of sub is
type rec is record
x : integer;
end record;
constant c : rec := (x => 2);
signal s : rec := c;
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : rec := c;
begin
r.x := add1(s.x);
assert r.x = 3;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity record9 is
end entity;
architecture test of record9 is
type rec is record
x : bit_vector(1 to 3);
end record;
constant c : rec := (x => "101");
signal s : rec := c;
begin
uut: entity work.sub;
s.x <= "111";
process is
begin
assert s = c;
wait for 1 ns;
assert s = (x => "111");
wait;
end process;
end architecture;
|
entity sub is
end entity;
architecture test of sub is
type rec is record
x : integer;
end record;
constant c : rec := (x => 2);
signal s : rec := c;
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : rec := c;
begin
r.x := add1(s.x);
assert r.x = 3;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity record9 is
end entity;
architecture test of record9 is
type rec is record
x : bit_vector(1 to 3);
end record;
constant c : rec := (x => "101");
signal s : rec := c;
begin
uut: entity work.sub;
s.x <= "111";
process is
begin
assert s = c;
wait for 1 ns;
assert s = (x => "111");
wait;
end process;
end architecture;
|
entity sub is
end entity;
architecture test of sub is
type rec is record
x : integer;
end record;
constant c : rec := (x => 2);
signal s : rec := c;
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : rec := c;
begin
r.x := add1(s.x);
assert r.x = 3;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity record9 is
end entity;
architecture test of record9 is
type rec is record
x : bit_vector(1 to 3);
end record;
constant c : rec := (x => "101");
signal s : rec := c;
begin
uut: entity work.sub;
s.x <= "111";
process is
begin
assert s = c;
wait for 1 ns;
assert s = (x => "111");
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- axi_sg_updt_cmdsts_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_cmdsts_if.vhd
-- Description: This entity is the descriptor update command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Update command write interface from fetch sm --
updt_cmnd_wr : in std_logic ; --
updt_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
updt_done : out std_logic ; --
updt_error : out std_logic ; --
updt_interr : out std_logic ; --
updt_slverr : out std_logic ; --
updt_decerr : out std_logic --
);
end axi_sg_updt_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_slverr_i : std_logic := '0';
signal updt_decerr_i : std_logic := '0';
signal updt_interr_i : std_logic := '0';
signal s2mm_error : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_slverr <= updt_slverr_i;
updt_decerr <= updt_decerr_i;
updt_interr <= updt_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor update command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
elsif(updt_cmnd_wr = '1')then
s_axis_updt_cmd_tvalid <= '1';
s_axis_updt_cmd_tdata <= updt_cmnd_data;
elsif(s_axis_updt_cmd_tready = '1')then
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_updt_sts_tready <= '0';
else
m_axis_updt_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_slverr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
updt_decerr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT);
updt_interr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Transfer Done
-------------------------------------------------------------------------------
XFER_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_done <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_done <= m_axis_updt_sts_tdata(DATAMOVER_STS_CMDDONE_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_done <= '0';
end if;
end if;
end process XFER_DONE;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error <= updt_slverr_i or updt_decerr_i or updt_interr_i;
-- Log errors into a global error output
UPDATE_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error <= '0';
elsif(s2mm_error = '1')then
updt_error <= '1';
end if;
end if;
end process UPDATE_ERROR_PROCESS;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_sg_updt_cmdsts_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_cmdsts_if.vhd
-- Description: This entity is the descriptor update command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Update command write interface from fetch sm --
updt_cmnd_wr : in std_logic ; --
updt_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
updt_done : out std_logic ; --
updt_error : out std_logic ; --
updt_interr : out std_logic ; --
updt_slverr : out std_logic ; --
updt_decerr : out std_logic --
);
end axi_sg_updt_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_slverr_i : std_logic := '0';
signal updt_decerr_i : std_logic := '0';
signal updt_interr_i : std_logic := '0';
signal s2mm_error : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_slverr <= updt_slverr_i;
updt_decerr <= updt_decerr_i;
updt_interr <= updt_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor update command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
elsif(updt_cmnd_wr = '1')then
s_axis_updt_cmd_tvalid <= '1';
s_axis_updt_cmd_tdata <= updt_cmnd_data;
elsif(s_axis_updt_cmd_tready = '1')then
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_updt_sts_tready <= '0';
else
m_axis_updt_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_slverr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
updt_decerr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT);
updt_interr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Transfer Done
-------------------------------------------------------------------------------
XFER_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_done <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_done <= m_axis_updt_sts_tdata(DATAMOVER_STS_CMDDONE_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_done <= '0';
end if;
end if;
end process XFER_DONE;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error <= updt_slverr_i or updt_decerr_i or updt_interr_i;
-- Log errors into a global error output
UPDATE_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error <= '0';
elsif(s2mm_error = '1')then
updt_error <= '1';
end if;
end if;
end process UPDATE_ERROR_PROCESS;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_sg_updt_cmdsts_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_cmdsts_if.vhd
-- Description: This entity is the descriptor update command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Update command write interface from fetch sm --
updt_cmnd_wr : in std_logic ; --
updt_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
updt_done : out std_logic ; --
updt_error : out std_logic ; --
updt_interr : out std_logic ; --
updt_slverr : out std_logic ; --
updt_decerr : out std_logic --
);
end axi_sg_updt_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_slverr_i : std_logic := '0';
signal updt_decerr_i : std_logic := '0';
signal updt_interr_i : std_logic := '0';
signal s2mm_error : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_slverr <= updt_slverr_i;
updt_decerr <= updt_decerr_i;
updt_interr <= updt_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor update command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
elsif(updt_cmnd_wr = '1')then
s_axis_updt_cmd_tvalid <= '1';
s_axis_updt_cmd_tdata <= updt_cmnd_data;
elsif(s_axis_updt_cmd_tready = '1')then
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_updt_sts_tready <= '0';
else
m_axis_updt_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_slverr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
updt_decerr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT);
updt_interr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Transfer Done
-------------------------------------------------------------------------------
XFER_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_done <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_done <= m_axis_updt_sts_tdata(DATAMOVER_STS_CMDDONE_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_done <= '0';
end if;
end if;
end process XFER_DONE;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error <= updt_slverr_i or updt_decerr_i or updt_interr_i;
-- Log errors into a global error output
UPDATE_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error <= '0';
elsif(s2mm_error = '1')then
updt_error <= '1';
end if;
end if;
end process UPDATE_ERROR_PROCESS;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_sg_updt_cmdsts_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_cmdsts_if.vhd
-- Description: This entity is the descriptor update command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Update command write interface from fetch sm --
updt_cmnd_wr : in std_logic ; --
updt_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
updt_done : out std_logic ; --
updt_error : out std_logic ; --
updt_interr : out std_logic ; --
updt_slverr : out std_logic ; --
updt_decerr : out std_logic --
);
end axi_sg_updt_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_slverr_i : std_logic := '0';
signal updt_decerr_i : std_logic := '0';
signal updt_interr_i : std_logic := '0';
signal s2mm_error : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_slverr <= updt_slverr_i;
updt_decerr <= updt_decerr_i;
updt_interr <= updt_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor update command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
elsif(updt_cmnd_wr = '1')then
s_axis_updt_cmd_tvalid <= '1';
s_axis_updt_cmd_tdata <= updt_cmnd_data;
elsif(s_axis_updt_cmd_tready = '1')then
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_updt_sts_tready <= '0';
else
m_axis_updt_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_slverr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
updt_decerr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT);
updt_interr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Transfer Done
-------------------------------------------------------------------------------
XFER_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_done <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_done <= m_axis_updt_sts_tdata(DATAMOVER_STS_CMDDONE_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_done <= '0';
end if;
end if;
end process XFER_DONE;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error <= updt_slverr_i or updt_decerr_i or updt_interr_i;
-- Log errors into a global error output
UPDATE_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error <= '0';
elsif(s2mm_error = '1')then
updt_error <= '1';
end if;
end if;
end process UPDATE_ERROR_PROCESS;
end implementation;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book:
package byte_swap_types is
subtype halfword is bit_vector(0 to 15);
end package byte_swap_types;
use work.byte_swap_types.all;
-- end not in book:
entity byte_swap is
port (input : in halfword; output : out halfword);
end entity byte_swap;
--------------------------------------------------
architecture behavior of byte_swap is
begin
swap : process (input)
begin
output(8 to 15) <= input(0 to 7);
output(0 to 7) <= input(8 to 15);
end process swap;
end architecture behavior;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book:
package byte_swap_types is
subtype halfword is bit_vector(0 to 15);
end package byte_swap_types;
use work.byte_swap_types.all;
-- end not in book:
entity byte_swap is
port (input : in halfword; output : out halfword);
end entity byte_swap;
--------------------------------------------------
architecture behavior of byte_swap is
begin
swap : process (input)
begin
output(8 to 15) <= input(0 to 7);
output(0 to 7) <= input(8 to 15);
end process swap;
end architecture behavior;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book:
package byte_swap_types is
subtype halfword is bit_vector(0 to 15);
end package byte_swap_types;
use work.byte_swap_types.all;
-- end not in book:
entity byte_swap is
port (input : in halfword; output : out halfword);
end entity byte_swap;
--------------------------------------------------
architecture behavior of byte_swap is
begin
swap : process (input)
begin
output(8 to 15) <= input(0 to 7);
output(0 to 7) <= input(8 to 15);
end process swap;
end architecture behavior;
|
library IEEE;
use IEEE.std_logic_1164.all;
library Examples;
use Examples.examples.all;
entity Top is
port (
clk_i : in std_logic;
led_o : out std_logic
);
end entity Top;
architecture Structural of Top is
constant FREQ : positive := 125e6;
begin
dut: Blinking
generic map (FREQ => FREQ, SECS => 1)
port map (clk_i => clk_i, led_o => led_o);
end architecture Structural;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:c_addsub:12.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY c_addsub_v12_0_10;
USE c_addsub_v12_0_10.c_addsub_v12_0_10;
ENTITY system_c_addsub_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_c_addsub_0_0;
ARCHITECTURE system_c_addsub_0_0_arch OF system_c_addsub_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_c_addsub_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT c_addsub_v12_0_10 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_XDEVICEFAMILY : STRING;
C_IMPLEMENTATION : INTEGER;
C_A_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_OUT_WIDTH : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_A_TYPE : INTEGER;
C_B_TYPE : INTEGER;
C_LATENCY : INTEGER;
C_ADD_MODE : INTEGER;
C_B_CONSTANT : INTEGER;
C_B_VALUE : STRING;
C_AINIT_VAL : STRING;
C_SINIT_VAL : STRING;
C_CE_OVERRIDES_BYPASS : INTEGER;
C_BYPASS_LOW : INTEGER;
C_SCLR_OVERRIDES_SSET : INTEGER;
C_HAS_C_IN : INTEGER;
C_HAS_C_OUT : INTEGER;
C_BORROW_LOW : INTEGER;
C_HAS_CE : INTEGER;
C_HAS_BYPASS : INTEGER;
C_HAS_SCLR : INTEGER;
C_HAS_SSET : INTEGER;
C_HAS_SINIT : INTEGER
);
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
CLK : IN STD_LOGIC;
ADD : IN STD_LOGIC;
C_IN : IN STD_LOGIC;
CE : IN STD_LOGIC;
BYPASS : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
SSET : IN STD_LOGIC;
SINIT : IN STD_LOGIC;
C_OUT : OUT STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT c_addsub_v12_0_10;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF S: SIGNAL IS "xilinx.com:signal:data:1.0 s_intf DATA";
BEGIN
U0 : c_addsub_v12_0_10
GENERIC MAP (
C_VERBOSITY => 0,
C_XDEVICEFAMILY => "zynq",
C_IMPLEMENTATION => 0,
C_A_WIDTH => 10,
C_B_WIDTH => 10,
C_OUT_WIDTH => 10,
C_CE_OVERRIDES_SCLR => 0,
C_A_TYPE => 0,
C_B_TYPE => 0,
C_LATENCY => 0,
C_ADD_MODE => 0,
C_B_CONSTANT => 0,
C_B_VALUE => "0000000000",
C_AINIT_VAL => "0",
C_SINIT_VAL => "0",
C_CE_OVERRIDES_BYPASS => 1,
C_BYPASS_LOW => 0,
C_SCLR_OVERRIDES_SSET => 1,
C_HAS_C_IN => 0,
C_HAS_C_OUT => 0,
C_BORROW_LOW => 1,
C_HAS_CE => 0,
C_HAS_BYPASS => 0,
C_HAS_SCLR => 0,
C_HAS_SSET => 0,
C_HAS_SINIT => 0
)
PORT MAP (
A => A,
B => B,
CLK => '0',
ADD => '1',
C_IN => '0',
CE => '1',
BYPASS => '0',
SCLR => '0',
SSET => '0',
SINIT => '0',
S => S
);
END system_c_addsub_0_0_arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 21:06:44 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/system_clock_splitter_0_0_sim_netlist.vhdl
-- Design : system_clock_splitter_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clock_splitter_0_0_clock_splitter is
port (
clk_out : out STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_clock_splitter_0_0_clock_splitter : entity is "clock_splitter";
end system_clock_splitter_0_0_clock_splitter;
architecture STRUCTURE of system_clock_splitter_0_0_clock_splitter is
signal clk_i_1_n_0 : STD_LOGIC;
signal \^clk_out\ : STD_LOGIC;
signal last_edge : STD_LOGIC;
begin
clk_out <= \^clk_out\;
clk_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"6F"
)
port map (
I0 => latch_edge,
I1 => last_edge,
I2 => \^clk_out\,
O => clk_i_1_n_0
);
clk_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_in,
CE => '1',
D => clk_i_1_n_0,
Q => \^clk_out\,
R => '0'
);
last_edge_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_in,
CE => '1',
D => latch_edge,
Q => last_edge,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clock_splitter_0_0 is
port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clock_splitter_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_clock_splitter_0_0 : entity is "system_clock_splitter_0_0,clock_splitter,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_clock_splitter_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_clock_splitter_0_0 : entity is "clock_splitter,Vivado 2016.4";
end system_clock_splitter_0_0;
architecture STRUCTURE of system_clock_splitter_0_0 is
begin
U0: entity work.system_clock_splitter_0_0_clock_splitter
port map (
clk_in => clk_in,
clk_out => clk_out,
latch_edge => latch_edge
);
end STRUCTURE;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/fft_16_bit_pkg.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE fft_16_bit_pkg IS
TYPE vector_of_signed17 IS ARRAY (NATURAL RANGE <>) OF signed(16 DOWNTO 0);
TYPE vector_of_std_logic_vector16 IS ARRAY (NATURAL RANGE <>) OF std_logic_vector(15 DOWNTO 0);
TYPE vector_of_std_logic_vector21 IS ARRAY (NATURAL RANGE <>) OF std_logic_vector(20 DOWNTO 0);
END fft_16_bit_pkg;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity other_sim is
port(hi : in std_logic);
end other_sim;
architecture behavioral of other_sim is
component data_stack
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
e0_sel : in STD_LOGIC_VECTOR(1 downto 0);
e1_sel : in STD_LOGIC_VECTOR(1 downto 0);
e2_sel : in STD_LOGIC_VECTOR(1 downto 0);
e0_en : in STD_LOGIC;
e1_en : in STD_LOGIC;
e2_en : in STD_LOGIC;
push : in STD_LOGIC;
pop : in STD_LOGIC;
pop2 : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(31 downto 0);
e0_out : out STD_LOGIC_VECTOR(31 downto 0);
e1_out : out STD_LOGIC_VECTOR(31 downto 0));
end component;
signal clk, rst, e0_en, e1_en, e2_en, push, pop, pop2 : std_logic;
signal e0_sel, e1_sel, e2_sel : std_logic_vector(1 downto 0);
signal data_in, next_data_in, e0_out, e1_out : std_logic_vector(31 downto 0);
type ops_type is (reset, drop, swap, rot, nrot, push_op, dup, rd, nrd, rds, nrds, over, wr_mem);
signal op, next_op: ops_type;
begin
uut : data_stack
port map(
clk => clk,
rst => rst,
e0_sel => e0_sel,
e1_sel => e1_sel,
e2_sel => e2_sel,
e0_en => e0_en,
e1_en => e1_en,
e2_en => e2_en,
push => push,
pop => pop,
pop2 => pop2,
data_in => data_in,
e0_out => e0_out,
e1_out => e1_out
);
ctl : process (clk, rst) is
begin
if rst = '1' then
op <= reset;
data_in <= (others => '0');
elsif rising_edge(clk) then
op <= next_op;
data_in <= next_data_in;
end if;
end process;
ops : process is
begin
next_op <= reset;
next_data_in <= (others => '0');
wait for 100 ns;
next_op <= push_op;
next_data_in <= x"44444444";
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"33333333";
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"22222222";
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"11111111";
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"11111111";
wait for 20 ns;
next_op <= drop;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= swap;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= swap;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= over;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= drop;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= dup;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= drop;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= rot;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= nrot;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= rot;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= drop;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"11111111";
wait for 20 ns;
next_op <= rd;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= drop;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= drop;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= drop;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"44444444";
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"33333333";
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"22222222";
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"11111111";
wait for 20 ns;
next_op <= nrd;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"33333333";
wait for 20 ns;
next_op <= rot;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= rds;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"22222222";
wait for 20 ns;
next_op <= swap;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= nrds;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"88888888";
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"BBBBBBBB";
wait for 20 ns;
next_op <= wr_mem;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= reset;
next_data_in <= (others => '0');
wait;
end process;
ctl_async : process (op) is
begin
case op is
when reset =>
e0_sel <= "00";
e1_sel <= "00";
e2_sel <= "00";
e0_en <= '0';
e1_en <= '0';
e2_en <= '0';
push <= '0';
pop <= '0';
pop2 <= '0';
when drop =>
e0_sel <= "01";
e1_sel <= "01";
e2_sel <= "01";
e0_en <= '1';
e1_en <= '1';
e2_en <= '1';
push <= '0';
pop <= '1';
pop2 <= '0';
when swap =>
e0_sel <= "01";
e1_sel <= "00";
e2_sel <= "00";
e0_en <= '1';
e1_en <= '1';
e2_en <= '0';
push <= '0';
pop <= '0';
pop2 <= '0';
when nrot =>
e0_sel <= "01";
e1_sel <= "01";
e2_sel <= "10";
e0_en <= '1';
e1_en <= '1';
e2_en <= '1';
push <= '0';
pop <= '0';
pop2 <= '0';
when rot =>
e0_sel <= "10";
e1_sel <= "00";
e2_sel <= "00";
e0_en <= '1';
e1_en <= '1';
e2_en <= '1';
push <= '0';
pop <= '0';
pop2 <= '0';
when push_op =>
e0_sel <= "00";
e1_sel <= "00";
e2_sel <= "00";
e0_en <= '1';
e1_en <= '1';
e2_en <= '1';
push <= '1';
pop <= '0';
pop2 <= '0';
when dup =>
e0_sel <= "00";
e1_sel <= "00";
e2_sel <= "00";
e0_en <= '0';
e1_en <= '1';
e2_en <= '1';
push <= '1';
pop <= '0';
pop2 <= '0';
when nrd =>
e0_sel <= "10";
e1_sel <= "00";
e2_sel <= "01";
e0_en <= '1';
e1_en <= '1';
e2_en <= '1';
push <= '0';
pop <= '1';
pop2 <= '0';
when rd =>
e0_sel <= "00";
e1_sel <= "00";
e2_sel <= "01";
e0_en <= '0';
e1_en <= '0';
e2_en <= '1';
push <= '0';
pop <= '1';
pop2 <= '0';
when nrds =>
e0_sel <= "00";
e1_sel <= "01";
e2_sel <= "01";
e0_en <= '0';
e1_en <= '1';
e2_en <= '1';
push <= '0';
pop <= '1';
pop2 <= '0';
when rds =>
e0_sel <= "01";
e1_sel <= "00";
e2_sel <= "01";
e0_en <= '1';
e1_en <= '1';
e2_en <= '1';
push <= '0';
pop <= '1';
pop2 <= '0';
when over =>
e0_sel <= "01";
e1_sel <= "00";
e2_sel <= "00";
e0_en <= '1';
e1_en <= '1';
e2_en <= '1';
push <= '1';
pop <= '0';
pop2 <= '0';
when wr_mem =>
e0_sel <= "10";
e1_sel <= "10";
e2_sel <= "11";
e0_en <= '1';
e1_en <= '1';
e2_en <= '1';
push <= '0';
pop <= '0';
pop2 <= '1';
when others => null;
end case;
end process;
end behavioral; |
-- alu_ctrl.vhd
library ieee;
use ieee.std_logic_1164.all;
use work.myTypes.all;
entity alu_ctrl is
port (
OP : in AluOp;
BOOTH_STALL : in std_logic;
ALU_WORD : out std_logic_vector(12 downto 0)
);
end alu_ctrl;
architecture bhe of alu_ctrl is
signal out_mux_sel : std_logic_vector(2 downto 0);
signal left_right : std_logic;
signal logic_arith : std_logic;
signal sign_to_adder : std_logic;
signal lu_ctrl : std_logic_vector(1 downto 0);
signal comp_sel : std_logic_vector(2 downto 0);
signal enable_to_booth : std_logic;
signal sign_to_booth : std_logic;
begin
enable_to_booth <= '1' when (OP = MULTS or OP = MULTU) and BOOTH_STALL = '0' else
'0';
ALU_WORD <= out_mux_sel&left_right&logic_arith&sign_to_adder&lu_ctrl&comp_sel&enable_to_booth&sign_to_booth;
-- combinatorial process used to send the right data to components
process(OP)
begin
case OP is
-- when NOP we do a random LU operation, maybe change this into something smarter??
when NOP =>
out_mux_sel <= "100";
sign_to_booth <= '0'; -- useless but avoids errors on simulation
when SLLS =>
out_mux_sel <= "010";
left_right <= '0';
logic_arith <= '0';
when SRLS =>
out_mux_sel <= "010";
left_right <= '1';
logic_arith <= '0';
when SRAS =>
out_mux_sel <= "010";
left_right <= '1';
logic_arith <= '1';
when ADDS =>
sign_to_adder <= '0';
out_mux_sel <= "000";
when ADDUS =>
sign_to_adder <= '0';
out_mux_sel <= "000";
when SUBS =>
sign_to_adder <= '1';
out_mux_sel <= "000";
when SUBUS =>
sign_to_adder <= '1';
out_mux_sel <= "000";
when ANDS =>
lu_ctrl <= "00";
out_mux_sel <= "001";
when ORS =>
lu_ctrl <= "01";
out_mux_sel <= "001";
when XORS =>
lu_ctrl <= "10";
out_mux_sel <= "001";
when SEQS =>
sign_to_adder <= '1';
comp_sel <= "100";
out_mux_sel <= "011";
sign_to_booth <= '0';
when SNES =>
sign_to_adder <= '1';
comp_sel <= "101";
out_mux_sel <= "011";
sign_to_booth <= '0';
when SLTS =>
sign_to_adder <= '1';
comp_sel <= "010";
out_mux_sel <= "011";
sign_to_booth <= '1';
when SGTS =>
sign_to_adder <= '1';
comp_sel <= "000";
out_mux_sel <= "011";
sign_to_booth <= '1';
when SLES =>
sign_to_adder <= '1';
comp_sel <= "011";
out_mux_sel <= "011";
sign_to_booth <= '1';
when SGES =>
sign_to_adder <= '1';
comp_sel <= "001";
out_mux_sel <= "011";
sign_to_booth <= '1';
-- UNIMPLEMENTED OPS
-- when MOVI2SS => DOUT <= (others => '0');
-- when MOVS2IS => DOUT <= (others => '0');
-- when MOVFS => DOUT <= (others => '0');
-- when MOVDS => DOUT <= (others => '0');
-- when MOVFP2IS => DOUT <= (others => '0');
-- when MOVI2FP => DOUT <= (others => '0');
-- when MOVI2TS => DOUT <= (others => '0');
-- when MOVT2IS => DOUT <= (others => '0');
when SLTUS =>
sign_to_adder <= '1';
comp_sel <= "010";
out_mux_sel <= "011";
sign_to_booth <= '0';
when SGTUS =>
sign_to_adder <= '1';
comp_sel <= "000";
out_mux_sel <= "011";
sign_to_booth <= '0';
when SLEUS =>
sign_to_adder <= '1';
comp_sel <= "011";
out_mux_sel <= "011";
sign_to_booth <= '0';
when SGEUS =>
sign_to_adder <= '1';
comp_sel <= "001";
out_mux_sel <= "011";
sign_to_booth <= '0';
when MULTU =>
out_mux_sel <= "101";
sign_to_booth <= '0';
when MULTS =>
out_mux_sel <= "101";
sign_to_booth <= '1';
when others => out_mux_sel <= "000";
end case;
end process;
end bhe;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity nco is
generic(
width : integer := 32
);
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto 0);
lo_i_0 : out std_logic_vector(width - 1 downto 0);
lo_i_1 : out std_logic_vector(width - 1 downto 0);
lo_i_2 : out std_logic_vector(width - 1 downto 0);
lo_i_3 : out std_logic_vector(width - 1 downto 0);
lo_i_4 : out std_logic_vector(width - 1 downto 0);
lo_i_5 : out std_logic_vector(width - 1 downto 0);
lo_i_6 : out std_logic_vector(width - 1 downto 0);
lo_i_7 : out std_logic_vector(width - 1 downto 0);
lo_q_0 : out std_logic_vector(width - 1 downto 0);
lo_q_1 : out std_logic_vector(width - 1 downto 0);
lo_q_2 : out std_logic_vector(width - 1 downto 0);
lo_q_3 : out std_logic_vector(width - 1 downto 0);
lo_q_4 : out std_logic_vector(width - 1 downto 0);
lo_q_5 : out std_logic_vector(width - 1 downto 0);
lo_q_6 : out std_logic_vector(width - 1 downto 0);
lo_q_7 : out std_logic_vector(width - 1 downto 0)
);
end entity nco;
architecture rtl of nco is
constant sin_bits : integer := width;
constant sin_scale : real := 2.0**real(sin_bits);
constant sin_output_scale : real := ((2.0**real(sin_bits-1))-1.0) / sqrt(2.0);
constant sin_input_scale : real := ((2.0 * math_pi)/sin_scale);
type sin_array_type is array (0 to (2**sin_bits)-1) of std_logic_vector(sin_bits-1 downto 0);
function initialise_sin_array return sin_array_type is
variable x : sin_array_type;
begin
for i in 0 to (2**sin_bits)-1 loop
x(i) := std_logic_vector(to_signed(-integer(round(sin_output_scale * sin(real(i) * sin_input_scale))), sin_bits));
end loop;
return x;
end function;
function initialise_cos_array return sin_array_type is
variable x : sin_array_type;
begin
for i in 0 to (2**sin_bits)-1 loop
x(i) := std_logic_vector(to_signed(integer(round(sin_output_scale * cos(real(i) * sin_input_scale))), sin_bits));
end loop;
return x;
end function;
constant sin_array : sin_array_type := initialise_sin_array;
constant cos_array : sin_array_type := initialise_cos_array;
signal w_0 : unsigned(31 downto 0);
signal w_1 : unsigned(31 downto 0);
signal w_2 : unsigned(31 downto 0);
signal w_3 : unsigned(31 downto 0);
signal w_4 : unsigned(31 downto 0);
signal w_5 : unsigned(31 downto 0);
signal w_6 : unsigned(31 downto 0);
signal w_7 : unsigned(31 downto 0);
signal frequency_d1 : unsigned(31 downto 0) := (others => '0');
signal frequency_d2 : unsigned(31 downto 0) := (others => '0');
signal frequency_d3 : unsigned(31 downto 0) := (others => '0');
signal accum : unsigned(31 downto 0) := (others => '0');
signal tree_0 : unsigned(31 downto 0) := (others => '0');
signal tree_1 : unsigned(31 downto 0) := (others => '0');
signal tree_00 : unsigned(31 downto 0) := (others => '0');
signal tree_01 : unsigned(31 downto 0) := (others => '0');
signal tree_10 : unsigned(31 downto 0) := (others => '0');
signal tree_11 : unsigned(31 downto 0) := (others => '0');
signal tree_000 : unsigned(31 downto 0) := (others => '0');
signal tree_001 : unsigned(31 downto 0) := (others => '0');
signal tree_010 : unsigned(31 downto 0) := (others => '0');
signal tree_011 : unsigned(31 downto 0) := (others => '0');
signal tree_100 : unsigned(31 downto 0) := (others => '0');
signal tree_101 : unsigned(31 downto 0) := (others => '0');
signal tree_110 : unsigned(31 downto 0) := (others => '0');
signal tree_111 : unsigned(31 downto 0) := (others => '0');
begin
process
begin
wait until rising_edge(clk);
frequency_d1 <= unsigned(frequency);
frequency_d2 <= frequency_d1;
frequency_d3 <= frequency_d2;
accum <= accum + (unsigned(frequency(28 downto 0)) & "000");
tree_0 <= accum;
tree_1 <= accum + (frequency_d1(29 downto 0) & "00");
tree_00 <= tree_0;
tree_01 <= tree_0 + (frequency_d2(30 downto 0) & '0');
tree_10 <= tree_1;
tree_11 <= tree_1 + (frequency_d2(30 downto 0) & '0');
tree_000 <= tree_00;
tree_001 <= tree_00 + frequency_d3;
tree_010 <= tree_01;
tree_011 <= tree_01 + frequency_d3;
tree_100 <= tree_10;
tree_101 <= tree_10 + frequency_d3;
tree_110 <= tree_11;
tree_111 <= tree_11 + frequency_d3;
w_0 <= tree_000;
w_1 <= tree_001;
w_2 <= tree_010;
w_3 <= tree_011;
w_4 <= tree_100;
w_5 <= tree_101;
w_6 <= tree_110;
w_7 <= tree_111;
lo_q_0 <= sin_array(to_integer(w_0(31 downto 32-sin_bits)));
lo_q_1 <= sin_array(to_integer(w_1(31 downto 32-sin_bits)));
lo_q_2 <= sin_array(to_integer(w_2(31 downto 32-sin_bits)));
lo_q_3 <= sin_array(to_integer(w_3(31 downto 32-sin_bits)));
lo_q_4 <= sin_array(to_integer(w_4(31 downto 32-sin_bits)));
lo_q_5 <= sin_array(to_integer(w_5(31 downto 32-sin_bits)));
lo_q_6 <= sin_array(to_integer(w_6(31 downto 32-sin_bits)));
lo_q_7 <= sin_array(to_integer(w_7(31 downto 32-sin_bits)));
lo_i_0 <= cos_array(to_integer(w_0(31 downto 32-sin_bits)));
lo_i_1 <= cos_array(to_integer(w_1(31 downto 32-sin_bits)));
lo_i_2 <= cos_array(to_integer(w_2(31 downto 32-sin_bits)));
lo_i_3 <= cos_array(to_integer(w_3(31 downto 32-sin_bits)));
lo_i_4 <= cos_array(to_integer(w_4(31 downto 32-sin_bits)));
lo_i_5 <= cos_array(to_integer(w_5(31 downto 32-sin_bits)));
lo_i_6 <= cos_array(to_integer(w_6(31 downto 32-sin_bits)));
lo_i_7 <= cos_array(to_integer(w_7(31 downto 32-sin_bits)));
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity nco is
generic(
width : integer := 32
);
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto 0);
lo_i_0 : out std_logic_vector(width - 1 downto 0);
lo_i_1 : out std_logic_vector(width - 1 downto 0);
lo_i_2 : out std_logic_vector(width - 1 downto 0);
lo_i_3 : out std_logic_vector(width - 1 downto 0);
lo_i_4 : out std_logic_vector(width - 1 downto 0);
lo_i_5 : out std_logic_vector(width - 1 downto 0);
lo_i_6 : out std_logic_vector(width - 1 downto 0);
lo_i_7 : out std_logic_vector(width - 1 downto 0);
lo_q_0 : out std_logic_vector(width - 1 downto 0);
lo_q_1 : out std_logic_vector(width - 1 downto 0);
lo_q_2 : out std_logic_vector(width - 1 downto 0);
lo_q_3 : out std_logic_vector(width - 1 downto 0);
lo_q_4 : out std_logic_vector(width - 1 downto 0);
lo_q_5 : out std_logic_vector(width - 1 downto 0);
lo_q_6 : out std_logic_vector(width - 1 downto 0);
lo_q_7 : out std_logic_vector(width - 1 downto 0)
);
end entity nco;
architecture rtl of nco is
constant sin_bits : integer := width;
constant sin_scale : real := 2.0**real(sin_bits);
constant sin_output_scale : real := ((2.0**real(sin_bits-1))-1.0) / sqrt(2.0);
constant sin_input_scale : real := ((2.0 * math_pi)/sin_scale);
type sin_array_type is array (0 to (2**sin_bits)-1) of std_logic_vector(sin_bits-1 downto 0);
function initialise_sin_array return sin_array_type is
variable x : sin_array_type;
begin
for i in 0 to (2**sin_bits)-1 loop
x(i) := std_logic_vector(to_signed(-integer(round(sin_output_scale * sin(real(i) * sin_input_scale))), sin_bits));
end loop;
return x;
end function;
function initialise_cos_array return sin_array_type is
variable x : sin_array_type;
begin
for i in 0 to (2**sin_bits)-1 loop
x(i) := std_logic_vector(to_signed(integer(round(sin_output_scale * cos(real(i) * sin_input_scale))), sin_bits));
end loop;
return x;
end function;
constant sin_array : sin_array_type := initialise_sin_array;
constant cos_array : sin_array_type := initialise_cos_array;
signal w_0 : unsigned(31 downto 0);
signal w_1 : unsigned(31 downto 0);
signal w_2 : unsigned(31 downto 0);
signal w_3 : unsigned(31 downto 0);
signal w_4 : unsigned(31 downto 0);
signal w_5 : unsigned(31 downto 0);
signal w_6 : unsigned(31 downto 0);
signal w_7 : unsigned(31 downto 0);
signal frequency_d1 : unsigned(31 downto 0) := (others => '0');
signal frequency_d2 : unsigned(31 downto 0) := (others => '0');
signal frequency_d3 : unsigned(31 downto 0) := (others => '0');
signal accum : unsigned(31 downto 0) := (others => '0');
signal tree_0 : unsigned(31 downto 0) := (others => '0');
signal tree_1 : unsigned(31 downto 0) := (others => '0');
signal tree_00 : unsigned(31 downto 0) := (others => '0');
signal tree_01 : unsigned(31 downto 0) := (others => '0');
signal tree_10 : unsigned(31 downto 0) := (others => '0');
signal tree_11 : unsigned(31 downto 0) := (others => '0');
signal tree_000 : unsigned(31 downto 0) := (others => '0');
signal tree_001 : unsigned(31 downto 0) := (others => '0');
signal tree_010 : unsigned(31 downto 0) := (others => '0');
signal tree_011 : unsigned(31 downto 0) := (others => '0');
signal tree_100 : unsigned(31 downto 0) := (others => '0');
signal tree_101 : unsigned(31 downto 0) := (others => '0');
signal tree_110 : unsigned(31 downto 0) := (others => '0');
signal tree_111 : unsigned(31 downto 0) := (others => '0');
begin
process
begin
wait until rising_edge(clk);
frequency_d1 <= unsigned(frequency);
frequency_d2 <= frequency_d1;
frequency_d3 <= frequency_d2;
accum <= accum + (unsigned(frequency(28 downto 0)) & "000");
tree_0 <= accum;
tree_1 <= accum + (frequency_d1(29 downto 0) & "00");
tree_00 <= tree_0;
tree_01 <= tree_0 + (frequency_d2(30 downto 0) & '0');
tree_10 <= tree_1;
tree_11 <= tree_1 + (frequency_d2(30 downto 0) & '0');
tree_000 <= tree_00;
tree_001 <= tree_00 + frequency_d3;
tree_010 <= tree_01;
tree_011 <= tree_01 + frequency_d3;
tree_100 <= tree_10;
tree_101 <= tree_10 + frequency_d3;
tree_110 <= tree_11;
tree_111 <= tree_11 + frequency_d3;
w_0 <= tree_000;
w_1 <= tree_001;
w_2 <= tree_010;
w_3 <= tree_011;
w_4 <= tree_100;
w_5 <= tree_101;
w_6 <= tree_110;
w_7 <= tree_111;
lo_q_0 <= sin_array(to_integer(w_0(31 downto 32-sin_bits)));
lo_q_1 <= sin_array(to_integer(w_1(31 downto 32-sin_bits)));
lo_q_2 <= sin_array(to_integer(w_2(31 downto 32-sin_bits)));
lo_q_3 <= sin_array(to_integer(w_3(31 downto 32-sin_bits)));
lo_q_4 <= sin_array(to_integer(w_4(31 downto 32-sin_bits)));
lo_q_5 <= sin_array(to_integer(w_5(31 downto 32-sin_bits)));
lo_q_6 <= sin_array(to_integer(w_6(31 downto 32-sin_bits)));
lo_q_7 <= sin_array(to_integer(w_7(31 downto 32-sin_bits)));
lo_i_0 <= cos_array(to_integer(w_0(31 downto 32-sin_bits)));
lo_i_1 <= cos_array(to_integer(w_1(31 downto 32-sin_bits)));
lo_i_2 <= cos_array(to_integer(w_2(31 downto 32-sin_bits)));
lo_i_3 <= cos_array(to_integer(w_3(31 downto 32-sin_bits)));
lo_i_4 <= cos_array(to_integer(w_4(31 downto 32-sin_bits)));
lo_i_5 <= cos_array(to_integer(w_5(31 downto 32-sin_bits)));
lo_i_6 <= cos_array(to_integer(w_6(31 downto 32-sin_bits)));
lo_i_7 <= cos_array(to_integer(w_7(31 downto 32-sin_bits)));
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity nco is
generic(
width : integer := 32
);
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto 0);
lo_i_0 : out std_logic_vector(width - 1 downto 0);
lo_i_1 : out std_logic_vector(width - 1 downto 0);
lo_i_2 : out std_logic_vector(width - 1 downto 0);
lo_i_3 : out std_logic_vector(width - 1 downto 0);
lo_i_4 : out std_logic_vector(width - 1 downto 0);
lo_i_5 : out std_logic_vector(width - 1 downto 0);
lo_i_6 : out std_logic_vector(width - 1 downto 0);
lo_i_7 : out std_logic_vector(width - 1 downto 0);
lo_q_0 : out std_logic_vector(width - 1 downto 0);
lo_q_1 : out std_logic_vector(width - 1 downto 0);
lo_q_2 : out std_logic_vector(width - 1 downto 0);
lo_q_3 : out std_logic_vector(width - 1 downto 0);
lo_q_4 : out std_logic_vector(width - 1 downto 0);
lo_q_5 : out std_logic_vector(width - 1 downto 0);
lo_q_6 : out std_logic_vector(width - 1 downto 0);
lo_q_7 : out std_logic_vector(width - 1 downto 0)
);
end entity nco;
architecture rtl of nco is
constant sin_bits : integer := width;
constant sin_scale : real := 2.0**real(sin_bits);
constant sin_output_scale : real := ((2.0**real(sin_bits-1))-1.0) / sqrt(2.0);
constant sin_input_scale : real := ((2.0 * math_pi)/sin_scale);
type sin_array_type is array (0 to (2**sin_bits)-1) of std_logic_vector(sin_bits-1 downto 0);
function initialise_sin_array return sin_array_type is
variable x : sin_array_type;
begin
for i in 0 to (2**sin_bits)-1 loop
x(i) := std_logic_vector(to_signed(-integer(round(sin_output_scale * sin(real(i) * sin_input_scale))), sin_bits));
end loop;
return x;
end function;
function initialise_cos_array return sin_array_type is
variable x : sin_array_type;
begin
for i in 0 to (2**sin_bits)-1 loop
x(i) := std_logic_vector(to_signed(integer(round(sin_output_scale * cos(real(i) * sin_input_scale))), sin_bits));
end loop;
return x;
end function;
constant sin_array : sin_array_type := initialise_sin_array;
constant cos_array : sin_array_type := initialise_cos_array;
signal w_0 : unsigned(31 downto 0);
signal w_1 : unsigned(31 downto 0);
signal w_2 : unsigned(31 downto 0);
signal w_3 : unsigned(31 downto 0);
signal w_4 : unsigned(31 downto 0);
signal w_5 : unsigned(31 downto 0);
signal w_6 : unsigned(31 downto 0);
signal w_7 : unsigned(31 downto 0);
signal frequency_d1 : unsigned(31 downto 0) := (others => '0');
signal frequency_d2 : unsigned(31 downto 0) := (others => '0');
signal frequency_d3 : unsigned(31 downto 0) := (others => '0');
signal accum : unsigned(31 downto 0) := (others => '0');
signal tree_0 : unsigned(31 downto 0) := (others => '0');
signal tree_1 : unsigned(31 downto 0) := (others => '0');
signal tree_00 : unsigned(31 downto 0) := (others => '0');
signal tree_01 : unsigned(31 downto 0) := (others => '0');
signal tree_10 : unsigned(31 downto 0) := (others => '0');
signal tree_11 : unsigned(31 downto 0) := (others => '0');
signal tree_000 : unsigned(31 downto 0) := (others => '0');
signal tree_001 : unsigned(31 downto 0) := (others => '0');
signal tree_010 : unsigned(31 downto 0) := (others => '0');
signal tree_011 : unsigned(31 downto 0) := (others => '0');
signal tree_100 : unsigned(31 downto 0) := (others => '0');
signal tree_101 : unsigned(31 downto 0) := (others => '0');
signal tree_110 : unsigned(31 downto 0) := (others => '0');
signal tree_111 : unsigned(31 downto 0) := (others => '0');
begin
process
begin
wait until rising_edge(clk);
frequency_d1 <= unsigned(frequency);
frequency_d2 <= frequency_d1;
frequency_d3 <= frequency_d2;
accum <= accum + (unsigned(frequency(28 downto 0)) & "000");
tree_0 <= accum;
tree_1 <= accum + (frequency_d1(29 downto 0) & "00");
tree_00 <= tree_0;
tree_01 <= tree_0 + (frequency_d2(30 downto 0) & '0');
tree_10 <= tree_1;
tree_11 <= tree_1 + (frequency_d2(30 downto 0) & '0');
tree_000 <= tree_00;
tree_001 <= tree_00 + frequency_d3;
tree_010 <= tree_01;
tree_011 <= tree_01 + frequency_d3;
tree_100 <= tree_10;
tree_101 <= tree_10 + frequency_d3;
tree_110 <= tree_11;
tree_111 <= tree_11 + frequency_d3;
w_0 <= tree_000;
w_1 <= tree_001;
w_2 <= tree_010;
w_3 <= tree_011;
w_4 <= tree_100;
w_5 <= tree_101;
w_6 <= tree_110;
w_7 <= tree_111;
lo_q_0 <= sin_array(to_integer(w_0(31 downto 32-sin_bits)));
lo_q_1 <= sin_array(to_integer(w_1(31 downto 32-sin_bits)));
lo_q_2 <= sin_array(to_integer(w_2(31 downto 32-sin_bits)));
lo_q_3 <= sin_array(to_integer(w_3(31 downto 32-sin_bits)));
lo_q_4 <= sin_array(to_integer(w_4(31 downto 32-sin_bits)));
lo_q_5 <= sin_array(to_integer(w_5(31 downto 32-sin_bits)));
lo_q_6 <= sin_array(to_integer(w_6(31 downto 32-sin_bits)));
lo_q_7 <= sin_array(to_integer(w_7(31 downto 32-sin_bits)));
lo_i_0 <= cos_array(to_integer(w_0(31 downto 32-sin_bits)));
lo_i_1 <= cos_array(to_integer(w_1(31 downto 32-sin_bits)));
lo_i_2 <= cos_array(to_integer(w_2(31 downto 32-sin_bits)));
lo_i_3 <= cos_array(to_integer(w_3(31 downto 32-sin_bits)));
lo_i_4 <= cos_array(to_integer(w_4(31 downto 32-sin_bits)));
lo_i_5 <= cos_array(to_integer(w_5(31 downto 32-sin_bits)));
lo_i_6 <= cos_array(to_integer(w_6(31 downto 32-sin_bits)));
lo_i_7 <= cos_array(to_integer(w_7(31 downto 32-sin_bits)));
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity muxb_201 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end muxb_201;
architecture augh of muxb_201 is
begin
out_data <= in_data0 when in_sel = '0' else in_data1;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity muxb_201 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end muxb_201;
architecture augh of muxb_201 is
begin
out_data <= in_data0 when in_sel = '0' else in_data1;
end architecture;
|
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** DP_FABS.VHD ***
--*** ***
--*** Function: Single Precision Absolute Value ***
--*** ***
--*** abs(x) ***
--*** ***
--*** Created 12/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fabs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END dp_fabs;
ARCHITECTURE rtl OF dp_fabs IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= '0';
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 11 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(11));
expmax <= expmaxchk(11);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 52 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(52));
mannonzero <= manzerochk(52);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** DP_FABS.VHD ***
--*** ***
--*** Function: Single Precision Absolute Value ***
--*** ***
--*** abs(x) ***
--*** ***
--*** Created 12/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fabs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END dp_fabs;
ARCHITECTURE rtl OF dp_fabs IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= '0';
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 11 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(11));
expmax <= expmaxchk(11);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 52 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(52));
mannonzero <= manzerochk(52);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** DP_FABS.VHD ***
--*** ***
--*** Function: Single Precision Absolute Value ***
--*** ***
--*** abs(x) ***
--*** ***
--*** Created 12/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fabs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END dp_fabs;
ARCHITECTURE rtl OF dp_fabs IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= '0';
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 11 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(11));
expmax <= expmaxchk(11);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 52 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(52));
mannonzero <= manzerochk(52);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** DP_FABS.VHD ***
--*** ***
--*** Function: Single Precision Absolute Value ***
--*** ***
--*** abs(x) ***
--*** ***
--*** Created 12/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fabs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END dp_fabs;
ARCHITECTURE rtl OF dp_fabs IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= '0';
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 11 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(11));
expmax <= expmaxchk(11);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 52 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(52));
mannonzero <= manzerochk(52);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** DP_FABS.VHD ***
--*** ***
--*** Function: Single Precision Absolute Value ***
--*** ***
--*** abs(x) ***
--*** ***
--*** Created 12/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fabs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END dp_fabs;
ARCHITECTURE rtl OF dp_fabs IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= '0';
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 11 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(11));
expmax <= expmaxchk(11);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 52 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(52));
mannonzero <= manzerochk(52);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** DP_FABS.VHD ***
--*** ***
--*** Function: Single Precision Absolute Value ***
--*** ***
--*** abs(x) ***
--*** ***
--*** Created 12/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fabs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END dp_fabs;
ARCHITECTURE rtl OF dp_fabs IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= '0';
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 11 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(11));
expmax <= expmaxchk(11);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 52 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(52));
mannonzero <= manzerochk(52);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** DP_FABS.VHD ***
--*** ***
--*** Function: Single Precision Absolute Value ***
--*** ***
--*** abs(x) ***
--*** ***
--*** Created 12/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fabs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END dp_fabs;
ARCHITECTURE rtl OF dp_fabs IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= '0';
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 11 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(11));
expmax <= expmaxchk(11);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 52 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(52));
mannonzero <= manzerochk(52);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** DP_FABS.VHD ***
--*** ***
--*** Function: Single Precision Absolute Value ***
--*** ***
--*** abs(x) ***
--*** ***
--*** Created 12/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fabs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END dp_fabs;
ARCHITECTURE rtl OF dp_fabs IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= '0';
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 11 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(11));
expmax <= expmaxchk(11);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 52 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(52));
mannonzero <= manzerochk(52);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** DP_FABS.VHD ***
--*** ***
--*** Function: Single Precision Absolute Value ***
--*** ***
--*** abs(x) ***
--*** ***
--*** Created 12/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fabs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END dp_fabs;
ARCHITECTURE rtl OF dp_fabs IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= '0';
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 11 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(11));
expmax <= expmaxchk(11);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 52 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(52));
mannonzero <= manzerochk(52);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** DP_FABS.VHD ***
--*** ***
--*** Function: Single Precision Absolute Value ***
--*** ***
--*** abs(x) ***
--*** ***
--*** Created 12/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fabs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END dp_fabs;
ARCHITECTURE rtl OF dp_fabs IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= '0';
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 11 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(11));
expmax <= expmaxchk(11);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 52 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(52));
mannonzero <= manzerochk(52);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Polynomial_Evaluator
-- Module Name: Controller_Polynomial_Evaluator
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 3rd step in Goppa Code Decoding.
--
-- This circuit is the state machine to control both polynomial_evaluator_n and
-- polynomial_evaluator_n_v2. Because both circuits have similar behavioral on
-- how the registers are loaded, they can share the same state machine.
-- The difference is how each pipeline computes inside each, which does not matter
-- for state machine inner workings.
--
-- This state machine works by preparing the pipeline by loading the polynomial
-- coefficients and respective first values to be evaluated. Then it loads the
-- remaining evaluated values. When there are no more values to be evaluated,
-- it restarts loading the values to be evaluated and the remaining polynomial
-- coefficients.
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_polynomial_evaluator is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_load_x_values : in STD_LOGIC;
last_store_x_values : in STD_LOGIC;
limit_polynomial_degree : in STD_LOGIC;
pipeline_ready : in STD_LOGIC;
evaluation_data_in : out STD_LOGIC;
reg_write_enable_rst : out STD_LOGIC;
ctr_load_x_address_ce : out STD_LOGIC;
ctr_load_x_address_rst : out STD_LOGIC;
ctr_store_x_address_ce : out STD_LOGIC;
ctr_store_x_address_rst : out STD_LOGIC;
reg_first_values_ce : out STD_LOGIC;
reg_first_values_rst : out STD_LOGIC;
ctr_address_polynomial_ce : out STD_LOGIC;
ctr_address_polynomial_rst : out STD_LOGIC;
reg_x_rst_rst : out STD_LOGIC;
shift_polynomial_ce_ce : out STD_LOGIC;
shift_polynomial_ce_rst : out STD_LOGIC;
last_coefficients : out STD_LOGIC;
evaluation_finalized : out STD_LOGIC
);
end controller_polynomial_evaluator;
architecture Behavioral of controller_polynomial_evaluator is
type State is (reset, load_counter, load_first_polynomial_coefficient, reset_first_polynomial_coefficient, prepare_load_polynomial_coefficient, load_polynomial_coefficient, reset_polynomial_coefficient, load_x_write_x, last_load_x_write_x, write_x, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, last_load_x_values, last_store_x_values, limit_polynomial_degree, pipeline_ready)
begin
case (actual_state) is
when reset =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '1';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '1';
reg_x_rst_rst <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '1';
last_coefficients <= '0';
evaluation_finalized <= '0';
when load_counter =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '1';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
when load_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
elsif(limit_polynomial_degree = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '1';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
end if;
when reset_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '1';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '1';
evaluation_finalized <= '0';
end if;
when prepare_load_polynomial_coefficient =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '1';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '1';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
when load_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
elsif(limit_polynomial_degree = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '1';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
end if;
when reset_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '1';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '1';
evaluation_finalized <= '0';
end if;
when load_x_write_x =>
if(last_load_x_values = '1' and limit_polynomial_degree = '0') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
end if;
when last_load_x_write_x =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
when write_x =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
when final =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '1';
when others =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
end case;
end process;
NewState: process (actual_state, last_load_x_values, last_store_x_values, limit_polynomial_degree, pipeline_ready)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= load_first_polynomial_coefficient;
when load_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= load_x_write_x;
elsif(limit_polynomial_degree = '1') then
next_state <= reset_first_polynomial_coefficient;
else
next_state <= load_first_polynomial_coefficient;
end if;
when reset_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= load_x_write_x;
else
next_state <= reset_first_polynomial_coefficient;
end if;
when prepare_load_polynomial_coefficient =>
next_state <= load_polynomial_coefficient;
when load_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= load_x_write_x;
elsif(limit_polynomial_degree = '1') then
next_state <= reset_polynomial_coefficient;
else
next_state <= load_polynomial_coefficient;
end if;
when reset_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= load_x_write_x;
else
next_state <= reset_polynomial_coefficient;
end if;
when load_x_write_x =>
if(last_load_x_values = '1') then
if(limit_polynomial_degree = '1') then
next_state <= last_load_x_write_x;
else
next_state <= prepare_load_polynomial_coefficient;
end if;
else
next_state <= load_x_write_x;
end if;
when last_load_x_write_x =>
next_state <= write_x;
when write_x =>
if(last_store_x_values = '1') then
next_state <= final;
else
next_state <= write_x;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use work.iface.all;
use work.amba.all;
entity ddm is
port (
rst : in std_logic;
clk : in clk_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ddmi : in ddm_in_type;
ddmo : out ddm_out_type;
irq : out std_logic
);
end;
architecture rtl of ddm is
type ddmregs is record
-- ***********************
-- memory mapped registers
-- bit 0 of 0x80000200
audioenreq : std_logic; -- audio function enabled active
-- bit 1 of 0x80000200
recorden : std_logic; -- audio record '1' or playback '1'
-- bit 2 of 0x80000200
loopen : std_logic; -- enable loop mode;
-- bit 3 of 0x80000200
irqen : std_logic; -- enable interrupt
-- bit 4 of 0x80000200
irq : std_logic; -- irq request
-- 32 bit at 0x80000204
startaddr : std_logic_vector(31 downto 0); -- dma transfer start address
-- 32 bit at 0x80000208
stopaddr : std_logic_vector(31 downto 0); -- dma transfer stop address
-- 14 bit at 0x8000020c
scalerup : std_logic_vector(13 downto 0); -- scaler update register value
-- masterclock / (sampling frequenz * 20*2)
-- lowest 8 bit of 0x80000210
display : std_logic_vector(7 downto 0); -- value to be displayed on the 2
-- digit display
-- bit 9 of 0x80000210
dispen : std_logic; -- enable display on board
-- bit 0-4 of 0x80000214
button0 : std_logic; -- status of the buttons
button1 : std_logic;
button2 : std_logic;
button3 : std_logic;
-- 0x80000218
memoryadr : std_logic_vector(31 downto 0); -- actual dma address /read only
-- memory mapped registers end
-- ***************************
-- internal registers
audioen : std_logic;
dmatransfreq : std_logic;
audiobuffer : std_logic_vector(31 downto 0); -- audio data buffer for
-- memory transfers
shiftcounter : std_logic_vector(4 downto 0); -- counter for 20 bit shiftregister
audioshifter : std_logic_vector(19 downto 0); -- serial shift register for
-- audio a/d and d/a converter
shifttick : std_logic; -- tick from serial 5 bit (from 20 bit shift
-- register) counter
readaudio_clk: std_logic;
shiftstop : std_logic; -- set for the 12 bit not shifted
lrsel : std_logic; -- left/right output selector
masterclk : std_logic;
sclk : std_logic;
audioout : std_logic; -- 1 bit audio output to d/a converter
digit0 : std_logic_vector(6 downto 0);
digit1 : std_logic_vector(6 downto 0);
-- amba status registers
busact : std_logic;
busown : std_logic;
busgrant : std_logic;
busown2cyc : std_logic;
end record;
type timer is record
scaler : std_logic_vector(13 downto 0);
masterclk : std_logic;
sclkscaler : std_logic_vector(1 downto 0); -- shiftclk generator
sclk : std_logic; -- shiftclk output
sclk_old : std_logic; -- old status of shiftclk for signal
-- change recognition
end record;
signal r,rin : ddmregs;
signal timerout,timerin : timer;
begin
ddmtop : process(rst,r, apbi, ahbi, ddmi, timerout)
variable rdata : std_logic_vector(31 downto 0);
variable tmp: ddmregs;
variable regaddr : std_logic_vector(4 downto 0):="10000";
-- amba ahb variables
variable haddr : std_logic_vector(31 downto 0); -- address bus
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_logic; -- read/write
variable hsize : std_logic_vector(2 downto 0); -- transfer size
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable hwdata : std_logic_vector(31 downto 0); -- write data
variable hbusreq : std_logic; -- bus request
begin
-- init
tmp:=r;
htrans := HTRANS_IDLE; -- do nothing if granted without request
hbusreq := '0';
-- read/write memory mapped registers witch amba apb bus
rdata := (others => '0'); -- init
case apbi.paddr(4 downto 2) is
when "000" =>
rdata(0) := r.audioen or r.audioenreq;
rdata(1) := r.recorden;
rdata(2) := r.loopen;
rdata(3) := r.irqen;
rdata(4) := r.irq;
when "001" =>
rdata := r.startaddr;
when "010" =>
rdata := r.stopaddr;
when "011" =>
rdata(13 downto 0) := r.scalerup;
when "100" =>
rdata(7 downto 0) := r.display;
rdata(8) := r.dispen;
when "101" =>
rdata(0) := r.button0;
rdata(1) := r.button1;
rdata(2) := r.button2;
rdata(3) := r.button3;
when "110" =>
rdata := r.memoryadr;
when others => null;
end case;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
tmp.audioenreq := apbi.pwdata(0);
tmp.recorden := apbi.pwdata(1);
tmp.loopen := apbi.pwdata(2);
tmp.irqen := apbi.pwdata(3);
if apbi.pwdata(4)='0' then -- allow only interrupt reset
tmp.irq := '0';
end if;
if tmp.audioenreq = '1' and r.audioenreq = '0' then -- init audio transaction
tmp.memoryadr := r.startaddr;
if tmp.recorden = '0' then -- load first audio data when play back
tmp.dmatransfreq := '1';
end if;
end if;
when "001" =>
tmp.startaddr := apbi.pwdata;
when "010" =>
tmp.stopaddr := apbi.pwdata;
when "011" =>
tmp.scalerup := apbi.pwdata(13 downto 0);
when "100" =>
tmp.display := apbi.pwdata(7 downto 0);
tmp.dispen := apbi.pwdata(8);
when others => null;
end case;
end if;
-- update buttonreg
tmp.button0 := ddmi.button0;
tmp.button1 := ddmi.button1;
tmp.button2 := ddmi.button2;
tmp.button3 := ddmi.button3;
-- decode display input to digits
case r.display(3 downto 0) is
when "0000" =>
tmp.digit0 := "1110111";
when "0001" =>
tmp.digit0 := "0100100";
when "0010" =>
tmp.digit0 := "1011101";
when "0011" =>
tmp.digit0 := "1101101";
when "0100" =>
tmp.digit0 := "0101110";
when "0101" =>
tmp.digit0 := "1101011";
when "0110" =>
tmp.digit0 := "1111011";
when "0111" =>
tmp.digit0 := "0100111";
when "1000" =>
tmp.digit0 := "1111111";
when "1001" =>
tmp.digit0 := "1101111";
when "1010" =>
tmp.digit0 := "0111111";
when "1011" =>
tmp.digit0 := "1111010";
when "1100" =>
tmp.digit0 := "1010011";
when "1101" =>
tmp.digit0 := "1111100";
when "1110" =>
tmp.digit0 := "1011011";
when "1111" =>
tmp.digit0 := "0011011";
when others => null;
end case;
case r.display(7 downto 4) is
when "0000" =>
tmp.digit1 := "1110111";
when "0001" =>
tmp.digit1 := "0100100";
when "0010" =>
tmp.digit1 := "1011101";
when "0011" =>
tmp.digit1 := "1101101";
when "0100" =>
tmp.digit1 := "0101110";
when "0101" =>
tmp.digit1 := "1101011";
when "0110" =>
tmp.digit1 := "1111011";
when "0111" =>
tmp.digit1 := "0100111";
when "1000" =>
tmp.digit1 := "1111111";
when "1001" =>
tmp.digit1 := "1101111";
when "1010" =>
tmp.digit1 := "0111111";
when "1011" =>
tmp.digit1 := "1111010";
when "1100" =>
tmp.digit1 := "1010011";
when "1101" =>
tmp.digit1 := "1111100";
when "1110" =>
tmp.digit1 := "1011011";
when "1111" =>
tmp.digit1 := "0011011";
when others => null;
end case;
-- audio in/out
tmp.masterclk:=timerout.masterclk;
tmp.sclk :=timerout.sclk;
-- audio shifter out/in
if (timerout.sclk='1') and (timerout.sclk_old='0') then
tmp.shiftcounter := tmp.shiftcounter+1;
tmp.shifttick := r.shiftcounter(4) and not tmp.shiftcounter(4);
if tmp.shiftcounter="10100" then -- stop shifting after 20 bit
tmp.shiftstop :='1';
end if;
-- audio shifregister to buffer update and vice versa
if (tmp.shifttick ='1') and (r.shifttick= '0') then -- all 32 data bits
tmp.lrsel:=not r.lrsel; -- change left/right channel
if tmp.lrsel = '1' then -- only transmit data to or from memory when audio is on for one phase
if r.audioen='1' then
if r.recorden = '1' then -- if record shiftreg to buffer
tmp.audiobuffer(19 downto 0) := tmp.audioshifter; -- save record
-- data from
-- shiftregister
-- in buffer
tmp.dmatransfreq := '1'; -- start dma transfer action for
-- recording
else
tmp.audioshifter := r.audiobuffer(19 downto 0); -- else load new audio data
end if;
end if;
tmp.audioen:=tmp.audioenreq; -- enable audio if requested
if tmp.audioen='1' and tmp.recorden='0' then
tmp.dmatransfreq:='1'; -- load data for playback from memory
end if;
else
tmp.shiftstop:='0'; -- start shifting
end if;
end if;
if r.audioen ='1' then
if r.recorden = '1' then
if tmp.shiftstop='0' then
tmp.readaudio_clk:='1';
else
tmp.audioout := '0';
end if;
else
if tmp.shiftstop='0' then
tmp.audioout := tmp.audioshifter(19);
tmp.audioshifter := tmp.audioshifter(18 downto 0) & '0';
else
tmp.audioout:='0';
end if;
end if;
else
tmp.audioout:='0';
tmp.audioshifter := (others => '0');
end if;
end if;
-- audio data must be read one clk later as mclk is generated
if r.readaudio_clk='1' then
tmp.readaudio_clk:='0';
tmp.audioshifter := tmp.audioshifter(18 downto 0) & ddmi.audioin;
tmp.audioout:=ddmi.audioin;
end if;
-- audio shifregister to buffer update and vice versa
-- dma/amba ahb activity (master)
-- start ahb action
if r.dmatransfreq = '1' then -- request bus for action
hbusreq := '1';
end if;
-- check for bus ownership
tmp.busgrant := ahbi.hgrant;
if tmp.busgrant = '1' and r.dmatransfreq = '1' then
tmp.busact := '1'; -- bus granted and requested
else
tmp.busact := '0'; -- bus granted but not requested
end if;
if (tmp.busact = '1') and (ahbi.hready= '1') then -- bus active
tmp.busown:='1'; -- bus owner at next clock
tmp.dmatransfreq := '0';
end if;
-- control and address cycle of ahb transfer
if r.busown='1' then
haddr := r.memoryadr;
hsize := HSIZE_WORD;
hburst := HBURST_SINGLE;
htrans := HTRANS_NONSEQ;
if r.recorden = '1'then
hwrite := '1';
else
hwrite := '0';
end if;
if ahbi.hready='1' then -- check for data cycle
tmp.busown:='0';
tmp.busown2cyc:='1';
end if;
end if;
-- data cycle of ahb transfer
if r.busown2cyc='1' then
if r.recorden = '1'then
hwdata:=r.audiobuffer;
end if;
if ahbi.hready='1' then
tmp.busown:='0';
tmp.busown2cyc:='0';
tmp.memoryadr := r.memoryadr+4; -- next memory address
if r.recorden='0' then
tmp.audiobuffer := ahbi.hrdata;
end if;
end if;
end if;
-- check for audio action end
if tmp.memoryadr = r.stopaddr then -- stop address reached ?
if r.loopen = '1' then -- if loopmode activated
tmp.memoryadr := r.startaddr; -- loop mode; begin again at start
else
tmp.audioen := '0'; -- audio task finished , in output
-- mode last sample gets lost
tmp.audioenreq := '0';
tmp.audiobuffer:= (others => '0');
end if;
tmp.irq := r.irqen; -- request interrupt when enabled
end if;
-- reset operation of ddm-module
if rst = '0' then
tmp.audiobuffer := (others => '0');
tmp.audioshifter := (others => '0');
tmp.startaddr := (others => '0');
tmp.stopaddr := (others => '0');
tmp.memoryadr := (others => '0');
tmp.scalerup := "00000000000001";
tmp.shiftcounter := (others => '0');
tmp.shiftstop := '0';
tmp.audioen := '0';
tmp.recorden := '0';
tmp.irqen := '0';
tmp.irq := '0';
tmp.display := (others => '0');
tmp.dmatransfreq := '0';
tmp.lrsel := '0';
tmp.dispen := '0';
tmp.busown := '0';
tmp.busown2cyc := '0';
tmp.busact := '0';
tmp.readaudio_clk:='0';
end if;
-- update registers
rin <= tmp;
-- output from ddm to ambabus and outworld
ddmo.digit0 <= r.digit0;
ddmo.digit1 <= r.digit1;
ddmo.audioout <= r.audioout;
ddmo.lr_out <= r.lrsel;
ddmo.shift_clk <= not r.sclk;
ddmo.dispen <= r.dispen;
ddmo.mclk <= r.masterclk;
irq <= r.irq;
apbo.prdata <= rdata;
ahbo.haddr <= haddr;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq;
ahbo.hwdata <= hwdata;
ahbo.hlock <= '0';
ahbo.hwrite <= hwrite;
ahbo.hsize <= hsize;
ahbo.hburst <= hburst;
ahbo.hprot <= (others => '0');
end process;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
timerout <= timerin;
end if;
end process;
timerpr : process(timerout, rst)
variable scaler : std_logic_vector(13 downto 0);
variable masterclk : std_logic;
variable tick : std_logic;
variable rscaler : std_logic_vector(1 downto 0);
variable sclk: std_logic;
-- scaler update
begin
if rst = '1' then
sclk:= timerout.sclk;
scaler := timerout.scaler-1;
masterclk := timerout.masterclk;
tick := scaler(13) and not timerout.scaler(13);
rscaler := timerout.sclkscaler;
if tick = '1' then
scaler := r.scalerup;
masterclk := not timerout.masterclk;
rscaler := rscaler+1; -- generating shiftclk
if ((not rscaler(0)) and (not rscaler(1)))='1' then
sclk := not sclk;
end if;
end if;
-- audio shiftclk generation
timerin.sclkscaler <= rscaler;
timerin.sclk_old <= timerout.sclk;
timerin.scaler <= scaler;
timerin.masterclk <= masterclk;
timerin.sclk <= sclk;
else
timerin.sclkscaler <= "00"; --reset
timerin.sclk_old <= '0';
timerin.sclk <= '0';
timerin.scaler <= "00000000000001";
timerin.masterclk <= '0';
end if;
end process;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use work.iface.all;
use work.amba.all;
entity ddm is
port (
rst : in std_logic;
clk : in clk_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ddmi : in ddm_in_type;
ddmo : out ddm_out_type;
irq : out std_logic
);
end;
architecture rtl of ddm is
type ddmregs is record
-- ***********************
-- memory mapped registers
-- bit 0 of 0x80000200
audioenreq : std_logic; -- audio function enabled active
-- bit 1 of 0x80000200
recorden : std_logic; -- audio record '1' or playback '1'
-- bit 2 of 0x80000200
loopen : std_logic; -- enable loop mode;
-- bit 3 of 0x80000200
irqen : std_logic; -- enable interrupt
-- bit 4 of 0x80000200
irq : std_logic; -- irq request
-- 32 bit at 0x80000204
startaddr : std_logic_vector(31 downto 0); -- dma transfer start address
-- 32 bit at 0x80000208
stopaddr : std_logic_vector(31 downto 0); -- dma transfer stop address
-- 14 bit at 0x8000020c
scalerup : std_logic_vector(13 downto 0); -- scaler update register value
-- masterclock / (sampling frequenz * 20*2)
-- lowest 8 bit of 0x80000210
display : std_logic_vector(7 downto 0); -- value to be displayed on the 2
-- digit display
-- bit 9 of 0x80000210
dispen : std_logic; -- enable display on board
-- bit 0-4 of 0x80000214
button0 : std_logic; -- status of the buttons
button1 : std_logic;
button2 : std_logic;
button3 : std_logic;
-- 0x80000218
memoryadr : std_logic_vector(31 downto 0); -- actual dma address /read only
-- memory mapped registers end
-- ***************************
-- internal registers
audioen : std_logic;
dmatransfreq : std_logic;
audiobuffer : std_logic_vector(31 downto 0); -- audio data buffer for
-- memory transfers
shiftcounter : std_logic_vector(4 downto 0); -- counter for 20 bit shiftregister
audioshifter : std_logic_vector(19 downto 0); -- serial shift register for
-- audio a/d and d/a converter
shifttick : std_logic; -- tick from serial 5 bit (from 20 bit shift
-- register) counter
readaudio_clk: std_logic;
shiftstop : std_logic; -- set for the 12 bit not shifted
lrsel : std_logic; -- left/right output selector
masterclk : std_logic;
sclk : std_logic;
audioout : std_logic; -- 1 bit audio output to d/a converter
digit0 : std_logic_vector(6 downto 0);
digit1 : std_logic_vector(6 downto 0);
-- amba status registers
busact : std_logic;
busown : std_logic;
busgrant : std_logic;
busown2cyc : std_logic;
end record;
type timer is record
scaler : std_logic_vector(13 downto 0);
masterclk : std_logic;
sclkscaler : std_logic_vector(1 downto 0); -- shiftclk generator
sclk : std_logic; -- shiftclk output
sclk_old : std_logic; -- old status of shiftclk for signal
-- change recognition
end record;
signal r,rin : ddmregs;
signal timerout,timerin : timer;
begin
ddmtop : process(rst,r, apbi, ahbi, ddmi, timerout)
variable rdata : std_logic_vector(31 downto 0);
variable tmp: ddmregs;
variable regaddr : std_logic_vector(4 downto 0):="10000";
-- amba ahb variables
variable haddr : std_logic_vector(31 downto 0); -- address bus
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_logic; -- read/write
variable hsize : std_logic_vector(2 downto 0); -- transfer size
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable hwdata : std_logic_vector(31 downto 0); -- write data
variable hbusreq : std_logic; -- bus request
begin
-- init
tmp:=r;
htrans := HTRANS_IDLE; -- do nothing if granted without request
hbusreq := '0';
-- read/write memory mapped registers witch amba apb bus
rdata := (others => '0'); -- init
case apbi.paddr(4 downto 2) is
when "000" =>
rdata(0) := r.audioen or r.audioenreq;
rdata(1) := r.recorden;
rdata(2) := r.loopen;
rdata(3) := r.irqen;
rdata(4) := r.irq;
when "001" =>
rdata := r.startaddr;
when "010" =>
rdata := r.stopaddr;
when "011" =>
rdata(13 downto 0) := r.scalerup;
when "100" =>
rdata(7 downto 0) := r.display;
rdata(8) := r.dispen;
when "101" =>
rdata(0) := r.button0;
rdata(1) := r.button1;
rdata(2) := r.button2;
rdata(3) := r.button3;
when "110" =>
rdata := r.memoryadr;
when others => null;
end case;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
tmp.audioenreq := apbi.pwdata(0);
tmp.recorden := apbi.pwdata(1);
tmp.loopen := apbi.pwdata(2);
tmp.irqen := apbi.pwdata(3);
if apbi.pwdata(4)='0' then -- allow only interrupt reset
tmp.irq := '0';
end if;
if tmp.audioenreq = '1' and r.audioenreq = '0' then -- init audio transaction
tmp.memoryadr := r.startaddr;
if tmp.recorden = '0' then -- load first audio data when play back
tmp.dmatransfreq := '1';
end if;
end if;
when "001" =>
tmp.startaddr := apbi.pwdata;
when "010" =>
tmp.stopaddr := apbi.pwdata;
when "011" =>
tmp.scalerup := apbi.pwdata(13 downto 0);
when "100" =>
tmp.display := apbi.pwdata(7 downto 0);
tmp.dispen := apbi.pwdata(8);
when others => null;
end case;
end if;
-- update buttonreg
tmp.button0 := ddmi.button0;
tmp.button1 := ddmi.button1;
tmp.button2 := ddmi.button2;
tmp.button3 := ddmi.button3;
-- decode display input to digits
case r.display(3 downto 0) is
when "0000" =>
tmp.digit0 := "1110111";
when "0001" =>
tmp.digit0 := "0100100";
when "0010" =>
tmp.digit0 := "1011101";
when "0011" =>
tmp.digit0 := "1101101";
when "0100" =>
tmp.digit0 := "0101110";
when "0101" =>
tmp.digit0 := "1101011";
when "0110" =>
tmp.digit0 := "1111011";
when "0111" =>
tmp.digit0 := "0100111";
when "1000" =>
tmp.digit0 := "1111111";
when "1001" =>
tmp.digit0 := "1101111";
when "1010" =>
tmp.digit0 := "0111111";
when "1011" =>
tmp.digit0 := "1111010";
when "1100" =>
tmp.digit0 := "1010011";
when "1101" =>
tmp.digit0 := "1111100";
when "1110" =>
tmp.digit0 := "1011011";
when "1111" =>
tmp.digit0 := "0011011";
when others => null;
end case;
case r.display(7 downto 4) is
when "0000" =>
tmp.digit1 := "1110111";
when "0001" =>
tmp.digit1 := "0100100";
when "0010" =>
tmp.digit1 := "1011101";
when "0011" =>
tmp.digit1 := "1101101";
when "0100" =>
tmp.digit1 := "0101110";
when "0101" =>
tmp.digit1 := "1101011";
when "0110" =>
tmp.digit1 := "1111011";
when "0111" =>
tmp.digit1 := "0100111";
when "1000" =>
tmp.digit1 := "1111111";
when "1001" =>
tmp.digit1 := "1101111";
when "1010" =>
tmp.digit1 := "0111111";
when "1011" =>
tmp.digit1 := "1111010";
when "1100" =>
tmp.digit1 := "1010011";
when "1101" =>
tmp.digit1 := "1111100";
when "1110" =>
tmp.digit1 := "1011011";
when "1111" =>
tmp.digit1 := "0011011";
when others => null;
end case;
-- audio in/out
tmp.masterclk:=timerout.masterclk;
tmp.sclk :=timerout.sclk;
-- audio shifter out/in
if (timerout.sclk='1') and (timerout.sclk_old='0') then
tmp.shiftcounter := tmp.shiftcounter+1;
tmp.shifttick := r.shiftcounter(4) and not tmp.shiftcounter(4);
if tmp.shiftcounter="10100" then -- stop shifting after 20 bit
tmp.shiftstop :='1';
end if;
-- audio shifregister to buffer update and vice versa
if (tmp.shifttick ='1') and (r.shifttick= '0') then -- all 32 data bits
tmp.lrsel:=not r.lrsel; -- change left/right channel
if tmp.lrsel = '1' then -- only transmit data to or from memory when audio is on for one phase
if r.audioen='1' then
if r.recorden = '1' then -- if record shiftreg to buffer
tmp.audiobuffer(19 downto 0) := tmp.audioshifter; -- save record
-- data from
-- shiftregister
-- in buffer
tmp.dmatransfreq := '1'; -- start dma transfer action for
-- recording
else
tmp.audioshifter := r.audiobuffer(19 downto 0); -- else load new audio data
end if;
end if;
tmp.audioen:=tmp.audioenreq; -- enable audio if requested
if tmp.audioen='1' and tmp.recorden='0' then
tmp.dmatransfreq:='1'; -- load data for playback from memory
end if;
else
tmp.shiftstop:='0'; -- start shifting
end if;
end if;
if r.audioen ='1' then
if r.recorden = '1' then
if tmp.shiftstop='0' then
tmp.readaudio_clk:='1';
else
tmp.audioout := '0';
end if;
else
if tmp.shiftstop='0' then
tmp.audioout := tmp.audioshifter(19);
tmp.audioshifter := tmp.audioshifter(18 downto 0) & '0';
else
tmp.audioout:='0';
end if;
end if;
else
tmp.audioout:='0';
tmp.audioshifter := (others => '0');
end if;
end if;
-- audio data must be read one clk later as mclk is generated
if r.readaudio_clk='1' then
tmp.readaudio_clk:='0';
tmp.audioshifter := tmp.audioshifter(18 downto 0) & ddmi.audioin;
tmp.audioout:=ddmi.audioin;
end if;
-- audio shifregister to buffer update and vice versa
-- dma/amba ahb activity (master)
-- start ahb action
if r.dmatransfreq = '1' then -- request bus for action
hbusreq := '1';
end if;
-- check for bus ownership
tmp.busgrant := ahbi.hgrant;
if tmp.busgrant = '1' and r.dmatransfreq = '1' then
tmp.busact := '1'; -- bus granted and requested
else
tmp.busact := '0'; -- bus granted but not requested
end if;
if (tmp.busact = '1') and (ahbi.hready= '1') then -- bus active
tmp.busown:='1'; -- bus owner at next clock
tmp.dmatransfreq := '0';
end if;
-- control and address cycle of ahb transfer
if r.busown='1' then
haddr := r.memoryadr;
hsize := HSIZE_WORD;
hburst := HBURST_SINGLE;
htrans := HTRANS_NONSEQ;
if r.recorden = '1'then
hwrite := '1';
else
hwrite := '0';
end if;
if ahbi.hready='1' then -- check for data cycle
tmp.busown:='0';
tmp.busown2cyc:='1';
end if;
end if;
-- data cycle of ahb transfer
if r.busown2cyc='1' then
if r.recorden = '1'then
hwdata:=r.audiobuffer;
end if;
if ahbi.hready='1' then
tmp.busown:='0';
tmp.busown2cyc:='0';
tmp.memoryadr := r.memoryadr+4; -- next memory address
if r.recorden='0' then
tmp.audiobuffer := ahbi.hrdata;
end if;
end if;
end if;
-- check for audio action end
if tmp.memoryadr = r.stopaddr then -- stop address reached ?
if r.loopen = '1' then -- if loopmode activated
tmp.memoryadr := r.startaddr; -- loop mode; begin again at start
else
tmp.audioen := '0'; -- audio task finished , in output
-- mode last sample gets lost
tmp.audioenreq := '0';
tmp.audiobuffer:= (others => '0');
end if;
tmp.irq := r.irqen; -- request interrupt when enabled
end if;
-- reset operation of ddm-module
if rst = '0' then
tmp.audiobuffer := (others => '0');
tmp.audioshifter := (others => '0');
tmp.startaddr := (others => '0');
tmp.stopaddr := (others => '0');
tmp.memoryadr := (others => '0');
tmp.scalerup := "00000000000001";
tmp.shiftcounter := (others => '0');
tmp.shiftstop := '0';
tmp.audioen := '0';
tmp.recorden := '0';
tmp.irqen := '0';
tmp.irq := '0';
tmp.display := (others => '0');
tmp.dmatransfreq := '0';
tmp.lrsel := '0';
tmp.dispen := '0';
tmp.busown := '0';
tmp.busown2cyc := '0';
tmp.busact := '0';
tmp.readaudio_clk:='0';
end if;
-- update registers
rin <= tmp;
-- output from ddm to ambabus and outworld
ddmo.digit0 <= r.digit0;
ddmo.digit1 <= r.digit1;
ddmo.audioout <= r.audioout;
ddmo.lr_out <= r.lrsel;
ddmo.shift_clk <= not r.sclk;
ddmo.dispen <= r.dispen;
ddmo.mclk <= r.masterclk;
irq <= r.irq;
apbo.prdata <= rdata;
ahbo.haddr <= haddr;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq;
ahbo.hwdata <= hwdata;
ahbo.hlock <= '0';
ahbo.hwrite <= hwrite;
ahbo.hsize <= hsize;
ahbo.hburst <= hburst;
ahbo.hprot <= (others => '0');
end process;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
timerout <= timerin;
end if;
end process;
timerpr : process(timerout, rst)
variable scaler : std_logic_vector(13 downto 0);
variable masterclk : std_logic;
variable tick : std_logic;
variable rscaler : std_logic_vector(1 downto 0);
variable sclk: std_logic;
-- scaler update
begin
if rst = '1' then
sclk:= timerout.sclk;
scaler := timerout.scaler-1;
masterclk := timerout.masterclk;
tick := scaler(13) and not timerout.scaler(13);
rscaler := timerout.sclkscaler;
if tick = '1' then
scaler := r.scalerup;
masterclk := not timerout.masterclk;
rscaler := rscaler+1; -- generating shiftclk
if ((not rscaler(0)) and (not rscaler(1)))='1' then
sclk := not sclk;
end if;
end if;
-- audio shiftclk generation
timerin.sclkscaler <= rscaler;
timerin.sclk_old <= timerout.sclk;
timerin.scaler <= scaler;
timerin.masterclk <= masterclk;
timerin.sclk <= sclk;
else
timerin.sclkscaler <= "00"; --reset
timerin.sclk_old <= '0';
timerin.sclk <= '0';
timerin.scaler <= "00000000000001";
timerin.masterclk <= '0';
end if;
end process;
end;
|
--------------------------------------------------------------------------------
--|
--| Filename : cntr
--| Author : R. Friesenhahn
--| Origin Date : 20130906
--|
--------------------------------------------------------------------------------
--|
--| Abstract
--|
--|
--|
--------------------------------------------------------------------------------
--|
--| Modification History
--|
--|
--|
--------------------------------------------------------------------------------
--|
--| References
--|
--|
--|
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cntr is
generic (
CntrWidth : integer := 8
);
port (
Clk : in std_ulogic;
Rst : in std_ulogic;
En : in std_ulogic;
Clr : in std_ulogic;
CritValue : in std_ulogic_vector(CntrWidth-1 downto 0);
CntrValue : out std_ulogic_vector(CntrWidth-1 downto 0);
CntReached : out std_ulogic
);
end cntr;
|
-- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
---------------------------------------------------------------------------------------------------------}}}
entity CU_mem_cntrl is --{{{
port(
clk : in std_logic;
-- from the CV
cv_wrData : in SLV32_ARRAY(CV_SIZE-1 downto 0); -- level 17.
cv_addr : in GMEM_ADDR_ARRAY; -- level 17.
cv_gmem_we : in std_logic;
cv_gmem_re : in std_logic;
cv_gmem_atomic : in std_logic;
cv_lmem_rqst : in std_logic; -- level 17.
cv_lmem_we : in std_logic;
cv_op_type : in std_logic_vector(2 downto 0); -- level 17.
cv_alu_en : in std_logic_vector(CV_SIZE-1 downto 0);
cv_alu_en_pri_enc : in integer range 0 to CV_SIZE-1 := 0;
cv_rd_addr : in unsigned(REG_FILE_W-1 downto 0);
-- to the CV
regFile_wrAddr : out unsigned(REG_FILE_W-1 downto 0) := (others=>'0'); -- stage -1 (stable for 3 clock cycles)
regFile_we : out std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- stage 0 (stable for 2 clock cycles) (level 20. for loads from lmem)
regFile_wrData : out SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- stage 0 (stable for 2 clock cycles)
regFile_we_lmem_p0 : out std_logic := '0'; -- level 19.
-- interface to the global memory controller
cache_rdAck : in std_logic := '0';
cache_rdAddr : in unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
cache_rdData : in std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0);
atomic_rdData : in std_logic_vector(DATA_W-1 downto 0) := (others=>'0');
atomic_rdData_v : in std_logic := '0';
atomic_sgntr : in std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0');
gmem_wrData : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0');
gmem_valid : out std_logic := '0';
gmem_we : out std_logic_vector(DATA_W/8-1 downto 0) := (others=>'0');
gmem_rnw : out std_logic := '0';
gmem_atomic : out std_logic := '0';
gmem_atomic_sgntr : out std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0');
gmem_ready : in std_logic;
gmem_rqst_addr : out unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0');
-- to CU scheduler
wf_finish : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0');
finish_exec : in std_logic := '0';
cntrl_idle : out std_logic := '0';
nrst : in std_logic
);
end entity; --}}}
architecture Behavioral of CU_mem_cntrl is
-- signals definitions ---------------------------------------------------------------------{{{
-- internal signals definitions {{{
signal gmem_valid_i : std_logic := '0';
signal regFile_wrAddr_i : unsigned(REG_FILE_W-1 downto 0) := (others=>'0');
signal cntrl_idle_i : std_logic := '0';
-- }}}
-- constants & functions {{{
constant N_STATIONS : natural := CV_SIZE*N_STATIONS_ALU;
type stations_for_alu_array is array(CV_SIZE-1 downto 0) of nat_array(N_STATIONS_ALU-1 downto 0);
-- functions ------------------------------------------------------------------ {{{
function distribute_stations_on_ALUs(n_stations: integer; n_alus: integer) return nat_array is
variable res: nat_array(n_stations-1 downto 0) := (others=>0);
begin
for i in 0 to n_stations-1 loop
for k in 0 to n_alus-1 loop
if i < (k+1)*(n_stations/n_alus) and i >= k*(n_stations/n_alus) then
res(i) := k;
exit;
end if;
end loop;
end loop;
return res;
end function;
function order_stations_by_priority(n_stations: integer; n_alus: integer) return nat_array is
-- variable res: nat_array(n_stations-1 downto 0) := (0=>13, 1=>15, 2=>0, 3=>2, 4=>4, 5=>6, 6=>8, 7=>10, 8=>12, 9=>14, 10=>1, 11=>3, 12=>5, 13=>7, 14=>9, 15=>11);
-- variable res: nat_array(n_stations-1 downto 0) := (0=>9, 1=>11, 2=>13, 3=>15, 4=>0, 5=>2, 6=>4, 7=>6, 8=>8, 9=>10, 10=>12, 11=>14, 12=>1, 13=>3, 14=>5, 15=>7);
variable res: nat_array(n_stations-1 downto 0) := (others=>0);
begin
-- if n_stations /= 16 or n_alus /= 8 then
for i in 0 to n_alus-1 loop
for j in 0 to n_stations/n_alus -1 loop
res(i + j*n_alus) := i*n_stations/n_alus + j;
end loop;
end loop;
-- end if;
return res;
end function;
function distribute_alus_on_stations(n_stations: natural; n_alus: natural) return stations_for_alu_array is
variable res: stations_for_alu_array := (others=>(others=>0));
begin
for k in 0 to n_alus-1 loop
for j in 0 to (n_stations/n_alus)-1 loop
res(k)(j) := k*n_stations/n_alus + j;
end loop;
end loop;
return res;
end function;
-------------------------------------------------------------------------------------}}}
--station signals
constant c_alu_for_stations : nat_array(N_STATIONS-1 downto 0) := distribute_stations_on_ALUs(N_STATIONS, CV_SIZE);
constant c_stations_for_alus : stations_for_alu_array := distribute_alus_on_stations(N_STATIONS, CV_SIZE);
constant c_stations_ordered_for_priority: nat_array(N_STATIONS-1 downto 0) := order_stations_by_priority(N_STATIONS, CV_SIZE);
--- }}}
-- finish signals {{{
type st_finish_type is (idle, serving, finished);
type st_finish_array_type is array (natural range<>) of st_finish_type;
signal st_finish, st_finish_n : st_finish_array_type(N_WF_CU-1 downto 0) := (others=>idle);
signal check_finish : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0');
signal check_finish_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0');
signal wf_finish_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0');
signal wfs_being_served : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0');
-- }}}
-- stations signals {{{
type st_station_type is (idle, get_ticket, wait_read_done, write_back, wait_atomic);
type st_station_array is array(natural range <>) of st_station_type;
signal st_stations, st_stations_n : st_station_array(N_STATIONS-1 downto 0) := (others=>idle);
signal station_gmem_addr : gmem_addr_array(N_STATIONS-1 downto 0) := (others=>(others=>'0'));
signal station_gmem_addr_n : gmem_addr_array(N_STATIONS-1 downto 0) := (others=>(others=>'0'));
signal station_rd_addr : reg_addr_array(N_STATIONS-1 downto 0) := (others=>(others=>'0'));
signal station_rd_addr_n : reg_addr_array(N_STATIONS-1 downto 0) := (others=>(others=>'0'));
signal station_free, station_free_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0');
signal station_wait_atomic : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0');
signal station_wait_atomic_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0');
signal station_go, station_go_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0');
signal station_rnw, station_rnw_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0');
signal station_atomic, station_atomic_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0');
signal station_perfomed : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0');
signal station_perfomed_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0');
signal station_rdData_n, station_rdData : SLV32_ARRAY(N_STATIONS-1 downto 0) := (others=>(others=>'0'));
signal station_wrData_n, station_wrData : SLV32_ARRAY(N_STATIONS-1 downto 0) := (others=>(others=>'0'));
type op_type_array is array (natural range <>) of std_logic_vector(2 downto 0);
signal station_op_type : op_type_array(N_STATIONS-1 downto 0) := (others=>(others=>'0'));
signal station_op_type_n : op_type_array(N_STATIONS-1 downto 0) := (others=>(others=>'0'));
signal station_written_back : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0');
signal station_written_back_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0');
signal regFile_we_latch : std_logic := '0';
signal regFile_we_latch_p0 : std_logic := '0';
signal regFile_we_latch_p0_n : std_logic := '0';
signal ticket_granted : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0');
signal stations_prefered : integer range 0 to N_STATIONS_ALU-1 := 0;
signal station_read_performed_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0');
signal station_atomic_perormed : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0');
signal atomic_rdData_v_d0 : std_logic := '0';
signal atomic_rdData_v_d1 : std_logic := '0';
signal atomic_rdData_d0 : std_logic_vector(DATA_W-1 downto 0) := (others=>'0');
signal atomic_rdData_d1 : std_logic_vector(DATA_W-1 downto 0) := (others=>'0');
attribute max_fanout of atomic_rdData_d1 : signal is 10;
signal atomic_sgntr_d0 : std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0');
signal station_last_atomic_serve : integer range 0 to N_STATIONS-1 := 0;
signal station_wf_indx : wf_active_array(N_STATIONS-1 downto 0) := (others=>(others=>'0'));
signal station_wf_indx_n : wf_active_array(N_STATIONS-1 downto 0) := (others=>(others=>'0'));
-- }}}
-- memory requests buffer {{{
-- 0..31: DATA, 32:63: ADDR, 64:re, 65:atomic, 66..68: op_type, 69:alu_en, 70..80: rd_addr
constant MEM_RQST_W : integer := DATA_W+GMEM_ADDR_W+1+1+3+1+REG_FILE_W;
constant MEM_RQST_DATA_LOW : integer := 0;
constant MEM_RQST_DATA_HIGH : integer := MEM_RQST_DATA_LOW+DATA_W-1; -- 31
constant MEM_RQST_ADDR_LOW : integer := MEM_RQST_DATA_HIGH+1; -- 32
constant MEM_RQST_ADDR_HIGH : integer := MEM_RQST_ADDR_LOW+GMEM_ADDR_W-1; -- 63
constant MEM_RQST_RE_POS : integer := MEM_RQST_ADDR_HIGH+1; -- 64
constant MEM_RQST_ATOMIC_POS : integer := MEM_RQST_RE_POS+1; -- 65
constant MEM_RQST_OP_TYPE_LOW : integer := MEM_RQST_ATOMIC_POS+1; -- 66
constant MEM_RQST_OP_TYPE_HIGH : integer := MEM_RQST_OP_TYPE_LOW+2; -- 68
constant MEM_RQST_ALU_EN_POS : integer := MEM_RQST_OP_TYPE_HIGH+1; -- 69
constant MEM_RQST_RD_ADDR_LOW : integer := MEM_RQST_ALU_EN_POS+1; -- 70
constant MEM_RQST_RD_ADDR_HIGH : integer := MEM_RQST_RD_ADDR_LOW+REG_FILE_W-1; -- 80
type mem_rqsts_buffer_type is array(natural range <>) of std_logic_vector(CV_SIZE*MEM_RQST_W-1 downto 0);
signal mem_rqsts : mem_rqsts_buffer_type(N_WF_CU*2**(PHASE_W)-1 downto 0) := (others=>(others=>'0'));
signal mem_rqsts_data : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- alias
signal mem_rqsts_addr : gmem_addr_array(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- alias
signal mem_rqsts_re : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); --alias
signal mem_rqsts_atomic : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); --alias
signal mem_rqsts_op_type : op_type_array(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- alias
signal mem_rqsts_rd_addr : reg_addr_array(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- alias
signal mem_rqsts_alu_en : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); --alias
signal mem_rqsts_rdAddr : unsigned(N_WF_CU_W+PHASE_W-1 downto 0) := (others=>'0');
signal mem_rqsts_rdAddr_inc_n : std_logic := '0';
signal mem_rqsts_wrAddr : unsigned(N_WF_CU_W+PHASE_W-1 downto 0) := (others=>'0');
type mem_rqsts_array is array(natural range <>) of std_logic_vector(MEM_RQST_W-1 downto 0);
signal mem_rqsts_rdData_n : std_logic_vector(CV_SIZE*MEM_RQST_W-1 downto 0) := (others=>'0');
signal mem_rqsts_rdData : std_logic_vector(CV_SIZE*MEM_RQST_W-1 downto 0) := (others=>'0');
signal mem_rqsts_rdData_ltchd_n : mem_rqsts_array(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal mem_rqsts_rdData_ltchd : mem_rqsts_array(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
attribute max_fanout of mem_rqsts_rdData_ltchd : signal is 300;
signal mem_rqsts_phase_ltchd : std_logic_vector(PHASE_W-1 downto 0) := (others=>'0');
signal mem_rqsts_phase_ltchd_n : std_logic_vector(PHASE_W-1 downto 0) := (others=>'0');
signal mem_rqsts_wf_indx_ltchd : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0');
signal mem_rqsts_wf_indx_ltchd_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0');
signal mem_rqsts_wrData : std_logic_vector(CV_SIZE*MEM_RQST_W-1 downto 0) := (others=>'0');
signal mem_rqsts_we : std_logic := '0';
signal mem_rqst_waiting : std_logic := '0';
signal mem_rqst_waiting_p0 : std_logic := '0';
signal mem_rqsts_nserved : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0');
signal mem_rqsts_nserved_n : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0');
-- }}}
-- CV side signals {{{
type st_cv_side_type is (get_rqst, fill_stations, wait_update);
signal st_cv_side, st_cv_side_n : st_cv_side_type := get_rqst;
signal latch_rdData, latch_rdData_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0');
-- }}}
-- regFile signals {{{
type regFile_interface_type is (choose_rd_addr, update, wait_1_cycle, wait_scratchpad);
signal st_regFile_int, st_regFile_int_n : regFile_interface_type := choose_rd_addr;
signal regFile_wrAddr_p0_n : unsigned(REG_FILE_W-1 downto 0) := (others=>'0');
signal regFile_wrAddr_p0 : unsigned(REG_FILE_W-1 downto 0) := (others=>'0');
signal regFile_we_p0_n, regFile_we_p0 : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0');
-- }}}
-- signals of the request waiting to be processed {{{
type st_waiting_type is (free, one_serve_zero_wait, one_serve_one_wait, zero_serve_one_wait);
type cv_wrData_waiting_type is array(natural range <>) of SLV32_ARRAY(CV_SIZE-1 downto 0);
type cv_addr_waiting_type is array(natural range <>) of GMEM_ADDR_ARRAY(CV_SIZE-1 downto 0);
-- }}}
-- mem interface {{{
signal station_get_ticket : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0');
signal station_get_ticket_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0');
-- fifo line
-- addr station_sgntr atomic data rnw we
-- GMEM_WORD_ADDR_W N_CU_STATIONS_W 1 DATA_W 1 DATA_W/8
type fifo_type is array (natural range <>) of std_logic_vector(DATA_W+1+DATA_W/8+N_CU_STATIONS_W downto 0);
type fifo_addr_type is array (natural range <>) of std_logic_vector(GMEM_ADDR_W-1 downto 0);
signal fifo : fifo_type(2**FIFO_ADDR_W-1 downto 0) := (others=>(others=>'0'));
signal fifo_addr : fifo_addr_type(2**FIFO_ADDR_W-1 downto 0) := (others=>(others=>'0'));
signal fifo_wrAddr, fifo_rdAddr : unsigned(FIFO_ADDR_W-1 downto 0) := (others=>'0');
signal fifo_wrAddr_n, fifo_rdAddr_n : unsigned(FIFO_ADDR_W-1 downto 0) := (others=>'0');
signal push, push_d0 : std_logic := '0';
signal push_rqst_fifo_n : std_logic := '0';
signal fifo_full : std_logic := '0';
signal pop : std_logic := '0';
signal din_rqst_fifo, din_rqst_fifo_d0 : std_logic_vector(DATA_W+1+DATA_W/8+N_CU_STATIONS_W downto 0) := (others=>'0');
signal din_rqst_fifo_addr : std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0');
signal din_rqst_fifo_addr_d0 : std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0');
signal station_slctd_indx, station_slctd_indx_n : natural range 0 to N_STATIONS-1 := 0;
attribute max_fanout of station_slctd_indx : signal is 60; --extra
constant c_rqst_fifo_addr_valid_len : natural := 3;
signal din_rqst_fifo_addr_d0_v : unsigned(c_rqst_fifo_addr_valid_len-1 downto 0) := (others=>'0');
signal fifo_dout : fifo_type(CV_TO_CACHE_SLICE-1 downto 0) := (others=>(others=>'0'));
signal fifo_addr_dout : fifo_addr_type(CV_TO_CACHE_SLICE-1 downto 0) := (others=>(others=>'0'));
signal gmem_valid_vec : std_logic_vector(CV_TO_CACHE_SLICE-1 downto 0) := (others=>'0');
signal pop_vec : std_logic_vector(CV_TO_CACHE_SLICE-1 downto 0) := (others=>'0');
signal lmem_rdData : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal lmem_rdData_d0 : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal lmem_rdData_v : std_logic := '0';
signal lmem_rdData_alu_en : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0');
signal lmem_rdData_rd_addr : unsigned(REG_FILE_W-1 downto 0) := (others=>'0');
signal sp : unsigned(LMEM_ADDR_W-N_WF_CU_W-PHASE_W-1 downto 0) := (others=>'0');
-- }}}
-- read cache buffer signals ----------------------------------------------------------------------------{{{
signal rd_fifo_data, rd_fifo_data_d0 : std_logic_vector(DATA_W*RD_CACHE_N_WORDS-1 downto 0) := (others=>'0');
attribute max_fanout of rd_fifo_data_d0 : signal is 8; --extra
signal rd_fifo_addr : unsigned(GMEM_WORD_ADDR_W-RD_CACHE_N_WORDS_W-1 downto 0) := (others=>'0');
signal rd_fifo_v : std_logic := '0';
---------------------------------------------------------------------------------------------------------}}}
------------------------------------------------------------------------------------------------}}}
begin
-- internal signals assignments -------------------------------------------------------------------------{{{
regFile_wrAddr <= regFile_wrAddr_i;
assert CV_TO_CACHE_SLICE > 0 severity failure;
cntrl_idle <= cntrl_idle_i;
---------------------------------------------------------------------------------------------------------}}}
-- CV interface (get requests) -------------------------------------------------------------------------------{{{
process(clk)
begin
if rising_edge(clk) then
mem_rqsts_rdData_n <= mem_rqsts(to_integer(mem_rqsts_rdAddr));
if mem_rqsts_we = '1' then
mem_rqsts(to_integer(mem_rqsts_wrAddr)) <= mem_rqsts_wrData;
end if;
mem_rqsts_rdData <= mem_rqsts_rdData_n;
mem_rqsts_we <= '0';
if cv_gmem_re = '1' or cv_gmem_we = '1' or (ATOMIC_IMPLEMENT /= 0 and cv_gmem_atomic = '1') then
mem_rqsts_we <= '1';
end if;
for i in 0 to CV_SIZE-1 loop
mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_DATA_HIGH downto i*MEM_RQST_W+MEM_RQST_DATA_LOW) <= cv_wrData(i);
mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_ADDR_HIGH downto i*MEM_RQST_W+MEM_RQST_ADDR_LOW) <= std_logic_vector(cv_addr(i));
mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_RE_POS) <= cv_gmem_re;
if ATOMIC_IMPLEMENT /= 0 then
mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_ATOMIC_POS) <= cv_gmem_atomic;
end if;
mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_OP_TYPE_HIGH downto i*MEM_RQST_W+MEM_RQST_OP_TYPE_LOW) <= cv_op_type;
mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_ALU_EN_POS) <= cv_alu_en(i);
mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_RD_ADDR_HIGH downto i*MEM_RQST_W+MEM_RQST_RD_ADDR_LOW) <= std_logic_vector(cv_rd_addr);
end loop;
mem_rqst_waiting_p0 <= '0';
if mem_rqsts_wrAddr /= mem_rqsts_rdAddr then
mem_rqst_waiting_p0 <= '1';
end if;
mem_rqst_waiting <= mem_rqst_waiting_p0;
if nrst = '0' then
mem_rqsts_wrAddr <= (others=>'0');
mem_rqsts_rdAddr <= (others=>'0');
else
if mem_rqsts_we = '1' then
mem_rqsts_wrAddr <= mem_rqsts_wrAddr + 1;
end if;
if mem_rqsts_rdAddr_inc_n = '1' then
mem_rqsts_rdAddr <= mem_rqsts_rdAddr + 1;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
-- CV interface (schedule requests) -------------------------------------------------------------------{{{
cv_side_trans: process(clk)
begin
if rising_edge(clk) then
station_go <= station_go_n;
mem_rqsts_rdData_ltchd <= mem_rqsts_rdData_ltchd_n;
mem_rqsts_phase_ltchd <= mem_rqsts_phase_ltchd_n;
mem_rqsts_wf_indx_ltchd <= mem_rqsts_wf_indx_ltchd_n;
mem_rqsts_nserved <= mem_rqsts_nserved_n;
check_finish <= check_finish_n;
if nrst = '0' then
st_cv_side <= get_rqst;
else
st_cv_side <= st_cv_side_n;
end if;
end if;
end process;
cv_side_comb: process(st_cv_side, mem_rqst_waiting, station_free, mem_rqsts_rdData, mem_rqsts_nserved, mem_rqsts_phase_ltchd,
mem_rqsts_rdData_ltchd, mem_rqsts_wf_indx_ltchd)
begin
st_cv_side_n <= st_cv_side;
station_go_n <= (others=>'0');
mem_rqsts_rdAddr_inc_n <= '0';
mem_rqsts_nserved_n <= mem_rqsts_nserved;
check_finish_n <= (others=>'0');
mem_rqsts_rdData_ltchd_n <= mem_rqsts_rdData_ltchd;
mem_rqsts_wf_indx_ltchd_n <= mem_rqsts_wf_indx_ltchd;
mem_rqsts_phase_ltchd_n <= mem_rqsts_phase_ltchd;
case st_cv_side is
when get_rqst =>
for i in 0 to CV_SIZE-1 loop
mem_rqsts_rdData_ltchd_n(i) <= mem_rqsts_rdData((i+1)*MEM_RQST_W-1 downto i*MEM_RQST_W);
end loop;
-- latch wf_indx and phase from first ALU
mem_rqsts_wf_indx_ltchd_n <= (others=>'0');
mem_rqsts_wf_indx_ltchd_n(to_integer(unsigned(
mem_rqsts_rdData(MEM_RQST_RD_ADDR_LOW+WI_REG_ADDR_W+N_WF_CU_W-1 downto MEM_RQST_RD_ADDR_LOW+WI_REG_ADDR_W)))) <= '1';
mem_rqsts_phase_ltchd_n(1 downto 0) <= mem_rqsts_rdData(MEM_RQST_RD_ADDR_HIGH downto MEM_RQST_RD_ADDR_HIGH-1);
mem_rqsts_phase_ltchd_n(2) <= mem_rqsts_rdData(MEM_RQST_RD_ADDR_HIGH-2);
for i in 0 to CV_SIZE-1 loop
mem_rqsts_nserved_n(i) <= mem_rqsts_rdData(i*MEM_RQST_W + MEM_RQST_ALU_EN_POS);
end loop;
if mem_rqst_waiting = '1' then
st_cv_side_n <= fill_stations;
mem_rqsts_rdAddr_inc_n <= '1';
end if;
when fill_stations =>
for i in 0 to cv_size-1 loop
for j in 0 to n_stations_alu-1 loop
if station_free(c_stations_for_alus(i)(j)) = '1' and mem_rqsts_nserved(i) = '1' then
station_go_n(c_stations_for_alus(i)(j)) <= '1';
mem_rqsts_nserved_n(i) <= '0';
exit;
end if;
end loop;
end loop;
if mem_rqsts_nserved = (mem_rqsts_nserved'reverse_range => '0') then
st_cv_side_n <= wait_update;
end if;
when wait_update => -- necessary to wait for mem_rqsts_rdData to be ready in case no alu was enabled
st_cv_side_n <= get_rqst;
if mem_rqsts_phase_ltchd = (mem_rqsts_phase_ltchd'reverse_range=>'1') then
check_finish_n <= mem_rqsts_wf_indx_ltchd;
end if;
end case;
end process;
----------------------------------------------------------------------------------------- }}}
-- gmem controller interface -------------------------------------------------------------------------------------------{{{
-- fifo {{{
process(clk)
begin
if rising_edge(clk) then
if nrst = '0' then
gmem_valid_vec <= (others=>'0');
else
if pop = '1' or gmem_valid_vec /= (gmem_valid_vec'reverse_range=>'1') then
gmem_valid_vec(gmem_valid_vec'high) <= gmem_valid_i;
end if;
for i in CV_TO_CACHE_SLICE-1 downto 1 loop
if pop = '1' or gmem_valid_vec(i-1 downto 0) /= (i-1 downto 0=>'1') then
gmem_valid_vec(i-1) <= gmem_valid_vec(i);
end if;
end loop;
end if;
if push_d0 = '1' then
fifo(to_integer(fifo_wrAddr)) <= din_rqst_fifo_d0;
fifo_addr(to_integer(fifo_wrAddr)) <= din_rqst_fifo_addr_d0;
end if;
if pop = '1' or gmem_valid_vec /= (gmem_valid_vec'reverse_range=>'1') then
fifo_addr_dout(fifo_addr_dout'high) <= fifo_addr(to_integer(fifo_rdAddr));
fifo_dout(fifo_dout'high) <= fifo(to_integer(fifo_rdAddr));
end if;
for i in CV_TO_CACHE_SLICE-1 downto 1 loop
if pop = '1' or gmem_valid_vec(i-1 downto 0) /= (i-1 downto 0=>'1') then
fifo_addr_dout(i-1) <= fifo_addr_dout(i);
fifo_dout(i-1) <= fifo_dout(i);
end if;
end loop;
if pop = '1' or gmem_valid_vec(CV_TO_CACHE_SLICE-2 downto 0) /= (0 to CV_TO_CACHE_SLICE-2 =>'1') then
if SUB_INTEGER_IMPLEMENT /= 0 then
case fifo_dout(CV_TO_CACHE_SLICE-1)(DATA_W+1+DATA_W/8)&fifo_dout(CV_TO_CACHE_SLICE-1)(2 downto 0) is -- DATA_W+1+DATA_W/8 for atomic bit
when "0001" => -- byte
case fifo_addr_dout(CV_TO_CACHE_SLICE-1)(1 downto 0) is
when "00" => -- 1st byte
fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "0001";
when "01" => -- 2nd byte
fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "0010";
fifo_dout(CV_TO_CACHE_SLICE-2)(2*8+5-1 downto 5+8) <= fifo_dout(CV_TO_CACHE_SLICE-1)(7+5 downto 5);
when "10" => -- 3rd byte
fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "0100";
fifo_dout(CV_TO_CACHE_SLICE-2)(3*8+5-1 downto 5+2*8) <= fifo_dout(CV_TO_CACHE_SLICE-1)(7+5 downto 5);
when others => -- 4th byte
fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "1000";
fifo_dout(CV_TO_CACHE_SLICE-2)(4*8+5-1 downto 5+3*8) <= fifo_dout(CV_TO_CACHE_SLICE-1)(7+5 downto 5);
end case;
when "0010" => -- half
case fifo_addr_dout(CV_TO_CACHE_SLICE-1)(1) is
when '0' => -- 1st half
fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "0011";
when others => -- 2nd half
fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "1100";
fifo_dout(CV_TO_CACHE_SLICE-2)(4*8+5-1 downto 5+2*8) <= fifo_dout(CV_TO_CACHE_SLICE-1)(2*8+5-1 downto 5);
end case;
when "0100" => -- word
fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= (others=>'1');
when others=>
fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= '0'&fifo_dout(CV_TO_CACHE_SLICE-1)(2 downto 0);
end case;
else
case fifo_dout(CV_TO_CACHE_SLICE-1)(DATA_W+1+DATA_W/8)&fifo_dout(CV_TO_CACHE_SLICE-1)(2 downto 0) is -- DATA_W+1+DATA_W/8 for atomic bit
when "0100" => -- word
fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= (others=>'1');
when others=>
fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= '0'&fifo_dout(CV_TO_CACHE_SLICE-1)(2 downto 0);
end case;
end if;
end if;
end if;
end process;
-- fifo read port
gmem_rqst_addr <= unsigned(fifo_addr_dout(0)(GMEM_ADDR_W-1 downto 2));
gmem_wrData <= fifo_dout(0)(DATA_W+DATA_W/8+1-1 downto DATA_W/8+1);
gmem_rnw <= fifo_dout(0)(DATA_W/8);
gmem_we <= fifo_dout(0)(DATA_W/8-1 downto 0);
-- assert gmem_rqst_addr(GMEM_WORD_ADDR_W-1 downto GMEM_WORD_ADDR_W-4) = X"01" or gmem_we /= X"F" severity failure;
atomic_signals: if ATOMIC_IMPLEMENT /= 0 generate
gmem_atomic <= fifo_dout(0)(DATA_W+DATA_W/8+1);
gmem_atomic_sgntr <= fifo_dout(0)(din_rqst_fifo'high downto din_rqst_fifo'high - N_CU_STATIONS_W+1);
end generate;
gmem_valid <= gmem_valid_vec(0);
pop <= gmem_valid_vec(0) and gmem_ready;
-- prepare write data into the fifo
din_rqst_fifo_addr <= std_logic_vector(station_gmem_addr(station_slctd_indx));
din_rqst_fifo(din_rqst_fifo'high downto din_rqst_fifo'high-N_CU_STATIONS_W+1) <= std_logic_vector(to_unsigned(station_slctd_indx, N_CU_STATIONS_W));
atomic_din: if ATOMIC_IMPLEMENT /= 0 generate
din_rqst_fifo(DATA_W+1+DATA_W/8) <= station_atomic(station_slctd_indx);
end generate;
din_rqst_fifo(DATA_W+1+DATA_W/8-1 downto 1+DATA_W/8) <= station_wrData(station_slctd_indx);
din_rqst_fifo(DATA_W/8) <= station_rnw(station_slctd_indx);
din_rqst_fifo(2 downto 0) <= station_op_type(station_slctd_indx);
rqst_fifo: process(clk)
begin
if rising_edge(clk) then
push_d0 <= push;
if din_rqst_fifo_addr_d0_v /= (din_rqst_fifo_addr_d0_v'reverse_range=>'0') and
din_rqst_fifo_addr_d0(GMEM_ADDR_W-1 downto CACHE_N_BANKS_W+2) = din_rqst_fifo_addr(GMEM_ADDR_W-1 downto CACHE_N_BANKS_W+2) and
din_rqst_fifo_d0(DATA_W/8) = '1' and din_rqst_fifo(DATA_W/8) = '1' then
push_d0 <= '0';
end if;
din_rqst_fifo_addr_d0_v(din_rqst_fifo_addr_d0_v'high) <= '0';
din_rqst_fifo_addr_d0_v(din_rqst_fifo_addr_d0_v'high-1 downto 0) <= din_rqst_fifo_addr_d0_v(din_rqst_fifo_addr_d0_v'high downto 1);
if push = '1' then
din_rqst_fifo_d0 <= din_rqst_fifo;
din_rqst_fifo_addr_d0 <= din_rqst_fifo_addr;
din_rqst_fifo_addr_d0_v(din_rqst_fifo_addr_d0_v'high) <= '1';
end if;
if din_rqst_fifo_addr_d0(GMEM_ADDR_W-1 downto CACHE_N_BANKS_W+2) = std_logic_vector(cache_rdAddr) and cache_rdAck = '1' then
din_rqst_fifo_addr_d0_v <= (others=>'0');
-- report "clean happened";
end if;
if nrst = '0' then
fifo_wrAddr <= (others=>'0');
fifo_rdAddr <= (others=>'0');
fifo_full <= '0';
gmem_valid_i <= '0';
else
if push_d0 = '1' then
fifo_wrAddr <= fifo_wrAddr +1;
end if;
if (pop = '1' or gmem_valid_vec(gmem_valid_vec'high downto 0) /= (0 to gmem_valid_vec'high =>'1')) and gmem_valid_i = '1' then
fifo_rdAddr <= fifo_rdAddr + 1;
end if;
if push_d0 = '0' and (pop = '1' or gmem_valid_vec(gmem_valid_vec'high downto 0) /= (0 to gmem_valid_vec'high =>'1')) then
if fifo_rdAddr = fifo_wrAddr+2 then
fifo_full <= '0';
end if;
if fifo_rdAddr+1 = fifo_wrAddr then
gmem_valid_i <= '0';
end if;
end if;
if push_d0 = '1' then
gmem_valid_i <= '1';
if fifo_rdAddr = fifo_wrAddr+3 and (pop = '0' and gmem_valid_vec(gmem_valid_vec'high downto 0) = (0 to gmem_valid_vec'high =>'1')) then -- 2 because of extra clock delay (push -> push_d0)
fifo_full <= '1';
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
process(clk)
begin
if rising_edge(clk) then
push <= push_rqst_fifo_n;
station_slctd_indx <= station_slctd_indx_n;
end if;
end process;
process(station_get_ticket, fifo_full)
variable station : natural range 0 to N_STATIONS-1 := 0;
begin
ticket_granted <= (others=>'0');
push_rqst_fifo_n <= '0';
station_slctd_indx_n <= 0;
-- grant ticket
if fifo_full = '0' then
for i in 0 to N_STATIONS-1 loop
station := c_stations_ordered_for_priority(i);
-- station := i;
if station_get_ticket(station) = '1' then
push_rqst_fifo_n <= '1';
station_slctd_indx_n <= station;
ticket_granted(station) <= '1';
exit;
end if;
end loop;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
-- stations FSMs -------------------------------------------------------------------------------------------{{{
tras_stations: process(clk) -- {{{
begin
if rising_edge(clk) then
station_free <= station_free_n;
rd_fifo_data_d0 <= rd_fifo_data;
station_gmem_addr <= station_gmem_addr_n;
station_rd_addr <= station_rd_addr_n;
station_wf_indx <= station_wf_indx_n;
station_rnw <= station_rnw_n;
if ATOMIC_IMPLEMENT /= 0 then
station_atomic <= station_atomic_n;
end if;
station_rdData <= station_rdData_n;
station_wrData <= station_wrData_n;
station_op_type <= station_op_type_n;
if nrst = '0' then
st_stations <= (others=>idle);
station_get_ticket <= (others=>'0');
station_perfomed <= (others=>'0');
if ATOMIC_IMPLEMENT /= 0 then
station_wait_atomic <= (others=>'0');
end if;
else
st_stations <= st_stations_n;
station_get_ticket <= station_get_ticket_n;
station_perfomed <= station_perfomed_n;
if ATOMIC_IMPLEMENT /= 0 then
station_wait_atomic <= station_wait_atomic_n;
end if;
end if;
end if;
end process; -- }}}
stations_read_performed: process(station_gmem_addr, rd_fifo_addr, rd_fifo_v) -- {{{
begin
station_read_performed_n <= (others=>'0');
for i in 0 to N_STATIONS-1 loop
if station_gmem_addr(i)(GMEM_ADDR_W-1 downto 2+RD_CACHE_N_WORDS_W) = rd_fifo_addr and rd_fifo_v = '1' then
station_read_performed_n(i) <= '1';
end if;
end loop;
end process; -- }}}
process(clk)
begin
if rising_edge(clk) then
if ATOMIC_IMPLEMENT /= 0 then
atomic_rdData_v_d0 <= atomic_rdData_v;
atomic_rdData_v_d1 <= atomic_rdData_v_d0;
atomic_sgntr_d0 <= atomic_sgntr;
atomic_rdData_d0 <= atomic_rdData;
atomic_rdData_d1 <= atomic_rdData_d0;
station_atomic_perormed <= (others=>'0');
for i in 0 to N_STATIONS-1 loop
-- if station_gmem_addr(i)(GMEM_ADDR_W-1 downto 2) = atomic_rdAddr_d0 and atomic_rdData_v_d0 = '1' and
-- station_op_type(i) = atomic_rdData_type_d0 and station_wait_atomic(i) = '1' and
-- (station_last_atomic_serve /= i or atomic_rdData_v_d1 = '0')then
-- station_last_atomic_serve <= i;
if unsigned(atomic_sgntr_d0) = to_unsigned(i, N_CU_STATIONS_W) and atomic_rdData_v_d0 = '1' and station_wait_atomic(i) = '1' then
station_atomic_perormed(i) <= '1';
end if;
end loop;
end if;
end if;
end process;
process(st_stations, station_free, station_go, station_gmem_addr, station_rd_addr, station_rnw, mem_rqsts_wf_indx_ltchd,
station_get_ticket, station_op_type, ticket_granted, station_perfomed, station_written_back, station_wrData,
station_rdData, rd_fifo_data_d0, station_read_performed_n, latch_rdData, station_atomic, station_wait_atomic,
station_atomic_perormed, atomic_rdData_d1, mem_rqsts_rdData_ltchd, station_wf_indx)
variable rdIndx : integer range 0 to CACHE_N_BANKS-1 := 0;
begin
for i in 0 to N_STATIONS-1 loop
station_rnw_n(i) <= station_rnw(i);
if ATOMIC_IMPLEMENT /= 0 then
station_atomic_n(i) <= station_atomic(i);
station_wait_atomic_n(i) <= station_wait_atomic(i);
end if;
station_rd_addr_n(i) <= station_rd_addr(i);
station_gmem_addr_n(i) <= station_gmem_addr(i);
station_free_n(i) <= station_free(i);
st_stations_n(i) <= st_stations(i);
station_get_ticket_n(i) <= station_get_ticket(i);
station_rdData_n(i) <= station_rdData(i);
station_perfomed_n(i) <= station_perfomed(i);
station_wrData_n(i) <= station_wrData(i);
station_op_type_n(i) <= station_op_type(i);
latch_rdData_n(i) <= '0';
station_wf_indx_n(i) <= station_wf_indx(i);
case st_stations(i) is
when idle => -- {{{
station_free_n(i) <= '1';
station_wf_indx_n(i) <= mem_rqsts_wf_indx_ltchd;
if station_go(i) = '1' then
st_stations_n(i) <= get_ticket;
station_get_ticket_n(i) <= '1';
station_free_n(i) <= '0';
station_gmem_addr_n(i) <= unsigned(mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_ADDR_HIGH downto MEM_RQST_ADDR_LOW));
station_rd_addr_n(i) <= unsigned(mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_RD_ADDR_HIGH downto MEM_RQST_RD_ADDR_LOW));
station_rnw_n(i) <= mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_RE_POS);
if ATOMIC_IMPLEMENT /= 0 then
station_atomic_n(i) <= mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_ATOMIC_POS);
end if;
station_wrData_n(i) <= mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_DATA_HIGH downto MEM_RQST_DATA_LOW);
station_op_type_n(i) <= mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_OP_TYPE_HIGH downto MEM_RQST_OP_TYPE_LOW);
end if; -- }}}
when get_ticket => -- {{{
-- assert (station_gmem_addr(i)(17 downto 2) = unsigned(station_wrData(i)(15 downto 0))) or station_rnw(i) = '1'
-- report integer'image(to_integer(station_gmem_addr(i)(GMEM_ADDR_W-1 downto 2))) & ", data = " &
-- integer'image(to_integer(unsigned(station_wrData(i)))) severity failure;
if station_rnw(i) = '1' and station_read_performed_n(i) = '1' then
station_get_ticket_n(i) <= '0';
station_perfomed_n(i) <= '1';
st_stations_n(i) <= write_back;
latch_rdData_n(i) <= '1';
station_get_ticket_n(i) <= '0';
elsif ticket_granted(i) = '1' then
if station_rnw(i) = '1' then
st_stations_n(i) <= wait_read_done;
elsif ATOMIC_IMPLEMENT /= 0 and station_atomic(i) = '1' then
st_stations_n(i) <= wait_atomic;
station_wait_atomic_n(i) <= '1';
else
st_stations_n(i) <= idle;
station_free_n(i) <= '1';
end if;
station_get_ticket_n(i) <= '0';
end if; -- }}}
when wait_atomic => -- {{{
if ATOMIC_IMPLEMENT /= 0 then
station_rdData_n(i) <= atomic_rdData_d1;
if station_atomic_perormed(i) = '1' then
st_stations_n(i) <= write_back;
station_perfomed_n(i) <= '1';
station_wait_atomic_n(i) <= '0';
end if;
end if;
-- }}}
when wait_read_done => -- {{{
if station_read_performed_n(i) = '1' then
latch_rdData_n(i) <= '1';
st_stations_n(i) <= write_back;
station_perfomed_n(i) <= '1';
end if; -- }}}
when write_back => -- {{{
if latch_rdData(i) = '1' then
if RD_CACHE_N_WORDS_W /= 0 then
rdIndx := to_integer(station_gmem_addr(i)(max(RD_CACHE_N_WORDS_W,1)+2-1 downto 2));
else
rdIndx := 0;
end if;
station_rdData_n(i) <= rd_fifo_data_d0((rdIndx+1)*DATA_W-1 downto rdIndx*DATA_W);
end if;
if station_written_back(i) = '1' then
st_stations_n(i) <= idle;
station_free_n(i) <= '1';
station_perfomed_n(i) <= '0';
end if; -- }}}
end case;
end loop;
end process;
---------------------------------------------------------------------------------------------------------}}}
-- regFile interface ---------------------------------------------------------------------------------------{{{
-- regFile comb process ---------------------------------------------------------------------------------{{{
process(st_regFile_int, station_perfomed, regFile_wrAddr_p0, station_rd_addr, station_written_back, cv_lmem_rqst)
begin
st_regFile_int_n <= st_regFile_int;
regFile_wrAddr_p0_n <= regFile_wrAddr_p0;
regFile_we_p0_n <= (others=>'0');
station_written_back_n <= (others=>'0');
regFile_we_latch_p0_n <= '0';
case st_regFile_int is
when choose_rd_addr =>
for i in N_STATIONS-1 downto 0 loop
if station_perfomed(i) = '1' and station_written_back(i) = '0' then
regFile_wrAddr_p0_n <= station_rd_addr(i);
st_regFile_int_n <= update;
end if;
end loop;
if LMEM_IMPLEMENT /= 0 and cv_lmem_rqst = '1' then
st_regFile_int_n <= wait_scratchpad;
end if;
when update =>
st_regFile_int_n <= wait_1_cycle;
if LMEM_IMPLEMENT /= 0 and cv_lmem_rqst = '1' then
st_regFile_int_n <= wait_scratchpad;
else
for i in 0 to CV_SIZE-1 loop
for j in N_STATIONS_ALU-1 downto 0 loop
if station_perfomed(i*N_STATIONS_ALU+j) = '1' and station_rd_addr(i*N_STATIONS_ALU+j) = regFile_wrAddr_p0 then
regFile_we_p0_n(i) <= '1';
station_written_back_n(i*N_STATIONS_ALU+j) <= '1';
regFile_we_latch_p0_n <= '1';
end if;
end loop;
end loop;
end if;
when wait_1_cycle =>
st_regFile_int_n <= choose_rd_addr;
when wait_scratchpad =>
if LMEM_IMPLEMENT /= 0 and cv_lmem_rqst = '0' then
st_regFile_int_n <= choose_rd_addr;
end if;
end case;
end process;
---------------------------------------------------------------------------------------------------------}}}
-- regFile trans process --------------------------------------------------------------------------------{{{
regFile_we_lmem_p0 <= lmem_rdData_v; -- @ level 19.
regFile_side_trans: process(clk)
begin
if rising_edge(clk) then
regFile_we_p0 <= regFile_we_p0_n;
latch_rdData <= latch_rdData_n;
station_written_back <= station_written_back_n;
regFile_we_latch_p0 <= regFile_we_latch_p0_n;
regFile_we_latch <= regFile_we_latch_p0;
regFile_wrAddr_i <= regFile_wrAddr_p0;
if regFile_we_latch = '0' then
regFile_we <= regFile_we_p0;
end if;
regFile_wrAddr_p0 <= regFile_wrAddr_p0_n;
lmem_rdData_d0 <= lmem_rdData; -- @ 20.
if LMEM_IMPLEMENT /= 0 and lmem_rdData_v = '1' then -- level 19.
regFile_we <= lmem_rdData_alu_en; -- @ 20.
regFile_wrAddr_i <= lmem_rdData_rd_addr; -- @ 20.
end if;
if LMEM_IMPLEMENT /= 0 and regFile_we_latch = '0' then
regFile_wrData <= lmem_rdData; -- @ 20.
end if;
for i in 0 to CV_SIZE-1 loop
for j in N_STATIONS_ALU-1 downto 0 loop
if station_written_back(i*N_STATIONS_ALU+j) = '1' then
regFile_wrData(i) <= station_rdData(i*N_STATIONS_ALU+j);
end if;
end loop;
end loop;
if nrst = '0' then
st_regFile_int <= choose_rd_addr;
else
st_regFile_int <= st_regFile_int_n;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
-----------------------------------------------------------------------------------}}}
-- gmem finished -------------------------------------------------------{{{
process(clk)
variable wf_busy_indices : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0');
begin
if rising_edge(clk) then
wf_finish <= wf_finish_n;
if nrst = '0' then
st_finish <= (others=>idle);
else
st_finish <= st_finish_n;
end if;
wf_busy_indices := (others=>'0');
for i in 0 to N_STATIONS-1 loop
if station_free(i) = '0' then
wf_busy_indices := wf_busy_indices or station_wf_indx(i);
end if;
end loop;
wfs_being_served <= wf_busy_indices;
end if;
end process;
st_finish_array: for i in 0 to N_WF_CU-1 generate
begin
process(st_finish(i), check_finish(i), wfs_being_served(i))
begin
st_finish_n(i) <= st_finish(i);
wf_finish_n(i) <= '0';
case st_finish(i) is
when idle =>
if check_finish(i) = '1' then
st_finish_n(i) <= serving;
end if;
when serving =>
if wfs_being_served(i) = '0' then
st_finish_n(i) <= finished;
end if;
when finished =>
wf_finish_n(i) <= '1';
st_finish_n(i) <= idle;
end case;
end process;
end generate;
---------------------------------------------------------------------------------------------------------}}}
-- controller idle -------------------------------------------------------------------------------------{{{
process(clk)
begin
if rising_edge(clk) then
cntrl_idle_i <= '0';
if station_free = (station_free'reverse_range=>'1') and gmem_valid_i = '0' and st_cv_side = get_rqst then
cntrl_idle_i <= '1';
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
-- cache read fifo -------------------------------------------------------------------------------------------{{{
-- cu_mem_cntrl <- port A (myram) port B -> cache
cache_rd_buffer_inst: entity rd_cache_fifo
generic map (
SIZEA => 2**(RD_CACHE_FIFO_PORTB_ADDR_W+CACHE_N_BANKS_W-RD_CACHE_N_WORDS_W),
ADDRWIDTHA => RD_CACHE_FIFO_PORTB_ADDR_W+CACHE_N_BANKS_W-RD_CACHE_N_WORDS_W,
SIZEB => 2**RD_CACHE_FIFO_PORTB_ADDR_W,
ADDRWIDTHB => RD_CACHE_FIFO_PORTB_ADDR_W
)
port map(
clk => clk,
push => cache_rdAck,
cache_rdData => cache_rdData,
cache_rdAddr => cache_rdAddr,
rdData => rd_fifo_data,
rdAddr => rd_fifo_addr,
nempty => rd_fifo_v,
nrst => nrst
);
---------------------------------------------------------------------------------------------------------}}}
-- lmem -------------------------------------------------------------------------------------------------{{{
local_memory_inst: if LMEM_IMPLEMENT /= 0 generate
begin
sp <= cv_addr(cv_alu_en_pri_enc)(LMEM_ADDR_W-N_WF_CU_W-PHASE_W-1 downto 0);
local_memory: entity lmem
port map(
clk => clk,
rqst => cv_lmem_rqst, -- level 17.
we => cv_lmem_we,
alu_en => cv_alu_en,
wrData => cv_wrData,
rdData => lmem_rdData, -- level 19.
rdData_rd_addr => lmem_rdData_rd_addr, -- level 19.
rdData_v => lmem_rdData_v, -- level 19.
rdData_alu_en => lmem_rdData_alu_en, -- level 19.
-- connect all of cv_addr; you have 8 SPs!!
sp => sp,
rd_addr => cv_rd_addr,
nrst => nrst
);
end generate;
---------------------------------------------------------------------------------------------------------}}}
end architecture;
|
-------------------------------------------------------------------------------
-- uartlite_tx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_tx.vhd
-- Version: v2.0
-- Description: UART Lite Transmit Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.UNSIGNED;
use IEEE.numeric_std.to_unsigned;
use IEEE.numeric_std."-";
library lib_srl_fifo_v1_0;
-- dynshreg_i_f refered from proc_common_v4_00_a
library axi_uartlite_v2_0;
-- uartlite_core refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.all;
-- srl_fifo_f refered from proc_common_v4_00_a
use lib_srl_fifo_v1_0.srl_fifo_f;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- TX -- Transmit Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Write_TX_FIFO -- Write transmit FIFO
-- Reset_TX_FIFO -- Reset transmit FIFO
-- TX_Data -- Transmit data input
-- TX_Buffer_Full -- Transmit buffer full
-- TX_Buffer_Empty -- Transmit buffer empty
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_tx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
TX : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_DATA_BITS-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic
);
end entity uartlite_tx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_tx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
-------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------
constant MUX_SEL_INIT : std_logic_vector(0 to 2) :=
std_logic_vector(to_unsigned(C_DATA_BITS-1, 3));
-------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------
signal parity : std_logic;
signal tx_Run1 : std_logic;
signal select_Parity : std_logic;
signal data_to_transfer : std_logic_vector(0 to C_DATA_BITS-1);
signal div16 : std_logic;
signal tx_Data_Enable : std_logic;
signal tx_Start : std_logic;
signal tx_DataBits : std_logic;
signal tx_Run : std_logic;
signal mux_sel : std_logic_vector(0 to 2);
signal mux_sel_is_zero : std_logic;
signal mux_01 : std_logic;
signal mux_23 : std_logic;
signal mux_45 : std_logic;
signal mux_67 : std_logic;
signal mux_0123 : std_logic;
signal mux_4567 : std_logic;
signal mux_Out : std_logic;
signal serial_Data : std_logic;
signal fifo_Read : std_logic;
signal fifo_Data_Present : std_logic := '0';
signal fifo_Data_Empty : std_logic;
signal fifo_DOut : std_logic_vector(0 to C_DATA_BITS-1);
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal tx_buffer_full_i : std_logic;
signal TX_FIFO_Reset : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
--MID_START_BIT_SRL16_I : Shift register is used to generate div16 that
-- gets shifted for 16 times(as Addr = 15) when
-- EN_16x_Baud is high.
---------------------------------------------------------------------------
MID_START_BIT_SRL16_I : entity axi_uartlite_v2_0.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_INIT_VALUE => X"8000",
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => div16,
Dout(0) => div16
);
------------------------------------------------------------------------
-- TX_DATA_ENABLE_DFF : tx_Data_Enable is '1' when div16 is 1 and
-- EN_16x_Baud is 1. It will deasserted in the
-- next clock cycle.
------------------------------------------------------------------------
TX_DATA_ENABLE_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Data_Enable <= '0';
else
if (tx_Data_Enable = '1') then
tx_Data_Enable <= '0';
elsif (EN_16x_Baud = '1') then
tx_Data_Enable <= div16;
end if;
end if;
end if;
end process TX_DATA_ENABLE_DFF;
------------------------------------------------------------------------
-- TX_START_DFF : tx_start is '1' for the start bit in a transmission
------------------------------------------------------------------------
TX_START_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Start <= '0';
else
tx_Start <= (not(tx_Run) and (tx_Start or
(fifo_Data_Present and tx_Data_Enable)));
end if;
end if;
end process TX_START_DFF;
--------------------------------------------------------------------------
-- TX_DATA_DFF : tx_DataBits is '1' during all databits transmission
--------------------------------------------------------------------------
TX_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_DataBits <= '0';
else
tx_DataBits <= (not(fifo_Read) and (tx_DataBits or
(tx_Start and tx_Data_Enable)));
end if;
end if;
end process TX_DATA_DFF;
-------------------------------------------------------------------------
-- COUNTER : If mux_sel is zero then reload with the init value else if
-- tx_DataBits = '1', decrement
-------------------------------------------------------------------------
COUNTER : process (Clk) is
begin -- process Mux_Addr_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
mux_sel <= std_logic_vector(to_unsigned(C_DATA_BITS-1,
mux_sel'length));
elsif (tx_Data_Enable = '1') then
if (mux_sel_is_zero = '1') then
mux_sel <= MUX_SEL_INIT;
elsif (tx_DataBits = '1') then
mux_sel <= std_logic_vector(UNSIGNED(mux_sel) - 1);
end if;
end if;
end if;
end process COUNTER;
------------------------------------------------------------------------
-- Detecting when mux_sel is zero, i.e. all data bits are transfered
------------------------------------------------------------------------
mux_sel_is_zero <= '1' when mux_sel = "000" else '0';
--------------------------------------------------------------------------
-- FIFO_READ_DFF : Read out the next data from the transmit fifo when the
-- data has been transmitted
--------------------------------------------------------------------------
FIFO_READ_DFF : process (Clk) is
begin -- process FIFO_Read_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Read <= '0';
else
fifo_Read <= tx_Data_Enable and mux_sel_is_zero;
end if;
end if;
end process FIFO_READ_DFF;
--------------------------------------------------------------------------
-- Select which bit within the data word to transmit
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- PARITY_BIT_INSERTION : Need special treatment for inserting the parity
-- bit because of parity generation
--------------------------------------------------------------------------
data_to_transfer(0 to C_DATA_BITS-2) <= fifo_DOut(0 to C_DATA_BITS-2);
data_to_transfer(C_DATA_BITS-1) <= parity when select_Parity = '1' else
fifo_DOut(C_DATA_BITS-1);
mux_01 <= data_to_transfer(1) when mux_sel(2) = '1' else
data_to_transfer(0);
mux_23 <= data_to_transfer(3) when mux_sel(2) = '1' else
data_to_transfer(2);
--------------------------------------------------------------------------
-- DATA_BITS_IS_5 : Select total 5 data bits when C_DATA_BITS = 5
--------------------------------------------------------------------------
DATA_BITS_IS_5 : if (C_DATA_BITS = 5) generate
mux_45 <= data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_5;
--------------------------------------------------------------------------
-- DATA_BITS_IS_6 : Select total 6 data bits when C_DATA_BITS = 6
--------------------------------------------------------------------------
DATA_BITS_IS_6 : if (C_DATA_BITS = 6) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_6;
--------------------------------------------------------------------------
-- DATA_BITS_IS_7 : Select total 7 data bits when C_DATA_BITS = 7
--------------------------------------------------------------------------
DATA_BITS_IS_7 : if (C_DATA_BITS = 7) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(6);
end generate DATA_BITS_IS_7;
--------------------------------------------------------------------------
-- DATA_BITS_IS_8 : Select total 8 data bits when C_DATA_BITS = 8
--------------------------------------------------------------------------
DATA_BITS_IS_8 : if (C_DATA_BITS = 8) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(7) when mux_sel(2) = '1' else
data_to_transfer(6);
end generate DATA_BITS_IS_8;
mux_0123 <= mux_23 when mux_sel(1) = '1' else mux_01;
mux_4567 <= mux_67 when mux_sel(1) = '1' else mux_45;
mux_Out <= mux_4567 when mux_sel(0) = '1' else mux_0123;
--------------------------------------------------------------------------
-- SERIAL_DATA_DFF : Register the mux_Out
--------------------------------------------------------------------------
SERIAL_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
serial_Data <= '0';
else
serial_Data <= mux_Out;
end if;
end if;
end process SERIAL_DATA_DFF;
--------------------------------------------------------------------------
-- SERIAL_OUT_DFF :Force a '0' when tx_start is '1', Start_bit
-- Force a '1' when tx_run is '0', Idle
-- otherwise put out the serial_data
--------------------------------------------------------------------------
SERIAL_OUT_DFF : process (Clk) is
begin -- process Serial_Out_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
TX <= '1';
else
TX <= (not(tx_Run) or serial_Data) and (not(tx_Start));
end if;
end if;
end process SERIAL_OUT_DFF;
--------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
--------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (tx_Start = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (tx_Data_Enable = '1') then
parity <= parity xor serial_Data;
end if;
end if;
end process PARITY_DFF;
TX_RUN1_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Run1 <= '0';
elsif (tx_Data_Enable = '1') then
tx_Run1 <= tx_DataBits;
end if;
end if;
end process TX_RUN1_DFF;
tx_Run <= tx_Run1 or tx_DataBits;
SELECT_PARITY_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
select_Parity <= '0';
elsif (tx_Data_Enable = '1') then
select_Parity <= mux_sel_is_zero;
end if;
end if;
end process SELECT_PARITY_DFF;
end generate USING_PARITY;
--------------------------------------------------------------------------
-- NO_PARITY : When C_USE_PARITY = 0 select parity as '0'
--------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
tx_Run <= tx_DataBits;
select_Parity <= '0';
end generate NO_PARITY;
--------------------------------------------------------------------------
-- Write TX FIFO when FIFO is not full when AXI writes data in TX FIFO
--------------------------------------------------------------------------
fifo_wr <= Write_TX_FIFO and (not tx_buffer_full_i);
--------------------------------------------------------------------------
-- Read TX FIFO when FIFO is not empty when AXI reads data from TX FIFO
--------------------------------------------------------------------------
fifo_rd <= fifo_Read and (not fifo_Data_Empty);
--------------------------------------------------------------------------
-- Reset TX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
TX_FIFO_Reset <= Reset_TX_FIFO or Reset;
--------------------------------------------------------------------------
-- SRL_FIFO_I : Transmit FIFO Interface
--------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => TX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => TX_Data,
FIFO_Read => fifo_rd,
Data_Out => fifo_DOut,
FIFO_Full => tx_buffer_full_i,
FIFO_Empty => fifo_Data_Empty
);
TX_Buffer_Full <= tx_buffer_full_i;
TX_Buffer_Empty <= fifo_Data_Empty;
fifo_Data_Present <= not fifo_Data_Empty;
end architecture RTL;
|
-------------------------------------------------------------------------------
-- uartlite_tx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_tx.vhd
-- Version: v2.0
-- Description: UART Lite Transmit Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.UNSIGNED;
use IEEE.numeric_std.to_unsigned;
use IEEE.numeric_std."-";
library lib_srl_fifo_v1_0;
-- dynshreg_i_f refered from proc_common_v4_00_a
library axi_uartlite_v2_0;
-- uartlite_core refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.all;
-- srl_fifo_f refered from proc_common_v4_00_a
use lib_srl_fifo_v1_0.srl_fifo_f;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- TX -- Transmit Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Write_TX_FIFO -- Write transmit FIFO
-- Reset_TX_FIFO -- Reset transmit FIFO
-- TX_Data -- Transmit data input
-- TX_Buffer_Full -- Transmit buffer full
-- TX_Buffer_Empty -- Transmit buffer empty
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_tx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
TX : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_DATA_BITS-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic
);
end entity uartlite_tx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_tx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
-------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------
constant MUX_SEL_INIT : std_logic_vector(0 to 2) :=
std_logic_vector(to_unsigned(C_DATA_BITS-1, 3));
-------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------
signal parity : std_logic;
signal tx_Run1 : std_logic;
signal select_Parity : std_logic;
signal data_to_transfer : std_logic_vector(0 to C_DATA_BITS-1);
signal div16 : std_logic;
signal tx_Data_Enable : std_logic;
signal tx_Start : std_logic;
signal tx_DataBits : std_logic;
signal tx_Run : std_logic;
signal mux_sel : std_logic_vector(0 to 2);
signal mux_sel_is_zero : std_logic;
signal mux_01 : std_logic;
signal mux_23 : std_logic;
signal mux_45 : std_logic;
signal mux_67 : std_logic;
signal mux_0123 : std_logic;
signal mux_4567 : std_logic;
signal mux_Out : std_logic;
signal serial_Data : std_logic;
signal fifo_Read : std_logic;
signal fifo_Data_Present : std_logic := '0';
signal fifo_Data_Empty : std_logic;
signal fifo_DOut : std_logic_vector(0 to C_DATA_BITS-1);
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal tx_buffer_full_i : std_logic;
signal TX_FIFO_Reset : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
--MID_START_BIT_SRL16_I : Shift register is used to generate div16 that
-- gets shifted for 16 times(as Addr = 15) when
-- EN_16x_Baud is high.
---------------------------------------------------------------------------
MID_START_BIT_SRL16_I : entity axi_uartlite_v2_0.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_INIT_VALUE => X"8000",
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => div16,
Dout(0) => div16
);
------------------------------------------------------------------------
-- TX_DATA_ENABLE_DFF : tx_Data_Enable is '1' when div16 is 1 and
-- EN_16x_Baud is 1. It will deasserted in the
-- next clock cycle.
------------------------------------------------------------------------
TX_DATA_ENABLE_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Data_Enable <= '0';
else
if (tx_Data_Enable = '1') then
tx_Data_Enable <= '0';
elsif (EN_16x_Baud = '1') then
tx_Data_Enable <= div16;
end if;
end if;
end if;
end process TX_DATA_ENABLE_DFF;
------------------------------------------------------------------------
-- TX_START_DFF : tx_start is '1' for the start bit in a transmission
------------------------------------------------------------------------
TX_START_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Start <= '0';
else
tx_Start <= (not(tx_Run) and (tx_Start or
(fifo_Data_Present and tx_Data_Enable)));
end if;
end if;
end process TX_START_DFF;
--------------------------------------------------------------------------
-- TX_DATA_DFF : tx_DataBits is '1' during all databits transmission
--------------------------------------------------------------------------
TX_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_DataBits <= '0';
else
tx_DataBits <= (not(fifo_Read) and (tx_DataBits or
(tx_Start and tx_Data_Enable)));
end if;
end if;
end process TX_DATA_DFF;
-------------------------------------------------------------------------
-- COUNTER : If mux_sel is zero then reload with the init value else if
-- tx_DataBits = '1', decrement
-------------------------------------------------------------------------
COUNTER : process (Clk) is
begin -- process Mux_Addr_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
mux_sel <= std_logic_vector(to_unsigned(C_DATA_BITS-1,
mux_sel'length));
elsif (tx_Data_Enable = '1') then
if (mux_sel_is_zero = '1') then
mux_sel <= MUX_SEL_INIT;
elsif (tx_DataBits = '1') then
mux_sel <= std_logic_vector(UNSIGNED(mux_sel) - 1);
end if;
end if;
end if;
end process COUNTER;
------------------------------------------------------------------------
-- Detecting when mux_sel is zero, i.e. all data bits are transfered
------------------------------------------------------------------------
mux_sel_is_zero <= '1' when mux_sel = "000" else '0';
--------------------------------------------------------------------------
-- FIFO_READ_DFF : Read out the next data from the transmit fifo when the
-- data has been transmitted
--------------------------------------------------------------------------
FIFO_READ_DFF : process (Clk) is
begin -- process FIFO_Read_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Read <= '0';
else
fifo_Read <= tx_Data_Enable and mux_sel_is_zero;
end if;
end if;
end process FIFO_READ_DFF;
--------------------------------------------------------------------------
-- Select which bit within the data word to transmit
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- PARITY_BIT_INSERTION : Need special treatment for inserting the parity
-- bit because of parity generation
--------------------------------------------------------------------------
data_to_transfer(0 to C_DATA_BITS-2) <= fifo_DOut(0 to C_DATA_BITS-2);
data_to_transfer(C_DATA_BITS-1) <= parity when select_Parity = '1' else
fifo_DOut(C_DATA_BITS-1);
mux_01 <= data_to_transfer(1) when mux_sel(2) = '1' else
data_to_transfer(0);
mux_23 <= data_to_transfer(3) when mux_sel(2) = '1' else
data_to_transfer(2);
--------------------------------------------------------------------------
-- DATA_BITS_IS_5 : Select total 5 data bits when C_DATA_BITS = 5
--------------------------------------------------------------------------
DATA_BITS_IS_5 : if (C_DATA_BITS = 5) generate
mux_45 <= data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_5;
--------------------------------------------------------------------------
-- DATA_BITS_IS_6 : Select total 6 data bits when C_DATA_BITS = 6
--------------------------------------------------------------------------
DATA_BITS_IS_6 : if (C_DATA_BITS = 6) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_6;
--------------------------------------------------------------------------
-- DATA_BITS_IS_7 : Select total 7 data bits when C_DATA_BITS = 7
--------------------------------------------------------------------------
DATA_BITS_IS_7 : if (C_DATA_BITS = 7) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(6);
end generate DATA_BITS_IS_7;
--------------------------------------------------------------------------
-- DATA_BITS_IS_8 : Select total 8 data bits when C_DATA_BITS = 8
--------------------------------------------------------------------------
DATA_BITS_IS_8 : if (C_DATA_BITS = 8) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(7) when mux_sel(2) = '1' else
data_to_transfer(6);
end generate DATA_BITS_IS_8;
mux_0123 <= mux_23 when mux_sel(1) = '1' else mux_01;
mux_4567 <= mux_67 when mux_sel(1) = '1' else mux_45;
mux_Out <= mux_4567 when mux_sel(0) = '1' else mux_0123;
--------------------------------------------------------------------------
-- SERIAL_DATA_DFF : Register the mux_Out
--------------------------------------------------------------------------
SERIAL_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
serial_Data <= '0';
else
serial_Data <= mux_Out;
end if;
end if;
end process SERIAL_DATA_DFF;
--------------------------------------------------------------------------
-- SERIAL_OUT_DFF :Force a '0' when tx_start is '1', Start_bit
-- Force a '1' when tx_run is '0', Idle
-- otherwise put out the serial_data
--------------------------------------------------------------------------
SERIAL_OUT_DFF : process (Clk) is
begin -- process Serial_Out_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
TX <= '1';
else
TX <= (not(tx_Run) or serial_Data) and (not(tx_Start));
end if;
end if;
end process SERIAL_OUT_DFF;
--------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
--------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (tx_Start = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (tx_Data_Enable = '1') then
parity <= parity xor serial_Data;
end if;
end if;
end process PARITY_DFF;
TX_RUN1_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Run1 <= '0';
elsif (tx_Data_Enable = '1') then
tx_Run1 <= tx_DataBits;
end if;
end if;
end process TX_RUN1_DFF;
tx_Run <= tx_Run1 or tx_DataBits;
SELECT_PARITY_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
select_Parity <= '0';
elsif (tx_Data_Enable = '1') then
select_Parity <= mux_sel_is_zero;
end if;
end if;
end process SELECT_PARITY_DFF;
end generate USING_PARITY;
--------------------------------------------------------------------------
-- NO_PARITY : When C_USE_PARITY = 0 select parity as '0'
--------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
tx_Run <= tx_DataBits;
select_Parity <= '0';
end generate NO_PARITY;
--------------------------------------------------------------------------
-- Write TX FIFO when FIFO is not full when AXI writes data in TX FIFO
--------------------------------------------------------------------------
fifo_wr <= Write_TX_FIFO and (not tx_buffer_full_i);
--------------------------------------------------------------------------
-- Read TX FIFO when FIFO is not empty when AXI reads data from TX FIFO
--------------------------------------------------------------------------
fifo_rd <= fifo_Read and (not fifo_Data_Empty);
--------------------------------------------------------------------------
-- Reset TX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
TX_FIFO_Reset <= Reset_TX_FIFO or Reset;
--------------------------------------------------------------------------
-- SRL_FIFO_I : Transmit FIFO Interface
--------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => TX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => TX_Data,
FIFO_Read => fifo_rd,
Data_Out => fifo_DOut,
FIFO_Full => tx_buffer_full_i,
FIFO_Empty => fifo_Data_Empty
);
TX_Buffer_Full <= tx_buffer_full_i;
TX_Buffer_Empty <= fifo_Data_Empty;
fifo_Data_Present <= not fifo_Data_Empty;
end architecture RTL;
|
-------------------------------------------------------------------------------
-- uartlite_tx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_tx.vhd
-- Version: v2.0
-- Description: UART Lite Transmit Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.UNSIGNED;
use IEEE.numeric_std.to_unsigned;
use IEEE.numeric_std."-";
library lib_srl_fifo_v1_0;
-- dynshreg_i_f refered from proc_common_v4_00_a
library axi_uartlite_v2_0;
-- uartlite_core refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.all;
-- srl_fifo_f refered from proc_common_v4_00_a
use lib_srl_fifo_v1_0.srl_fifo_f;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- TX -- Transmit Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Write_TX_FIFO -- Write transmit FIFO
-- Reset_TX_FIFO -- Reset transmit FIFO
-- TX_Data -- Transmit data input
-- TX_Buffer_Full -- Transmit buffer full
-- TX_Buffer_Empty -- Transmit buffer empty
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_tx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
TX : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_DATA_BITS-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic
);
end entity uartlite_tx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_tx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
-------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------
constant MUX_SEL_INIT : std_logic_vector(0 to 2) :=
std_logic_vector(to_unsigned(C_DATA_BITS-1, 3));
-------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------
signal parity : std_logic;
signal tx_Run1 : std_logic;
signal select_Parity : std_logic;
signal data_to_transfer : std_logic_vector(0 to C_DATA_BITS-1);
signal div16 : std_logic;
signal tx_Data_Enable : std_logic;
signal tx_Start : std_logic;
signal tx_DataBits : std_logic;
signal tx_Run : std_logic;
signal mux_sel : std_logic_vector(0 to 2);
signal mux_sel_is_zero : std_logic;
signal mux_01 : std_logic;
signal mux_23 : std_logic;
signal mux_45 : std_logic;
signal mux_67 : std_logic;
signal mux_0123 : std_logic;
signal mux_4567 : std_logic;
signal mux_Out : std_logic;
signal serial_Data : std_logic;
signal fifo_Read : std_logic;
signal fifo_Data_Present : std_logic := '0';
signal fifo_Data_Empty : std_logic;
signal fifo_DOut : std_logic_vector(0 to C_DATA_BITS-1);
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal tx_buffer_full_i : std_logic;
signal TX_FIFO_Reset : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
--MID_START_BIT_SRL16_I : Shift register is used to generate div16 that
-- gets shifted for 16 times(as Addr = 15) when
-- EN_16x_Baud is high.
---------------------------------------------------------------------------
MID_START_BIT_SRL16_I : entity axi_uartlite_v2_0.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_INIT_VALUE => X"8000",
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => div16,
Dout(0) => div16
);
------------------------------------------------------------------------
-- TX_DATA_ENABLE_DFF : tx_Data_Enable is '1' when div16 is 1 and
-- EN_16x_Baud is 1. It will deasserted in the
-- next clock cycle.
------------------------------------------------------------------------
TX_DATA_ENABLE_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Data_Enable <= '0';
else
if (tx_Data_Enable = '1') then
tx_Data_Enable <= '0';
elsif (EN_16x_Baud = '1') then
tx_Data_Enable <= div16;
end if;
end if;
end if;
end process TX_DATA_ENABLE_DFF;
------------------------------------------------------------------------
-- TX_START_DFF : tx_start is '1' for the start bit in a transmission
------------------------------------------------------------------------
TX_START_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Start <= '0';
else
tx_Start <= (not(tx_Run) and (tx_Start or
(fifo_Data_Present and tx_Data_Enable)));
end if;
end if;
end process TX_START_DFF;
--------------------------------------------------------------------------
-- TX_DATA_DFF : tx_DataBits is '1' during all databits transmission
--------------------------------------------------------------------------
TX_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_DataBits <= '0';
else
tx_DataBits <= (not(fifo_Read) and (tx_DataBits or
(tx_Start and tx_Data_Enable)));
end if;
end if;
end process TX_DATA_DFF;
-------------------------------------------------------------------------
-- COUNTER : If mux_sel is zero then reload with the init value else if
-- tx_DataBits = '1', decrement
-------------------------------------------------------------------------
COUNTER : process (Clk) is
begin -- process Mux_Addr_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
mux_sel <= std_logic_vector(to_unsigned(C_DATA_BITS-1,
mux_sel'length));
elsif (tx_Data_Enable = '1') then
if (mux_sel_is_zero = '1') then
mux_sel <= MUX_SEL_INIT;
elsif (tx_DataBits = '1') then
mux_sel <= std_logic_vector(UNSIGNED(mux_sel) - 1);
end if;
end if;
end if;
end process COUNTER;
------------------------------------------------------------------------
-- Detecting when mux_sel is zero, i.e. all data bits are transfered
------------------------------------------------------------------------
mux_sel_is_zero <= '1' when mux_sel = "000" else '0';
--------------------------------------------------------------------------
-- FIFO_READ_DFF : Read out the next data from the transmit fifo when the
-- data has been transmitted
--------------------------------------------------------------------------
FIFO_READ_DFF : process (Clk) is
begin -- process FIFO_Read_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Read <= '0';
else
fifo_Read <= tx_Data_Enable and mux_sel_is_zero;
end if;
end if;
end process FIFO_READ_DFF;
--------------------------------------------------------------------------
-- Select which bit within the data word to transmit
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- PARITY_BIT_INSERTION : Need special treatment for inserting the parity
-- bit because of parity generation
--------------------------------------------------------------------------
data_to_transfer(0 to C_DATA_BITS-2) <= fifo_DOut(0 to C_DATA_BITS-2);
data_to_transfer(C_DATA_BITS-1) <= parity when select_Parity = '1' else
fifo_DOut(C_DATA_BITS-1);
mux_01 <= data_to_transfer(1) when mux_sel(2) = '1' else
data_to_transfer(0);
mux_23 <= data_to_transfer(3) when mux_sel(2) = '1' else
data_to_transfer(2);
--------------------------------------------------------------------------
-- DATA_BITS_IS_5 : Select total 5 data bits when C_DATA_BITS = 5
--------------------------------------------------------------------------
DATA_BITS_IS_5 : if (C_DATA_BITS = 5) generate
mux_45 <= data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_5;
--------------------------------------------------------------------------
-- DATA_BITS_IS_6 : Select total 6 data bits when C_DATA_BITS = 6
--------------------------------------------------------------------------
DATA_BITS_IS_6 : if (C_DATA_BITS = 6) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_6;
--------------------------------------------------------------------------
-- DATA_BITS_IS_7 : Select total 7 data bits when C_DATA_BITS = 7
--------------------------------------------------------------------------
DATA_BITS_IS_7 : if (C_DATA_BITS = 7) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(6);
end generate DATA_BITS_IS_7;
--------------------------------------------------------------------------
-- DATA_BITS_IS_8 : Select total 8 data bits when C_DATA_BITS = 8
--------------------------------------------------------------------------
DATA_BITS_IS_8 : if (C_DATA_BITS = 8) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(7) when mux_sel(2) = '1' else
data_to_transfer(6);
end generate DATA_BITS_IS_8;
mux_0123 <= mux_23 when mux_sel(1) = '1' else mux_01;
mux_4567 <= mux_67 when mux_sel(1) = '1' else mux_45;
mux_Out <= mux_4567 when mux_sel(0) = '1' else mux_0123;
--------------------------------------------------------------------------
-- SERIAL_DATA_DFF : Register the mux_Out
--------------------------------------------------------------------------
SERIAL_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
serial_Data <= '0';
else
serial_Data <= mux_Out;
end if;
end if;
end process SERIAL_DATA_DFF;
--------------------------------------------------------------------------
-- SERIAL_OUT_DFF :Force a '0' when tx_start is '1', Start_bit
-- Force a '1' when tx_run is '0', Idle
-- otherwise put out the serial_data
--------------------------------------------------------------------------
SERIAL_OUT_DFF : process (Clk) is
begin -- process Serial_Out_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
TX <= '1';
else
TX <= (not(tx_Run) or serial_Data) and (not(tx_Start));
end if;
end if;
end process SERIAL_OUT_DFF;
--------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
--------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (tx_Start = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (tx_Data_Enable = '1') then
parity <= parity xor serial_Data;
end if;
end if;
end process PARITY_DFF;
TX_RUN1_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Run1 <= '0';
elsif (tx_Data_Enable = '1') then
tx_Run1 <= tx_DataBits;
end if;
end if;
end process TX_RUN1_DFF;
tx_Run <= tx_Run1 or tx_DataBits;
SELECT_PARITY_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
select_Parity <= '0';
elsif (tx_Data_Enable = '1') then
select_Parity <= mux_sel_is_zero;
end if;
end if;
end process SELECT_PARITY_DFF;
end generate USING_PARITY;
--------------------------------------------------------------------------
-- NO_PARITY : When C_USE_PARITY = 0 select parity as '0'
--------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
tx_Run <= tx_DataBits;
select_Parity <= '0';
end generate NO_PARITY;
--------------------------------------------------------------------------
-- Write TX FIFO when FIFO is not full when AXI writes data in TX FIFO
--------------------------------------------------------------------------
fifo_wr <= Write_TX_FIFO and (not tx_buffer_full_i);
--------------------------------------------------------------------------
-- Read TX FIFO when FIFO is not empty when AXI reads data from TX FIFO
--------------------------------------------------------------------------
fifo_rd <= fifo_Read and (not fifo_Data_Empty);
--------------------------------------------------------------------------
-- Reset TX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
TX_FIFO_Reset <= Reset_TX_FIFO or Reset;
--------------------------------------------------------------------------
-- SRL_FIFO_I : Transmit FIFO Interface
--------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => TX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => TX_Data,
FIFO_Read => fifo_rd,
Data_Out => fifo_DOut,
FIFO_Full => tx_buffer_full_i,
FIFO_Empty => fifo_Data_Empty
);
TX_Buffer_Full <= tx_buffer_full_i;
TX_Buffer_Empty <= fifo_Data_Empty;
fifo_Data_Present <= not fifo_Data_Empty;
end architecture RTL;
|
-------------------------------------------------------------------------------
-- uartlite_tx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_tx.vhd
-- Version: v2.0
-- Description: UART Lite Transmit Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.UNSIGNED;
use IEEE.numeric_std.to_unsigned;
use IEEE.numeric_std."-";
library lib_srl_fifo_v1_0;
-- dynshreg_i_f refered from proc_common_v4_00_a
library axi_uartlite_v2_0;
-- uartlite_core refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.all;
-- srl_fifo_f refered from proc_common_v4_00_a
use lib_srl_fifo_v1_0.srl_fifo_f;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- TX -- Transmit Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Write_TX_FIFO -- Write transmit FIFO
-- Reset_TX_FIFO -- Reset transmit FIFO
-- TX_Data -- Transmit data input
-- TX_Buffer_Full -- Transmit buffer full
-- TX_Buffer_Empty -- Transmit buffer empty
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_tx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
TX : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_DATA_BITS-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic
);
end entity uartlite_tx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_tx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
-------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------
constant MUX_SEL_INIT : std_logic_vector(0 to 2) :=
std_logic_vector(to_unsigned(C_DATA_BITS-1, 3));
-------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------
signal parity : std_logic;
signal tx_Run1 : std_logic;
signal select_Parity : std_logic;
signal data_to_transfer : std_logic_vector(0 to C_DATA_BITS-1);
signal div16 : std_logic;
signal tx_Data_Enable : std_logic;
signal tx_Start : std_logic;
signal tx_DataBits : std_logic;
signal tx_Run : std_logic;
signal mux_sel : std_logic_vector(0 to 2);
signal mux_sel_is_zero : std_logic;
signal mux_01 : std_logic;
signal mux_23 : std_logic;
signal mux_45 : std_logic;
signal mux_67 : std_logic;
signal mux_0123 : std_logic;
signal mux_4567 : std_logic;
signal mux_Out : std_logic;
signal serial_Data : std_logic;
signal fifo_Read : std_logic;
signal fifo_Data_Present : std_logic := '0';
signal fifo_Data_Empty : std_logic;
signal fifo_DOut : std_logic_vector(0 to C_DATA_BITS-1);
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal tx_buffer_full_i : std_logic;
signal TX_FIFO_Reset : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
--MID_START_BIT_SRL16_I : Shift register is used to generate div16 that
-- gets shifted for 16 times(as Addr = 15) when
-- EN_16x_Baud is high.
---------------------------------------------------------------------------
MID_START_BIT_SRL16_I : entity axi_uartlite_v2_0.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_INIT_VALUE => X"8000",
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => div16,
Dout(0) => div16
);
------------------------------------------------------------------------
-- TX_DATA_ENABLE_DFF : tx_Data_Enable is '1' when div16 is 1 and
-- EN_16x_Baud is 1. It will deasserted in the
-- next clock cycle.
------------------------------------------------------------------------
TX_DATA_ENABLE_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Data_Enable <= '0';
else
if (tx_Data_Enable = '1') then
tx_Data_Enable <= '0';
elsif (EN_16x_Baud = '1') then
tx_Data_Enable <= div16;
end if;
end if;
end if;
end process TX_DATA_ENABLE_DFF;
------------------------------------------------------------------------
-- TX_START_DFF : tx_start is '1' for the start bit in a transmission
------------------------------------------------------------------------
TX_START_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Start <= '0';
else
tx_Start <= (not(tx_Run) and (tx_Start or
(fifo_Data_Present and tx_Data_Enable)));
end if;
end if;
end process TX_START_DFF;
--------------------------------------------------------------------------
-- TX_DATA_DFF : tx_DataBits is '1' during all databits transmission
--------------------------------------------------------------------------
TX_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_DataBits <= '0';
else
tx_DataBits <= (not(fifo_Read) and (tx_DataBits or
(tx_Start and tx_Data_Enable)));
end if;
end if;
end process TX_DATA_DFF;
-------------------------------------------------------------------------
-- COUNTER : If mux_sel is zero then reload with the init value else if
-- tx_DataBits = '1', decrement
-------------------------------------------------------------------------
COUNTER : process (Clk) is
begin -- process Mux_Addr_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
mux_sel <= std_logic_vector(to_unsigned(C_DATA_BITS-1,
mux_sel'length));
elsif (tx_Data_Enable = '1') then
if (mux_sel_is_zero = '1') then
mux_sel <= MUX_SEL_INIT;
elsif (tx_DataBits = '1') then
mux_sel <= std_logic_vector(UNSIGNED(mux_sel) - 1);
end if;
end if;
end if;
end process COUNTER;
------------------------------------------------------------------------
-- Detecting when mux_sel is zero, i.e. all data bits are transfered
------------------------------------------------------------------------
mux_sel_is_zero <= '1' when mux_sel = "000" else '0';
--------------------------------------------------------------------------
-- FIFO_READ_DFF : Read out the next data from the transmit fifo when the
-- data has been transmitted
--------------------------------------------------------------------------
FIFO_READ_DFF : process (Clk) is
begin -- process FIFO_Read_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Read <= '0';
else
fifo_Read <= tx_Data_Enable and mux_sel_is_zero;
end if;
end if;
end process FIFO_READ_DFF;
--------------------------------------------------------------------------
-- Select which bit within the data word to transmit
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- PARITY_BIT_INSERTION : Need special treatment for inserting the parity
-- bit because of parity generation
--------------------------------------------------------------------------
data_to_transfer(0 to C_DATA_BITS-2) <= fifo_DOut(0 to C_DATA_BITS-2);
data_to_transfer(C_DATA_BITS-1) <= parity when select_Parity = '1' else
fifo_DOut(C_DATA_BITS-1);
mux_01 <= data_to_transfer(1) when mux_sel(2) = '1' else
data_to_transfer(0);
mux_23 <= data_to_transfer(3) when mux_sel(2) = '1' else
data_to_transfer(2);
--------------------------------------------------------------------------
-- DATA_BITS_IS_5 : Select total 5 data bits when C_DATA_BITS = 5
--------------------------------------------------------------------------
DATA_BITS_IS_5 : if (C_DATA_BITS = 5) generate
mux_45 <= data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_5;
--------------------------------------------------------------------------
-- DATA_BITS_IS_6 : Select total 6 data bits when C_DATA_BITS = 6
--------------------------------------------------------------------------
DATA_BITS_IS_6 : if (C_DATA_BITS = 6) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_6;
--------------------------------------------------------------------------
-- DATA_BITS_IS_7 : Select total 7 data bits when C_DATA_BITS = 7
--------------------------------------------------------------------------
DATA_BITS_IS_7 : if (C_DATA_BITS = 7) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(6);
end generate DATA_BITS_IS_7;
--------------------------------------------------------------------------
-- DATA_BITS_IS_8 : Select total 8 data bits when C_DATA_BITS = 8
--------------------------------------------------------------------------
DATA_BITS_IS_8 : if (C_DATA_BITS = 8) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(7) when mux_sel(2) = '1' else
data_to_transfer(6);
end generate DATA_BITS_IS_8;
mux_0123 <= mux_23 when mux_sel(1) = '1' else mux_01;
mux_4567 <= mux_67 when mux_sel(1) = '1' else mux_45;
mux_Out <= mux_4567 when mux_sel(0) = '1' else mux_0123;
--------------------------------------------------------------------------
-- SERIAL_DATA_DFF : Register the mux_Out
--------------------------------------------------------------------------
SERIAL_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
serial_Data <= '0';
else
serial_Data <= mux_Out;
end if;
end if;
end process SERIAL_DATA_DFF;
--------------------------------------------------------------------------
-- SERIAL_OUT_DFF :Force a '0' when tx_start is '1', Start_bit
-- Force a '1' when tx_run is '0', Idle
-- otherwise put out the serial_data
--------------------------------------------------------------------------
SERIAL_OUT_DFF : process (Clk) is
begin -- process Serial_Out_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
TX <= '1';
else
TX <= (not(tx_Run) or serial_Data) and (not(tx_Start));
end if;
end if;
end process SERIAL_OUT_DFF;
--------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
--------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (tx_Start = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (tx_Data_Enable = '1') then
parity <= parity xor serial_Data;
end if;
end if;
end process PARITY_DFF;
TX_RUN1_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Run1 <= '0';
elsif (tx_Data_Enable = '1') then
tx_Run1 <= tx_DataBits;
end if;
end if;
end process TX_RUN1_DFF;
tx_Run <= tx_Run1 or tx_DataBits;
SELECT_PARITY_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
select_Parity <= '0';
elsif (tx_Data_Enable = '1') then
select_Parity <= mux_sel_is_zero;
end if;
end if;
end process SELECT_PARITY_DFF;
end generate USING_PARITY;
--------------------------------------------------------------------------
-- NO_PARITY : When C_USE_PARITY = 0 select parity as '0'
--------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
tx_Run <= tx_DataBits;
select_Parity <= '0';
end generate NO_PARITY;
--------------------------------------------------------------------------
-- Write TX FIFO when FIFO is not full when AXI writes data in TX FIFO
--------------------------------------------------------------------------
fifo_wr <= Write_TX_FIFO and (not tx_buffer_full_i);
--------------------------------------------------------------------------
-- Read TX FIFO when FIFO is not empty when AXI reads data from TX FIFO
--------------------------------------------------------------------------
fifo_rd <= fifo_Read and (not fifo_Data_Empty);
--------------------------------------------------------------------------
-- Reset TX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
TX_FIFO_Reset <= Reset_TX_FIFO or Reset;
--------------------------------------------------------------------------
-- SRL_FIFO_I : Transmit FIFO Interface
--------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => TX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => TX_Data,
FIFO_Read => fifo_rd,
Data_Out => fifo_DOut,
FIFO_Full => tx_buffer_full_i,
FIFO_Empty => fifo_Data_Empty
);
TX_Buffer_Full <= tx_buffer_full_i;
TX_Buffer_Empty <= fifo_Data_Empty;
fifo_Data_Present <= not fifo_Data_Empty;
end architecture RTL;
|
-------------------------------------------------------------------------------
-- uartlite_tx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_tx.vhd
-- Version: v2.0
-- Description: UART Lite Transmit Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.UNSIGNED;
use IEEE.numeric_std.to_unsigned;
use IEEE.numeric_std."-";
library lib_srl_fifo_v1_0;
-- dynshreg_i_f refered from proc_common_v4_00_a
library axi_uartlite_v2_0;
-- uartlite_core refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.all;
-- srl_fifo_f refered from proc_common_v4_00_a
use lib_srl_fifo_v1_0.srl_fifo_f;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- TX -- Transmit Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Write_TX_FIFO -- Write transmit FIFO
-- Reset_TX_FIFO -- Reset transmit FIFO
-- TX_Data -- Transmit data input
-- TX_Buffer_Full -- Transmit buffer full
-- TX_Buffer_Empty -- Transmit buffer empty
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_tx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
TX : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_DATA_BITS-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic
);
end entity uartlite_tx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_tx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
-------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------
constant MUX_SEL_INIT : std_logic_vector(0 to 2) :=
std_logic_vector(to_unsigned(C_DATA_BITS-1, 3));
-------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------
signal parity : std_logic;
signal tx_Run1 : std_logic;
signal select_Parity : std_logic;
signal data_to_transfer : std_logic_vector(0 to C_DATA_BITS-1);
signal div16 : std_logic;
signal tx_Data_Enable : std_logic;
signal tx_Start : std_logic;
signal tx_DataBits : std_logic;
signal tx_Run : std_logic;
signal mux_sel : std_logic_vector(0 to 2);
signal mux_sel_is_zero : std_logic;
signal mux_01 : std_logic;
signal mux_23 : std_logic;
signal mux_45 : std_logic;
signal mux_67 : std_logic;
signal mux_0123 : std_logic;
signal mux_4567 : std_logic;
signal mux_Out : std_logic;
signal serial_Data : std_logic;
signal fifo_Read : std_logic;
signal fifo_Data_Present : std_logic := '0';
signal fifo_Data_Empty : std_logic;
signal fifo_DOut : std_logic_vector(0 to C_DATA_BITS-1);
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal tx_buffer_full_i : std_logic;
signal TX_FIFO_Reset : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
--MID_START_BIT_SRL16_I : Shift register is used to generate div16 that
-- gets shifted for 16 times(as Addr = 15) when
-- EN_16x_Baud is high.
---------------------------------------------------------------------------
MID_START_BIT_SRL16_I : entity axi_uartlite_v2_0.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_INIT_VALUE => X"8000",
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => div16,
Dout(0) => div16
);
------------------------------------------------------------------------
-- TX_DATA_ENABLE_DFF : tx_Data_Enable is '1' when div16 is 1 and
-- EN_16x_Baud is 1. It will deasserted in the
-- next clock cycle.
------------------------------------------------------------------------
TX_DATA_ENABLE_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Data_Enable <= '0';
else
if (tx_Data_Enable = '1') then
tx_Data_Enable <= '0';
elsif (EN_16x_Baud = '1') then
tx_Data_Enable <= div16;
end if;
end if;
end if;
end process TX_DATA_ENABLE_DFF;
------------------------------------------------------------------------
-- TX_START_DFF : tx_start is '1' for the start bit in a transmission
------------------------------------------------------------------------
TX_START_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Start <= '0';
else
tx_Start <= (not(tx_Run) and (tx_Start or
(fifo_Data_Present and tx_Data_Enable)));
end if;
end if;
end process TX_START_DFF;
--------------------------------------------------------------------------
-- TX_DATA_DFF : tx_DataBits is '1' during all databits transmission
--------------------------------------------------------------------------
TX_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_DataBits <= '0';
else
tx_DataBits <= (not(fifo_Read) and (tx_DataBits or
(tx_Start and tx_Data_Enable)));
end if;
end if;
end process TX_DATA_DFF;
-------------------------------------------------------------------------
-- COUNTER : If mux_sel is zero then reload with the init value else if
-- tx_DataBits = '1', decrement
-------------------------------------------------------------------------
COUNTER : process (Clk) is
begin -- process Mux_Addr_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
mux_sel <= std_logic_vector(to_unsigned(C_DATA_BITS-1,
mux_sel'length));
elsif (tx_Data_Enable = '1') then
if (mux_sel_is_zero = '1') then
mux_sel <= MUX_SEL_INIT;
elsif (tx_DataBits = '1') then
mux_sel <= std_logic_vector(UNSIGNED(mux_sel) - 1);
end if;
end if;
end if;
end process COUNTER;
------------------------------------------------------------------------
-- Detecting when mux_sel is zero, i.e. all data bits are transfered
------------------------------------------------------------------------
mux_sel_is_zero <= '1' when mux_sel = "000" else '0';
--------------------------------------------------------------------------
-- FIFO_READ_DFF : Read out the next data from the transmit fifo when the
-- data has been transmitted
--------------------------------------------------------------------------
FIFO_READ_DFF : process (Clk) is
begin -- process FIFO_Read_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Read <= '0';
else
fifo_Read <= tx_Data_Enable and mux_sel_is_zero;
end if;
end if;
end process FIFO_READ_DFF;
--------------------------------------------------------------------------
-- Select which bit within the data word to transmit
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- PARITY_BIT_INSERTION : Need special treatment for inserting the parity
-- bit because of parity generation
--------------------------------------------------------------------------
data_to_transfer(0 to C_DATA_BITS-2) <= fifo_DOut(0 to C_DATA_BITS-2);
data_to_transfer(C_DATA_BITS-1) <= parity when select_Parity = '1' else
fifo_DOut(C_DATA_BITS-1);
mux_01 <= data_to_transfer(1) when mux_sel(2) = '1' else
data_to_transfer(0);
mux_23 <= data_to_transfer(3) when mux_sel(2) = '1' else
data_to_transfer(2);
--------------------------------------------------------------------------
-- DATA_BITS_IS_5 : Select total 5 data bits when C_DATA_BITS = 5
--------------------------------------------------------------------------
DATA_BITS_IS_5 : if (C_DATA_BITS = 5) generate
mux_45 <= data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_5;
--------------------------------------------------------------------------
-- DATA_BITS_IS_6 : Select total 6 data bits when C_DATA_BITS = 6
--------------------------------------------------------------------------
DATA_BITS_IS_6 : if (C_DATA_BITS = 6) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_6;
--------------------------------------------------------------------------
-- DATA_BITS_IS_7 : Select total 7 data bits when C_DATA_BITS = 7
--------------------------------------------------------------------------
DATA_BITS_IS_7 : if (C_DATA_BITS = 7) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(6);
end generate DATA_BITS_IS_7;
--------------------------------------------------------------------------
-- DATA_BITS_IS_8 : Select total 8 data bits when C_DATA_BITS = 8
--------------------------------------------------------------------------
DATA_BITS_IS_8 : if (C_DATA_BITS = 8) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(7) when mux_sel(2) = '1' else
data_to_transfer(6);
end generate DATA_BITS_IS_8;
mux_0123 <= mux_23 when mux_sel(1) = '1' else mux_01;
mux_4567 <= mux_67 when mux_sel(1) = '1' else mux_45;
mux_Out <= mux_4567 when mux_sel(0) = '1' else mux_0123;
--------------------------------------------------------------------------
-- SERIAL_DATA_DFF : Register the mux_Out
--------------------------------------------------------------------------
SERIAL_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
serial_Data <= '0';
else
serial_Data <= mux_Out;
end if;
end if;
end process SERIAL_DATA_DFF;
--------------------------------------------------------------------------
-- SERIAL_OUT_DFF :Force a '0' when tx_start is '1', Start_bit
-- Force a '1' when tx_run is '0', Idle
-- otherwise put out the serial_data
--------------------------------------------------------------------------
SERIAL_OUT_DFF : process (Clk) is
begin -- process Serial_Out_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
TX <= '1';
else
TX <= (not(tx_Run) or serial_Data) and (not(tx_Start));
end if;
end if;
end process SERIAL_OUT_DFF;
--------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
--------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (tx_Start = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (tx_Data_Enable = '1') then
parity <= parity xor serial_Data;
end if;
end if;
end process PARITY_DFF;
TX_RUN1_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Run1 <= '0';
elsif (tx_Data_Enable = '1') then
tx_Run1 <= tx_DataBits;
end if;
end if;
end process TX_RUN1_DFF;
tx_Run <= tx_Run1 or tx_DataBits;
SELECT_PARITY_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
select_Parity <= '0';
elsif (tx_Data_Enable = '1') then
select_Parity <= mux_sel_is_zero;
end if;
end if;
end process SELECT_PARITY_DFF;
end generate USING_PARITY;
--------------------------------------------------------------------------
-- NO_PARITY : When C_USE_PARITY = 0 select parity as '0'
--------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
tx_Run <= tx_DataBits;
select_Parity <= '0';
end generate NO_PARITY;
--------------------------------------------------------------------------
-- Write TX FIFO when FIFO is not full when AXI writes data in TX FIFO
--------------------------------------------------------------------------
fifo_wr <= Write_TX_FIFO and (not tx_buffer_full_i);
--------------------------------------------------------------------------
-- Read TX FIFO when FIFO is not empty when AXI reads data from TX FIFO
--------------------------------------------------------------------------
fifo_rd <= fifo_Read and (not fifo_Data_Empty);
--------------------------------------------------------------------------
-- Reset TX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
TX_FIFO_Reset <= Reset_TX_FIFO or Reset;
--------------------------------------------------------------------------
-- SRL_FIFO_I : Transmit FIFO Interface
--------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => TX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => TX_Data,
FIFO_Read => fifo_rd,
Data_Out => fifo_DOut,
FIFO_Full => tx_buffer_full_i,
FIFO_Empty => fifo_Data_Empty
);
TX_Buffer_Full <= tx_buffer_full_i;
TX_Buffer_Empty <= fifo_Data_Empty;
fifo_Data_Present <= not fifo_Data_Empty;
end architecture RTL;
|
-------------------------------------------------------------------------------
-- uartlite_tx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_tx.vhd
-- Version: v2.0
-- Description: UART Lite Transmit Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.UNSIGNED;
use IEEE.numeric_std.to_unsigned;
use IEEE.numeric_std."-";
library lib_srl_fifo_v1_0;
-- dynshreg_i_f refered from proc_common_v4_00_a
library axi_uartlite_v2_0;
-- uartlite_core refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.all;
-- srl_fifo_f refered from proc_common_v4_00_a
use lib_srl_fifo_v1_0.srl_fifo_f;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- TX -- Transmit Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Write_TX_FIFO -- Write transmit FIFO
-- Reset_TX_FIFO -- Reset transmit FIFO
-- TX_Data -- Transmit data input
-- TX_Buffer_Full -- Transmit buffer full
-- TX_Buffer_Empty -- Transmit buffer empty
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_tx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
TX : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_DATA_BITS-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic
);
end entity uartlite_tx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_tx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
-------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------
constant MUX_SEL_INIT : std_logic_vector(0 to 2) :=
std_logic_vector(to_unsigned(C_DATA_BITS-1, 3));
-------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------
signal parity : std_logic;
signal tx_Run1 : std_logic;
signal select_Parity : std_logic;
signal data_to_transfer : std_logic_vector(0 to C_DATA_BITS-1);
signal div16 : std_logic;
signal tx_Data_Enable : std_logic;
signal tx_Start : std_logic;
signal tx_DataBits : std_logic;
signal tx_Run : std_logic;
signal mux_sel : std_logic_vector(0 to 2);
signal mux_sel_is_zero : std_logic;
signal mux_01 : std_logic;
signal mux_23 : std_logic;
signal mux_45 : std_logic;
signal mux_67 : std_logic;
signal mux_0123 : std_logic;
signal mux_4567 : std_logic;
signal mux_Out : std_logic;
signal serial_Data : std_logic;
signal fifo_Read : std_logic;
signal fifo_Data_Present : std_logic := '0';
signal fifo_Data_Empty : std_logic;
signal fifo_DOut : std_logic_vector(0 to C_DATA_BITS-1);
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal tx_buffer_full_i : std_logic;
signal TX_FIFO_Reset : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
--MID_START_BIT_SRL16_I : Shift register is used to generate div16 that
-- gets shifted for 16 times(as Addr = 15) when
-- EN_16x_Baud is high.
---------------------------------------------------------------------------
MID_START_BIT_SRL16_I : entity axi_uartlite_v2_0.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_INIT_VALUE => X"8000",
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => div16,
Dout(0) => div16
);
------------------------------------------------------------------------
-- TX_DATA_ENABLE_DFF : tx_Data_Enable is '1' when div16 is 1 and
-- EN_16x_Baud is 1. It will deasserted in the
-- next clock cycle.
------------------------------------------------------------------------
TX_DATA_ENABLE_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Data_Enable <= '0';
else
if (tx_Data_Enable = '1') then
tx_Data_Enable <= '0';
elsif (EN_16x_Baud = '1') then
tx_Data_Enable <= div16;
end if;
end if;
end if;
end process TX_DATA_ENABLE_DFF;
------------------------------------------------------------------------
-- TX_START_DFF : tx_start is '1' for the start bit in a transmission
------------------------------------------------------------------------
TX_START_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Start <= '0';
else
tx_Start <= (not(tx_Run) and (tx_Start or
(fifo_Data_Present and tx_Data_Enable)));
end if;
end if;
end process TX_START_DFF;
--------------------------------------------------------------------------
-- TX_DATA_DFF : tx_DataBits is '1' during all databits transmission
--------------------------------------------------------------------------
TX_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_DataBits <= '0';
else
tx_DataBits <= (not(fifo_Read) and (tx_DataBits or
(tx_Start and tx_Data_Enable)));
end if;
end if;
end process TX_DATA_DFF;
-------------------------------------------------------------------------
-- COUNTER : If mux_sel is zero then reload with the init value else if
-- tx_DataBits = '1', decrement
-------------------------------------------------------------------------
COUNTER : process (Clk) is
begin -- process Mux_Addr_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
mux_sel <= std_logic_vector(to_unsigned(C_DATA_BITS-1,
mux_sel'length));
elsif (tx_Data_Enable = '1') then
if (mux_sel_is_zero = '1') then
mux_sel <= MUX_SEL_INIT;
elsif (tx_DataBits = '1') then
mux_sel <= std_logic_vector(UNSIGNED(mux_sel) - 1);
end if;
end if;
end if;
end process COUNTER;
------------------------------------------------------------------------
-- Detecting when mux_sel is zero, i.e. all data bits are transfered
------------------------------------------------------------------------
mux_sel_is_zero <= '1' when mux_sel = "000" else '0';
--------------------------------------------------------------------------
-- FIFO_READ_DFF : Read out the next data from the transmit fifo when the
-- data has been transmitted
--------------------------------------------------------------------------
FIFO_READ_DFF : process (Clk) is
begin -- process FIFO_Read_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Read <= '0';
else
fifo_Read <= tx_Data_Enable and mux_sel_is_zero;
end if;
end if;
end process FIFO_READ_DFF;
--------------------------------------------------------------------------
-- Select which bit within the data word to transmit
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- PARITY_BIT_INSERTION : Need special treatment for inserting the parity
-- bit because of parity generation
--------------------------------------------------------------------------
data_to_transfer(0 to C_DATA_BITS-2) <= fifo_DOut(0 to C_DATA_BITS-2);
data_to_transfer(C_DATA_BITS-1) <= parity when select_Parity = '1' else
fifo_DOut(C_DATA_BITS-1);
mux_01 <= data_to_transfer(1) when mux_sel(2) = '1' else
data_to_transfer(0);
mux_23 <= data_to_transfer(3) when mux_sel(2) = '1' else
data_to_transfer(2);
--------------------------------------------------------------------------
-- DATA_BITS_IS_5 : Select total 5 data bits when C_DATA_BITS = 5
--------------------------------------------------------------------------
DATA_BITS_IS_5 : if (C_DATA_BITS = 5) generate
mux_45 <= data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_5;
--------------------------------------------------------------------------
-- DATA_BITS_IS_6 : Select total 6 data bits when C_DATA_BITS = 6
--------------------------------------------------------------------------
DATA_BITS_IS_6 : if (C_DATA_BITS = 6) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_6;
--------------------------------------------------------------------------
-- DATA_BITS_IS_7 : Select total 7 data bits when C_DATA_BITS = 7
--------------------------------------------------------------------------
DATA_BITS_IS_7 : if (C_DATA_BITS = 7) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(6);
end generate DATA_BITS_IS_7;
--------------------------------------------------------------------------
-- DATA_BITS_IS_8 : Select total 8 data bits when C_DATA_BITS = 8
--------------------------------------------------------------------------
DATA_BITS_IS_8 : if (C_DATA_BITS = 8) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(7) when mux_sel(2) = '1' else
data_to_transfer(6);
end generate DATA_BITS_IS_8;
mux_0123 <= mux_23 when mux_sel(1) = '1' else mux_01;
mux_4567 <= mux_67 when mux_sel(1) = '1' else mux_45;
mux_Out <= mux_4567 when mux_sel(0) = '1' else mux_0123;
--------------------------------------------------------------------------
-- SERIAL_DATA_DFF : Register the mux_Out
--------------------------------------------------------------------------
SERIAL_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
serial_Data <= '0';
else
serial_Data <= mux_Out;
end if;
end if;
end process SERIAL_DATA_DFF;
--------------------------------------------------------------------------
-- SERIAL_OUT_DFF :Force a '0' when tx_start is '1', Start_bit
-- Force a '1' when tx_run is '0', Idle
-- otherwise put out the serial_data
--------------------------------------------------------------------------
SERIAL_OUT_DFF : process (Clk) is
begin -- process Serial_Out_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
TX <= '1';
else
TX <= (not(tx_Run) or serial_Data) and (not(tx_Start));
end if;
end if;
end process SERIAL_OUT_DFF;
--------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
--------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (tx_Start = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (tx_Data_Enable = '1') then
parity <= parity xor serial_Data;
end if;
end if;
end process PARITY_DFF;
TX_RUN1_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Run1 <= '0';
elsif (tx_Data_Enable = '1') then
tx_Run1 <= tx_DataBits;
end if;
end if;
end process TX_RUN1_DFF;
tx_Run <= tx_Run1 or tx_DataBits;
SELECT_PARITY_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
select_Parity <= '0';
elsif (tx_Data_Enable = '1') then
select_Parity <= mux_sel_is_zero;
end if;
end if;
end process SELECT_PARITY_DFF;
end generate USING_PARITY;
--------------------------------------------------------------------------
-- NO_PARITY : When C_USE_PARITY = 0 select parity as '0'
--------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
tx_Run <= tx_DataBits;
select_Parity <= '0';
end generate NO_PARITY;
--------------------------------------------------------------------------
-- Write TX FIFO when FIFO is not full when AXI writes data in TX FIFO
--------------------------------------------------------------------------
fifo_wr <= Write_TX_FIFO and (not tx_buffer_full_i);
--------------------------------------------------------------------------
-- Read TX FIFO when FIFO is not empty when AXI reads data from TX FIFO
--------------------------------------------------------------------------
fifo_rd <= fifo_Read and (not fifo_Data_Empty);
--------------------------------------------------------------------------
-- Reset TX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
TX_FIFO_Reset <= Reset_TX_FIFO or Reset;
--------------------------------------------------------------------------
-- SRL_FIFO_I : Transmit FIFO Interface
--------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => TX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => TX_Data,
FIFO_Read => fifo_rd,
Data_Out => fifo_DOut,
FIFO_Full => tx_buffer_full_i,
FIFO_Empty => fifo_Data_Empty
);
TX_Buffer_Full <= tx_buffer_full_i;
TX_Buffer_Empty <= fifo_Data_Empty;
fifo_Data_Present <= not fifo_Data_Empty;
end architecture RTL;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity debounce is
generic(
CNT : integer := 1500000; -- 30 ms at 50 MHz
CNT_WDT : integer := 21
);
port(
clk_50 : in std_logic;
input : in std_logic;
output : out std_logic;
riseedge : out std_logic;
falledge : out std_logic
);
end debounce;
architecture behavioural of debounce is
signal scnt : unsigned(CNT_WDT-1 downto 0) := (others => '0');
signal values : std_logic_vector(3 downto 0) := (others => '0');
signal io_out : std_logic;
signal io_out_dly : std_logic;
begin
io_out <= '1' when values(2 downto 0) = "111" else
'0';
output <= io_out;
riseedge <= io_out and (not io_out_dly);
falledge <= (not io_out) and io_out_dly;
io_dly: process(clk_50)
begin
if rising_edge(clk_50) then
io_out_dly <= io_out;
end if;
end process;
shift_in: process(clk_50, scnt)
begin
if rising_edge(clk_50) and scnt = CNT then
values <= input & values(3 downto 1);
end if;
end process;
delay_cnt : process(clk_50)
begin
if rising_edge(clk_50) then
if scnt = CNT then
scnt <= (others=>'0');
else
scnt <= scnt + 1;
end if;
end if;
end process;
end behavioural;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
-- Title : Flat Memory Model package
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This package implements a memory model that can be used
-- as or in bus functional models. It implements different
-- banks, such that only one package is needed for all memories
-- in the whole project. These banks are dynamic, just like
-- the contents of the memories. Internally, this memory model
-- is 32-bit, but can be accessed by means of functions and
-- procedures that exist in various widths.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
use work.tl_string_util_pkg.all;
package tl_flat_memory_model_pkg is
constant c_fm_max_bank : integer := 255;
constant c_fm_max_sector : integer := 65535;
constant c_fm_sector_size : integer := 16384;
subtype t_byte is std_logic_vector(7 downto 0);
type flat_mem_sector_t is array(0 to c_fm_sector_size-1) of integer; -- each sector is 64kB
type flat_mem_sector_p is access flat_mem_sector_t;
type flat_mem_bank_t is array(0 to c_fm_max_sector) of flat_mem_sector_p; -- there are 64k sectors (4 GB)
type flat_mem_bank_p is access flat_mem_bank_t;
-- we need to use a handle rather than a pointer, because we can't pass pointers in function calls
-- Hence, we don't use a linked list, but an array.
type flat_mem_object_t is record
path : string(1 to 256);
name : string(1 to 128);
bank : flat_mem_bank_p;
end record;
type flat_mem_object_p is access flat_mem_object_t;
type flat_mem_array_t is array(1 to c_fm_max_bank) of flat_mem_object_p;
subtype h_mem_object is integer range 0 to c_fm_max_bank;
---------------------------------------------------------------------------
shared variable flat_memories : flat_mem_array_t := (others => null);
---------------------------------------------------------------------------
procedure register_mem_model(
path : string;
named : string;
variable handle : out h_mem_object);
procedure bind_mem_model (
named : string;
variable handle : out h_mem_object);
---------------------------------------------------------------------------
-- Low level calls
impure function read_memory(
bank : integer;
sector : integer;
entry : integer)
return integer;
procedure write_memory(
bank : integer;
sector : integer;
entry : integer;
data : integer);
procedure clear_memory(
bank : integer);
procedure clean_up;
-- 32-bit address/data access calls
impure function read_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0));
procedure write_memory_be(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0));
-- 16-bit address/data access calls
impure function read_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(15 downto 0));
-- 8-bit address/data access calls
impure function read_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(7 downto 0));
-- integer direct access calls
impure function read_memory_int(
bank : integer;
address : integer )
return integer;
procedure write_memory_int(
bank : integer;
address : integer;
data : integer );
-- File Access Procedures
procedure load_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0));
procedure save_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer);
procedure load_memory_hex(
filename : string;
bank : integer);
procedure save_memory_hex(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer);
end package;
package body tl_flat_memory_model_pkg is
-- Memory model module registration into array
procedure register_mem_model(
path : string;
named : string;
variable handle : out h_mem_object) is
begin
handle := 0;
L1 : for i in flat_memories'range loop
if flat_memories(i) = null then
-- report "my name is "& named;
handle := i;
flat_memories(i) := new flat_mem_object_t;
flat_memories(i).path(path'range) := path;
flat_memories(i).name(named'range) := named;
flat_memories(i).bank := new flat_mem_bank_t;
exit L1;
end if;
end loop;
end procedure register_mem_model;
-- Memory model module binding
procedure bind_mem_model (
named : string;
variable handle : out h_mem_object) is
begin
handle := 0;
wait for 1 ns;
L1 : for i in flat_memories'range loop
if flat_memories(i) /= null then
if flat_memories(i).name(named'range) = named or
flat_memories(i).path(named'range) = named then
handle := i;
return;
end if;
end if;
end loop;
report "Can't find memory model '"&named&"'."
severity failure;
end procedure bind_mem_model;
-- Base calls
impure function read_memory(
bank : integer;
sector : integer;
entry : integer) return integer is
begin
if flat_memories(bank) = null then
return 0;
end if;
if flat_memories(bank).bank(sector) = null then
return 0;
end if;
return flat_memories(bank).bank(sector).all(entry);
end function read_memory;
procedure write_memory(
bank : integer;
sector : integer;
entry : integer;
data : integer) is
begin
if flat_memories(bank) = null then
flat_memories(bank) := new flat_mem_object_t;
flat_memories(bank).bank(0 to c_fm_max_sector) := (others => null);
end if;
if flat_memories(bank).bank(sector) = null then
flat_memories(bank).bank(sector) := new flat_mem_sector_t;
flat_memories(bank).bank(sector).all(0 to c_fm_sector_size-1) := (others => 0);
end if;
flat_memories(bank).bank(sector).all(entry) := data;
end procedure write_memory;
procedure clear_memory(bank : integer) is
begin
if flat_memories(bank) /= null then
for i in flat_memories(bank).bank'range loop
if flat_memories(bank).bank(i) /= null then
deallocate(flat_memories(bank).bank(i));
end if;
end loop;
deallocate(flat_memories(bank));
flat_memories(bank) := null;
end if;
end procedure clear_memory;
procedure clean_up is
begin
for i in flat_memories'range loop
clear_memory(i);
end loop;
end procedure clean_up;
-- 32-bit address/data access calls
impure function read_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
return std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
end function read_memory_32;
procedure write_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0))
is
variable sector_idx : integer;
variable entry_idx : integer;
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
write_memory(bank, sector_idx, entry_idx, to_integer(signed(data)));
end procedure write_memory_32;
procedure write_memory_be(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0))
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
begin
--write_s(L, "Writing " & vec_to_hex(data, 8) & " to location " & vec_to_hex(address, 8));
--writeline(output, L);
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
for i in be'range loop
if to_x01(be(i)) = '1' then
read_data(7+8*i downto 8*i) := data(7+8*i downto 8*i);
end if;
end loop;
write_memory(bank, sector_idx, entry_idx, to_integer(signed(read_data)));
end procedure write_memory_be;
-- 16-bit address/data access calls
impure function read_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
if address(1) = '0' then
return read_data(15 downto 0);
else
return read_data(31 downto 16);
end if;
end function read_memory_16;
procedure write_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(15 downto 0))
is
variable be_temp : std_logic_vector(3 downto 0);
variable write_data : std_logic_vector(31 downto 0);
begin
write_data := data & data;
be_temp := address(1) & address(1) & not address(1) & not address(1);
write_memory_be(bank, address, write_data, be_temp);
end procedure write_memory_16;
-- 8-bit address/data access calls
impure function read_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
case address(1 downto 0) is
when "11" =>
return read_data(31 downto 24);
when "01" =>
return read_data(15 downto 8);
when "10" =>
return read_data(23 downto 16);
when others =>
return read_data(7 downto 0);
end case;
end function read_memory_8;
procedure write_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(7 downto 0))
is
variable be_temp : std_logic_vector(3 downto 0) := (others => '0');
variable write_data : std_logic_vector(31 downto 0);
begin
write_data := data & data & data & data;
be_temp(to_integer(unsigned(address(1 downto 0)))) := '1';
write_memory_be(bank, address, write_data, be_temp);
end procedure write_memory_8;
-- Integer direct procedures
impure function read_memory_int(
bank : integer;
address : integer )
return integer is
variable sect, index : integer;
begin
sect := address / c_fm_sector_size;
index := address mod c_fm_sector_size;
return read_memory(bank, sect, index);
end function read_memory_int;
procedure write_memory_int(
bank : integer;
address : integer;
data : integer ) is
variable sect, index : integer;
begin
sect := address / c_fm_sector_size;
index := address mod c_fm_sector_size;
write_memory(bank, sect, index, data);
end procedure write_memory_int;
-- File access procedures
-- not a public procedure.
procedure read_binary_file(
file myfile : t_binary_file;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
variable myrec : inout t_binary_file_rec)
is
variable addr : unsigned(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable i : integer;
variable sector_idx : integer;
variable entry_idx : integer;
begin
addr := unsigned(startaddr);
if startaddr(1 downto 0) = "00" then
sector_idx := to_integer(addr(31 downto 16));
entry_idx := to_integer(addr(15 downto 2));
aligned : while true loop
if EndFile(myfile) then
exit aligned;
end if;
read(myfile, i);
write_memory(bank, sector_idx, entry_idx, i);
if entry_idx = c_fm_sector_size-1 then
entry_idx := 0;
if sector_idx = c_fm_max_sector then
sector_idx := 0;
else
sector_idx := sector_idx + 1;
end if;
else
entry_idx := entry_idx + 1;
end if;
end loop;
else
unaligned : while true loop
if EndFile(myfile) and myrec.Offset = 0 then
exit unaligned;
end if;
read_byte(myfile, data, myrec);
write_memory_8(bank, std_logic_vector(addr), data);
--report "Writing " & hstr(data) & " to " & hstr(addr);
addr := addr + 1;
end loop;
end if;
end read_binary_file;
-- not a public procedure
procedure read_hex_file (
file myfile : text;
bank : integer)
is
variable L : line;
variable addr : unsigned(31 downto 0) := (others => '0');
variable c : character;
variable data : t_byte;
variable sum : unsigned(7 downto 0);
variable rectype : t_byte;
variable tmp_addr : std_logic_vector(15 downto 0);
variable fileend : boolean;
variable linenr : integer := 0;
variable len : integer;
begin
outer : while true loop
if EndFile(myfile) then
report "Missing end of file record."
severity warning;
return;
end if;
-- search for lines starting with ':'
start : while true loop
readline(myfile, L);
linenr := linenr + 1;
read(L, c);
if c = ':' then
exit start;
end if;
end loop;
-- parse the rest of the line
sum := X"00";
get_byte_from_file(myfile, L, fileend, data);
len := to_integer(unsigned(data));
get_byte_from_file(myfile, L, fileend, tmp_addr(15 downto 8));
get_byte_from_file(myfile, L, fileend, tmp_addr(7 downto 0));
get_byte_from_file(myfile, L, fileend, rectype);
sum := sum - (unsigned(data) + unsigned(tmp_addr(15 downto 8)) + unsigned(tmp_addr(7 downto 0)) + unsigned(rectype));
case rectype is
when X"00" => -- data record
addr(15 downto 0) := unsigned(tmp_addr);
for i in 0 to len-1 loop
get_byte_from_file(myfile, L, fileend, data);
sum := sum - unsigned(data);
write_memory_8(bank, std_logic_vector(addr), data);
addr := addr + 1;
end loop;
when X"01" => -- end of file record
return;
when X"04" => -- extended linear address record
get_byte_from_file(myfile, L, fileend, data);
addr(31 downto 24) := unsigned(data);
sum := sum - addr(31 downto 24);
get_byte_from_file(myfile, L, fileend, data);
addr(23 downto 16) := unsigned(data);
sum := sum - addr(23 downto 16);
when others =>
report "Unexpected record type " & vec_to_hex(rectype, 2)
severity warning;
return;
end case;
-- check checksum
get_byte_from_file(myfile, L, fileend, data);
assert sum = unsigned(data)
report "Warning: Checksum incorrect at line: " & integer'image(linenr)
severity warning;
end loop;
end read_hex_file;
-- public procedure:
procedure load_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0))
is
variable stat : file_open_status;
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
begin
-- open file
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
init_record(myrec);
read_binary_file (myfile, bank, address, myrec);
file_close(myfile);
end load_memory;
-- public procedure:
procedure load_memory_hex(
filename : string;
bank : integer)
is
variable stat : file_open_status;
file myfile : text;
begin
-- open file
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file (myfile, bank);
file_close(myfile);
end load_memory_hex;
-- not a public procedure.
procedure write_binary_file(
file myfile : t_binary_file;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
length : integer;
variable myrec : inout t_binary_file_rec)
is
variable addr : unsigned(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable i : integer;
variable sector_idx : integer;
variable entry_idx : integer;
variable remaining : integer;
begin
addr := unsigned(startaddr);
if startaddr(1 downto 0) = "00" then
sector_idx := to_integer(addr(31 downto 16));
entry_idx := to_integer(addr(15 downto 2));
remaining := (length + 3) / 4;
aligned : while remaining > 0 loop
i := read_memory(bank, sector_idx, entry_idx);
write(myfile, i);
remaining := remaining - 1;
if entry_idx = c_fm_sector_size-1 then
if sector_idx = c_fm_max_sector then
sector_idx := 0;
else
sector_idx := sector_idx + 1;
end if;
else
entry_idx := entry_idx + 1;
end if;
end loop;
else
remaining := length;
unaligned : while remaining > 0 loop
data := read_memory_8(bank, std_logic_vector(addr));
write_byte(myfile, data, myrec);
addr := addr + 1;
remaining := remaining - 1;
end loop;
purge(myfile, myrec);
end if;
end write_binary_file;
-- not a public procedure.
procedure write_hex_file(
file myfile : text;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
length : integer)
is
variable addr : std_logic_vector(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable remaining : integer;
variable maxlen : integer;
variable sum : unsigned(7 downto 0);
variable L : line;
variable prev_hi : std_logic_vector(31 downto 16) := (others => '-');
begin
addr := startaddr;
remaining := length;
unaligned : while remaining > 0 loop
-- check if we need to write a new extended address record
if addr(31 downto 16) /= prev_hi then
write_string(L, ":02000004");
write(L, vec_to_hex(addr(31 downto 16), 4));
write(L, vec_to_hex(std_logic_vector(X"FA" - unsigned(addr(31 downto 24)) - unsigned(addr(23 downto 16))), 2));
writeline(myfile, L);
prev_hi := addr(31 downto 16);
end if;
-- check for maximum length (until 64k boundary)
maxlen := 65536 - to_integer(unsigned(addr(15 downto 0)));
if maxlen > 16 then maxlen := 16; end if;
-- create data record
sum := X"00";
write(L, ':');
write(L, vec_to_hex(std_logic_vector(to_unsigned(maxlen, 8)), 2));
write(L, vec_to_hex(addr(15 downto 0), 4));
write_string(L, "00");
sum := sum - maxlen;
sum := sum - unsigned(addr(15 downto 8));
sum := sum - unsigned(addr(7 downto 0));
for i in 1 to maxlen loop
data := read_memory_8(bank, addr);
sum := sum - unsigned(data);
write(L, vec_to_hex(data, 2));
addr := std_logic_vector(unsigned(addr) + 1);
end loop;
remaining := remaining - maxlen;
write(L, vec_to_hex(std_logic_vector(sum), 2));
writeline(myfile, L);
end loop;
write_string(L, ":00000001");
writeline(myfile, L);
end write_hex_file;
-- public procedure:
procedure save_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer)
is
variable stat : file_open_status;
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
begin
-- open file
file_open(stat, myfile, filename, write_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for writing."
severity failure;
init_record(myrec);
write_binary_file (myfile, bank, address, length, myrec);
file_close(myfile);
end save_memory;
-- public procedure:
procedure save_memory_hex(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer)
is
variable stat : file_open_status;
file myfile : text;
begin
-- open file
file_open(stat, myfile, filename, write_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for writing."
severity failure;
write_hex_file (myfile, bank, address, length);
file_close(myfile);
end save_memory_hex;
end;
|
----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: md5_mux - Behavioral
-- Description:
-- A demux to select which md5 to use for hashing
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- include the hash_array type --
use work.hash_array_pkg.all;
entity md5_demux is
generic (
N : integer
);
port (
i_md5_indata : in md5_indata_t;
i_select : in std_logic_vector(N-1 downto 0); -- should be ceil(log2(N-1))
o_md5_indata : out md5_indata_t_array(N-1 downto 0)
);
end md5_demux;
architecture Behavioral of md5_demux is
begin
o_md5_indata(to_integer(unsigned(i_select))) <= i_md5_indata;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library grlib;
--use grlib.stdlib.all;
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
entity INTERFACE_SEQU_1 is
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
inp : in sequential32_in_type;
outp : out sequential32_out_type
);
end;
architecture rtl of INTERFACE_SEQU_1 is
-------------------------------------------------------------------------
-- PRAGMA BEGIN DECLARATION
-- PRAGMA END DECLARATION
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN SIGNAL
-- PRAGMA END SIGNAL
-------------------------------------------------------------------------
SIGNAL INPUT_1 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL INPUT_2 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL FLUSH : STD_LOGIC;
SIGNAL START : STD_LOGIC;
SIGNAL dInstr : STD_LOGIC_VECTOR(8 downto 0);
SIGNAL aInstr : STD_LOGIC_VECTOR(8 downto 0);
SIGNAL eInstr : STD_LOGIC_VECTOR(8 downto 0);
SIGNAL mInstr : STD_LOGIC_VECTOR(8 downto 0);
SIGNAL op1d : std_logic_vector(1 downto 0);
SIGNAL op3d : std_logic_vector(5 downto 0);
SIGNAL op1a : std_logic_vector(1 downto 0);
SIGNAL op3a : std_logic_vector(5 downto 0);
SIGNAL op1e : std_logic_vector(1 downto 0);
SIGNAL op3e : std_logic_vector(5 downto 0);
SIGNAL holdI : std_logic;
SIGNAL gclock : std_logic;
SIGNAL gValue : std_logic;
SIGNAL gpipeline : std_logic; -- a, e, m
BEGIN
-- ON SIMPLIFIE LE CODE POUR LA SUITE
INPUT_1 <= inp.op1(31 downto 0);
INPUT_2 <= inp.op2(31 downto 0);
FLUSH <= inp.flush;
DELAY_START : process(clk, rst)
BEGIN
IF (rst = '0') then
START <= '0';
ELSE
START <= inp.start;
END IF;
END PROCESS;
dInstr <= inp.dInstr(13 downto 5);
aInstr <= inp.aInstr(13 downto 5);
eInstr <= inp.eInstr(13 downto 5);
mInstr <= inp.mInstr(13 downto 5);
-- op1d <= inp.dInstr(31 downto 30);
-- op3d <= inp.dInstr(24 downto 19);
-- op1a <= inp.aInstr(31 downto 30);
-- op3a <= inp.aInstr(24 downto 19);
-- op1e <= inp.eInstr(31 downto 30);
-- op3e <= inp.eInstr(24 downto 19);
-------------------------------------------------------------------------
--
-- VERSION FONCTIONNELLE DU PIPELINE ...
--
--GATED_CLOCK : process(clk, rst)
--BEGIN
-- if (rst = '0') then
-- gpipeline <= '0';
-- elsif clk'event and clk = '1' then
-- if HOLDn = '0' then
-- gpipeline <= gpipeline;
-- else
-- gpipeline <= (aInstr(2) AND START) OR (gpipeline AND (NOT nREADY_3));
-- end if;
-- end if;
--END PROCESS;
--gclock <= clk and (gpipeline OR (aInstr(2) AND START)); --gpipeline(0) OR gpipeline(1) OR gpipeline(2) OR (aInstr(2) AND START);
--PROCESS( gclock )
--BEGIN
--if clk'event and clk = '1' then
--printmsg("(SEQ1) => (GCLOCK) VALUE (" & to_bin_str(gpipeline(0) & gpipeline(1) & gpipeline(2) & aInstr(2) & START & gclock) & ")");
--if gclock = '1' then
--REPORT "(PGDC) CLOCK ENABLE (1)";
--elsif gclock = '0' then
--REPORT "(PGDC) CLOCK DISABLE (1)";
--else
--REPORT "(PGDC) CLOCK XXXXXXX (1)";
--end if;
--end if;
--END PROCESS;
--PROCESS( gpipeline )
--BEGIN
--if gpipeline'event then
--printmsg("(SEQ1) => (GCLOCK) VALUE (" & to_bin_str(gpipeline(0) & gpipeline(1) & gpipeline(2) & aInstr(2) & START & gclock) & ")");
--if gpipeline = '1' then
--REPORT "(PGDC) gpipeline ENABLE (1)";
--elsif gpipeline = '0' then
--REPORT "(PGDC) gpipeline DISABLE (1)";
--else
--REPORT "(PGDC) CLOCK XXXXXXX (1)";
--end if;
--end if;
--END PROCESS;
--WITH gpipeline SELECT
-- gclock <= '0' WHEN "000", '1' WHEN OTHERS;
-------------------------------------------------------------------------
-- PROCESS( inp )
-- BEGIN
-- if clk'event and clk = '1' then
-- IF inp.start = '1' THEN REPORT "(INT) inp.start = '1'"; END IF;
-- IF( (inp.dInstr(31 downto 30) = "10") AND (inp.dInstr(24 downto 19) = "101111") ) THEN
-- IF (dInstr(0) AND inp.start) = '1' THEN REPORT "(INT) dSTART TO DIVIDER"; END IF;
-- IF (dInstr(1) AND inp.start) = '1' THEN REPORT "(INT) dSTART TO MODULUS"; END IF;
-- IF (dInstr(2) AND inp.start) = '1' THEN REPORT "(INT) dSTART TO PGCD"; END IF;
-- IF ((dInstr(2) AND inp.start) = '1') AND (holdn = '0') THEN REPORT "(INT) dSTART AND holdN"; END IF;
-- printmsg("(INT) dSTART MEMORISATION PROCESS (" & to_int_str(INPUT_1,6) & ")");
-- printmsg("(INT) dSTART MEMORISATION PROCESS (" & to_int_str(INPUT_2,6) & ")");
-- printmsg("(INT) dSTART INSTRUCTION (" & to_bin_str(dInstr) & ")");
-- END IF;
-- IF START(0) = '1' THEN REPORT "(INT) aSTART = '1'"; END IF;
-- case op1a is
-- when "10" =>
-- case op3a is
-- when "101111" =>
-- IF (START(0) AND aInstr(0)) = '1' THEN REPORT "(INT) aSTART TO DIVIDER"; END IF;
-- IF (START(0) AND aInstr(1)) = '1' THEN REPORT "(INT) aSTART TO MODULUS"; END IF;
-- IF (START(0) AND aInstr(2)) = '1' THEN REPORT "(INT) aSTART TO PGCD"; END IF;
-- IF ((START(0) AND aInstr(2)) = '1') AND (holdn = '0') THEN REPORT "(INT) aSTART AND holdN"; END IF;
-- printmsg("(INT) aSTART MEMORISATION PROCESS (" & to_int_str(INPUT_1,6) & ")");
-- printmsg("(INT) aSTART MEMORISATION PROCESS (" & to_int_str(INPUT_2,6) & ")");
-- printmsg("(INT) aSTART INSTRUCTION (" & to_bin_str(aInstr) & ")");
-- when others => null;
-- end case;
-- when others => null;
-- end case;
-- IF START(1) = '1' THEN REPORT "(INT) eSTART = '1'"; END IF;
-- case op1e is
-- when "10" =>
-- case op3e is
-- when "101111" =>
-- IF (START(1) AND eInstr(0)) = '1' THEN REPORT "(INT) eSTART TO DIVIDER"; END IF;
-- IF (START(1) AND eInstr(1)) = '1' THEN REPORT "(INT) eSTART TO MODULUS"; END IF;
-- IF (START(1) AND eInstr(2)) = '1' THEN REPORT "(INT) eSTART TO PGCD"; END IF;
-- IF ((START(1) AND eInstr(2)) = '1') AND (holdn = '0') THEN REPORT "(INT) eSTART AND holdN"; END IF;
-- printmsg("(INT) eSTART MEMORISATION PROCESS (" & to_int_str(INPUT_1,6) & ")");
-- printmsg("(INT) eSTART MEMORISATION PROCESS (" & to_int_str(INPUT_2,6) & ")");
-- printmsg("(INT) eSTART INSTRUCTION (" & to_bin_str(eInstr) & ")");
-- when others => null;
-- end case;
-- when others => null;
-- end case;
-- end if;
-- end process;
-------------------------------------------------------------------------
-- PRAGMA BEGIN START_SIGNAL_GENERATION
-- PRAGMA END START_SIGNAL_GENERATION
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN INSTANCIATION
-- PRAGMA END INSTANCIATION
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN RESULT SELECTION
-- PRAGMA END RESULT SELECTION
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN READY_SIGNAL_SELECTION
-- PRAGMA END READY_SIGNAL_SELECTION
-------------------------------------------------------------------------
END;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Mon Sep 16 04:56:41 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_rst_ps7_0_50M_0_sim_netlist.vhdl
-- Design : design_1_rst_ps7_0_50M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_asr : in STD_LOGIC;
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
aux_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => p_1_in,
I2 => p_2_in,
I3 => \^scndry_out\,
I4 => asr_lpf(0),
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
signal exr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => exr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => exr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(1),
I2 => p_3_out(2),
I3 => \^scndry_out\,
I4 => p_3_out(0),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute box_type : string;
attribute box_type of POR_SRL_I : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => dcm_locked,
I1 => lpf_exr,
I2 => lpf_asr,
I3 => Q,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
port (
MB_out : out STD_LOGIC;
Bsr_out : out STD_LOGIC;
Pr_out : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
signal \^bsr_out\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^mb_out\ : STD_LOGIC;
signal \^pr_out\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Bsr_out <= \^bsr_out\;
MB_out <= \^mb_out\;
Pr_out <= \^pr_out\;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr_out\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr_out\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mb_out\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^mb_out\,
S => lpf_int
);
SEQ_COUNTER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0090"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(4),
I2 => seq_cnt(3),
I3 => seq_cnt(5),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr_out\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr_out\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9000"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(4),
I2 => seq_cnt(3),
I3 => seq_cnt(5),
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^mb_out\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0018"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(0),
I2 => seq_cnt(2),
I3 => seq_cnt(1),
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0480"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr_out\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr_out\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
signal Bsr_out : STD_LOGIC;
signal MB_out : STD_LOGIC;
signal Pr_out : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal lpf_int : STD_LOGIC;
attribute box_type : string;
attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE";
attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE";
attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE";
attribute box_type of FDRE_inst : label is "PRIMITIVE";
attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Bsr_out,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
FDRE_inst: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => MB_out,
Q => mb_reset,
R => '0'
);
\PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Pr_out,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4,
Bsr_out => Bsr_out,
MB_out => MB_out,
Pr_out => Pr_out,
lpf_int => lpf_int,
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_rst_ps7_0_50M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "proc_sys_reset,Vivado 2018.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
attribute x_interface_info : string;
attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST";
attribute x_interface_parameter : string;
attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST";
attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST";
attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST";
attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK";
attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
entity initial_permutation is
port( data_in: in std_logic_vector(63 downto 0);
permuted_right_half: out std_logic_vector(31 downto 0);
permuted_left_half: out std_logic_vector(31 downto 0));
end initial_permutation;
architecture behavior of initial_permutation is
type ip_array is array(63 downto 0) of integer range 0 to 63;
constant ip: ip_array :=
((57,49,41,33,25,17,9,1,59,51,43,35,27,19,11,3,61,53,45,37,29,21,13,5,63,55,47,39,31,23,15,7,56,48,40,32,24,16,8,0,58,50,42,34,26,18,10,2,60,52,44,36,28,20,12,4,62,54,46,38,30,22,14,6));
begin
process(data_in) is
variable permuted : std_logic_vector(0 to 63);
begin
for i in data_in'range loop
permuted(i):=data_in(ip(i));
end loop;
permuted_right_half<=permuted(32 to 63);
permuted_left_half<=permuted(0 to 31);
end process;
end behavior;
|
-- $Id: arty_dram_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: arty_dram_dummy - syn
-- Description: arty target (base; serport loopback, dram project)
--
-- Dependencies: -
-- To test: tb_arty_dram
-- Target Devices: generic
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-28 1063 1.0 Initial version (derived from arty_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity arty_dram_dummy is -- ARTY dummy (base+dram)
-- implements arty_dram_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRN : in slv4; -- arty pwrmon (neg)
A_VPWRP : in slv4; -- arty pwrmon (pos)
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end arty_dram_dummy;
architecture syn of arty_dram_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_LED <= I_SWI; -- mirror SWI on LED
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED0
O_RGBLED1 <= (others=>'0');
O_RGBLED2 <= (others=>'0');
O_RGBLED3 <= (others=>'0');
DDR3_DQ <= (others=>'Z');
DDR3_DQS_P <= (others=>'Z');
DDR3_DQS_N <= (others=>'Z');
DDR3_ADDR <= (others=>'0');
DDR3_BA <= (others=>'0');
DDR3_RAS_N <= '1';
DDR3_CAS_N <= '1';
DDR3_WE_N <= '1';
DDR3_RESET_N <= '1';
DDR3_CK_P <= (others=>'0');
DDR3_CK_N <= (others=>'1');
DDR3_CKE <= (others=>'0');
DDR3_CS_N <= (others=>'1');
DDR3_DM <= (others=>'0');
DDR3_ODT <= (others=>'0');
end syn;
|
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`protect end_protected
|
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