module_content
stringlengths 18
1.05M
|
|---|
module's undeclared outputs)
reg [63:0] r1_d_d2r;
reg [63:0] r2_d_d2r;
// End of automatics
// Writes
wire [3:0] m_w1_onehotwe = ({4{w1_en}} & (4'b1 << w1_a));
wire [3:0] m_w2_onehotwe = ({4{w2_en}} & (4'b1 << w2_a));
wire [63:0] rg0_wrdat = m_w1_onehotwe[0] ? w1_d : w2_d;
wire [63:0] rg1_wrdat = m_w1_onehotwe[1] ? w1_d : w2_d;
wire [63:0] rg2_wrdat = m_w1_onehotwe[2] ? w1_d : w2_d;
wire [63:0] rg3_wrdat = m_w1_onehotwe[3] ? w1_d : w2_d;
wire [3:0] m_w_onehotwe = m_w1_onehotwe | m_w2_onehotwe;
// Storage
reg [63:0] m_rg0_r;
reg [63:0] m_rg1_r;
reg [63:0] m_rg2_r;
reg [63:0] m_rg3_r;
always @ (posedge clk) begin
if (m_w_onehotwe[0]) m_rg0_r <= rg0_wrdat;
if (m_w_onehotwe[1]) m_rg1_r <= rg1_wrdat;
if (m_w_onehotwe[2]) m_rg2_r <= rg2_wrdat;
if (m_w_onehotwe[3]) m_rg3_r <= rg3_wrdat;
end
// Reads
reg [1:0] m_r1_ad_d1r;
reg [1:0] m_r2_ad_d1r;
reg [1:0] m_ren_d1r;
always @ (posedge clk) begin
if (r1_en) m_r1_ad_d1r <= r1_ad;
if (r2_en) m_r2_ad_d1r <= r2_ad;
m_ren_d1r <= {r2_en, r1_en};
end
// Scheme1: shift...
wire [3:0] m_r1_onehot_d1 = (4'b1 << m_r1_ad_d1r);
// Scheme2: bit mask
reg [3:0] m_r2_onehot_d1;
always @* begin
m_r2_onehot_d1 = 4'd0;
m_r2_onehot_d1[m_r2_ad_d1r] = 1'b1;
end
wire [63:0] m_r1_d_d1 = (({64{m_r1_onehot_d1[0]}} & m_rg0_r) |
({64{m_r1_onehot_d1[1]}} & m_rg1_r) |
({64{m_r1_onehot_d1[2]}} & m_rg2_r) |
({64{m_r1_onehot_d1[3]}} & m_rg3_r));
wire [63:0] m_r2_d_d1 = (({64{m_r2_onehot_d1[0]}} & m_rg0_r) |
({64{m_r2_onehot_d1[1]}} & m_rg1_r) |
({64{m_r2_onehot_d1[2]}} & m_rg2_r) |
({64{m_r2_onehot_d1[3]}} & m_rg3_r));
always @ (posedge clk) begin
if (m_ren_d1r[0]) r1_d_d2r <= m_r1_d_d1;
if (m_ren_d1r[1]) r2_d_d2r <= m_r2_d_d1;
end
endmodule
|
module outputs)
wire [63:0] r1_d_d2r; // From file of file.v
wire [63:0] r2_d_d2r; // From file of file.v
// End of automatics
file file (/*AUTOINST*/
// Outputs
.r1_d_d2r (r1_d_d2r[63:0]),
.r2_d_d2r (r2_d_d2r[63:0]),
// Inputs
.clk (clk),
.r1_en (r1_en),
.r1_ad (r1_ad[1:0]),
.r2_en (r2_en),
.r2_ad (r2_ad[1:0]),
.w1_en (w1_en),
.w1_a (w1_a[1:0]),
.w1_d (w1_d[63:0]),
.w2_en (w2_en),
.w2_a (w2_a[1:0]),
.w2_d (w2_d[63:0]));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d EN=%b%b%b%b R0=%x R1=%x\n",$time, cyc, r1_en,r2_en,w1_en,w2_en, r1_d_d2r, r2_d_d2r);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {r1_d_d2r ^ r2_d_d2r} ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
// We've manually verified all X's are out of the design by this point
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h5e9ea8c33a97f81e) $stop;
$finish;
end
end
endmodule
|
module's undeclared outputs)
reg [63:0] r1_d_d2r;
reg [63:0] r2_d_d2r;
// End of automatics
// Writes
wire [3:0] m_w1_onehotwe = ({4{w1_en}} & (4'b1 << w1_a));
wire [3:0] m_w2_onehotwe = ({4{w2_en}} & (4'b1 << w2_a));
wire [63:0] rg0_wrdat = m_w1_onehotwe[0] ? w1_d : w2_d;
wire [63:0] rg1_wrdat = m_w1_onehotwe[1] ? w1_d : w2_d;
wire [63:0] rg2_wrdat = m_w1_onehotwe[2] ? w1_d : w2_d;
wire [63:0] rg3_wrdat = m_w1_onehotwe[3] ? w1_d : w2_d;
wire [3:0] m_w_onehotwe = m_w1_onehotwe | m_w2_onehotwe;
// Storage
reg [63:0] m_rg0_r;
reg [63:0] m_rg1_r;
reg [63:0] m_rg2_r;
reg [63:0] m_rg3_r;
always @ (posedge clk) begin
if (m_w_onehotwe[0]) m_rg0_r <= rg0_wrdat;
if (m_w_onehotwe[1]) m_rg1_r <= rg1_wrdat;
if (m_w_onehotwe[2]) m_rg2_r <= rg2_wrdat;
if (m_w_onehotwe[3]) m_rg3_r <= rg3_wrdat;
end
// Reads
reg [1:0] m_r1_ad_d1r;
reg [1:0] m_r2_ad_d1r;
reg [1:0] m_ren_d1r;
always @ (posedge clk) begin
if (r1_en) m_r1_ad_d1r <= r1_ad;
if (r2_en) m_r2_ad_d1r <= r2_ad;
m_ren_d1r <= {r2_en, r1_en};
end
// Scheme1: shift...
wire [3:0] m_r1_onehot_d1 = (4'b1 << m_r1_ad_d1r);
// Scheme2: bit mask
reg [3:0] m_r2_onehot_d1;
always @* begin
m_r2_onehot_d1 = 4'd0;
m_r2_onehot_d1[m_r2_ad_d1r] = 1'b1;
end
wire [63:0] m_r1_d_d1 = (({64{m_r1_onehot_d1[0]}} & m_rg0_r) |
({64{m_r1_onehot_d1[1]}} & m_rg1_r) |
({64{m_r1_onehot_d1[2]}} & m_rg2_r) |
({64{m_r1_onehot_d1[3]}} & m_rg3_r));
wire [63:0] m_r2_d_d1 = (({64{m_r2_onehot_d1[0]}} & m_rg0_r) |
({64{m_r2_onehot_d1[1]}} & m_rg1_r) |
({64{m_r2_onehot_d1[2]}} & m_rg2_r) |
({64{m_r2_onehot_d1[3]}} & m_rg3_r));
always @ (posedge clk) begin
if (m_ren_d1r[0]) r1_d_d2r <= m_r1_d_d1;
if (m_ren_d1r[1]) r2_d_d2r <= m_r2_d_d1;
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
`ifdef verilator
// Else it becomes a localparam, per IEEE 4.10.1, but we don't check it
defparam m3.FROMDEFP = 19;
`endif
m3 #(.P3(PAR),
.P2(2))
m3(.clk(clk));
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module m3
#(
parameter UNCH = 99,
parameter P1 = 10,
parameter P2 = 20,
P3 = 30
)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam LOC = 13;
parameter FROMDEFP = 11;
initial begin
$display("%x %x %x",P1,P2,P3);
end
always @ (posedge clk) begin
if (UNCH !== 99) $stop;
if (P1 !== 10) $stop;
if (P2 !== 2) $stop;
if (P3 !== 3) $stop;
`ifdef verilator
if (FROMDEFP !== 19) $stop;
`endif
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
`ifdef verilator
// Else it becomes a localparam, per IEEE 4.10.1, but we don't check it
defparam m3.FROMDEFP = 19;
`endif
m3 #(.P3(PAR),
.P2(2))
m3(.clk(clk));
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module m3
#(
parameter UNCH = 99,
parameter P1 = 10,
parameter P2 = 20,
P3 = 30
)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam LOC = 13;
parameter FROMDEFP = 11;
initial begin
$display("%x %x %x",P1,P2,P3);
end
always @ (posedge clk) begin
if (UNCH !== 99) $stop;
if (P1 !== 10) $stop;
if (P2 !== 2) $stop;
if (P3 !== 3) $stop;
`ifdef verilator
if (FROMDEFP !== 19) $stop;
`endif
end
endmodule
|
module t_case_write2_tasks ();
// verilator lint_off WIDTH
// verilator lint_off CASEINCOMPLETE
`define FD_BITS 31:0
parameter STRLEN = 78;
task ozonerab;
input [6:0] rab;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rab[6:0])
7'h00 : $fwrite (fd, " 0");
7'h01 : $fwrite (fd, " 1");
7'h02 : $fwrite (fd, " 2");
7'h03 : $fwrite (fd, " 3");
7'h04 : $fwrite (fd, " 4");
7'h05 : $fwrite (fd, " 5");
7'h06 : $fwrite (fd, " 6");
7'h07 : $fwrite (fd, " 7");
7'h08 : $fwrite (fd, " 8");
7'h09 : $fwrite (fd, " 9");
7'h0a : $fwrite (fd, " 10");
7'h0b : $fwrite (fd, " 11");
7'h0c : $fwrite (fd, " 12");
7'h0d : $fwrite (fd, " 13");
7'h0e : $fwrite (fd, " 14");
7'h0f : $fwrite (fd, " 15");
7'h10 : $fwrite (fd, " 16");
7'h11 : $fwrite (fd, " 17");
7'h12 : $fwrite (fd, " 18");
7'h13 : $fwrite (fd, " 19");
7'h14 : $fwrite (fd, " 20");
7'h15 : $fwrite (fd, " 21");
7'h16 : $fwrite (fd, " 22");
7'h17 : $fwrite (fd, " 23");
7'h18 : $fwrite (fd, " 24");
7'h19 : $fwrite (fd, " 25");
7'h1a : $fwrite (fd, " 26");
7'h1b : $fwrite (fd, " 27");
7'h1c : $fwrite (fd, " 28");
7'h1d : $fwrite (fd, " 29");
7'h1e : $fwrite (fd, " 30");
7'h1f : $fwrite (fd, " 31");
7'h20 : $fwrite (fd, " 32");
7'h21 : $fwrite (fd, " 33");
7'h22 : $fwrite (fd, " 34");
7'h23 : $fwrite (fd, " 35");
7'h24 : $fwrite (fd, " 36");
7'h25 : $fwrite (fd, " 37");
7'h26 : $fwrite (fd, " 38");
7'h27 : $fwrite (fd, " 39");
7'h28 : $fwrite (fd, " 40");
7'h29 : $fwrite (fd, " 41");
7'h2a : $fwrite (fd, " 42");
7'h2b : $fwrite (fd, " 43");
7'h2c : $fwrite (fd, " 44");
7'h2d : $fwrite (fd, " 45");
7'h2e : $fwrite (fd, " 46");
7'h2f : $fwrite (fd, " 47");
7'h30 : $fwrite (fd, " 48");
7'h31 : $fwrite (fd, " 49");
7'h32 : $fwrite (fd, " 50");
7'h33 : $fwrite (fd, " 51");
7'h34 : $fwrite (fd, " 52");
7'h35 : $fwrite (fd, " 53");
7'h36 : $fwrite (fd, " 54");
7'h37 : $fwrite (fd, " 55");
7'h38 : $fwrite (fd, " 56");
7'h39 : $fwrite (fd, " 57");
7'h3a : $fwrite (fd, " 58");
7'h3b : $fwrite (fd, " 59");
7'h3c : $fwrite (fd, " 60");
7'h3d : $fwrite (fd, " 61");
7'h3e : $fwrite (fd, " 62");
7'h3f : $fwrite (fd, " 63");
7'h40 : $fwrite (fd, " 64");
7'h41 : $fwrite (fd, " 65");
7'h42 : $fwrite (fd, " 66");
7'h43 : $fwrite (fd, " 67");
7'h44 : $fwrite (fd, " 68");
7'h45 : $fwrite (fd, " 69");
7'h46 : $fwrite (fd, " 70");
7'h47 : $fwrite (fd, " 71");
7'h48 : $fwrite (fd, " 72");
7'h49 : $fwrite (fd, " 73");
7'h4a : $fwrite (fd, " 74");
7'h4b : $fwrite (fd, " 75");
7'h4c : $fwrite (fd, " 76");
7'h4d : $fwrite (fd, " 77");
7'h4e : $fwrite (fd, " 78");
7'h4f : $fwrite (fd, " 79");
7'h50 : $fwrite (fd, " 80");
7'h51 : $fwrite (fd, " 81");
7'h52 : $fwrite (fd, " 82");
7'h53 : $fwrite (fd, " 83");
7'h54 : $fwrite (fd, " 84");
7'h55 : $fwrite (fd, " 85");
7'h56 : $fwrite (fd, " 86");
7'h57 : $fwrite (fd, " 87");
7'h58 : $fwrite (fd, " 88");
7'h59 : $fwrite (fd, " 89");
7'h5a : $fwrite (fd, " 90");
7'h5b : $fwrite (fd, " 91");
7'h5c : $fwrite (fd, " 92");
7'h5d : $fwrite (fd, " 93");
7'h5e : $fwrite (fd, " 94");
7'h5f : $fwrite (fd, " 95");
7'h60 : $fwrite (fd, " 96");
7'h61 : $fwrite (fd, " 97");
7'h62 : $fwrite (fd, " 98");
7'h63 : $fwrite (fd, " 99");
7'h64 : $fwrite (fd, " 100");
7'h65 : $fwrite (fd, " 101");
7'h66 : $fwrite (fd, " 102");
7'h67 : $fwrite (fd, " 103");
7'h68 : $fwrite (fd, " 104");
7'h69 : $fwrite (fd, " 105");
7'h6a : $fwrite (fd, " 106");
7'h6b : $fwrite (fd, " 107");
7'h6c : $fwrite (fd, " 108");
7'h6d : $fwrite (fd, " 109");
7'h6e : $fwrite (fd, " 110");
7'h6f : $fwrite (fd, " 111");
7'h70 : $fwrite (fd, " 112");
7'h71 : $fwrite (fd, " 113");
7'h72 : $fwrite (fd, " 114");
7'h73 : $fwrite (fd, " 115");
7'h74 : $fwrite (fd, " 116");
7'h75 : $fwrite (fd, " 117");
7'h76 : $fwrite (fd, " 118");
7'h77 : $fwrite (fd, " 119");
7'h78 : $fwrite (fd, " 120");
7'h79 : $fwrite (fd, " 121");
7'h7a : $fwrite (fd, " 122");
7'h7b : $fwrite (fd, " 123");
7'h7c : $fwrite (fd, " 124");
7'h7d : $fwrite (fd, " 125");
7'h7e : $fwrite (fd, " 126");
7'h7f : $fwrite (fd, " 127");
default:$fwrite (fd, " 128");
endcase
end
endtask
task ozonerb;
input [5:0] rb;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rb[5:0])
6'h10,
6'h17,
6'h1e,
6'h1f: $fwrite (fd, " 129");
default: ozonerab({1'b1, rb}, fd);
endcase
end
endtask
task ozonef3f4_iext;
input [1:0] foo;
input [15:0] im16;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 :
begin
skyway({4{im16[15]}}, fd);
skyway({4{im16[15]}}, fd);
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
$fwrite (fd, " 130");
end
2'h1 :
begin
$fwrite (fd, " 131");
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
end
2'h2 :
begin
skyway({4{im16[15]}}, fd);
skyway({4{im16[15]}}, fd);
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
$fwrite (fd, " 132");
end
2'h3 :
begin
$fwrite (fd, " 133");
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
end
endcase
end
endtask
task skyway;
input [ 3:0] hex;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (hex)
4'h0 : $fwrite (fd, " 134");
4'h1 : $fwrite (fd, " 135");
4'h2 : $fwrite (fd, " 136");
4'h3 : $fwrite (fd, " 137");
4'h4 : $fwrite (fd, " 138");
4'h5 : $fwrite (fd, " 139");
4'h6 : $fwrite (fd, " 140");
4'h7 : $fwrite (fd, " 141");
4'h8 : $fwrite (fd, " 142");
4'h9 : $fwrite (fd, " 143");
4'ha : $fwrite (fd, " 144");
4'hb : $fwrite (fd, " 145");
4'hc : $fwrite (fd, " 146");
4'hd : $fwrite (fd, " 147");
4'he : $fwrite (fd, " 148");
4'hf : $fwrite (fd, " 149");
endcase
end
endtask
task ozonesr;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[11: 9])
3'h0 : $fwrite (fd, " 158");
3'h1 : $fwrite (fd, " 159");
3'h2 : $fwrite (fd, " 160");
3'h3 : $fwrite (fd, " 161");
3'h4 : $fwrite (fd, " 162");
3'h5 : $fwrite (fd, " 163");
3'h6 : $fwrite (fd, " 164");
3'h7 : $fwrite (fd, " 165");
endcase
end
endtask
task ozonejk;
input k;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
if (k)
$fwrite (fd, " 166");
else
$fwrite (fd, " 167");
end
endtask
task ozoneae;
input [ 2:0] ae;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ae)
3'b000 : $fwrite (fd, " 168");
3'b001 : $fwrite (fd, " 169");
3'b010 : $fwrite (fd, " 170");
3'b011 : $fwrite (fd, " 171");
3'b100 : $fwrite (fd, " 172");
3'b101 : $fwrite (fd, " 173");
3'b110 : $fwrite (fd, " 174");
3'b111 : $fwrite (fd, " 175");
endcase
end
endtask
task ozoneaee;
input [ 2:0] aee;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (aee)
3'b001,
3'b011,
3'b101,
3'b111 : $fwrite (fd, " 176");
3'b000 : $fwrite (fd, " 177");
3'b010 : $fwrite (fd, " 178");
3'b100 : $fwrite (fd, " 179");
3'b110 : $fwrite (fd, " 180");
endcase
end
endtask
task ozoneape;
input [ 2:0] ape;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ape)
3'b001,
3'b011,
3'b101,
3'b111 : $fwrite (fd, " 181");
3'b000 : $fwrite (fd, " 182");
3'b010 : $fwrite (fd, " 183");
3'b100 : $fwrite (fd, " 184");
3'b110 : $fwrite (fd, " 185");
endcase
end
endtask
task ozonef1;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
if (foo[26])
$fwrite (fd, " 186");
else
$fwrite (fd, " 187");
4'h1 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 188");
2'b01 : $fwrite (fd, " 189");
2'b10 : $fwrite (fd, " 190");
2'b11 : $fwrite (fd, " 191");
endcase
4'h2 : $fwrite (fd, " 192");
4'h3 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 193");
2'b01 : $fwrite (fd, " 194");
2'b10 : $fwrite (fd, " 195");
2'b11 : $fwrite (fd, " 196");
endcase
4'h4 :
if (foo[26])
$fwrite (fd, " 197");
else
$fwrite (fd, " 198");
4'h5 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 199");
2'b01 : $fwrite (fd, " 200");
2'b10 : $fwrite (fd, " 201");
2'b11 : $fwrite (fd, " 202");
endcase
4'h6 : $fwrite (fd, " 203");
4'h7 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 204");
2'b01 : $fwrite (fd, " 205");
2'b10 : $fwrite (fd, " 206");
2'b11 : $fwrite (fd, " 207");
endcase
4'h8 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 208");
2'b01 : $fwrite (fd, " 209");
2'b10 : $fwrite (fd, " 210");
2'b11 : $fwrite (fd, " 211");
endcase
4'h9 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 212");
2'b01 : $fwrite (fd, " 213");
2'b10 : $fwrite (fd, " 214");
2'b11 : $fwrite (fd, " 215");
endcase
4'ha :
if (foo[25])
$fwrite (fd, " 216");
else
$fwrite (fd, " 217");
4'hb :
if (foo[25])
$fwrite (fd, " 218");
else
$fwrite (fd, " 219");
4'hc :
if (foo[26])
$fwrite (fd, " 220");
else
$fwrite (fd, " 221");
4'hd :
case (foo[26:25])
2'b00 : $fwrite (fd, " 222");
2'b01 : $fwrite (fd, " 223");
2'b10 : $fwrite (fd, " 224");
2'b11 : $fwrite (fd, " 225");
endcase
4'he :
case (foo[26:25])
2'b00 : $fwrite (fd, " 226");
2'b01 : $fwrite (fd, " 227");
2'b10 : $fwrite (fd, " 228");
2'b11 : $fwrite (fd, " 229");
endcase
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd, " 230");
2'b01 : $fwrite (fd, " 231");
2'b10 : $fwrite (fd, " 232");
2'b11 : $fwrite (fd, " 233");
endcase
endcase
end
endtask
task ozonef1e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[27:21])
7'h00:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 234");
$fwrite (fd, " 235");
end
7'h01:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 236");
ozoneae(foo[17:15], fd);
$fwrite (fd," 237");
$fwrite (fd, " 238");
end
7'h02:
$fwrite (fd, " 239");
7'h03:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 240");
ozoneae(foo[17:15], fd);
$fwrite (fd," 241");
$fwrite (fd, " 242");
end
7'h04:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 243");
$fwrite (fd," 244");
end
7'h05:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 245");
ozoneae(foo[17:15], fd);
$fwrite (fd," 246");
end
7'h06:
$fwrite (fd, " 247");
7'h07:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 248");
ozoneae(foo[17:15], fd);
$fwrite (fd," 249");
end
7'h08:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 250");
ozoneae(foo[17:15], fd);
$fwrite (fd," 251");
end
7'h09:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 252");
ozoneae(foo[17:15], fd);
$fwrite (fd," 253");
end
7'h0a:
begin
ozoneae(foo[17:15], fd);
$fwrite (fd," 254");
end
7'h0b:
begin
ozoneae(foo[17:15], fd);
$fwrite (fd," 255");
end
7'h0c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 256");
end
7'h0d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 257");
ozoneae(foo[17:15], fd);
$fwrite (fd," 258");
end
7'h0e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 259");
ozoneae(foo[17:15], fd);
$fwrite (fd," 260");
end
7'h0f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 261");
ozoneae(foo[17:15], fd);
$fwrite (fd," 262");
end
7'h10:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 263");
ozoneae(foo[17:15], fd);
$fwrite (fd," 264");
$fwrite (fd, " 265");
$fwrite (fd, " 266");
end
7'h11:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 267");
ozoneae(foo[17:15], fd);
$fwrite (fd," 268");
$fwrite (fd, " 269");
$fwrite (fd, " 270");
end
7'h12:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 271");
ozoneae(foo[17:15], fd);
$fwrite (fd," 272");
$fwrite (fd, " 273");
$fwrite (fd, " 274");
end
7'h13:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 275");
ozoneae(foo[17:15], fd);
$fwrite (fd," 276");
$fwrite (fd, " 277");
$fwrite (fd, " 278");
end
7'h14:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 279");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 280");
ozoneape(foo[20:18], fd);
$fwrite (fd," 281");
ozoneape(foo[17:15], fd);
$fwrite (fd," 282");
$fwrite (fd, " 283");
$fwrite (fd, " 284");
end
7'h15:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 285");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 286");
ozoneape(foo[20:18], fd);
$fwrite (fd," 287");
ozoneape(foo[17:15], fd);
$fwrite (fd," 288");
$fwrite (fd, " 289");
$fwrite (fd, " 290");
end
7'h16:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 291");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 292");
ozoneape(foo[20:18], fd);
$fwrite (fd," 293");
ozoneape(foo[17:15], fd);
$fwrite (fd," 294");
$fwrite (fd, " 295");
$fwrite (fd, " 296");
end
7'h17:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 297");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 298");
ozoneape(foo[20:18], fd);
$fwrite (fd," 299");
ozoneape(foo[17:15], fd);
$fwrite (fd," 300");
$fwrite (fd, " 301");
$fwrite (fd, " 302");
end
7'h18:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 303");
ozoneae(foo[17:15], fd);
$fwrite (fd," 304");
$fwrite (fd, " 305");
$fwrite (fd, " 306");
end
7'h19:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 307");
ozoneae(foo[17:15], fd);
$fwrite (fd," 308");
$fwrite (fd, " 309");
$fwrite (fd, " 310");
end
7'h1a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 311");
ozoneae(foo[17:15], fd);
$fwrite (fd," 312");
$fwrite (fd, " 313");
$fwrite (fd, " 314");
end
7'h1b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 315");
ozoneae(foo[17:15], fd);
$fwrite (fd," 316");
$fwrite (fd, " 317");
$fwrite (fd, " 318");
end
7'h1c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 319");
ozoneae(foo[17:15], fd);
$fwrite (fd," 320");
$fwrite (fd, " 321");
$fwrite (fd, " 322");
end
7'h1d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 323");
ozoneae(foo[17:15], fd);
$fwrite (fd," 324");
$fwrite (fd, " 325");
$fwrite (fd, " 326");
end
7'h1e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 327");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 328");
ozoneape(foo[20:18], fd);
$fwrite (fd," 329");
ozoneape(foo[17:15], fd);
$fwrite (fd," 330");
$fwrite (fd, " 331");
$fwrite (fd, " 332");
end
7'h1f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 333");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 334");
ozoneape(foo[20:18], fd);
$fwrite (fd," 335");
ozoneape(foo[17:15], fd);
$fwrite (fd," 336");
$fwrite (fd, " 337");
$fwrite (fd, " 338");
end
7'h20:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 339");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 340");
ozoneape(foo[20:18], fd);
$fwrite (fd," 341");
ozoneape(foo[17:15], fd);
$fwrite (fd," 342");
$fwrite (fd, " 343");
$fwrite (fd, " 344");
end
7'h21:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 345");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 346");
ozoneape(foo[20:18], fd);
$fwrite (fd," 347");
ozoneape(foo[17:15], fd);
$fwrite (fd," 348");
$fwrite (fd, " 349");
$fwrite (fd, " 350");
end
7'h22:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 351");
ozoneae(foo[17:15], fd);
$fwrite (fd," 352");
$fwrite (fd, " 353");
$fwrite (fd, " 354");
end
7'h23:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 355");
ozoneae(foo[17:15], fd);
$fwrite (fd," 356");
$fwrite (fd, " 357");
$fwrite (fd, " 358");
end
7'h24:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 359");
ozoneae(foo[17:15], fd);
$fwrite (fd," 360");
$fwrite (fd, " 361");
$fwrite (fd, " 362");
end
7'h25:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 363");
ozoneae(foo[17:15], fd);
$fwrite (fd," 364");
$fwrite (fd, " 365");
$fwrite (fd, " 366");
end
7'h26:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 367");
ozoneae(foo[17:15], fd);
$fwrite (fd," 368");
$fwrite (fd, " 369");
$fwrite (fd, " 370");
end
7'h27:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 371");
ozoneae(foo[17:15], fd);
$fwrite (fd," 372");
$fwrite (fd, " 373");
$fwrite (fd, " 374");
end
7'h28:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 375");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 376");
ozoneape(foo[20:18], fd);
$fwrite (fd," 377");
ozoneape(foo[17:15], fd);
$fwrite (fd," 378");
$fwrite (fd, " 379");
$fwrite (fd, " 380");
end
7'h29:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 381");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 382");
ozoneape(foo[20:18], fd);
$fwrite (fd," 383");
ozoneape(foo[17:15], fd);
$fwrite (fd," 384");
$fwrite (fd, " 385");
$fwrite (fd, " 386");
end
7'h2a:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 387");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 388");
ozoneape(foo[20:18], fd);
$fwrite (fd," 389");
ozoneape(foo[17:15], fd);
$fwrite (fd," 390");
$fwrite (fd, " 391");
$fwrite (fd, " 392");
end
7'h2b:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 393");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 394");
ozoneape(foo[20:18], fd);
$fwrite (fd," 395");
ozoneape(foo[17:15], fd);
$fwrite (fd," 396");
$fwrite (fd, " 397");
$fwrite (fd, " 398");
end
7'h2c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 399");
ozoneae(foo[17:15], fd);
$fwrite (fd," 400");
$fwrite (fd, " 401");
$fwrite (fd, " 402");
end
7'h2d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 403");
ozoneae(foo[17:15], fd);
$fwrite (fd," 404");
$fwrite (fd, " 405");
$fwrite (fd, " 406");
end
7'h2e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 407");
ozoneae(foo[17:15], fd);
$fwrite (fd," 408");
$fwrite (fd, " 409");
$fwrite (fd, " 410");
end
7'h2f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 411");
ozoneae(foo[17:15], fd);
$fwrite (fd," 412");
$fwrite (fd, " 413");
$fwrite (fd, " 414");
end
7'h30:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 415");
ozoneae(foo[17:15], fd);
$fwrite (fd," 416");
$fwrite (fd, " 417");
$fwrite (fd, " 418");
end
7'h31:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 419");
ozoneae(foo[17:15], fd);
$fwrite (fd," 420");
$fwrite (fd, " 421");
$fwrite (fd, " 422");
end
7'h32:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 423");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 424");
ozoneape(foo[20:18], fd);
$fwrite (fd," 425");
ozoneape(foo[17:15], fd);
$fwrite (fd," 426");
$fwrite (fd, " 427");
$fwrite (fd, " 428");
end
7'h33:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 429");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 430");
ozoneape(foo[20:18], fd);
$fwrite (fd," 431");
ozoneape(foo[17:15], fd);
$fwrite (fd," 432");
$fwrite (fd, " 433");
$fwrite (fd, " 434");
end
7'h34:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 435");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 436");
ozoneape(foo[20:18], fd);
$fwrite (fd," 437");
ozoneape(foo[17:15], fd);
$fwrite (fd," 438");
$fwrite (fd, " 439");
$fwrite (fd, " 440");
end
7'h35:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 441");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 442");
ozoneape(foo[20:18], fd);
$fwrite (fd," 443");
ozoneape(foo[17:15], fd);
$fwrite (fd," 444");
$fwrite (fd, " 445");
$fwrite (fd, " 446");
end
7'h36:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 447");
ozoneae(foo[17:15], fd);
$fwrite (fd," 448");
$fwrite (fd, " 449");
$fwrite (fd, " 450");
end
7'h37:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 451");
ozoneae(foo[17:15], fd);
$fwrite (fd," 452");
$fwrite (fd, " 453");
$fwrite (fd, " 454");
end
7'h38:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 455");
ozoneae(foo[17:15], fd);
$fwrite (fd," 456");
$fwrite (fd, " 457");
end
7'h39:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 458");
ozoneae(foo[17:15], fd);
$fwrite (fd," 459");
$fwrite (fd, " 460");
end
7'h3a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 461");
ozoneae(foo[17:15], fd);
$fwrite (fd," 462");
$fwrite (fd, " 463");
end
7'h3b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 464");
ozoneae(foo[17:15], fd);
$fwrite (fd," 465");
$fwrite (fd, " 466");
end
7'h3c:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 467");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 468");
ozoneape(foo[20:18], fd);
$fwrite (fd," 469");
ozoneape(foo[17:15], fd);
$fwrite (fd," 470");
$fwrite (fd, " 471");
end
7'h3d:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 472");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 473");
ozoneape(foo[20:18], fd);
$fwrite (fd," 474");
ozoneape(foo[17:15], fd);
$fwrite (fd," 475");
$fwrite (fd, " 476");
end
7'h3e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 477");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 478");
ozoneape(foo[20:18], fd);
$fwrite (fd," 479");
ozoneape(foo[17:15], fd);
$fwrite (fd," 480");
$fwrite (fd, " 481");
end
7'h3f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 482");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 483");
ozoneape(foo[20:18], fd);
$fwrite (fd," 484");
ozoneape(foo[17:15], fd);
$fwrite (fd," 485");
$fwrite (fd, " 486");
end
7'h40:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 487");
ozoneae(foo[17:15], fd);
$fwrite (fd," 488");
$fwrite (fd, " 489");
$fwrite (fd, " 490");
end
7'h41:
begin
$fwrite (fd, " 491");
$fwrite (fd, " 492");
end
7'h42:
begin
$fwrite (fd, " 493");
$fwrite (fd, " 494");
end
7'h43:
begin
$fwrite (fd, " 495");
$fwrite (fd, " 496");
end
7'h44:
begin
$fwrite (fd, " 497");
$fwrite (fd, " 498");
end
7'h45:
$fwrite (fd, " 499");
7'h46:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 500");
$fwrite (fd, " 501");
$fwrite (fd, " 502");
end
7'h47:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 503");
ozoneae(foo[17:15], fd);
$fwrite (fd," 504");
ozoneape(foo[20:18], fd);
$fwrite (fd," 505");
ozoneape(foo[20:18], fd);
$fwrite (fd," 506");
$fwrite (fd, " 507");
$fwrite (fd, " 508");
end
7'h48:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 509");
ozoneape(foo[20:18], fd);
$fwrite (fd," 510");
ozoneape(foo[20:18], fd);
$fwrite (fd," 511");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 512");
ozoneape(foo[17:15], fd);
$fwrite (fd," 513");
end
7'h49:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 514");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 515");
ozoneape(foo[17:15], fd);
$fwrite (fd," 516");
end
7'h4a:
$fwrite (fd," 517");
7'h4b:
$fwrite (fd, " 518");
7'h4c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 519");
$fwrite (fd, " 520");
$fwrite (fd, " 521");
end
7'h4d:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 522");
ozoneae(foo[17:15], fd);
$fwrite (fd," 523");
ozoneape(foo[20:18], fd);
$fwrite (fd," 524");
ozoneape(foo[20:18], fd);
$fwrite (fd," 525");
$fwrite (fd, " 526");
$fwrite (fd, " 527");
end
7'h4e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 528");
ozoneae(foo[17:15], fd);
$fwrite (fd," 529");
ozoneape(foo[20:18], fd);
$fwrite (fd," 530");
ozoneape(foo[20:18], fd);
$fwrite (fd," 531");
end
7'h4f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 532");
end
7'h50:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 533");
ozoneae(foo[17:15], fd);
$fwrite (fd," 534");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 535");
ozoneae(foo[17:15], fd);
$fwrite (fd," 536");
ozoneape(foo[20:18], fd);
$fwrite (fd," 537");
ozoneae(foo[17:15], fd);
$fwrite (fd," 538");
ozoneape(foo[20:18], fd);
$fwrite (fd," 539");
ozoneae(foo[17:15], fd);
$fwrite (fd," 540");
end
7'h51:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 541");
ozoneape(foo[20:18], fd);
$fwrite (fd," 542");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 543");
ozoneape(foo[20:18], fd);
$fwrite (fd," 544");
ozoneae(foo[17:15], fd);
$fwrite (fd," 545");
end
7'h52:
$fwrite (fd, " 546");
7'h53:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 547");
end
7'h54:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 548");
ozoneae(foo[17:15], fd);
$fwrite (fd," 549");
end
7'h55:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 550");
ozoneae(foo[17:15], fd);
$fwrite (fd," 551");
end
7'h56:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 552");
ozoneae(foo[17:15], fd);
$fwrite (fd," 553");
$fwrite (fd, " 554");
end
7'h57:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 555");
ozoneae(foo[17:15], fd);
$fwrite (fd," 556");
ozoneape(foo[20:18], fd);
$fwrite (fd," 557");
ozoneape(foo[20:18], fd);
$fwrite (fd," 558");
end
7'h58:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 559");
end
7'h59:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 560");
ozoneae(foo[17:15], fd);
$fwrite (fd," 561");
ozoneape(foo[20:18], fd);
$fwrite (fd," 562");
ozoneape(foo[20:18], fd);
$fwrite (fd," 563");
end
7'h5a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 564");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 565");
end
7'h5b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 566");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 567");
end
7'h5c:
begin
$fwrite (fd," 568");
ozoneape(foo[17:15], fd);
$fwrite (fd," 569");
$fwrite (fd," 570");
ozoneape(foo[17:15], fd);
$fwrite (fd," 571");
ozoneae(foo[20:18], fd);
$fwrite (fd," 572");
ozoneaee(foo[17:15], fd);
$fwrite (fd, " 573");
end
7'h5d:
begin
$fwrite (fd," 574");
ozoneape(foo[17:15], fd);
$fwrite (fd," 575");
$fwrite (fd," 576");
ozoneape(foo[17:15], fd);
$fwrite (fd," 577");
ozoneae(foo[20:18], fd);
$fwrite (fd," 578");
ozoneaee(foo[17:15], fd);
$fwrite (fd, " 579");
end
7'h5e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 580");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 581");
end
7'h5f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 582");
ozoneae(foo[17:15], fd);
$fwrite (fd," 583");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 584");
ozoneae(foo[17:15], fd);
$fwrite (fd," 585");
ozoneape(foo[20:18], fd);
$fwrite (fd," 586");
ozoneae(foo[17:15], fd);
$fwrite (fd," 587");
ozoneape(foo[20:18], fd);
$fwrite (fd," 588");
ozoneae(foo[17:15], fd);
$fwrite (fd," 589");
end
7'h60:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 590");
ozoneae(foo[17:15], fd);
$fwrite (fd," 591");
end
7'h61:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 592");
ozoneae(foo[17:15], fd);
$fwrite (fd," 593");
end
7'h62:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 594");
ozoneae(foo[17:15], fd);
$fwrite (fd," 595");
end
7'h63:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 596");
ozoneae(foo[17:15], fd);
$fwrite (fd," 597");
end
7'h64:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 598");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 599");
ozoneape(foo[20:18], fd);
$fwrite (fd," 600");
ozoneape(foo[17:15], fd);
$fwrite (fd," 601");
end
7'h65:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 602");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 603");
ozoneape(foo[20:18], fd);
$fwrite (fd," 604");
ozoneape(foo[17:15], fd);
$fwrite (fd," 605");
end
7'h66:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 606");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 607");
ozoneape(foo[20:18], fd);
$fwrite (fd," 608");
ozoneape(foo[17:15], fd);
$fwrite (fd," 609");
end
7'h67:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 610");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 611");
ozoneape(foo[20:18], fd);
$fwrite (fd," 612");
ozoneape(foo[17:15], fd);
$fwrite (fd," 613");
end
7'h68:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 614");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 615");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 616");
ozoneape(foo[20:18], fd);
$fwrite (fd," 617");
ozoneape(foo[20:18], fd);
$fwrite (fd," 618");
ozoneape(foo[17:15], fd);
end
7'h69:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 619");
ozoneae(foo[17:15], fd);
$fwrite (fd," 620");
ozoneae(foo[20:18], fd);
$fwrite (fd," 621");
end
7'h6a:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 622");
ozoneae(foo[17:15], fd);
$fwrite (fd," 623");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 624");
ozoneape(foo[20:18], fd);
$fwrite (fd," 625");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 626");
ozoneae(foo[17:15], fd);
end
7'h6b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 627");
ozoneae(foo[17:15], fd);
$fwrite (fd," 628");
ozoneae(foo[20:18], fd);
$fwrite (fd," 629");
end
7'h6c:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 630");
ozoneae(foo[17:15], fd);
$fwrite (fd," 631");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 632");
ozoneape(foo[20:18], fd);
$fwrite (fd," 633");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 634");
ozoneae(foo[17:15], fd);
end
7'h6d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 635");
ozoneae(foo[17:15], fd);
$fwrite (fd," 636");
ozoneae(foo[20:18], fd);
$fwrite (fd," 637");
end
7'h6e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 638");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 639");
ozoneape(foo[20:18], fd);
$fwrite (fd," 640");
ozoneape(foo[17:15], fd);
$fwrite (fd," 641");
end
7'h6f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 642");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 643");
ozoneape(foo[20:18], fd);
$fwrite (fd," 644");
ozoneape(foo[17:15], fd);
$fwrite (fd," 645");
end
7'h70:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 646");
ozoneae(foo[20:18], fd);
$fwrite (fd," 647");
ozoneae(foo[17:15], fd);
$fwrite (fd," 648");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 649");
end
7'h71:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 650");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 651");
end
7'h72:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 652");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 653");
end
7'h73:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 654");
ozoneae(foo[20:18], fd);
$fwrite (fd," 655");
ozoneae(foo[17:15], fd);
end
7'h74:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 656");
ozoneae(foo[20:18], fd);
$fwrite (fd," 657");
ozoneae(foo[17:15], fd);
end
7'h75:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 658");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 659");
ozoneape(foo[20:18], fd);
$fwrite (fd," 660");
ozoneape(foo[17:15], fd);
$fwrite (fd," 661");
$fwrite (fd, " 662");
$fwrite (fd, " 663");
end
7'h76:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 664");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 665");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 666");
ozoneape(foo[20:18], fd);
$fwrite (fd," 667");
ozoneape(foo[17:15], fd);
$fwrite (fd," 668");
ozoneape(foo[20:18], fd);
$fwrite (fd," 669");
end
7'h77:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 670");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 671");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 672");
ozoneape(foo[20:18], fd);
$fwrite (fd," 673");
ozoneape(foo[17:15], fd);
$fwrite (fd," 674");
ozoneape(foo[17:15], fd);
$fwrite (fd," 675");
end
7'h78,
7'h79,
7'h7a,
7'h7b,
7'h7c,
7'h7d,
7'h7e,
7'h7f:
$fwrite (fd," 676");
endcase
end
endtask
task ozonef2;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
case (foo[26:25])
2'b00 : $fwrite (fd," 677");
2'b01 : $fwrite (fd," 678");
2'b10 : $fwrite (fd," 679");
2'b11 : $fwrite (fd," 680");
endcase
4'h1 :
case (foo[26:25])
2'b00 : $fwrite (fd," 681");
2'b01 : $fwrite (fd," 682");
2'b10 : $fwrite (fd," 683");
2'b11 : $fwrite (fd," 684");
endcase
4'h2 :
case (foo[26:25])
2'b00 : $fwrite (fd," 685");
2'b01 : $fwrite (fd," 686");
2'b10 : $fwrite (fd," 687");
2'b11 : $fwrite (fd," 688");
endcase
4'h3 :
case (foo[26:25])
2'b00 : $fwrite (fd," 689");
2'b01 : $fwrite (fd," 690");
2'b10 : $fwrite (fd," 691");
2'b11 : $fwrite (fd," 692");
endcase
4'h4 :
case (foo[26:25])
2'b00 : $fwrite (fd," 693");
2'b01 : $fwrite (fd," 694");
2'b10 : $fwrite (fd," 695");
2'b11 : $fwrite (fd," 696");
endcase
4'h5 :
case (foo[26:25])
2'b00 : $fwrite (fd," 697");
2'b01 : $fwrite (fd," 698");
2'b10 : $fwrite (fd," 699");
2'b11 : $fwrite (fd," 700");
endcase
4'h6 :
case (foo[26:25])
2'b00 : $fwrite (fd," 701");
2'b01 : $fwrite (fd," 702");
2'b10 : $fwrite (fd," 703");
2'b11 : $fwrite (fd," 704");
endcase
4'h7 :
case (foo[26:25])
2'b00 : $fwrite (fd," 705");
2'b01 : $fwrite (fd," 706");
2'b10 : $fwrite (fd," 707");
2'b11 : $fwrite (fd," 708");
endcase
4'h8 :
if (foo[26])
$fwrite (fd," 709");
else
$fwrite (fd," 710");
4'h9 :
case (foo[26:25])
2'b00 : $fwrite (fd," 711");
2'b01 : $fwrite (fd," 712");
2'b10 : $fwrite (fd," 713");
2'b11 : $fwrite (fd," 714");
endcase
4'ha :
case (foo[26:25])
2'b00 : $fwrite (fd," 715");
2'b01 : $fwrite (fd," 716");
2'b10 : $fwrite (fd," 717");
2'b11 : $fwrite (fd," 718");
endcase
4'hb :
case (foo[26:25])
2'b00 : $fwrite (fd," 719");
2'b01 : $fwrite (fd," 720");
2'b10 : $fwrite (fd," 721");
2'b11 : $fwrite (fd," 722");
endcase
4'hc :
if (foo[26])
$fwrite (fd," 723");
else
$fwrite (fd," 724");
4'hd :
case (foo[26:25])
2'b00 : $fwrite (fd," 725");
2'b01 : $fwrite (fd," 726");
2'b10 : $fwrite (fd," 727");
2'b11 : $fwrite (fd," 728");
endcase
4'he :
case (foo[26:25])
2'b00 : $fwrite (fd," 729");
2'b01 : $fwrite (fd," 730");
2'b10 : $fwrite (fd," 731");
2'b11 : $fwrite (fd," 732");
endcase
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd," 733");
2'b01 : $fwrite (fd," 734");
2'b10 : $fwrite (fd," 735");
2'b11 : $fwrite (fd," 736");
endcase
endcase
end
endtask
task ozonef2e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
casez (foo[25:21])
5'h00 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 737");
ozoneae(foo[17:15], fd);
$fwrite (fd," 738");
end
5'h01 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 739");
ozoneae(foo[17:15], fd);
$fwrite (fd," 740");
end
5'h02 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 741");
ozoneae(foo[17:15], fd);
$fwrite (fd," 742");
end
5'h03 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 743");
ozoneae(foo[17:15], fd);
$fwrite (fd," 744");
end
5'h04 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 745");
ozoneae(foo[17:15], fd);
$fwrite (fd," 746");
end
5'h05 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 747");
ozoneae(foo[17:15], fd);
$fwrite (fd," 748");
end
5'h06 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 749");
ozoneae(foo[17:15], fd);
$fwrite (fd," 750");
end
5'h07 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 751");
ozoneae(foo[17:15], fd);
$fwrite (fd," 752");
end
5'h08 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 753");
if (foo[ 6])
$fwrite (fd," 754");
else
$fwrite (fd," 755");
end
5'h09 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 756");
ozoneae(foo[17:15], fd);
$fwrite (fd," 757");
end
5'h0a :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 758");
ozoneae(foo[17:15], fd);
end
5'h0b :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 759");
ozoneae(foo[17:15], fd);
$fwrite (fd," 760");
end
5'h0c :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 761");
end
5'h0d :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 762");
ozoneae(foo[17:15], fd);
$fwrite (fd," 763");
end
5'h0e :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 764");
ozoneae(foo[17:15], fd);
end
5'h0f :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 765");
ozoneae(foo[17:15], fd);
end
5'h10 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 766");
ozoneae(foo[17:15], fd);
$fwrite (fd," 767");
end
5'h11 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 768");
ozoneae(foo[17:15], fd);
$fwrite (fd," 769");
end
5'h18 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 770");
if (foo[ 6])
$fwrite (fd," 771");
else
$fwrite (fd," 772");
end
5'h1a :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 773");
ozoneae(foo[17:15], fd);
$fwrite (fd," 774");
end
5'h1b :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 775");
ozoneae(foo[17:15], fd);
$fwrite (fd," 776");
if (foo[ 6])
$fwrite (fd," 777");
else
$fwrite (fd," 778");
$fwrite (fd," 779");
end
5'h1c :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 780");
end
5'h1d :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 781");
if (foo[ 6])
$fwrite (fd," 782");
else
$fwrite (fd," 783");
$fwrite (fd," 784");
end
5'h1e :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 785");
if (foo[ 6])
$fwrite (fd," 786");
else
$fwrite (fd," 787");
$fwrite (fd," 788");
end
5'h1f :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 789");
ozoneae(foo[17:15], fd);
$fwrite (fd," 790");
if (foo[ 6])
$fwrite (fd," 791");
else
$fwrite (fd," 792");
$fwrite (fd," 793");
end
default :
$fwrite (fd," 794");
endcase
end
endtask
task ozonef3e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[25:21])
5'h00,
5'h01,
5'h02:
begin
ozoneae(foo[20:18], fd);
case (foo[22:21])
2'h0: $fwrite (fd," 795");
2'h1: $fwrite (fd," 796");
2'h2: $fwrite (fd," 797");
endcase
ozoneae(foo[17:15], fd);
$fwrite (fd," 798");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
$fwrite (fd," 799");
end
5'h08,
5'h09,
5'h0d,
5'h0e,
5'h0f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 800");
ozoneae(foo[17:15], fd);
case (foo[23:21])
3'h0: $fwrite (fd," 801");
3'h1: $fwrite (fd," 802");
3'h5: $fwrite (fd," 803");
3'h6: $fwrite (fd," 804");
3'h7: $fwrite (fd," 805");
endcase
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
end
5'h0a,
5'h0b:
begin
ozoneae(foo[17:15], fd);
if (foo[21])
$fwrite (fd," 806");
else
$fwrite (fd," 807");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
end
5'h0c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 808");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
$fwrite (fd," 809");
ozoneae(foo[17:15], fd);
end
5'h10,
5'h11,
5'h12,
5'h13:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 810");
ozoneae(foo[17:15], fd);
case (foo[22:21])
2'h0,
2'h2:
$fwrite (fd," 811");
2'h1,
2'h3:
$fwrite (fd," 812");
endcase
ozoneae(foo[ 8: 6], fd);
$fwrite (fd," 813");
ozoneae((foo[20:18]+1), fd);
$fwrite (fd," 814");
ozoneae((foo[17:15]+1), fd);
case (foo[22:21])
2'h0,
2'h3:
$fwrite (fd," 815");
2'h1,
2'h2:
$fwrite (fd," 816");
endcase
ozoneae((foo[ 8: 6]+1), fd);
end
5'h18:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 817");
ozoneae(foo[17:15], fd);
$fwrite (fd," 818");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd," 819");
ozoneae(foo[20:18], fd);
$fwrite (fd," 820");
ozoneae(foo[17:15], fd);
$fwrite (fd," 821");
ozoneae(foo[ 8: 6], fd);
end
default :
$fwrite (fd," 822");
endcase
end
endtask
task ozonef3e_te;
input [ 2:0] te;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (te)
3'b100 : $fwrite (fd, " 823");
3'b101 : $fwrite (fd, " 824");
3'b110 : $fwrite (fd, " 825");
default: $fwrite (fd, " 826");
endcase
end
endtask
task ozonearm;
input [ 2:0] ate;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ate)
3'b000 : $fwrite (fd, " 827");
3'b001 : $fwrite (fd, " 828");
3'b010 : $fwrite (fd, " 829");
3'b011 : $fwrite (fd, " 830");
3'b100 : $fwrite (fd, " 831");
3'b101 : $fwrite (fd, " 832");
3'b110 : $fwrite (fd, " 833");
3'b111 : $fwrite (fd, " 834");
endcase
end
endtask
task ozonebmuop;
input [ 4:0] f4;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (f4[ 4:0])
5'h00,
5'h04 :
$fwrite (fd, " 835");
5'h01,
5'h05 :
$fwrite (fd, " 836");
5'h02,
5'h06 :
$fwrite (fd, " 837");
5'h03,
5'h07 :
$fwrite (fd, " 838");
5'h08,
5'h18 :
$fwrite (fd, " 839");
5'h09,
5'h19 :
$fwrite (fd, " 840");
5'h0a,
5'h1a :
$fwrite (fd, " 841");
5'h0b :
$fwrite (fd, " 842");
5'h1b :
$fwrite (fd, " 843");
5'h0c,
5'h1c :
$fwrite (fd, " 844");
5'h0d,
5'h1d :
$fwrite (fd, " 845");
5'h1e :
$fwrite (fd, " 846");
endcase
end
endtask
task ozonef3;
input [ 31:0] foo;
input [`FD_BITS] fd;
reg nacho;
// verilator no_inline_task
begin : f3_body
nacho = 1'b0;
case (foo[24:21])
4'h0:
case (foo[26:25])
2'b00 : $fwrite (fd, " 847");
2'b01 : $fwrite (fd, " 848");
2'b10 : $fwrite (fd, " 849");
2'b11 : $fwrite (fd, " 850");
endcase
4'h1:
case (foo[26:25])
2'b00 : $fwrite (fd, " 851");
2'b01 : $fwrite (fd, " 852");
2'b10 : $fwrite (fd, " 853");
2'b11 : $fwrite (fd, " 854");
endcase
4'h2:
case (foo[26:25])
2'b00 : $fwrite (fd, " 855");
2'b01 : $fwrite (fd, " 856");
2'b10 : $fwrite (fd, " 857");
2'b11 : $fwrite (fd, " 858");
endcase
4'h8,
4'h9,
4'hd,
4'he,
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd, " 859");
2'b01 : $fwrite (fd, " 860");
2'b10 : $fwrite (fd, " 861");
2'b11 : $fwrite (fd, " 862");
endcase
4'ha,
4'hb :
if (foo[25])
$fwrite (fd, " 863");
else
$fwrite (fd, " 864");
4'hc :
if (foo[26])
$fwrite (fd, " 865");
else
$fwrite (fd, " 866");
default :
begin
$fwrite (fd, " 867");
nacho = 1'b1;
end
endcase
if (~nacho)
begin
case (foo[24:21])
4'h8 :
$fwrite (fd, " 868");
4'h9 :
$fwrite (fd, " 869");
4'ha,
4'he :
$fwrite (fd, " 870");
4'hb,
4'hf :
$fwrite (fd, " 871");
4'hd :
$fwrite (fd, " 872");
endcase
if (foo[20])
case (foo[18:16])
3'b000 : $fwrite (fd, " 873");
3'b100 : $fwrite (fd, " 874");
default: $fwrite (fd, " 875");
endcase
else
ozoneae(foo[18:16], fd);
if (foo[24:21] === 4'hc)
if (foo[25])
$fwrite (fd, " 876");
else
$fwrite (fd, " 877");
case (foo[24:21])
4'h0,
4'h1,
4'h2:
$fwrite (fd, " 878");
endcase
end
end
endtask
task ozonerx;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[19:18])
2'h0 : $fwrite (fd, " 879");
2'h1 : $fwrite (fd, " 880");
2'h2 : $fwrite (fd, " 881");
2'h3 : $fwrite (fd, " 882");
endcase
case (foo[17:16])
2'h1 : $fwrite (fd, " 883");
2'h2 : $fwrite (fd, " 884");
2'h3 : $fwrite (fd, " 885");
endcase
end
endtask
task ozonerme;
input [ 2:0] rme;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rme)
3'h0 : $fwrite (fd, " 886");
3'h1 : $fwrite (fd, " 887");
3'h2 : $fwrite (fd, " 888");
3'h3 : $fwrite (fd, " 889");
3'h4 : $fwrite (fd, " 890");
3'h5 : $fwrite (fd, " 891");
3'h6 : $fwrite (fd, " 892");
3'h7 : $fwrite (fd, " 893");
endcase
end
endtask
task ozoneye;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
$fwrite (fd, " 894");
ozonerme(ye[5:3], fd);
case ({ye[ 2:0], l})
4'h2,
4'ha: $fwrite (fd, " 895");
4'h4,
4'hb: $fwrite (fd, " 896");
4'h6,
4'he: $fwrite (fd, " 897");
4'h8,
4'hc: $fwrite (fd, " 898");
endcase
end
endtask
task ozonef1e_ye;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
$fwrite (fd, " 899");
ozonerme(ye[5:3], fd);
ozonef1e_inc_dec(ye[5:0], l , fd);
end
endtask
task ozonef1e_h;
input [ 2:0] e;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
if (e[ 2:0] <= 3'h4)
$fwrite (fd, " 900");
end
endtask
task ozonef1e_inc_dec;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case ({ye[ 2:0], l})
4'h2,
4'h3,
4'ha: $fwrite (fd, " 901");
4'h4,
4'h5,
4'hb: $fwrite (fd, " 902");
4'h6,
4'h7,
4'he: $fwrite (fd, " 903");
4'h8,
4'h9,
4'hc: $fwrite (fd, " 904");
4'hf: $fwrite (fd, " 905");
endcase
end
endtask
task ozonef1e_hl;
input [ 2:0] e;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case ({e[ 2:0], l})
4'h0,
4'h2,
4'h4,
4'h6,
4'h8: $fwrite (fd, " 906");
4'h1,
4'h3,
4'h5,
4'h7,
4'h9: $fwrite (fd, " 907");
endcase
end
endtask
task ozonexe;
input [ 3:0] xe;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (xe[3])
1'b0 : $fwrite (fd, " 908");
1'b1 : $fwrite (fd, " 909");
endcase
case (xe[ 2:0])
3'h1,
3'h5: $fwrite (fd, " 910");
3'h2,
3'h6: $fwrite (fd, " 911");
3'h3,
3'h7: $fwrite (fd, " 912");
3'h4: $fwrite (fd, " 913");
endcase
end
endtask
task ozonerp;
input [ 2:0] rp;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rp)
3'h0 : $fwrite (fd, " 914");
3'h1 : $fwrite (fd, " 915");
3'h2 : $fwrite (fd, " 916");
3'h3 : $fwrite (fd, " 917");
3'h4 : $fwrite (fd, " 918");
3'h5 : $fwrite (fd, " 919");
3'h6 : $fwrite (fd, " 920");
3'h7 : $fwrite (fd, " 921");
endcase
end
endtask
task ozonery;
input [ 3:0] ry;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ry)
4'h0 : $fwrite (fd, " 922");
4'h1 : $fwrite (fd, " 923");
4'h2 : $fwrite (fd, " 924");
4'h3 : $fwrite (fd, " 925");
4'h4 : $fwrite (fd, " 926");
4'h5 : $fwrite (fd, " 927");
4'h6 : $fwrite (fd, " 928");
4'h7 : $fwrite (fd, " 929");
4'h8 : $fwrite (fd, " 930");
4'h9 : $fwrite (fd, " 931");
4'ha : $fwrite (fd, " 932");
4'hb : $fwrite (fd, " 933");
4'hc : $fwrite (fd, " 934");
4'hd : $fwrite (fd, " 935");
4'he : $fwrite (fd, " 936");
4'hf : $fwrite (fd, " 937");
endcase
end
endtask
task ozonearx;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[1:0])
2'h0 : $fwrite (fd, " 938");
2'h1 : $fwrite (fd, " 939");
2'h2 : $fwrite (fd, " 940");
2'h3 : $fwrite (fd, " 941");
endcase
end
endtask
task ozonef3f4imop;
input [ 4:0] f3f4iml;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
casez (f3f4iml)
5'b000??: $fwrite (fd, " 942");
5'b001??: $fwrite (fd, " 943");
5'b?10??: $fwrite (fd, " 944");
5'b0110?: $fwrite (fd, " 945");
5'b01110: $fwrite (fd, " 946");
5'b01111: $fwrite (fd, " 947");
5'b10???: $fwrite (fd, " 948");
5'b11100: $fwrite (fd, " 949");
5'b11101: $fwrite (fd, " 950");
5'b11110: $fwrite (fd, " 951");
5'b11111: $fwrite (fd, " 952");
endcase
end
endtask
task ozonecon;
input [ 4:0] con;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (con)
5'h00 : $fwrite (fd, " 953");
5'h01 : $fwrite (fd, " 954");
5'h02 : $fwrite (fd, " 955");
5'h03 : $fwrite (fd, " 956");
5'h04 : $fwrite (fd, " 957");
5'h05 : $fwrite (fd, " 958");
5'h06 : $fwrite (fd, " 959");
5'h07 : $fwrite (fd, " 960");
5'h08 : $fwrite (fd, " 961");
5'h09 : $fwrite (fd, " 962");
5'h0a : $fwrite (fd, " 963");
5'h0b : $fwrite (fd, " 964");
5'h0c : $fwrite (fd, " 965");
5'h0d : $fwrite (fd, " 966");
5'h0e : $fwrite (fd, " 967");
5'h0f : $fwrite (fd, " 968");
5'h10 : $fwrite (fd, " 969");
5'h11 : $fwrite (fd, " 970");
5'h12 : $fwrite (fd, " 971");
5'h13 : $fwrite (fd, " 972");
5'h14 : $fwrite (fd, " 973");
5'h15 : $fwrite (fd, " 974");
5'h16 : $fwrite (fd, " 975");
5'h17 : $fwrite (fd, " 976");
5'h18 : $fwrite (fd, " 977");
5'h19 : $fwrite (fd, " 978");
5'h1a : $fwrite (fd, " 979");
5'h1b : $fwrite (fd, " 980");
5'h1c : $fwrite (fd, " 981");
5'h1d : $fwrite (fd, " 982");
5'h1e : $fwrite (fd, " 983");
5'h1f : $fwrite (fd, " 984");
endcase
end
endtask
task ozonedr;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[ 9: 6])
4'h0 : $fwrite (fd, " 985");
4'h1 : $fwrite (fd, " 986");
4'h2 : $fwrite (fd, " 987");
4'h3 : $fwrite (fd, " 988");
4'h4 : $fwrite (fd, " 989");
4'h5 : $fwrite (fd, " 990");
4'h6 : $fwrite (fd, " 991");
4'h7 : $fwrite (fd, " 992");
4'h8 : $fwrite (fd, " 993");
4'h9 : $fwrite (fd, " 994");
4'ha : $fwrite (fd, " 995");
4'hb : $fwrite (fd, " 996");
4'hc : $fwrite (fd, " 997");
4'hd : $fwrite (fd, " 998");
4'he : $fwrite (fd, " 999");
4'hf : $fwrite (fd, " 1000");
endcase
end
endtask
task ozoneshift;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[ 4: 3])
2'h0 : $fwrite (fd, " 1001");
2'h1 : $fwrite (fd, " 1002");
2'h2 : $fwrite (fd, " 1003");
2'h3 : $fwrite (fd, " 1004");
endcase
end
endtask
task ozoneacc;
input foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 : $fwrite (fd, " 1005");
2'h1 : $fwrite (fd, " 1006");
endcase
end
endtask
task ozonehl;
input foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 : $fwrite (fd, " 1007");
2'h1 : $fwrite (fd, " 1008");
endcase
end
endtask
task dude;
input [`FD_BITS] fd;
// verilator no_inline_task
$fwrite(fd," dude");
endtask
task big_case;
input [ `FD_BITS] fd;
input [ 31:0] foo;
// verilator no_inline_task
begin
$fwrite(fd," 1009");
if (&foo === 1'bx)
$fwrite(fd, " 1010");
else
casez ( {foo[31:26], foo[19:15], foo[5:0]} )
17'b00_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1011");
ozoneacc(~foo[26], fd);
ozonehl(foo[20], fd);
$fwrite (fd, " 1012");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1013");
end
17'b01_001?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1014");
ozonerx(foo, fd);
$fwrite (fd, " 1015");
$fwrite (fd, " 1016:%x", foo[20]);
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1017");
end
17'b10_100?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1018");
ozonerx(foo, fd);
$fwrite (fd, " 1019");
$fwrite (fd, " 1020");
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1021");
end
17'b10_101?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1022");
if (foo[20])
begin
$fwrite (fd, " 1023");
ozoneacc(foo[18], fd);
$fwrite (fd, " 1024");
$fwrite (fd, " 1025");
if (foo[19])
$fwrite (fd, " 1026");
else
$fwrite (fd, " 1027");
end
else
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1028");
end
17'b10_110?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1029");
$fwrite (fd, " 1030");
ozonehl(foo[20], fd);
$fwrite (fd, " 1031");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1032");
end
17'b10_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1033");
$fwrite (fd, " 1034");
ozonehl(foo[20], fd);
$fwrite (fd, " 1035");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1036");
end
17'b11_001?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1037");
ozonerx(foo, fd);
$fwrite (fd, " 1038");
$fwrite (fd, " 1039");
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1040");
end
17'b11_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1041");
$fwrite (fd, " 1042");
ozonerx(foo, fd);
$fwrite (fd, " 1043");
if (foo[20])
$fwrite (fd, " 1044");
else
$fwrite (fd, " 1045");
dude(fd);
$fwrite (fd, " 1046");
end
17'b00_10??_?_????_?1_1111 :
casez (foo[11: 5])
7'b??_0_010_0:
begin
$fwrite (fd, " 1047");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1048");
ozonef1e(foo, fd);
dude(fd);
$fwrite (fd, " 1049");
end
7'b00_?_110_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1050");
case ({foo[ 9],foo[ 5]})
2'b00:
begin
$fwrite (fd, " 1051");
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
end
2'b01:
begin
$fwrite (fd, " 1052");
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
end
2'b10:
begin
$fwrite (fd, " 1053");
ozoneae(foo[14:12], fd);
end
2'b11: $fwrite (fd, " 1054");
endcase
dude(fd);
$fwrite (fd, " 1055");
end
7'b01_?_110_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1056");
case ({foo[ 9],foo[ 5]})
2'b00:
begin
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
$fwrite (fd, " 1057");
end
2'b01:
begin
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
$fwrite (fd, " 1058");
end
2'b10:
begin
ozoneae(foo[14:12], fd);
$fwrite (fd, " 1059");
end
2'b11: $fwrite (fd, " 1060");
endcase
dude(fd);
$fwrite (fd, " 1061");
end
7'b10_0_110_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1062");
$fwrite (fd, " 1063");
if (foo[12])
$fwrite (fd, " 1064");
else
ozonerab({4'b1001, foo[14:12]}, fd);
dude(fd);
$fwrite (fd, " 1065");
end
7'b10_0_110_1:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1066");
if (foo[12])
$fwrite (fd, " 1067");
else
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1068");
dude(fd);
$fwrite (fd, " 1069");
end
7'b??_?_000_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1070");
$fwrite (fd, " 1071");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1072");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1073");
end
7'b??_?_100_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1074");
$fwrite (fd, " 1075");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1076");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1077");
end
7'b??_?_001_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1078");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1079");
$fwrite (fd, " 1080");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1081");
end
7'b??_?_011_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1082");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1083");
$fwrite (fd, " 1084");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1085");
end
7'b??_?_101_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1086");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1087");
end
endcase
17'b00_10??_?_????_?0_0110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1088");
ozoneae(foo[ 8: 6], fd);
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1089");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1090");
end
17'b00_10??_?_????_00_0111 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1091");
if (foo[ 6])
$fwrite (fd, " 1092");
else
ozonerab({4'b1001, foo[ 8: 6]}, fd);
$fwrite (fd, " 1093");
$fwrite (fd, " 1094");
ozonerme(foo[14:12], fd);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0, fd);
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1095");
endcase
dude(fd);
$fwrite (fd, " 1096");
end
17'b00_10??_?_????_?0_0100 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1097");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1098");
ozoneae(foo[ 8: 6], fd);
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1099");
end
17'b00_10??_?_????_10_0111 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1100");
$fwrite (fd, " 1101");
ozonerme(foo[14:12], fd);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0, fd);
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1102");
endcase
$fwrite (fd, " 1103");
if (foo[ 6])
$fwrite (fd, " 1104");
else
ozonerab({4'b1001, foo[ 8: 6]}, fd);
dude(fd);
$fwrite (fd, " 1105");
end
17'b00_10??_?_????_?0_1110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1106");
case (foo[11:9])
3'h2:
begin
$fwrite (fd, " 1107");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1108");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1109");
end
3'h6:
begin
$fwrite (fd, " 1110");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1111");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1112");
end
3'h0:
begin
$fwrite (fd, " 1113");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1114");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1115");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1116");
else
ozonexe(foo[ 8: 5], fd);
end
3'h1:
begin
$fwrite (fd, " 1117");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1118");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1119");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1120");
else
ozonexe(foo[ 8: 5], fd);
end
3'h4:
begin
$fwrite (fd, " 1121");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1122");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1123");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1124");
else
ozonexe(foo[ 8: 5], fd);
end
3'h5:
begin
$fwrite (fd, " 1125");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1126");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1127");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1128");
else
ozonexe(foo[ 8: 5], fd);
end
endcase
dude(fd);
$fwrite (fd, " 1129");
end
17'b00_10??_?_????_?0_1111 :
casez (foo[14: 9])
6'b001_10_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1130");
$fwrite (fd, " 1131");
ozonef1e_hl(foo[ 7: 5],foo[ 9], fd);
$fwrite (fd, " 1132");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1133");
end
6'b???_11_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1134");
ozoneae(foo[14:12], fd);
ozonef1e_hl(foo[ 7: 5],foo[ 9], fd);
$fwrite (fd, " 1135");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1136");
end
6'b000_10_1,
6'b010_10_1,
6'b100_10_1,
6'b110_10_1:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1137");
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1138");
if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3))
$fwrite (fd, " 1139");
else
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1140");
end
6'b000_10_0,
6'b010_10_0,
6'b100_10_0,
6'b110_10_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1141");
$fwrite (fd, " 1142");
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1143");
$fwrite (fd, " 1144");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1145");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1146");
end
6'b???_00_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1147");
if (foo[ 9])
begin
$fwrite (fd, " 1148");
ozoneae(foo[14:12], fd);
end
else
begin
$fwrite (fd, " 1149");
ozoneae(foo[14:12], fd);
$fwrite (fd, " 1150");
end
$fwrite (fd, " 1151");
$fwrite (fd, " 1152");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1153");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1154");
end
6'b???_01_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1155");
ozoneae(foo[14:12], fd);
if (foo[ 9])
$fwrite (fd, " 1156");
else
$fwrite (fd, " 1157");
$fwrite (fd, " 1158");
$fwrite (fd, " 1159");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1160");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1161");
end
6'b011_10_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1162");
case (foo[ 8: 5])
4'h0: $fwrite (fd, " 1163");
4'h1: $fwrite (fd, " 1164");
4'h2: $fwrite (fd, " 1165");
4'h3: $fwrite (fd, " 1166");
4'h4: $fwrite (fd, " 1167");
4'h5: $fwrite (fd, " 1168");
4'h8: $fwrite (fd, " 1169");
4'h9: $fwrite (fd, " 1170");
4'ha: $fwrite (fd, " 1171");
4'hb: $fwrite (fd, " 1172");
4'hc: $fwrite (fd, " 1173");
4'hd: $fwrite (fd, " 1174");
default: $fwrite (fd, " 1175");
endcase
dude(fd);
$fwrite (fd, " 1176");
end
default: $fwrite (fd, " 1177");
endcase
17'b00_10??_?_????_?0_110? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1178");
$fwrite (fd, " 1179");
ozonef1e_hl(foo[11:9], foo[0], fd);
$fwrite (fd, " 1180");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1181");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1182");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1183");
end
17'b00_10??_?_????_?1_110? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1184");
$fwrite (fd, " 1185");
ozonef1e_hl(foo[11:9],foo[0], fd);
$fwrite (fd, " 1186");
ozonef1e_ye(foo[14:9],foo[ 0], fd);
$fwrite (fd, " 1187");
$fwrite (fd, " 1188");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1189");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1190");
end
17'b00_10??_?_????_?0_101? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1191");
ozonef1e_ye(foo[14:9],foo[ 0], fd);
$fwrite (fd, " 1192");
$fwrite (fd, " 1193");
ozonef1e_hl(foo[11:9],foo[0], fd);
$fwrite (fd, " 1194");
$fwrite (fd, " 1195");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1196");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1197");
end
17'b00_10??_?_????_?0_1001 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1198");
$fwrite (fd, " 1199");
ozonef1e_h(foo[11:9], fd);
$fwrite (fd, " 1200");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1201");
case (foo[ 7: 5])
3'h1,
3'h2,
3'h3:
$fwrite (fd, " 1202");
default:
begin
$fwrite (fd, " 1203");
$fwrite (fd, " 1204");
ozonexe(foo[ 8: 5], fd);
end
endcase
dude(fd);
$fwrite (fd, " 1205");
end
17'b00_10??_?_????_?0_0101 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1206");
case (foo[11: 9])
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1207");
default:
begin
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1208");
$fwrite (fd, " 1209");
end
endcase
$fwrite (fd, " 1210");
$fwrite (fd, " 1211");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1212");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1213");
end
17'b00_10??_?_????_?1_1110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1214");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1215");
$fwrite (fd, " 1216");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1217");
$fwrite (fd, " 1218");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1219");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1220");
end
17'b00_10??_?_????_?0_1000 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1221");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1222");
$fwrite (fd, " 1223");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1224");
$fwrite (fd, " 1225");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1226");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1227");
end
17'b10_01??_?_????_??_???? :
begin
if (foo[27])
$fwrite (fd," 1228");
else
$fwrite (fd," 1229");
ozonecon(foo[20:16], fd);
$fwrite (fd, " 1230");
ozonef2(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1231");
end
17'b00_1000_?_????_01_0011 :
if (~|foo[ 9: 8])
begin
if (foo[ 7])
$fwrite (fd," 1232");
else
$fwrite (fd," 1233");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1234");
ozonef2e(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1235");
end
else
begin
$fwrite (fd, " 1236");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1237");
ozonef3e(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1238");
end
17'b11_110?_1_????_??_???? :
begin
ozonef3(foo[31:0], fd);
dude(fd);
$fwrite(fd, " 1239");
end
17'b11_110?_0_????_??_???? :
begin : f4_body
casez (foo[24:20])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite (fd, " 1240");
end
5'b0_00??:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1241");
ozoneacc(foo[25], fd);
ozonebmuop(foo[24:20], fd);
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1242");
dude(fd);
$fwrite(fd, " 1243");
end
5'b0_01??:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1244");
ozoneacc(foo[25], fd);
ozonebmuop(foo[24:20], fd);
ozonearm(foo[18:16], fd);
dude(fd);
$fwrite(fd, " 1245");
end
5'b0_1011:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1246");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1247");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1248");
dude(fd);
$fwrite(fd, " 1249");
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1250");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1251");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1252");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1253");
dude(fd);
$fwrite(fd, " 1254");
end
5'b0_1111 :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1255");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1256");
ozoneae(foo[18:16], fd);
dude(fd);
$fwrite(fd, " 1257");
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1258");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1259");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1260");
ozonearm(foo[18:16], fd);
$fwrite (fd, " 1261");
dude(fd);
$fwrite(fd, " 1262");
end
endcase
end
17'b11_100?_?_????_??_???? :
casez (foo[23:19])
5'b111??,
5'b0111?:
begin
ozoneae(foo[26:24], fd);
$fwrite (fd, " 1263");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1264");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1265");
skyway(foo[15:12], fd);
skyway(foo[11: 8], fd);
skyway(foo[ 7: 4], fd);
skyway(foo[ 3:0], fd);
$fwrite (fd, " 1266");
dude(fd);
$fwrite(fd, " 1267");
end
5'b?0???,
5'b110??:
begin
ozoneae(foo[26:24], fd);
$fwrite (fd, " 1268");
if (foo[23:21] == 3'b100)
$fwrite (fd, " 1269");
ozoneae(foo[18:16], fd);
if (foo[19])
$fwrite (fd, " 1270");
else
$fwrite (fd, " 1271");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1272");
ozonef3f4_iext(foo[20:19], foo[15:0], fd);
dude(fd);
$fwrite(fd, " 1273");
end
5'b010??,
5'b0110?:
begin
ozoneae(foo[18:16], fd);
if (foo[19])
$fwrite (fd, " 1274");
else
$fwrite (fd, " 1275");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1276");
ozonef3f4_iext(foo[20:19], foo[15:0], fd);
dude(fd);
$fwrite(fd, " 1277");
end
endcase
17'b00_1000_?_????_11_0011 :
begin
$fwrite (fd," 1278");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1279");
casez (foo[25:21])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite(fd, " 1280");
end
5'b0_00??:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1281");
ozoneae(foo[17:15], fd);
ozonebmuop(foo[25:21], fd);
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1282");
dude(fd);
$fwrite(fd, " 1283");
end
5'b0_01??:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1284");
ozoneae(foo[17:15], fd);
ozonebmuop(foo[25:21], fd);
ozonearm(foo[ 8: 6], fd);
dude(fd);
$fwrite(fd, " 1285");
end
5'b0_1011:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1286");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1287");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1288");
dude(fd);
$fwrite(fd, " 1289");
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1290");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1291");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1292");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1293");
dude(fd);
$fwrite(fd, " 1294");
end
5'b0_1111 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1295");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1296");
ozoneae(foo[ 8: 6], fd);
dude(fd);
$fwrite(fd, " 1297");
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1298");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1299");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1300");
ozonearm(foo[ 8: 6], fd);
$fwrite (fd, " 1301");
dude(fd);
$fwrite(fd, " 1302");
end
endcase
end
17'b00_0010_?_????_??_???? :
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1303");
skyway(foo[19:16], fd);
dude(fd);
$fwrite(fd, " 1304");
end
17'b00_01??_?_????_??_???? :
begin
if (foo[27])
begin
$fwrite (fd, " 1305");
if (foo[26])
$fwrite (fd, " 1306");
else
$fwrite (fd, " 1307");
skyway(foo[19:16], fd);
$fwrite (fd, " 1308");
ozonerab({1'b0, foo[25:20]}, fd);
end
else
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1309");
if (foo[26])
$fwrite (fd, " 1310");
else
$fwrite (fd, " 1311");
skyway(foo[19:16], fd);
$fwrite (fd, " 1312");
end
dude(fd);
$fwrite(fd, " 1313");
end
17'b01_000?_?_????_??_???? :
begin
if (foo[26])
begin
ozonerb(foo[25:20], fd);
$fwrite (fd, " 1314");
ozoneae(foo[18:16], fd);
ozonehl(foo[19], fd);
end
else
begin
ozoneae(foo[18:16], fd);
ozonehl(foo[19], fd);
$fwrite (fd, " 1315");
ozonerb(foo[25:20], fd);
end
dude(fd);
$fwrite(fd, " 1316");
end
17'b01_10??_?_????_??_???? :
begin
if (foo[27])
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1317");
ozonerx(foo, fd);
end
else
begin
ozonerx(foo, fd);
$fwrite (fd, " 1318");
ozonerab({1'b0, foo[25:20]}, fd);
end
dude(fd);
$fwrite(fd, " 1319");
end
17'b11_101?_?_????_??_???? :
begin
ozonerab (foo[26:20], fd);
$fwrite (fd, " 1320");
skyway(foo[19:16], fd);
skyway(foo[15:12], fd);
skyway(foo[11: 8], fd);
skyway(foo[ 7: 4], fd);
skyway(foo[ 3: 0], fd);
dude(fd);
$fwrite(fd, " 1321");
end
17'b11_0000_?_????_??_???? :
begin
casez (foo[25:23])
3'b00?:
begin
ozonerab(foo[22:16], fd);
$fwrite (fd, " 1322");
end
3'b01?:
begin
$fwrite (fd, " 1323");
if (foo[22:16]>=7'h60)
$fwrite (fd, " 1324");
else
ozonerab(foo[22:16], fd);
end
3'b110:
$fwrite (fd, " 1325");
3'b10?:
begin
$fwrite (fd, " 1326");
if (foo[22:16]>=7'h60)
$fwrite (fd, " 1327");
else
ozonerab(foo[22:16], fd);
end
3'b111:
begin
$fwrite (fd, " 1328");
ozonerab(foo[22:16], fd);
$fwrite (fd, " 1329");
end
endcase
dude(fd);
$fwrite(fd, " 1330");
end
17'b00_10??_?_????_?1_0000 :
begin
if (foo[27])
begin
$fwrite (fd, " 1331");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1332");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
$fwrite (fd, " 1333");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1334");
else
ozonerab(foo[26:20], fd);
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1335");
$fwrite (fd, " 1336");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1337");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
$fwrite (fd, " 1338");
end
dude(fd);
$fwrite(fd, " 1339");
end
17'b00_101?_1_0000_?1_0010 :
if (~|foo[11: 7])
begin
if (foo[ 6])
begin
$fwrite (fd, " 1340");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1341");
ozonejk(foo[ 5], fd);
$fwrite (fd, " 1342");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1343");
else
ozonerab(foo[26:20], fd);
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1344");
$fwrite (fd, " 1345");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1346");
ozonejk(foo[ 5], fd);
$fwrite (fd, " 1347");
end
dude(fd);
$fwrite(fd, " 1348");
end
else
$fwrite(fd, " 1349");
17'b00_100?_0_0011_?1_0101 :
if (~|foo[ 8: 7])
begin
if (foo[6])
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1350");
ozoneye(foo[14: 9],foo[ 5], fd);
end
else
begin
ozoneye(foo[14: 9],foo[ 5], fd);
$fwrite (fd, " 1351");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1352");
else
ozonerab(foo[26:20], fd);
end
dude(fd);
$fwrite(fd, " 1353");
end
else
$fwrite(fd, " 1354");
17'b00_1001_0_0000_?1_0010 :
if (~|foo[25:20])
begin
ozoneye(foo[14: 9],1'b0, fd);
$fwrite (fd, " 1355");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1356");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1357");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1358");
end
else
$fwrite(fd, " 1359");
17'b00_101?_0_????_?1_0010 :
if (~foo[13])
begin
if (foo[12])
begin
$fwrite (fd, " 1360");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1361");
else
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1362");
$fwrite (fd, " 1363");
skyway({1'b0,foo[18:16]}, fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1364");
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1365");
$fwrite (fd, " 1366");
skyway({1'b0,foo[18:16]}, fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1367");
end
end
else
$fwrite(fd, " 1368");
17'b01_01??_?_????_??_???? :
begin
ozonerab({1'b0,foo[27:26],foo[19:16]}, fd);
$fwrite (fd, " 1369");
ozonerab({1'b0,foo[25:20]}, fd);
dude(fd);
$fwrite(fd, " 1370");
end
17'b00_100?_?_???0_11_0101 :
if (~foo[6])
begin
$fwrite (fd," 1371");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1372");
ozonerab({foo[ 9: 7],foo[19:16]}, fd);
$fwrite (fd, " 1373");
ozonerab({foo[26:20]}, fd);
dude(fd);
$fwrite(fd, " 1374");
end
else
$fwrite(fd, " 1375");
17'b00_1000_?_????_?1_0010 :
if (~|foo[25:24])
begin
ozonery(foo[23:20], fd);
$fwrite (fd, " 1376");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1377");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1378");
end
else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6])
begin
ozonery(foo[23:20], fd);
$fwrite (fd, " 1379");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1380");
ozonejk(foo[ 5], fd);
dude(fd);
$fwrite(fd, " 1381");
end
else
$fwrite(fd, " 1382");
17'b11_01??_?_????_??_????,
17'b10_00??_?_????_??_???? :
if (foo[30])
$fwrite(fd, " 1383:%x", foo[27:16]);
else
$fwrite(fd, " 1384:%x", foo[27:16]);
17'b00_10??_?_????_01_1000 :
if (~foo[6])
begin
if (foo[7])
$fwrite(fd, " 1385:%x", foo[27: 8]);
else
$fwrite(fd, " 1386:%x", foo[27: 8]);
end
else
$fwrite(fd, " 1387");
17'b00_10??_?_????_11_1000 :
begin
$fwrite (fd," 1388");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1389");
if (foo[15])
$fwrite (fd, " 1390");
else
$fwrite (fd, " 1391");
skyway(foo[27:24], fd);
skyway(foo[23:20], fd);
skyway(foo[19:16], fd);
skyway(foo[ 9: 6], fd);
dude(fd);
$fwrite(fd, " 1392");
end
17'b11_0001_?_????_??_???? :
casez (foo[25:22])
4'b01?? :
begin
$fwrite (fd," 1393");
ozonecon(foo[20:16], fd);
case (foo[23:21])
3'h0 : $fwrite (fd, " 1394");
3'h1 : $fwrite (fd, " 1395");
3'h2 : $fwrite (fd, " 1396");
3'h3 : $fwrite (fd, " 1397");
3'h4 : $fwrite (fd, " 1398");
3'h5 : $fwrite (fd, " 1399");
3'h6 : $fwrite (fd, " 1400");
3'h7 : $fwrite (fd, " 1401");
endcase
dude(fd);
$fwrite(fd, " 1402");
end
4'b0000 :
$fwrite(fd, " 1403:%x", foo[21:16]);
4'b0010 :
if (~|foo[21:16])
$fwrite(fd, " 1404");
4'b1010 :
if (~|foo[21:17])
begin
if (foo[16])
$fwrite(fd, " 1405");
else
$fwrite(fd, " 1406");
end
default :
$fwrite(fd, " 1407");
endcase
17'b01_11??_?_????_??_???? :
if (foo[27:23] === 5'h00)
$fwrite(fd, " 1408:%x", foo[22:16]);
else
$fwrite(fd, " 1409:%x", foo[22:16]);
default: $fwrite(fd, " 1410");
endcase
end
endtask
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil)
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil)
endmodule
|
module t_case_write2_tasks ();
// verilator lint_off WIDTH
// verilator lint_off CASEINCOMPLETE
`define FD_BITS 31:0
parameter STRLEN = 78;
task ozonerab;
input [6:0] rab;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rab[6:0])
7'h00 : $fwrite (fd, " 0");
7'h01 : $fwrite (fd, " 1");
7'h02 : $fwrite (fd, " 2");
7'h03 : $fwrite (fd, " 3");
7'h04 : $fwrite (fd, " 4");
7'h05 : $fwrite (fd, " 5");
7'h06 : $fwrite (fd, " 6");
7'h07 : $fwrite (fd, " 7");
7'h08 : $fwrite (fd, " 8");
7'h09 : $fwrite (fd, " 9");
7'h0a : $fwrite (fd, " 10");
7'h0b : $fwrite (fd, " 11");
7'h0c : $fwrite (fd, " 12");
7'h0d : $fwrite (fd, " 13");
7'h0e : $fwrite (fd, " 14");
7'h0f : $fwrite (fd, " 15");
7'h10 : $fwrite (fd, " 16");
7'h11 : $fwrite (fd, " 17");
7'h12 : $fwrite (fd, " 18");
7'h13 : $fwrite (fd, " 19");
7'h14 : $fwrite (fd, " 20");
7'h15 : $fwrite (fd, " 21");
7'h16 : $fwrite (fd, " 22");
7'h17 : $fwrite (fd, " 23");
7'h18 : $fwrite (fd, " 24");
7'h19 : $fwrite (fd, " 25");
7'h1a : $fwrite (fd, " 26");
7'h1b : $fwrite (fd, " 27");
7'h1c : $fwrite (fd, " 28");
7'h1d : $fwrite (fd, " 29");
7'h1e : $fwrite (fd, " 30");
7'h1f : $fwrite (fd, " 31");
7'h20 : $fwrite (fd, " 32");
7'h21 : $fwrite (fd, " 33");
7'h22 : $fwrite (fd, " 34");
7'h23 : $fwrite (fd, " 35");
7'h24 : $fwrite (fd, " 36");
7'h25 : $fwrite (fd, " 37");
7'h26 : $fwrite (fd, " 38");
7'h27 : $fwrite (fd, " 39");
7'h28 : $fwrite (fd, " 40");
7'h29 : $fwrite (fd, " 41");
7'h2a : $fwrite (fd, " 42");
7'h2b : $fwrite (fd, " 43");
7'h2c : $fwrite (fd, " 44");
7'h2d : $fwrite (fd, " 45");
7'h2e : $fwrite (fd, " 46");
7'h2f : $fwrite (fd, " 47");
7'h30 : $fwrite (fd, " 48");
7'h31 : $fwrite (fd, " 49");
7'h32 : $fwrite (fd, " 50");
7'h33 : $fwrite (fd, " 51");
7'h34 : $fwrite (fd, " 52");
7'h35 : $fwrite (fd, " 53");
7'h36 : $fwrite (fd, " 54");
7'h37 : $fwrite (fd, " 55");
7'h38 : $fwrite (fd, " 56");
7'h39 : $fwrite (fd, " 57");
7'h3a : $fwrite (fd, " 58");
7'h3b : $fwrite (fd, " 59");
7'h3c : $fwrite (fd, " 60");
7'h3d : $fwrite (fd, " 61");
7'h3e : $fwrite (fd, " 62");
7'h3f : $fwrite (fd, " 63");
7'h40 : $fwrite (fd, " 64");
7'h41 : $fwrite (fd, " 65");
7'h42 : $fwrite (fd, " 66");
7'h43 : $fwrite (fd, " 67");
7'h44 : $fwrite (fd, " 68");
7'h45 : $fwrite (fd, " 69");
7'h46 : $fwrite (fd, " 70");
7'h47 : $fwrite (fd, " 71");
7'h48 : $fwrite (fd, " 72");
7'h49 : $fwrite (fd, " 73");
7'h4a : $fwrite (fd, " 74");
7'h4b : $fwrite (fd, " 75");
7'h4c : $fwrite (fd, " 76");
7'h4d : $fwrite (fd, " 77");
7'h4e : $fwrite (fd, " 78");
7'h4f : $fwrite (fd, " 79");
7'h50 : $fwrite (fd, " 80");
7'h51 : $fwrite (fd, " 81");
7'h52 : $fwrite (fd, " 82");
7'h53 : $fwrite (fd, " 83");
7'h54 : $fwrite (fd, " 84");
7'h55 : $fwrite (fd, " 85");
7'h56 : $fwrite (fd, " 86");
7'h57 : $fwrite (fd, " 87");
7'h58 : $fwrite (fd, " 88");
7'h59 : $fwrite (fd, " 89");
7'h5a : $fwrite (fd, " 90");
7'h5b : $fwrite (fd, " 91");
7'h5c : $fwrite (fd, " 92");
7'h5d : $fwrite (fd, " 93");
7'h5e : $fwrite (fd, " 94");
7'h5f : $fwrite (fd, " 95");
7'h60 : $fwrite (fd, " 96");
7'h61 : $fwrite (fd, " 97");
7'h62 : $fwrite (fd, " 98");
7'h63 : $fwrite (fd, " 99");
7'h64 : $fwrite (fd, " 100");
7'h65 : $fwrite (fd, " 101");
7'h66 : $fwrite (fd, " 102");
7'h67 : $fwrite (fd, " 103");
7'h68 : $fwrite (fd, " 104");
7'h69 : $fwrite (fd, " 105");
7'h6a : $fwrite (fd, " 106");
7'h6b : $fwrite (fd, " 107");
7'h6c : $fwrite (fd, " 108");
7'h6d : $fwrite (fd, " 109");
7'h6e : $fwrite (fd, " 110");
7'h6f : $fwrite (fd, " 111");
7'h70 : $fwrite (fd, " 112");
7'h71 : $fwrite (fd, " 113");
7'h72 : $fwrite (fd, " 114");
7'h73 : $fwrite (fd, " 115");
7'h74 : $fwrite (fd, " 116");
7'h75 : $fwrite (fd, " 117");
7'h76 : $fwrite (fd, " 118");
7'h77 : $fwrite (fd, " 119");
7'h78 : $fwrite (fd, " 120");
7'h79 : $fwrite (fd, " 121");
7'h7a : $fwrite (fd, " 122");
7'h7b : $fwrite (fd, " 123");
7'h7c : $fwrite (fd, " 124");
7'h7d : $fwrite (fd, " 125");
7'h7e : $fwrite (fd, " 126");
7'h7f : $fwrite (fd, " 127");
default:$fwrite (fd, " 128");
endcase
end
endtask
task ozonerb;
input [5:0] rb;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rb[5:0])
6'h10,
6'h17,
6'h1e,
6'h1f: $fwrite (fd, " 129");
default: ozonerab({1'b1, rb}, fd);
endcase
end
endtask
task ozonef3f4_iext;
input [1:0] foo;
input [15:0] im16;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 :
begin
skyway({4{im16[15]}}, fd);
skyway({4{im16[15]}}, fd);
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
$fwrite (fd, " 130");
end
2'h1 :
begin
$fwrite (fd, " 131");
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
end
2'h2 :
begin
skyway({4{im16[15]}}, fd);
skyway({4{im16[15]}}, fd);
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
$fwrite (fd, " 132");
end
2'h3 :
begin
$fwrite (fd, " 133");
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
end
endcase
end
endtask
task skyway;
input [ 3:0] hex;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (hex)
4'h0 : $fwrite (fd, " 134");
4'h1 : $fwrite (fd, " 135");
4'h2 : $fwrite (fd, " 136");
4'h3 : $fwrite (fd, " 137");
4'h4 : $fwrite (fd, " 138");
4'h5 : $fwrite (fd, " 139");
4'h6 : $fwrite (fd, " 140");
4'h7 : $fwrite (fd, " 141");
4'h8 : $fwrite (fd, " 142");
4'h9 : $fwrite (fd, " 143");
4'ha : $fwrite (fd, " 144");
4'hb : $fwrite (fd, " 145");
4'hc : $fwrite (fd, " 146");
4'hd : $fwrite (fd, " 147");
4'he : $fwrite (fd, " 148");
4'hf : $fwrite (fd, " 149");
endcase
end
endtask
task ozonesr;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[11: 9])
3'h0 : $fwrite (fd, " 158");
3'h1 : $fwrite (fd, " 159");
3'h2 : $fwrite (fd, " 160");
3'h3 : $fwrite (fd, " 161");
3'h4 : $fwrite (fd, " 162");
3'h5 : $fwrite (fd, " 163");
3'h6 : $fwrite (fd, " 164");
3'h7 : $fwrite (fd, " 165");
endcase
end
endtask
task ozonejk;
input k;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
if (k)
$fwrite (fd, " 166");
else
$fwrite (fd, " 167");
end
endtask
task ozoneae;
input [ 2:0] ae;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ae)
3'b000 : $fwrite (fd, " 168");
3'b001 : $fwrite (fd, " 169");
3'b010 : $fwrite (fd, " 170");
3'b011 : $fwrite (fd, " 171");
3'b100 : $fwrite (fd, " 172");
3'b101 : $fwrite (fd, " 173");
3'b110 : $fwrite (fd, " 174");
3'b111 : $fwrite (fd, " 175");
endcase
end
endtask
task ozoneaee;
input [ 2:0] aee;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (aee)
3'b001,
3'b011,
3'b101,
3'b111 : $fwrite (fd, " 176");
3'b000 : $fwrite (fd, " 177");
3'b010 : $fwrite (fd, " 178");
3'b100 : $fwrite (fd, " 179");
3'b110 : $fwrite (fd, " 180");
endcase
end
endtask
task ozoneape;
input [ 2:0] ape;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ape)
3'b001,
3'b011,
3'b101,
3'b111 : $fwrite (fd, " 181");
3'b000 : $fwrite (fd, " 182");
3'b010 : $fwrite (fd, " 183");
3'b100 : $fwrite (fd, " 184");
3'b110 : $fwrite (fd, " 185");
endcase
end
endtask
task ozonef1;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
if (foo[26])
$fwrite (fd, " 186");
else
$fwrite (fd, " 187");
4'h1 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 188");
2'b01 : $fwrite (fd, " 189");
2'b10 : $fwrite (fd, " 190");
2'b11 : $fwrite (fd, " 191");
endcase
4'h2 : $fwrite (fd, " 192");
4'h3 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 193");
2'b01 : $fwrite (fd, " 194");
2'b10 : $fwrite (fd, " 195");
2'b11 : $fwrite (fd, " 196");
endcase
4'h4 :
if (foo[26])
$fwrite (fd, " 197");
else
$fwrite (fd, " 198");
4'h5 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 199");
2'b01 : $fwrite (fd, " 200");
2'b10 : $fwrite (fd, " 201");
2'b11 : $fwrite (fd, " 202");
endcase
4'h6 : $fwrite (fd, " 203");
4'h7 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 204");
2'b01 : $fwrite (fd, " 205");
2'b10 : $fwrite (fd, " 206");
2'b11 : $fwrite (fd, " 207");
endcase
4'h8 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 208");
2'b01 : $fwrite (fd, " 209");
2'b10 : $fwrite (fd, " 210");
2'b11 : $fwrite (fd, " 211");
endcase
4'h9 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 212");
2'b01 : $fwrite (fd, " 213");
2'b10 : $fwrite (fd, " 214");
2'b11 : $fwrite (fd, " 215");
endcase
4'ha :
if (foo[25])
$fwrite (fd, " 216");
else
$fwrite (fd, " 217");
4'hb :
if (foo[25])
$fwrite (fd, " 218");
else
$fwrite (fd, " 219");
4'hc :
if (foo[26])
$fwrite (fd, " 220");
else
$fwrite (fd, " 221");
4'hd :
case (foo[26:25])
2'b00 : $fwrite (fd, " 222");
2'b01 : $fwrite (fd, " 223");
2'b10 : $fwrite (fd, " 224");
2'b11 : $fwrite (fd, " 225");
endcase
4'he :
case (foo[26:25])
2'b00 : $fwrite (fd, " 226");
2'b01 : $fwrite (fd, " 227");
2'b10 : $fwrite (fd, " 228");
2'b11 : $fwrite (fd, " 229");
endcase
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd, " 230");
2'b01 : $fwrite (fd, " 231");
2'b10 : $fwrite (fd, " 232");
2'b11 : $fwrite (fd, " 233");
endcase
endcase
end
endtask
task ozonef1e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[27:21])
7'h00:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 234");
$fwrite (fd, " 235");
end
7'h01:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 236");
ozoneae(foo[17:15], fd);
$fwrite (fd," 237");
$fwrite (fd, " 238");
end
7'h02:
$fwrite (fd, " 239");
7'h03:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 240");
ozoneae(foo[17:15], fd);
$fwrite (fd," 241");
$fwrite (fd, " 242");
end
7'h04:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 243");
$fwrite (fd," 244");
end
7'h05:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 245");
ozoneae(foo[17:15], fd);
$fwrite (fd," 246");
end
7'h06:
$fwrite (fd, " 247");
7'h07:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 248");
ozoneae(foo[17:15], fd);
$fwrite (fd," 249");
end
7'h08:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 250");
ozoneae(foo[17:15], fd);
$fwrite (fd," 251");
end
7'h09:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 252");
ozoneae(foo[17:15], fd);
$fwrite (fd," 253");
end
7'h0a:
begin
ozoneae(foo[17:15], fd);
$fwrite (fd," 254");
end
7'h0b:
begin
ozoneae(foo[17:15], fd);
$fwrite (fd," 255");
end
7'h0c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 256");
end
7'h0d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 257");
ozoneae(foo[17:15], fd);
$fwrite (fd," 258");
end
7'h0e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 259");
ozoneae(foo[17:15], fd);
$fwrite (fd," 260");
end
7'h0f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 261");
ozoneae(foo[17:15], fd);
$fwrite (fd," 262");
end
7'h10:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 263");
ozoneae(foo[17:15], fd);
$fwrite (fd," 264");
$fwrite (fd, " 265");
$fwrite (fd, " 266");
end
7'h11:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 267");
ozoneae(foo[17:15], fd);
$fwrite (fd," 268");
$fwrite (fd, " 269");
$fwrite (fd, " 270");
end
7'h12:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 271");
ozoneae(foo[17:15], fd);
$fwrite (fd," 272");
$fwrite (fd, " 273");
$fwrite (fd, " 274");
end
7'h13:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 275");
ozoneae(foo[17:15], fd);
$fwrite (fd," 276");
$fwrite (fd, " 277");
$fwrite (fd, " 278");
end
7'h14:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 279");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 280");
ozoneape(foo[20:18], fd);
$fwrite (fd," 281");
ozoneape(foo[17:15], fd);
$fwrite (fd," 282");
$fwrite (fd, " 283");
$fwrite (fd, " 284");
end
7'h15:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 285");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 286");
ozoneape(foo[20:18], fd);
$fwrite (fd," 287");
ozoneape(foo[17:15], fd);
$fwrite (fd," 288");
$fwrite (fd, " 289");
$fwrite (fd, " 290");
end
7'h16:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 291");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 292");
ozoneape(foo[20:18], fd);
$fwrite (fd," 293");
ozoneape(foo[17:15], fd);
$fwrite (fd," 294");
$fwrite (fd, " 295");
$fwrite (fd, " 296");
end
7'h17:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 297");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 298");
ozoneape(foo[20:18], fd);
$fwrite (fd," 299");
ozoneape(foo[17:15], fd);
$fwrite (fd," 300");
$fwrite (fd, " 301");
$fwrite (fd, " 302");
end
7'h18:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 303");
ozoneae(foo[17:15], fd);
$fwrite (fd," 304");
$fwrite (fd, " 305");
$fwrite (fd, " 306");
end
7'h19:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 307");
ozoneae(foo[17:15], fd);
$fwrite (fd," 308");
$fwrite (fd, " 309");
$fwrite (fd, " 310");
end
7'h1a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 311");
ozoneae(foo[17:15], fd);
$fwrite (fd," 312");
$fwrite (fd, " 313");
$fwrite (fd, " 314");
end
7'h1b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 315");
ozoneae(foo[17:15], fd);
$fwrite (fd," 316");
$fwrite (fd, " 317");
$fwrite (fd, " 318");
end
7'h1c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 319");
ozoneae(foo[17:15], fd);
$fwrite (fd," 320");
$fwrite (fd, " 321");
$fwrite (fd, " 322");
end
7'h1d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 323");
ozoneae(foo[17:15], fd);
$fwrite (fd," 324");
$fwrite (fd, " 325");
$fwrite (fd, " 326");
end
7'h1e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 327");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 328");
ozoneape(foo[20:18], fd);
$fwrite (fd," 329");
ozoneape(foo[17:15], fd);
$fwrite (fd," 330");
$fwrite (fd, " 331");
$fwrite (fd, " 332");
end
7'h1f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 333");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 334");
ozoneape(foo[20:18], fd);
$fwrite (fd," 335");
ozoneape(foo[17:15], fd);
$fwrite (fd," 336");
$fwrite (fd, " 337");
$fwrite (fd, " 338");
end
7'h20:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 339");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 340");
ozoneape(foo[20:18], fd);
$fwrite (fd," 341");
ozoneape(foo[17:15], fd);
$fwrite (fd," 342");
$fwrite (fd, " 343");
$fwrite (fd, " 344");
end
7'h21:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 345");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 346");
ozoneape(foo[20:18], fd);
$fwrite (fd," 347");
ozoneape(foo[17:15], fd);
$fwrite (fd," 348");
$fwrite (fd, " 349");
$fwrite (fd, " 350");
end
7'h22:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 351");
ozoneae(foo[17:15], fd);
$fwrite (fd," 352");
$fwrite (fd, " 353");
$fwrite (fd, " 354");
end
7'h23:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 355");
ozoneae(foo[17:15], fd);
$fwrite (fd," 356");
$fwrite (fd, " 357");
$fwrite (fd, " 358");
end
7'h24:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 359");
ozoneae(foo[17:15], fd);
$fwrite (fd," 360");
$fwrite (fd, " 361");
$fwrite (fd, " 362");
end
7'h25:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 363");
ozoneae(foo[17:15], fd);
$fwrite (fd," 364");
$fwrite (fd, " 365");
$fwrite (fd, " 366");
end
7'h26:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 367");
ozoneae(foo[17:15], fd);
$fwrite (fd," 368");
$fwrite (fd, " 369");
$fwrite (fd, " 370");
end
7'h27:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 371");
ozoneae(foo[17:15], fd);
$fwrite (fd," 372");
$fwrite (fd, " 373");
$fwrite (fd, " 374");
end
7'h28:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 375");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 376");
ozoneape(foo[20:18], fd);
$fwrite (fd," 377");
ozoneape(foo[17:15], fd);
$fwrite (fd," 378");
$fwrite (fd, " 379");
$fwrite (fd, " 380");
end
7'h29:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 381");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 382");
ozoneape(foo[20:18], fd);
$fwrite (fd," 383");
ozoneape(foo[17:15], fd);
$fwrite (fd," 384");
$fwrite (fd, " 385");
$fwrite (fd, " 386");
end
7'h2a:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 387");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 388");
ozoneape(foo[20:18], fd);
$fwrite (fd," 389");
ozoneape(foo[17:15], fd);
$fwrite (fd," 390");
$fwrite (fd, " 391");
$fwrite (fd, " 392");
end
7'h2b:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 393");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 394");
ozoneape(foo[20:18], fd);
$fwrite (fd," 395");
ozoneape(foo[17:15], fd);
$fwrite (fd," 396");
$fwrite (fd, " 397");
$fwrite (fd, " 398");
end
7'h2c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 399");
ozoneae(foo[17:15], fd);
$fwrite (fd," 400");
$fwrite (fd, " 401");
$fwrite (fd, " 402");
end
7'h2d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 403");
ozoneae(foo[17:15], fd);
$fwrite (fd," 404");
$fwrite (fd, " 405");
$fwrite (fd, " 406");
end
7'h2e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 407");
ozoneae(foo[17:15], fd);
$fwrite (fd," 408");
$fwrite (fd, " 409");
$fwrite (fd, " 410");
end
7'h2f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 411");
ozoneae(foo[17:15], fd);
$fwrite (fd," 412");
$fwrite (fd, " 413");
$fwrite (fd, " 414");
end
7'h30:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 415");
ozoneae(foo[17:15], fd);
$fwrite (fd," 416");
$fwrite (fd, " 417");
$fwrite (fd, " 418");
end
7'h31:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 419");
ozoneae(foo[17:15], fd);
$fwrite (fd," 420");
$fwrite (fd, " 421");
$fwrite (fd, " 422");
end
7'h32:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 423");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 424");
ozoneape(foo[20:18], fd);
$fwrite (fd," 425");
ozoneape(foo[17:15], fd);
$fwrite (fd," 426");
$fwrite (fd, " 427");
$fwrite (fd, " 428");
end
7'h33:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 429");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 430");
ozoneape(foo[20:18], fd);
$fwrite (fd," 431");
ozoneape(foo[17:15], fd);
$fwrite (fd," 432");
$fwrite (fd, " 433");
$fwrite (fd, " 434");
end
7'h34:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 435");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 436");
ozoneape(foo[20:18], fd);
$fwrite (fd," 437");
ozoneape(foo[17:15], fd);
$fwrite (fd," 438");
$fwrite (fd, " 439");
$fwrite (fd, " 440");
end
7'h35:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 441");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 442");
ozoneape(foo[20:18], fd);
$fwrite (fd," 443");
ozoneape(foo[17:15], fd);
$fwrite (fd," 444");
$fwrite (fd, " 445");
$fwrite (fd, " 446");
end
7'h36:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 447");
ozoneae(foo[17:15], fd);
$fwrite (fd," 448");
$fwrite (fd, " 449");
$fwrite (fd, " 450");
end
7'h37:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 451");
ozoneae(foo[17:15], fd);
$fwrite (fd," 452");
$fwrite (fd, " 453");
$fwrite (fd, " 454");
end
7'h38:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 455");
ozoneae(foo[17:15], fd);
$fwrite (fd," 456");
$fwrite (fd, " 457");
end
7'h39:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 458");
ozoneae(foo[17:15], fd);
$fwrite (fd," 459");
$fwrite (fd, " 460");
end
7'h3a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 461");
ozoneae(foo[17:15], fd);
$fwrite (fd," 462");
$fwrite (fd, " 463");
end
7'h3b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 464");
ozoneae(foo[17:15], fd);
$fwrite (fd," 465");
$fwrite (fd, " 466");
end
7'h3c:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 467");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 468");
ozoneape(foo[20:18], fd);
$fwrite (fd," 469");
ozoneape(foo[17:15], fd);
$fwrite (fd," 470");
$fwrite (fd, " 471");
end
7'h3d:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 472");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 473");
ozoneape(foo[20:18], fd);
$fwrite (fd," 474");
ozoneape(foo[17:15], fd);
$fwrite (fd," 475");
$fwrite (fd, " 476");
end
7'h3e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 477");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 478");
ozoneape(foo[20:18], fd);
$fwrite (fd," 479");
ozoneape(foo[17:15], fd);
$fwrite (fd," 480");
$fwrite (fd, " 481");
end
7'h3f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 482");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 483");
ozoneape(foo[20:18], fd);
$fwrite (fd," 484");
ozoneape(foo[17:15], fd);
$fwrite (fd," 485");
$fwrite (fd, " 486");
end
7'h40:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 487");
ozoneae(foo[17:15], fd);
$fwrite (fd," 488");
$fwrite (fd, " 489");
$fwrite (fd, " 490");
end
7'h41:
begin
$fwrite (fd, " 491");
$fwrite (fd, " 492");
end
7'h42:
begin
$fwrite (fd, " 493");
$fwrite (fd, " 494");
end
7'h43:
begin
$fwrite (fd, " 495");
$fwrite (fd, " 496");
end
7'h44:
begin
$fwrite (fd, " 497");
$fwrite (fd, " 498");
end
7'h45:
$fwrite (fd, " 499");
7'h46:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 500");
$fwrite (fd, " 501");
$fwrite (fd, " 502");
end
7'h47:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 503");
ozoneae(foo[17:15], fd);
$fwrite (fd," 504");
ozoneape(foo[20:18], fd);
$fwrite (fd," 505");
ozoneape(foo[20:18], fd);
$fwrite (fd," 506");
$fwrite (fd, " 507");
$fwrite (fd, " 508");
end
7'h48:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 509");
ozoneape(foo[20:18], fd);
$fwrite (fd," 510");
ozoneape(foo[20:18], fd);
$fwrite (fd," 511");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 512");
ozoneape(foo[17:15], fd);
$fwrite (fd," 513");
end
7'h49:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 514");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 515");
ozoneape(foo[17:15], fd);
$fwrite (fd," 516");
end
7'h4a:
$fwrite (fd," 517");
7'h4b:
$fwrite (fd, " 518");
7'h4c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 519");
$fwrite (fd, " 520");
$fwrite (fd, " 521");
end
7'h4d:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 522");
ozoneae(foo[17:15], fd);
$fwrite (fd," 523");
ozoneape(foo[20:18], fd);
$fwrite (fd," 524");
ozoneape(foo[20:18], fd);
$fwrite (fd," 525");
$fwrite (fd, " 526");
$fwrite (fd, " 527");
end
7'h4e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 528");
ozoneae(foo[17:15], fd);
$fwrite (fd," 529");
ozoneape(foo[20:18], fd);
$fwrite (fd," 530");
ozoneape(foo[20:18], fd);
$fwrite (fd," 531");
end
7'h4f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 532");
end
7'h50:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 533");
ozoneae(foo[17:15], fd);
$fwrite (fd," 534");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 535");
ozoneae(foo[17:15], fd);
$fwrite (fd," 536");
ozoneape(foo[20:18], fd);
$fwrite (fd," 537");
ozoneae(foo[17:15], fd);
$fwrite (fd," 538");
ozoneape(foo[20:18], fd);
$fwrite (fd," 539");
ozoneae(foo[17:15], fd);
$fwrite (fd," 540");
end
7'h51:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 541");
ozoneape(foo[20:18], fd);
$fwrite (fd," 542");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 543");
ozoneape(foo[20:18], fd);
$fwrite (fd," 544");
ozoneae(foo[17:15], fd);
$fwrite (fd," 545");
end
7'h52:
$fwrite (fd, " 546");
7'h53:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 547");
end
7'h54:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 548");
ozoneae(foo[17:15], fd);
$fwrite (fd," 549");
end
7'h55:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 550");
ozoneae(foo[17:15], fd);
$fwrite (fd," 551");
end
7'h56:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 552");
ozoneae(foo[17:15], fd);
$fwrite (fd," 553");
$fwrite (fd, " 554");
end
7'h57:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 555");
ozoneae(foo[17:15], fd);
$fwrite (fd," 556");
ozoneape(foo[20:18], fd);
$fwrite (fd," 557");
ozoneape(foo[20:18], fd);
$fwrite (fd," 558");
end
7'h58:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 559");
end
7'h59:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 560");
ozoneae(foo[17:15], fd);
$fwrite (fd," 561");
ozoneape(foo[20:18], fd);
$fwrite (fd," 562");
ozoneape(foo[20:18], fd);
$fwrite (fd," 563");
end
7'h5a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 564");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 565");
end
7'h5b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 566");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 567");
end
7'h5c:
begin
$fwrite (fd," 568");
ozoneape(foo[17:15], fd);
$fwrite (fd," 569");
$fwrite (fd," 570");
ozoneape(foo[17:15], fd);
$fwrite (fd," 571");
ozoneae(foo[20:18], fd);
$fwrite (fd," 572");
ozoneaee(foo[17:15], fd);
$fwrite (fd, " 573");
end
7'h5d:
begin
$fwrite (fd," 574");
ozoneape(foo[17:15], fd);
$fwrite (fd," 575");
$fwrite (fd," 576");
ozoneape(foo[17:15], fd);
$fwrite (fd," 577");
ozoneae(foo[20:18], fd);
$fwrite (fd," 578");
ozoneaee(foo[17:15], fd);
$fwrite (fd, " 579");
end
7'h5e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 580");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 581");
end
7'h5f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 582");
ozoneae(foo[17:15], fd);
$fwrite (fd," 583");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 584");
ozoneae(foo[17:15], fd);
$fwrite (fd," 585");
ozoneape(foo[20:18], fd);
$fwrite (fd," 586");
ozoneae(foo[17:15], fd);
$fwrite (fd," 587");
ozoneape(foo[20:18], fd);
$fwrite (fd," 588");
ozoneae(foo[17:15], fd);
$fwrite (fd," 589");
end
7'h60:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 590");
ozoneae(foo[17:15], fd);
$fwrite (fd," 591");
end
7'h61:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 592");
ozoneae(foo[17:15], fd);
$fwrite (fd," 593");
end
7'h62:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 594");
ozoneae(foo[17:15], fd);
$fwrite (fd," 595");
end
7'h63:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 596");
ozoneae(foo[17:15], fd);
$fwrite (fd," 597");
end
7'h64:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 598");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 599");
ozoneape(foo[20:18], fd);
$fwrite (fd," 600");
ozoneape(foo[17:15], fd);
$fwrite (fd," 601");
end
7'h65:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 602");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 603");
ozoneape(foo[20:18], fd);
$fwrite (fd," 604");
ozoneape(foo[17:15], fd);
$fwrite (fd," 605");
end
7'h66:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 606");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 607");
ozoneape(foo[20:18], fd);
$fwrite (fd," 608");
ozoneape(foo[17:15], fd);
$fwrite (fd," 609");
end
7'h67:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 610");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 611");
ozoneape(foo[20:18], fd);
$fwrite (fd," 612");
ozoneape(foo[17:15], fd);
$fwrite (fd," 613");
end
7'h68:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 614");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 615");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 616");
ozoneape(foo[20:18], fd);
$fwrite (fd," 617");
ozoneape(foo[20:18], fd);
$fwrite (fd," 618");
ozoneape(foo[17:15], fd);
end
7'h69:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 619");
ozoneae(foo[17:15], fd);
$fwrite (fd," 620");
ozoneae(foo[20:18], fd);
$fwrite (fd," 621");
end
7'h6a:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 622");
ozoneae(foo[17:15], fd);
$fwrite (fd," 623");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 624");
ozoneape(foo[20:18], fd);
$fwrite (fd," 625");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 626");
ozoneae(foo[17:15], fd);
end
7'h6b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 627");
ozoneae(foo[17:15], fd);
$fwrite (fd," 628");
ozoneae(foo[20:18], fd);
$fwrite (fd," 629");
end
7'h6c:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 630");
ozoneae(foo[17:15], fd);
$fwrite (fd," 631");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 632");
ozoneape(foo[20:18], fd);
$fwrite (fd," 633");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 634");
ozoneae(foo[17:15], fd);
end
7'h6d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 635");
ozoneae(foo[17:15], fd);
$fwrite (fd," 636");
ozoneae(foo[20:18], fd);
$fwrite (fd," 637");
end
7'h6e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 638");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 639");
ozoneape(foo[20:18], fd);
$fwrite (fd," 640");
ozoneape(foo[17:15], fd);
$fwrite (fd," 641");
end
7'h6f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 642");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 643");
ozoneape(foo[20:18], fd);
$fwrite (fd," 644");
ozoneape(foo[17:15], fd);
$fwrite (fd," 645");
end
7'h70:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 646");
ozoneae(foo[20:18], fd);
$fwrite (fd," 647");
ozoneae(foo[17:15], fd);
$fwrite (fd," 648");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 649");
end
7'h71:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 650");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 651");
end
7'h72:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 652");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 653");
end
7'h73:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 654");
ozoneae(foo[20:18], fd);
$fwrite (fd," 655");
ozoneae(foo[17:15], fd);
end
7'h74:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 656");
ozoneae(foo[20:18], fd);
$fwrite (fd," 657");
ozoneae(foo[17:15], fd);
end
7'h75:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 658");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 659");
ozoneape(foo[20:18], fd);
$fwrite (fd," 660");
ozoneape(foo[17:15], fd);
$fwrite (fd," 661");
$fwrite (fd, " 662");
$fwrite (fd, " 663");
end
7'h76:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 664");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 665");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 666");
ozoneape(foo[20:18], fd);
$fwrite (fd," 667");
ozoneape(foo[17:15], fd);
$fwrite (fd," 668");
ozoneape(foo[20:18], fd);
$fwrite (fd," 669");
end
7'h77:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 670");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 671");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 672");
ozoneape(foo[20:18], fd);
$fwrite (fd," 673");
ozoneape(foo[17:15], fd);
$fwrite (fd," 674");
ozoneape(foo[17:15], fd);
$fwrite (fd," 675");
end
7'h78,
7'h79,
7'h7a,
7'h7b,
7'h7c,
7'h7d,
7'h7e,
7'h7f:
$fwrite (fd," 676");
endcase
end
endtask
task ozonef2;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
case (foo[26:25])
2'b00 : $fwrite (fd," 677");
2'b01 : $fwrite (fd," 678");
2'b10 : $fwrite (fd," 679");
2'b11 : $fwrite (fd," 680");
endcase
4'h1 :
case (foo[26:25])
2'b00 : $fwrite (fd," 681");
2'b01 : $fwrite (fd," 682");
2'b10 : $fwrite (fd," 683");
2'b11 : $fwrite (fd," 684");
endcase
4'h2 :
case (foo[26:25])
2'b00 : $fwrite (fd," 685");
2'b01 : $fwrite (fd," 686");
2'b10 : $fwrite (fd," 687");
2'b11 : $fwrite (fd," 688");
endcase
4'h3 :
case (foo[26:25])
2'b00 : $fwrite (fd," 689");
2'b01 : $fwrite (fd," 690");
2'b10 : $fwrite (fd," 691");
2'b11 : $fwrite (fd," 692");
endcase
4'h4 :
case (foo[26:25])
2'b00 : $fwrite (fd," 693");
2'b01 : $fwrite (fd," 694");
2'b10 : $fwrite (fd," 695");
2'b11 : $fwrite (fd," 696");
endcase
4'h5 :
case (foo[26:25])
2'b00 : $fwrite (fd," 697");
2'b01 : $fwrite (fd," 698");
2'b10 : $fwrite (fd," 699");
2'b11 : $fwrite (fd," 700");
endcase
4'h6 :
case (foo[26:25])
2'b00 : $fwrite (fd," 701");
2'b01 : $fwrite (fd," 702");
2'b10 : $fwrite (fd," 703");
2'b11 : $fwrite (fd," 704");
endcase
4'h7 :
case (foo[26:25])
2'b00 : $fwrite (fd," 705");
2'b01 : $fwrite (fd," 706");
2'b10 : $fwrite (fd," 707");
2'b11 : $fwrite (fd," 708");
endcase
4'h8 :
if (foo[26])
$fwrite (fd," 709");
else
$fwrite (fd," 710");
4'h9 :
case (foo[26:25])
2'b00 : $fwrite (fd," 711");
2'b01 : $fwrite (fd," 712");
2'b10 : $fwrite (fd," 713");
2'b11 : $fwrite (fd," 714");
endcase
4'ha :
case (foo[26:25])
2'b00 : $fwrite (fd," 715");
2'b01 : $fwrite (fd," 716");
2'b10 : $fwrite (fd," 717");
2'b11 : $fwrite (fd," 718");
endcase
4'hb :
case (foo[26:25])
2'b00 : $fwrite (fd," 719");
2'b01 : $fwrite (fd," 720");
2'b10 : $fwrite (fd," 721");
2'b11 : $fwrite (fd," 722");
endcase
4'hc :
if (foo[26])
$fwrite (fd," 723");
else
$fwrite (fd," 724");
4'hd :
case (foo[26:25])
2'b00 : $fwrite (fd," 725");
2'b01 : $fwrite (fd," 726");
2'b10 : $fwrite (fd," 727");
2'b11 : $fwrite (fd," 728");
endcase
4'he :
case (foo[26:25])
2'b00 : $fwrite (fd," 729");
2'b01 : $fwrite (fd," 730");
2'b10 : $fwrite (fd," 731");
2'b11 : $fwrite (fd," 732");
endcase
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd," 733");
2'b01 : $fwrite (fd," 734");
2'b10 : $fwrite (fd," 735");
2'b11 : $fwrite (fd," 736");
endcase
endcase
end
endtask
task ozonef2e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
casez (foo[25:21])
5'h00 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 737");
ozoneae(foo[17:15], fd);
$fwrite (fd," 738");
end
5'h01 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 739");
ozoneae(foo[17:15], fd);
$fwrite (fd," 740");
end
5'h02 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 741");
ozoneae(foo[17:15], fd);
$fwrite (fd," 742");
end
5'h03 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 743");
ozoneae(foo[17:15], fd);
$fwrite (fd," 744");
end
5'h04 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 745");
ozoneae(foo[17:15], fd);
$fwrite (fd," 746");
end
5'h05 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 747");
ozoneae(foo[17:15], fd);
$fwrite (fd," 748");
end
5'h06 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 749");
ozoneae(foo[17:15], fd);
$fwrite (fd," 750");
end
5'h07 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 751");
ozoneae(foo[17:15], fd);
$fwrite (fd," 752");
end
5'h08 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 753");
if (foo[ 6])
$fwrite (fd," 754");
else
$fwrite (fd," 755");
end
5'h09 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 756");
ozoneae(foo[17:15], fd);
$fwrite (fd," 757");
end
5'h0a :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 758");
ozoneae(foo[17:15], fd);
end
5'h0b :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 759");
ozoneae(foo[17:15], fd);
$fwrite (fd," 760");
end
5'h0c :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 761");
end
5'h0d :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 762");
ozoneae(foo[17:15], fd);
$fwrite (fd," 763");
end
5'h0e :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 764");
ozoneae(foo[17:15], fd);
end
5'h0f :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 765");
ozoneae(foo[17:15], fd);
end
5'h10 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 766");
ozoneae(foo[17:15], fd);
$fwrite (fd," 767");
end
5'h11 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 768");
ozoneae(foo[17:15], fd);
$fwrite (fd," 769");
end
5'h18 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 770");
if (foo[ 6])
$fwrite (fd," 771");
else
$fwrite (fd," 772");
end
5'h1a :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 773");
ozoneae(foo[17:15], fd);
$fwrite (fd," 774");
end
5'h1b :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 775");
ozoneae(foo[17:15], fd);
$fwrite (fd," 776");
if (foo[ 6])
$fwrite (fd," 777");
else
$fwrite (fd," 778");
$fwrite (fd," 779");
end
5'h1c :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 780");
end
5'h1d :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 781");
if (foo[ 6])
$fwrite (fd," 782");
else
$fwrite (fd," 783");
$fwrite (fd," 784");
end
5'h1e :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 785");
if (foo[ 6])
$fwrite (fd," 786");
else
$fwrite (fd," 787");
$fwrite (fd," 788");
end
5'h1f :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 789");
ozoneae(foo[17:15], fd);
$fwrite (fd," 790");
if (foo[ 6])
$fwrite (fd," 791");
else
$fwrite (fd," 792");
$fwrite (fd," 793");
end
default :
$fwrite (fd," 794");
endcase
end
endtask
task ozonef3e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[25:21])
5'h00,
5'h01,
5'h02:
begin
ozoneae(foo[20:18], fd);
case (foo[22:21])
2'h0: $fwrite (fd," 795");
2'h1: $fwrite (fd," 796");
2'h2: $fwrite (fd," 797");
endcase
ozoneae(foo[17:15], fd);
$fwrite (fd," 798");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
$fwrite (fd," 799");
end
5'h08,
5'h09,
5'h0d,
5'h0e,
5'h0f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 800");
ozoneae(foo[17:15], fd);
case (foo[23:21])
3'h0: $fwrite (fd," 801");
3'h1: $fwrite (fd," 802");
3'h5: $fwrite (fd," 803");
3'h6: $fwrite (fd," 804");
3'h7: $fwrite (fd," 805");
endcase
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
end
5'h0a,
5'h0b:
begin
ozoneae(foo[17:15], fd);
if (foo[21])
$fwrite (fd," 806");
else
$fwrite (fd," 807");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
end
5'h0c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 808");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
$fwrite (fd," 809");
ozoneae(foo[17:15], fd);
end
5'h10,
5'h11,
5'h12,
5'h13:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 810");
ozoneae(foo[17:15], fd);
case (foo[22:21])
2'h0,
2'h2:
$fwrite (fd," 811");
2'h1,
2'h3:
$fwrite (fd," 812");
endcase
ozoneae(foo[ 8: 6], fd);
$fwrite (fd," 813");
ozoneae((foo[20:18]+1), fd);
$fwrite (fd," 814");
ozoneae((foo[17:15]+1), fd);
case (foo[22:21])
2'h0,
2'h3:
$fwrite (fd," 815");
2'h1,
2'h2:
$fwrite (fd," 816");
endcase
ozoneae((foo[ 8: 6]+1), fd);
end
5'h18:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 817");
ozoneae(foo[17:15], fd);
$fwrite (fd," 818");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd," 819");
ozoneae(foo[20:18], fd);
$fwrite (fd," 820");
ozoneae(foo[17:15], fd);
$fwrite (fd," 821");
ozoneae(foo[ 8: 6], fd);
end
default :
$fwrite (fd," 822");
endcase
end
endtask
task ozonef3e_te;
input [ 2:0] te;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (te)
3'b100 : $fwrite (fd, " 823");
3'b101 : $fwrite (fd, " 824");
3'b110 : $fwrite (fd, " 825");
default: $fwrite (fd, " 826");
endcase
end
endtask
task ozonearm;
input [ 2:0] ate;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ate)
3'b000 : $fwrite (fd, " 827");
3'b001 : $fwrite (fd, " 828");
3'b010 : $fwrite (fd, " 829");
3'b011 : $fwrite (fd, " 830");
3'b100 : $fwrite (fd, " 831");
3'b101 : $fwrite (fd, " 832");
3'b110 : $fwrite (fd, " 833");
3'b111 : $fwrite (fd, " 834");
endcase
end
endtask
task ozonebmuop;
input [ 4:0] f4;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (f4[ 4:0])
5'h00,
5'h04 :
$fwrite (fd, " 835");
5'h01,
5'h05 :
$fwrite (fd, " 836");
5'h02,
5'h06 :
$fwrite (fd, " 837");
5'h03,
5'h07 :
$fwrite (fd, " 838");
5'h08,
5'h18 :
$fwrite (fd, " 839");
5'h09,
5'h19 :
$fwrite (fd, " 840");
5'h0a,
5'h1a :
$fwrite (fd, " 841");
5'h0b :
$fwrite (fd, " 842");
5'h1b :
$fwrite (fd, " 843");
5'h0c,
5'h1c :
$fwrite (fd, " 844");
5'h0d,
5'h1d :
$fwrite (fd, " 845");
5'h1e :
$fwrite (fd, " 846");
endcase
end
endtask
task ozonef3;
input [ 31:0] foo;
input [`FD_BITS] fd;
reg nacho;
// verilator no_inline_task
begin : f3_body
nacho = 1'b0;
case (foo[24:21])
4'h0:
case (foo[26:25])
2'b00 : $fwrite (fd, " 847");
2'b01 : $fwrite (fd, " 848");
2'b10 : $fwrite (fd, " 849");
2'b11 : $fwrite (fd, " 850");
endcase
4'h1:
case (foo[26:25])
2'b00 : $fwrite (fd, " 851");
2'b01 : $fwrite (fd, " 852");
2'b10 : $fwrite (fd, " 853");
2'b11 : $fwrite (fd, " 854");
endcase
4'h2:
case (foo[26:25])
2'b00 : $fwrite (fd, " 855");
2'b01 : $fwrite (fd, " 856");
2'b10 : $fwrite (fd, " 857");
2'b11 : $fwrite (fd, " 858");
endcase
4'h8,
4'h9,
4'hd,
4'he,
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd, " 859");
2'b01 : $fwrite (fd, " 860");
2'b10 : $fwrite (fd, " 861");
2'b11 : $fwrite (fd, " 862");
endcase
4'ha,
4'hb :
if (foo[25])
$fwrite (fd, " 863");
else
$fwrite (fd, " 864");
4'hc :
if (foo[26])
$fwrite (fd, " 865");
else
$fwrite (fd, " 866");
default :
begin
$fwrite (fd, " 867");
nacho = 1'b1;
end
endcase
if (~nacho)
begin
case (foo[24:21])
4'h8 :
$fwrite (fd, " 868");
4'h9 :
$fwrite (fd, " 869");
4'ha,
4'he :
$fwrite (fd, " 870");
4'hb,
4'hf :
$fwrite (fd, " 871");
4'hd :
$fwrite (fd, " 872");
endcase
if (foo[20])
case (foo[18:16])
3'b000 : $fwrite (fd, " 873");
3'b100 : $fwrite (fd, " 874");
default: $fwrite (fd, " 875");
endcase
else
ozoneae(foo[18:16], fd);
if (foo[24:21] === 4'hc)
if (foo[25])
$fwrite (fd, " 876");
else
$fwrite (fd, " 877");
case (foo[24:21])
4'h0,
4'h1,
4'h2:
$fwrite (fd, " 878");
endcase
end
end
endtask
task ozonerx;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[19:18])
2'h0 : $fwrite (fd, " 879");
2'h1 : $fwrite (fd, " 880");
2'h2 : $fwrite (fd, " 881");
2'h3 : $fwrite (fd, " 882");
endcase
case (foo[17:16])
2'h1 : $fwrite (fd, " 883");
2'h2 : $fwrite (fd, " 884");
2'h3 : $fwrite (fd, " 885");
endcase
end
endtask
task ozonerme;
input [ 2:0] rme;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rme)
3'h0 : $fwrite (fd, " 886");
3'h1 : $fwrite (fd, " 887");
3'h2 : $fwrite (fd, " 888");
3'h3 : $fwrite (fd, " 889");
3'h4 : $fwrite (fd, " 890");
3'h5 : $fwrite (fd, " 891");
3'h6 : $fwrite (fd, " 892");
3'h7 : $fwrite (fd, " 893");
endcase
end
endtask
task ozoneye;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
$fwrite (fd, " 894");
ozonerme(ye[5:3], fd);
case ({ye[ 2:0], l})
4'h2,
4'ha: $fwrite (fd, " 895");
4'h4,
4'hb: $fwrite (fd, " 896");
4'h6,
4'he: $fwrite (fd, " 897");
4'h8,
4'hc: $fwrite (fd, " 898");
endcase
end
endtask
task ozonef1e_ye;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
$fwrite (fd, " 899");
ozonerme(ye[5:3], fd);
ozonef1e_inc_dec(ye[5:0], l , fd);
end
endtask
task ozonef1e_h;
input [ 2:0] e;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
if (e[ 2:0] <= 3'h4)
$fwrite (fd, " 900");
end
endtask
task ozonef1e_inc_dec;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case ({ye[ 2:0], l})
4'h2,
4'h3,
4'ha: $fwrite (fd, " 901");
4'h4,
4'h5,
4'hb: $fwrite (fd, " 902");
4'h6,
4'h7,
4'he: $fwrite (fd, " 903");
4'h8,
4'h9,
4'hc: $fwrite (fd, " 904");
4'hf: $fwrite (fd, " 905");
endcase
end
endtask
task ozonef1e_hl;
input [ 2:0] e;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case ({e[ 2:0], l})
4'h0,
4'h2,
4'h4,
4'h6,
4'h8: $fwrite (fd, " 906");
4'h1,
4'h3,
4'h5,
4'h7,
4'h9: $fwrite (fd, " 907");
endcase
end
endtask
task ozonexe;
input [ 3:0] xe;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (xe[3])
1'b0 : $fwrite (fd, " 908");
1'b1 : $fwrite (fd, " 909");
endcase
case (xe[ 2:0])
3'h1,
3'h5: $fwrite (fd, " 910");
3'h2,
3'h6: $fwrite (fd, " 911");
3'h3,
3'h7: $fwrite (fd, " 912");
3'h4: $fwrite (fd, " 913");
endcase
end
endtask
task ozonerp;
input [ 2:0] rp;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rp)
3'h0 : $fwrite (fd, " 914");
3'h1 : $fwrite (fd, " 915");
3'h2 : $fwrite (fd, " 916");
3'h3 : $fwrite (fd, " 917");
3'h4 : $fwrite (fd, " 918");
3'h5 : $fwrite (fd, " 919");
3'h6 : $fwrite (fd, " 920");
3'h7 : $fwrite (fd, " 921");
endcase
end
endtask
task ozonery;
input [ 3:0] ry;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ry)
4'h0 : $fwrite (fd, " 922");
4'h1 : $fwrite (fd, " 923");
4'h2 : $fwrite (fd, " 924");
4'h3 : $fwrite (fd, " 925");
4'h4 : $fwrite (fd, " 926");
4'h5 : $fwrite (fd, " 927");
4'h6 : $fwrite (fd, " 928");
4'h7 : $fwrite (fd, " 929");
4'h8 : $fwrite (fd, " 930");
4'h9 : $fwrite (fd, " 931");
4'ha : $fwrite (fd, " 932");
4'hb : $fwrite (fd, " 933");
4'hc : $fwrite (fd, " 934");
4'hd : $fwrite (fd, " 935");
4'he : $fwrite (fd, " 936");
4'hf : $fwrite (fd, " 937");
endcase
end
endtask
task ozonearx;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[1:0])
2'h0 : $fwrite (fd, " 938");
2'h1 : $fwrite (fd, " 939");
2'h2 : $fwrite (fd, " 940");
2'h3 : $fwrite (fd, " 941");
endcase
end
endtask
task ozonef3f4imop;
input [ 4:0] f3f4iml;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
casez (f3f4iml)
5'b000??: $fwrite (fd, " 942");
5'b001??: $fwrite (fd, " 943");
5'b?10??: $fwrite (fd, " 944");
5'b0110?: $fwrite (fd, " 945");
5'b01110: $fwrite (fd, " 946");
5'b01111: $fwrite (fd, " 947");
5'b10???: $fwrite (fd, " 948");
5'b11100: $fwrite (fd, " 949");
5'b11101: $fwrite (fd, " 950");
5'b11110: $fwrite (fd, " 951");
5'b11111: $fwrite (fd, " 952");
endcase
end
endtask
task ozonecon;
input [ 4:0] con;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (con)
5'h00 : $fwrite (fd, " 953");
5'h01 : $fwrite (fd, " 954");
5'h02 : $fwrite (fd, " 955");
5'h03 : $fwrite (fd, " 956");
5'h04 : $fwrite (fd, " 957");
5'h05 : $fwrite (fd, " 958");
5'h06 : $fwrite (fd, " 959");
5'h07 : $fwrite (fd, " 960");
5'h08 : $fwrite (fd, " 961");
5'h09 : $fwrite (fd, " 962");
5'h0a : $fwrite (fd, " 963");
5'h0b : $fwrite (fd, " 964");
5'h0c : $fwrite (fd, " 965");
5'h0d : $fwrite (fd, " 966");
5'h0e : $fwrite (fd, " 967");
5'h0f : $fwrite (fd, " 968");
5'h10 : $fwrite (fd, " 969");
5'h11 : $fwrite (fd, " 970");
5'h12 : $fwrite (fd, " 971");
5'h13 : $fwrite (fd, " 972");
5'h14 : $fwrite (fd, " 973");
5'h15 : $fwrite (fd, " 974");
5'h16 : $fwrite (fd, " 975");
5'h17 : $fwrite (fd, " 976");
5'h18 : $fwrite (fd, " 977");
5'h19 : $fwrite (fd, " 978");
5'h1a : $fwrite (fd, " 979");
5'h1b : $fwrite (fd, " 980");
5'h1c : $fwrite (fd, " 981");
5'h1d : $fwrite (fd, " 982");
5'h1e : $fwrite (fd, " 983");
5'h1f : $fwrite (fd, " 984");
endcase
end
endtask
task ozonedr;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[ 9: 6])
4'h0 : $fwrite (fd, " 985");
4'h1 : $fwrite (fd, " 986");
4'h2 : $fwrite (fd, " 987");
4'h3 : $fwrite (fd, " 988");
4'h4 : $fwrite (fd, " 989");
4'h5 : $fwrite (fd, " 990");
4'h6 : $fwrite (fd, " 991");
4'h7 : $fwrite (fd, " 992");
4'h8 : $fwrite (fd, " 993");
4'h9 : $fwrite (fd, " 994");
4'ha : $fwrite (fd, " 995");
4'hb : $fwrite (fd, " 996");
4'hc : $fwrite (fd, " 997");
4'hd : $fwrite (fd, " 998");
4'he : $fwrite (fd, " 999");
4'hf : $fwrite (fd, " 1000");
endcase
end
endtask
task ozoneshift;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[ 4: 3])
2'h0 : $fwrite (fd, " 1001");
2'h1 : $fwrite (fd, " 1002");
2'h2 : $fwrite (fd, " 1003");
2'h3 : $fwrite (fd, " 1004");
endcase
end
endtask
task ozoneacc;
input foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 : $fwrite (fd, " 1005");
2'h1 : $fwrite (fd, " 1006");
endcase
end
endtask
task ozonehl;
input foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 : $fwrite (fd, " 1007");
2'h1 : $fwrite (fd, " 1008");
endcase
end
endtask
task dude;
input [`FD_BITS] fd;
// verilator no_inline_task
$fwrite(fd," dude");
endtask
task big_case;
input [ `FD_BITS] fd;
input [ 31:0] foo;
// verilator no_inline_task
begin
$fwrite(fd," 1009");
if (&foo === 1'bx)
$fwrite(fd, " 1010");
else
casez ( {foo[31:26], foo[19:15], foo[5:0]} )
17'b00_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1011");
ozoneacc(~foo[26], fd);
ozonehl(foo[20], fd);
$fwrite (fd, " 1012");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1013");
end
17'b01_001?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1014");
ozonerx(foo, fd);
$fwrite (fd, " 1015");
$fwrite (fd, " 1016:%x", foo[20]);
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1017");
end
17'b10_100?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1018");
ozonerx(foo, fd);
$fwrite (fd, " 1019");
$fwrite (fd, " 1020");
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1021");
end
17'b10_101?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1022");
if (foo[20])
begin
$fwrite (fd, " 1023");
ozoneacc(foo[18], fd);
$fwrite (fd, " 1024");
$fwrite (fd, " 1025");
if (foo[19])
$fwrite (fd, " 1026");
else
$fwrite (fd, " 1027");
end
else
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1028");
end
17'b10_110?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1029");
$fwrite (fd, " 1030");
ozonehl(foo[20], fd);
$fwrite (fd, " 1031");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1032");
end
17'b10_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1033");
$fwrite (fd, " 1034");
ozonehl(foo[20], fd);
$fwrite (fd, " 1035");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1036");
end
17'b11_001?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1037");
ozonerx(foo, fd);
$fwrite (fd, " 1038");
$fwrite (fd, " 1039");
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1040");
end
17'b11_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1041");
$fwrite (fd, " 1042");
ozonerx(foo, fd);
$fwrite (fd, " 1043");
if (foo[20])
$fwrite (fd, " 1044");
else
$fwrite (fd, " 1045");
dude(fd);
$fwrite (fd, " 1046");
end
17'b00_10??_?_????_?1_1111 :
casez (foo[11: 5])
7'b??_0_010_0:
begin
$fwrite (fd, " 1047");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1048");
ozonef1e(foo, fd);
dude(fd);
$fwrite (fd, " 1049");
end
7'b00_?_110_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1050");
case ({foo[ 9],foo[ 5]})
2'b00:
begin
$fwrite (fd, " 1051");
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
end
2'b01:
begin
$fwrite (fd, " 1052");
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
end
2'b10:
begin
$fwrite (fd, " 1053");
ozoneae(foo[14:12], fd);
end
2'b11: $fwrite (fd, " 1054");
endcase
dude(fd);
$fwrite (fd, " 1055");
end
7'b01_?_110_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1056");
case ({foo[ 9],foo[ 5]})
2'b00:
begin
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
$fwrite (fd, " 1057");
end
2'b01:
begin
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
$fwrite (fd, " 1058");
end
2'b10:
begin
ozoneae(foo[14:12], fd);
$fwrite (fd, " 1059");
end
2'b11: $fwrite (fd, " 1060");
endcase
dude(fd);
$fwrite (fd, " 1061");
end
7'b10_0_110_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1062");
$fwrite (fd, " 1063");
if (foo[12])
$fwrite (fd, " 1064");
else
ozonerab({4'b1001, foo[14:12]}, fd);
dude(fd);
$fwrite (fd, " 1065");
end
7'b10_0_110_1:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1066");
if (foo[12])
$fwrite (fd, " 1067");
else
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1068");
dude(fd);
$fwrite (fd, " 1069");
end
7'b??_?_000_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1070");
$fwrite (fd, " 1071");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1072");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1073");
end
7'b??_?_100_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1074");
$fwrite (fd, " 1075");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1076");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1077");
end
7'b??_?_001_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1078");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1079");
$fwrite (fd, " 1080");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1081");
end
7'b??_?_011_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1082");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1083");
$fwrite (fd, " 1084");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1085");
end
7'b??_?_101_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1086");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1087");
end
endcase
17'b00_10??_?_????_?0_0110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1088");
ozoneae(foo[ 8: 6], fd);
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1089");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1090");
end
17'b00_10??_?_????_00_0111 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1091");
if (foo[ 6])
$fwrite (fd, " 1092");
else
ozonerab({4'b1001, foo[ 8: 6]}, fd);
$fwrite (fd, " 1093");
$fwrite (fd, " 1094");
ozonerme(foo[14:12], fd);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0, fd);
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1095");
endcase
dude(fd);
$fwrite (fd, " 1096");
end
17'b00_10??_?_????_?0_0100 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1097");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1098");
ozoneae(foo[ 8: 6], fd);
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1099");
end
17'b00_10??_?_????_10_0111 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1100");
$fwrite (fd, " 1101");
ozonerme(foo[14:12], fd);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0, fd);
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1102");
endcase
$fwrite (fd, " 1103");
if (foo[ 6])
$fwrite (fd, " 1104");
else
ozonerab({4'b1001, foo[ 8: 6]}, fd);
dude(fd);
$fwrite (fd, " 1105");
end
17'b00_10??_?_????_?0_1110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1106");
case (foo[11:9])
3'h2:
begin
$fwrite (fd, " 1107");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1108");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1109");
end
3'h6:
begin
$fwrite (fd, " 1110");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1111");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1112");
end
3'h0:
begin
$fwrite (fd, " 1113");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1114");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1115");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1116");
else
ozonexe(foo[ 8: 5], fd);
end
3'h1:
begin
$fwrite (fd, " 1117");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1118");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1119");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1120");
else
ozonexe(foo[ 8: 5], fd);
end
3'h4:
begin
$fwrite (fd, " 1121");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1122");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1123");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1124");
else
ozonexe(foo[ 8: 5], fd);
end
3'h5:
begin
$fwrite (fd, " 1125");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1126");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1127");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1128");
else
ozonexe(foo[ 8: 5], fd);
end
endcase
dude(fd);
$fwrite (fd, " 1129");
end
17'b00_10??_?_????_?0_1111 :
casez (foo[14: 9])
6'b001_10_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1130");
$fwrite (fd, " 1131");
ozonef1e_hl(foo[ 7: 5],foo[ 9], fd);
$fwrite (fd, " 1132");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1133");
end
6'b???_11_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1134");
ozoneae(foo[14:12], fd);
ozonef1e_hl(foo[ 7: 5],foo[ 9], fd);
$fwrite (fd, " 1135");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1136");
end
6'b000_10_1,
6'b010_10_1,
6'b100_10_1,
6'b110_10_1:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1137");
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1138");
if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3))
$fwrite (fd, " 1139");
else
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1140");
end
6'b000_10_0,
6'b010_10_0,
6'b100_10_0,
6'b110_10_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1141");
$fwrite (fd, " 1142");
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1143");
$fwrite (fd, " 1144");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1145");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1146");
end
6'b???_00_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1147");
if (foo[ 9])
begin
$fwrite (fd, " 1148");
ozoneae(foo[14:12], fd);
end
else
begin
$fwrite (fd, " 1149");
ozoneae(foo[14:12], fd);
$fwrite (fd, " 1150");
end
$fwrite (fd, " 1151");
$fwrite (fd, " 1152");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1153");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1154");
end
6'b???_01_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1155");
ozoneae(foo[14:12], fd);
if (foo[ 9])
$fwrite (fd, " 1156");
else
$fwrite (fd, " 1157");
$fwrite (fd, " 1158");
$fwrite (fd, " 1159");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1160");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1161");
end
6'b011_10_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1162");
case (foo[ 8: 5])
4'h0: $fwrite (fd, " 1163");
4'h1: $fwrite (fd, " 1164");
4'h2: $fwrite (fd, " 1165");
4'h3: $fwrite (fd, " 1166");
4'h4: $fwrite (fd, " 1167");
4'h5: $fwrite (fd, " 1168");
4'h8: $fwrite (fd, " 1169");
4'h9: $fwrite (fd, " 1170");
4'ha: $fwrite (fd, " 1171");
4'hb: $fwrite (fd, " 1172");
4'hc: $fwrite (fd, " 1173");
4'hd: $fwrite (fd, " 1174");
default: $fwrite (fd, " 1175");
endcase
dude(fd);
$fwrite (fd, " 1176");
end
default: $fwrite (fd, " 1177");
endcase
17'b00_10??_?_????_?0_110? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1178");
$fwrite (fd, " 1179");
ozonef1e_hl(foo[11:9], foo[0], fd);
$fwrite (fd, " 1180");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1181");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1182");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1183");
end
17'b00_10??_?_????_?1_110? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1184");
$fwrite (fd, " 1185");
ozonef1e_hl(foo[11:9],foo[0], fd);
$fwrite (fd, " 1186");
ozonef1e_ye(foo[14:9],foo[ 0], fd);
$fwrite (fd, " 1187");
$fwrite (fd, " 1188");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1189");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1190");
end
17'b00_10??_?_????_?0_101? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1191");
ozonef1e_ye(foo[14:9],foo[ 0], fd);
$fwrite (fd, " 1192");
$fwrite (fd, " 1193");
ozonef1e_hl(foo[11:9],foo[0], fd);
$fwrite (fd, " 1194");
$fwrite (fd, " 1195");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1196");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1197");
end
17'b00_10??_?_????_?0_1001 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1198");
$fwrite (fd, " 1199");
ozonef1e_h(foo[11:9], fd);
$fwrite (fd, " 1200");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1201");
case (foo[ 7: 5])
3'h1,
3'h2,
3'h3:
$fwrite (fd, " 1202");
default:
begin
$fwrite (fd, " 1203");
$fwrite (fd, " 1204");
ozonexe(foo[ 8: 5], fd);
end
endcase
dude(fd);
$fwrite (fd, " 1205");
end
17'b00_10??_?_????_?0_0101 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1206");
case (foo[11: 9])
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1207");
default:
begin
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1208");
$fwrite (fd, " 1209");
end
endcase
$fwrite (fd, " 1210");
$fwrite (fd, " 1211");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1212");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1213");
end
17'b00_10??_?_????_?1_1110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1214");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1215");
$fwrite (fd, " 1216");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1217");
$fwrite (fd, " 1218");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1219");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1220");
end
17'b00_10??_?_????_?0_1000 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1221");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1222");
$fwrite (fd, " 1223");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1224");
$fwrite (fd, " 1225");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1226");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1227");
end
17'b10_01??_?_????_??_???? :
begin
if (foo[27])
$fwrite (fd," 1228");
else
$fwrite (fd," 1229");
ozonecon(foo[20:16], fd);
$fwrite (fd, " 1230");
ozonef2(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1231");
end
17'b00_1000_?_????_01_0011 :
if (~|foo[ 9: 8])
begin
if (foo[ 7])
$fwrite (fd," 1232");
else
$fwrite (fd," 1233");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1234");
ozonef2e(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1235");
end
else
begin
$fwrite (fd, " 1236");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1237");
ozonef3e(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1238");
end
17'b11_110?_1_????_??_???? :
begin
ozonef3(foo[31:0], fd);
dude(fd);
$fwrite(fd, " 1239");
end
17'b11_110?_0_????_??_???? :
begin : f4_body
casez (foo[24:20])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite (fd, " 1240");
end
5'b0_00??:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1241");
ozoneacc(foo[25], fd);
ozonebmuop(foo[24:20], fd);
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1242");
dude(fd);
$fwrite(fd, " 1243");
end
5'b0_01??:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1244");
ozoneacc(foo[25], fd);
ozonebmuop(foo[24:20], fd);
ozonearm(foo[18:16], fd);
dude(fd);
$fwrite(fd, " 1245");
end
5'b0_1011:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1246");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1247");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1248");
dude(fd);
$fwrite(fd, " 1249");
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1250");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1251");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1252");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1253");
dude(fd);
$fwrite(fd, " 1254");
end
5'b0_1111 :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1255");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1256");
ozoneae(foo[18:16], fd);
dude(fd);
$fwrite(fd, " 1257");
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1258");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1259");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1260");
ozonearm(foo[18:16], fd);
$fwrite (fd, " 1261");
dude(fd);
$fwrite(fd, " 1262");
end
endcase
end
17'b11_100?_?_????_??_???? :
casez (foo[23:19])
5'b111??,
5'b0111?:
begin
ozoneae(foo[26:24], fd);
$fwrite (fd, " 1263");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1264");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1265");
skyway(foo[15:12], fd);
skyway(foo[11: 8], fd);
skyway(foo[ 7: 4], fd);
skyway(foo[ 3:0], fd);
$fwrite (fd, " 1266");
dude(fd);
$fwrite(fd, " 1267");
end
5'b?0???,
5'b110??:
begin
ozoneae(foo[26:24], fd);
$fwrite (fd, " 1268");
if (foo[23:21] == 3'b100)
$fwrite (fd, " 1269");
ozoneae(foo[18:16], fd);
if (foo[19])
$fwrite (fd, " 1270");
else
$fwrite (fd, " 1271");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1272");
ozonef3f4_iext(foo[20:19], foo[15:0], fd);
dude(fd);
$fwrite(fd, " 1273");
end
5'b010??,
5'b0110?:
begin
ozoneae(foo[18:16], fd);
if (foo[19])
$fwrite (fd, " 1274");
else
$fwrite (fd, " 1275");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1276");
ozonef3f4_iext(foo[20:19], foo[15:0], fd);
dude(fd);
$fwrite(fd, " 1277");
end
endcase
17'b00_1000_?_????_11_0011 :
begin
$fwrite (fd," 1278");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1279");
casez (foo[25:21])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite(fd, " 1280");
end
5'b0_00??:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1281");
ozoneae(foo[17:15], fd);
ozonebmuop(foo[25:21], fd);
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1282");
dude(fd);
$fwrite(fd, " 1283");
end
5'b0_01??:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1284");
ozoneae(foo[17:15], fd);
ozonebmuop(foo[25:21], fd);
ozonearm(foo[ 8: 6], fd);
dude(fd);
$fwrite(fd, " 1285");
end
5'b0_1011:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1286");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1287");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1288");
dude(fd);
$fwrite(fd, " 1289");
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1290");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1291");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1292");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1293");
dude(fd);
$fwrite(fd, " 1294");
end
5'b0_1111 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1295");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1296");
ozoneae(foo[ 8: 6], fd);
dude(fd);
$fwrite(fd, " 1297");
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1298");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1299");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1300");
ozonearm(foo[ 8: 6], fd);
$fwrite (fd, " 1301");
dude(fd);
$fwrite(fd, " 1302");
end
endcase
end
17'b00_0010_?_????_??_???? :
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1303");
skyway(foo[19:16], fd);
dude(fd);
$fwrite(fd, " 1304");
end
17'b00_01??_?_????_??_???? :
begin
if (foo[27])
begin
$fwrite (fd, " 1305");
if (foo[26])
$fwrite (fd, " 1306");
else
$fwrite (fd, " 1307");
skyway(foo[19:16], fd);
$fwrite (fd, " 1308");
ozonerab({1'b0, foo[25:20]}, fd);
end
else
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1309");
if (foo[26])
$fwrite (fd, " 1310");
else
$fwrite (fd, " 1311");
skyway(foo[19:16], fd);
$fwrite (fd, " 1312");
end
dude(fd);
$fwrite(fd, " 1313");
end
17'b01_000?_?_????_??_???? :
begin
if (foo[26])
begin
ozonerb(foo[25:20], fd);
$fwrite (fd, " 1314");
ozoneae(foo[18:16], fd);
ozonehl(foo[19], fd);
end
else
begin
ozoneae(foo[18:16], fd);
ozonehl(foo[19], fd);
$fwrite (fd, " 1315");
ozonerb(foo[25:20], fd);
end
dude(fd);
$fwrite(fd, " 1316");
end
17'b01_10??_?_????_??_???? :
begin
if (foo[27])
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1317");
ozonerx(foo, fd);
end
else
begin
ozonerx(foo, fd);
$fwrite (fd, " 1318");
ozonerab({1'b0, foo[25:20]}, fd);
end
dude(fd);
$fwrite(fd, " 1319");
end
17'b11_101?_?_????_??_???? :
begin
ozonerab (foo[26:20], fd);
$fwrite (fd, " 1320");
skyway(foo[19:16], fd);
skyway(foo[15:12], fd);
skyway(foo[11: 8], fd);
skyway(foo[ 7: 4], fd);
skyway(foo[ 3: 0], fd);
dude(fd);
$fwrite(fd, " 1321");
end
17'b11_0000_?_????_??_???? :
begin
casez (foo[25:23])
3'b00?:
begin
ozonerab(foo[22:16], fd);
$fwrite (fd, " 1322");
end
3'b01?:
begin
$fwrite (fd, " 1323");
if (foo[22:16]>=7'h60)
$fwrite (fd, " 1324");
else
ozonerab(foo[22:16], fd);
end
3'b110:
$fwrite (fd, " 1325");
3'b10?:
begin
$fwrite (fd, " 1326");
if (foo[22:16]>=7'h60)
$fwrite (fd, " 1327");
else
ozonerab(foo[22:16], fd);
end
3'b111:
begin
$fwrite (fd, " 1328");
ozonerab(foo[22:16], fd);
$fwrite (fd, " 1329");
end
endcase
dude(fd);
$fwrite(fd, " 1330");
end
17'b00_10??_?_????_?1_0000 :
begin
if (foo[27])
begin
$fwrite (fd, " 1331");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1332");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
$fwrite (fd, " 1333");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1334");
else
ozonerab(foo[26:20], fd);
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1335");
$fwrite (fd, " 1336");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1337");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
$fwrite (fd, " 1338");
end
dude(fd);
$fwrite(fd, " 1339");
end
17'b00_101?_1_0000_?1_0010 :
if (~|foo[11: 7])
begin
if (foo[ 6])
begin
$fwrite (fd, " 1340");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1341");
ozonejk(foo[ 5], fd);
$fwrite (fd, " 1342");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1343");
else
ozonerab(foo[26:20], fd);
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1344");
$fwrite (fd, " 1345");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1346");
ozonejk(foo[ 5], fd);
$fwrite (fd, " 1347");
end
dude(fd);
$fwrite(fd, " 1348");
end
else
$fwrite(fd, " 1349");
17'b00_100?_0_0011_?1_0101 :
if (~|foo[ 8: 7])
begin
if (foo[6])
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1350");
ozoneye(foo[14: 9],foo[ 5], fd);
end
else
begin
ozoneye(foo[14: 9],foo[ 5], fd);
$fwrite (fd, " 1351");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1352");
else
ozonerab(foo[26:20], fd);
end
dude(fd);
$fwrite(fd, " 1353");
end
else
$fwrite(fd, " 1354");
17'b00_1001_0_0000_?1_0010 :
if (~|foo[25:20])
begin
ozoneye(foo[14: 9],1'b0, fd);
$fwrite (fd, " 1355");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1356");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1357");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1358");
end
else
$fwrite(fd, " 1359");
17'b00_101?_0_????_?1_0010 :
if (~foo[13])
begin
if (foo[12])
begin
$fwrite (fd, " 1360");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1361");
else
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1362");
$fwrite (fd, " 1363");
skyway({1'b0,foo[18:16]}, fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1364");
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1365");
$fwrite (fd, " 1366");
skyway({1'b0,foo[18:16]}, fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1367");
end
end
else
$fwrite(fd, " 1368");
17'b01_01??_?_????_??_???? :
begin
ozonerab({1'b0,foo[27:26],foo[19:16]}, fd);
$fwrite (fd, " 1369");
ozonerab({1'b0,foo[25:20]}, fd);
dude(fd);
$fwrite(fd, " 1370");
end
17'b00_100?_?_???0_11_0101 :
if (~foo[6])
begin
$fwrite (fd," 1371");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1372");
ozonerab({foo[ 9: 7],foo[19:16]}, fd);
$fwrite (fd, " 1373");
ozonerab({foo[26:20]}, fd);
dude(fd);
$fwrite(fd, " 1374");
end
else
$fwrite(fd, " 1375");
17'b00_1000_?_????_?1_0010 :
if (~|foo[25:24])
begin
ozonery(foo[23:20], fd);
$fwrite (fd, " 1376");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1377");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1378");
end
else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6])
begin
ozonery(foo[23:20], fd);
$fwrite (fd, " 1379");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1380");
ozonejk(foo[ 5], fd);
dude(fd);
$fwrite(fd, " 1381");
end
else
$fwrite(fd, " 1382");
17'b11_01??_?_????_??_????,
17'b10_00??_?_????_??_???? :
if (foo[30])
$fwrite(fd, " 1383:%x", foo[27:16]);
else
$fwrite(fd, " 1384:%x", foo[27:16]);
17'b00_10??_?_????_01_1000 :
if (~foo[6])
begin
if (foo[7])
$fwrite(fd, " 1385:%x", foo[27: 8]);
else
$fwrite(fd, " 1386:%x", foo[27: 8]);
end
else
$fwrite(fd, " 1387");
17'b00_10??_?_????_11_1000 :
begin
$fwrite (fd," 1388");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1389");
if (foo[15])
$fwrite (fd, " 1390");
else
$fwrite (fd, " 1391");
skyway(foo[27:24], fd);
skyway(foo[23:20], fd);
skyway(foo[19:16], fd);
skyway(foo[ 9: 6], fd);
dude(fd);
$fwrite(fd, " 1392");
end
17'b11_0001_?_????_??_???? :
casez (foo[25:22])
4'b01?? :
begin
$fwrite (fd," 1393");
ozonecon(foo[20:16], fd);
case (foo[23:21])
3'h0 : $fwrite (fd, " 1394");
3'h1 : $fwrite (fd, " 1395");
3'h2 : $fwrite (fd, " 1396");
3'h3 : $fwrite (fd, " 1397");
3'h4 : $fwrite (fd, " 1398");
3'h5 : $fwrite (fd, " 1399");
3'h6 : $fwrite (fd, " 1400");
3'h7 : $fwrite (fd, " 1401");
endcase
dude(fd);
$fwrite(fd, " 1402");
end
4'b0000 :
$fwrite(fd, " 1403:%x", foo[21:16]);
4'b0010 :
if (~|foo[21:16])
$fwrite(fd, " 1404");
4'b1010 :
if (~|foo[21:17])
begin
if (foo[16])
$fwrite(fd, " 1405");
else
$fwrite(fd, " 1406");
end
default :
$fwrite(fd, " 1407");
endcase
17'b01_11??_?_????_??_???? :
if (foo[27:23] === 5'h00)
$fwrite(fd, " 1408:%x", foo[22:16]);
else
$fwrite(fd, " 1409:%x", foo[22:16]);
default: $fwrite(fd, " 1410");
endcase
end
endtask
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil)
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil)
endmodule
|
module t (clk);
input clk;
reg [2:0] a;
reg [2:0] b;
reg q;
f6 f6 (/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a[2:0]),
.b (b[2:0]),
.clk (clk));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 3'b000;
b <= 3'b100;
end
if (cyc==2) begin
a <= 3'b011;
b <= 3'b001;
if (q != 1'b0) $stop;
end
if (cyc==3) begin
a <= 3'b011;
b <= 3'b011;
if (q != 1'b0) $stop;
end
if (cyc==9) begin
if (q != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module f6 (a, b, clk, q);
input [2:0] a;
input [2:0] b;
input clk;
output q;
reg out;
function func6;
reg result;
input [5:0] src;
begin
if (src[5:0] == 6'b011011) begin
result = 1'b1;
end
else begin
result = 1'b0;
end
func6 = result;
end
endfunction
wire [5:0] w6 = {a, b};
always @(posedge clk) begin
out <= func6(w6);
end
assign q = out;
endmodule
|
module t (clk);
input clk;
reg [2:0] a;
reg [2:0] b;
reg q;
f6 f6 (/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a[2:0]),
.b (b[2:0]),
.clk (clk));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 3'b000;
b <= 3'b100;
end
if (cyc==2) begin
a <= 3'b011;
b <= 3'b001;
if (q != 1'b0) $stop;
end
if (cyc==3) begin
a <= 3'b011;
b <= 3'b011;
if (q != 1'b0) $stop;
end
if (cyc==9) begin
if (q != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module f6 (a, b, clk, q);
input [2:0] a;
input [2:0] b;
input clk;
output q;
reg out;
function func6;
reg result;
input [5:0] src;
begin
if (src[5:0] == 6'b011011) begin
result = 1'b1;
end
else begin
result = 1'b0;
end
func6 = result;
end
endfunction
wire [5:0] w6 = {a, b};
always @(posedge clk) begin
out <= func6(w6);
end
assign q = out;
endmodule
|
module t (clk);
input clk;
reg [2:0] a;
reg [2:0] b;
reg q;
f6 f6 (/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a[2:0]),
.b (b[2:0]),
.clk (clk));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 3'b000;
b <= 3'b100;
end
if (cyc==2) begin
a <= 3'b011;
b <= 3'b001;
if (q != 1'b0) $stop;
end
if (cyc==3) begin
a <= 3'b011;
b <= 3'b011;
if (q != 1'b0) $stop;
end
if (cyc==9) begin
if (q != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module f6 (a, b, clk, q);
input [2:0] a;
input [2:0] b;
input clk;
output q;
reg out;
function func6;
reg result;
input [5:0] src;
begin
if (src[5:0] == 6'b011011) begin
result = 1'b1;
end
else begin
result = 1'b0;
end
func6 = result;
end
endfunction
wire [5:0] w6 = {a, b};
always @(posedge clk) begin
out <= func6(w6);
end
assign q = out;
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg out1;
reg [4:0] out2;
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n",$time, cyc, crc, sum, out1,out2);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
if (cyc==0) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==90) begin
if (sum !== 64'hf0afc2bfa78277c5) $stop;
end
else if (cyc==91) begin
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in
);
input [23:0] in;
output reg out1;
output reg [4:0] out2;
always @* begin
// Test empty cases
casez (in[0])
endcase
casez (in)
24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00};
24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00};
24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01};
24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02};
24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03};
24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04};
24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05};
24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06};
24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07};
// Same pattern, but reversed to test we work OK.
24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17};
24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16};
24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15};
24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14};
24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13};
24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12};
24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11};
24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10};
24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f};
24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e};
24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d};
24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c};
24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b};
24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a};
24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09};
24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08};
endcase
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
enum integer {
EP_State_IDLE ,
EP_State_CMDSHIFT0 ,
EP_State_CMDSHIFT13 ,
EP_State_CMDSHIFT14 ,
EP_State_CMDSHIFT15 ,
EP_State_CMDSHIFT16 ,
EP_State_DWAIT ,
EP_State_DSHIFT0 ,
EP_State_DSHIFT1 ,
EP_State_DSHIFT15 } m_state_xr, m_state2_xr;
// Beginning of automatic ASCII enum decoding
reg [79:0] m_stateAscii_xr; // Decode of m_state_xr
always @(m_state_xr) begin
case ({m_state_xr})
EP_State_IDLE: m_stateAscii_xr = "idle ";
EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 ";
EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13";
EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14";
EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15";
EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16";
EP_State_DWAIT: m_stateAscii_xr = "dwait ";
EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 ";
EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 ";
EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 ";
default: m_stateAscii_xr = "%Error ";
endcase
end
// End of automatics
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
if (cyc==1) begin
m_state_xr <= EP_State_IDLE;
m_state2_xr <= EP_State_IDLE;
end
if (cyc==2) begin
if (m_stateAscii_xr != "idle ") $stop;
m_state_xr <= EP_State_CMDSHIFT13;
if (m_state2_xr != EP_State_IDLE) $stop;
m_state2_xr <= EP_State_CMDSHIFT13;
end
if (cyc==3) begin
if (m_stateAscii_xr != "cmdshift13") $stop;
m_state_xr <= EP_State_CMDSHIFT16;
if (m_state2_xr != EP_State_CMDSHIFT13) $stop;
m_state2_xr <= EP_State_CMDSHIFT16;
end
if (cyc==4) begin
if (m_stateAscii_xr != "cmdshift16") $stop;
m_state_xr <= EP_State_DWAIT;
if (m_state2_xr != EP_State_CMDSHIFT16) $stop;
m_state2_xr <= EP_State_DWAIT;
end
if (cyc==9) begin
if (m_stateAscii_xr != "dwait ") $stop;
if (m_state2_xr != EP_State_DWAIT) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
fastclk, clk
);
`ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge
`define posstyle posedge
`define negstyle negedge
`else
`define posstyle
`define negstyle
`endif
input fastclk;
input clk;
reg [7:0] data;
reg [7:0] data_a;
reg [7:0] data_a_a;
reg [7:0] data_a_b;
reg [7:0] data_b;
reg [7:0] data_b_a;
reg [7:0] data_b_b;
reg [8*6-1:0] check [100:0];
wire [8*6-1:0] compare = {data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b};
initial begin
check[7'd19] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd20] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd21] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd22] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd23] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd24] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd25] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd26] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd27] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd28] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd29] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd30] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd31] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd32] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd33] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd34] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd35] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd36] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
check[7'd37] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
end
// verilator lint_off COMBDLY
always @ (`posstyle clk /*AS*/ or data) begin
if (clk) begin
data_a <= data + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_a) begin
if (clk) begin
data_a_a <= data_a + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_b) begin
if (clk) begin
data_b_a <= data_b + 8'd1;
end
end
always @ (`negstyle clk /*AS*/ or data or data_a) begin
if (~clk) begin
data_b <= data + 8'd1;
data_a_b <= data_a + 8'd1;
data_b_b <= data_b + 8'd1;
end
end
integer cyc; initial cyc=0;
always @ (posedge fastclk) begin
cyc <= cyc+1;
`ifdef TEST_VERBOSE
$write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b);
`endif
if (cyc>=19 && cyc<36) begin
if (compare !== check[cyc]) begin
$write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]);
$stop;
end
end
if (cyc == 10) begin
data <= 8'd12;
end
if (cyc == 20) begin
data <= 8'd20;
end
if (cyc == 30) begin
data <= 8'd30;
end
if (cyc == 40) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
fastclk, clk
);
`ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge
`define posstyle posedge
`define negstyle negedge
`else
`define posstyle
`define negstyle
`endif
input fastclk;
input clk;
reg [7:0] data;
reg [7:0] data_a;
reg [7:0] data_a_a;
reg [7:0] data_a_b;
reg [7:0] data_b;
reg [7:0] data_b_a;
reg [7:0] data_b_b;
reg [8*6-1:0] check [100:0];
wire [8*6-1:0] compare = {data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b};
initial begin
check[7'd19] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd20] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd21] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd22] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd23] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd24] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd25] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd26] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd27] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd28] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd29] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd30] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd31] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd32] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd33] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd34] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd35] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd36] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
check[7'd37] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
end
// verilator lint_off COMBDLY
always @ (`posstyle clk /*AS*/ or data) begin
if (clk) begin
data_a <= data + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_a) begin
if (clk) begin
data_a_a <= data_a + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_b) begin
if (clk) begin
data_b_a <= data_b + 8'd1;
end
end
always @ (`negstyle clk /*AS*/ or data or data_a) begin
if (~clk) begin
data_b <= data + 8'd1;
data_a_b <= data_a + 8'd1;
data_b_b <= data_b + 8'd1;
end
end
integer cyc; initial cyc=0;
always @ (posedge fastclk) begin
cyc <= cyc+1;
`ifdef TEST_VERBOSE
$write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b);
`endif
if (cyc>=19 && cyc<36) begin
if (compare !== check[cyc]) begin
$write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]);
$stop;
end
end
if (cyc == 10) begin
data <= 8'd12;
end
if (cyc == 20) begin
data <= 8'd20;
end
if (cyc == 30) begin
data <= 8'd30;
end
if (cyc == 40) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
fastclk, clk
);
`ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge
`define posstyle posedge
`define negstyle negedge
`else
`define posstyle
`define negstyle
`endif
input fastclk;
input clk;
reg [7:0] data;
reg [7:0] data_a;
reg [7:0] data_a_a;
reg [7:0] data_a_b;
reg [7:0] data_b;
reg [7:0] data_b_a;
reg [7:0] data_b_b;
reg [8*6-1:0] check [100:0];
wire [8*6-1:0] compare = {data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b};
initial begin
check[7'd19] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd20] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd21] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd22] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd23] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd24] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd25] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd26] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd27] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd28] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd29] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd30] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd31] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd32] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd33] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd34] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd35] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd36] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
check[7'd37] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
end
// verilator lint_off COMBDLY
always @ (`posstyle clk /*AS*/ or data) begin
if (clk) begin
data_a <= data + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_a) begin
if (clk) begin
data_a_a <= data_a + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_b) begin
if (clk) begin
data_b_a <= data_b + 8'd1;
end
end
always @ (`negstyle clk /*AS*/ or data or data_a) begin
if (~clk) begin
data_b <= data + 8'd1;
data_a_b <= data_a + 8'd1;
data_b_b <= data_b + 8'd1;
end
end
integer cyc; initial cyc=0;
always @ (posedge fastclk) begin
cyc <= cyc+1;
`ifdef TEST_VERBOSE
$write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b);
`endif
if (cyc>=19 && cyc<36) begin
if (compare !== check[cyc]) begin
$write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]);
$stop;
end
end
if (cyc == 10) begin
data <= 8'd12;
end
if (cyc == 20) begin
data <= 8'd20;
end
if (cyc == 30) begin
data <= 8'd30;
end
if (cyc == 40) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module cclk_detector #(
parameter CLK_RATE = 50000000
)(
input clk,
input rst,
input cclk,
output ready
);
parameter CTR_SIZE = $clog2(CLK_RATE/50000);
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg ready_d, ready_q;
assign ready = ready_q;
// ready should only go high once cclk has been high for a while
// if cclk ever falls, ready should go low again
always @(ctr_q or cclk) begin
ready_d = 1'b0;
if (cclk == 1'b0) begin // when cclk is 0 reset the counter
ctr_d = 1'b0;
end else if (ctr_q != {CTR_SIZE{1'b1}}) begin
ctr_d = ctr_q + 1'b1; // counter isn't max value yet
end else begin
ctr_d = ctr_q;
ready_d = 1'b1; // counter reached the max, we are ready
end
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
ready_q <= 1'b0;
end else begin
ctr_q <= ctr_d;
ready_q <= ready_d;
end
end
endmodule
|
module t (clk);
input clk;
tpub p1 (.clk(clk), .i(32'd1));
tpub p2 (.clk(clk), .i(32'd2));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
`ifdef verilator
$c("publicTop();");
`endif
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
task publicTop;
// verilator public
// We have different optimizations if only one of something, so try it out.
$write("Hello in publicTop\n");
endtask
endmodule
|
module tpub (
input clk,
input [31:0] i);
reg [23:0] var_long;
reg [59:0] var_quad;
reg [71:0] var_wide;
reg var_bool;
// verilator lint_off BLKANDNBLK
reg [11:0] var_flop;
// verilator lint_on BLKANDNBLK
reg [23:0] got_long /*verilator public*/;
reg [59:0] got_quad /*verilator public*/;
reg [71:0] got_wide /*verilator public*/;
reg got_bool /*verilator public*/;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
// cyc==1 is in top level
if (cyc==2) begin
publicNoArgs;
publicSetBool(1'b1);
publicSetLong(24'habca);
publicSetQuad(60'h4444_3333_2222);
publicSetWide(72'h12_5678_9123_1245_2352);
var_flop <= 12'habe;
end
if (cyc==3) begin
if (1'b1 != publicGetSetBool(1'b0)) $stop;
if (24'habca != publicGetSetLong(24'h1234)) $stop;
if (60'h4444_3333_2222 != publicGetSetQuad(60'h123_4567_89ab)) $stop;
if (72'h12_5678_9123_1245_2352 != publicGetSetWide(72'hac_abca_aaaa_bbbb_1234)) $stop;
end
if (cyc==4) begin
publicGetBool(got_bool);
if (1'b0 != got_bool) $stop;
publicGetLong(got_long);
if (24'h1234 != got_long) $stop;
publicGetQuad(got_quad);
if (60'h123_4567_89ab != got_quad) $stop;
publicGetWide(got_wide);
if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop;
end
//
`ifdef VERILATOR_PUBLIC_TASKS
if (cyc==11) begin
$c("publicNoArgs();");
$c("publicSetBool(true);");
$c("publicSetLong(0x11bca);");
$c("publicSetQuad(VL_ULL(0x66655554444));");
$c("publicSetFlop(0x321);");
//Unsupported: $c("WData w[3] = {0x12, 0x5678_9123, 0x1245_2352}; publicSetWide(w);");
end
if (cyc==12) begin
$c("got_bool = publicGetSetBool(true);");
$c("got_long = publicGetSetLong(0x11bca);");
$c("got_quad = publicGetSetQuad(VL_ULL(0xaaaabbbbcccc));");
end
if (cyc==13) begin
$c("{ bool gb; publicGetBool(gb); got_bool=gb; }");
if (1'b1 != got_bool) $stop;
$c("publicGetLong(got_long);");
if (24'h11bca != got_long) $stop;
$c("{ vluint64_t qq; publicGetQuad(qq); got_quad=qq; }");
if (60'haaaa_bbbb_cccc != got_quad) $stop;
$c("{ WData gw[3]; publicGetWide(gw); VL_ASSIGN_W(72,got_wide,gw); }");
if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop;
//Below doesn't work, because we're calling it inside the loop that sets var_flop
// if (12'h321 != var_flop) $stop;
end
if (cyc==14) begin
if ($c32("publicInstNum()") != i) $stop;
end
`endif
end
end
task publicEmpty;
// verilator public
begin end
endtask
task publicNoArgs;
// verilator public
$write("Hello in publicNoArgs\n");
endtask
task publicSetBool;
// verilator public
input in_bool;
var_bool = in_bool;
endtask
task publicSetLong;
// verilator public
input [23:0] in_long;
reg [23:0] not_long;
begin
not_long = ~in_long; // Test that we can have local variables
var_long = ~not_long;
end
endtask
task publicSetQuad;
// verilator public
input [59:0] in_quad;
var_quad = in_quad;
endtask
task publicSetFlop;
// verilator public
input [11:0] in_flop;
var_flop = in_flop;
endtask
task publicSetWide;
// verilator public
input [71:0] in_wide;
var_wide = in_wide;
endtask
task publicGetBool;
// verilator public
output out_bool;
out_bool = var_bool;
endtask
task publicGetLong;
// verilator public
output [23:0] out_long;
out_long = var_long;
endtask
task publicGetQuad;
// verilator public
output [59:0] out_quad;
out_quad = var_quad;
endtask
task publicGetWide;
// verilator public
output [71:0] out_wide;
out_wide = var_wide;
endtask
function publicGetSetBool;
// verilator public
input in_bool;
begin
publicGetSetBool = var_bool;
var_bool = in_bool;
end
endfunction
function [23:0] publicGetSetLong;
// verilator public
input [23:0] in_long;
begin
publicGetSetLong = var_long;
var_long = in_long;
end
endfunction
function [59:0] publicGetSetQuad;
// verilator public
input [59:0] in_quad;
begin
publicGetSetQuad = var_quad;
var_quad = in_quad;
end
endfunction
function [71:0] publicGetSetWide;
// Can't be public, as no wide return types in C++
input [71:0] in_wide;
begin
publicGetSetWide = var_wide;
var_wide = in_wide;
end
endfunction
`ifdef VERILATOR_PUBLIC_TASKS
function [31:0] publicInstNum;
// verilator public
publicInstNum = i;
endfunction
`endif
endmodule
|
module pbkdfengine
(hash_clk, pbkdf_clk, data1, data2, data3, target, nonce_msb, nonce_out, golden_nonce_out, golden_nonce_match, loadnonce,
salsa_din, salsa_dout, salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift, hash_out);
input hash_clk; // Just drives shift register
input pbkdf_clk;
input [255:0] data1;
input [255:0] data2;
input [127:0] data3;
input [31:0] target;
input [3:0] nonce_msb;
output reg [31:0] nonce_out;
output reg [31:0] hash_out; // Hash value for nonce_out (ztex port)
output [31:0] golden_nonce_out;
output golden_nonce_match; // Strobe valid one cycle on a match (needed for serial comms)
input loadnonce; // Strobe loads nonce (used for serial interface)
parameter SBITS = 8; // Shift data path width
input [SBITS-1:0] salsa_dout;
output [SBITS-1:0] salsa_din;
input salsa_busy, salsa_result; // NB hash_clk domain
output salsa_reset;
output salsa_start;
output reg salsa_shift = 1'b0; // NB hash_clk domain
reg [4:0]resetcycles = 4'd0;
reg reset = 1'b0;
assign salsa_reset = reset; // Propagate reset to salsaengine
`ifdef WANTCYCLICRESET
reg [23:0]cycresetcount = 24'd0;
`endif
always @ (posedge pbkdf_clk)
begin
// Hard code a 31 cycle reset (NB assumes THREADS=16 in salsaengine, else we need more)
// NB hash_clk is faster than pbkdf_clk so the salsaengine will actually be initialised well before
// this period ends, but keep to 15 for now as simulation uses equal pbkdf and salsa clock speeds.
resetcycles <= resetcycles + 1'd1;
if (resetcycles == 0)
reset <= 1'b1;
if (resetcycles == 31)
begin
reset <= 1'b0;
resetcycles <= 31;
end
`ifdef WANTCYCLICRESET
// Cyclical reset every 2_500_000 clocks to ensure salsa pipeline does not drift out of sync
// This may be unneccessary if we reset every loadnonce
// Actually it seems to do more harm than good, so disabled
cycresetcount <= cycresetcount + 1'd1;
if (cycresetcount == 2_500_000) // 10 per second at 25MHz (adjust as neccessary)
begin
cycresetcount <= 24'd0;
resetcycles <= 5'd0;
end
`endif
// Reset on loadnonce (the hash results will be junk anyway since data changes, so no loss of shares)
if (loadnonce)
resetcycles <= 5'd0;
end
`ifndef ICARUS
reg [31:0] nonce_previous_load = 32'hffffffff; // See note in salsa mix FSM
`endif
`ifndef NOMULTICORE
`ifdef SIM
reg [27:0] nonce_cnt = 28'h318f; // Start point for simulation (NB also define SIM in serial.v)
`else
reg [27:0] nonce_cnt = 28'd0; // Multiple cores use different prefix
`endif
wire [31:0] nonce;
assign nonce = { nonce_msb, nonce_cnt };
`else
reg [31:0] nonce = 32'd0; // NB Initially loaded from data3[127:96], see salsa mix FSM
`endif
reg [31:0] nonce_sr = 32'd0; // Nonce is shifted to salsaengine for storage/retrieval (hash_clk domain)
reg [31:0] golden_nonce = 32'd0;
assign golden_nonce_out = golden_nonce;
reg golden_nonce_match = 1'b0;
reg [2:0] nonce_wait = 3'd0;
reg [255:0] rx_state;
reg [511:0] rx_input;
wire [255:0] tx_hash;
reg [255:0] khash = 256'd0; // Key hash (NB scrypt.c calls this ihash)
reg [255:0] ihash = 256'd0; // IPAD hash
reg [255:0] ohash = 256'd0; // OPAD hash
`ifdef SIM
reg [255:0] final_hash = 256'd0; // Just for DEBUG, only need top 32 bits in live code.
`endif
reg [2:0] blockcnt = 3'd0; // Takes values 1..5 for block iteration
reg [1023:0] Xbuf = 1024'd0; // Shared input/output buffer and shift register (hash_clk domain)
reg [5:0] cnt = 6'd0;
wire feedback;
assign feedback = (cnt != 6'b0);
assign salsa_din = Xbuf[1023:1024-SBITS];
wire [1023:0] MixOutRewire; // Need to do endian conversion (see the generate below)
// MixOut is little-endian word format to match scrypt.c so convert back to big-endian
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] mix;
assign mix = Xbuf[`IDX(i)]; // NB MixOut now shares Xbuf since shifted in/out
assign MixOutRewire[`IDX(i)] = { mix[7:0], mix[15:8], mix[23:16], mix[31:24] };
end
endgenerate
// Interface control. This should be OK provided the threads remain evenly spaced (hence we reset on loadnonce)
reg SMixInRdy_state = 1'b0; // SMix input ready flag (set in SHA256, reset in SMIX)
reg SMixOutRdy_state = 1'b0; // SMix output ready flag (set in SMIX, reset in SHA256)
wire SMixInRdy;
wire SMixOutRdy;
reg Set_SMixInRdy = 1'b0;
reg Clr_SMixOutRdy = 1'b0;
wire Clr_SMixInRdy;
wire Set_SMixOutRdy;
reg [4:0]salsa_busy_d = 0; // Sync to pbkdf_clk domain
reg [4:0]salsa_result_d = 0;
always @ (posedge hash_clk)
begin
// Sync to pbkdf_clk domain
salsa_busy_d[0] <= salsa_busy;
if (salsa_busy & ~ salsa_busy_d[0])
salsa_busy_d[1] <= ~ salsa_busy_d[1]; // Toggle on busy going high
salsa_result_d[0] <= salsa_result;
if (salsa_result & ~ salsa_result_d[0])
salsa_result_d[1] <= ~ salsa_result_d[1]; // Toggle on result going high
end
always @ (posedge pbkdf_clk)
begin
salsa_busy_d[4:2] <= salsa_busy_d[3:1];
salsa_result_d[4:2] <= salsa_result_d[3:1];
if (Set_SMixInRdy)
SMixInRdy_state <= 1'b1;
if (Clr_SMixInRdy)
SMixInRdy_state <= 1'b0; // Clr overrides set
if (Set_SMixOutRdy)
SMixOutRdy_state <= 1'b1;
if (Clr_SMixOutRdy)
SMixOutRdy_state <= 1'b0; // Clr overrides set
// CARE there is a race with Set_SMixInRdy, Clr_SMixOutRdy which are set in the FSM
// Need to assert reset for several cycles to ensure consistency (acutally use 15 since salsaengine needs more)
if (reset)
begin // Reset takes priority
SMixInRdy_state <= 1'b0;
SMixOutRdy_state <= 1'b0;
end
end
assign Clr_SMixInRdy = SMixInRdy_state & (salsa_busy_d[3] ^ salsa_busy_d[4]); // Clear on transition to busy
assign Set_SMixOutRdy = ~SMixOutRdy_state & (salsa_result_d[3] ^ salsa_result_d[4]); // Set on transition to result
// Achieves identical timing to original version, but probably overkill
assign SMixInRdy = Clr_SMixInRdy ? 1'b0 : Set_SMixInRdy ? 1'b1 : SMixInRdy_state;
assign SMixOutRdy = Clr_SMixOutRdy ? 1'b0 : Set_SMixOutRdy ? 1'b1 : SMixOutRdy_state;
assign salsa_start = SMixInRdy;
// Clock crossing flags for shift register control (span pbkdf_clk, hash_clk domains)
reg [3:0]Xbuf_load_request = 1'b0;
reg [3:0]shift_request = 1'b0;
reg [3:0]shift_acknowledge = 1'b0;
// Controller FSM for PBKDF2_SHA256_80_128 (multiple hashes using the sha256_transform)
// Based on scrypt.c from cgminer (Colin Percival, ArtForz)
parameter S_IDLE=0,
S_H1= 1, S_H2= 2, S_H3= 3, S_H4= 4, S_H5= 5, S_H6= 6, // Initial hash of block header (khash)
S_I1= 7, S_I2= 8, S_I3= 9, S_I4=10, S_I5=11, S_I6=12, // IPAD hash (ihash)
S_O1=13, S_O2=14, S_O3=15, // OPAD hash (ohash)
S_B1=16, S_B2=17, S_B3=18, S_B4=19, S_B5=20, S_B6=21, // Iterate blocks
S_NONCE=22, S_SHIFT_IN=41, S_SHIFT_OUT=42, // Direction relative to salsa unit
// Final PBKDF2_SHA256_80_128_32 (reuses S_H1 to S_H6 for khash, alternatively could piplenine value)
S_R1=23, S_R2=24, S_R3=25, S_R4=26, S_R5=27, S_R6=28, // Final PBKDF2_SHA256_80_128_32
S_R7=29, S_R8=30, S_R9=31, S_R10=32, S_R11=33, S_R12=34,
S_R13=35, S_R14=36, S_R15=37, S_R16=38, S_R17=39, S_R18=40;
reg [5:0] state = S_IDLE;
reg mode = 0; // 0=PBKDF2_SHA256_80_128, 1=PBKDF2_SHA256_80_128_32
reg start_output = 0;
always @ (posedge pbkdf_clk)
begin
Set_SMixInRdy <= 1'b0; // Ugly hack, these are overriden below
Clr_SMixOutRdy <= 1'b0;
golden_nonce_match <= 1'b0; // Default to reset
shift_acknowledge[3:1] <= shift_acknowledge[2:0]; // Clock crossing
`ifdef ICARUS
if (loadnonce) // Separate clock domains means comparison is unsafe
`else
if (loadnonce || (nonce_previous_load != data3[127:96]))
`endif
begin
`ifdef NOMULTICORE
nonce <= data3[127:96]; // Supports loading of initial nonce for test purposes (potentially
// overriden by the increment below, but this occurs very rarely)
// This also gives a consistent start point when we send the first work
// packet (but ONLY the first one since its always zero) when using live data
// as we initialise nonce_previous_load to ffffffff
`else
nonce_cnt <= data3[123:96]; // The 4 msb of nonce are hardwired in MULTICORE mode, so test nonce
// needs to be <= 0fffffff and will only match in the 0 core
`endif
`ifndef ICARUS
nonce_previous_load <= data3[127:96];
`endif
end
if (reset == 1'b1)
begin
state <= S_IDLE;
start_output <= 1'b0;
end
else
begin
case (state)
S_IDLE: begin
if (SMixOutRdy & ~start_output)
begin
shift_request[0] <= ~shift_request[0]; // Request shifter to start
state <= S_SHIFT_OUT;
end
else
begin
if (start_output || // Process output
!SMixInRdy) // Process input unless already done
begin
start_output <= 1'b0;
mode <= 1'b0;
// Both cases use same initial calculaton of khash (its not worth trying to reuse previous khash
// for the second case as we're not constrained by SHA256 timing)
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { data2, data1 }; // Block header is passwd (used as key)
blockcnt <= 3'd1;
cnt <= 6'd0;
if (SMixOutRdy) // Give preference to output
mode <= 1'b1;
state <= S_H1;
end
end
end
// Hash the block header (result is khash)
S_H1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H2;
end
end
S_H2: begin // Sync hash
state <= S_H3;
end
S_H3: begin // Sync hash
rx_state <= tx_hash;
// Hash last 16 bytes of header including nonce and padded to 64 bytes with 1, zeros and length
// NB this sequence is used for both input and final PBKDF2_SHA256, hence switch nonce on mode
rx_input <= { 384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000,
mode ? nonce_sr : nonce, data3[95:0] };
state <= S_H4;
end
S_H4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H5;
end
end
S_H5: begin // Sync hash
state <= S_H6;
end
S_H6: begin // Sync hash
khash <= tx_hash; // Save for OPAD hash
// Setup for IPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h3636363636363636363636363636363636363636363636363636363636363636 ,
tx_hash ^ 256'h3636363636363636363636363636363636363636363636363636363636363636 };
cnt <= 6'd0;
if (mode)
state <= S_R1;
else
state <= S_I1;
end
// IPAD hash
S_I1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I2;
end
end
S_I2: begin // Sync hash
state <= S_I3;
end
S_I3: begin // Sync hash
rx_state <= tx_hash;
rx_input <= { data2, data1 }; // Passwd (used as message)
state <= S_I4;
end
S_I4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I5;
end
end
S_I5: begin // Sync hash
state <= S_I6;
end
S_I6: begin // Sync hash
ihash <= tx_hash; // Save result
// Setup for OPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_O1;
end
// OPAD hash
S_O1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_O2;
end
end
S_O2: begin // Sync hash
state <= S_O3;
end
S_O3: begin // Sync hash
ohash <= tx_hash; // Save result
// Setup for block iteration
rx_state <= ihash;
// TODO hardwire top 29 bits of blockcnt as zero
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] }; // blockcnt is 3 bits, top 29 are hardcoded 0
blockcnt <= blockcnt + 1'd1; // Increment for next time
cnt <= 6'd0;
state <= S_B1;
end
// Block iteration (4 cycles)
S_B1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B2;
end
end
S_B2: begin // Sync hash
state <= S_B3;
end
S_B3: begin // Sync hash
rx_state <= ohash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, tx_hash };
state <= S_B4;
end
S_B4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B5;
end
end
S_B5: begin // Sync hash
state <= S_B6;
end
S_B6: begin
khash <= tx_hash; // Save temporarily (for Xbuf)
Xbuf_load_request[0] <= ~Xbuf_load_request[0]; // NB also loads nonce_sr
if (blockcnt == 3'd5)
begin
nonce_wait <= 3'd7;
state <= S_NONCE;
end
else begin
// Setup for next block
rx_state <= ihash;
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] }; // blockcnt is 3 bits, top 29 are hardcoded 0
blockcnt <= blockcnt + 1'd1; // Increment for next time
cnt <= 6'd0;
state <= S_B1;
end
end
S_NONCE: begin
// Need to delay a few clocks for Xbuf_load_request to complete
nonce_wait <= nonce_wait - 1'd1;
if (nonce_wait == 0)
begin
`ifndef NOMULTICORE
nonce_cnt <= nonce_cnt + 1'd1;
`else
nonce <= nonce + 1'd1;
`endif
shift_request[0] <= ~shift_request[0];
state <= S_SHIFT_IN;
end
end
S_SHIFT_IN: begin // Shifting from PBKDF2_SHA256 to salsa
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
Set_SMixInRdy <= 1'd1; // Flag salsa to start
state <= S_IDLE;
end
end
S_SHIFT_OUT: begin // Shifting from salsa to PBKDF2_SHA256
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
start_output <= 1'd1; // Flag self to start
state <= S_IDLE;
end
end
// Final PBKDF2_SHA256_80_128_32 NB Entered from S_H6 via mode flag
// Similar to S_I0 but using MixOut as salt and finalblk padding
S_R1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R2;
end
end
S_R2: begin // Sync hash
state <= S_R3;
end
S_R3: begin // Sync hash
rx_state <= tx_hash;
rx_input <= MixOutRewire[511:0]; // Salt (first block)
state <= S_R4;
end
S_R4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R5;
end
end
S_R5: begin // Sync hash
state <= S_R6;
end
S_R6: begin // Sync hash
rx_state <= tx_hash;
rx_input <= MixOutRewire[1023:512]; // Salt (second block)
state <= S_R7;
end
S_R7: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R8;
end
end
S_R8: begin // Sync hash
state <= S_R9;
end
S_R9: begin // Sync hash
rx_state <= tx_hash;
// Final padding
rx_input <= 512'h00000620000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000001;
state <= S_R10;
end
S_R10: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R11;
end
end
S_R11: begin // Sync hash
state <= S_R12;
end
S_R12: begin // Sync hash
ihash <= tx_hash; // Save (reuse ihash)
// Setup for OPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_R13;
end
S_R13: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R14;
end
end
S_R14: begin // Sync hash
state <= S_R15;
end
S_R15: begin // Sync hash
rx_state <= tx_hash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, ihash };
state <= S_R16;
end
S_R16: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R17;
end
end
S_R17: begin // Sync hash
state <= S_R18;
end
S_R18: begin // Sync hash
// Check for golden nonce in tx_hash
`ifdef SIM
final_hash <= tx_hash; // For debug
`endif
nonce_out <= nonce_sr; // Ztex port
hash_out <= tx_hash[255:224];
// Could optimise target calc ...
if ( { tx_hash[231:224], tx_hash[239:232], tx_hash[247:240], tx_hash[255:248] } < target)
begin
golden_nonce <= nonce_sr;
golden_nonce_match <= 1'b1; // Set flag (for one cycle only, see default at top)
end
state <= S_IDLE;
mode <= 1'b0;
// SMixOutRdy <= 1'b0; // Original version
Clr_SMixOutRdy <= 1'b1; // Ugly hack
end
endcase
end
end
// Shift register control - NB hash_clk domain
reg [10:0]shift_count = 11'd0; // hash_clk domain
always @ (posedge hash_clk)
begin
if (reset)
begin
salsa_shift <= 1'b0;
shift_count <= 11'd0;
end
// Clock crossing logic
Xbuf_load_request[3:1] <= Xbuf_load_request[2:0];
if (Xbuf_load_request[3] != Xbuf_load_request[2])
begin
// Shift output into X buffer from MSB->LSB
Xbuf[255:0] <= Xbuf[511:256];
Xbuf[511:256] <= Xbuf[767:512];
Xbuf[767:512] <= Xbuf[1023:768];
Xbuf[1023:768] <= khash;
nonce_sr <= nonce; // Loaded several times, but of no consequence
end
shift_request[3:1] <= shift_request[2:0];
if (shift_request[3] != shift_request[2])
begin
salsa_shift <= 1'b1;
end
if (salsa_shift)
begin
shift_count <= shift_count + 1'b1;
Xbuf <= { Xbuf[1023-SBITS:0], nonce_sr[31:32-SBITS] };
nonce_sr <= { nonce_sr[31-SBITS:0], salsa_dout };
end
if (shift_count == (1024+32)/SBITS-1)
begin
shift_acknowledge[0] = ~shift_acknowledge[0];
shift_count <= 0;
salsa_shift <= 0;
end
end
// Using LOOP=64 to simplify timing (needs slightly modified version of original sha256_transform.v)
// since pipelining is inappropriate for ltc (we need to rehash same data several times in succession)
sha256_transform # (.LOOP(64)) sha256_blk (
.clk(pbkdf_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(rx_state),
.rx_input(rx_input),
.tx_hash(tx_hash)
);
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [3:0] l_stop = crc[3:0];
wire [3:0] l_break = crc[7:4];
wire [3:0] l_continue = crc[11:8];
/*AUTOWIRE*/
wire [15:0] out0 = Test0(l_stop, l_break, l_continue);
wire [15:0] out1 = Test1(l_stop, l_break, l_continue);
wire [15:0] out2 = Test2(l_stop, l_break, l_continue);
wire [15:0] out3 = Test3(l_stop, l_break, l_continue);
// Aggregate outputs into a single result vector
wire [63:0] result = {out3,out2,out1,out0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
if (out0!==out1) $stop;
if (out0!==out2) $stop;
if (out0!==out3) $stop;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h293e9f9798e97da0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
function [15:0] Test0;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
reg broken;
Test0 = 0;
broken = 0;
begin
for (i=1; i<20; i=i+1) begin
if (!broken) begin
Test0 = Test0 + 1;
if (i[3:0] != loop_continue) begin // continue
if (i[3:0] == loop_break) begin
broken = 1'b1;
end
if (!broken) begin
Test0 = Test0 + i[15:0];
end
end
end
end
end
endfunction
function [15:0] Test1;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test1 = 0;
begin : outer_block
for (i=1; i<20; i=i+1) begin : inner_block
Test1 = Test1 + 1;
// continue, IE jump to end-of-inner_block. Must be inside inner_block.
if (i[3:0] == loop_continue) disable inner_block;
// break, IE jump to end-of-outer_block. Must be inside outer_block.
if (i[3:0] == loop_break) disable outer_block;
Test1 = Test1 + i[15:0];
end : inner_block
end : outer_block
endfunction
function [15:0] Test2;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test2 = 0;
begin
for (i=1; i<20; i=i+1) begin
Test2 = Test2 + 1;
if (i[3:0] == loop_continue) continue;
if (i[3:0] == loop_break) break;
Test2 = Test2 + i[15:0];
end
end
endfunction
function [15:0] Test3;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test3 = 0;
begin
for (i=1; i<20; i=i+1) begin
Test3 = Test3 + 1;
if (i[3:0] == loop_continue) continue;
// return, IE jump to end-of-function optionally setting return value
if (i[3:0] == loop_break) return Test3;
Test3 = Test3 + i[15:0];
end
end
endfunction
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [3:0] l_stop = crc[3:0];
wire [3:0] l_break = crc[7:4];
wire [3:0] l_continue = crc[11:8];
/*AUTOWIRE*/
wire [15:0] out0 = Test0(l_stop, l_break, l_continue);
wire [15:0] out1 = Test1(l_stop, l_break, l_continue);
wire [15:0] out2 = Test2(l_stop, l_break, l_continue);
wire [15:0] out3 = Test3(l_stop, l_break, l_continue);
// Aggregate outputs into a single result vector
wire [63:0] result = {out3,out2,out1,out0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
if (out0!==out1) $stop;
if (out0!==out2) $stop;
if (out0!==out3) $stop;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h293e9f9798e97da0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
function [15:0] Test0;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
reg broken;
Test0 = 0;
broken = 0;
begin
for (i=1; i<20; i=i+1) begin
if (!broken) begin
Test0 = Test0 + 1;
if (i[3:0] != loop_continue) begin // continue
if (i[3:0] == loop_break) begin
broken = 1'b1;
end
if (!broken) begin
Test0 = Test0 + i[15:0];
end
end
end
end
end
endfunction
function [15:0] Test1;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test1 = 0;
begin : outer_block
for (i=1; i<20; i=i+1) begin : inner_block
Test1 = Test1 + 1;
// continue, IE jump to end-of-inner_block. Must be inside inner_block.
if (i[3:0] == loop_continue) disable inner_block;
// break, IE jump to end-of-outer_block. Must be inside outer_block.
if (i[3:0] == loop_break) disable outer_block;
Test1 = Test1 + i[15:0];
end : inner_block
end : outer_block
endfunction
function [15:0] Test2;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test2 = 0;
begin
for (i=1; i<20; i=i+1) begin
Test2 = Test2 + 1;
if (i[3:0] == loop_continue) continue;
if (i[3:0] == loop_break) break;
Test2 = Test2 + i[15:0];
end
end
endfunction
function [15:0] Test3;
input [3:0] loop_stop;
input [3:0] loop_break;
input [3:0] loop_continue;
integer i;
Test3 = 0;
begin
for (i=1; i<20; i=i+1) begin
Test3 = Test3 + 1;
if (i[3:0] == loop_continue) continue;
// return, IE jump to end-of-function optionally setting return value
if (i[3:0] == loop_break) return Test3;
Test3 = Test3 + i[15:0];
end
end
endfunction
endmodule
|
module outputs)
wire myevent; // From test of Test.v
wire myevent_pending; // From test of Test.v
wire [1:0] state; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.state (state[1:0]),
.myevent (myevent),
.myevent_pending (myevent_pending),
// Inputs
.clk (clk),
.reset (reset));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, myevent_pending,myevent,state};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x me=%0x mep=%x\n",$time, cyc, crc, result, myevent, myevent_pending);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
reset <= (cyc<2);
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4e93a74bd97b25ef
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module Test (/*AUTOARG*/
// Outputs
state, myevent, myevent_pending,
// Inputs
clk, reset
);
input clk;
input reset;
output [1:0] state;
output myevent;
output myevent_pending;
reg [5:0] count = 0;
always @ (posedge clk)
if (reset) count <= 0;
else count <= count + 1;
reg myevent = 1'b0;
always @ (posedge clk)
myevent <= (count == 6'd27);
reg myevent_done;
reg hickup_ready;
reg hickup_done;
localparam STATE_ZERO = 0;
localparam STATE_ONE = 1;
localparam STATE_TWO = 2;
reg [1:0] state = STATE_ZERO;
reg state_start_myevent = 1'b0;
reg state_start_hickup = 1'b0;
reg myevent_pending = 1'b0;
always @ (posedge clk) begin
state <= state;
myevent_pending <= myevent_pending || myevent;
state_start_myevent <= 1'b0;
state_start_hickup <= 1'b0;
case (state)
STATE_ZERO:
if (myevent_pending) begin
state <= STATE_ONE;
myevent_pending <= 1'b0;
state_start_myevent <= 1'b1;
end else if (hickup_ready) begin
state <= STATE_TWO;
state_start_hickup <= 1'b1;
end
STATE_ONE:
if (myevent_done)
state <= STATE_ZERO;
STATE_TWO:
if (hickup_done)
state <= STATE_ZERO;
default:
; /* do nothing */
endcase
end
reg [3:0] myevent_count = 0;
always @ (posedge clk)
if (state_start_myevent)
myevent_count <= 9;
else if (myevent_count > 0)
myevent_count <= myevent_count - 1;
initial myevent_done = 1'b0;
always @ (posedge clk)
myevent_done <= (myevent_count == 0);
reg [4:0] hickup_backlog = 2;
always @ (posedge clk)
if (state_start_myevent)
hickup_backlog <= hickup_backlog - 1;
else if (state_start_hickup)
hickup_backlog <= hickup_backlog + 1;
initial hickup_ready = 1'b1;
always @ (posedge clk)
hickup_ready <= (hickup_backlog < 3);
reg [3:0] hickup_count = 0;
always @ (posedge clk)
if (state_start_hickup)
hickup_count <= 10;
else if (hickup_count > 0)
hickup_count <= hickup_count - 1;
initial hickup_done = 1'b0;
always @ (posedge clk)
hickup_done <= (hickup_count == 1);
endmodule
|
module outputs)
wire myevent; // From test of Test.v
wire myevent_pending; // From test of Test.v
wire [1:0] state; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.state (state[1:0]),
.myevent (myevent),
.myevent_pending (myevent_pending),
// Inputs
.clk (clk),
.reset (reset));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, myevent_pending,myevent,state};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x me=%0x mep=%x\n",$time, cyc, crc, result, myevent, myevent_pending);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
reset <= (cyc<2);
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4e93a74bd97b25ef
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module Test (/*AUTOARG*/
// Outputs
state, myevent, myevent_pending,
// Inputs
clk, reset
);
input clk;
input reset;
output [1:0] state;
output myevent;
output myevent_pending;
reg [5:0] count = 0;
always @ (posedge clk)
if (reset) count <= 0;
else count <= count + 1;
reg myevent = 1'b0;
always @ (posedge clk)
myevent <= (count == 6'd27);
reg myevent_done;
reg hickup_ready;
reg hickup_done;
localparam STATE_ZERO = 0;
localparam STATE_ONE = 1;
localparam STATE_TWO = 2;
reg [1:0] state = STATE_ZERO;
reg state_start_myevent = 1'b0;
reg state_start_hickup = 1'b0;
reg myevent_pending = 1'b0;
always @ (posedge clk) begin
state <= state;
myevent_pending <= myevent_pending || myevent;
state_start_myevent <= 1'b0;
state_start_hickup <= 1'b0;
case (state)
STATE_ZERO:
if (myevent_pending) begin
state <= STATE_ONE;
myevent_pending <= 1'b0;
state_start_myevent <= 1'b1;
end else if (hickup_ready) begin
state <= STATE_TWO;
state_start_hickup <= 1'b1;
end
STATE_ONE:
if (myevent_done)
state <= STATE_ZERO;
STATE_TWO:
if (hickup_done)
state <= STATE_ZERO;
default:
; /* do nothing */
endcase
end
reg [3:0] myevent_count = 0;
always @ (posedge clk)
if (state_start_myevent)
myevent_count <= 9;
else if (myevent_count > 0)
myevent_count <= myevent_count - 1;
initial myevent_done = 1'b0;
always @ (posedge clk)
myevent_done <= (myevent_count == 0);
reg [4:0] hickup_backlog = 2;
always @ (posedge clk)
if (state_start_myevent)
hickup_backlog <= hickup_backlog - 1;
else if (state_start_hickup)
hickup_backlog <= hickup_backlog + 1;
initial hickup_ready = 1'b1;
always @ (posedge clk)
hickup_ready <= (hickup_backlog < 3);
reg [3:0] hickup_count = 0;
always @ (posedge clk)
if (state_start_hickup)
hickup_count <= 10;
else if (hickup_count > 0)
hickup_count <= hickup_count - 1;
initial hickup_done = 1'b0;
always @ (posedge clk)
hickup_done <= (hickup_count == 1);
endmodule
|
module outputs)
wire myevent; // From test of Test.v
wire myevent_pending; // From test of Test.v
wire [1:0] state; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.state (state[1:0]),
.myevent (myevent),
.myevent_pending (myevent_pending),
// Inputs
.clk (clk),
.reset (reset));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, myevent_pending,myevent,state};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x me=%0x mep=%x\n",$time, cyc, crc, result, myevent, myevent_pending);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
reset <= (cyc<2);
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4e93a74bd97b25ef
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module Test (/*AUTOARG*/
// Outputs
state, myevent, myevent_pending,
// Inputs
clk, reset
);
input clk;
input reset;
output [1:0] state;
output myevent;
output myevent_pending;
reg [5:0] count = 0;
always @ (posedge clk)
if (reset) count <= 0;
else count <= count + 1;
reg myevent = 1'b0;
always @ (posedge clk)
myevent <= (count == 6'd27);
reg myevent_done;
reg hickup_ready;
reg hickup_done;
localparam STATE_ZERO = 0;
localparam STATE_ONE = 1;
localparam STATE_TWO = 2;
reg [1:0] state = STATE_ZERO;
reg state_start_myevent = 1'b0;
reg state_start_hickup = 1'b0;
reg myevent_pending = 1'b0;
always @ (posedge clk) begin
state <= state;
myevent_pending <= myevent_pending || myevent;
state_start_myevent <= 1'b0;
state_start_hickup <= 1'b0;
case (state)
STATE_ZERO:
if (myevent_pending) begin
state <= STATE_ONE;
myevent_pending <= 1'b0;
state_start_myevent <= 1'b1;
end else if (hickup_ready) begin
state <= STATE_TWO;
state_start_hickup <= 1'b1;
end
STATE_ONE:
if (myevent_done)
state <= STATE_ZERO;
STATE_TWO:
if (hickup_done)
state <= STATE_ZERO;
default:
; /* do nothing */
endcase
end
reg [3:0] myevent_count = 0;
always @ (posedge clk)
if (state_start_myevent)
myevent_count <= 9;
else if (myevent_count > 0)
myevent_count <= myevent_count - 1;
initial myevent_done = 1'b0;
always @ (posedge clk)
myevent_done <= (myevent_count == 0);
reg [4:0] hickup_backlog = 2;
always @ (posedge clk)
if (state_start_myevent)
hickup_backlog <= hickup_backlog - 1;
else if (state_start_hickup)
hickup_backlog <= hickup_backlog + 1;
initial hickup_ready = 1'b1;
always @ (posedge clk)
hickup_ready <= (hickup_backlog < 3);
reg [3:0] hickup_count = 0;
always @ (posedge clk)
if (state_start_hickup)
hickup_count <= 10;
else if (hickup_count > 0)
hickup_count <= hickup_count - 1;
initial hickup_done = 1'b0;
always @ (posedge clk)
hickup_done <= (hickup_count == 1);
endmodule
|
module t (
clk
);
input clk;
integer cyc=0;
reg [63:0] crc; initial crc = 64'h1;
chk chk (.clk (clk),
.rst_l (1'b1),
.expr (|crc)
);
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module chk (input clk, input rst_l, input expr);
integer errors; initial errors = 0;
task printerr;
input [8*64:1] msg;
begin
errors = errors + 1;
$write("%%Error: %0s\n", msg);
$stop;
end
endtask
always @(posedge clk) begin
if (rst_l) begin
if (expr == 1'b0) begin
printerr("expr not asserted");
end
end
end
wire noxs = ((expr ^ expr) == 1'b0);
reg hasx;
always @ (noxs) begin
if (noxs) begin
hasx = 1'b0;
end
else begin
hasx = 1'b1;
end
end
always @(posedge clk) begin
if (rst_l) begin
if (hasx) begin
printerr("expr has unknowns");
end
end
end
endmodule
|
module t(data_i, data_o, single);
parameter op_bits = 32;
input [op_bits -1:0] data_i;
output [31:0] data_o;
input single;
//simplistic example, should choose 1st conditional generate and assign straight through
//the tool also compiles the special case and determines an error (replication value is 0
generate
if (op_bits == 32) begin : general_case
assign data_o = data_i;
// Test implicit signals
/* verilator lint_off IMPLICIT */
assign imp = single;
/* verilator lint_on IMPLICIT */
end
else begin : special_case
assign data_o = {{(32 -op_bits){1'b0}},data_i};
/* verilator lint_off IMPLICIT */
assign imp = single;
/* verilator lint_on IMPLICIT */
end
endgenerate
endmodule
|
module t(data_i, data_o, single);
parameter op_bits = 32;
input [op_bits -1:0] data_i;
output [31:0] data_o;
input single;
//simplistic example, should choose 1st conditional generate and assign straight through
//the tool also compiles the special case and determines an error (replication value is 0
generate
if (op_bits == 32) begin : general_case
assign data_o = data_i;
// Test implicit signals
/* verilator lint_off IMPLICIT */
assign imp = single;
/* verilator lint_on IMPLICIT */
end
else begin : special_case
assign data_o = {{(32 -op_bits){1'b0}},data_i};
/* verilator lint_off IMPLICIT */
assign imp = single;
/* verilator lint_on IMPLICIT */
end
endgenerate
endmodule
|
module outputs)
wire [71:0] muxed; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {muxed[63:0]};
wire [5:0] width_check = cyc[5:0] + 1;
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h20050a66e7b253d1
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module Test (/*AUTOARG*/
// Outputs
muxed,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [71:0] muxed;
wire [71:0] a = {in[7:0],~in[31:0],in[31:0]};
wire [71:0] b = {~in[7:0],in[31:0],~in[31:0]};
/*AUTOWIRE*/
Muxer muxer (
.sa (0),
.sb (in[0]),
/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.a (a[71:0]),
.b (b[71:0]));
endmodule
|
module Muxer (/*AUTOARG*/
// Outputs
muxed,
// Inputs
sa, sb, a, b
);
input sa;
input sb;
output wire [71:0] muxed;
input [71:0] a;
input [71:0] b;
// Constification wasn't sizing with inlining and gave
// unsized error on below
// v
assign muxed = (({72{sa}} & a)
| ({72{sb}} & b));
endmodule
|
module outputs)
wire [1:0] count; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.count (count[1:0]),
// Inputs
.clkvec (clkvec[1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, count};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
initial count[igen] = 1'b0;
always @ (posedge clkvec[igen])
count[igen] <= count[igen] + 1;
end
endgenerate
always @ (count) begin
$write("hi\n");
end
endmodule
|
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
// Unsupported: Count is multidriven, though if we did better analysis it wouldn't
// need to be.
initial count[igen] = 1'b0;
always @ (posedge clk_tmp)
count[igen] <= count[igen] + 1;
end
endgenerate
endmodule
|
module Test
(
input wire [1:0] clkvec,
output wire [1:0] count
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
reg tmp_count = 1'b0;
always @ (posedge clk_tmp) begin
tmp_count <= tmp_count + 1;
end
assign count[igen] = tmp_count;
end
endgenerate
endmodule
|
module outputs)
wire [1:0] count; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.count (count[1:0]),
// Inputs
.clkvec (clkvec[1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, count};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
initial count[igen] = 1'b0;
always @ (posedge clkvec[igen])
count[igen] <= count[igen] + 1;
end
endgenerate
always @ (count) begin
$write("hi\n");
end
endmodule
|
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
// Unsupported: Count is multidriven, though if we did better analysis it wouldn't
// need to be.
initial count[igen] = 1'b0;
always @ (posedge clk_tmp)
count[igen] <= count[igen] + 1;
end
endgenerate
endmodule
|
module Test
(
input wire [1:0] clkvec,
output wire [1:0] count
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
reg tmp_count = 1'b0;
always @ (posedge clk_tmp) begin
tmp_count <= tmp_count + 1;
end
assign count[igen] = tmp_count;
end
endgenerate
endmodule
|
module outputs)
wire [1:0] count; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.count (count[1:0]),
// Inputs
.clkvec (clkvec[1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, count};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
initial count[igen] = 1'b0;
always @ (posedge clkvec[igen])
count[igen] <= count[igen] + 1;
end
endgenerate
always @ (count) begin
$write("hi\n");
end
endmodule
|
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
// Unsupported: Count is multidriven, though if we did better analysis it wouldn't
// need to be.
initial count[igen] = 1'b0;
always @ (posedge clk_tmp)
count[igen] <= count[igen] + 1;
end
endgenerate
endmodule
|
module Test
(
input wire [1:0] clkvec,
output wire [1:0] count
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
reg tmp_count = 1'b0;
always @ (posedge clk_tmp) begin
tmp_count <= tmp_count + 1;
end
assign count[igen] = tmp_count;
end
endgenerate
endmodule
|
module outputs)
wire [1:0] count; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.count (count[1:0]),
// Inputs
.clkvec (clkvec[1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, count};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
initial count[igen] = 1'b0;
always @ (posedge clkvec[igen])
count[igen] <= count[igen] + 1;
end
endgenerate
always @ (count) begin
$write("hi\n");
end
endmodule
|
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
// Unsupported: Count is multidriven, though if we did better analysis it wouldn't
// need to be.
initial count[igen] = 1'b0;
always @ (posedge clk_tmp)
count[igen] <= count[igen] + 1;
end
endgenerate
endmodule
|
module Test
(
input wire [1:0] clkvec,
output wire [1:0] count
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
reg tmp_count = 1'b0;
always @ (posedge clk_tmp) begin
tmp_count <= tmp_count + 1;
end
assign count[igen] = tmp_count;
end
endgenerate
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
/*verilator public_module*/
input clk;
// No verilator_public needed, because it's outside the "" in the $c statement
reg [7:0] cyc; initial cyc=0;
reg c_worked;
reg [8:0] c_wider;
wire one = 1'b1;
always @ (posedge clk) begin
cyc <= cyc+8'd1;
// coverage testing
if (one) begin end
if (!one) begin end
if (cyc[0]) begin end if (!cyc[0]) begin end // multiple on a line
if (cyc == 8'd1) begin
c_worked <= 0;
end
if (cyc == 8'd2) begin
`ifdef VERILATOR
$c("VL_PRINTF(\"Calling $c, calling $c...\\n\");");
$c("VL_PRINTF(\"Cyc=%d\\n\",",cyc,");");
c_worked <= $c("my_function()");
c_wider <= $c9("0x10");
`else
c_worked <= 1'b1;
c_wider <= 9'h10;
`endif
end
if (cyc == 8'd3) begin
if (c_worked !== 1'b1) $stop;
if (c_wider !== 9'h10) $stop;
$finish;
end
end
`ifdef verilator
`systemc_header
#define DID_INT_HEADER 1
`systemc_interface
#ifndef DID_INT_HEADER
#error "`systemc_header didn't work"
#endif
bool m_did_ctor;
vluint32_t my_function() {
if (!m_did_ctor) vl_fatal(__FILE__,__LINE__,__FILE__,"`systemc_ctor didn't work");
return 1;
}
`systemc_imp_header
#define DID_IMP_HEADER 1
`systemc_implementation
#ifndef DID_IMP_HEADER
#error "`systemc_imp_header didn't work"
#endif
`systemc_ctor
m_did_ctor = 1;
`systemc_dtor
printf("In systemc_dtor\n");
printf("*-* All Finished *-*\n");
`verilog
// Test verilator comment after a endif
`endif // verilator
endmodule
|
module's undeclared outputs)
reg [9:0] outa;
reg [1:0] outb;
reg outc;
// End of automatics
// =============================
// Created from perl
// for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); };
always @(/*AS*/index) begin
case (index)
8'h00: begin outa = 10'h152; outb = 2'b00; outc = 1'b1; end
8'h01: begin outa = 10'h318; outb = 2'b11; outc = 1'b1; end
8'h02: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end
8'h03: begin outa = 10'h392; outb = 2'b01; outc = 1'b1; end
8'h04: begin outa = 10'h1ef; outb = 2'b00; outc = 1'b0; end
8'h05: begin outa = 10'h06c; outb = 2'b10; outc = 1'b1; end
8'h06: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end
8'h07: begin outa = 10'h29a; outb = 2'b10; outc = 1'b0; end
8'h08: begin outa = 10'h3ce; outb = 2'b01; outc = 1'b0; end
8'h09: begin outa = 10'h37c; outb = 2'b01; outc = 1'b0; end
8'h0a: begin outa = 10'h058; outb = 2'b10; outc = 1'b0; end
8'h0b: begin outa = 10'h3b2; outb = 2'b01; outc = 1'b1; end
8'h0c: begin outa = 10'h36f; outb = 2'b11; outc = 1'b0; end
8'h0d: begin outa = 10'h2c5; outb = 2'b11; outc = 1'b0; end
8'h0e: begin outa = 10'h23a; outb = 2'b00; outc = 1'b0; end
8'h0f: begin outa = 10'h222; outb = 2'b01; outc = 1'b1; end
8'h10: begin outa = 10'h328; outb = 2'b00; outc = 1'b1; end
8'h11: begin outa = 10'h3c3; outb = 2'b00; outc = 1'b1; end
8'h12: begin outa = 10'h12c; outb = 2'b01; outc = 1'b0; end
8'h13: begin outa = 10'h1d0; outb = 2'b00; outc = 1'b1; end
8'h14: begin outa = 10'h3ff; outb = 2'b01; outc = 1'b1; end
8'h15: begin outa = 10'h115; outb = 2'b11; outc = 1'b1; end
8'h16: begin outa = 10'h3ba; outb = 2'b10; outc = 1'b0; end
8'h17: begin outa = 10'h3ba; outb = 2'b00; outc = 1'b0; end
8'h18: begin outa = 10'h10d; outb = 2'b00; outc = 1'b1; end
8'h19: begin outa = 10'h13b; outb = 2'b01; outc = 1'b1; end
8'h1a: begin outa = 10'h0a0; outb = 2'b10; outc = 1'b1; end
8'h1b: begin outa = 10'h264; outb = 2'b11; outc = 1'b0; end
8'h1c: begin outa = 10'h3a2; outb = 2'b10; outc = 1'b0; end
8'h1d: begin outa = 10'h07c; outb = 2'b00; outc = 1'b1; end
8'h1e: begin outa = 10'h291; outb = 2'b00; outc = 1'b0; end
8'h1f: begin outa = 10'h1d1; outb = 2'b10; outc = 1'b0; end
8'h20: begin outa = 10'h354; outb = 2'b11; outc = 1'b1; end
8'h21: begin outa = 10'h0c0; outb = 2'b00; outc = 1'b1; end
8'h22: begin outa = 10'h191; outb = 2'b00; outc = 1'b0; end
8'h23: begin outa = 10'h379; outb = 2'b01; outc = 1'b0; end
8'h24: begin outa = 10'h073; outb = 2'b00; outc = 1'b0; end
8'h25: begin outa = 10'h2fd; outb = 2'b11; outc = 1'b1; end
8'h26: begin outa = 10'h2e0; outb = 2'b11; outc = 1'b1; end
8'h27: begin outa = 10'h337; outb = 2'b01; outc = 1'b1; end
8'h28: begin outa = 10'h2c7; outb = 2'b11; outc = 1'b1; end
8'h29: begin outa = 10'h19e; outb = 2'b11; outc = 1'b0; end
8'h2a: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end
8'h2b: begin outa = 10'h06a; outb = 2'b01; outc = 1'b1; end
8'h2c: begin outa = 10'h1c7; outb = 2'b01; outc = 1'b1; end
8'h2d: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end
8'h2e: begin outa = 10'h0cf; outb = 2'b01; outc = 1'b1; end
8'h2f: begin outa = 10'h009; outb = 2'b11; outc = 1'b1; end
8'h30: begin outa = 10'h09d; outb = 2'b00; outc = 1'b1; end
8'h31: begin outa = 10'h28e; outb = 2'b00; outc = 1'b0; end
8'h32: begin outa = 10'h010; outb = 2'b01; outc = 1'b0; end
8'h33: begin outa = 10'h1e0; outb = 2'b10; outc = 1'b0; end
8'h34: begin outa = 10'h079; outb = 2'b01; outc = 1'b1; end
8'h35: begin outa = 10'h13e; outb = 2'b10; outc = 1'b1; end
8'h36: begin outa = 10'h282; outb = 2'b11; outc = 1'b0; end
8'h37: begin outa = 10'h21c; outb = 2'b11; outc = 1'b1; end
8'h38: begin outa = 10'h148; outb = 2'b00; outc = 1'b1; end
8'h39: begin outa = 10'h3c0; outb = 2'b10; outc = 1'b0; end
8'h3a: begin outa = 10'h176; outb = 2'b01; outc = 1'b1; end
8'h3b: begin outa = 10'h3fc; outb = 2'b10; outc = 1'b1; end
8'h3c: begin outa = 10'h295; outb = 2'b11; outc = 1'b1; end
8'h3d: begin outa = 10'h113; outb = 2'b10; outc = 1'b1; end
8'h3e: begin outa = 10'h354; outb = 2'b01; outc = 1'b1; end
8'h3f: begin outa = 10'h0db; outb = 2'b11; outc = 1'b0; end
8'h40: begin outa = 10'h238; outb = 2'b01; outc = 1'b0; end
8'h41: begin outa = 10'h12b; outb = 2'b01; outc = 1'b1; end
8'h42: begin outa = 10'h1dc; outb = 2'b10; outc = 1'b0; end
8'h43: begin outa = 10'h137; outb = 2'b01; outc = 1'b1; end
8'h44: begin outa = 10'h1e2; outb = 2'b01; outc = 1'b1; end
8'h45: begin outa = 10'h3d5; outb = 2'b11; outc = 1'b1; end
8'h46: begin outa = 10'h30c; outb = 2'b11; outc = 1'b0; end
8'h47: begin outa = 10'h298; outb = 2'b11; outc = 1'b0; end
8'h48: begin outa = 10'h080; outb = 2'b00; outc = 1'b1; end
8'h49: begin outa = 10'h35a; outb = 2'b11; outc = 1'b1; end
8'h4a: begin outa = 10'h01b; outb = 2'b00; outc = 1'b0; end
8'h4b: begin outa = 10'h0a3; outb = 2'b11; outc = 1'b0; end
8'h4c: begin outa = 10'h0b3; outb = 2'b11; outc = 1'b1; end
8'h4d: begin outa = 10'h17a; outb = 2'b00; outc = 1'b0; end
8'h4e: begin outa = 10'h3ae; outb = 2'b11; outc = 1'b0; end
8'h4f: begin outa = 10'h078; outb = 2'b11; outc = 1'b0; end
8'h50: begin outa = 10'h322; outb = 2'b00; outc = 1'b1; end
8'h51: begin outa = 10'h213; outb = 2'b11; outc = 1'b0; end
8'h52: begin outa = 10'h11a; outb = 2'b11; outc = 1'b0; end
8'h53: begin outa = 10'h1a7; outb = 2'b00; outc = 1'b0; end
8'h54: begin outa = 10'h35a; outb = 2'b00; outc = 1'b1; end
8'h55: begin outa = 10'h233; outb = 2'b00; outc = 1'b0; end
8'h56: begin outa = 10'h01d; outb = 2'b01; outc = 1'b1; end
8'h57: begin outa = 10'h2d5; outb = 2'b00; outc = 1'b0; end
8'h58: begin outa = 10'h1a0; outb = 2'b00; outc = 1'b1; end
8'h59: begin outa = 10'h3d0; outb = 2'b00; outc = 1'b1; end
8'h5a: begin outa = 10'h181; outb = 2'b01; outc = 1'b1; end
8'h5b: begin outa = 10'h219; outb = 2'b01; outc = 1'b1; end
8'h5c: begin outa = 10'h26a; outb = 2'b01; outc = 1'b1; end
8'h5d: begin outa = 10'h050; outb = 2'b10; outc = 1'b0; end
8'h5e: begin outa = 10'h189; outb = 2'b10; outc = 1'b0; end
8'h5f: begin outa = 10'h1eb; outb = 2'b01; outc = 1'b1; end
8'h60: begin outa = 10'h224; outb = 2'b00; outc = 1'b1; end
8'h61: begin outa = 10'h2fe; outb = 2'b00; outc = 1'b0; end
8'h62: begin outa = 10'h0ae; outb = 2'b00; outc = 1'b1; end
8'h63: begin outa = 10'h1cd; outb = 2'b00; outc = 1'b0; end
8'h64: begin outa = 10'h273; outb = 2'b10; outc = 1'b1; end
8'h65: begin outa = 10'h268; outb = 2'b10; outc = 1'b0; end
8'h66: begin outa = 10'h111; outb = 2'b01; outc = 1'b0; end
8'h67: begin outa = 10'h1f9; outb = 2'b00; outc = 1'b0; end
8'h68: begin outa = 10'h232; outb = 2'b00; outc = 1'b1; end
8'h69: begin outa = 10'h255; outb = 2'b11; outc = 1'b0; end
8'h6a: begin outa = 10'h34c; outb = 2'b01; outc = 1'b1; end
8'h6b: begin outa = 10'h049; outb = 2'b01; outc = 1'b1; end
8'h6c: begin outa = 10'h197; outb = 2'b11; outc = 1'b0; end
8'h6d: begin outa = 10'h0fe; outb = 2'b11; outc = 1'b0; end
8'h6e: begin outa = 10'h253; outb = 2'b01; outc = 1'b1; end
8'h6f: begin outa = 10'h2de; outb = 2'b11; outc = 1'b0; end
8'h70: begin outa = 10'h13b; outb = 2'b10; outc = 1'b1; end
8'h71: begin outa = 10'h040; outb = 2'b10; outc = 1'b0; end
8'h72: begin outa = 10'h0b4; outb = 2'b00; outc = 1'b1; end
8'h73: begin outa = 10'h233; outb = 2'b11; outc = 1'b1; end
8'h74: begin outa = 10'h198; outb = 2'b00; outc = 1'b1; end
8'h75: begin outa = 10'h018; outb = 2'b00; outc = 1'b1; end
8'h76: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end
8'h77: begin outa = 10'h134; outb = 2'b11; outc = 1'b0; end
8'h78: begin outa = 10'h1ca; outb = 2'b10; outc = 1'b0; end
8'h79: begin outa = 10'h286; outb = 2'b10; outc = 1'b1; end
8'h7a: begin outa = 10'h0e6; outb = 2'b11; outc = 1'b1; end
8'h7b: begin outa = 10'h064; outb = 2'b10; outc = 1'b1; end
8'h7c: begin outa = 10'h257; outb = 2'b00; outc = 1'b1; end
8'h7d: begin outa = 10'h31a; outb = 2'b10; outc = 1'b1; end
8'h7e: begin outa = 10'h247; outb = 2'b01; outc = 1'b0; end
8'h7f: begin outa = 10'h299; outb = 2'b00; outc = 1'b0; end
8'h80: begin outa = 10'h02c; outb = 2'b00; outc = 1'b0; end
8'h81: begin outa = 10'h2bb; outb = 2'b11; outc = 1'b0; end
8'h82: begin outa = 10'h180; outb = 2'b10; outc = 1'b0; end
8'h83: begin outa = 10'h245; outb = 2'b01; outc = 1'b1; end
8'h84: begin outa = 10'h0da; outb = 2'b10; outc = 1'b0; end
8'h85: begin outa = 10'h367; outb = 2'b10; outc = 1'b0; end
8'h86: begin outa = 10'h304; outb = 2'b01; outc = 1'b0; end
8'h87: begin outa = 10'h38b; outb = 2'b11; outc = 1'b0; end
8'h88: begin outa = 10'h09f; outb = 2'b01; outc = 1'b0; end
8'h89: begin outa = 10'h1f0; outb = 2'b10; outc = 1'b1; end
8'h8a: begin outa = 10'h281; outb = 2'b10; outc = 1'b1; end
8'h8b: begin outa = 10'h019; outb = 2'b00; outc = 1'b0; end
8'h8c: begin outa = 10'h1f2; outb = 2'b10; outc = 1'b0; end
8'h8d: begin outa = 10'h0b1; outb = 2'b01; outc = 1'b1; end
8'h8e: begin outa = 10'h058; outb = 2'b01; outc = 1'b1; end
8'h8f: begin outa = 10'h39b; outb = 2'b00; outc = 1'b1; end
8'h90: begin outa = 10'h2ec; outb = 2'b10; outc = 1'b1; end
8'h91: begin outa = 10'h250; outb = 2'b00; outc = 1'b1; end
8'h92: begin outa = 10'h3f4; outb = 2'b10; outc = 1'b1; end
8'h93: begin outa = 10'h057; outb = 2'b10; outc = 1'b1; end
8'h94: begin outa = 10'h18f; outb = 2'b01; outc = 1'b1; end
8'h95: begin outa = 10'h105; outb = 2'b01; outc = 1'b1; end
8'h96: begin outa = 10'h1ae; outb = 2'b00; outc = 1'b1; end
8'h97: begin outa = 10'h04e; outb = 2'b10; outc = 1'b0; end
8'h98: begin outa = 10'h240; outb = 2'b11; outc = 1'b0; end
8'h99: begin outa = 10'h3e4; outb = 2'b01; outc = 1'b0; end
8'h9a: begin outa = 10'h3c6; outb = 2'b01; outc = 1'b0; end
8'h9b: begin outa = 10'h109; outb = 2'b00; outc = 1'b1; end
8'h9c: begin outa = 10'h073; outb = 2'b10; outc = 1'b1; end
8'h9d: begin outa = 10'h19f; outb = 2'b01; outc = 1'b0; end
8'h9e: begin outa = 10'h3b8; outb = 2'b01; outc = 1'b0; end
8'h9f: begin outa = 10'h00e; outb = 2'b00; outc = 1'b1; end
8'ha0: begin outa = 10'h1b3; outb = 2'b11; outc = 1'b1; end
8'ha1: begin outa = 10'h2bd; outb = 2'b11; outc = 1'b0; end
8'ha2: begin outa = 10'h324; outb = 2'b00; outc = 1'b1; end
8'ha3: begin outa = 10'h343; outb = 2'b10; outc = 1'b0; end
8'ha4: begin outa = 10'h1c9; outb = 2'b01; outc = 1'b0; end
8'ha5: begin outa = 10'h185; outb = 2'b00; outc = 1'b1; end
8'ha6: begin outa = 10'h37a; outb = 2'b00; outc = 1'b1; end
8'ha7: begin outa = 10'h0e0; outb = 2'b01; outc = 1'b1; end
8'ha8: begin outa = 10'h0a3; outb = 2'b10; outc = 1'b0; end
8'ha9: begin outa = 10'h019; outb = 2'b11; outc = 1'b0; end
8'haa: begin outa = 10'h099; outb = 2'b00; outc = 1'b1; end
8'hab: begin outa = 10'h376; outb = 2'b01; outc = 1'b1; end
8'hac: begin outa = 10'h077; outb = 2'b00; outc = 1'b1; end
8'had: begin outa = 10'h2b1; outb = 2'b11; outc = 1'b1; end
8'hae: begin outa = 10'h27f; outb = 2'b00; outc = 1'b0; end
8'haf: begin outa = 10'h265; outb = 2'b11; outc = 1'b0; end
8'hb0: begin outa = 10'h156; outb = 2'b10; outc = 1'b1; end
8'hb1: begin outa = 10'h1ce; outb = 2'b00; outc = 1'b0; end
8'hb2: begin outa = 10'h008; outb = 2'b01; outc = 1'b0; end
8'hb3: begin outa = 10'h12e; outb = 2'b11; outc = 1'b1; end
8'hb4: begin outa = 10'h199; outb = 2'b11; outc = 1'b0; end
8'hb5: begin outa = 10'h330; outb = 2'b10; outc = 1'b0; end
8'hb6: begin outa = 10'h1ab; outb = 2'b01; outc = 1'b1; end
8'hb7: begin outa = 10'h3bd; outb = 2'b00; outc = 1'b0; end
8'hb8: begin outa = 10'h0ca; outb = 2'b10; outc = 1'b0; end
8'hb9: begin outa = 10'h367; outb = 2'b00; outc = 1'b0; end
8'hba: begin outa = 10'h334; outb = 2'b00; outc = 1'b0; end
8'hbb: begin outa = 10'h040; outb = 2'b00; outc = 1'b1; end
8'hbc: begin outa = 10'h1a7; outb = 2'b10; outc = 1'b1; end
8'hbd: begin outa = 10'h036; outb = 2'b11; outc = 1'b1; end
8'hbe: begin outa = 10'h223; outb = 2'b11; outc = 1'b1; end
8'hbf: begin outa = 10'h075; outb = 2'b01; outc = 1'b0; end
8'hc0: begin outa = 10'h3c4; outb = 2'b00; outc = 1'b1; end
8'hc1: begin outa = 10'h2cc; outb = 2'b01; outc = 1'b0; end
8'hc2: begin outa = 10'h123; outb = 2'b01; outc = 1'b0; end
8'hc3: begin outa = 10'h3fd; outb = 2'b01; outc = 1'b1; end
8'hc4: begin outa = 10'h11e; outb = 2'b00; outc = 1'b0; end
8'hc5: begin outa = 10'h27c; outb = 2'b11; outc = 1'b1; end
8'hc6: begin outa = 10'h1e2; outb = 2'b11; outc = 1'b0; end
8'hc7: begin outa = 10'h377; outb = 2'b11; outc = 1'b0; end
8'hc8: begin outa = 10'h33a; outb = 2'b11; outc = 1'b0; end
8'hc9: begin outa = 10'h32d; outb = 2'b11; outc = 1'b1; end
8'hca: begin outa = 10'h014; outb = 2'b11; outc = 1'b0; end
8'hcb: begin outa = 10'h332; outb = 2'b10; outc = 1'b0; end
8'hcc: begin outa = 10'h359; outb = 2'b00; outc = 1'b0; end
8'hcd: begin outa = 10'h0a4; outb = 2'b10; outc = 1'b1; end
8'hce: begin outa = 10'h348; outb = 2'b00; outc = 1'b1; end
8'hcf: begin outa = 10'h04b; outb = 2'b11; outc = 1'b1; end
8'hd0: begin outa = 10'h147; outb = 2'b10; outc = 1'b1; end
8'hd1: begin outa = 10'h026; outb = 2'b00; outc = 1'b1; end
8'hd2: begin outa = 10'h103; outb = 2'b00; outc = 1'b0; end
8'hd3: begin outa = 10'h106; outb = 2'b00; outc = 1'b1; end
8'hd4: begin outa = 10'h35a; outb = 2'b00; outc = 1'b0; end
8'hd5: begin outa = 10'h254; outb = 2'b01; outc = 1'b0; end
8'hd6: begin outa = 10'h0cd; outb = 2'b01; outc = 1'b0; end
8'hd7: begin outa = 10'h17c; outb = 2'b11; outc = 1'b1; end
8'hd8: begin outa = 10'h37e; outb = 2'b10; outc = 1'b1; end
8'hd9: begin outa = 10'h0a9; outb = 2'b11; outc = 1'b1; end
8'hda: begin outa = 10'h0fe; outb = 2'b01; outc = 1'b0; end
8'hdb: begin outa = 10'h3c0; outb = 2'b11; outc = 1'b1; end
8'hdc: begin outa = 10'h1d9; outb = 2'b10; outc = 1'b1; end
8'hdd: begin outa = 10'h10e; outb = 2'b00; outc = 1'b1; end
8'hde: begin outa = 10'h394; outb = 2'b01; outc = 1'b0; end
8'hdf: begin outa = 10'h316; outb = 2'b01; outc = 1'b0; end
8'he0: begin outa = 10'h05b; outb = 2'b11; outc = 1'b0; end
8'he1: begin outa = 10'h126; outb = 2'b01; outc = 1'b1; end
8'he2: begin outa = 10'h369; outb = 2'b11; outc = 1'b0; end
8'he3: begin outa = 10'h291; outb = 2'b10; outc = 1'b1; end
8'he4: begin outa = 10'h2ca; outb = 2'b00; outc = 1'b1; end
8'he5: begin outa = 10'h25b; outb = 2'b01; outc = 1'b1; end
8'he6: begin outa = 10'h106; outb = 2'b00; outc = 1'b0; end
8'he7: begin outa = 10'h172; outb = 2'b11; outc = 1'b1; end
8'he8: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end
8'he9: begin outa = 10'h2d3; outb = 2'b11; outc = 1'b1; end
8'hea: begin outa = 10'h182; outb = 2'b00; outc = 1'b0; end
8'heb: begin outa = 10'h327; outb = 2'b00; outc = 1'b1; end
8'hec: begin outa = 10'h1d0; outb = 2'b10; outc = 1'b0; end
8'hed: begin outa = 10'h204; outb = 2'b00; outc = 1'b1; end
8'hee: begin outa = 10'h11f; outb = 2'b00; outc = 1'b1; end
8'hef: begin outa = 10'h365; outb = 2'b11; outc = 1'b1; end
8'hf0: begin outa = 10'h2c2; outb = 2'b01; outc = 1'b1; end
8'hf1: begin outa = 10'h2b5; outb = 2'b10; outc = 1'b0; end
8'hf2: begin outa = 10'h1f8; outb = 2'b10; outc = 1'b1; end
8'hf3: begin outa = 10'h2a7; outb = 2'b01; outc = 1'b1; end
8'hf4: begin outa = 10'h1be; outb = 2'b10; outc = 1'b1; end
8'hf5: begin outa = 10'h25e; outb = 2'b10; outc = 1'b1; end
8'hf6: begin outa = 10'h032; outb = 2'b10; outc = 1'b0; end
8'hf7: begin outa = 10'h2ef; outb = 2'b00; outc = 1'b0; end
8'hf8: begin outa = 10'h02f; outb = 2'b00; outc = 1'b1; end
8'hf9: begin outa = 10'h201; outb = 2'b10; outc = 1'b0; end
8'hfa: begin outa = 10'h054; outb = 2'b01; outc = 1'b1; end
8'hfb: begin outa = 10'h013; outb = 2'b10; outc = 1'b0; end
8'hfc: begin outa = 10'h249; outb = 2'b01; outc = 1'b0; end
8'hfd: begin outa = 10'h09a; outb = 2'b10; outc = 1'b0; end
8'hfe: begin outa = 10'h012; outb = 2'b00; outc = 1'b0; end
8'hff: begin outa = 10'h114; outb = 2'b10; outc = 1'b1; end
endcase
end
endmodule
|
module's undeclared outputs)
reg [9:0] outa;
reg [1:0] outb;
reg outc;
// End of automatics
// =============================
// Created from perl
// for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); };
always @(/*AS*/index) begin
case (index)
8'h00: begin outa = 10'h152; outb = 2'b00; outc = 1'b1; end
8'h01: begin outa = 10'h318; outb = 2'b11; outc = 1'b1; end
8'h02: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end
8'h03: begin outa = 10'h392; outb = 2'b01; outc = 1'b1; end
8'h04: begin outa = 10'h1ef; outb = 2'b00; outc = 1'b0; end
8'h05: begin outa = 10'h06c; outb = 2'b10; outc = 1'b1; end
8'h06: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end
8'h07: begin outa = 10'h29a; outb = 2'b10; outc = 1'b0; end
8'h08: begin outa = 10'h3ce; outb = 2'b01; outc = 1'b0; end
8'h09: begin outa = 10'h37c; outb = 2'b01; outc = 1'b0; end
8'h0a: begin outa = 10'h058; outb = 2'b10; outc = 1'b0; end
8'h0b: begin outa = 10'h3b2; outb = 2'b01; outc = 1'b1; end
8'h0c: begin outa = 10'h36f; outb = 2'b11; outc = 1'b0; end
8'h0d: begin outa = 10'h2c5; outb = 2'b11; outc = 1'b0; end
8'h0e: begin outa = 10'h23a; outb = 2'b00; outc = 1'b0; end
8'h0f: begin outa = 10'h222; outb = 2'b01; outc = 1'b1; end
8'h10: begin outa = 10'h328; outb = 2'b00; outc = 1'b1; end
8'h11: begin outa = 10'h3c3; outb = 2'b00; outc = 1'b1; end
8'h12: begin outa = 10'h12c; outb = 2'b01; outc = 1'b0; end
8'h13: begin outa = 10'h1d0; outb = 2'b00; outc = 1'b1; end
8'h14: begin outa = 10'h3ff; outb = 2'b01; outc = 1'b1; end
8'h15: begin outa = 10'h115; outb = 2'b11; outc = 1'b1; end
8'h16: begin outa = 10'h3ba; outb = 2'b10; outc = 1'b0; end
8'h17: begin outa = 10'h3ba; outb = 2'b00; outc = 1'b0; end
8'h18: begin outa = 10'h10d; outb = 2'b00; outc = 1'b1; end
8'h19: begin outa = 10'h13b; outb = 2'b01; outc = 1'b1; end
8'h1a: begin outa = 10'h0a0; outb = 2'b10; outc = 1'b1; end
8'h1b: begin outa = 10'h264; outb = 2'b11; outc = 1'b0; end
8'h1c: begin outa = 10'h3a2; outb = 2'b10; outc = 1'b0; end
8'h1d: begin outa = 10'h07c; outb = 2'b00; outc = 1'b1; end
8'h1e: begin outa = 10'h291; outb = 2'b00; outc = 1'b0; end
8'h1f: begin outa = 10'h1d1; outb = 2'b10; outc = 1'b0; end
8'h20: begin outa = 10'h354; outb = 2'b11; outc = 1'b1; end
8'h21: begin outa = 10'h0c0; outb = 2'b00; outc = 1'b1; end
8'h22: begin outa = 10'h191; outb = 2'b00; outc = 1'b0; end
8'h23: begin outa = 10'h379; outb = 2'b01; outc = 1'b0; end
8'h24: begin outa = 10'h073; outb = 2'b00; outc = 1'b0; end
8'h25: begin outa = 10'h2fd; outb = 2'b11; outc = 1'b1; end
8'h26: begin outa = 10'h2e0; outb = 2'b11; outc = 1'b1; end
8'h27: begin outa = 10'h337; outb = 2'b01; outc = 1'b1; end
8'h28: begin outa = 10'h2c7; outb = 2'b11; outc = 1'b1; end
8'h29: begin outa = 10'h19e; outb = 2'b11; outc = 1'b0; end
8'h2a: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end
8'h2b: begin outa = 10'h06a; outb = 2'b01; outc = 1'b1; end
8'h2c: begin outa = 10'h1c7; outb = 2'b01; outc = 1'b1; end
8'h2d: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end
8'h2e: begin outa = 10'h0cf; outb = 2'b01; outc = 1'b1; end
8'h2f: begin outa = 10'h009; outb = 2'b11; outc = 1'b1; end
8'h30: begin outa = 10'h09d; outb = 2'b00; outc = 1'b1; end
8'h31: begin outa = 10'h28e; outb = 2'b00; outc = 1'b0; end
8'h32: begin outa = 10'h010; outb = 2'b01; outc = 1'b0; end
8'h33: begin outa = 10'h1e0; outb = 2'b10; outc = 1'b0; end
8'h34: begin outa = 10'h079; outb = 2'b01; outc = 1'b1; end
8'h35: begin outa = 10'h13e; outb = 2'b10; outc = 1'b1; end
8'h36: begin outa = 10'h282; outb = 2'b11; outc = 1'b0; end
8'h37: begin outa = 10'h21c; outb = 2'b11; outc = 1'b1; end
8'h38: begin outa = 10'h148; outb = 2'b00; outc = 1'b1; end
8'h39: begin outa = 10'h3c0; outb = 2'b10; outc = 1'b0; end
8'h3a: begin outa = 10'h176; outb = 2'b01; outc = 1'b1; end
8'h3b: begin outa = 10'h3fc; outb = 2'b10; outc = 1'b1; end
8'h3c: begin outa = 10'h295; outb = 2'b11; outc = 1'b1; end
8'h3d: begin outa = 10'h113; outb = 2'b10; outc = 1'b1; end
8'h3e: begin outa = 10'h354; outb = 2'b01; outc = 1'b1; end
8'h3f: begin outa = 10'h0db; outb = 2'b11; outc = 1'b0; end
8'h40: begin outa = 10'h238; outb = 2'b01; outc = 1'b0; end
8'h41: begin outa = 10'h12b; outb = 2'b01; outc = 1'b1; end
8'h42: begin outa = 10'h1dc; outb = 2'b10; outc = 1'b0; end
8'h43: begin outa = 10'h137; outb = 2'b01; outc = 1'b1; end
8'h44: begin outa = 10'h1e2; outb = 2'b01; outc = 1'b1; end
8'h45: begin outa = 10'h3d5; outb = 2'b11; outc = 1'b1; end
8'h46: begin outa = 10'h30c; outb = 2'b11; outc = 1'b0; end
8'h47: begin outa = 10'h298; outb = 2'b11; outc = 1'b0; end
8'h48: begin outa = 10'h080; outb = 2'b00; outc = 1'b1; end
8'h49: begin outa = 10'h35a; outb = 2'b11; outc = 1'b1; end
8'h4a: begin outa = 10'h01b; outb = 2'b00; outc = 1'b0; end
8'h4b: begin outa = 10'h0a3; outb = 2'b11; outc = 1'b0; end
8'h4c: begin outa = 10'h0b3; outb = 2'b11; outc = 1'b1; end
8'h4d: begin outa = 10'h17a; outb = 2'b00; outc = 1'b0; end
8'h4e: begin outa = 10'h3ae; outb = 2'b11; outc = 1'b0; end
8'h4f: begin outa = 10'h078; outb = 2'b11; outc = 1'b0; end
8'h50: begin outa = 10'h322; outb = 2'b00; outc = 1'b1; end
8'h51: begin outa = 10'h213; outb = 2'b11; outc = 1'b0; end
8'h52: begin outa = 10'h11a; outb = 2'b11; outc = 1'b0; end
8'h53: begin outa = 10'h1a7; outb = 2'b00; outc = 1'b0; end
8'h54: begin outa = 10'h35a; outb = 2'b00; outc = 1'b1; end
8'h55: begin outa = 10'h233; outb = 2'b00; outc = 1'b0; end
8'h56: begin outa = 10'h01d; outb = 2'b01; outc = 1'b1; end
8'h57: begin outa = 10'h2d5; outb = 2'b00; outc = 1'b0; end
8'h58: begin outa = 10'h1a0; outb = 2'b00; outc = 1'b1; end
8'h59: begin outa = 10'h3d0; outb = 2'b00; outc = 1'b1; end
8'h5a: begin outa = 10'h181; outb = 2'b01; outc = 1'b1; end
8'h5b: begin outa = 10'h219; outb = 2'b01; outc = 1'b1; end
8'h5c: begin outa = 10'h26a; outb = 2'b01; outc = 1'b1; end
8'h5d: begin outa = 10'h050; outb = 2'b10; outc = 1'b0; end
8'h5e: begin outa = 10'h189; outb = 2'b10; outc = 1'b0; end
8'h5f: begin outa = 10'h1eb; outb = 2'b01; outc = 1'b1; end
8'h60: begin outa = 10'h224; outb = 2'b00; outc = 1'b1; end
8'h61: begin outa = 10'h2fe; outb = 2'b00; outc = 1'b0; end
8'h62: begin outa = 10'h0ae; outb = 2'b00; outc = 1'b1; end
8'h63: begin outa = 10'h1cd; outb = 2'b00; outc = 1'b0; end
8'h64: begin outa = 10'h273; outb = 2'b10; outc = 1'b1; end
8'h65: begin outa = 10'h268; outb = 2'b10; outc = 1'b0; end
8'h66: begin outa = 10'h111; outb = 2'b01; outc = 1'b0; end
8'h67: begin outa = 10'h1f9; outb = 2'b00; outc = 1'b0; end
8'h68: begin outa = 10'h232; outb = 2'b00; outc = 1'b1; end
8'h69: begin outa = 10'h255; outb = 2'b11; outc = 1'b0; end
8'h6a: begin outa = 10'h34c; outb = 2'b01; outc = 1'b1; end
8'h6b: begin outa = 10'h049; outb = 2'b01; outc = 1'b1; end
8'h6c: begin outa = 10'h197; outb = 2'b11; outc = 1'b0; end
8'h6d: begin outa = 10'h0fe; outb = 2'b11; outc = 1'b0; end
8'h6e: begin outa = 10'h253; outb = 2'b01; outc = 1'b1; end
8'h6f: begin outa = 10'h2de; outb = 2'b11; outc = 1'b0; end
8'h70: begin outa = 10'h13b; outb = 2'b10; outc = 1'b1; end
8'h71: begin outa = 10'h040; outb = 2'b10; outc = 1'b0; end
8'h72: begin outa = 10'h0b4; outb = 2'b00; outc = 1'b1; end
8'h73: begin outa = 10'h233; outb = 2'b11; outc = 1'b1; end
8'h74: begin outa = 10'h198; outb = 2'b00; outc = 1'b1; end
8'h75: begin outa = 10'h018; outb = 2'b00; outc = 1'b1; end
8'h76: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end
8'h77: begin outa = 10'h134; outb = 2'b11; outc = 1'b0; end
8'h78: begin outa = 10'h1ca; outb = 2'b10; outc = 1'b0; end
8'h79: begin outa = 10'h286; outb = 2'b10; outc = 1'b1; end
8'h7a: begin outa = 10'h0e6; outb = 2'b11; outc = 1'b1; end
8'h7b: begin outa = 10'h064; outb = 2'b10; outc = 1'b1; end
8'h7c: begin outa = 10'h257; outb = 2'b00; outc = 1'b1; end
8'h7d: begin outa = 10'h31a; outb = 2'b10; outc = 1'b1; end
8'h7e: begin outa = 10'h247; outb = 2'b01; outc = 1'b0; end
8'h7f: begin outa = 10'h299; outb = 2'b00; outc = 1'b0; end
8'h80: begin outa = 10'h02c; outb = 2'b00; outc = 1'b0; end
8'h81: begin outa = 10'h2bb; outb = 2'b11; outc = 1'b0; end
8'h82: begin outa = 10'h180; outb = 2'b10; outc = 1'b0; end
8'h83: begin outa = 10'h245; outb = 2'b01; outc = 1'b1; end
8'h84: begin outa = 10'h0da; outb = 2'b10; outc = 1'b0; end
8'h85: begin outa = 10'h367; outb = 2'b10; outc = 1'b0; end
8'h86: begin outa = 10'h304; outb = 2'b01; outc = 1'b0; end
8'h87: begin outa = 10'h38b; outb = 2'b11; outc = 1'b0; end
8'h88: begin outa = 10'h09f; outb = 2'b01; outc = 1'b0; end
8'h89: begin outa = 10'h1f0; outb = 2'b10; outc = 1'b1; end
8'h8a: begin outa = 10'h281; outb = 2'b10; outc = 1'b1; end
8'h8b: begin outa = 10'h019; outb = 2'b00; outc = 1'b0; end
8'h8c: begin outa = 10'h1f2; outb = 2'b10; outc = 1'b0; end
8'h8d: begin outa = 10'h0b1; outb = 2'b01; outc = 1'b1; end
8'h8e: begin outa = 10'h058; outb = 2'b01; outc = 1'b1; end
8'h8f: begin outa = 10'h39b; outb = 2'b00; outc = 1'b1; end
8'h90: begin outa = 10'h2ec; outb = 2'b10; outc = 1'b1; end
8'h91: begin outa = 10'h250; outb = 2'b00; outc = 1'b1; end
8'h92: begin outa = 10'h3f4; outb = 2'b10; outc = 1'b1; end
8'h93: begin outa = 10'h057; outb = 2'b10; outc = 1'b1; end
8'h94: begin outa = 10'h18f; outb = 2'b01; outc = 1'b1; end
8'h95: begin outa = 10'h105; outb = 2'b01; outc = 1'b1; end
8'h96: begin outa = 10'h1ae; outb = 2'b00; outc = 1'b1; end
8'h97: begin outa = 10'h04e; outb = 2'b10; outc = 1'b0; end
8'h98: begin outa = 10'h240; outb = 2'b11; outc = 1'b0; end
8'h99: begin outa = 10'h3e4; outb = 2'b01; outc = 1'b0; end
8'h9a: begin outa = 10'h3c6; outb = 2'b01; outc = 1'b0; end
8'h9b: begin outa = 10'h109; outb = 2'b00; outc = 1'b1; end
8'h9c: begin outa = 10'h073; outb = 2'b10; outc = 1'b1; end
8'h9d: begin outa = 10'h19f; outb = 2'b01; outc = 1'b0; end
8'h9e: begin outa = 10'h3b8; outb = 2'b01; outc = 1'b0; end
8'h9f: begin outa = 10'h00e; outb = 2'b00; outc = 1'b1; end
8'ha0: begin outa = 10'h1b3; outb = 2'b11; outc = 1'b1; end
8'ha1: begin outa = 10'h2bd; outb = 2'b11; outc = 1'b0; end
8'ha2: begin outa = 10'h324; outb = 2'b00; outc = 1'b1; end
8'ha3: begin outa = 10'h343; outb = 2'b10; outc = 1'b0; end
8'ha4: begin outa = 10'h1c9; outb = 2'b01; outc = 1'b0; end
8'ha5: begin outa = 10'h185; outb = 2'b00; outc = 1'b1; end
8'ha6: begin outa = 10'h37a; outb = 2'b00; outc = 1'b1; end
8'ha7: begin outa = 10'h0e0; outb = 2'b01; outc = 1'b1; end
8'ha8: begin outa = 10'h0a3; outb = 2'b10; outc = 1'b0; end
8'ha9: begin outa = 10'h019; outb = 2'b11; outc = 1'b0; end
8'haa: begin outa = 10'h099; outb = 2'b00; outc = 1'b1; end
8'hab: begin outa = 10'h376; outb = 2'b01; outc = 1'b1; end
8'hac: begin outa = 10'h077; outb = 2'b00; outc = 1'b1; end
8'had: begin outa = 10'h2b1; outb = 2'b11; outc = 1'b1; end
8'hae: begin outa = 10'h27f; outb = 2'b00; outc = 1'b0; end
8'haf: begin outa = 10'h265; outb = 2'b11; outc = 1'b0; end
8'hb0: begin outa = 10'h156; outb = 2'b10; outc = 1'b1; end
8'hb1: begin outa = 10'h1ce; outb = 2'b00; outc = 1'b0; end
8'hb2: begin outa = 10'h008; outb = 2'b01; outc = 1'b0; end
8'hb3: begin outa = 10'h12e; outb = 2'b11; outc = 1'b1; end
8'hb4: begin outa = 10'h199; outb = 2'b11; outc = 1'b0; end
8'hb5: begin outa = 10'h330; outb = 2'b10; outc = 1'b0; end
8'hb6: begin outa = 10'h1ab; outb = 2'b01; outc = 1'b1; end
8'hb7: begin outa = 10'h3bd; outb = 2'b00; outc = 1'b0; end
8'hb8: begin outa = 10'h0ca; outb = 2'b10; outc = 1'b0; end
8'hb9: begin outa = 10'h367; outb = 2'b00; outc = 1'b0; end
8'hba: begin outa = 10'h334; outb = 2'b00; outc = 1'b0; end
8'hbb: begin outa = 10'h040; outb = 2'b00; outc = 1'b1; end
8'hbc: begin outa = 10'h1a7; outb = 2'b10; outc = 1'b1; end
8'hbd: begin outa = 10'h036; outb = 2'b11; outc = 1'b1; end
8'hbe: begin outa = 10'h223; outb = 2'b11; outc = 1'b1; end
8'hbf: begin outa = 10'h075; outb = 2'b01; outc = 1'b0; end
8'hc0: begin outa = 10'h3c4; outb = 2'b00; outc = 1'b1; end
8'hc1: begin outa = 10'h2cc; outb = 2'b01; outc = 1'b0; end
8'hc2: begin outa = 10'h123; outb = 2'b01; outc = 1'b0; end
8'hc3: begin outa = 10'h3fd; outb = 2'b01; outc = 1'b1; end
8'hc4: begin outa = 10'h11e; outb = 2'b00; outc = 1'b0; end
8'hc5: begin outa = 10'h27c; outb = 2'b11; outc = 1'b1; end
8'hc6: begin outa = 10'h1e2; outb = 2'b11; outc = 1'b0; end
8'hc7: begin outa = 10'h377; outb = 2'b11; outc = 1'b0; end
8'hc8: begin outa = 10'h33a; outb = 2'b11; outc = 1'b0; end
8'hc9: begin outa = 10'h32d; outb = 2'b11; outc = 1'b1; end
8'hca: begin outa = 10'h014; outb = 2'b11; outc = 1'b0; end
8'hcb: begin outa = 10'h332; outb = 2'b10; outc = 1'b0; end
8'hcc: begin outa = 10'h359; outb = 2'b00; outc = 1'b0; end
8'hcd: begin outa = 10'h0a4; outb = 2'b10; outc = 1'b1; end
8'hce: begin outa = 10'h348; outb = 2'b00; outc = 1'b1; end
8'hcf: begin outa = 10'h04b; outb = 2'b11; outc = 1'b1; end
8'hd0: begin outa = 10'h147; outb = 2'b10; outc = 1'b1; end
8'hd1: begin outa = 10'h026; outb = 2'b00; outc = 1'b1; end
8'hd2: begin outa = 10'h103; outb = 2'b00; outc = 1'b0; end
8'hd3: begin outa = 10'h106; outb = 2'b00; outc = 1'b1; end
8'hd4: begin outa = 10'h35a; outb = 2'b00; outc = 1'b0; end
8'hd5: begin outa = 10'h254; outb = 2'b01; outc = 1'b0; end
8'hd6: begin outa = 10'h0cd; outb = 2'b01; outc = 1'b0; end
8'hd7: begin outa = 10'h17c; outb = 2'b11; outc = 1'b1; end
8'hd8: begin outa = 10'h37e; outb = 2'b10; outc = 1'b1; end
8'hd9: begin outa = 10'h0a9; outb = 2'b11; outc = 1'b1; end
8'hda: begin outa = 10'h0fe; outb = 2'b01; outc = 1'b0; end
8'hdb: begin outa = 10'h3c0; outb = 2'b11; outc = 1'b1; end
8'hdc: begin outa = 10'h1d9; outb = 2'b10; outc = 1'b1; end
8'hdd: begin outa = 10'h10e; outb = 2'b00; outc = 1'b1; end
8'hde: begin outa = 10'h394; outb = 2'b01; outc = 1'b0; end
8'hdf: begin outa = 10'h316; outb = 2'b01; outc = 1'b0; end
8'he0: begin outa = 10'h05b; outb = 2'b11; outc = 1'b0; end
8'he1: begin outa = 10'h126; outb = 2'b01; outc = 1'b1; end
8'he2: begin outa = 10'h369; outb = 2'b11; outc = 1'b0; end
8'he3: begin outa = 10'h291; outb = 2'b10; outc = 1'b1; end
8'he4: begin outa = 10'h2ca; outb = 2'b00; outc = 1'b1; end
8'he5: begin outa = 10'h25b; outb = 2'b01; outc = 1'b1; end
8'he6: begin outa = 10'h106; outb = 2'b00; outc = 1'b0; end
8'he7: begin outa = 10'h172; outb = 2'b11; outc = 1'b1; end
8'he8: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end
8'he9: begin outa = 10'h2d3; outb = 2'b11; outc = 1'b1; end
8'hea: begin outa = 10'h182; outb = 2'b00; outc = 1'b0; end
8'heb: begin outa = 10'h327; outb = 2'b00; outc = 1'b1; end
8'hec: begin outa = 10'h1d0; outb = 2'b10; outc = 1'b0; end
8'hed: begin outa = 10'h204; outb = 2'b00; outc = 1'b1; end
8'hee: begin outa = 10'h11f; outb = 2'b00; outc = 1'b1; end
8'hef: begin outa = 10'h365; outb = 2'b11; outc = 1'b1; end
8'hf0: begin outa = 10'h2c2; outb = 2'b01; outc = 1'b1; end
8'hf1: begin outa = 10'h2b5; outb = 2'b10; outc = 1'b0; end
8'hf2: begin outa = 10'h1f8; outb = 2'b10; outc = 1'b1; end
8'hf3: begin outa = 10'h2a7; outb = 2'b01; outc = 1'b1; end
8'hf4: begin outa = 10'h1be; outb = 2'b10; outc = 1'b1; end
8'hf5: begin outa = 10'h25e; outb = 2'b10; outc = 1'b1; end
8'hf6: begin outa = 10'h032; outb = 2'b10; outc = 1'b0; end
8'hf7: begin outa = 10'h2ef; outb = 2'b00; outc = 1'b0; end
8'hf8: begin outa = 10'h02f; outb = 2'b00; outc = 1'b1; end
8'hf9: begin outa = 10'h201; outb = 2'b10; outc = 1'b0; end
8'hfa: begin outa = 10'h054; outb = 2'b01; outc = 1'b1; end
8'hfb: begin outa = 10'h013; outb = 2'b10; outc = 1'b0; end
8'hfc: begin outa = 10'h249; outb = 2'b01; outc = 1'b0; end
8'hfd: begin outa = 10'h09a; outb = 2'b10; outc = 1'b0; end
8'hfe: begin outa = 10'h012; outb = 2'b00; outc = 1'b0; end
8'hff: begin outa = 10'h114; outb = 2'b10; outc = 1'b1; end
endcase
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [15:-16] sel2 = crc[31:0];
wire [80:-10] sel3 = {crc[26:0],crc};
wire [3:0] out21 = sel2[-3 : -6];
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} - 16 +: 4];
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} - 10 -: 4];
wire [3:0] out31 = sel3[-3 : -6];
wire [3:0] out32 = sel3[crc[5:0] - 6 +: 4];
wire [3:0] out33 = sel3[crc[5:0] - 6 -: 4];
// Aggregate outputs into a single result vector
wire [63:0] result = {40'h0, out21, out22, out23, out31, out32, out33};
reg [15:-16] sel1;
initial begin
// Path clearing
sel1 = 32'h12345678;
if (sel1 != 32'h12345678) $stop;
if (sel1[-13 : -16] != 4'h8) $stop;
if (sel1[3:0] != 4'h4) $stop;
if (sel1[4 +: 4] != 4'h3) $stop;
if (sel1[11 -: 4] != 4'h2) $stop;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] sels=%x,%x,%x %x,%x,%x\n",$time, out21,out22,out23, out31,out32,out33);
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hba7fe1e7ac128362
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [41:0] aaa;
wire [41:0] bbb;
// verilator public_module
wire [41:0] z_0;
wire [41:0] z_1;
wide w_0(
.xxx( { {40{1'b0}},2'b11 } ),
.yyy( aaa[1:0] ),
.zzz( z_0 )
);
wide w_1(
.xxx( aaa ),
.yyy( 2'b10 ),
.zzz( z_1 )
);
assign bbb= z_0 + z_1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
aaa <= 42'b01;
end
if (cyc==2) begin
aaa <= 42'b10;
if (z_0 != 42'h4) $stop;
if (z_1 != 42'h3) $stop;
end
if (cyc==3) begin
if (z_0 != 42'h5) $stop;
if (z_1 != 42'h4) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module wide (
input [41:0] xxx,
input [1:0] yyy,
output [41:0] zzz
);
// verilator public_module
assign zzz = xxx+ { {40{1'b0}},yyy };
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [41:0] aaa;
wire [41:0] bbb;
// verilator public_module
wire [41:0] z_0;
wire [41:0] z_1;
wide w_0(
.xxx( { {40{1'b0}},2'b11 } ),
.yyy( aaa[1:0] ),
.zzz( z_0 )
);
wide w_1(
.xxx( aaa ),
.yyy( 2'b10 ),
.zzz( z_1 )
);
assign bbb= z_0 + z_1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
aaa <= 42'b01;
end
if (cyc==2) begin
aaa <= 42'b10;
if (z_0 != 42'h4) $stop;
if (z_1 != 42'h3) $stop;
end
if (cyc==3) begin
if (z_0 != 42'h5) $stop;
if (z_1 != 42'h4) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module wide (
input [41:0] xxx,
input [1:0] yyy,
output [41:0] zzz
);
// verilator public_module
assign zzz = xxx+ { {40{1'b0}},yyy };
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Insure that we can declare a type with a function declaration
function enum integer {
EF_TRUE = 1,
EF_FALSE = 0 }
f_enum_inv ( input a);
f_enum_inv = a ? EF_FALSE : EF_TRUE;
endfunction
initial begin
if (f_enum_inv(1) != 0) $stop;
if (f_enum_inv(0) != 1) $stop;
end
En_t a, z;
sub sub (/*AUTOINST*/
// Outputs
.z (z),
// Inputs
.a (a));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= EN_ZERO;
end
if (cyc==2) begin
a <= EN_ONE;
if (z != EN_ONE) $stop;
end
if (cyc==3) begin
if (z != EN_ZERO) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module sub (input En_t a, output En_t z);
always @* z = (a==EN_ONE) ? EN_ZERO : EN_ONE;
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer _mode;
reg _guard1;
reg [127:0] r_wide0;
reg _guard2;
wire [63:0] r_wide1;
reg _guard3;
reg _guard4;
reg _guard5;
reg _guard6;
assign r_wide1 = r_wide0[127:64];
// surefire lint_off STMINI
initial _mode = 0;
always @ (posedge clk) begin
if (_mode==0) begin
$write("[%0t] t_equal: Running\n", $time);
_guard1 <= 0;
_guard2 <= 0;
_guard3 <= 0;
_guard4 <= 0;
_guard5 <= 0;
_guard6 <= 0;
_mode<=1;
r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444};
end
else if (_mode==1) begin
_mode<=2;
//
if (5'd10 != 5'b1010) $stop;
if (5'd10 != 5'd10) $stop;
if (5'd10 != 5'ha) $stop;
if (5'd10 != 5'o12) $stop;
if (5'd10 != 5'B 1010) $stop;
if (5'd10 != 5'D10) $stop;
if (5'd10 != 5'H a) $stop;
if (5'd10 != 5 'O 12) $stop;
//
if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop;
if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop;
if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin
$write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module t;
real n0; initial n0 = 0.0;
real n1; initial n1 = 1.0;
real n2; initial n2 = 0.1;
real n3; initial n3 = 1.2345e-15;
real n4; initial n4 = 2.579e+15;
reg [7:0] r8; initial r8 = 3;
initial begin
// Display formatting
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n0,n0,n0,n0);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n0,n0,n0,n0);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n0,n0,n0,n0);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n1,n1,n1,n1);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n1,n1,n1,n1);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n1,n1,n1,n1);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n2,n2,n2,n2);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n2,n2,n2,n2);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n2,n2,n2,n2);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n3,n3,n3,n3);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n3,n3,n3,n3);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n3,n3,n3,n3);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n4,n4,n4,n4);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n4,n4,n4,n4);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n4,n4,n4,n4);
$display;
$display("r8=%d n1=%g n2=%g", r8, n1, n2);
$display("n1=%g n2=%g r8=%d", n1, n2, r8);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
module outputs)
wire [7:0] out; // From dspchip of t_dspchip.v
// End of automatics
t_dspchip dspchip (/*AUTOINST*/
// Outputs
.out (out[7:0]),
// Inputs
.dsp_ph1 (dsp_ph1),
.dsp_ph2 (dsp_ph2),
.dsp_reset (dsp_reset),
.padd (padd[7:0]));
always @ (posedge clk) begin
$write("cyc %d\n",cyc);
if (cyc == 8'd0) begin
cyc <= 8'd1;
dsp_reset <= 0; // Need a posedge
padd <= 0;
end
else if (cyc == 8'd20) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
cyc <= cyc + 8'd1;
dsp_ph1 <= ((cyc&8'd3) == 8'd0);
dsp_ph2 <= ((cyc&8'd3) == 8'd2);
dsp_reset <= (cyc == 8'd1);
padd <= cyc;
//$write("[%0t] cyc %d %x->%x\n", $time, cyc, padd, out);
case (cyc)
default: $stop;
8'd01: ;
8'd02: ;
8'd03: ;
8'd04: ;
8'd05: ;
8'd06: ;
8'd07: ;
8'd08: ;
8'd09: if (out!==8'h04) $stop;
8'd10: if (out!==8'h04) $stop;
8'd11: if (out!==8'h08) $stop;
8'd12: if (out!==8'h08) $stop;
8'd13: if (out!==8'h00) $stop;
8'd14: if (out!==8'h00) $stop;
8'd15: if (out!==8'h00) $stop;
8'd16: if (out!==8'h00) $stop;
8'd17: if (out!==8'h0c) $stop;
8'd18: if (out!==8'h0c) $stop;
8'd19: if (out!==8'h10) $stop;
endcase
end
end
endmodule
|
module t_dspchip (/*AUTOARG*/
// Outputs
out,
// Inputs
dsp_ph1, dsp_ph2, dsp_reset, padd
);
input dsp_ph1, dsp_ph2, dsp_reset;
input [7:0] padd;
output [7:0] out;
wire dsp_ph1, dsp_ph2;
wire [7:0] out;
wire pla_ph1, pla_ph2;
wire out1_r;
wire [7:0] out2_r, padd;
wire clk_en;
t_dspcore t_dspcore (/*AUTOINST*/
// Outputs
.out1_r (out1_r),
.pla_ph1 (pla_ph1),
.pla_ph2 (pla_ph2),
// Inputs
.dsp_ph1 (dsp_ph1),
.dsp_ph2 (dsp_ph2),
.dsp_reset (dsp_reset),
.clk_en (clk_en));
t_dsppla t_dsppla (/*AUTOINST*/
// Outputs
.out2_r (out2_r[7:0]),
// Inputs
.pla_ph1 (pla_ph1),
.pla_ph2 (pla_ph2),
.dsp_reset (dsp_reset),
.padd (padd[7:0]));
assign out = out1_r ? 8'h00 : out2_r;
assign clk_en = 1'b1;
endmodule
|
module t_dspcore (/*AUTOARG*/
// Outputs
out1_r, pla_ph1, pla_ph2,
// Inputs
dsp_ph1, dsp_ph2, dsp_reset, clk_en
);
input dsp_ph1, dsp_ph2, dsp_reset;
input clk_en;
output out1_r, pla_ph1, pla_ph2;
wire dsp_ph1, dsp_ph2, dsp_reset;
wire pla_ph1, pla_ph2;
reg out1_r;
always @(posedge dsp_ph1 or posedge dsp_reset) begin
if (dsp_reset)
out1_r <= 1'h0;
else
out1_r <= ~out1_r;
end
assign pla_ph1 = dsp_ph1;
assign pla_ph2 = dsp_ph2 & clk_en;
endmodule
|
module t_dsppla (/*AUTOARG*/
// Outputs
out2_r,
// Inputs
pla_ph1, pla_ph2, dsp_reset, padd
);
input pla_ph1, pla_ph2, dsp_reset;
input [7:0] padd;
output [7:0] out2_r;
wire pla_ph1, pla_ph2, dsp_reset;
wire [7:0] padd;
reg [7:0] out2_r;
reg [7:0] latched_r;
always @(posedge pla_ph1 or posedge dsp_reset) begin
if (dsp_reset)
latched_r <= 8'h00;
else
latched_r <= padd;
end
always @(posedge pla_ph2 or posedge dsp_reset) begin
if (dsp_reset)
out2_r <= 8'h00;
else
out2_r <= latched_r;
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [255:0] i;
wire [255:0] q;
assign q = {
i[176],i[168],i[126],i[177],i[097],i[123],i[231],i[039],
i[156],i[026],i[001],i[052],i[005],i[240],i[157],i[048],
i[111],i[088],i[133],i[225],i[046],i[038],i[004],i[234],
i[115],i[008],i[069],i[099],i[137],i[130],i[255],i[122],
i[223],i[195],i[224],i[083],i[094],i[018],i[067],i[034],
i[221],i[105],i[104],i[107],i[053],i[066],i[020],i[174],
i[010],i[196],i[003],i[041],i[071],i[194],i[154],i[110],
i[186],i[210],i[040],i[044],i[243],i[236],i[239],i[183],
i[164],i[064],i[086],i[193],i[055],i[206],i[203],i[128],
i[190],i[233],i[023],i[022],i[135],i[108],i[061],i[139],
i[180],i[043],i[109],i[090],i[229],i[238],i[095],i[173],
i[208],i[054],i[025],i[024],i[148],i[079],i[246],i[142],
i[181],i[129],i[120],i[220],i[036],i[159],i[201],i[119],
i[216],i[152],i[175],i[138],i[242],i[143],i[101],i[035],
i[228],i[082],i[211],i[062],i[076],i[124],i[150],i[149],
i[235],i[227],i[250],i[134],i[068],i[032],i[060],i[144],
i[042],i[163],i[087],i[059],i[213],i[251],i[200],i[070],
i[145],i[204],i[249],i[191],i[127],i[247],i[106],i[017],
i[028],i[045],i[215],i[162],i[205],i[073],i[065],i[084],
i[153],i[158],i[085],i[197],i[212],i[114],i[096],i[118],
i[146],i[030],i[058],i[230],i[141],i[000],i[199],i[171],
i[182],i[185],i[021],i[016],i[033],i[237],i[015],i[112],
i[222],i[253],i[244],i[031],i[248],i[092],i[226],i[179],
i[189],i[056],i[132],i[116],i[072],i[184],i[027],i[002],
i[103],i[125],i[009],i[078],i[178],i[245],i[170],i[161],
i[102],i[047],i[192],i[012],i[057],i[207],i[187],i[151],
i[218],i[254],i[214],i[037],i[131],i[165],i[011],i[098],
i[169],i[209],i[167],i[202],i[100],i[172],i[147],i[013],
i[136],i[166],i[252],i[077],i[051],i[074],i[140],i[050],
i[217],i[198],i[081],i[091],i[075],i[121],i[188],i[219],
i[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029],
i[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093]
};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x %x\n", q, i);
`endif
if (cyc==1) begin
i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
end
if (cyc==2) begin
i <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
if (q != 256'h697bad4b0cf2d7fa4ad22809293710bb67d1eb3131e8eb2135f2c7bd820baa84) $stop;
end
if (cyc==3) begin
if (q != 256'h320eda5078b3e942353d16dddc8b29fd773b4fcec8323612dadfb1fa483f602c) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [255:0] i;
wire [255:0] q;
assign q = {
i[176],i[168],i[126],i[177],i[097],i[123],i[231],i[039],
i[156],i[026],i[001],i[052],i[005],i[240],i[157],i[048],
i[111],i[088],i[133],i[225],i[046],i[038],i[004],i[234],
i[115],i[008],i[069],i[099],i[137],i[130],i[255],i[122],
i[223],i[195],i[224],i[083],i[094],i[018],i[067],i[034],
i[221],i[105],i[104],i[107],i[053],i[066],i[020],i[174],
i[010],i[196],i[003],i[041],i[071],i[194],i[154],i[110],
i[186],i[210],i[040],i[044],i[243],i[236],i[239],i[183],
i[164],i[064],i[086],i[193],i[055],i[206],i[203],i[128],
i[190],i[233],i[023],i[022],i[135],i[108],i[061],i[139],
i[180],i[043],i[109],i[090],i[229],i[238],i[095],i[173],
i[208],i[054],i[025],i[024],i[148],i[079],i[246],i[142],
i[181],i[129],i[120],i[220],i[036],i[159],i[201],i[119],
i[216],i[152],i[175],i[138],i[242],i[143],i[101],i[035],
i[228],i[082],i[211],i[062],i[076],i[124],i[150],i[149],
i[235],i[227],i[250],i[134],i[068],i[032],i[060],i[144],
i[042],i[163],i[087],i[059],i[213],i[251],i[200],i[070],
i[145],i[204],i[249],i[191],i[127],i[247],i[106],i[017],
i[028],i[045],i[215],i[162],i[205],i[073],i[065],i[084],
i[153],i[158],i[085],i[197],i[212],i[114],i[096],i[118],
i[146],i[030],i[058],i[230],i[141],i[000],i[199],i[171],
i[182],i[185],i[021],i[016],i[033],i[237],i[015],i[112],
i[222],i[253],i[244],i[031],i[248],i[092],i[226],i[179],
i[189],i[056],i[132],i[116],i[072],i[184],i[027],i[002],
i[103],i[125],i[009],i[078],i[178],i[245],i[170],i[161],
i[102],i[047],i[192],i[012],i[057],i[207],i[187],i[151],
i[218],i[254],i[214],i[037],i[131],i[165],i[011],i[098],
i[169],i[209],i[167],i[202],i[100],i[172],i[147],i[013],
i[136],i[166],i[252],i[077],i[051],i[074],i[140],i[050],
i[217],i[198],i[081],i[091],i[075],i[121],i[188],i[219],
i[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029],
i[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093]
};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x %x\n", q, i);
`endif
if (cyc==1) begin
i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
end
if (cyc==2) begin
i <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
if (q != 256'h697bad4b0cf2d7fa4ad22809293710bb67d1eb3131e8eb2135f2c7bd820baa84) $stop;
end
if (cyc==3) begin
if (q != 256'h320eda5078b3e942353d16dddc8b29fd773b4fcec8323612dadfb1fa483f602c) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [255:0] i;
wire [255:0] q;
assign q = {
i[176],i[168],i[126],i[177],i[097],i[123],i[231],i[039],
i[156],i[026],i[001],i[052],i[005],i[240],i[157],i[048],
i[111],i[088],i[133],i[225],i[046],i[038],i[004],i[234],
i[115],i[008],i[069],i[099],i[137],i[130],i[255],i[122],
i[223],i[195],i[224],i[083],i[094],i[018],i[067],i[034],
i[221],i[105],i[104],i[107],i[053],i[066],i[020],i[174],
i[010],i[196],i[003],i[041],i[071],i[194],i[154],i[110],
i[186],i[210],i[040],i[044],i[243],i[236],i[239],i[183],
i[164],i[064],i[086],i[193],i[055],i[206],i[203],i[128],
i[190],i[233],i[023],i[022],i[135],i[108],i[061],i[139],
i[180],i[043],i[109],i[090],i[229],i[238],i[095],i[173],
i[208],i[054],i[025],i[024],i[148],i[079],i[246],i[142],
i[181],i[129],i[120],i[220],i[036],i[159],i[201],i[119],
i[216],i[152],i[175],i[138],i[242],i[143],i[101],i[035],
i[228],i[082],i[211],i[062],i[076],i[124],i[150],i[149],
i[235],i[227],i[250],i[134],i[068],i[032],i[060],i[144],
i[042],i[163],i[087],i[059],i[213],i[251],i[200],i[070],
i[145],i[204],i[249],i[191],i[127],i[247],i[106],i[017],
i[028],i[045],i[215],i[162],i[205],i[073],i[065],i[084],
i[153],i[158],i[085],i[197],i[212],i[114],i[096],i[118],
i[146],i[030],i[058],i[230],i[141],i[000],i[199],i[171],
i[182],i[185],i[021],i[016],i[033],i[237],i[015],i[112],
i[222],i[253],i[244],i[031],i[248],i[092],i[226],i[179],
i[189],i[056],i[132],i[116],i[072],i[184],i[027],i[002],
i[103],i[125],i[009],i[078],i[178],i[245],i[170],i[161],
i[102],i[047],i[192],i[012],i[057],i[207],i[187],i[151],
i[218],i[254],i[214],i[037],i[131],i[165],i[011],i[098],
i[169],i[209],i[167],i[202],i[100],i[172],i[147],i[013],
i[136],i[166],i[252],i[077],i[051],i[074],i[140],i[050],
i[217],i[198],i[081],i[091],i[075],i[121],i[188],i[219],
i[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029],
i[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093]
};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x %x\n", q, i);
`endif
if (cyc==1) begin
i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
end
if (cyc==2) begin
i <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
if (q != 256'h697bad4b0cf2d7fa4ad22809293710bb67d1eb3131e8eb2135f2c7bd820baa84) $stop;
end
if (cyc==3) begin
if (q != 256'h320eda5078b3e942353d16dddc8b29fd773b4fcec8323612dadfb1fa483f602c) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [255:0] i;
wire [255:0] q;
assign q = {
i[176],i[168],i[126],i[177],i[097],i[123],i[231],i[039],
i[156],i[026],i[001],i[052],i[005],i[240],i[157],i[048],
i[111],i[088],i[133],i[225],i[046],i[038],i[004],i[234],
i[115],i[008],i[069],i[099],i[137],i[130],i[255],i[122],
i[223],i[195],i[224],i[083],i[094],i[018],i[067],i[034],
i[221],i[105],i[104],i[107],i[053],i[066],i[020],i[174],
i[010],i[196],i[003],i[041],i[071],i[194],i[154],i[110],
i[186],i[210],i[040],i[044],i[243],i[236],i[239],i[183],
i[164],i[064],i[086],i[193],i[055],i[206],i[203],i[128],
i[190],i[233],i[023],i[022],i[135],i[108],i[061],i[139],
i[180],i[043],i[109],i[090],i[229],i[238],i[095],i[173],
i[208],i[054],i[025],i[024],i[148],i[079],i[246],i[142],
i[181],i[129],i[120],i[220],i[036],i[159],i[201],i[119],
i[216],i[152],i[175],i[138],i[242],i[143],i[101],i[035],
i[228],i[082],i[211],i[062],i[076],i[124],i[150],i[149],
i[235],i[227],i[250],i[134],i[068],i[032],i[060],i[144],
i[042],i[163],i[087],i[059],i[213],i[251],i[200],i[070],
i[145],i[204],i[249],i[191],i[127],i[247],i[106],i[017],
i[028],i[045],i[215],i[162],i[205],i[073],i[065],i[084],
i[153],i[158],i[085],i[197],i[212],i[114],i[096],i[118],
i[146],i[030],i[058],i[230],i[141],i[000],i[199],i[171],
i[182],i[185],i[021],i[016],i[033],i[237],i[015],i[112],
i[222],i[253],i[244],i[031],i[248],i[092],i[226],i[179],
i[189],i[056],i[132],i[116],i[072],i[184],i[027],i[002],
i[103],i[125],i[009],i[078],i[178],i[245],i[170],i[161],
i[102],i[047],i[192],i[012],i[057],i[207],i[187],i[151],
i[218],i[254],i[214],i[037],i[131],i[165],i[011],i[098],
i[169],i[209],i[167],i[202],i[100],i[172],i[147],i[013],
i[136],i[166],i[252],i[077],i[051],i[074],i[140],i[050],
i[217],i[198],i[081],i[091],i[075],i[121],i[188],i[219],
i[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029],
i[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093]
};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x %x\n", q, i);
`endif
if (cyc==1) begin
i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
end
if (cyc==2) begin
i <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
if (q != 256'h697bad4b0cf2d7fa4ad22809293710bb67d1eb3131e8eb2135f2c7bd820baa84) $stop;
end
if (cyc==3) begin
if (q != 256'h320eda5078b3e942353d16dddc8b29fd773b4fcec8323612dadfb1fa483f602c) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
integer j;
reg [63:0] cam_lookup_hit_vector;
integer hit_count;
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
hit_count = 0;
for (j=0; j < 64; j=j+1) begin
hit_count = hit_count + {31'h0, cam_lookup_hit_vector[j]};
end
end
integer hit_count2;
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
hit_count2 = 0;
for (j=63; j >= 0; j=j-1) begin
hit_count2 = hit_count2 + {31'h0, cam_lookup_hit_vector[j]};
end
end
integer hit_count3;
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
hit_count3 = 0;
for (j=63; j > 0; j=j-1) begin
if (cam_lookup_hit_vector[j]) hit_count3 = hit_count3 + 32'd1;
end
end
reg [127:0] wide_for_index;
reg [31:0] wide_for_count;
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
wide_for_count = 0;
for (wide_for_index = 128'hff_00000000_00000000;
wide_for_index < 128'hff_00000000_00000100;
wide_for_index = wide_for_index + 2) begin
wide_for_count = wide_for_count+32'h1;
end
end
// While loop
integer w;
initial begin
while (w<10) w=w+1;
if (w!=10) $stop;
while (w<20) begin w=w+2; end
while (w<20) begin w=w+99999; end // NEVER
if (w!=20) $stop;
end
// Do-While loop
integer dw;
initial begin
do dw=dw+1; while (dw<10);
if (dw!=10) $stop;
do dw=dw+2; while (dw<20);
if (dw!=20) $stop;
do dw=dw+5; while (dw<20); // Once
if (dw!=25) $stop;
end
always @ (posedge clk) begin
cam_lookup_hit_vector <= 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
cam_lookup_hit_vector <= 64'h00010000_00010000;
end
if (cyc==2) begin
if (hit_count != 32'd2) $stop;
if (hit_count2 != 32'd2) $stop;
if (hit_count3 != 32'd2) $stop;
cam_lookup_hit_vector <= 64'h01010010_00010001;
end
if (cyc==3) begin
if (hit_count != 32'd5) $stop;
if (hit_count2 != 32'd5) $stop;
if (hit_count3 != 32'd4) $stop;
if (wide_for_count != 32'h80) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module t(/*AUTOARG*/
// Inputs
clk
);
// surefire lint_off NBAJAM
input clk;
reg [7:0] _ranit;
reg [2:0] a;
reg [7:0] vvector;
reg [7:0] vvector_flip;
// surefire lint_off STMINI
initial _ranit = 0;
always @ (posedge clk) begin
a <= a + 3'd1;
vvector[a] <= 1'b1; // This should use "old" value for a
vvector_flip[~a] <= 1'b1; // This should use "old" value for a
//
//========
if (_ranit==8'd0) begin
_ranit <= 8'd1;
$write("[%0t] t_select_index: Running\n", $time);
vvector <= 0;
vvector_flip <= 0;
a <= 3'b1;
end
else _ranit <= _ranit + 8'd1;
//
if (_ranit==8'd3) begin
$write("%x %x\n",vvector,vvector_flip);
if (vvector !== 8'b0000110) $stop;
if (vvector_flip !== 8'b0110_0000) $stop;
//
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module t(/*AUTOARG*/
// Inputs
clk
);
// surefire lint_off NBAJAM
input clk;
reg [7:0] _ranit;
reg [2:0] a;
reg [7:0] vvector;
reg [7:0] vvector_flip;
// surefire lint_off STMINI
initial _ranit = 0;
always @ (posedge clk) begin
a <= a + 3'd1;
vvector[a] <= 1'b1; // This should use "old" value for a
vvector_flip[~a] <= 1'b1; // This should use "old" value for a
//
//========
if (_ranit==8'd0) begin
_ranit <= 8'd1;
$write("[%0t] t_select_index: Running\n", $time);
vvector <= 0;
vvector_flip <= 0;
a <= 3'b1;
end
else _ranit <= _ranit + 8'd1;
//
if (_ranit==8'd3) begin
$write("%x %x\n",vvector,vvector_flip);
if (vvector !== 8'b0000110) $stop;
if (vvector_flip !== 8'b0110_0000) $stop;
//
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module t(/*AUTOARG*/
// Inputs
clk
);
// surefire lint_off NBAJAM
input clk;
reg [7:0] _ranit;
reg [2:0] a;
reg [7:0] vvector;
reg [7:0] vvector_flip;
// surefire lint_off STMINI
initial _ranit = 0;
always @ (posedge clk) begin
a <= a + 3'd1;
vvector[a] <= 1'b1; // This should use "old" value for a
vvector_flip[~a] <= 1'b1; // This should use "old" value for a
//
//========
if (_ranit==8'd0) begin
_ranit <= 8'd1;
$write("[%0t] t_select_index: Running\n", $time);
vvector <= 0;
vvector_flip <= 0;
a <= 3'b1;
end
else _ranit <= _ranit + 8'd1;
//
if (_ranit==8'd3) begin
$write("%x %x\n",vvector,vvector_flip);
if (vvector !== 8'b0000110) $stop;
if (vvector_flip !== 8'b0110_0000) $stop;
//
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module outputs)
wire [wl-1:0] Quotient; // From test of Test.v
wire [wl-1:0] Remainder; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.Quotient (Quotient[wl-1:0]),
.Remainder (Remainder[wl-1:0]),
// Inputs
.Operand1 (Operand1[wl*2-1:0]),
.Operand2 (Operand2[wl-1:0]),
.clk (clk),
.rst (rst),
.Unsigned (Unsigned));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, Quotient, Remainder};
// What checksum will we end up with
`define EXPECTED_SUM 64'h98d41f89a8be5693
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x it=%x\n",$time, cyc, crc, result, test.Iteration);
`endif
cyc <= cyc + 1;
if (cyc < 20 || test.Iteration==4'd15) begin
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
end
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
rst <= 1'b1;
end
else if (cyc<20) begin
sum <= 64'h0;
rst <= 1'b0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'h8dd70a44972ad809) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module Test(clk, rst, Operand1, Operand2, Unsigned, Quotient, Remainder);
parameter wl = 16;
input [wl*2-1:0] Operand1;
input [wl-1:0] Operand2;
input clk, rst, Unsigned;
output [wl-1:0] Quotient, Remainder;
reg Cy, Overflow, Sign1, Sign2, Zero, Negative;
reg [wl-1:0] ah,al,Quotient, Remainder;
reg [3:0] Iteration;
reg [wl-1:0] sub_quot,op;
reg ah_ext;
reg [1:0] a,b,c,d,e;
always @(posedge clk) begin
if (!rst) begin
{a,b,c,d,e} = Operand1[9:0];
{a,b,c,d,e} = {e,d,c,b,a};
if (a != Operand1[1:0]) $stop;
if (b != Operand1[3:2]) $stop;
if (c != Operand1[5:4]) $stop;
if (d != Operand1[7:6]) $stop;
if (e != Operand1[9:8]) $stop;
end
end
always @(posedge clk) begin
if (rst) begin
Iteration <= 0;
Quotient <= 0;
Remainder <= 0;
end
else begin
if (Iteration == 0) begin
{ah,al} = Operand1;
op = Operand2;
Cy = 0;
Overflow = 0;
Sign1 = (~Unsigned)&ah[wl-1];
Sign2 = (~Unsigned)&(ah[wl-1]^op[wl-1]);
if (Sign1) {ah,al} = -{ah,al};
end
`define BUG1
`ifdef BUG1
{ah_ext,ah,al} = {ah,al,Cy};
`else
ah_ext = ah[15];
ah[15:1] = ah[14:0];
ah[0] = al[15];
al[15:1] = al[14:0];
al[0] = Cy;
`endif
`ifdef TEST_VERBOSE
$display("%x %x %x %x %x %x %x %x %x",
Iteration, ah, al, Quotient, Remainder, Overflow, ah_ext, sub_quot, Cy);
`endif
{Cy,sub_quot} = (~Unsigned)&op[wl-1]? {ah_ext,ah}+op : {ah_ext,ah} - {1'b1,op};
if (Cy)
begin
{ah_ext,ah} = {1'b0,sub_quot};
end
if (Iteration != 15 )
begin
if (ah_ext) Overflow = 1;
end
else
begin
if (al[14] && ~Unsigned) Overflow = 1;
Quotient <= Sign2 ? -{al[14:0],Cy} : {al[14:0],Cy};
Remainder <= Sign1 ? -ah : ah;
if (Overflow)
begin
Quotient <= Sign2 ? 16'h8001 : {Unsigned,{15{1'b1}}};
Remainder <= Unsigned ? 16'hffff : 16'h8000;
Zero = 1;
Negative = 1;
end
end
Iteration <= Iteration + 1; // Count number of times this instruction is repeated
end
end
endmodule
|
module outputs)
wire [wl-1:0] Quotient; // From test of Test.v
wire [wl-1:0] Remainder; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.Quotient (Quotient[wl-1:0]),
.Remainder (Remainder[wl-1:0]),
// Inputs
.Operand1 (Operand1[wl*2-1:0]),
.Operand2 (Operand2[wl-1:0]),
.clk (clk),
.rst (rst),
.Unsigned (Unsigned));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, Quotient, Remainder};
// What checksum will we end up with
`define EXPECTED_SUM 64'h98d41f89a8be5693
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x it=%x\n",$time, cyc, crc, result, test.Iteration);
`endif
cyc <= cyc + 1;
if (cyc < 20 || test.Iteration==4'd15) begin
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
end
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
rst <= 1'b1;
end
else if (cyc<20) begin
sum <= 64'h0;
rst <= 1'b0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'h8dd70a44972ad809) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module Test(clk, rst, Operand1, Operand2, Unsigned, Quotient, Remainder);
parameter wl = 16;
input [wl*2-1:0] Operand1;
input [wl-1:0] Operand2;
input clk, rst, Unsigned;
output [wl-1:0] Quotient, Remainder;
reg Cy, Overflow, Sign1, Sign2, Zero, Negative;
reg [wl-1:0] ah,al,Quotient, Remainder;
reg [3:0] Iteration;
reg [wl-1:0] sub_quot,op;
reg ah_ext;
reg [1:0] a,b,c,d,e;
always @(posedge clk) begin
if (!rst) begin
{a,b,c,d,e} = Operand1[9:0];
{a,b,c,d,e} = {e,d,c,b,a};
if (a != Operand1[1:0]) $stop;
if (b != Operand1[3:2]) $stop;
if (c != Operand1[5:4]) $stop;
if (d != Operand1[7:6]) $stop;
if (e != Operand1[9:8]) $stop;
end
end
always @(posedge clk) begin
if (rst) begin
Iteration <= 0;
Quotient <= 0;
Remainder <= 0;
end
else begin
if (Iteration == 0) begin
{ah,al} = Operand1;
op = Operand2;
Cy = 0;
Overflow = 0;
Sign1 = (~Unsigned)&ah[wl-1];
Sign2 = (~Unsigned)&(ah[wl-1]^op[wl-1]);
if (Sign1) {ah,al} = -{ah,al};
end
`define BUG1
`ifdef BUG1
{ah_ext,ah,al} = {ah,al,Cy};
`else
ah_ext = ah[15];
ah[15:1] = ah[14:0];
ah[0] = al[15];
al[15:1] = al[14:0];
al[0] = Cy;
`endif
`ifdef TEST_VERBOSE
$display("%x %x %x %x %x %x %x %x %x",
Iteration, ah, al, Quotient, Remainder, Overflow, ah_ext, sub_quot, Cy);
`endif
{Cy,sub_quot} = (~Unsigned)&op[wl-1]? {ah_ext,ah}+op : {ah_ext,ah} - {1'b1,op};
if (Cy)
begin
{ah_ext,ah} = {1'b0,sub_quot};
end
if (Iteration != 15 )
begin
if (ah_ext) Overflow = 1;
end
else
begin
if (al[14] && ~Unsigned) Overflow = 1;
Quotient <= Sign2 ? -{al[14:0],Cy} : {al[14:0],Cy};
Remainder <= Sign1 ? -ah : ah;
if (Overflow)
begin
Quotient <= Sign2 ? 16'h8001 : {Unsigned,{15{1'b1}}};
Remainder <= Unsigned ? 16'hffff : 16'h8000;
Zero = 1;
Negative = 1;
end
end
Iteration <= Iteration + 1; // Count number of times this instruction is repeated
end
end
endmodule
|
module outputs)
wire [15:0] outa; // From test of Test.v
wire [15:0] outb; // From test of Test.v
wire [15:0] outc; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.outa (outa[15:0]),
.outb (outb[15:0]),
.outc (outc[15:0]),
// Inputs
.clk (clk),
.in (in[15:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {16'h0, outa, outb, outc};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h09be74b1b0f8c35d
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module Test (/*AUTOARG*/
// Outputs
outa, outb, outc,
// Inputs
clk, in
);
input clk;
input [15:0] in;
output reg [15:0] outa;
output reg [15:0] outb;
output reg [15:0] outc;
parameter WIDTH = 0;
always @(posedge clk) begin
outa <= {in};
outb <= {{WIDTH{1'b0}}, in};
outc <= {in, {WIDTH{1'b0}}};
end
endmodule
|
module outputs)
wire [15:0] outa; // From test of Test.v
wire [15:0] outb; // From test of Test.v
wire [15:0] outc; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.outa (outa[15:0]),
.outb (outb[15:0]),
.outc (outc[15:0]),
// Inputs
.clk (clk),
.in (in[15:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {16'h0, outa, outb, outc};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h09be74b1b0f8c35d
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module Test (/*AUTOARG*/
// Outputs
outa, outb, outc,
// Inputs
clk, in
);
input clk;
input [15:0] in;
output reg [15:0] outa;
output reg [15:0] outb;
output reg [15:0] outc;
parameter WIDTH = 0;
always @(posedge clk) begin
outa <= {in};
outb <= {{WIDTH{1'b0}}, in};
outc <= {in, {WIDTH{1'b0}}};
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [15:0] m_din;
// OK
reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
c_split_1 <= 16'h0;
c_split_2 <= 16'h0;
c_split_3 <= 16'h0;
c_split_4 <= 0;
c_split_5 <= 0;
// End of automatics
end
else begin
c_split_1 <= m_din;
c_split_2 <= c_split_1;
c_split_3 <= c_split_2 & {16{(cyc!=0)}};
if (cyc==1) begin
c_split_4 <= 16'h4;
c_split_5 <= 16'h5;
end
else begin
c_split_4 <= c_split_3;
c_split_5 <= c_split_4;
end
end
end
// OK
reg [15:0] d_split_1, d_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
d_split_1 <= 16'h0;
d_split_2 <= 16'h0;
// End of automatics
end
else begin
d_split_1 <= m_din;
d_split_2 <= d_split_1;
d_split_1 <= ~m_din;
end
end
// Not OK
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
// End of automatics
end
else begin
$write(" foo %x", m_din);
$write(" bar %x\n", m_din);
end
end
// Not OK
reg [15:0] e_split_1, e_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
e_split_1 = 16'h0;
e_split_2 = 16'h0;
// End of automatics
end
else begin
e_split_1 = m_din;
e_split_2 = e_split_1;
end
end
// Not OK
reg [15:0] f_split_1, f_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
f_split_1 = 16'h0;
f_split_2 = 16'h0;
// End of automatics
end
else begin
f_split_2 = f_split_1;
f_split_1 = m_din;
end
end
always @ (posedge clk) begin
if (cyc!=0) begin
//$write(" C %d %x %x\n", cyc, c_split_1, c_split_2);
cyc<=cyc+1;
if (cyc==1) begin
m_din <= 16'hfeed;
end
if (cyc==3) begin
end
if (cyc==4) begin
m_din <= 16'he11e;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop;
end
if (cyc==5) begin
m_din <= 16'he22e;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop;
end
if (cyc==6) begin
m_din <= 16'he33e;
if (!(c_split_1==16'he11e && c_split_2==16'hfeed && c_split_3==16'hfeed)) $stop;
if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop;
if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop;
end
if (cyc==7) begin
m_din <= 16'he44e;
if (!(c_split_1==16'he22e && c_split_2==16'he11e && c_split_3==16'hfeed)) $stop;
end
if (cyc==8) begin
m_din <= 16'he55e;
if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e
&& c_split_4==16'hfeed && c_split_5==16'hfeed)) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [31:0] sum;
wire [8:0] Output;
wire [8:0] Input = crc[8:0];
assigns assigns (/*AUTOINST*/
// Outputs
.Output (Output[8:0]),
// Inputs
.Input (Input[8:0]));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 32'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[30:0],sum[31]} ^ {23'h0, crc[8:0]};
end
else if (cyc==99) begin
if (sum !== 32'he8bbd130) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module assigns(Input, Output);
input [8:0] Input;
output [8:0] Output;
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : ap
assign Output[(i>0) ? i-1 : 8] = Input[(i>0) ? i-1 : 8];
end
endgenerate
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [31:0] sum;
wire [8:0] Output;
wire [8:0] Input = crc[8:0];
assigns assigns (/*AUTOINST*/
// Outputs
.Output (Output[8:0]),
// Inputs
.Input (Input[8:0]));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 32'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[30:0],sum[31]} ^ {23'h0, crc[8:0]};
end
else if (cyc==99) begin
if (sum !== 32'he8bbd130) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module assigns(Input, Output);
input [8:0] Input;
output [8:0] Output;
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : ap
assign Output[(i>0) ? i-1 : 8] = Input[(i>0) ? i-1 : 8];
end
endgenerate
endmodule
|
module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test #(16,2) test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hf9b3a5000165ed38
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [31:0] out;
parameter N = 0;
parameter PASSDOWN = 1;
add #(PASSDOWN) add (.in (in[(2*N)-1:(0*N)]),
.out (out));
endmodule
|
module add (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter PASSDOWN = 9999;
input [31:0] in;
output [31:0] out;
wire out = in + PASSDOWN;
endmodule
|
module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test #(16,2) test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hf9b3a5000165ed38
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [31:0] out;
parameter N = 0;
parameter PASSDOWN = 1;
add #(PASSDOWN) add (.in (in[(2*N)-1:(0*N)]),
.out (out));
endmodule
|
module add (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter PASSDOWN = 9999;
input [31:0] in;
output [31:0] out;
wire out = in + PASSDOWN;
endmodule
|
module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test #(16,2) test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hf9b3a5000165ed38
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
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