module_content
stringlengths 18
1.05M
|
|---|
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [31:0] out;
parameter N = 0;
parameter PASSDOWN = 1;
add #(PASSDOWN) add (.in (in[(2*N)-1:(0*N)]),
.out (out));
endmodule
|
module add (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter PASSDOWN = 9999;
input [31:0] in;
output [31:0] out;
wire out = in + PASSDOWN;
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
defparam i.L00 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L01 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L02 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L03 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L04 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L05 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L06 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L07 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L08 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L09 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L10 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L11 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L12 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L13 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L14 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L15 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L16 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L17 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L18 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L19 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L20 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L21 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L22 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L23 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L24 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L25 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L26 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L27 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L28 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L29 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L30 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L31 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L32 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L33 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L34 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L35 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L36 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L37 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L38 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L39 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.A0 = "HELLO_WORLD_BOY_THIS_IS_LONG";
defparam i.A1 = "HELLO_WORLD_BOY_THIS_IS_LONG";
defparam i.A2 = "HELLO_WORLD_BOY_THIS_IS_LONG";
i i (.clk(clk));
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module i
(/*AUTOARG*/
// Inputs
clk
);
// verilator public_module
input clk;
parameter [255:0] L00 = 256'h0;
parameter [255:0] L01 = 256'h0;
parameter [255:0] L02 = 256'h0;
parameter [255:0] L03 = 256'h0;
parameter [255:0] L04 = 256'h0;
parameter [255:0] L05 = 256'h0;
parameter [255:0] L06 = 256'h0;
parameter [255:0] L07 = 256'h0;
parameter [255:0] L08 = 256'h0;
parameter [255:0] L09 = 256'h0;
parameter [255:0] L0A = 256'h0;
parameter [255:0] L0B = 256'h0;
parameter [255:0] L0C = 256'h0;
parameter [255:0] L0D = 256'h0;
parameter [255:0] L0E = 256'h0;
parameter [255:0] L0F = 256'h0;
parameter [255:0] L10 = 256'h0;
parameter [255:0] L11 = 256'h0;
parameter [255:0] L12 = 256'h0;
parameter [255:0] L13 = 256'h0;
parameter [255:0] L14 = 256'h0;
parameter [255:0] L15 = 256'h0;
parameter [255:0] L16 = 256'h0;
parameter [255:0] L17 = 256'h0;
parameter [255:0] L18 = 256'h0;
parameter [255:0] L19 = 256'h0;
parameter [255:0] L1A = 256'h0;
parameter [255:0] L1B = 256'h0;
parameter [255:0] L1C = 256'h0;
parameter [255:0] L1D = 256'h0;
parameter [255:0] L1E = 256'h0;
parameter [255:0] L1F = 256'h0;
parameter [255:0] L20 = 256'h0;
parameter [255:0] L21 = 256'h0;
parameter [255:0] L22 = 256'h0;
parameter [255:0] L23 = 256'h0;
parameter [255:0] L24 = 256'h0;
parameter [255:0] L25 = 256'h0;
parameter [255:0] L26 = 256'h0;
parameter [255:0] L27 = 256'h0;
parameter [255:0] L28 = 256'h0;
parameter [255:0] L29 = 256'h0;
parameter [255:0] L2A = 256'h0;
parameter [255:0] L2B = 256'h0;
parameter [255:0] L2C = 256'h0;
parameter [255:0] L2D = 256'h0;
parameter [255:0] L2E = 256'h0;
parameter [255:0] L2F = 256'h0;
parameter [255:0] L30 = 256'h0;
parameter [255:0] L31 = 256'h0;
parameter [255:0] L32 = 256'h0;
parameter [255:0] L33 = 256'h0;
parameter [255:0] L34 = 256'h0;
parameter [255:0] L35 = 256'h0;
parameter [255:0] L36 = 256'h0;
parameter [255:0] L37 = 256'h0;
parameter [255:0] L38 = 256'h0;
parameter [255:0] L39 = 256'h0;
parameter [255:0] L3A = 256'h0;
parameter [255:0] L3B = 256'h0;
parameter [255:0] L3C = 256'h0;
parameter [255:0] L3D = 256'h0;
parameter [255:0] L3E = 256'h0;
parameter [255:0] L3F = 256'h0;
parameter [255:0] A0 = 256'h0;
parameter [255:0] A1 = 256'h0;
parameter [255:0] A2 = 256'h0;
always @ (posedge clk) begin
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
defparam i.L00 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L01 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L02 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L03 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L04 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L05 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L06 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L07 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L08 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L09 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L10 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L11 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L12 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L13 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L14 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L15 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L16 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L17 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L18 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L19 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L20 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L21 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L22 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L23 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L24 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L25 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L26 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L27 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L28 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L29 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L30 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L31 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L32 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L33 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L34 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L35 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L36 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L37 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L38 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L39 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.A0 = "HELLO_WORLD_BOY_THIS_IS_LONG";
defparam i.A1 = "HELLO_WORLD_BOY_THIS_IS_LONG";
defparam i.A2 = "HELLO_WORLD_BOY_THIS_IS_LONG";
i i (.clk(clk));
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module i
(/*AUTOARG*/
// Inputs
clk
);
// verilator public_module
input clk;
parameter [255:0] L00 = 256'h0;
parameter [255:0] L01 = 256'h0;
parameter [255:0] L02 = 256'h0;
parameter [255:0] L03 = 256'h0;
parameter [255:0] L04 = 256'h0;
parameter [255:0] L05 = 256'h0;
parameter [255:0] L06 = 256'h0;
parameter [255:0] L07 = 256'h0;
parameter [255:0] L08 = 256'h0;
parameter [255:0] L09 = 256'h0;
parameter [255:0] L0A = 256'h0;
parameter [255:0] L0B = 256'h0;
parameter [255:0] L0C = 256'h0;
parameter [255:0] L0D = 256'h0;
parameter [255:0] L0E = 256'h0;
parameter [255:0] L0F = 256'h0;
parameter [255:0] L10 = 256'h0;
parameter [255:0] L11 = 256'h0;
parameter [255:0] L12 = 256'h0;
parameter [255:0] L13 = 256'h0;
parameter [255:0] L14 = 256'h0;
parameter [255:0] L15 = 256'h0;
parameter [255:0] L16 = 256'h0;
parameter [255:0] L17 = 256'h0;
parameter [255:0] L18 = 256'h0;
parameter [255:0] L19 = 256'h0;
parameter [255:0] L1A = 256'h0;
parameter [255:0] L1B = 256'h0;
parameter [255:0] L1C = 256'h0;
parameter [255:0] L1D = 256'h0;
parameter [255:0] L1E = 256'h0;
parameter [255:0] L1F = 256'h0;
parameter [255:0] L20 = 256'h0;
parameter [255:0] L21 = 256'h0;
parameter [255:0] L22 = 256'h0;
parameter [255:0] L23 = 256'h0;
parameter [255:0] L24 = 256'h0;
parameter [255:0] L25 = 256'h0;
parameter [255:0] L26 = 256'h0;
parameter [255:0] L27 = 256'h0;
parameter [255:0] L28 = 256'h0;
parameter [255:0] L29 = 256'h0;
parameter [255:0] L2A = 256'h0;
parameter [255:0] L2B = 256'h0;
parameter [255:0] L2C = 256'h0;
parameter [255:0] L2D = 256'h0;
parameter [255:0] L2E = 256'h0;
parameter [255:0] L2F = 256'h0;
parameter [255:0] L30 = 256'h0;
parameter [255:0] L31 = 256'h0;
parameter [255:0] L32 = 256'h0;
parameter [255:0] L33 = 256'h0;
parameter [255:0] L34 = 256'h0;
parameter [255:0] L35 = 256'h0;
parameter [255:0] L36 = 256'h0;
parameter [255:0] L37 = 256'h0;
parameter [255:0] L38 = 256'h0;
parameter [255:0] L39 = 256'h0;
parameter [255:0] L3A = 256'h0;
parameter [255:0] L3B = 256'h0;
parameter [255:0] L3C = 256'h0;
parameter [255:0] L3D = 256'h0;
parameter [255:0] L3E = 256'h0;
parameter [255:0] L3F = 256'h0;
parameter [255:0] A0 = 256'h0;
parameter [255:0] A1 = 256'h0;
parameter [255:0] A2 = 256'h0;
always @ (posedge clk) begin
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
defparam i.L00 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L01 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L02 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L03 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L04 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L05 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L06 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L07 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L08 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L09 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L0F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L10 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L11 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L12 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L13 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L14 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L15 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L16 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L17 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L18 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L19 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L1F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L20 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L21 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L22 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L23 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L24 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L25 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L26 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L27 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L28 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L29 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L2F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L30 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L31 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L32 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L33 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L34 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L35 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L36 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L37 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L38 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L39 = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3A = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3B = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3C = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3D = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3E = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.L3F = 256'h000012300000000000000000000000000000000000000000000000000000cdef;
defparam i.A0 = "HELLO_WORLD_BOY_THIS_IS_LONG";
defparam i.A1 = "HELLO_WORLD_BOY_THIS_IS_LONG";
defparam i.A2 = "HELLO_WORLD_BOY_THIS_IS_LONG";
i i (.clk(clk));
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module i
(/*AUTOARG*/
// Inputs
clk
);
// verilator public_module
input clk;
parameter [255:0] L00 = 256'h0;
parameter [255:0] L01 = 256'h0;
parameter [255:0] L02 = 256'h0;
parameter [255:0] L03 = 256'h0;
parameter [255:0] L04 = 256'h0;
parameter [255:0] L05 = 256'h0;
parameter [255:0] L06 = 256'h0;
parameter [255:0] L07 = 256'h0;
parameter [255:0] L08 = 256'h0;
parameter [255:0] L09 = 256'h0;
parameter [255:0] L0A = 256'h0;
parameter [255:0] L0B = 256'h0;
parameter [255:0] L0C = 256'h0;
parameter [255:0] L0D = 256'h0;
parameter [255:0] L0E = 256'h0;
parameter [255:0] L0F = 256'h0;
parameter [255:0] L10 = 256'h0;
parameter [255:0] L11 = 256'h0;
parameter [255:0] L12 = 256'h0;
parameter [255:0] L13 = 256'h0;
parameter [255:0] L14 = 256'h0;
parameter [255:0] L15 = 256'h0;
parameter [255:0] L16 = 256'h0;
parameter [255:0] L17 = 256'h0;
parameter [255:0] L18 = 256'h0;
parameter [255:0] L19 = 256'h0;
parameter [255:0] L1A = 256'h0;
parameter [255:0] L1B = 256'h0;
parameter [255:0] L1C = 256'h0;
parameter [255:0] L1D = 256'h0;
parameter [255:0] L1E = 256'h0;
parameter [255:0] L1F = 256'h0;
parameter [255:0] L20 = 256'h0;
parameter [255:0] L21 = 256'h0;
parameter [255:0] L22 = 256'h0;
parameter [255:0] L23 = 256'h0;
parameter [255:0] L24 = 256'h0;
parameter [255:0] L25 = 256'h0;
parameter [255:0] L26 = 256'h0;
parameter [255:0] L27 = 256'h0;
parameter [255:0] L28 = 256'h0;
parameter [255:0] L29 = 256'h0;
parameter [255:0] L2A = 256'h0;
parameter [255:0] L2B = 256'h0;
parameter [255:0] L2C = 256'h0;
parameter [255:0] L2D = 256'h0;
parameter [255:0] L2E = 256'h0;
parameter [255:0] L2F = 256'h0;
parameter [255:0] L30 = 256'h0;
parameter [255:0] L31 = 256'h0;
parameter [255:0] L32 = 256'h0;
parameter [255:0] L33 = 256'h0;
parameter [255:0] L34 = 256'h0;
parameter [255:0] L35 = 256'h0;
parameter [255:0] L36 = 256'h0;
parameter [255:0] L37 = 256'h0;
parameter [255:0] L38 = 256'h0;
parameter [255:0] L39 = 256'h0;
parameter [255:0] L3A = 256'h0;
parameter [255:0] L3B = 256'h0;
parameter [255:0] L3C = 256'h0;
parameter [255:0] L3D = 256'h0;
parameter [255:0] L3E = 256'h0;
parameter [255:0] L3F = 256'h0;
parameter [255:0] A0 = 256'h0;
parameter [255:0] A1 = 256'h0;
parameter [255:0] A2 = 256'h0;
always @ (posedge clk) begin
end
endmodule
|
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= {DATA_WIDTH{1'b0}};
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= {DATA_WIDTH{1'b0}};
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= {DATA_WIDTH{1'b0}};
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= {DATA_WIDTH{1'b0}};
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
module t (clk);
input clk;
integer cyc; initial cyc=1;
integer sum;
integer cpre;
always @ (posedge clk) begin
if (cyc!=0) begin
cpre = cyc;
cyc <= cyc + 1;
if (cyc==1) begin
if (mlog2(32'd0) != 32'd0) $stop;
if (mlog2(32'd1) != 32'd0) $stop;
if (mlog2(32'd3) != 32'd2) $stop;
sum <= 32'd0;
end
else if (cyc<90) begin
// (cyc) so if we trash the variable things will get upset.
sum <= mlog2(cyc) + sum * 32'd42;
if (cpre != cyc) $stop;
end
else if (cyc==90) begin
if (sum !== 32'h0f12bb51) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
function integer mlog2;
input [31:0] value;
integer i;
begin
if(value < 32'd1) begin
mlog2 = 0;
end
else begin
value = value - 32'd1;
mlog2 = 0;
for(i=0;i<32;i=i+1) begin
if(value > 32'd0) begin
mlog2 = mlog2 + 1;
end
value = value >> 1;
end
end
end
endfunction
endmodule
|
module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'h966e272fd829e672
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module's undeclared outputs)
reg [31:0] out;
// End of automatics
`ifdef verilator
`define dontOptimize $c1("1")
`else
`define dontOptimize 1'b1
`endif
always @(posedge clk) begin
out <= in;
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (in[0])
out <= ~in;
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [15:0] l;
reg [49:0] q;
reg [79:0] w;
reg [4:0] lc;
reg lo;
reg l0;
reg [5:0] qc;
reg qo;
reg q0;
reg [6:0] wc;
reg wo;
reg w0;
always @* begin
lc = $countones(l);
lo = $onehot(l);
l0 = $onehot0(l);
wc = $countones(w);
wo = $onehot(w);
w0 = $onehot0(w);
qc = $countones(q);
qo = $onehot(q);
q0 = $onehot0(q);
end
integer cyc; initial cyc=1;
integer cyc_com;
always_comb begin
cyc_com = cyc;
end
integer cyc_d1;
always_ff @ (posedge clk) begin
cyc_d1 <= cyc_com;
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %d %x %x %x %d %x %x %x %d %x %x\n",
// cyc, l, lc, lo, l0, q,qc,qo,q0, w,wc,wo,w0);
if (cyc_com != cyc_com) $stop;
if (cyc_d1 != cyc-1) $stop;
if (cyc==0) begin
// Constification check
if ($countones(32'b11001011101) != 7) $stop;
if ($countones(32'b0) != 0) $stop;
if ($isunknown(32'b11101x11111) != 1) $stop;
if ($isunknown(32'b11101011111) != 0) $stop;
if ($isunknown(32'b10zzzzzzzzz) != 0) $stop;
if ($bits(0) != 32'd32) $stop;
if ($bits(lc) != 5) $stop;
if ($onehot(32'b00000001000000) != 1'b1) $stop;
if ($onehot(32'b00001001000000) != 1'b0) $stop;
if ($onehot(32'b0) != 1'b0) $stop;
if ($onehot0(32'b00000001000000) != 1'b1) $stop;
if ($onehot0(32'b00001001000000) != 1'b0) $stop;
if ($onehot0(32'b0) != 1'b1) $stop;
end
if (cyc==1) begin
l <= 16'b0;
q <= 50'h0;
w <= 80'h0;
end
if (cyc==2) begin
l <= ~16'b0;
q <= ~50'h0;
w <= ~80'h0;
//
if ({lc,lo,l0} != {5'd0,1'b0,1'b1}) $stop;
if ({qc,qo,q0} != {6'd0,1'b0,1'b1}) $stop;
if ({wc,wo,w0} != {7'd0,1'b0,1'b1}) $stop;
end
if (cyc==3) begin
l <= 16'b0010110010110111;
q <= 50'h01_1111_0001;
w <= 80'h0100_0000_0f00_00f0_0000;
//
if ({lc,lo,l0} != {5'd16,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd50,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd80,1'b0,1'b0}) $stop;
end
if (cyc==4) begin
l <= 16'b0000010000000000;
q <= 50'h1_0000_0000;
w <= 80'h010_00000000_00000000;
//
if ({lc,lo,l0} != {5'd9,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd6,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd9,1'b0,1'b0}) $stop;
end
if (cyc==5) begin
l <= 16'b0000000100000000;
q <= 50'h8000_0000_0000;
w <= 80'h10_00000000_00000000;
//
if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop;
if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop;
if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop;
end
if (cyc==6) begin
l <= 16'b0000100100000000;
q <= 50'h01_00000100;
w <= 80'h01_00000100_00000000;
//
if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop;
if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop;
if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop;
end
if (cyc==7) begin
//
if ({lc,lo,l0} != {5'd2,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd2,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd2,1'b0,1'b0}) $stop;
end
if (cyc==8) begin
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
final begin
$write("Goodbye world, at cycle %0d\n", cyc);
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [15:0] l;
reg [49:0] q;
reg [79:0] w;
reg [4:0] lc;
reg lo;
reg l0;
reg [5:0] qc;
reg qo;
reg q0;
reg [6:0] wc;
reg wo;
reg w0;
always @* begin
lc = $countones(l);
lo = $onehot(l);
l0 = $onehot0(l);
wc = $countones(w);
wo = $onehot(w);
w0 = $onehot0(w);
qc = $countones(q);
qo = $onehot(q);
q0 = $onehot0(q);
end
integer cyc; initial cyc=1;
integer cyc_com;
always_comb begin
cyc_com = cyc;
end
integer cyc_d1;
always_ff @ (posedge clk) begin
cyc_d1 <= cyc_com;
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %d %x %x %x %d %x %x %x %d %x %x\n",
// cyc, l, lc, lo, l0, q,qc,qo,q0, w,wc,wo,w0);
if (cyc_com != cyc_com) $stop;
if (cyc_d1 != cyc-1) $stop;
if (cyc==0) begin
// Constification check
if ($countones(32'b11001011101) != 7) $stop;
if ($countones(32'b0) != 0) $stop;
if ($isunknown(32'b11101x11111) != 1) $stop;
if ($isunknown(32'b11101011111) != 0) $stop;
if ($isunknown(32'b10zzzzzzzzz) != 0) $stop;
if ($bits(0) != 32'd32) $stop;
if ($bits(lc) != 5) $stop;
if ($onehot(32'b00000001000000) != 1'b1) $stop;
if ($onehot(32'b00001001000000) != 1'b0) $stop;
if ($onehot(32'b0) != 1'b0) $stop;
if ($onehot0(32'b00000001000000) != 1'b1) $stop;
if ($onehot0(32'b00001001000000) != 1'b0) $stop;
if ($onehot0(32'b0) != 1'b1) $stop;
end
if (cyc==1) begin
l <= 16'b0;
q <= 50'h0;
w <= 80'h0;
end
if (cyc==2) begin
l <= ~16'b0;
q <= ~50'h0;
w <= ~80'h0;
//
if ({lc,lo,l0} != {5'd0,1'b0,1'b1}) $stop;
if ({qc,qo,q0} != {6'd0,1'b0,1'b1}) $stop;
if ({wc,wo,w0} != {7'd0,1'b0,1'b1}) $stop;
end
if (cyc==3) begin
l <= 16'b0010110010110111;
q <= 50'h01_1111_0001;
w <= 80'h0100_0000_0f00_00f0_0000;
//
if ({lc,lo,l0} != {5'd16,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd50,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd80,1'b0,1'b0}) $stop;
end
if (cyc==4) begin
l <= 16'b0000010000000000;
q <= 50'h1_0000_0000;
w <= 80'h010_00000000_00000000;
//
if ({lc,lo,l0} != {5'd9,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd6,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd9,1'b0,1'b0}) $stop;
end
if (cyc==5) begin
l <= 16'b0000000100000000;
q <= 50'h8000_0000_0000;
w <= 80'h10_00000000_00000000;
//
if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop;
if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop;
if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop;
end
if (cyc==6) begin
l <= 16'b0000100100000000;
q <= 50'h01_00000100;
w <= 80'h01_00000100_00000000;
//
if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop;
if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop;
if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop;
end
if (cyc==7) begin
//
if ({lc,lo,l0} != {5'd2,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd2,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd2,1'b0,1'b0}) $stop;
end
if (cyc==8) begin
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
final begin
$write("Goodbye world, at cycle %0d\n", cyc);
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// Life analysis checks
reg [15:0] life;
// Ding case
reg [7:0] din;
reg [15:0] fixin;
always @* begin
fixin = {din[7:0],din[7:0]};
case (din[1:0])
2'b00: begin
fixin = {fixin[14:0], 1'b1};
if (cyc==101) $display("Prevent ?: optimization a");
end
2'b01: begin
fixin = {fixin[13:0], 2'b11};
if (cyc==101) $display("Prevent ?: optimization b");
end
2'b10: begin
fixin = {fixin[12:0], 3'b111};
if (cyc==101) $display("Prevent ?: optimization c");
end
2'b11: begin
fixin = {fixin[11:0], 4'b1111};
if (cyc==101) $display("Prevent ?: optimization d");
end
endcase
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
life = 16'h8000; // Dropped
life = 16'h0010; // Used below
if (life != 16'h0010) $stop;
//
life = 16'h0020; // Used below
if ($time < 10000)
if (life != 16'h0020) $stop;
//
life = 16'h8000; // Dropped
if ($time > 100000) begin
if ($time != 0) $stop; // Prevent conversion to ?:
life = 16'h1030;
end
else
life = 16'h0030;
if (life != 16'h0030) $stop;
//
life = 16'h0040; // Not dropped, no else below
if ($time > 100000)
life = 16'h1040;
if (life != 16'h0040) $stop;
//
life = 16'h8000; // Dropped
if ($time > 100000) begin
life = 16'h1050;
if (life != 0) $stop; // Ignored, as set is first
end
else begin
if ($time > 100010)
life = 16'h1050;
else life = 16'h0050;
end
if (life != 16'h0050) $stop;
end
if (cyc==2) begin
din <= 8'haa;
end
if (cyc==3) begin
din <= 8'hfb;
if (fixin != 16'h5557) $stop;
end
if (cyc==4) begin
din <= 8'h5c;
if (fixin != 16'hbfbf) $stop;
end
if (cyc==5) begin
din <= 8'hed;
if (fixin != 16'hb8b9) $stop;
end
if (cyc==6) begin
if (fixin != 16'hb7b7) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module t (clk);
// verilator lint_off WIDTH
parameter WIDTH = 16; // Must be a power of 2
parameter WIDTH_LOG2 = 4; // set to log2(WIDTH)
parameter USE_BS = 1; // set to 1 for enable
input clk;
function [`VECTOR_RANGE] func_tree_left;
input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector
reg [`VECTOR_RANGE] flip;
begin
flip = 'd0;
func_tree_left = flip;
end
endfunction
reg [WIDTH-1:0] a; // value to be shifted
reg [WIDTH-1:0] tree_left;
always @(a) begin : barrel_shift
tree_left = func_tree_left (a);
end // barrel_shift
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a = 5;
end
if (cyc==2) begin
$display ("%x\n",tree_left);
//if (tree_left != 'd15) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module t (clk);
// verilator lint_off WIDTH
parameter WIDTH = 16; // Must be a power of 2
parameter WIDTH_LOG2 = 4; // set to log2(WIDTH)
parameter USE_BS = 1; // set to 1 for enable
input clk;
function [`VECTOR_RANGE] func_tree_left;
input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector
reg [`VECTOR_RANGE] flip;
begin
flip = 'd0;
func_tree_left = flip;
end
endfunction
reg [WIDTH-1:0] a; // value to be shifted
reg [WIDTH-1:0] tree_left;
always @(a) begin : barrel_shift
tree_left = func_tree_left (a);
end // barrel_shift
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a = 5;
end
if (cyc==2) begin
$display ("%x\n",tree_left);
//if (tree_left != 'd15) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module t (clk);
// verilator lint_off WIDTH
parameter WIDTH = 16; // Must be a power of 2
parameter WIDTH_LOG2 = 4; // set to log2(WIDTH)
parameter USE_BS = 1; // set to 1 for enable
input clk;
function [`VECTOR_RANGE] func_tree_left;
input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector
reg [`VECTOR_RANGE] flip;
begin
flip = 'd0;
func_tree_left = flip;
end
endfunction
reg [WIDTH-1:0] a; // value to be shifted
reg [WIDTH-1:0] tree_left;
always @(a) begin : barrel_shift
tree_left = func_tree_left (a);
end // barrel_shift
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a = 5;
end
if (cyc==2) begin
$display ("%x\n",tree_left);
//if (tree_left != 'd15) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module's undeclared outputs)
reg [9:0] outa;
// End of automatics
// =============================
// Created from perl
// for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); };
always @(/*AS*/index) begin
case (index[7:0])
`ifdef VERILATOR // Harder test
8'h00: begin outa = $c("0"); end // Makes whole table non-optimizable
`else
8'h00: begin outa = 10'h0; end
`endif
8'h01: begin outa = 10'h318; end
8'h02: begin outa = 10'h29f; end
8'h03: begin outa = 10'h392; end
8'h04: begin outa = 10'h1ef; end
8'h05: begin outa = 10'h06c; end
8'h06: begin outa = 10'h29f; end
8'h07: begin outa = 10'h29a; end
8'h08: begin outa = 10'h3ce; end
8'h09: begin outa = 10'h37c; end
8'h0a: begin outa = 10'h058; end
8'h0b: begin outa = 10'h3b2; end
8'h0c: begin outa = 10'h36f; end
8'h0d: begin outa = 10'h2c5; end
8'h0e: begin outa = 10'h23a; end
8'h0f: begin outa = 10'h222; end
8'h10: begin outa = 10'h328; end
8'h11: begin outa = 10'h3c3; end
8'h12: begin outa = 10'h12c; end
8'h13: begin outa = 10'h1d0; end
8'h14: begin outa = 10'h3ff; end
8'h15: begin outa = 10'h115; end
8'h16: begin outa = 10'h3ba; end
8'h17: begin outa = 10'h3ba; end
8'h18: begin outa = 10'h10d; end
8'h19: begin outa = 10'h13b; end
8'h1a: begin outa = 10'h0a0; end
8'h1b: begin outa = 10'h264; end
8'h1c: begin outa = 10'h3a2; end
8'h1d: begin outa = 10'h07c; end
8'h1e: begin outa = 10'h291; end
8'h1f: begin outa = 10'h1d1; end
8'h20: begin outa = 10'h354; end
8'h21: begin outa = 10'h0c0; end
8'h22: begin outa = 10'h191; end
8'h23: begin outa = 10'h379; end
8'h24: begin outa = 10'h073; end
8'h25: begin outa = 10'h2fd; end
8'h26: begin outa = 10'h2e0; end
8'h27: begin outa = 10'h337; end
8'h28: begin outa = 10'h2c7; end
8'h29: begin outa = 10'h19e; end
8'h2a: begin outa = 10'h107; end
8'h2b: begin outa = 10'h06a; end
8'h2c: begin outa = 10'h1c7; end
8'h2d: begin outa = 10'h107; end
8'h2e: begin outa = 10'h0cf; end
8'h2f: begin outa = 10'h009; end
8'h30: begin outa = 10'h09d; end
8'h31: begin outa = 10'h28e; end
8'h32: begin outa = 10'h010; end
8'h33: begin outa = 10'h1e0; end
8'h34: begin outa = 10'h079; end
8'h35: begin outa = 10'h13e; end
8'h36: begin outa = 10'h282; end
8'h37: begin outa = 10'h21c; end
8'h38: begin outa = 10'h148; end
8'h39: begin outa = 10'h3c0; end
8'h3a: begin outa = 10'h176; end
8'h3b: begin outa = 10'h3fc; end
8'h3c: begin outa = 10'h295; end
8'h3d: begin outa = 10'h113; end
8'h3e: begin outa = 10'h354; end
8'h3f: begin outa = 10'h0db; end
8'h40: begin outa = 10'h238; end
8'h41: begin outa = 10'h12b; end
8'h42: begin outa = 10'h1dc; end
8'h43: begin outa = 10'h137; end
8'h44: begin outa = 10'h1e2; end
8'h45: begin outa = 10'h3d5; end
8'h46: begin outa = 10'h30c; end
8'h47: begin outa = 10'h298; end
8'h48: begin outa = 10'h080; end
8'h49: begin outa = 10'h35a; end
8'h4a: begin outa = 10'h01b; end
8'h4b: begin outa = 10'h0a3; end
8'h4c: begin outa = 10'h0b3; end
8'h4d: begin outa = 10'h17a; end
8'h4e: begin outa = 10'h3ae; end
8'h4f: begin outa = 10'h078; end
8'h50: begin outa = 10'h322; end
8'h51: begin outa = 10'h213; end
8'h52: begin outa = 10'h11a; end
8'h53: begin outa = 10'h1a7; end
8'h54: begin outa = 10'h35a; end
8'h55: begin outa = 10'h233; end
8'h56: begin outa = 10'h01d; end
8'h57: begin outa = 10'h2d5; end
8'h58: begin outa = 10'h1a0; end
8'h59: begin outa = 10'h3d0; end
8'h5a: begin outa = 10'h181; end
8'h5b: begin outa = 10'h219; end
8'h5c: begin outa = 10'h26a; end
8'h5d: begin outa = 10'h050; end
8'h5e: begin outa = 10'h189; end
8'h5f: begin outa = 10'h1eb; end
8'h60: begin outa = 10'h224; end
8'h61: begin outa = 10'h2fe; end
8'h62: begin outa = 10'h0ae; end
8'h63: begin outa = 10'h1cd; end
8'h64: begin outa = 10'h273; end
8'h65: begin outa = 10'h268; end
8'h66: begin outa = 10'h111; end
8'h67: begin outa = 10'h1f9; end
8'h68: begin outa = 10'h232; end
8'h69: begin outa = 10'h255; end
8'h6a: begin outa = 10'h34c; end
8'h6b: begin outa = 10'h049; end
8'h6c: begin outa = 10'h197; end
8'h6d: begin outa = 10'h0fe; end
8'h6e: begin outa = 10'h253; end
8'h6f: begin outa = 10'h2de; end
8'h70: begin outa = 10'h13b; end
8'h71: begin outa = 10'h040; end
8'h72: begin outa = 10'h0b4; end
8'h73: begin outa = 10'h233; end
8'h74: begin outa = 10'h198; end
8'h75: begin outa = 10'h018; end
8'h76: begin outa = 10'h2f7; end
8'h77: begin outa = 10'h134; end
8'h78: begin outa = 10'h1ca; end
8'h79: begin outa = 10'h286; end
8'h7a: begin outa = 10'h0e6; end
8'h7b: begin outa = 10'h064; end
8'h7c: begin outa = 10'h257; end
8'h7d: begin outa = 10'h31a; end
8'h7e: begin outa = 10'h247; end
8'h7f: begin outa = 10'h299; end
8'h80: begin outa = 10'h02c; end
8'h81: begin outa = 10'h2bb; end
8'h82: begin outa = 10'h180; end
8'h83: begin outa = 10'h245; end
8'h84: begin outa = 10'h0da; end
8'h85: begin outa = 10'h367; end
8'h86: begin outa = 10'h304; end
8'h87: begin outa = 10'h38b; end
8'h88: begin outa = 10'h09f; end
8'h89: begin outa = 10'h1f0; end
8'h8a: begin outa = 10'h281; end
8'h8b: begin outa = 10'h019; end
8'h8c: begin outa = 10'h1f2; end
8'h8d: begin outa = 10'h0b1; end
8'h8e: begin outa = 10'h058; end
8'h8f: begin outa = 10'h39b; end
8'h90: begin outa = 10'h2ec; end
8'h91: begin outa = 10'h250; end
8'h92: begin outa = 10'h3f4; end
8'h93: begin outa = 10'h057; end
8'h94: begin outa = 10'h18f; end
8'h95: begin outa = 10'h105; end
8'h96: begin outa = 10'h1ae; end
8'h97: begin outa = 10'h04e; end
8'h98: begin outa = 10'h240; end
8'h99: begin outa = 10'h3e4; end
8'h9a: begin outa = 10'h3c6; end
8'h9b: begin outa = 10'h109; end
8'h9c: begin outa = 10'h073; end
8'h9d: begin outa = 10'h19f; end
8'h9e: begin outa = 10'h3b8; end
8'h9f: begin outa = 10'h00e; end
8'ha0: begin outa = 10'h1b3; end
8'ha1: begin outa = 10'h2bd; end
8'ha2: begin outa = 10'h324; end
8'ha3: begin outa = 10'h343; end
8'ha4: begin outa = 10'h1c9; end
8'ha5: begin outa = 10'h185; end
8'ha6: begin outa = 10'h37a; end
8'ha7: begin outa = 10'h0e0; end
8'ha8: begin outa = 10'h0a3; end
8'ha9: begin outa = 10'h019; end
8'haa: begin outa = 10'h099; end
8'hab: begin outa = 10'h376; end
8'hac: begin outa = 10'h077; end
8'had: begin outa = 10'h2b1; end
8'hae: begin outa = 10'h27f; end
8'haf: begin outa = 10'h265; end
8'hb0: begin outa = 10'h156; end
8'hb1: begin outa = 10'h1ce; end
8'hb2: begin outa = 10'h008; end
8'hb3: begin outa = 10'h12e; end
8'hb4: begin outa = 10'h199; end
8'hb5: begin outa = 10'h330; end
8'hb6: begin outa = 10'h1ab; end
8'hb7: begin outa = 10'h3bd; end
8'hb8: begin outa = 10'h0ca; end
8'hb9: begin outa = 10'h367; end
8'hba: begin outa = 10'h334; end
8'hbb: begin outa = 10'h040; end
8'hbc: begin outa = 10'h1a7; end
8'hbd: begin outa = 10'h036; end
8'hbe: begin outa = 10'h223; end
8'hbf: begin outa = 10'h075; end
8'hc0: begin outa = 10'h3c4; end
8'hc1: begin outa = 10'h2cc; end
8'hc2: begin outa = 10'h123; end
8'hc3: begin outa = 10'h3fd; end
8'hc4: begin outa = 10'h11e; end
8'hc5: begin outa = 10'h27c; end
8'hc6: begin outa = 10'h1e2; end
8'hc7: begin outa = 10'h377; end
8'hc8: begin outa = 10'h33a; end
8'hc9: begin outa = 10'h32d; end
8'hca: begin outa = 10'h014; end
8'hcb: begin outa = 10'h332; end
8'hcc: begin outa = 10'h359; end
8'hcd: begin outa = 10'h0a4; end
8'hce: begin outa = 10'h348; end
8'hcf: begin outa = 10'h04b; end
8'hd0: begin outa = 10'h147; end
8'hd1: begin outa = 10'h026; end
8'hd2: begin outa = 10'h103; end
8'hd3: begin outa = 10'h106; end
8'hd4: begin outa = 10'h35a; end
8'hd5: begin outa = 10'h254; end
8'hd6: begin outa = 10'h0cd; end
8'hd7: begin outa = 10'h17c; end
8'hd8: begin outa = 10'h37e; end
8'hd9: begin outa = 10'h0a9; end
8'hda: begin outa = 10'h0fe; end
8'hdb: begin outa = 10'h3c0; end
8'hdc: begin outa = 10'h1d9; end
8'hdd: begin outa = 10'h10e; end
8'hde: begin outa = 10'h394; end
8'hdf: begin outa = 10'h316; end
8'he0: begin outa = 10'h05b; end
8'he1: begin outa = 10'h126; end
8'he2: begin outa = 10'h369; end
8'he3: begin outa = 10'h291; end
8'he4: begin outa = 10'h2ca; end
8'he5: begin outa = 10'h25b; end
8'he6: begin outa = 10'h106; end
8'he7: begin outa = 10'h172; end
8'he8: begin outa = 10'h2f7; end
8'he9: begin outa = 10'h2d3; end
8'hea: begin outa = 10'h182; end
8'heb: begin outa = 10'h327; end
8'hec: begin outa = 10'h1d0; end
8'hed: begin outa = 10'h204; end
8'hee: begin outa = 10'h11f; end
8'hef: begin outa = 10'h365; end
8'hf0: begin outa = 10'h2c2; end
8'hf1: begin outa = 10'h2b5; end
8'hf2: begin outa = 10'h1f8; end
8'hf3: begin outa = 10'h2a7; end
8'hf4: begin outa = 10'h1be; end
8'hf5: begin outa = 10'h25e; end
8'hf6: begin outa = 10'h032; end
8'hf7: begin outa = 10'h2ef; end
8'hf8: begin outa = 10'h02f; end
8'hf9: begin outa = 10'h201; end
8'hfa: begin outa = 10'h054; end
8'hfb: begin outa = 10'h013; end
8'hfc: begin outa = 10'h249; end
8'hfd: begin outa = 10'h09a; end
8'hfe: begin outa = 10'h012; end
8'hff: begin outa = 10'h114; end
endcase
end
endmodule
|
module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h3e3a62edb61f8c7f
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [31:0] in;
output [31:0] out;
genvar i;
generate
for (i=0; i<16; i=i+1) begin : gblk
assign out[i*2+1:i*2] = in[(30-i*2)+1:(30-i*2)];
end
endgenerate
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [127:0] i;
wire [127:0] q1;
wire [127:0] q32;
wire [127:0] q64;
wire [63:0] q64_low;
assign q1 = {
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4],
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1],
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
assign q64[127:64] = {
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4],
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]};
assign q64[63:0] = {
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
assign q64_low = {
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
assign q32[127:96] = {
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4]};
assign q32[95:64] = {
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]};
assign q32[63:32] = {
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2]};
assign q32[31:0] = {
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x %x\n", q1, i);
`endif
if (cyc==1) begin
i <= 128'hed388e646c843d35de489bab2413d770;
end
if (cyc==2) begin
i <= 128'h0e17c88f3d5fe51a982646c8e2bd68c3;
if (q1 != 128'h06f0b17c6551e269e3ab07723b26fb10) $stop;
if (q1 != q32) $stop;
if (q1 != q64) $stop;
if (q1[63:0] != q64_low) $stop;
end
if (cyc==3) begin
i <= 128'he236ddfddddbdad20a48e039c9f395b8;
if (q1 != 128'h8c6f018c8a992c979a3e7859f29ac36d) $stop;
if (q1 != q32) $stop;
if (q1 != q64) $stop;
if (q1[63:0] != q64_low) $stop;
end
if (cyc==4) begin
i <= 128'h45e0eb7642b148537491f3da147e7f26;
if (q1 != 128'hf45fc07e4fa8524cf9571425f17f9ad7) $stop;
if (q1 != q32) $stop;
if (q1 != q64) $stop;
if (q1[63:0] != q64_low) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [127:0] i;
wire [127:0] q1;
wire [127:0] q32;
wire [127:0] q64;
wire [63:0] q64_low;
assign q1 = {
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4],
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1],
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
assign q64[127:64] = {
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4],
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]};
assign q64[63:0] = {
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
assign q64_low = {
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
assign q32[127:96] = {
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4]};
assign q32[95:64] = {
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]};
assign q32[63:32] = {
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2]};
assign q32[31:0] = {
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x %x\n", q1, i);
`endif
if (cyc==1) begin
i <= 128'hed388e646c843d35de489bab2413d770;
end
if (cyc==2) begin
i <= 128'h0e17c88f3d5fe51a982646c8e2bd68c3;
if (q1 != 128'h06f0b17c6551e269e3ab07723b26fb10) $stop;
if (q1 != q32) $stop;
if (q1 != q64) $stop;
if (q1[63:0] != q64_low) $stop;
end
if (cyc==3) begin
i <= 128'he236ddfddddbdad20a48e039c9f395b8;
if (q1 != 128'h8c6f018c8a992c979a3e7859f29ac36d) $stop;
if (q1 != q32) $stop;
if (q1 != q64) $stop;
if (q1[63:0] != q64_low) $stop;
end
if (cyc==4) begin
i <= 128'h45e0eb7642b148537491f3da147e7f26;
if (q1 != 128'hf45fc07e4fa8524cf9571425f17f9ad7) $stop;
if (q1 != q32) $stop;
if (q1 != q64) $stop;
if (q1[63:0] != q64_low) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [127:0] i;
wire [127:0] q1;
wire [127:0] q32;
wire [127:0] q64;
wire [63:0] q64_low;
assign q1 = {
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4],
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1],
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
assign q64[127:64] = {
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4],
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]};
assign q64[63:0] = {
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
assign q64_low = {
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
assign q32[127:96] = {
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4]};
assign q32[95:64] = {
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]};
assign q32[63:32] = {
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2]};
assign q32[31:0] = {
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x %x\n", q1, i);
`endif
if (cyc==1) begin
i <= 128'hed388e646c843d35de489bab2413d770;
end
if (cyc==2) begin
i <= 128'h0e17c88f3d5fe51a982646c8e2bd68c3;
if (q1 != 128'h06f0b17c6551e269e3ab07723b26fb10) $stop;
if (q1 != q32) $stop;
if (q1 != q64) $stop;
if (q1[63:0] != q64_low) $stop;
end
if (cyc==3) begin
i <= 128'he236ddfddddbdad20a48e039c9f395b8;
if (q1 != 128'h8c6f018c8a992c979a3e7859f29ac36d) $stop;
if (q1 != q32) $stop;
if (q1 != q64) $stop;
if (q1[63:0] != q64_low) $stop;
end
if (cyc==4) begin
i <= 128'h45e0eb7642b148537491f3da147e7f26;
if (q1 != 128'hf45fc07e4fa8524cf9571425f17f9ad7) $stop;
if (q1 != q32) $stop;
if (q1 != q64) $stop;
if (q1[63:0] != q64_low) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [63:0] d;
reg [31:0] c;
wire [31:0] q = crc (d, c);
reg [31:0] q_r;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
q_r <= q;
c <= q;
d <= {d[62:0], ^d[63:48]};
//$write("%d crc(%x,%x)=%x\n", cyc, d, c, q);
if (cyc==1) begin
// Assign inputs randomly
q_r <= 32'h12345678;
c <= 32'h12345678;
d <= 64'hffffffff_ffffffff;
end
if (cyc==2) begin
d <= 64'hffffffff_ffffffff;
end
if (cyc==3) begin
d <= 64'hffffffff_ffffffff;
end
if (cyc==4) begin
d <= 64'h50183721_81a04b1a;
end
if (cyc==5) begin
end
if (cyc==9) begin
if (q !== 32'h38295e96) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
function [31:0] crc;
input [63:0] di;
input [31:0] ci;
reg [63:0] drev;
begin
drev = reverse(di);
crc = newcrc(drev, ci);
end
endfunction
function [63:0] reverse;
input [63:0] di;
integer i;
begin
reverse = 64'b0;
for (i=0; i<64; i=i+1) reverse[i] = di[63-i];
end
endfunction
function [31:0] newcrc;
input [63:0] D;
input [31:0] C;
reg [31:0] N;
reg [31:0] DT;
begin
N = 32'b0;
// Note this isn't a real CRC code; it's been munged for privacy
N[0] = D[59]^D[53]^D[52]^D[49]^D[44]^D[41]^D[40]^D[39]^D[37]^D[32]^D[29]^D[26]^D[22]^D[21]^D[20]^D[16]^D[15]^D[14]^D[9]^D[7]^D[0]
^C[29]^C[27]^C[24]^C[23]^C[22]^C[21]^C[19]^C[15]^C[13]^C[10]^C[8]^C[3]^C[1];
N[1] = D[61]^D[57]^D[51]^D[47]^D[43]^D[37]^D[35]^D[32]^D[28]^D[24]^D[22]^D[21]^D[20]^D[16]^D[12]^D[11]^D[10]^D[8]^D[7]^D[6]^D[1]^D[0]
^C[30]^C[27]^C[26]^C[20]^C[16]^C[14]^C[13]^C[11]^C[10]^C[8]^C[5]^C[0];
N[2] = D[63]^D[62]^D[61]^D[60]^D[55]^D[54]^D[52]^D[44]^D[43]^D[42]^D[37]^D[34]^D[33]^D[29]^D[28]^D[25]^D[24]^D[23]^D[22]^D[18]^D[16]^D[15]^D[13]^D[12]^D[11]
^C[31]^C[30]^C[27]^C[22]^C[21]^C[18]^C[15]^C[12]^C[11]^C[10]^C[7];
N[3] = D[62]^D[54]^D[50]^D[47]^D[46]^D[38]^D[36]^D[35]^D[34]^D[33]^D[32]^D[30]^D[27]^D[25]^D[21]^D[20]^D[19]^D[17]^D[15]^D[11]^D[8]^D[5]^D[3]^D[1]^D[0]
^C[28]^C[25]^C[24]^C[13]^C[11]^C[9]^C[8]^C[7]^C[3]^C[1];
N[4] = D[57]^D[54]^D[53]^D[52]^D[45]^D[44]^D[43]^D[39]^D[37]^D[34]^D[33]^D[32]^D[31]^D[28]^D[24]^D[23]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[1]^D[0]
^C[30]^C[24]^C[20]^C[16]^C[14]^C[11]^C[8]^C[7]^C[6]^C[5]^C[2];
N[5] = D[58]^D[57]^D[50]^D[49]^D[48]^D[47]^D[43]^D[39]^D[29]^D[26]^D[23]^D[22]^D[20]^D[18]^D[14]^D[10]^D[9]^D[6]^D[5]^D[4]^D[1]
^C[27]^C[24]^C[20]^C[19]^C[18]^C[14]^C[13]^C[12]^C[11]^C[8]^C[7]^C[1];
N[6] = D[63]^D[62]^D[61]^D[57]^D[51]^D[50]^D[47]^D[38]^D[37]^D[34]^D[30]^D[28]^D[27]^D[25]^D[21]^D[16]^D[15]^D[10]^D[9]^D[6]^D[5]^D[2]^D[1]
^C[31]^C[27]^C[25]^C[16]^C[13]^C[9]^C[8]^C[7]^C[0];
N[7] = ^D[62]^D[61]^D[59]^D[54]^D[52]^D[51]^D[49]^D[46]^D[45]^D[42]^D[41]^D[38]^D[35]^D[29]^D[26]^D[24]^D[15]^D[12]^D[11]^D[9]^D[2]^D[0]
^C[28]^C[27]^C[26]^C[20]^C[19]^C[18]^C[15]^C[12]^C[7]^C[4];
N[8] = D[62]^D[61]^D[60]^D[59]^D[52]^D[50]^D[48]^D[47]^D[46]^D[45]^D[44]^D[42]^D[41]^D[40]^D[30]^D[24]^D[23]^D[22]^D[19]^D[17]^D[11]^D[10]^D[7]^D[6]^D[2]
^C[31]^C[29]^C[27]^C[22]^C[21]^C[19]^C[17]^C[11]^C[9]^C[7]^C[6];
N[9] = D[62]^D[59]^D[58]^D[57]^D[54]^D[51]^D[50]^D[43]^D[41]^D[39]^D[28]^D[25]^D[24]^D[23]^D[22]^D[21]^D[18]^D[16]^D[15]^D[7]
^C[30]^C[29]^C[27]^C[25]^C[23]^C[22]^C[13]^C[12]^C[7]^C[6]^C[5]^C[1];
N[10] = D[61]^D[60]^D[58]^D[56]^D[54]^D[53]^D[51]^D[48]^D[46]^D[43]^D[42]^D[38]^D[37]^D[35]^D[33]^D[31]^D[30]^D[27]^D[26]^D[24]^D[19]^D[10]^D[8]^D[6]^D[1]
^C[31]^C[30]^C[26]^C[25]^C[24]^C[21]^C[16]^C[12]^C[3]^C[2];
N[11] = D[59]^D[57]^D[56]^D[50]^D[49]^D[48]^D[47]^D[46]^D[45]^D[42]^D[41]^D[40]^D[33]^D[32]^D[30]^D[25]^D[21]^D[15]^D[14]^D[13]^D[12]^D[11]^D[5]^D[1]
^C[27]^C[25]^C[24]^C[21]^C[16]^C[12]^C[7]^C[3]^C[2]^C[1];
N[12] = D[62]^D[61]^D[59]^D[58]^D[56]^D[55]^D[53]^D[48]^D[47]^D[44]^D[43]^D[35]^D[31]^D[30]^D[28]^D[24]^D[23]^D[21]^D[14]^D[5]^D[2]
^C[28]^C[26]^C[25]^C[23]^C[22]^C[18]^C[16]^C[15]^C[6];
N[13] = D[63]^D[60]^D[58]^D[57]^D[55]^D[54]^D[53]^D[51]^D[47]^D[45]^D[42]^D[41]^D[38]^D[28]^D[26]^D[25]^D[22]^D[20]^D[18]^D[17]^D[15]^D[13]^D[12]^D[11]
^C[29]^C[28]^C[25]^C[22]^C[19]^C[17]^C[16]^C[15]^C[14]^C[12]^C[10]^C[9];
N[14] = D[58]^D[56]^D[55]^D[52]^D[47]^D[43]^D[41]^D[40]^D[39]^D[38]^D[30]^D[26]^D[25]^D[22]^D[19]^D[17]^D[13]^D[11]^D[10]^D[9]^D[8]^D[3]^D[2]^D[0]
^C[31]^C[28]^C[20]^C[18]^C[17]^C[16]^C[15]^C[13]^C[11]^C[4]^C[2]^C[1];
N[15] = D[63]^D[62]^D[61]^D[59]^D[58]^D[48]^D[47]^D[43]^D[42]^D[35]^D[28]^D[26]^D[25]^D[24]^D[23]^D[22]^D[21]^D[20]^D[19]^D[17]^D[11]^D[7]^D[2]
^C[30]^C[29]^C[27]^C[24]^C[20]^C[17]^C[16]^C[15]^C[11]^C[9]^C[5];
N[16] = D[60]^D[57]^D[49]^D[46]^D[45]^D[43]^D[39]^D[36]^D[32]^D[30]^D[29]^D[28]^D[27]^D[26]^D[23]^D[20]^D[19]^D[17]^D[11]^D[8]^D[5]^D[1]
^C[28]^C[26]^C[23]^C[22]^C[18]^C[16]^C[13]^C[12]^C[10]^C[9]^C[6];
N[17] = D[63]^D[62]^D[61]^D[60]^D[58]^D[54]^D[53]^D[51]^D[48]^D[42]^D[41]^D[37]^D[36]^D[34]^D[28]^D[27]^D[26]^D[24]^D[13]^D[12]^D[9]^D[7]^D[4]^D[0]
^C[31]^C[30]^C[27]^C[23]^C[20]^C[17]^C[14]^C[9]^C[6]^C[4]^C[3]^C[0];
N[18] = D[63]^D[61]^D[59]^D[56]^D[52]^D[50]^D[47]^D[42]^D[37]^D[35]^D[34]^D[31]^D[30]^D[29]^D[22]^D[19]^D[17]^D[16]^D[11]^D[9]^D[8]^D[7]
^C[26]^C[22]^C[20]^C[19]^C[16]^C[11]^C[8]^C[6]^C[5]^C[0];
N[19] = D[62]^D[60]^D[52]^D[49]^D[44]^D[43]^D[42]^D[37]^D[33]^D[32]^D[29]^D[26]^D[19]^D[17]^D[16]^D[12]^D[10]^D[7]^D[6]^D[4]^D[3]^D[2]
^C[30]^C[29]^C[26]^C[25]^C[22]^C[19]^C[14]^C[7]^C[6]^C[5]^C[2]^C[0];
N[20] = D[63]^D[58]^D[54]^D[48]^D[47]^D[40]^D[39]^D[35]^D[34]^D[32]^D[31]^D[28]^D[27]^D[25]^D[18]^D[12]^D[9]^D[7]^D[5]^D[4]^D[3]^D[2]^D[1]
^C[31]^C[29]^C[28]^C[25]^C[19]^C[18]^C[17]^C[15]^C[10]^C[9]^C[6]^C[4];
N[21] = D[61]^D[59]^D[57]^D[56]^D[53]^D[48]^D[44]^D[43]^D[41]^D[35]^D[29]^D[26]^D[25]^D[20]^D[18]^D[17]^D[16]^D[12]^D[9]^D[6]^D[5]^D[3]^D[1]
^C[30]^C[27]^C[24]^C[23]^C[22]^C[21]^C[20]^C[13]^C[9]^C[3]^C[2];
N[22] = D[63]^D[62]^D[60]^D[57]^D[53]^D[51]^D[45]^D[44]^D[42]^D[34]^D[33]^D[27]^D[20]^D[19]^D[18]^D[15]^D[10]^D[9]^D[8]^D[4]^D[3]
^C[24]^C[23]^C[18]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[9]^C[6]^C[5];
N[23] = D[58]^D[56]^D[54]^D[51]^D[47]^D[43]^D[42]^D[40]^D[37]^D[36]^D[33]^D[25]^D[23]^D[20]^D[18]^D[16]^D[15]^D[12]^D[10]^D[8]^D[7]^D[5]^D[3]
^C[31]^C[27]^C[26]^C[23]^C[21]^C[18]^C[15]^C[11]^C[10]^C[8]^C[7]^C[1];
N[24] = D[60]^D[59]^D[52]^D[50]^D[48]^D[44]^D[39]^D[36]^D[35]^D[31]^D[30]^D[28]^D[27]^D[23]^D[22]^D[21]^D[19]^D[14]^D[13]^D[12]^D[9]^D[4]^D[1]^D[0]
^C[27]^C[25]^C[23]^C[21]^C[17]^C[11]^C[10]^C[4]^C[0];
N[25] = D[61]^D[60]^D[56]^D[54]^D[51]^D[46]^D[43]^D[41]^D[40]^D[38]^D[37]^D[36]^D[29]^D[28]^D[27]^D[22]^D[17]^D[15]^D[10]^D[7]^D[4]^D[2]
^C[29]^C[28]^C[26]^C[23]^C[18]^C[14]^C[13]^C[12]^C[11]^C[9]^C[8]^C[6];
N[26] = D[63]^D[62]^D[58]^D[55]^D[54]^D[52]^D[50]^D[39]^D[37]^D[36]^D[35]^D[33]^D[31]^D[29]^D[27]^D[18]^D[14]^D[10]^D[3]^D[2]^D[0]
^C[31]^C[27]^C[26]^C[25]^C[24]^C[21]^C[13]^C[12]^C[10]^C[1];
N[27] = D[62]^D[60]^D[58]^D[56]^D[55]^D[54]^D[51]^D[44]^D[41]^D[36]^D[34]^D[32]^D[31]^D[29]^D[28]^D[27]^D[23]^D[17]^D[12]^D[11]^D[8]^D[6]^D[4]^D[2]
^C[31]^C[30]^C[28]^C[27]^C[23]^C[19]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[3];
N[28] = D[57]^D[54]^D[53]^D[51]^D[50]^D[48]^D[40]^D[38]^D[34]^D[33]^D[31]^D[30]^D[29]^D[27]^D[23]^D[21]^D[14]^D[9]^D[7]^D[6]^D[5]^D[4]^D[0]
^C[31]^C[30]^C[26]^C[24]^C[15]^C[14]^C[13]^C[7]^C[6]^C[4]^C[3]^C[0];
N[29] = D[62]^D[60]^D[55]^D[46]^D[45]^D[44]^D[43]^D[41]^D[40]^D[35]^D[33]^D[32]^D[30]^D[28]^D[25]^D[23]^D[22]^D[13]^D[8]^D[7]^D[6]^D[5]^D[4]^D[3]^D[1]^D[0]
^C[31]^C[28]^C[27]^C[18]^C[11]^C[8]^C[6]^C[4]^C[2]^C[1]^C[0];
N[30] = D[63]^D[62]^D[59]^D[58]^D[55]^D[52]^D[47]^D[44]^D[36]^D[35]^D[34]^D[31]^D[29]^D[22]^D[21]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[3]^D[2]^D[0]
^C[28]^C[25]^C[24]^C[22]^C[20]^C[15]^C[14]^C[12]^C[10]^C[9]^C[4]^C[0];
N[31] = D[61]^D[58]^D[56]^D[55]^D[54]^D[52]^D[51]^D[50]^D[49]^D[42]^D[38]^D[37]^D[36]^D[34]^D[31]^D[30]^D[27]^D[26]^D[23]^D[22]^D[21]^D[19]^D[18]^D[12]^D[0]
^C[28]^C[26]^C[24]^C[21]^C[17]^C[16]^C[14]^C[13]^C[10]^C[8]^C[2];
newcrc = N;
end
endfunction
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [63:0] d;
reg [31:0] c;
wire [31:0] q = crc (d, c);
reg [31:0] q_r;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
q_r <= q;
c <= q;
d <= {d[62:0], ^d[63:48]};
//$write("%d crc(%x,%x)=%x\n", cyc, d, c, q);
if (cyc==1) begin
// Assign inputs randomly
q_r <= 32'h12345678;
c <= 32'h12345678;
d <= 64'hffffffff_ffffffff;
end
if (cyc==2) begin
d <= 64'hffffffff_ffffffff;
end
if (cyc==3) begin
d <= 64'hffffffff_ffffffff;
end
if (cyc==4) begin
d <= 64'h50183721_81a04b1a;
end
if (cyc==5) begin
end
if (cyc==9) begin
if (q !== 32'h38295e96) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
function [31:0] crc;
input [63:0] di;
input [31:0] ci;
reg [63:0] drev;
begin
drev = reverse(di);
crc = newcrc(drev, ci);
end
endfunction
function [63:0] reverse;
input [63:0] di;
integer i;
begin
reverse = 64'b0;
for (i=0; i<64; i=i+1) reverse[i] = di[63-i];
end
endfunction
function [31:0] newcrc;
input [63:0] D;
input [31:0] C;
reg [31:0] N;
reg [31:0] DT;
begin
N = 32'b0;
// Note this isn't a real CRC code; it's been munged for privacy
N[0] = D[59]^D[53]^D[52]^D[49]^D[44]^D[41]^D[40]^D[39]^D[37]^D[32]^D[29]^D[26]^D[22]^D[21]^D[20]^D[16]^D[15]^D[14]^D[9]^D[7]^D[0]
^C[29]^C[27]^C[24]^C[23]^C[22]^C[21]^C[19]^C[15]^C[13]^C[10]^C[8]^C[3]^C[1];
N[1] = D[61]^D[57]^D[51]^D[47]^D[43]^D[37]^D[35]^D[32]^D[28]^D[24]^D[22]^D[21]^D[20]^D[16]^D[12]^D[11]^D[10]^D[8]^D[7]^D[6]^D[1]^D[0]
^C[30]^C[27]^C[26]^C[20]^C[16]^C[14]^C[13]^C[11]^C[10]^C[8]^C[5]^C[0];
N[2] = D[63]^D[62]^D[61]^D[60]^D[55]^D[54]^D[52]^D[44]^D[43]^D[42]^D[37]^D[34]^D[33]^D[29]^D[28]^D[25]^D[24]^D[23]^D[22]^D[18]^D[16]^D[15]^D[13]^D[12]^D[11]
^C[31]^C[30]^C[27]^C[22]^C[21]^C[18]^C[15]^C[12]^C[11]^C[10]^C[7];
N[3] = D[62]^D[54]^D[50]^D[47]^D[46]^D[38]^D[36]^D[35]^D[34]^D[33]^D[32]^D[30]^D[27]^D[25]^D[21]^D[20]^D[19]^D[17]^D[15]^D[11]^D[8]^D[5]^D[3]^D[1]^D[0]
^C[28]^C[25]^C[24]^C[13]^C[11]^C[9]^C[8]^C[7]^C[3]^C[1];
N[4] = D[57]^D[54]^D[53]^D[52]^D[45]^D[44]^D[43]^D[39]^D[37]^D[34]^D[33]^D[32]^D[31]^D[28]^D[24]^D[23]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[1]^D[0]
^C[30]^C[24]^C[20]^C[16]^C[14]^C[11]^C[8]^C[7]^C[6]^C[5]^C[2];
N[5] = D[58]^D[57]^D[50]^D[49]^D[48]^D[47]^D[43]^D[39]^D[29]^D[26]^D[23]^D[22]^D[20]^D[18]^D[14]^D[10]^D[9]^D[6]^D[5]^D[4]^D[1]
^C[27]^C[24]^C[20]^C[19]^C[18]^C[14]^C[13]^C[12]^C[11]^C[8]^C[7]^C[1];
N[6] = D[63]^D[62]^D[61]^D[57]^D[51]^D[50]^D[47]^D[38]^D[37]^D[34]^D[30]^D[28]^D[27]^D[25]^D[21]^D[16]^D[15]^D[10]^D[9]^D[6]^D[5]^D[2]^D[1]
^C[31]^C[27]^C[25]^C[16]^C[13]^C[9]^C[8]^C[7]^C[0];
N[7] = ^D[62]^D[61]^D[59]^D[54]^D[52]^D[51]^D[49]^D[46]^D[45]^D[42]^D[41]^D[38]^D[35]^D[29]^D[26]^D[24]^D[15]^D[12]^D[11]^D[9]^D[2]^D[0]
^C[28]^C[27]^C[26]^C[20]^C[19]^C[18]^C[15]^C[12]^C[7]^C[4];
N[8] = D[62]^D[61]^D[60]^D[59]^D[52]^D[50]^D[48]^D[47]^D[46]^D[45]^D[44]^D[42]^D[41]^D[40]^D[30]^D[24]^D[23]^D[22]^D[19]^D[17]^D[11]^D[10]^D[7]^D[6]^D[2]
^C[31]^C[29]^C[27]^C[22]^C[21]^C[19]^C[17]^C[11]^C[9]^C[7]^C[6];
N[9] = D[62]^D[59]^D[58]^D[57]^D[54]^D[51]^D[50]^D[43]^D[41]^D[39]^D[28]^D[25]^D[24]^D[23]^D[22]^D[21]^D[18]^D[16]^D[15]^D[7]
^C[30]^C[29]^C[27]^C[25]^C[23]^C[22]^C[13]^C[12]^C[7]^C[6]^C[5]^C[1];
N[10] = D[61]^D[60]^D[58]^D[56]^D[54]^D[53]^D[51]^D[48]^D[46]^D[43]^D[42]^D[38]^D[37]^D[35]^D[33]^D[31]^D[30]^D[27]^D[26]^D[24]^D[19]^D[10]^D[8]^D[6]^D[1]
^C[31]^C[30]^C[26]^C[25]^C[24]^C[21]^C[16]^C[12]^C[3]^C[2];
N[11] = D[59]^D[57]^D[56]^D[50]^D[49]^D[48]^D[47]^D[46]^D[45]^D[42]^D[41]^D[40]^D[33]^D[32]^D[30]^D[25]^D[21]^D[15]^D[14]^D[13]^D[12]^D[11]^D[5]^D[1]
^C[27]^C[25]^C[24]^C[21]^C[16]^C[12]^C[7]^C[3]^C[2]^C[1];
N[12] = D[62]^D[61]^D[59]^D[58]^D[56]^D[55]^D[53]^D[48]^D[47]^D[44]^D[43]^D[35]^D[31]^D[30]^D[28]^D[24]^D[23]^D[21]^D[14]^D[5]^D[2]
^C[28]^C[26]^C[25]^C[23]^C[22]^C[18]^C[16]^C[15]^C[6];
N[13] = D[63]^D[60]^D[58]^D[57]^D[55]^D[54]^D[53]^D[51]^D[47]^D[45]^D[42]^D[41]^D[38]^D[28]^D[26]^D[25]^D[22]^D[20]^D[18]^D[17]^D[15]^D[13]^D[12]^D[11]
^C[29]^C[28]^C[25]^C[22]^C[19]^C[17]^C[16]^C[15]^C[14]^C[12]^C[10]^C[9];
N[14] = D[58]^D[56]^D[55]^D[52]^D[47]^D[43]^D[41]^D[40]^D[39]^D[38]^D[30]^D[26]^D[25]^D[22]^D[19]^D[17]^D[13]^D[11]^D[10]^D[9]^D[8]^D[3]^D[2]^D[0]
^C[31]^C[28]^C[20]^C[18]^C[17]^C[16]^C[15]^C[13]^C[11]^C[4]^C[2]^C[1];
N[15] = D[63]^D[62]^D[61]^D[59]^D[58]^D[48]^D[47]^D[43]^D[42]^D[35]^D[28]^D[26]^D[25]^D[24]^D[23]^D[22]^D[21]^D[20]^D[19]^D[17]^D[11]^D[7]^D[2]
^C[30]^C[29]^C[27]^C[24]^C[20]^C[17]^C[16]^C[15]^C[11]^C[9]^C[5];
N[16] = D[60]^D[57]^D[49]^D[46]^D[45]^D[43]^D[39]^D[36]^D[32]^D[30]^D[29]^D[28]^D[27]^D[26]^D[23]^D[20]^D[19]^D[17]^D[11]^D[8]^D[5]^D[1]
^C[28]^C[26]^C[23]^C[22]^C[18]^C[16]^C[13]^C[12]^C[10]^C[9]^C[6];
N[17] = D[63]^D[62]^D[61]^D[60]^D[58]^D[54]^D[53]^D[51]^D[48]^D[42]^D[41]^D[37]^D[36]^D[34]^D[28]^D[27]^D[26]^D[24]^D[13]^D[12]^D[9]^D[7]^D[4]^D[0]
^C[31]^C[30]^C[27]^C[23]^C[20]^C[17]^C[14]^C[9]^C[6]^C[4]^C[3]^C[0];
N[18] = D[63]^D[61]^D[59]^D[56]^D[52]^D[50]^D[47]^D[42]^D[37]^D[35]^D[34]^D[31]^D[30]^D[29]^D[22]^D[19]^D[17]^D[16]^D[11]^D[9]^D[8]^D[7]
^C[26]^C[22]^C[20]^C[19]^C[16]^C[11]^C[8]^C[6]^C[5]^C[0];
N[19] = D[62]^D[60]^D[52]^D[49]^D[44]^D[43]^D[42]^D[37]^D[33]^D[32]^D[29]^D[26]^D[19]^D[17]^D[16]^D[12]^D[10]^D[7]^D[6]^D[4]^D[3]^D[2]
^C[30]^C[29]^C[26]^C[25]^C[22]^C[19]^C[14]^C[7]^C[6]^C[5]^C[2]^C[0];
N[20] = D[63]^D[58]^D[54]^D[48]^D[47]^D[40]^D[39]^D[35]^D[34]^D[32]^D[31]^D[28]^D[27]^D[25]^D[18]^D[12]^D[9]^D[7]^D[5]^D[4]^D[3]^D[2]^D[1]
^C[31]^C[29]^C[28]^C[25]^C[19]^C[18]^C[17]^C[15]^C[10]^C[9]^C[6]^C[4];
N[21] = D[61]^D[59]^D[57]^D[56]^D[53]^D[48]^D[44]^D[43]^D[41]^D[35]^D[29]^D[26]^D[25]^D[20]^D[18]^D[17]^D[16]^D[12]^D[9]^D[6]^D[5]^D[3]^D[1]
^C[30]^C[27]^C[24]^C[23]^C[22]^C[21]^C[20]^C[13]^C[9]^C[3]^C[2];
N[22] = D[63]^D[62]^D[60]^D[57]^D[53]^D[51]^D[45]^D[44]^D[42]^D[34]^D[33]^D[27]^D[20]^D[19]^D[18]^D[15]^D[10]^D[9]^D[8]^D[4]^D[3]
^C[24]^C[23]^C[18]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[9]^C[6]^C[5];
N[23] = D[58]^D[56]^D[54]^D[51]^D[47]^D[43]^D[42]^D[40]^D[37]^D[36]^D[33]^D[25]^D[23]^D[20]^D[18]^D[16]^D[15]^D[12]^D[10]^D[8]^D[7]^D[5]^D[3]
^C[31]^C[27]^C[26]^C[23]^C[21]^C[18]^C[15]^C[11]^C[10]^C[8]^C[7]^C[1];
N[24] = D[60]^D[59]^D[52]^D[50]^D[48]^D[44]^D[39]^D[36]^D[35]^D[31]^D[30]^D[28]^D[27]^D[23]^D[22]^D[21]^D[19]^D[14]^D[13]^D[12]^D[9]^D[4]^D[1]^D[0]
^C[27]^C[25]^C[23]^C[21]^C[17]^C[11]^C[10]^C[4]^C[0];
N[25] = D[61]^D[60]^D[56]^D[54]^D[51]^D[46]^D[43]^D[41]^D[40]^D[38]^D[37]^D[36]^D[29]^D[28]^D[27]^D[22]^D[17]^D[15]^D[10]^D[7]^D[4]^D[2]
^C[29]^C[28]^C[26]^C[23]^C[18]^C[14]^C[13]^C[12]^C[11]^C[9]^C[8]^C[6];
N[26] = D[63]^D[62]^D[58]^D[55]^D[54]^D[52]^D[50]^D[39]^D[37]^D[36]^D[35]^D[33]^D[31]^D[29]^D[27]^D[18]^D[14]^D[10]^D[3]^D[2]^D[0]
^C[31]^C[27]^C[26]^C[25]^C[24]^C[21]^C[13]^C[12]^C[10]^C[1];
N[27] = D[62]^D[60]^D[58]^D[56]^D[55]^D[54]^D[51]^D[44]^D[41]^D[36]^D[34]^D[32]^D[31]^D[29]^D[28]^D[27]^D[23]^D[17]^D[12]^D[11]^D[8]^D[6]^D[4]^D[2]
^C[31]^C[30]^C[28]^C[27]^C[23]^C[19]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[3];
N[28] = D[57]^D[54]^D[53]^D[51]^D[50]^D[48]^D[40]^D[38]^D[34]^D[33]^D[31]^D[30]^D[29]^D[27]^D[23]^D[21]^D[14]^D[9]^D[7]^D[6]^D[5]^D[4]^D[0]
^C[31]^C[30]^C[26]^C[24]^C[15]^C[14]^C[13]^C[7]^C[6]^C[4]^C[3]^C[0];
N[29] = D[62]^D[60]^D[55]^D[46]^D[45]^D[44]^D[43]^D[41]^D[40]^D[35]^D[33]^D[32]^D[30]^D[28]^D[25]^D[23]^D[22]^D[13]^D[8]^D[7]^D[6]^D[5]^D[4]^D[3]^D[1]^D[0]
^C[31]^C[28]^C[27]^C[18]^C[11]^C[8]^C[6]^C[4]^C[2]^C[1]^C[0];
N[30] = D[63]^D[62]^D[59]^D[58]^D[55]^D[52]^D[47]^D[44]^D[36]^D[35]^D[34]^D[31]^D[29]^D[22]^D[21]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[3]^D[2]^D[0]
^C[28]^C[25]^C[24]^C[22]^C[20]^C[15]^C[14]^C[12]^C[10]^C[9]^C[4]^C[0];
N[31] = D[61]^D[58]^D[56]^D[55]^D[54]^D[52]^D[51]^D[50]^D[49]^D[42]^D[38]^D[37]^D[36]^D[34]^D[31]^D[30]^D[27]^D[26]^D[23]^D[22]^D[21]^D[19]^D[18]^D[12]^D[0]
^C[28]^C[26]^C[24]^C[21]^C[17]^C[16]^C[14]^C[13]^C[10]^C[8]^C[2];
newcrc = N;
end
endfunction
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [63:0] d;
reg [31:0] c;
wire [31:0] q = crc (d, c);
reg [31:0] q_r;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
q_r <= q;
c <= q;
d <= {d[62:0], ^d[63:48]};
//$write("%d crc(%x,%x)=%x\n", cyc, d, c, q);
if (cyc==1) begin
// Assign inputs randomly
q_r <= 32'h12345678;
c <= 32'h12345678;
d <= 64'hffffffff_ffffffff;
end
if (cyc==2) begin
d <= 64'hffffffff_ffffffff;
end
if (cyc==3) begin
d <= 64'hffffffff_ffffffff;
end
if (cyc==4) begin
d <= 64'h50183721_81a04b1a;
end
if (cyc==5) begin
end
if (cyc==9) begin
if (q !== 32'h38295e96) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
function [31:0] crc;
input [63:0] di;
input [31:0] ci;
reg [63:0] drev;
begin
drev = reverse(di);
crc = newcrc(drev, ci);
end
endfunction
function [63:0] reverse;
input [63:0] di;
integer i;
begin
reverse = 64'b0;
for (i=0; i<64; i=i+1) reverse[i] = di[63-i];
end
endfunction
function [31:0] newcrc;
input [63:0] D;
input [31:0] C;
reg [31:0] N;
reg [31:0] DT;
begin
N = 32'b0;
// Note this isn't a real CRC code; it's been munged for privacy
N[0] = D[59]^D[53]^D[52]^D[49]^D[44]^D[41]^D[40]^D[39]^D[37]^D[32]^D[29]^D[26]^D[22]^D[21]^D[20]^D[16]^D[15]^D[14]^D[9]^D[7]^D[0]
^C[29]^C[27]^C[24]^C[23]^C[22]^C[21]^C[19]^C[15]^C[13]^C[10]^C[8]^C[3]^C[1];
N[1] = D[61]^D[57]^D[51]^D[47]^D[43]^D[37]^D[35]^D[32]^D[28]^D[24]^D[22]^D[21]^D[20]^D[16]^D[12]^D[11]^D[10]^D[8]^D[7]^D[6]^D[1]^D[0]
^C[30]^C[27]^C[26]^C[20]^C[16]^C[14]^C[13]^C[11]^C[10]^C[8]^C[5]^C[0];
N[2] = D[63]^D[62]^D[61]^D[60]^D[55]^D[54]^D[52]^D[44]^D[43]^D[42]^D[37]^D[34]^D[33]^D[29]^D[28]^D[25]^D[24]^D[23]^D[22]^D[18]^D[16]^D[15]^D[13]^D[12]^D[11]
^C[31]^C[30]^C[27]^C[22]^C[21]^C[18]^C[15]^C[12]^C[11]^C[10]^C[7];
N[3] = D[62]^D[54]^D[50]^D[47]^D[46]^D[38]^D[36]^D[35]^D[34]^D[33]^D[32]^D[30]^D[27]^D[25]^D[21]^D[20]^D[19]^D[17]^D[15]^D[11]^D[8]^D[5]^D[3]^D[1]^D[0]
^C[28]^C[25]^C[24]^C[13]^C[11]^C[9]^C[8]^C[7]^C[3]^C[1];
N[4] = D[57]^D[54]^D[53]^D[52]^D[45]^D[44]^D[43]^D[39]^D[37]^D[34]^D[33]^D[32]^D[31]^D[28]^D[24]^D[23]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[1]^D[0]
^C[30]^C[24]^C[20]^C[16]^C[14]^C[11]^C[8]^C[7]^C[6]^C[5]^C[2];
N[5] = D[58]^D[57]^D[50]^D[49]^D[48]^D[47]^D[43]^D[39]^D[29]^D[26]^D[23]^D[22]^D[20]^D[18]^D[14]^D[10]^D[9]^D[6]^D[5]^D[4]^D[1]
^C[27]^C[24]^C[20]^C[19]^C[18]^C[14]^C[13]^C[12]^C[11]^C[8]^C[7]^C[1];
N[6] = D[63]^D[62]^D[61]^D[57]^D[51]^D[50]^D[47]^D[38]^D[37]^D[34]^D[30]^D[28]^D[27]^D[25]^D[21]^D[16]^D[15]^D[10]^D[9]^D[6]^D[5]^D[2]^D[1]
^C[31]^C[27]^C[25]^C[16]^C[13]^C[9]^C[8]^C[7]^C[0];
N[7] = ^D[62]^D[61]^D[59]^D[54]^D[52]^D[51]^D[49]^D[46]^D[45]^D[42]^D[41]^D[38]^D[35]^D[29]^D[26]^D[24]^D[15]^D[12]^D[11]^D[9]^D[2]^D[0]
^C[28]^C[27]^C[26]^C[20]^C[19]^C[18]^C[15]^C[12]^C[7]^C[4];
N[8] = D[62]^D[61]^D[60]^D[59]^D[52]^D[50]^D[48]^D[47]^D[46]^D[45]^D[44]^D[42]^D[41]^D[40]^D[30]^D[24]^D[23]^D[22]^D[19]^D[17]^D[11]^D[10]^D[7]^D[6]^D[2]
^C[31]^C[29]^C[27]^C[22]^C[21]^C[19]^C[17]^C[11]^C[9]^C[7]^C[6];
N[9] = D[62]^D[59]^D[58]^D[57]^D[54]^D[51]^D[50]^D[43]^D[41]^D[39]^D[28]^D[25]^D[24]^D[23]^D[22]^D[21]^D[18]^D[16]^D[15]^D[7]
^C[30]^C[29]^C[27]^C[25]^C[23]^C[22]^C[13]^C[12]^C[7]^C[6]^C[5]^C[1];
N[10] = D[61]^D[60]^D[58]^D[56]^D[54]^D[53]^D[51]^D[48]^D[46]^D[43]^D[42]^D[38]^D[37]^D[35]^D[33]^D[31]^D[30]^D[27]^D[26]^D[24]^D[19]^D[10]^D[8]^D[6]^D[1]
^C[31]^C[30]^C[26]^C[25]^C[24]^C[21]^C[16]^C[12]^C[3]^C[2];
N[11] = D[59]^D[57]^D[56]^D[50]^D[49]^D[48]^D[47]^D[46]^D[45]^D[42]^D[41]^D[40]^D[33]^D[32]^D[30]^D[25]^D[21]^D[15]^D[14]^D[13]^D[12]^D[11]^D[5]^D[1]
^C[27]^C[25]^C[24]^C[21]^C[16]^C[12]^C[7]^C[3]^C[2]^C[1];
N[12] = D[62]^D[61]^D[59]^D[58]^D[56]^D[55]^D[53]^D[48]^D[47]^D[44]^D[43]^D[35]^D[31]^D[30]^D[28]^D[24]^D[23]^D[21]^D[14]^D[5]^D[2]
^C[28]^C[26]^C[25]^C[23]^C[22]^C[18]^C[16]^C[15]^C[6];
N[13] = D[63]^D[60]^D[58]^D[57]^D[55]^D[54]^D[53]^D[51]^D[47]^D[45]^D[42]^D[41]^D[38]^D[28]^D[26]^D[25]^D[22]^D[20]^D[18]^D[17]^D[15]^D[13]^D[12]^D[11]
^C[29]^C[28]^C[25]^C[22]^C[19]^C[17]^C[16]^C[15]^C[14]^C[12]^C[10]^C[9];
N[14] = D[58]^D[56]^D[55]^D[52]^D[47]^D[43]^D[41]^D[40]^D[39]^D[38]^D[30]^D[26]^D[25]^D[22]^D[19]^D[17]^D[13]^D[11]^D[10]^D[9]^D[8]^D[3]^D[2]^D[0]
^C[31]^C[28]^C[20]^C[18]^C[17]^C[16]^C[15]^C[13]^C[11]^C[4]^C[2]^C[1];
N[15] = D[63]^D[62]^D[61]^D[59]^D[58]^D[48]^D[47]^D[43]^D[42]^D[35]^D[28]^D[26]^D[25]^D[24]^D[23]^D[22]^D[21]^D[20]^D[19]^D[17]^D[11]^D[7]^D[2]
^C[30]^C[29]^C[27]^C[24]^C[20]^C[17]^C[16]^C[15]^C[11]^C[9]^C[5];
N[16] = D[60]^D[57]^D[49]^D[46]^D[45]^D[43]^D[39]^D[36]^D[32]^D[30]^D[29]^D[28]^D[27]^D[26]^D[23]^D[20]^D[19]^D[17]^D[11]^D[8]^D[5]^D[1]
^C[28]^C[26]^C[23]^C[22]^C[18]^C[16]^C[13]^C[12]^C[10]^C[9]^C[6];
N[17] = D[63]^D[62]^D[61]^D[60]^D[58]^D[54]^D[53]^D[51]^D[48]^D[42]^D[41]^D[37]^D[36]^D[34]^D[28]^D[27]^D[26]^D[24]^D[13]^D[12]^D[9]^D[7]^D[4]^D[0]
^C[31]^C[30]^C[27]^C[23]^C[20]^C[17]^C[14]^C[9]^C[6]^C[4]^C[3]^C[0];
N[18] = D[63]^D[61]^D[59]^D[56]^D[52]^D[50]^D[47]^D[42]^D[37]^D[35]^D[34]^D[31]^D[30]^D[29]^D[22]^D[19]^D[17]^D[16]^D[11]^D[9]^D[8]^D[7]
^C[26]^C[22]^C[20]^C[19]^C[16]^C[11]^C[8]^C[6]^C[5]^C[0];
N[19] = D[62]^D[60]^D[52]^D[49]^D[44]^D[43]^D[42]^D[37]^D[33]^D[32]^D[29]^D[26]^D[19]^D[17]^D[16]^D[12]^D[10]^D[7]^D[6]^D[4]^D[3]^D[2]
^C[30]^C[29]^C[26]^C[25]^C[22]^C[19]^C[14]^C[7]^C[6]^C[5]^C[2]^C[0];
N[20] = D[63]^D[58]^D[54]^D[48]^D[47]^D[40]^D[39]^D[35]^D[34]^D[32]^D[31]^D[28]^D[27]^D[25]^D[18]^D[12]^D[9]^D[7]^D[5]^D[4]^D[3]^D[2]^D[1]
^C[31]^C[29]^C[28]^C[25]^C[19]^C[18]^C[17]^C[15]^C[10]^C[9]^C[6]^C[4];
N[21] = D[61]^D[59]^D[57]^D[56]^D[53]^D[48]^D[44]^D[43]^D[41]^D[35]^D[29]^D[26]^D[25]^D[20]^D[18]^D[17]^D[16]^D[12]^D[9]^D[6]^D[5]^D[3]^D[1]
^C[30]^C[27]^C[24]^C[23]^C[22]^C[21]^C[20]^C[13]^C[9]^C[3]^C[2];
N[22] = D[63]^D[62]^D[60]^D[57]^D[53]^D[51]^D[45]^D[44]^D[42]^D[34]^D[33]^D[27]^D[20]^D[19]^D[18]^D[15]^D[10]^D[9]^D[8]^D[4]^D[3]
^C[24]^C[23]^C[18]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[9]^C[6]^C[5];
N[23] = D[58]^D[56]^D[54]^D[51]^D[47]^D[43]^D[42]^D[40]^D[37]^D[36]^D[33]^D[25]^D[23]^D[20]^D[18]^D[16]^D[15]^D[12]^D[10]^D[8]^D[7]^D[5]^D[3]
^C[31]^C[27]^C[26]^C[23]^C[21]^C[18]^C[15]^C[11]^C[10]^C[8]^C[7]^C[1];
N[24] = D[60]^D[59]^D[52]^D[50]^D[48]^D[44]^D[39]^D[36]^D[35]^D[31]^D[30]^D[28]^D[27]^D[23]^D[22]^D[21]^D[19]^D[14]^D[13]^D[12]^D[9]^D[4]^D[1]^D[0]
^C[27]^C[25]^C[23]^C[21]^C[17]^C[11]^C[10]^C[4]^C[0];
N[25] = D[61]^D[60]^D[56]^D[54]^D[51]^D[46]^D[43]^D[41]^D[40]^D[38]^D[37]^D[36]^D[29]^D[28]^D[27]^D[22]^D[17]^D[15]^D[10]^D[7]^D[4]^D[2]
^C[29]^C[28]^C[26]^C[23]^C[18]^C[14]^C[13]^C[12]^C[11]^C[9]^C[8]^C[6];
N[26] = D[63]^D[62]^D[58]^D[55]^D[54]^D[52]^D[50]^D[39]^D[37]^D[36]^D[35]^D[33]^D[31]^D[29]^D[27]^D[18]^D[14]^D[10]^D[3]^D[2]^D[0]
^C[31]^C[27]^C[26]^C[25]^C[24]^C[21]^C[13]^C[12]^C[10]^C[1];
N[27] = D[62]^D[60]^D[58]^D[56]^D[55]^D[54]^D[51]^D[44]^D[41]^D[36]^D[34]^D[32]^D[31]^D[29]^D[28]^D[27]^D[23]^D[17]^D[12]^D[11]^D[8]^D[6]^D[4]^D[2]
^C[31]^C[30]^C[28]^C[27]^C[23]^C[19]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[3];
N[28] = D[57]^D[54]^D[53]^D[51]^D[50]^D[48]^D[40]^D[38]^D[34]^D[33]^D[31]^D[30]^D[29]^D[27]^D[23]^D[21]^D[14]^D[9]^D[7]^D[6]^D[5]^D[4]^D[0]
^C[31]^C[30]^C[26]^C[24]^C[15]^C[14]^C[13]^C[7]^C[6]^C[4]^C[3]^C[0];
N[29] = D[62]^D[60]^D[55]^D[46]^D[45]^D[44]^D[43]^D[41]^D[40]^D[35]^D[33]^D[32]^D[30]^D[28]^D[25]^D[23]^D[22]^D[13]^D[8]^D[7]^D[6]^D[5]^D[4]^D[3]^D[1]^D[0]
^C[31]^C[28]^C[27]^C[18]^C[11]^C[8]^C[6]^C[4]^C[2]^C[1]^C[0];
N[30] = D[63]^D[62]^D[59]^D[58]^D[55]^D[52]^D[47]^D[44]^D[36]^D[35]^D[34]^D[31]^D[29]^D[22]^D[21]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[3]^D[2]^D[0]
^C[28]^C[25]^C[24]^C[22]^C[20]^C[15]^C[14]^C[12]^C[10]^C[9]^C[4]^C[0];
N[31] = D[61]^D[58]^D[56]^D[55]^D[54]^D[52]^D[51]^D[50]^D[49]^D[42]^D[38]^D[37]^D[36]^D[34]^D[31]^D[30]^D[27]^D[26]^D[23]^D[22]^D[21]^D[19]^D[18]^D[12]^D[0]
^C[28]^C[26]^C[24]^C[21]^C[17]^C[16]^C[14]^C[13]^C[10]^C[8]^C[2];
newcrc = N;
end
endfunction
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] cyc; initial cyc=0;
reg [31:0] in;
wire [31:0] out;
t_extend_class_v sub (.in(in), .out(out));
always @ (posedge clk) begin
cyc <= cyc+8'd1;
if (cyc == 8'd1) begin
in <= 32'h10;
end
if (cyc == 8'd2) begin
if (out != 32'h11) $stop;
end
if (cyc == 8'd9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module t_extend_class_v (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [31:0] in;
output [31:0] out;
always @* begin
// When "in" changes, call my method
out = $c("m_myobjp->my_math(",in,")");
end
`systemc_header
#include "t_extend_class_c.h" // Header for contained object
`systemc_interface
t_extend_class_c* m_myobjp; // Pointer to object we are embedding
`systemc_ctor
m_myobjp = new t_extend_class_c(); // Construct contained object
`systemc_dtor
delete m_myobjp; // Destruct contained object
`verilog
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] cyc; initial cyc=0;
reg [31:0] in;
wire [31:0] out;
t_extend_class_v sub (.in(in), .out(out));
always @ (posedge clk) begin
cyc <= cyc+8'd1;
if (cyc == 8'd1) begin
in <= 32'h10;
end
if (cyc == 8'd2) begin
if (out != 32'h11) $stop;
end
if (cyc == 8'd9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module t_extend_class_v (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [31:0] in;
output [31:0] out;
always @* begin
// When "in" changes, call my method
out = $c("m_myobjp->my_math(",in,")");
end
`systemc_header
#include "t_extend_class_c.h" // Header for contained object
`systemc_interface
t_extend_class_c* m_myobjp; // Pointer to object we are embedding
`systemc_ctor
m_myobjp = new t_extend_class_c(); // Construct contained object
`systemc_dtor
delete m_myobjp; // Destruct contained object
`verilog
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [255:0] a;
reg [60:0] divisor;
reg [60:0] qq;
reg [60:0] rq;
reg signed [60:0] qqs;
reg signed [60:0] rqs;
always @* begin
qq = a[60:0] / divisor;
rq = a[60:0] % divisor;
qqs = $signed(a[60:0]) / $signed(divisor);
rqs = $signed(a[60:0]) % $signed(divisor);
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d: %x %x %x %x\n", cyc, qq, rq, qqs, rqs);
if (cyc==1) begin
a <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
divisor <= 61'h12371;
a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned
end
if (cyc==2) begin
a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
divisor <= 61'h1238123771;
a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned
if (qq!==61'h00000403ad81c0da) $stop;
if (rq!==61'h00000000000090ec) $stop;
if (qqs!==61'h00000403ad81c0da) $stop;
if (rqs!==61'h00000000000090ec) $stop;
end
if (cyc==3) begin
a <= 256'h0e17c88f00d5fe51a982646c8002bd68c3e236ddfd00ddbdad20a48e00f395b8;
divisor <= 61'hf1b;
a[60] <= 1'b1; divisor[60] <= 1'b0; // Signed
if (qq!==61'h000000000090832e) $stop;
if (rq!==61'h0000000334becc6a) $stop;
if (qqs!==61'h000000000090832e) $stop;
if (rqs!==61'h0000000334becc6a) $stop;
end
if (cyc==4) begin
a[60] <= 1'b0; divisor[60] <= 1'b1; // Signed
if (qq!==61'h0001eda37cca1be8) $stop;
if (rq!==61'h0000000000000c40) $stop;
if (qqs!==61'h1fffcf5187c76510) $stop;
if (rqs!==61'h1ffffffffffffd08) $stop;
end
if (cyc==5) begin
a[60] <= 1'b1; divisor[60] <= 1'b1; // Signed
if (qq!==61'h0000000000000000) $stop;
if (rq!==61'h0d20a48e00f395b8) $stop;
if (qqs!==61'h0000000000000000) $stop;
if (rqs!==61'h0d20a48e00f395b8) $stop;
end
if (cyc==6) begin
if (qq!==61'h0000000000000001) $stop;
if (rq!==61'h0d20a48e00f3869d) $stop;
if (qqs!==61'h0000000000000000) $stop;
if (rqs!==61'h1d20a48e00f395b8) $stop;
end
// Div by zero
if (cyc==9) begin
divisor <= 61'd0;
end
if (cyc==10) begin
`ifdef verilator
if (qq !== {61{1'b0}}) $stop;
if (rq !== {61{1'b0}}) $stop;
`else
if (qq !== {61{1'bx}}) $stop;
if (rq !== {61{1'bx}}) $stop;
`endif
if ({16{1'bx}} !== 16'd1/16'd0) $stop; // No div by zero errors
if ({16{1'bx}} !== 16'd1%16'd0) $stop; // No div by zero errors
end
if (cyc==19) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [3:0] Value = crc[3:0];
wire [3:0] Result;
wire [3:0] Result2;
Testit testit (/*AUTOINST*/
// Outputs
.Result (Result[3:0]),
.Result2 (Result2[3:0]),
// Inputs
.clk (clk),
.Value (Value[3:0]));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x %x %x %x\n",$time, cyc, crc, Result, Result2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {56'h0, Result, Result2}
^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h4af37965592f64f9) $stop;
$finish;
end
end
endmodule
|
module Test (clk, Value, Result);
input clk;
input Value;
output Result;
reg Internal;
assign Result = Internal ^ clk;
always @(posedge clk)
Internal <= #1 Value;
endmodule
|
module Test_wrap1 (clk, Value, Result);
input clk;
input Value;
output Result;
Test t (clk, Value, Result);
endmodule
|
module Test_wrap2 (clk, Value, Result);
input clk;
input Value;
output Result;
Test t (clk, Value, Result);
endmodule
|
module Testit (clk, Value, Result, Result2);
input clk;
input [3:0] Value;
output [3:0] Result;
output [3:0] Result2;
genvar i;
generate
for (i = 0; i < 4; i = i + 1)
begin : a
if ((i == 0) || (i == 2)) begin : gblk
Test_wrap1 test (clk, Value[i] , Result[i]);
end
else begin : gblk
Test_wrap2 test (clk, Value[i], Result[i]);
end
end
endgenerate
assign Result2[0] = a[0].gblk.test.t.Internal;
assign Result2[1] = a[1].gblk.test.t.Internal;
assign Result2[2] = a[2].gblk.test.t.Internal;
assign Result2[3] = a[3].gblk.test.t.Internal;
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [3:0] Value = crc[3:0];
wire [3:0] Result;
wire [3:0] Result2;
Testit testit (/*AUTOINST*/
// Outputs
.Result (Result[3:0]),
.Result2 (Result2[3:0]),
// Inputs
.clk (clk),
.Value (Value[3:0]));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x %x %x %x\n",$time, cyc, crc, Result, Result2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {56'h0, Result, Result2}
^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h4af37965592f64f9) $stop;
$finish;
end
end
endmodule
|
module Test (clk, Value, Result);
input clk;
input Value;
output Result;
reg Internal;
assign Result = Internal ^ clk;
always @(posedge clk)
Internal <= #1 Value;
endmodule
|
module Test_wrap1 (clk, Value, Result);
input clk;
input Value;
output Result;
Test t (clk, Value, Result);
endmodule
|
module Test_wrap2 (clk, Value, Result);
input clk;
input Value;
output Result;
Test t (clk, Value, Result);
endmodule
|
module Testit (clk, Value, Result, Result2);
input clk;
input [3:0] Value;
output [3:0] Result;
output [3:0] Result2;
genvar i;
generate
for (i = 0; i < 4; i = i + 1)
begin : a
if ((i == 0) || (i == 2)) begin : gblk
Test_wrap1 test (clk, Value[i] , Result[i]);
end
else begin : gblk
Test_wrap2 test (clk, Value[i], Result[i]);
end
end
endgenerate
assign Result2[0] = a[0].gblk.test.t.Internal;
assign Result2[1] = a[1].gblk.test.t.Internal;
assign Result2[2] = a[2].gblk.test.t.Internal;
assign Result2[3] = a[3].gblk.test.t.Internal;
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [2:0] index_a;
reg [2:0] index_b;
prover #(4) p4 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(32) p32 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(63) p63 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(64) p64 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(72) p72 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(126) p126 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(128) p128 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
integer cyc; initial cyc=0;
initial index_a = 3'b0;
initial index_b = 3'b0;
always @* begin
index_a = cyc[2:0]; if (index_a>3'd4) index_a=3'd4;
index_b = cyc[5:3]; if (index_b>3'd4) index_b=3'd4;
end
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module prover (
input clk,
input [2:0] index_a,
input [2:0] index_b
);
parameter WIDTH = 4;
reg signed [WIDTH-1:0] as;
reg signed [WIDTH-1:0] bs;
wire [WIDTH-1:0] b = bs;
always @* begin
casez (index_a)
3'd0: as = {(WIDTH){1'd0}}; // 0
3'd1: as = {{(WIDTH-1){1'd0}}, 1'b1}; // 1
3'd2: as = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv
3'd3: as = {(WIDTH){1'd1}}; // -1
3'd4: as = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv
default: $stop;
endcase
casez (index_b)
3'd0: bs = {(WIDTH){1'd0}}; // 0
3'd1: bs = {{(WIDTH-1){1'd0}}, 1'b1}; // 1
3'd2: bs = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv
3'd3: bs = {(WIDTH){1'd1}}; // -1
3'd4: bs = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv
default: $stop;
endcase
end
reg [7:0] results[4:0][4:0];
wire gt = as>b;
wire gts = as>bs;
wire gte = as>=b;
wire gtes = as>=bs;
wire lt = as<b;
wire lts = as<bs;
wire lte = as<=b;
wire ltes = as<=bs;
reg [7:0] exp;
reg [7:0] got;
integer cyc=0;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc>2) begin
`ifdef TEST_VERBOSE
$write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n",
index_a, index_b,
gt, gts, gte, gtes, lt, lts, lte, ltes);
`endif
exp = results[index_a][index_b];
got = {gt, gts, gte, gtes, lt, lts, lte, ltes};
if (exp !== got) begin
$display("%%Error: bad comparison width=%0d: %d/%d got=%b exp=%b", WIDTH, index_a,index_b,got, exp);
$stop;
end
end
end
// Result table
initial begin
// Indexes: 0, 1, -1, 127, -128
// Gt Gts Gte Gtes Lt Lts Lte Ltes
results[0][0] = 8'b0_0_1_1_0_0_1_1;
results[0][1] = 8'b0_0_0_0_1_1_1_1;
results[0][2] = 8'b0_0_1_1_0_0_1_1;
results[0][3] = 8'b0_1_0_1_1_0_1_0;
results[0][4] = 8'b0_1_0_1_1_0_1_0;
results[1][0] = 8'b1_1_1_1_0_0_0_0;
results[1][1] = 8'b0_0_1_1_0_0_1_1;
results[1][2] = 8'b1_1_1_1_0_0_0_0;
results[1][3] = 8'b0_1_0_1_1_0_1_0;
results[1][4] = 8'b0_1_0_1_1_0_1_0;
results[2][0] = 8'b0_0_1_1_0_0_1_1;
results[2][1] = 8'b0_0_0_0_1_1_1_1;
results[2][2] = 8'b0_0_1_1_0_0_1_1;
results[2][3] = 8'b0_1_0_1_1_0_1_0;
results[2][4] = 8'b0_1_0_1_1_0_1_0;
results[3][0] = 8'b1_0_1_0_0_1_0_1;
results[3][1] = 8'b1_0_1_0_0_1_0_1;
results[3][2] = 8'b1_0_1_0_0_1_0_1;
results[3][3] = 8'b0_0_1_1_0_0_1_1;
results[3][4] = 8'b1_1_1_1_0_0_0_0;
results[4][0] = 8'b1_0_1_0_0_1_0_1;
results[4][1] = 8'b1_0_1_0_0_1_0_1;
results[4][2] = 8'b1_0_1_0_0_1_0_1;
results[4][3] = 8'b0_0_0_0_1_1_1_1;
results[4][4] = 8'b0_0_1_1_0_0_1_1;
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [2:0] index_a;
reg [2:0] index_b;
prover #(4) p4 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(32) p32 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(63) p63 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(64) p64 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(72) p72 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(126) p126 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(128) p128 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
integer cyc; initial cyc=0;
initial index_a = 3'b0;
initial index_b = 3'b0;
always @* begin
index_a = cyc[2:0]; if (index_a>3'd4) index_a=3'd4;
index_b = cyc[5:3]; if (index_b>3'd4) index_b=3'd4;
end
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module prover (
input clk,
input [2:0] index_a,
input [2:0] index_b
);
parameter WIDTH = 4;
reg signed [WIDTH-1:0] as;
reg signed [WIDTH-1:0] bs;
wire [WIDTH-1:0] b = bs;
always @* begin
casez (index_a)
3'd0: as = {(WIDTH){1'd0}}; // 0
3'd1: as = {{(WIDTH-1){1'd0}}, 1'b1}; // 1
3'd2: as = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv
3'd3: as = {(WIDTH){1'd1}}; // -1
3'd4: as = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv
default: $stop;
endcase
casez (index_b)
3'd0: bs = {(WIDTH){1'd0}}; // 0
3'd1: bs = {{(WIDTH-1){1'd0}}, 1'b1}; // 1
3'd2: bs = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv
3'd3: bs = {(WIDTH){1'd1}}; // -1
3'd4: bs = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv
default: $stop;
endcase
end
reg [7:0] results[4:0][4:0];
wire gt = as>b;
wire gts = as>bs;
wire gte = as>=b;
wire gtes = as>=bs;
wire lt = as<b;
wire lts = as<bs;
wire lte = as<=b;
wire ltes = as<=bs;
reg [7:0] exp;
reg [7:0] got;
integer cyc=0;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc>2) begin
`ifdef TEST_VERBOSE
$write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n",
index_a, index_b,
gt, gts, gte, gtes, lt, lts, lte, ltes);
`endif
exp = results[index_a][index_b];
got = {gt, gts, gte, gtes, lt, lts, lte, ltes};
if (exp !== got) begin
$display("%%Error: bad comparison width=%0d: %d/%d got=%b exp=%b", WIDTH, index_a,index_b,got, exp);
$stop;
end
end
end
// Result table
initial begin
// Indexes: 0, 1, -1, 127, -128
// Gt Gts Gte Gtes Lt Lts Lte Ltes
results[0][0] = 8'b0_0_1_1_0_0_1_1;
results[0][1] = 8'b0_0_0_0_1_1_1_1;
results[0][2] = 8'b0_0_1_1_0_0_1_1;
results[0][3] = 8'b0_1_0_1_1_0_1_0;
results[0][4] = 8'b0_1_0_1_1_0_1_0;
results[1][0] = 8'b1_1_1_1_0_0_0_0;
results[1][1] = 8'b0_0_1_1_0_0_1_1;
results[1][2] = 8'b1_1_1_1_0_0_0_0;
results[1][3] = 8'b0_1_0_1_1_0_1_0;
results[1][4] = 8'b0_1_0_1_1_0_1_0;
results[2][0] = 8'b0_0_1_1_0_0_1_1;
results[2][1] = 8'b0_0_0_0_1_1_1_1;
results[2][2] = 8'b0_0_1_1_0_0_1_1;
results[2][3] = 8'b0_1_0_1_1_0_1_0;
results[2][4] = 8'b0_1_0_1_1_0_1_0;
results[3][0] = 8'b1_0_1_0_0_1_0_1;
results[3][1] = 8'b1_0_1_0_0_1_0_1;
results[3][2] = 8'b1_0_1_0_0_1_0_1;
results[3][3] = 8'b0_0_1_1_0_0_1_1;
results[3][4] = 8'b1_1_1_1_0_0_0_0;
results[4][0] = 8'b1_0_1_0_0_1_0_1;
results[4][1] = 8'b1_0_1_0_0_1_0_1;
results[4][2] = 8'b1_0_1_0_0_1_0_1;
results[4][3] = 8'b0_0_0_0_1_1_1_1;
results[4][4] = 8'b0_0_1_1_0_0_1_1;
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [2:0] index_a;
reg [2:0] index_b;
prover #(4) p4 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(32) p32 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(63) p63 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(64) p64 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(72) p72 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(126) p126 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(128) p128 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
integer cyc; initial cyc=0;
initial index_a = 3'b0;
initial index_b = 3'b0;
always @* begin
index_a = cyc[2:0]; if (index_a>3'd4) index_a=3'd4;
index_b = cyc[5:3]; if (index_b>3'd4) index_b=3'd4;
end
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module prover (
input clk,
input [2:0] index_a,
input [2:0] index_b
);
parameter WIDTH = 4;
reg signed [WIDTH-1:0] as;
reg signed [WIDTH-1:0] bs;
wire [WIDTH-1:0] b = bs;
always @* begin
casez (index_a)
3'd0: as = {(WIDTH){1'd0}}; // 0
3'd1: as = {{(WIDTH-1){1'd0}}, 1'b1}; // 1
3'd2: as = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv
3'd3: as = {(WIDTH){1'd1}}; // -1
3'd4: as = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv
default: $stop;
endcase
casez (index_b)
3'd0: bs = {(WIDTH){1'd0}}; // 0
3'd1: bs = {{(WIDTH-1){1'd0}}, 1'b1}; // 1
3'd2: bs = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv
3'd3: bs = {(WIDTH){1'd1}}; // -1
3'd4: bs = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv
default: $stop;
endcase
end
reg [7:0] results[4:0][4:0];
wire gt = as>b;
wire gts = as>bs;
wire gte = as>=b;
wire gtes = as>=bs;
wire lt = as<b;
wire lts = as<bs;
wire lte = as<=b;
wire ltes = as<=bs;
reg [7:0] exp;
reg [7:0] got;
integer cyc=0;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc>2) begin
`ifdef TEST_VERBOSE
$write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n",
index_a, index_b,
gt, gts, gte, gtes, lt, lts, lte, ltes);
`endif
exp = results[index_a][index_b];
got = {gt, gts, gte, gtes, lt, lts, lte, ltes};
if (exp !== got) begin
$display("%%Error: bad comparison width=%0d: %d/%d got=%b exp=%b", WIDTH, index_a,index_b,got, exp);
$stop;
end
end
end
// Result table
initial begin
// Indexes: 0, 1, -1, 127, -128
// Gt Gts Gte Gtes Lt Lts Lte Ltes
results[0][0] = 8'b0_0_1_1_0_0_1_1;
results[0][1] = 8'b0_0_0_0_1_1_1_1;
results[0][2] = 8'b0_0_1_1_0_0_1_1;
results[0][3] = 8'b0_1_0_1_1_0_1_0;
results[0][4] = 8'b0_1_0_1_1_0_1_0;
results[1][0] = 8'b1_1_1_1_0_0_0_0;
results[1][1] = 8'b0_0_1_1_0_0_1_1;
results[1][2] = 8'b1_1_1_1_0_0_0_0;
results[1][3] = 8'b0_1_0_1_1_0_1_0;
results[1][4] = 8'b0_1_0_1_1_0_1_0;
results[2][0] = 8'b0_0_1_1_0_0_1_1;
results[2][1] = 8'b0_0_0_0_1_1_1_1;
results[2][2] = 8'b0_0_1_1_0_0_1_1;
results[2][3] = 8'b0_1_0_1_1_0_1_0;
results[2][4] = 8'b0_1_0_1_1_0_1_0;
results[3][0] = 8'b1_0_1_0_0_1_0_1;
results[3][1] = 8'b1_0_1_0_0_1_0_1;
results[3][2] = 8'b1_0_1_0_0_1_0_1;
results[3][3] = 8'b0_0_1_1_0_0_1_1;
results[3][4] = 8'b1_1_1_1_0_0_0_0;
results[4][0] = 8'b1_0_1_0_0_1_0_1;
results[4][1] = 8'b1_0_1_0_0_1_0_1;
results[4][2] = 8'b1_0_1_0_0_1_0_1;
results[4][3] = 8'b0_0_0_0_1_1_1_1;
results[4][4] = 8'b0_0_1_1_0_0_1_1;
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [2:0] index_a;
reg [2:0] index_b;
prover #(4) p4 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(32) p32 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(63) p63 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(64) p64 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(72) p72 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(126) p126 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(128) p128 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
integer cyc; initial cyc=0;
initial index_a = 3'b0;
initial index_b = 3'b0;
always @* begin
index_a = cyc[2:0]; if (index_a>3'd4) index_a=3'd4;
index_b = cyc[5:3]; if (index_b>3'd4) index_b=3'd4;
end
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module prover (
input clk,
input [2:0] index_a,
input [2:0] index_b
);
parameter WIDTH = 4;
reg signed [WIDTH-1:0] as;
reg signed [WIDTH-1:0] bs;
wire [WIDTH-1:0] b = bs;
always @* begin
casez (index_a)
3'd0: as = {(WIDTH){1'd0}}; // 0
3'd1: as = {{(WIDTH-1){1'd0}}, 1'b1}; // 1
3'd2: as = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv
3'd3: as = {(WIDTH){1'd1}}; // -1
3'd4: as = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv
default: $stop;
endcase
casez (index_b)
3'd0: bs = {(WIDTH){1'd0}}; // 0
3'd1: bs = {{(WIDTH-1){1'd0}}, 1'b1}; // 1
3'd2: bs = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv
3'd3: bs = {(WIDTH){1'd1}}; // -1
3'd4: bs = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv
default: $stop;
endcase
end
reg [7:0] results[4:0][4:0];
wire gt = as>b;
wire gts = as>bs;
wire gte = as>=b;
wire gtes = as>=bs;
wire lt = as<b;
wire lts = as<bs;
wire lte = as<=b;
wire ltes = as<=bs;
reg [7:0] exp;
reg [7:0] got;
integer cyc=0;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc>2) begin
`ifdef TEST_VERBOSE
$write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n",
index_a, index_b,
gt, gts, gte, gtes, lt, lts, lte, ltes);
`endif
exp = results[index_a][index_b];
got = {gt, gts, gte, gtes, lt, lts, lte, ltes};
if (exp !== got) begin
$display("%%Error: bad comparison width=%0d: %d/%d got=%b exp=%b", WIDTH, index_a,index_b,got, exp);
$stop;
end
end
end
// Result table
initial begin
// Indexes: 0, 1, -1, 127, -128
// Gt Gts Gte Gtes Lt Lts Lte Ltes
results[0][0] = 8'b0_0_1_1_0_0_1_1;
results[0][1] = 8'b0_0_0_0_1_1_1_1;
results[0][2] = 8'b0_0_1_1_0_0_1_1;
results[0][3] = 8'b0_1_0_1_1_0_1_0;
results[0][4] = 8'b0_1_0_1_1_0_1_0;
results[1][0] = 8'b1_1_1_1_0_0_0_0;
results[1][1] = 8'b0_0_1_1_0_0_1_1;
results[1][2] = 8'b1_1_1_1_0_0_0_0;
results[1][3] = 8'b0_1_0_1_1_0_1_0;
results[1][4] = 8'b0_1_0_1_1_0_1_0;
results[2][0] = 8'b0_0_1_1_0_0_1_1;
results[2][1] = 8'b0_0_0_0_1_1_1_1;
results[2][2] = 8'b0_0_1_1_0_0_1_1;
results[2][3] = 8'b0_1_0_1_1_0_1_0;
results[2][4] = 8'b0_1_0_1_1_0_1_0;
results[3][0] = 8'b1_0_1_0_0_1_0_1;
results[3][1] = 8'b1_0_1_0_0_1_0_1;
results[3][2] = 8'b1_0_1_0_0_1_0_1;
results[3][3] = 8'b0_0_1_1_0_0_1_1;
results[3][4] = 8'b1_1_1_1_0_0_0_0;
results[4][0] = 8'b1_0_1_0_0_1_0_1;
results[4][1] = 8'b1_0_1_0_0_1_0_1;
results[4][2] = 8'b1_0_1_0_0_1_0_1;
results[4][3] = 8'b0_0_0_0_1_1_1_1;
results[4][4] = 8'b0_0_1_1_0_0_1_1;
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [31:0] in_a;
reg [31:0] in_b;
reg [31:0] e,f,g,h;
always @ (/*AS*/in_a) begin
e = in_a;
f = {e[15:0], e[31:16]};
g = {f[15:0], f[31:16]};
h = {g[15:0], g[31:16]};
end
// verilator lint_off UNOPTFLAT
reg [31:0] e2,f2,g2,h2;
always @ (/*AS*/f2) begin
h2 = {g2[15:0], g2[31:16]};
g2 = {f2[15:0], f2[31:16]};
end
always @ (/*AS*/in_a) begin
f2 = {e2[15:0], e2[31:16]};
e2 = in_a;
end
// verilator lint_on UNOPTFLAT
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x\n", cyc, h, h2);
if (h != h2) $stop;
if (cyc==1) begin
in_a <= 32'h89a14fab;
in_b <= 32'h7ab512fa;
end
if (cyc==2) begin
in_a <= 32'hf4c11a42;
in_b <= 32'h359967c6;
if (h != 32'h4fab89a1) $stop;
end
if (cyc==3) begin
if (h != 32'h1a42f4c1) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [31:0] in_a;
reg [31:0] in_b;
reg [31:0] e,f,g,h;
always @ (/*AS*/in_a) begin
e = in_a;
f = {e[15:0], e[31:16]};
g = {f[15:0], f[31:16]};
h = {g[15:0], g[31:16]};
end
// verilator lint_off UNOPTFLAT
reg [31:0] e2,f2,g2,h2;
always @ (/*AS*/f2) begin
h2 = {g2[15:0], g2[31:16]};
g2 = {f2[15:0], f2[31:16]};
end
always @ (/*AS*/in_a) begin
f2 = {e2[15:0], e2[31:16]};
e2 = in_a;
end
// verilator lint_on UNOPTFLAT
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x\n", cyc, h, h2);
if (h != h2) $stop;
if (cyc==1) begin
in_a <= 32'h89a14fab;
in_b <= 32'h7ab512fa;
end
if (cyc==2) begin
in_a <= 32'hf4c11a42;
in_b <= 32'h359967c6;
if (h != 32'h4fab89a1) $stop;
end
if (cyc==3) begin
if (h != 32'h1a42f4c1) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [31:0] in_a;
reg [31:0] in_b;
reg [31:0] e,f,g,h;
always @ (/*AS*/in_a) begin
e = in_a;
f = {e[15:0], e[31:16]};
g = {f[15:0], f[31:16]};
h = {g[15:0], g[31:16]};
end
// verilator lint_off UNOPTFLAT
reg [31:0] e2,f2,g2,h2;
always @ (/*AS*/f2) begin
h2 = {g2[15:0], g2[31:16]};
g2 = {f2[15:0], f2[31:16]};
end
always @ (/*AS*/in_a) begin
f2 = {e2[15:0], e2[31:16]};
e2 = in_a;
end
// verilator lint_on UNOPTFLAT
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x\n", cyc, h, h2);
if (h != h2) $stop;
if (cyc==1) begin
in_a <= 32'h89a14fab;
in_b <= 32'h7ab512fa;
end
if (cyc==2) begin
in_a <= 32'hf4c11a42;
in_b <= 32'h359967c6;
if (h != 32'h4fab89a1) $stop;
end
if (cyc==3) begin
if (h != 32'h1a42f4c1) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic [7:0] arr [7:0];
logic [7:0] arri [7:0];
has_array am1 (.clk(clk), .arri(arr), .arro(arri));
integer cyc; initial cyc = 0;
initial begin
for (int i = 0; i < 8; i++) begin
arr[i] = 0;
end
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5 && arri[1] != 8) begin
$stop;
end
for (int i = 0; i < 7; ++i) begin
arr[i+1] <= arr[i];
end
arr[0] <= arr[0] + 1;
end
endmodule
|
module has_array (
input clk,
input logic [7:0] arri [7:0],
output logic [7:0] arro [7:0]
);
integer cyc; initial cyc = 0;
always @(posedge clk) begin
cyc <= cyc + 1;
if (arri[0] == 10 && cyc == 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge clk) begin
for (integer i = 0; i < 7; ++i) begin
arro[i+1] <= arro[i];
end
arro[0] = arro[0] + 2;
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic [7:0] arr [7:0];
logic [7:0] arri [7:0];
has_array am1 (.clk(clk), .arri(arr), .arro(arri));
integer cyc; initial cyc = 0;
initial begin
for (int i = 0; i < 8; i++) begin
arr[i] = 0;
end
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5 && arri[1] != 8) begin
$stop;
end
for (int i = 0; i < 7; ++i) begin
arr[i+1] <= arr[i];
end
arr[0] <= arr[0] + 1;
end
endmodule
|
module has_array (
input clk,
input logic [7:0] arri [7:0],
output logic [7:0] arro [7:0]
);
integer cyc; initial cyc = 0;
always @(posedge clk) begin
cyc <= cyc + 1;
if (arri[0] == 10 && cyc == 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge clk) begin
for (integer i = 0; i < 7; ++i) begin
arro[i+1] <= arro[i];
end
arro[0] = arro[0] + 2;
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] wr_data;
reg wr_en;
wire [31:0] rd_data;
wire [1:0] rd_guards;
wire [1:0] rd_guardsok;
regfile regfile (/*AUTOINST*/
// Outputs
.rd_data (rd_data[31:0]),
.rd_guards (rd_guards[1:0]),
.rd_guardsok (rd_guardsok[1:0]),
// Inputs
.wr_data (wr_data[31:0]),
.wr_en (wr_en),
.clk (clk));
initial wr_en = 0;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
if (!rd_guards[0]) $stop;
if (!rd_guardsok[0]) $stop;
wr_en <= 1'b1;
wr_data <= 32'hfeedf;
end
if (cyc==2) begin
wr_en <= 0;
end
if (cyc==3) begin
wr_en <= 0;
if (rd_data != 32'hfeedf) $stop;
if (rd_guards != 2'b11) $stop;
if (rd_guardsok != 2'b11) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module regfile (
input [31:0] wr_data,
input wr_en,
output reg [31:0] rd_data,
output [1:0] rd_guards /*verilator public*/,
output [1:0] rd_guardsok /*verilator public*/,
input clk
);
always @(posedge clk) begin
if (wr_en)
begin
rd_data <= wr_data;
end
end
// this initial statement will induce correct initialize behavior
// initial rd_guards= { 2'b11 };
assign rd_guards= {
rd_data[0],
1'b1
};
assign rd_guardsok[0] = 1'b1;
assign rd_guardsok[1] = rd_data[0];
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] wr_data;
reg wr_en;
wire [31:0] rd_data;
wire [1:0] rd_guards;
wire [1:0] rd_guardsok;
regfile regfile (/*AUTOINST*/
// Outputs
.rd_data (rd_data[31:0]),
.rd_guards (rd_guards[1:0]),
.rd_guardsok (rd_guardsok[1:0]),
// Inputs
.wr_data (wr_data[31:0]),
.wr_en (wr_en),
.clk (clk));
initial wr_en = 0;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
if (!rd_guards[0]) $stop;
if (!rd_guardsok[0]) $stop;
wr_en <= 1'b1;
wr_data <= 32'hfeedf;
end
if (cyc==2) begin
wr_en <= 0;
end
if (cyc==3) begin
wr_en <= 0;
if (rd_data != 32'hfeedf) $stop;
if (rd_guards != 2'b11) $stop;
if (rd_guardsok != 2'b11) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module regfile (
input [31:0] wr_data,
input wr_en,
output reg [31:0] rd_data,
output [1:0] rd_guards /*verilator public*/,
output [1:0] rd_guardsok /*verilator public*/,
input clk
);
always @(posedge clk) begin
if (wr_en)
begin
rd_data <= wr_data;
end
end
// this initial statement will induce correct initialize behavior
// initial rd_guards= { 2'b11 };
assign rd_guards= {
rd_data[0],
1'b1
};
assign rd_guardsok[0] = 1'b1;
assign rd_guardsok[1] = rd_data[0];
endmodule
|
module t_case_write1_tasks ();
// verilator lint_off WIDTH
// verilator lint_off CASEINCOMPLETE
parameter STRLEN = 78;
task ozonerab;
input [6:0] rab;
inout [STRLEN*8:1] foobar;
// verilator no_inline_task
begin
case (rab[6:0])
7'h00 : foobar = {foobar, " 0"};
7'h01 : foobar = {foobar, " 1"};
7'h02 : foobar = {foobar, " 2"};
7'h03 : foobar = {foobar, " 3"};
7'h04 : foobar = {foobar, " 4"};
7'h05 : foobar = {foobar, " 5"};
7'h06 : foobar = {foobar, " 6"};
7'h07 : foobar = {foobar, " 7"};
7'h08 : foobar = {foobar, " 8"};
7'h09 : foobar = {foobar, " 9"};
7'h0a : foobar = {foobar, " 10"};
7'h0b : foobar = {foobar, " 11"};
7'h0c : foobar = {foobar, " 12"};
7'h0d : foobar = {foobar, " 13"};
7'h0e : foobar = {foobar, " 14"};
7'h0f : foobar = {foobar, " 15"};
7'h10 : foobar = {foobar, " 16"};
7'h11 : foobar = {foobar, " 17"};
7'h12 : foobar = {foobar, " 18"};
7'h13 : foobar = {foobar, " 19"};
7'h14 : foobar = {foobar, " 20"};
7'h15 : foobar = {foobar, " 21"};
7'h16 : foobar = {foobar, " 22"};
7'h17 : foobar = {foobar, " 23"};
7'h18 : foobar = {foobar, " 24"};
7'h19 : foobar = {foobar, " 25"};
7'h1a : foobar = {foobar, " 26"};
7'h1b : foobar = {foobar, " 27"};
7'h1c : foobar = {foobar, " 28"};
7'h1d : foobar = {foobar, " 29"};
7'h1e : foobar = {foobar, " 30"};
7'h1f : foobar = {foobar, " 31"};
7'h20 : foobar = {foobar, " 32"};
7'h21 : foobar = {foobar, " 33"};
7'h22 : foobar = {foobar, " 34"};
7'h23 : foobar = {foobar, " 35"};
7'h24 : foobar = {foobar, " 36"};
7'h25 : foobar = {foobar, " 37"};
7'h26 : foobar = {foobar, " 38"};
7'h27 : foobar = {foobar, " 39"};
7'h28 : foobar = {foobar, " 40"};
7'h29 : foobar = {foobar, " 41"};
7'h2a : foobar = {foobar, " 42"};
7'h2b : foobar = {foobar, " 43"};
7'h2c : foobar = {foobar, " 44"};
7'h2d : foobar = {foobar, " 45"};
7'h2e : foobar = {foobar, " 46"};
7'h2f : foobar = {foobar, " 47"};
7'h30 : foobar = {foobar, " 48"};
7'h31 : foobar = {foobar, " 49"};
7'h32 : foobar = {foobar, " 50"};
7'h33 : foobar = {foobar, " 51"};
7'h34 : foobar = {foobar, " 52"};
7'h35 : foobar = {foobar, " 53"};
7'h36 : foobar = {foobar, " 54"};
7'h37 : foobar = {foobar, " 55"};
7'h38 : foobar = {foobar, " 56"};
7'h39 : foobar = {foobar, " 57"};
7'h3a : foobar = {foobar, " 58"};
7'h3b : foobar = {foobar, " 59"};
7'h3c : foobar = {foobar, " 60"};
7'h3d : foobar = {foobar, " 61"};
7'h3e : foobar = {foobar, " 62"};
7'h3f : foobar = {foobar, " 63"};
7'h40 : foobar = {foobar, " 64"};
7'h41 : foobar = {foobar, " 65"};
7'h42 : foobar = {foobar, " 66"};
7'h43 : foobar = {foobar, " 67"};
7'h44 : foobar = {foobar, " 68"};
7'h45 : foobar = {foobar, " 69"};
7'h46 : foobar = {foobar, " 70"};
7'h47 : foobar = {foobar, " 71"};
7'h48 : foobar = {foobar, " 72"};
7'h49 : foobar = {foobar, " 73"};
7'h4a : foobar = {foobar, " 74"};
7'h4b : foobar = {foobar, " 75"};
7'h4c : foobar = {foobar, " 76"};
7'h4d : foobar = {foobar, " 77"};
7'h4e : foobar = {foobar, " 78"};
7'h4f : foobar = {foobar, " 79"};
7'h50 : foobar = {foobar, " 80"};
7'h51 : foobar = {foobar, " 81"};
7'h52 : foobar = {foobar, " 82"};
7'h53 : foobar = {foobar, " 83"};
7'h54 : foobar = {foobar, " 84"};
7'h55 : foobar = {foobar, " 85"};
7'h56 : foobar = {foobar, " 86"};
7'h57 : foobar = {foobar, " 87"};
7'h58 : foobar = {foobar, " 88"};
7'h59 : foobar = {foobar, " 89"};
7'h5a : foobar = {foobar, " 90"};
7'h5b : foobar = {foobar, " 91"};
7'h5c : foobar = {foobar, " 92"};
7'h5d : foobar = {foobar, " 93"};
7'h5e : foobar = {foobar, " 94"};
7'h5f : foobar = {foobar, " 95"};
7'h60 : foobar = {foobar, " 96"};
7'h61 : foobar = {foobar, " 97"};
7'h62 : foobar = {foobar, " 98"};
7'h63 : foobar = {foobar, " 99"};
7'h64 : foobar = {foobar, " 100"};
7'h65 : foobar = {foobar, " 101"};
7'h66 : foobar = {foobar, " 102"};
7'h67 : foobar = {foobar, " 103"};
7'h68 : foobar = {foobar, " 104"};
7'h69 : foobar = {foobar, " 105"};
7'h6a : foobar = {foobar, " 106"};
7'h6b : foobar = {foobar, " 107"};
7'h6c : foobar = {foobar, " 108"};
7'h6d : foobar = {foobar, " 109"};
7'h6e : foobar = {foobar, " 110"};
7'h6f : foobar = {foobar, " 111"};
7'h70 : foobar = {foobar, " 112"};
7'h71 : foobar = {foobar, " 113"};
7'h72 : foobar = {foobar, " 114"};
7'h73 : foobar = {foobar, " 115"};
7'h74 : foobar = {foobar, " 116"};
7'h75 : foobar = {foobar, " 117"};
7'h76 : foobar = {foobar, " 118"};
7'h77 : foobar = {foobar, " 119"};
7'h78 : foobar = {foobar, " 120"};
7'h79 : foobar = {foobar, " 121"};
7'h7a : foobar = {foobar, " 122"};
7'h7b : foobar = {foobar, " 123"};
7'h7c : foobar = {foobar, " 124"};
7'h7d : foobar = {foobar, " 125"};
7'h7e : foobar = {foobar, " 126"};
7'h7f : foobar = {foobar, " 127"};
default:foobar = {foobar, " 128"};
endcase
end
endtask
task ozonerb;
input [5:0] rb;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rb[5:0])
6'h10,
6'h17,
6'h1e,
6'h1f: foobar = {foobar, " 129"};
default: ozonerab({1'b1, rb}, foobar);
endcase
end
endtask
task ozonef3f4_iext;
input [1:0] foo;
input [15:0] im16;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 :
begin
skyway({4{im16[15]}}, foobar);
skyway({4{im16[15]}}, foobar);
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
foobar = {foobar, " 130"};
end
2'h1 :
begin
foobar = {foobar, " 131"};
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
end
2'h2 :
begin
skyway({4{im16[15]}}, foobar);
skyway({4{im16[15]}}, foobar);
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
foobar = {foobar, " 132"};
end
2'h3 :
begin
foobar = {foobar, " 133"};
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
end
endcase
end
endtask
task skyway;
input [ 3:0] hex;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (hex)
4'h0 : foobar = {foobar, " 134"};
4'h1 : foobar = {foobar, " 135"};
4'h2 : foobar = {foobar, " 136"};
4'h3 : foobar = {foobar, " 137"};
4'h4 : foobar = {foobar, " 138"};
4'h5 : foobar = {foobar, " 139"};
4'h6 : foobar = {foobar, " 140"};
4'h7 : foobar = {foobar, " 141"};
4'h8 : foobar = {foobar, " 142"};
4'h9 : foobar = {foobar, " 143"};
4'ha : foobar = {foobar, " 144"};
4'hb : foobar = {foobar, " 145"};
4'hc : foobar = {foobar, " 146"};
4'hd : foobar = {foobar, " 147"};
4'he : foobar = {foobar, " 148"};
4'hf : foobar = {foobar, " 149"};
endcase
end
endtask
task ozonesr;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[11: 9])
3'h0 : foobar = {foobar, " 158"};
3'h1 : foobar = {foobar, " 159"};
3'h2 : foobar = {foobar, " 160"};
3'h3 : foobar = {foobar, " 161"};
3'h4 : foobar = {foobar, " 162"};
3'h5 : foobar = {foobar, " 163"};
3'h6 : foobar = {foobar, " 164"};
3'h7 : foobar = {foobar, " 165"};
endcase
end
endtask
task ozonejk;
input k;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
if (k)
foobar = {foobar, " 166"};
else
foobar = {foobar, " 167"};
end
endtask
task ozoneae;
input [ 2:0] ae;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ae)
3'b000 : foobar = {foobar, " 168"};
3'b001 : foobar = {foobar, " 169"};
3'b010 : foobar = {foobar, " 170"};
3'b011 : foobar = {foobar, " 171"};
3'b100 : foobar = {foobar, " 172"};
3'b101 : foobar = {foobar, " 173"};
3'b110 : foobar = {foobar, " 174"};
3'b111 : foobar = {foobar, " 175"};
endcase
end
endtask
task ozoneaee;
input [ 2:0] aee;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (aee)
3'b001,
3'b011,
3'b101,
3'b111 : foobar = {foobar, " 176"};
3'b000 : foobar = {foobar, " 177"};
3'b010 : foobar = {foobar, " 178"};
3'b100 : foobar = {foobar, " 179"};
3'b110 : foobar = {foobar, " 180"};
endcase
end
endtask
task ozoneape;
input [ 2:0] ape;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ape)
3'b001,
3'b011,
3'b101,
3'b111 : foobar = {foobar, " 181"};
3'b000 : foobar = {foobar, " 182"};
3'b010 : foobar = {foobar, " 183"};
3'b100 : foobar = {foobar, " 184"};
3'b110 : foobar = {foobar, " 185"};
endcase
end
endtask
task ozonef1;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
if (foo[26])
foobar = {foobar, " 186"};
else
foobar = {foobar, " 187"};
4'h1 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 188"};
2'b01 : foobar = {foobar, " 189"};
2'b10 : foobar = {foobar, " 190"};
2'b11 : foobar = {foobar, " 191"};
endcase
4'h2 : foobar = {foobar, " 192"};
4'h3 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 193"};
2'b01 : foobar = {foobar, " 194"};
2'b10 : foobar = {foobar, " 195"};
2'b11 : foobar = {foobar, " 196"};
endcase
4'h4 :
if (foo[26])
foobar = {foobar, " 197"};
else
foobar = {foobar, " 198"};
4'h5 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 199"};
2'b01 : foobar = {foobar, " 200"};
2'b10 : foobar = {foobar, " 201"};
2'b11 : foobar = {foobar, " 202"};
endcase
4'h6 : foobar = {foobar, " 203"};
4'h7 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 204"};
2'b01 : foobar = {foobar, " 205"};
2'b10 : foobar = {foobar, " 206"};
2'b11 : foobar = {foobar, " 207"};
endcase
4'h8 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 208"};
2'b01 : foobar = {foobar, " 209"};
2'b10 : foobar = {foobar, " 210"};
2'b11 : foobar = {foobar, " 211"};
endcase
4'h9 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 212"};
2'b01 : foobar = {foobar, " 213"};
2'b10 : foobar = {foobar, " 214"};
2'b11 : foobar = {foobar, " 215"};
endcase
4'ha :
if (foo[25])
foobar = {foobar, " 216"};
else
foobar = {foobar, " 217"};
4'hb :
if (foo[25])
foobar = {foobar, " 218"};
else
foobar = {foobar, " 219"};
4'hc :
if (foo[26])
foobar = {foobar, " 220"};
else
foobar = {foobar, " 221"};
4'hd :
case (foo[26:25])
2'b00 : foobar = {foobar, " 222"};
2'b01 : foobar = {foobar, " 223"};
2'b10 : foobar = {foobar, " 224"};
2'b11 : foobar = {foobar, " 225"};
endcase
4'he :
case (foo[26:25])
2'b00 : foobar = {foobar, " 226"};
2'b01 : foobar = {foobar, " 227"};
2'b10 : foobar = {foobar, " 228"};
2'b11 : foobar = {foobar, " 229"};
endcase
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar, " 230"};
2'b01 : foobar = {foobar, " 231"};
2'b10 : foobar = {foobar, " 232"};
2'b11 : foobar = {foobar, " 233"};
endcase
endcase
end
endtask
task ozonef1e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[27:21])
7'h00:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 234"};
foobar = {foobar, " 235"};
end
7'h01:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 236"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 237"};
foobar = {foobar, " 238"};
end
7'h02:
foobar = {foobar, " 239"};
7'h03:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 240"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 241"};
foobar = {foobar, " 242"};
end
7'h04:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 243"};
foobar = {foobar," 244"};
end
7'h05:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 245"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 246"};
end
7'h06:
foobar = {foobar, " 247"};
7'h07:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 248"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 249"};
end
7'h08:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 250"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 251"};
end
7'h09:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 252"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 253"};
end
7'h0a:
begin
ozoneae(foo[17:15], foobar);
foobar = {foobar," 254"};
end
7'h0b:
begin
ozoneae(foo[17:15], foobar);
foobar = {foobar," 255"};
end
7'h0c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 256"};
end
7'h0d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 257"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 258"};
end
7'h0e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 259"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 260"};
end
7'h0f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 261"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 262"};
end
7'h10:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 263"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 264"};
foobar = {foobar, " 265"};
foobar = {foobar, " 266"};
end
7'h11:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 267"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 268"};
foobar = {foobar, " 269"};
foobar = {foobar, " 270"};
end
7'h12:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 271"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 272"};
foobar = {foobar, " 273"};
foobar = {foobar, " 274"};
end
7'h13:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 275"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 276"};
foobar = {foobar, " 277"};
foobar = {foobar, " 278"};
end
7'h14:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 279"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 280"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 281"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 282"};
foobar = {foobar, " 283"};
foobar = {foobar, " 284"};
end
7'h15:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 285"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 286"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 287"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 288"};
foobar = {foobar, " 289"};
foobar = {foobar, " 290"};
end
7'h16:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 291"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 292"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 293"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 294"};
foobar = {foobar, " 295"};
foobar = {foobar, " 296"};
end
7'h17:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 297"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 298"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 299"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 300"};
foobar = {foobar, " 301"};
foobar = {foobar, " 302"};
end
7'h18:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 303"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 304"};
foobar = {foobar, " 305"};
foobar = {foobar, " 306"};
end
7'h19:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 307"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 308"};
foobar = {foobar, " 309"};
foobar = {foobar, " 310"};
end
7'h1a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 311"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 312"};
foobar = {foobar, " 313"};
foobar = {foobar, " 314"};
end
7'h1b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 315"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 316"};
foobar = {foobar, " 317"};
foobar = {foobar, " 318"};
end
7'h1c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 319"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 320"};
foobar = {foobar, " 321"};
foobar = {foobar, " 322"};
end
7'h1d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 323"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 324"};
foobar = {foobar, " 325"};
foobar = {foobar, " 326"};
end
7'h1e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 327"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 328"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 329"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 330"};
foobar = {foobar, " 331"};
foobar = {foobar, " 332"};
end
7'h1f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 333"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 334"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 335"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 336"};
foobar = {foobar, " 337"};
foobar = {foobar, " 338"};
end
7'h20:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 339"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 340"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 341"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 342"};
foobar = {foobar, " 343"};
foobar = {foobar, " 344"};
end
7'h21:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 345"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 346"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 347"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 348"};
foobar = {foobar, " 349"};
foobar = {foobar, " 350"};
end
7'h22:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 351"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 352"};
foobar = {foobar, " 353"};
foobar = {foobar, " 354"};
end
7'h23:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 355"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 356"};
foobar = {foobar, " 357"};
foobar = {foobar, " 358"};
end
7'h24:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 359"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 360"};
foobar = {foobar, " 361"};
foobar = {foobar, " 362"};
end
7'h25:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 363"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 364"};
foobar = {foobar, " 365"};
foobar = {foobar, " 366"};
end
7'h26:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 367"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 368"};
foobar = {foobar, " 369"};
foobar = {foobar, " 370"};
end
7'h27:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 371"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 372"};
foobar = {foobar, " 373"};
foobar = {foobar, " 374"};
end
7'h28:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 375"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 376"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 377"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 378"};
foobar = {foobar, " 379"};
foobar = {foobar, " 380"};
end
7'h29:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 381"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 382"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 383"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 384"};
foobar = {foobar, " 385"};
foobar = {foobar, " 386"};
end
7'h2a:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 387"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 388"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 389"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 390"};
foobar = {foobar, " 391"};
foobar = {foobar, " 392"};
end
7'h2b:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 393"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 394"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 395"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 396"};
foobar = {foobar, " 397"};
foobar = {foobar, " 398"};
end
7'h2c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 399"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 400"};
foobar = {foobar, " 401"};
foobar = {foobar, " 402"};
end
7'h2d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 403"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 404"};
foobar = {foobar, " 405"};
foobar = {foobar, " 406"};
end
7'h2e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 407"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 408"};
foobar = {foobar, " 409"};
foobar = {foobar, " 410"};
end
7'h2f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 411"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 412"};
foobar = {foobar, " 413"};
foobar = {foobar, " 414"};
end
7'h30:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 415"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 416"};
foobar = {foobar, " 417"};
foobar = {foobar, " 418"};
end
7'h31:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 419"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 420"};
foobar = {foobar, " 421"};
foobar = {foobar, " 422"};
end
7'h32:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 423"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 424"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 425"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 426"};
foobar = {foobar, " 427"};
foobar = {foobar, " 428"};
end
7'h33:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 429"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 430"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 431"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 432"};
foobar = {foobar, " 433"};
foobar = {foobar, " 434"};
end
7'h34:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 435"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 436"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 437"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 438"};
foobar = {foobar, " 439"};
foobar = {foobar, " 440"};
end
7'h35:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 441"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 442"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 443"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 444"};
foobar = {foobar, " 445"};
foobar = {foobar, " 446"};
end
7'h36:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 447"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 448"};
foobar = {foobar, " 449"};
foobar = {foobar, " 450"};
end
7'h37:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 451"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 452"};
foobar = {foobar, " 453"};
foobar = {foobar, " 454"};
end
7'h38:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 455"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 456"};
foobar = {foobar, " 457"};
end
7'h39:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 458"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 459"};
foobar = {foobar, " 460"};
end
7'h3a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 461"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 462"};
foobar = {foobar, " 463"};
end
7'h3b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 464"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 465"};
foobar = {foobar, " 466"};
end
7'h3c:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 467"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 468"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 469"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 470"};
foobar = {foobar, " 471"};
end
7'h3d:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 472"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 473"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 474"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 475"};
foobar = {foobar, " 476"};
end
7'h3e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 477"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 478"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 479"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 480"};
foobar = {foobar, " 481"};
end
7'h3f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 482"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 483"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 484"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 485"};
foobar = {foobar, " 486"};
end
7'h40:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 487"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 488"};
foobar = {foobar, " 489"};
foobar = {foobar, " 490"};
end
7'h41:
begin
foobar = {foobar, " 491"};
foobar = {foobar, " 492"};
end
7'h42:
begin
foobar = {foobar, " 493"};
foobar = {foobar, " 494"};
end
7'h43:
begin
foobar = {foobar, " 495"};
foobar = {foobar, " 496"};
end
7'h44:
begin
foobar = {foobar, " 497"};
foobar = {foobar, " 498"};
end
7'h45:
foobar = {foobar, " 499"};
7'h46:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 500"};
foobar = {foobar, " 501"};
foobar = {foobar, " 502"};
end
7'h47:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 503"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 504"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 505"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 506"};
foobar = {foobar, " 507"};
foobar = {foobar, " 508"};
end
7'h48:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 509"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 510"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 511"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 512"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 513"};
end
7'h49:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 514"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 515"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 516"};
end
7'h4a:
foobar = {foobar," 517"};
7'h4b:
foobar = {foobar, " 518"};
7'h4c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 519"};
foobar = {foobar, " 520"};
foobar = {foobar, " 521"};
end
7'h4d:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 522"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 523"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 524"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 525"};
foobar = {foobar, " 526"};
foobar = {foobar, " 527"};
end
7'h4e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 528"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 529"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 530"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 531"};
end
7'h4f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 532"};
end
7'h50:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 533"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 534"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 535"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 536"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 537"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 538"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 539"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 540"};
end
7'h51:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 541"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 542"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 543"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 544"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 545"};
end
7'h52:
foobar = {foobar, " 546"};
7'h53:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 547"};
end
7'h54:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 548"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 549"};
end
7'h55:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 550"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 551"};
end
7'h56:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 552"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 553"};
foobar = {foobar, " 554"};
end
7'h57:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 555"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 556"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 557"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 558"};
end
7'h58:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 559"};
end
7'h59:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 560"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 561"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 562"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 563"};
end
7'h5a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 564"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 565"};
end
7'h5b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 566"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 567"};
end
7'h5c:
begin
foobar = {foobar," 568"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 569"};
foobar = {foobar," 570"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 571"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 572"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar, " 573"};
end
7'h5d:
begin
foobar = {foobar," 574"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 575"};
foobar = {foobar," 576"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 577"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 578"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar, " 579"};
end
7'h5e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 580"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 581"};
end
7'h5f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 582"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 583"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 584"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 585"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 586"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 587"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 588"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 589"};
end
7'h60:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 590"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 591"};
end
7'h61:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 592"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 593"};
end
7'h62:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 594"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 595"};
end
7'h63:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 596"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 597"};
end
7'h64:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 598"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 599"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 600"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 601"};
end
7'h65:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 602"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 603"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 604"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 605"};
end
7'h66:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 606"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 607"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 608"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 609"};
end
7'h67:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 610"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 611"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 612"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 613"};
end
7'h68:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 614"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 615"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 616"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 617"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 618"};
ozoneape(foo[17:15], foobar);
end
7'h69:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 619"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 620"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 621"};
end
7'h6a:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 622"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 623"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 624"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 625"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 626"};
ozoneae(foo[17:15], foobar);
end
7'h6b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 627"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 628"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 629"};
end
7'h6c:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 630"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 631"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 632"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 633"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 634"};
ozoneae(foo[17:15], foobar);
end
7'h6d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 635"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 636"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 637"};
end
7'h6e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 638"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 639"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 640"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 641"};
end
7'h6f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 642"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 643"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 644"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 645"};
end
7'h70:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 646"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 647"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 648"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 649"};
end
7'h71:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 650"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 651"};
end
7'h72:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 652"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 653"};
end
7'h73:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 654"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 655"};
ozoneae(foo[17:15], foobar);
end
7'h74:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 656"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 657"};
ozoneae(foo[17:15], foobar);
end
7'h75:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 658"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 659"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 660"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 661"};
foobar = {foobar, " 662"};
foobar = {foobar, " 663"};
end
7'h76:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 664"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 665"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 666"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 667"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 668"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 669"};
end
7'h77:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 670"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 671"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 672"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 673"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 674"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 675"};
end
7'h78,
7'h79,
7'h7a,
7'h7b,
7'h7c,
7'h7d,
7'h7e,
7'h7f:
foobar = {foobar," 676"};
endcase
end
endtask
task ozonef2;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
case (foo[26:25])
2'b00 : foobar = {foobar," 677"};
2'b01 : foobar = {foobar," 678"};
2'b10 : foobar = {foobar," 679"};
2'b11 : foobar = {foobar," 680"};
endcase
4'h1 :
case (foo[26:25])
2'b00 : foobar = {foobar," 681"};
2'b01 : foobar = {foobar," 682"};
2'b10 : foobar = {foobar," 683"};
2'b11 : foobar = {foobar," 684"};
endcase
4'h2 :
case (foo[26:25])
2'b00 : foobar = {foobar," 685"};
2'b01 : foobar = {foobar," 686"};
2'b10 : foobar = {foobar," 687"};
2'b11 : foobar = {foobar," 688"};
endcase
4'h3 :
case (foo[26:25])
2'b00 : foobar = {foobar," 689"};
2'b01 : foobar = {foobar," 690"};
2'b10 : foobar = {foobar," 691"};
2'b11 : foobar = {foobar," 692"};
endcase
4'h4 :
case (foo[26:25])
2'b00 : foobar = {foobar," 693"};
2'b01 : foobar = {foobar," 694"};
2'b10 : foobar = {foobar," 695"};
2'b11 : foobar = {foobar," 696"};
endcase
4'h5 :
case (foo[26:25])
2'b00 : foobar = {foobar," 697"};
2'b01 : foobar = {foobar," 698"};
2'b10 : foobar = {foobar," 699"};
2'b11 : foobar = {foobar," 700"};
endcase
4'h6 :
case (foo[26:25])
2'b00 : foobar = {foobar," 701"};
2'b01 : foobar = {foobar," 702"};
2'b10 : foobar = {foobar," 703"};
2'b11 : foobar = {foobar," 704"};
endcase
4'h7 :
case (foo[26:25])
2'b00 : foobar = {foobar," 705"};
2'b01 : foobar = {foobar," 706"};
2'b10 : foobar = {foobar," 707"};
2'b11 : foobar = {foobar," 708"};
endcase
4'h8 :
if (foo[26])
foobar = {foobar," 709"};
else
foobar = {foobar," 710"};
4'h9 :
case (foo[26:25])
2'b00 : foobar = {foobar," 711"};
2'b01 : foobar = {foobar," 712"};
2'b10 : foobar = {foobar," 713"};
2'b11 : foobar = {foobar," 714"};
endcase
4'ha :
case (foo[26:25])
2'b00 : foobar = {foobar," 715"};
2'b01 : foobar = {foobar," 716"};
2'b10 : foobar = {foobar," 717"};
2'b11 : foobar = {foobar," 718"};
endcase
4'hb :
case (foo[26:25])
2'b00 : foobar = {foobar," 719"};
2'b01 : foobar = {foobar," 720"};
2'b10 : foobar = {foobar," 721"};
2'b11 : foobar = {foobar," 722"};
endcase
4'hc :
if (foo[26])
foobar = {foobar," 723"};
else
foobar = {foobar," 724"};
4'hd :
case (foo[26:25])
2'b00 : foobar = {foobar," 725"};
2'b01 : foobar = {foobar," 726"};
2'b10 : foobar = {foobar," 727"};
2'b11 : foobar = {foobar," 728"};
endcase
4'he :
case (foo[26:25])
2'b00 : foobar = {foobar," 729"};
2'b01 : foobar = {foobar," 730"};
2'b10 : foobar = {foobar," 731"};
2'b11 : foobar = {foobar," 732"};
endcase
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar," 733"};
2'b01 : foobar = {foobar," 734"};
2'b10 : foobar = {foobar," 735"};
2'b11 : foobar = {foobar," 736"};
endcase
endcase
end
endtask
task ozonef2e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
casez (foo[25:21])
5'h00 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 737"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 738"};
end
5'h01 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 739"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 740"};
end
5'h02 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 741"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 742"};
end
5'h03 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 743"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 744"};
end
5'h04 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 745"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 746"};
end
5'h05 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 747"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 748"};
end
5'h06 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 749"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 750"};
end
5'h07 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 751"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 752"};
end
5'h08 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 753"};
if (foo[ 6])
foobar = {foobar," 754"};
else
foobar = {foobar," 755"};
end
5'h09 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 756"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 757"};
end
5'h0a :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 758"};
ozoneae(foo[17:15], foobar);
end
5'h0b :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 759"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 760"};
end
5'h0c :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 761"};
end
5'h0d :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 762"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 763"};
end
5'h0e :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 764"};
ozoneae(foo[17:15], foobar);
end
5'h0f :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 765"};
ozoneae(foo[17:15], foobar);
end
5'h10 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 766"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 767"};
end
5'h11 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 768"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 769"};
end
5'h18 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 770"};
if (foo[ 6])
foobar = {foobar," 771"};
else
foobar = {foobar," 772"};
end
5'h1a :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 773"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 774"};
end
5'h1b :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 775"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 776"};
if (foo[ 6])
foobar = {foobar," 777"};
else
foobar = {foobar," 778"};
foobar = {foobar," 779"};
end
5'h1c :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 780"};
end
5'h1d :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 781"};
if (foo[ 6])
foobar = {foobar," 782"};
else
foobar = {foobar," 783"};
foobar = {foobar," 784"};
end
5'h1e :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 785"};
if (foo[ 6])
foobar = {foobar," 786"};
else
foobar = {foobar," 787"};
foobar = {foobar," 788"};
end
5'h1f :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 789"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 790"};
if (foo[ 6])
foobar = {foobar," 791"};
else
foobar = {foobar," 792"};
foobar = {foobar," 793"};
end
default :
foobar = {foobar," 794"};
endcase
end
endtask
task ozonef3e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[25:21])
5'h00,
5'h01,
5'h02:
begin
ozoneae(foo[20:18], foobar);
case (foo[22:21])
2'h0: foobar = {foobar," 795"};
2'h1: foobar = {foobar," 796"};
2'h2: foobar = {foobar," 797"};
endcase
ozoneae(foo[17:15], foobar);
foobar = {foobar," 798"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
foobar = {foobar," 799"};
end
5'h08,
5'h09,
5'h0d,
5'h0e,
5'h0f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 800"};
ozoneae(foo[17:15], foobar);
case (foo[23:21])
3'h0: foobar = {foobar," 801"};
3'h1: foobar = {foobar," 802"};
3'h5: foobar = {foobar," 803"};
3'h6: foobar = {foobar," 804"};
3'h7: foobar = {foobar," 805"};
endcase
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
end
5'h0a,
5'h0b:
begin
ozoneae(foo[17:15], foobar);
if (foo[21])
foobar = {foobar," 806"};
else
foobar = {foobar," 807"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
end
5'h0c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 808"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
foobar = {foobar," 809"};
ozoneae(foo[17:15], foobar);
end
5'h10,
5'h11,
5'h12,
5'h13:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 810"};
ozoneae(foo[17:15], foobar);
case (foo[22:21])
2'h0,
2'h2:
foobar = {foobar," 811"};
2'h1,
2'h3:
foobar = {foobar," 812"};
endcase
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar," 813"};
ozoneae((foo[20:18]+1), foobar);
foobar = {foobar," 814"};
ozoneae((foo[17:15]+1), foobar);
case (foo[22:21])
2'h0,
2'h3:
foobar = {foobar," 815"};
2'h1,
2'h2:
foobar = {foobar," 816"};
endcase
ozoneae((foo[ 8: 6]+1), foobar);
end
5'h18:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 817"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 818"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar," 819"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 820"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 821"};
ozoneae(foo[ 8: 6], foobar);
end
default :
foobar = {foobar," 822"};
endcase
end
endtask
task ozonef3e_te;
input [ 2:0] te;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (te)
3'b100 : foobar = {foobar, " 823"};
3'b101 : foobar = {foobar, " 824"};
3'b110 : foobar = {foobar, " 825"};
default: foobar = {foobar, " 826"};
endcase
end
endtask
task ozonearm;
input [ 2:0] ate;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ate)
3'b000 : foobar = {foobar, " 827"};
3'b001 : foobar = {foobar, " 828"};
3'b010 : foobar = {foobar, " 829"};
3'b011 : foobar = {foobar, " 830"};
3'b100 : foobar = {foobar, " 831"};
3'b101 : foobar = {foobar, " 832"};
3'b110 : foobar = {foobar, " 833"};
3'b111 : foobar = {foobar, " 834"};
endcase
end
endtask
task ozonebmuop;
input [ 4:0] f4;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (f4[ 4:0])
5'h00,
5'h04 :
foobar = {foobar, " 835"};
5'h01,
5'h05 :
foobar = {foobar, " 836"};
5'h02,
5'h06 :
foobar = {foobar, " 837"};
5'h03,
5'h07 :
foobar = {foobar, " 838"};
5'h08,
5'h18 :
foobar = {foobar, " 839"};
5'h09,
5'h19 :
foobar = {foobar, " 840"};
5'h0a,
5'h1a :
foobar = {foobar, " 841"};
5'h0b :
foobar = {foobar, " 842"};
5'h1b :
foobar = {foobar, " 843"};
5'h0c,
5'h1c :
foobar = {foobar, " 844"};
5'h0d,
5'h1d :
foobar = {foobar, " 845"};
5'h1e :
foobar = {foobar, " 846"};
endcase
end
endtask
task ozonef3;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
reg nacho;
// verilator no_inline_task
begin : f3_body
nacho = 1'b0;
case (foo[24:21])
4'h0:
case (foo[26:25])
2'b00 : foobar = {foobar, " 847"};
2'b01 : foobar = {foobar, " 848"};
2'b10 : foobar = {foobar, " 849"};
2'b11 : foobar = {foobar, " 850"};
endcase
4'h1:
case (foo[26:25])
2'b00 : foobar = {foobar, " 851"};
2'b01 : foobar = {foobar, " 852"};
2'b10 : foobar = {foobar, " 853"};
2'b11 : foobar = {foobar, " 854"};
endcase
4'h2:
case (foo[26:25])
2'b00 : foobar = {foobar, " 855"};
2'b01 : foobar = {foobar, " 856"};
2'b10 : foobar = {foobar, " 857"};
2'b11 : foobar = {foobar, " 858"};
endcase
4'h8,
4'h9,
4'hd,
4'he,
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar, " 859"};
2'b01 : foobar = {foobar, " 860"};
2'b10 : foobar = {foobar, " 861"};
2'b11 : foobar = {foobar, " 862"};
endcase
4'ha,
4'hb :
if (foo[25])
foobar = {foobar, " 863"};
else
foobar = {foobar, " 864"};
4'hc :
if (foo[26])
foobar = {foobar, " 865"};
else
foobar = {foobar, " 866"};
default :
begin
foobar = {foobar, " 867"};
nacho = 1'b1;
end
endcase
if (~nacho)
begin
case (foo[24:21])
4'h8 :
foobar = {foobar, " 868"};
4'h9 :
foobar = {foobar, " 869"};
4'ha,
4'he :
foobar = {foobar, " 870"};
4'hb,
4'hf :
foobar = {foobar, " 871"};
4'hd :
foobar = {foobar, " 872"};
endcase
if (foo[20])
case (foo[18:16])
3'b000 : foobar = {foobar, " 873"};
3'b100 : foobar = {foobar, " 874"};
default: foobar = {foobar, " 875"};
endcase
else
ozoneae(foo[18:16], foobar);
if (foo[24:21] === 4'hc)
if (foo[25])
foobar = {foobar, " 876"};
else
foobar = {foobar, " 877"};
case (foo[24:21])
4'h0,
4'h1,
4'h2:
foobar = {foobar, " 878"};
endcase
end
end
endtask
task ozonerx;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[19:18])
2'h0 : foobar = {foobar, " 879"};
2'h1 : foobar = {foobar, " 880"};
2'h2 : foobar = {foobar, " 881"};
2'h3 : foobar = {foobar, " 882"};
endcase
case (foo[17:16])
2'h1 : foobar = {foobar, " 883"};
2'h2 : foobar = {foobar, " 884"};
2'h3 : foobar = {foobar, " 885"};
endcase
end
endtask
task ozonerme;
input [ 2:0] rme;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rme)
3'h0 : foobar = {foobar, " 886"};
3'h1 : foobar = {foobar, " 887"};
3'h2 : foobar = {foobar, " 888"};
3'h3 : foobar = {foobar, " 889"};
3'h4 : foobar = {foobar, " 890"};
3'h5 : foobar = {foobar, " 891"};
3'h6 : foobar = {foobar, " 892"};
3'h7 : foobar = {foobar, " 893"};
endcase
end
endtask
task ozoneye;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = {foobar, " 894"};
ozonerme(ye[5:3],foobar);
case ({ye[ 2:0], l})
4'h2,
4'ha: foobar = {foobar, " 895"};
4'h4,
4'hb: foobar = {foobar, " 896"};
4'h6,
4'he: foobar = {foobar, " 897"};
4'h8,
4'hc: foobar = {foobar, " 898"};
endcase
end
endtask
task ozonef1e_ye;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = {foobar, " 899"};
ozonerme(ye[5:3],foobar);
ozonef1e_inc_dec(ye[5:0], l ,foobar);
end
endtask
task ozonef1e_h;
input [ 2:0] e;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
if (e[ 2:0] <= 3'h4)
foobar = {foobar, " 900"};
end
endtask
task ozonef1e_inc_dec;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case ({ye[ 2:0], l})
4'h2,
4'h3,
4'ha: foobar = {foobar, " 901"};
4'h4,
4'h5,
4'hb: foobar = {foobar, " 902"};
4'h6,
4'h7,
4'he: foobar = {foobar, " 903"};
4'h8,
4'h9,
4'hc: foobar = {foobar, " 904"};
4'hf: foobar = {foobar, " 905"};
endcase
end
endtask
task ozonef1e_hl;
input [ 2:0] e;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case ({e[ 2:0], l})
4'h0,
4'h2,
4'h4,
4'h6,
4'h8: foobar = {foobar, " 906"};
4'h1,
4'h3,
4'h5,
4'h7,
4'h9: foobar = {foobar, " 907"};
endcase
end
endtask
task ozonexe;
input [ 3:0] xe;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (xe[3])
1'b0 : foobar = {foobar, " 908"};
1'b1 : foobar = {foobar, " 909"};
endcase
case (xe[ 2:0])
3'h1,
3'h5: foobar = {foobar, " 910"};
3'h2,
3'h6: foobar = {foobar, " 911"};
3'h3,
3'h7: foobar = {foobar, " 912"};
3'h4: foobar = {foobar, " 913"};
endcase
end
endtask
task ozonerp;
input [ 2:0] rp;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rp)
3'h0 : foobar = {foobar, " 914"};
3'h1 : foobar = {foobar, " 915"};
3'h2 : foobar = {foobar, " 916"};
3'h3 : foobar = {foobar, " 917"};
3'h4 : foobar = {foobar, " 918"};
3'h5 : foobar = {foobar, " 919"};
3'h6 : foobar = {foobar, " 920"};
3'h7 : foobar = {foobar, " 921"};
endcase
end
endtask
task ozonery;
input [ 3:0] ry;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ry)
4'h0 : foobar = {foobar, " 922"};
4'h1 : foobar = {foobar, " 923"};
4'h2 : foobar = {foobar, " 924"};
4'h3 : foobar = {foobar, " 925"};
4'h4 : foobar = {foobar, " 926"};
4'h5 : foobar = {foobar, " 927"};
4'h6 : foobar = {foobar, " 928"};
4'h7 : foobar = {foobar, " 929"};
4'h8 : foobar = {foobar, " 930"};
4'h9 : foobar = {foobar, " 931"};
4'ha : foobar = {foobar, " 932"};
4'hb : foobar = {foobar, " 933"};
4'hc : foobar = {foobar, " 934"};
4'hd : foobar = {foobar, " 935"};
4'he : foobar = {foobar, " 936"};
4'hf : foobar = {foobar, " 937"};
endcase
end
endtask
task ozonearx;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[1:0])
2'h0 : foobar = {foobar, " 938"};
2'h1 : foobar = {foobar, " 939"};
2'h2 : foobar = {foobar, " 940"};
2'h3 : foobar = {foobar, " 941"};
endcase
end
endtask
task ozonef3f4imop;
input [ 4:0] f3f4iml;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
casez (f3f4iml)
5'b000??: foobar = {foobar, " 942"};
5'b001??: foobar = {foobar, " 943"};
5'b?10??: foobar = {foobar, " 944"};
5'b0110?: foobar = {foobar, " 945"};
5'b01110: foobar = {foobar, " 946"};
5'b01111: foobar = {foobar, " 947"};
5'b10???: foobar = {foobar, " 948"};
5'b11100: foobar = {foobar, " 949"};
5'b11101: foobar = {foobar, " 950"};
5'b11110: foobar = {foobar, " 951"};
5'b11111: foobar = {foobar, " 952"};
endcase
end
endtask
task ozonecon;
input [ 4:0] con;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (con)
5'h00 : foobar = {foobar, " 953"};
5'h01 : foobar = {foobar, " 954"};
5'h02 : foobar = {foobar, " 955"};
5'h03 : foobar = {foobar, " 956"};
5'h04 : foobar = {foobar, " 957"};
5'h05 : foobar = {foobar, " 958"};
5'h06 : foobar = {foobar, " 959"};
5'h07 : foobar = {foobar, " 960"};
5'h08 : foobar = {foobar, " 961"};
5'h09 : foobar = {foobar, " 962"};
5'h0a : foobar = {foobar, " 963"};
5'h0b : foobar = {foobar, " 964"};
5'h0c : foobar = {foobar, " 965"};
5'h0d : foobar = {foobar, " 966"};
5'h0e : foobar = {foobar, " 967"};
5'h0f : foobar = {foobar, " 968"};
5'h10 : foobar = {foobar, " 969"};
5'h11 : foobar = {foobar, " 970"};
5'h12 : foobar = {foobar, " 971"};
5'h13 : foobar = {foobar, " 972"};
5'h14 : foobar = {foobar, " 973"};
5'h15 : foobar = {foobar, " 974"};
5'h16 : foobar = {foobar, " 975"};
5'h17 : foobar = {foobar, " 976"};
5'h18 : foobar = {foobar, " 977"};
5'h19 : foobar = {foobar, " 978"};
5'h1a : foobar = {foobar, " 979"};
5'h1b : foobar = {foobar, " 980"};
5'h1c : foobar = {foobar, " 981"};
5'h1d : foobar = {foobar, " 982"};
5'h1e : foobar = {foobar, " 983"};
5'h1f : foobar = {foobar, " 984"};
endcase
end
endtask
task ozonedr;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[ 9: 6])
4'h0 : foobar = {foobar, " 985"};
4'h1 : foobar = {foobar, " 986"};
4'h2 : foobar = {foobar, " 987"};
4'h3 : foobar = {foobar, " 988"};
4'h4 : foobar = {foobar, " 989"};
4'h5 : foobar = {foobar, " 990"};
4'h6 : foobar = {foobar, " 991"};
4'h7 : foobar = {foobar, " 992"};
4'h8 : foobar = {foobar, " 993"};
4'h9 : foobar = {foobar, " 994"};
4'ha : foobar = {foobar, " 995"};
4'hb : foobar = {foobar, " 996"};
4'hc : foobar = {foobar, " 997"};
4'hd : foobar = {foobar, " 998"};
4'he : foobar = {foobar, " 999"};
4'hf : foobar = {foobar, " 1000"};
endcase
end
endtask
task ozoneshift;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[ 4: 3])
2'h0 : foobar = {foobar, " 1001"};
2'h1 : foobar = {foobar, " 1002"};
2'h2 : foobar = {foobar, " 1003"};
2'h3 : foobar = {foobar, " 1004"};
endcase
end
endtask
task ozoneacc;
input foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 : foobar = {foobar, " 1005"};
2'h1 : foobar = {foobar, " 1006"};
endcase
end
endtask
task ozonehl;
input foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 : foobar = {foobar, " 1007"};
2'h1 : foobar = {foobar, " 1008"};
endcase
end
endtask
task dude;
inout [STRLEN*8: 1] foobar;
reg [ 7:0] temp;
integer i;
reg nacho;
// verilator no_inline_task
begin : justify_block
nacho = 1'b0;
for (i=STRLEN-1; i>1; i=i-1)
begin
temp = foobar>>((STRLEN-1)*8);
if (temp || nacho)
nacho = 1'b1;
else
begin
foobar = foobar<<8;
foobar[8:1] = 32;
end
end
end
endtask
task big_case;
input [ 31:0] fd;
input [ 31:0] foo;
reg [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = " 1009";
if (&foo === 1'bx)
$fwrite(fd, " 1010");
else
casez ( {foo[31:26], foo[19:15], foo[5:0]} )
17'b00_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1011"};
ozoneacc(~foo[26], foobar);
ozonehl(foo[20], foobar);
foobar = {foobar, " 1012"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1013:%s", foobar);
end
17'b01_001?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1014"};
ozonerx(foo, foobar);
foobar = {foobar, " 1015"};
foobar = {foobar, " 1016"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1017:%s", foobar);
end
17'b10_100?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1018"};
ozonerx(foo, foobar);
foobar = {foobar, " 1019"};
foobar = {foobar, " 1020"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1021:%s", foobar);
end
17'b10_101?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1022"};
if (foo[20])
begin
foobar = {foobar, " 1023"};
ozoneacc(foo[18], foobar);
foobar = {foobar, " 1024"};
foobar = {foobar, " 1025"};
if (foo[19])
foobar = {foobar, " 1026"};
else
foobar = {foobar, " 1027"};
end
else
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1028:%s", foobar);
end
17'b10_110?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1029"};
foobar = {foobar, " 1030"};
ozonehl(foo[20], foobar);
foobar = {foobar, " 1031"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1032:%s", foobar);
end
17'b10_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1033"};
foobar = {foobar, " 1034"};
ozonehl(foo[20], foobar);
foobar = {foobar, " 1035"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1036:%s", foobar);
end
17'b11_001?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1037"};
ozonerx(foo, foobar);
foobar = {foobar, " 1038"};
foobar = {foobar, " 1039"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1040:%s", foobar);
end
17'b11_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1041"};
foobar = {foobar, " 1042"};
ozonerx(foo, foobar);
foobar = {foobar, " 1043"};
if (foo[20])
foobar = {foobar, " 1044"};
else
foobar = {foobar, " 1045"};
dude(foobar);
$fwrite (fd, " 1046:%s", foobar);
end
17'b00_10??_?_????_?1_1111 :
casez (foo[11: 5])
7'b??_0_010_0:
begin
foobar = " 1047";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1048"};
ozonef1e(foo, foobar);
dude(foobar);
$fwrite (fd, " 1049:%s", foobar);
end
7'b00_?_110_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1050"};
case ({foo[ 9],foo[ 5]})
2'b00:
begin
foobar = {foobar, " 1051"};
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
end
2'b01:
begin
foobar = {foobar, " 1052"};
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
end
2'b10:
begin
foobar = {foobar, " 1053"};
ozoneae(foo[14:12], foobar);
end
2'b11: foobar = {foobar, " 1054"};
endcase
dude(foobar);
$fwrite (fd, " 1055:%s", foobar);
end
7'b01_?_110_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1056"};
case ({foo[ 9],foo[ 5]})
2'b00:
begin
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
foobar = {foobar, " 1057"};
end
2'b01:
begin
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
foobar = {foobar, " 1058"};
end
2'b10:
begin
ozoneae(foo[14:12], foobar);
foobar = {foobar, " 1059"};
end
2'b11: foobar = {foobar, " 1060"};
endcase
dude(foobar);
$fwrite (fd, " 1061:%s", foobar);
end
7'b10_0_110_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1062"};
foobar = {foobar, " 1063"};
if (foo[12])
foobar = {foobar, " 1064"};
else
ozonerab({4'b1001, foo[14:12]}, foobar);
dude(foobar);
$fwrite (fd, " 1065:%s", foobar);
end
7'b10_0_110_1:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1066"};
if (foo[12])
foobar = {foobar, " 1067"};
else
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1068"};
dude(foobar);
$fwrite (fd, " 1069:%s", foobar);
end
7'b??_?_000_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1070"};
foobar = {foobar, " 1071"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1072"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1073:%s", foobar);
end
7'b??_?_100_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1074"};
foobar = {foobar, " 1075"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1076"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1077:%s", foobar);
end
7'b??_?_001_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1078"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1079"};
foobar = {foobar, " 1080"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1081:%s", foobar);
end
7'b??_?_011_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1082"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1083"};
foobar = {foobar, " 1084"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1085:%s", foobar);
end
7'b??_?_101_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1086"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1087:%s", foobar);
end
endcase
17'b00_10??_?_????_?0_0110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1088"};
ozoneae(foo[ 8: 6], foobar);
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1089"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1090:%s", foobar);
end
17'b00_10??_?_????_00_0111 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1091"};
if (foo[ 6])
foobar = {foobar, " 1092"};
else
ozonerab({4'b1001, foo[ 8: 6]}, foobar);
foobar = {foobar, " 1093"};
foobar = {foobar, " 1094"};
ozonerme(foo[14:12],foobar);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0,foobar);
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1095"};
endcase
dude(foobar);
$fwrite (fd, " 1096:%s", foobar);
end
17'b00_10??_?_????_?0_0100 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1097"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1098"};
ozoneae(foo[ 8: 6], foobar);
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1099:%s", foobar);
end
17'b00_10??_?_????_10_0111 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1100"};
foobar = {foobar, " 1101"};
ozonerme(foo[14:12],foobar);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0,foobar);
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1102"};
endcase
foobar = {foobar, " 1103"};
if (foo[ 6])
foobar = {foobar, " 1104"};
else
ozonerab({4'b1001, foo[ 8: 6]}, foobar);
dude(foobar);
$fwrite (fd, " 1105:%s", foobar);
end
17'b00_10??_?_????_?0_1110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1106"};
case (foo[11:9])
3'h2:
begin
foobar = {foobar, " 1107"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1108"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1109"};
end
3'h6:
begin
foobar = {foobar, " 1110"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1111"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1112"};
end
3'h0:
begin
foobar = {foobar, " 1113"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1114"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1115"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1116"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h1:
begin
foobar = {foobar, " 1117"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1118"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1119"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1120"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h4:
begin
foobar = {foobar, " 1121"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1122"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1123"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1124"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h5:
begin
foobar = {foobar, " 1125"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1126"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1127"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1128"};
else
ozonexe(foo[ 8: 5], foobar);
end
endcase
dude(foobar);
$fwrite (fd, " 1129:%s", foobar);
end
17'b00_10??_?_????_?0_1111 :
casez (foo[14: 9])
6'b001_10_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1130"};
foobar = {foobar, " 1131"};
ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar);
foobar = {foobar, " 1132"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1133:%s", foobar);
end
6'b???_11_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1134"};
ozoneae(foo[14:12], foobar);
ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar);
foobar = {foobar, " 1135"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1136:%s", foobar);
end
6'b000_10_1,
6'b010_10_1,
6'b100_10_1,
6'b110_10_1:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1137"};
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1138"};
if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3))
foobar = {foobar, " 1139"};
else
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1140:%s", foobar);
end
6'b000_10_0,
6'b010_10_0,
6'b100_10_0,
6'b110_10_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1141"};
foobar = {foobar, " 1142"};
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1143"};
foobar = {foobar, " 1144"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1145"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1146:%s", foobar);
end
6'b???_00_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1147"};
if (foo[ 9])
begin
foobar = {foobar, " 1148"};
ozoneae(foo[14:12], foobar);
end
else
begin
foobar = {foobar, " 1149"};
ozoneae(foo[14:12], foobar);
foobar = {foobar, " 1150"};
end
foobar = {foobar, " 1151"};
foobar = {foobar, " 1152"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1153"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1154:%s", foobar);
end
6'b???_01_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1155"};
ozoneae(foo[14:12], foobar);
if (foo[ 9])
foobar = {foobar, " 1156"};
else
foobar = {foobar, " 1157"};
foobar = {foobar, " 1158"};
foobar = {foobar, " 1159"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1160"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1161:%s", foobar);
end
6'b011_10_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1162"};
case (foo[ 8: 5])
4'h0: foobar = {foobar, " 1163"};
4'h1: foobar = {foobar, " 1164"};
4'h2: foobar = {foobar, " 1165"};
4'h3: foobar = {foobar, " 1166"};
4'h4: foobar = {foobar, " 1167"};
4'h5: foobar = {foobar, " 1168"};
4'h8: foobar = {foobar, " 1169"};
4'h9: foobar = {foobar, " 1170"};
4'ha: foobar = {foobar, " 1171"};
4'hb: foobar = {foobar, " 1172"};
4'hc: foobar = {foobar, " 1173"};
4'hd: foobar = {foobar, " 1174"};
default: foobar = {foobar, " 1175"};
endcase
dude(foobar);
$fwrite (fd, " 1176:%s", foobar);
end
default: foobar = {foobar, " 1177"};
endcase
17'b00_10??_?_????_?0_110? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1178"};
foobar = {foobar, " 1179"};
ozonef1e_hl(foo[11:9], foo[0], foobar);
foobar = {foobar, " 1180"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1181"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1182"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1183:%s", foobar);
end
17'b00_10??_?_????_?1_110? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1184"};
foobar = {foobar, " 1185"};
ozonef1e_hl(foo[11:9],foo[0],foobar);
foobar = {foobar, " 1186"};
ozonef1e_ye(foo[14:9],foo[ 0],foobar);
foobar = {foobar, " 1187"};
foobar = {foobar, " 1188"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1189"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1190:%s", foobar);
end
17'b00_10??_?_????_?0_101? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1191"};
ozonef1e_ye(foo[14:9],foo[ 0],foobar);
foobar = {foobar, " 1192"};
foobar = {foobar, " 1193"};
ozonef1e_hl(foo[11:9],foo[0],foobar);
foobar = {foobar, " 1194"};
foobar = {foobar, " 1195"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1196"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1197:%s", foobar);
end
17'b00_10??_?_????_?0_1001 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1198"};
foobar = {foobar, " 1199"};
ozonef1e_h(foo[11:9],foobar);
foobar = {foobar, " 1200"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1201"};
case (foo[ 7: 5])
3'h1,
3'h2,
3'h3:
foobar = {foobar, " 1202"};
default:
begin
foobar = {foobar, " 1203"};
foobar = {foobar, " 1204"};
ozonexe(foo[ 8: 5], foobar);
end
endcase
dude(foobar);
$fwrite (fd, " 1205:%s", foobar);
end
17'b00_10??_?_????_?0_0101 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1206"};
case (foo[11: 9])
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1207"};
default:
begin
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1208"};
foobar = {foobar, " 1209"};
end
endcase
foobar = {foobar, " 1210"};
foobar = {foobar, " 1211"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1212"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1213:%s", foobar);
end
17'b00_10??_?_????_?1_1110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1214"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1215"};
foobar = {foobar, " 1216"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1217"};
foobar = {foobar, " 1218"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1219"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1220:%s", foobar);
end
17'b00_10??_?_????_?0_1000 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1221"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1222"};
foobar = {foobar, " 1223"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1224"};
foobar = {foobar, " 1225"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1226"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1227:%s", foobar);
end
17'b10_01??_?_????_??_???? :
begin
if (foo[27])
foobar = " 1228";
else
foobar = " 1229";
ozonecon(foo[20:16], foobar);
foobar = {foobar, " 1230"};
ozonef2(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1231:%s", foobar);
end
17'b00_1000_?_????_01_0011 :
if (~|foo[ 9: 8])
begin
if (foo[ 7])
foobar = " 1232";
else
foobar = " 1233";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1234"};
ozonef2e(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1235:%s", foobar);
end
else
begin
foobar = " 1236";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1237"};
ozonef3e(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1238:%s", foobar);
end
17'b11_110?_1_????_??_???? :
begin
ozonef3(foo[31:0], foobar);
dude(foobar);
$fwrite(fd, " 1239:%s", foobar);
end
17'b11_110?_0_????_??_???? :
begin : f4_body
casez (foo[24:20])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite (fd, " 1240");
end
5'b0_00??:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1241"};
ozoneacc(foo[25], foobar);
ozonebmuop(foo[24:20], foobar);
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1242"};
dude(foobar);
$fwrite(fd, " 1243:%s", foobar);
end
5'b0_01??:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1244"};
ozoneacc(foo[25], foobar);
ozonebmuop(foo[24:20], foobar);
ozonearm(foo[18:16], foobar);
dude(foobar);
$fwrite(fd, " 1245:%s", foobar);
end
5'b0_1011:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1246"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1247"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1248"};
dude(foobar);
$fwrite(fd, " 1249:%s", foobar);
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1250"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1251"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1252"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1253"};
dude(foobar);
$fwrite(fd, " 1254:%s", foobar);
end
5'b0_1111 :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1255"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1256"};
ozoneae(foo[18:16], foobar);
dude(foobar);
$fwrite(fd, " 1257:%s", foobar);
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1258"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1259"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1260"};
ozonearm(foo[18:16], foobar);
foobar = {foobar, " 1261"};
dude(foobar);
$fwrite(fd, " 1262:%s", foobar);
end
endcase
end
17'b11_100?_?_????_??_???? :
casez (foo[23:19])
5'b111??,
5'b0111?:
begin
ozoneae(foo[26:24], foobar);
foobar = {foobar, " 1263"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1264"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1265"};
skyway(foo[15:12], foobar);
skyway(foo[11: 8], foobar);
skyway(foo[ 7: 4], foobar);
skyway(foo[ 3:0], foobar);
foobar = {foobar, " 1266"};
dude(foobar);
$fwrite(fd, " 1267:%s", foobar);
end
5'b?0???,
5'b110??:
begin
ozoneae(foo[26:24], foobar);
foobar = {foobar, " 1268"};
if (foo[23:21] == 3'b100)
foobar = {foobar, " 1269"};
ozoneae(foo[18:16], foobar);
if (foo[19])
foobar = {foobar, " 1270"};
else
foobar = {foobar, " 1271"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1272"};
ozonef3f4_iext(foo[20:19], foo[15:0], foobar);
dude(foobar);
$fwrite(fd, " 1273:%s", foobar);
end
5'b010??,
5'b0110?:
begin
ozoneae(foo[18:16], foobar);
if (foo[19])
foobar = {foobar, " 1274"};
else
foobar = {foobar, " 1275"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1276"};
ozonef3f4_iext(foo[20:19], foo[15:0], foobar);
dude(foobar);
$fwrite(fd, " 1277:%s", foobar);
end
endcase
17'b00_1000_?_????_11_0011 :
begin
foobar = " 1278";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1279"};
casez (foo[25:21])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite(fd, " 1280");
end
5'b0_00??:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1281"};
ozoneae(foo[17:15], foobar);
ozonebmuop(foo[25:21], foobar);
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1282"};
dude(foobar);
$fwrite(fd, " 1283:%s", foobar);
end
5'b0_01??:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1284"};
ozoneae(foo[17:15], foobar);
ozonebmuop(foo[25:21], foobar);
ozonearm(foo[ 8: 6], foobar);
dude(foobar);
$fwrite(fd, " 1285:%s", foobar);
end
5'b0_1011:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1286"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1287"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1288"};
dude(foobar);
$fwrite(fd, " 1289:%s", foobar);
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1290"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1291"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1292"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1293"};
dude(foobar);
$fwrite(fd, " 1294:%s", foobar);
end
5'b0_1111 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1295"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1296"};
ozoneae(foo[ 8: 6], foobar);
dude(foobar);
$fwrite(fd, " 1297:%s", foobar);
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1298"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1299"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1300"};
ozonearm(foo[ 8: 6], foobar);
foobar = {foobar, " 1301"};
dude(foobar);
$fwrite(fd, " 1302:%s", foobar);
end
endcase
end
17'b00_0010_?_????_??_???? :
begin
$fwrite(fd, " 1304a:%x;%x", foobar, foo[25:20]);
ozonerab({1'b0, foo[25:20]}, foobar);
$fwrite(fd, " 1304b:%x", foobar);
foobar = {foobar, " 1303"};
$fwrite(fd, " 1304c:%x;%x", foobar, foo[19:16]);
skyway(foo[19:16], foobar);
$fwrite(fd, " 1304d:%x", foobar);
dude(foobar);
$fwrite(fd, " 1304e:%x", foobar);
$fwrite(fd, " 1304:%s", foobar);
end
17'b00_01??_?_????_??_???? :
begin
if (foo[27])
begin
foobar = {foobar, " 1305"};
if (foo[26])
foobar = {foobar, " 1306"};
else
foobar = {foobar, " 1307"};
skyway(foo[19:16], foobar);
foobar = {foobar, " 1308"};
ozonerab({1'b0, foo[25:20]}, foobar);
end
else
begin
ozonerab({1'b0, foo[25:20]}, foobar);
foobar = {foobar, " 1309"};
if (foo[26])
foobar = {foobar, " 1310"};
else
foobar = {foobar, " 1311"};
skyway(foo[19:16], foobar);
foobar = {foobar, " 1312"};
end
dude(foobar);
$fwrite(fd, " 1313:%s", foobar);
end
17'b01_000?_?_????_??_???? :
begin
if (foo[26])
begin
ozonerb(foo[25:20], foobar);
foobar = {foobar, " 1314"};
ozoneae(foo[18:16], foobar);
ozonehl(foo[19], foobar);
end
else
begin
ozoneae(foo[18:16], foobar);
ozonehl(foo[19], foobar);
foobar = {foobar, " 1315"};
ozonerb(foo[25:20], foobar);
end
dude(foobar);
$fwrite(fd, " 1316:%s", foobar);
end
17'b01_10??_?_????_??_???? :
begin
if (foo[27])
begin
ozonerab({1'b0, foo[25:20]}, foobar);
foobar = {foobar, " 1317"};
ozonerx(foo, foobar);
end
else
begin
ozonerx(foo, foobar);
foobar = {foobar, " 1318"};
ozonerab({1'b0, foo[25:20]}, foobar);
end
dude(foobar);
$fwrite(fd, " 1319:%s", foobar);
end
17'b11_101?_?_????_??_???? :
begin
ozonerab (foo[26:20], foobar);
foobar = {foobar, " 1320"};
skyway(foo[19:16], foobar);
skyway(foo[15:12], foobar);
skyway(foo[11: 8], foobar);
skyway(foo[ 7: 4], foobar);
skyway(foo[ 3: 0], foobar);
dude(foobar);
$fwrite(fd, " 1321:%s", foobar);
end
17'b11_0000_?_????_??_???? :
begin
casez (foo[25:23])
3'b00?:
begin
ozonerab(foo[22:16], foobar);
foobar = {foobar, " 1322"};
end
3'b01?:
begin
foobar = {foobar, " 1323"};
if (foo[22:16]>=7'h60)
foobar = {foobar, " 1324"};
else
ozonerab(foo[22:16], foobar);
end
3'b110:
foobar = {foobar, " 1325"};
3'b10?:
begin
foobar = {foobar, " 1326"};
if (foo[22:16]>=7'h60)
foobar = {foobar, " 1327"};
else
ozonerab(foo[22:16], foobar);
end
3'b111:
begin
foobar = {foobar, " 1328"};
ozonerab(foo[22:16], foobar);
foobar = {foobar, " 1329"};
end
endcase
dude(foobar);
$fwrite(fd, " 1330:%s", foobar);
end
17'b00_10??_?_????_?1_0000 :
begin
if (foo[27])
begin
foobar = {foobar, " 1331"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1332"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
foobar = {foobar, " 1333"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1334"};
else
ozonerab(foo[26:20], foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1335"};
foobar = {foobar, " 1336"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1337"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
foobar = {foobar, " 1338"};
end
dude(foobar);
$fwrite(fd, " 1339:%s", foobar);
end
17'b00_101?_1_0000_?1_0010 :
if (~|foo[11: 7])
begin
if (foo[ 6])
begin
foobar = {foobar, " 1340"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1341"};
ozonejk(foo[ 5], foobar);
foobar = {foobar, " 1342"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1343"};
else
ozonerab(foo[26:20], foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1344"};
foobar = {foobar, " 1345"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1346"};
ozonejk(foo[ 5], foobar);
foobar = {foobar, " 1347"};
end
dude(foobar);
$fwrite(fd, " 1348:%s", foobar);
end
else
$fwrite(fd, " 1349");
17'b00_100?_0_0011_?1_0101 :
if (~|foo[ 8: 7])
begin
if (foo[6])
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1350"};
ozoneye(foo[14: 9],foo[ 5], foobar);
end
else
begin
ozoneye(foo[14: 9],foo[ 5], foobar);
foobar = {foobar, " 1351"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1352"};
else
ozonerab(foo[26:20], foobar);
end
dude(foobar);
$fwrite(fd, " 1353:%s", foobar);
end
else
$fwrite(fd, " 1354");
17'b00_1001_0_0000_?1_0010 :
if (~|foo[25:20])
begin
ozoneye(foo[14: 9],1'b0, foobar);
foobar = {foobar, " 1355"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1356"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1357"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1358:%s", foobar);
end
else
$fwrite(fd, " 1359");
17'b00_101?_0_????_?1_0010 :
if (~foo[13])
begin
if (foo[12])
begin
foobar = {foobar, " 1360"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1361"};
else
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1362"};
foobar = {foobar, " 1363"};
skyway({1'b0,foo[18:16]}, foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1364:%s", foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1365"};
foobar = {foobar, " 1366"};
skyway({1'b0,foo[18:16]}, foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1367:%s", foobar);
end
end
else
$fwrite(fd, " 1368");
17'b01_01??_?_????_??_???? :
begin
ozonerab({1'b0,foo[27:26],foo[19:16]}, foobar);
foobar = {foobar, " 1369"};
ozonerab({1'b0,foo[25:20]}, foobar);
dude(foobar);
$fwrite(fd, " 1370:%s", foobar);
end
17'b00_100?_?_???0_11_0101 :
if (~foo[6])
begin
foobar = " 1371";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1372"};
ozonerab({foo[ 9: 7],foo[19:16]}, foobar);
foobar = {foobar, " 1373"};
ozonerab({foo[26:20]}, foobar);
dude(foobar);
$fwrite(fd, " 1374:%s", foobar);
end
else
$fwrite(fd, " 1375");
17'b00_1000_?_????_?1_0010 :
if (~|foo[25:24])
begin
ozonery(foo[23:20], foobar);
foobar = {foobar, " 1376"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1377"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1378:%s", foobar);
end
else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6])
begin
ozonery(foo[23:20], foobar);
foobar = {foobar, " 1379"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1380"};
ozonejk(foo[ 5], foobar);
dude(foobar);
$fwrite(fd, " 1381:%s", foobar);
end
else
$fwrite(fd, " 1382");
17'b11_01??_?_????_??_????,
17'b10_00??_?_????_??_???? :
if (foo[30])
$fwrite(fd, " 1383:%s", foo[27:16]);
else
$fwrite(fd, " 1384:%s", foo[27:16]);
17'b00_10??_?_????_01_1000 :
if (~foo[6])
begin
if (foo[7])
$fwrite(fd, " 1385:%s", foo[27: 8]);
else
$fwrite(fd, " 1386:%s", foo[27: 8]);
end
else
$fwrite(fd, " 1387");
17'b00_10??_?_????_11_1000 :
begin
foobar = " 1388";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1389"};
if (foo[15])
foobar = {foobar, " 1390"};
else
foobar = {foobar, " 1391"};
skyway(foo[27:24], foobar);
skyway(foo[23:20], foobar);
skyway(foo[19:16], foobar);
skyway(foo[ 9: 6], foobar);
dude(foobar);
$fwrite(fd, " 1392:%s", foobar);
end
17'b11_0001_?_????_??_???? :
casez (foo[25:22])
4'b01?? :
begin
foobar = " 1393";
ozonecon(foo[20:16], foobar);
case (foo[23:21])
3'h0 : foobar = {foobar, " 1394"};
3'h1 : foobar = {foobar, " 1395"};
3'h2 : foobar = {foobar, " 1396"};
3'h3 : foobar = {foobar, " 1397"};
3'h4 : foobar = {foobar, " 1398"};
3'h5 : foobar = {foobar, " 1399"};
3'h6 : foobar = {foobar, " 1400"};
3'h7 : foobar = {foobar, " 1401"};
endcase
dude(foobar);
$fwrite(fd, " 1402:%s", foobar);
end
4'b0000 :
$fwrite(fd, " 1403:%s", foo[21:16]);
4'b0010 :
if (~|foo[21:16])
$fwrite(fd, " 1404");
4'b1010 :
if (~|foo[21:17])
begin
if (foo[16])
$fwrite(fd, " 1405");
else
$fwrite(fd, " 1406");
end
default :
$fwrite(fd, " 1407");
endcase
17'b01_11??_?_????_??_???? :
if (foo[27:23] === 5'h00)
$fwrite(fd, " 1408:%s", foo[22:16]);
else
$fwrite(fd, " 1409:%s", foo[22:16]);
default: $fwrite(fd, " 1410");
endcase
end
endtask
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil)
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil)
endmodule
|
module outputs)
wire [63:0] HighLogicImm; // From example of example.v
wire [63:0] LogicImm; // From example of example.v
wire [63:0] LowLogicImm; // From example of example.v
// End of automatics
wire [5:0] LowMaskSel_Top = crc[5:0];
wire [5:0] LowMaskSel_Bot = crc[5:0];
wire [5:0] HighMaskSel_Top = crc[5:0]+{4'b0,crc[7:6]};
wire [5:0] HighMaskSel_Bot = crc[5:0]+{4'b0,crc[7:6]};
example example (/*AUTOINST*/
// Outputs
.LogicImm (LogicImm[63:0]),
.LowLogicImm (LowLogicImm[63:0]),
.HighLogicImm (HighLogicImm[63:0]),
// Inputs
.LowMaskSel_Top (LowMaskSel_Top[5:0]),
.HighMaskSel_Top (HighMaskSel_Top[5:0]),
.LowMaskSel_Bot (LowMaskSel_Bot[5:0]),
.HighMaskSel_Bot (HighMaskSel_Bot[5:0]));
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n",$time, cyc, crc,
LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot,
LowLogicImm, HighLogicImm, LogicImm);
`endif
if (cyc==0) begin
// Single case
crc <= 8'h0;
sum <= 64'h0;
end
else if (cyc==1) begin
// Setup
crc <= 8'hed;
sum <= 64'h0;
end
else if (cyc<90) begin
sum <= {sum[62:0],sum[63]} ^ LogicImm;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
if (crc !== 8'b00111000) $stop;
if (sum !== 64'h58743ffa61e41075) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module example (/*AUTOARG*/
// Outputs
LogicImm, LowLogicImm, HighLogicImm,
// Inputs
LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot
);
input [5:0] LowMaskSel_Top, HighMaskSel_Top;
input [5:0] LowMaskSel_Bot, HighMaskSel_Bot;
output [63:0] LogicImm;
output [63:0] LowLogicImm, HighLogicImm;
wire [63:0] LowLogicImm, HighLogicImm;
/* verilator lint_off UNSIGNED */
/* verilator lint_off CMPCONST */
genvar i;
generate
for (i=0;i<64;i=i+1) begin : MaskVal
if (i >= 32) begin
assign LowLogicImm[i] = (LowMaskSel_Top <= i[5:0]);
assign HighLogicImm[i] = (HighMaskSel_Top >= i[5:0]);
end
else begin
assign LowLogicImm[i] = (LowMaskSel_Bot <= i[5:0]);
assign HighLogicImm[i] = (HighMaskSel_Bot >= i[5:0]);
end
end
endgenerate
/* verilator lint_on UNSIGNED */
/* verilator lint_on CMPCONST */
assign LogicImm = LowLogicImm & HighLogicImm;
endmodule
|
module outputs)
wire [63:0] HighLogicImm; // From example of example.v
wire [63:0] LogicImm; // From example of example.v
wire [63:0] LowLogicImm; // From example of example.v
// End of automatics
wire [5:0] LowMaskSel_Top = crc[5:0];
wire [5:0] LowMaskSel_Bot = crc[5:0];
wire [5:0] HighMaskSel_Top = crc[5:0]+{4'b0,crc[7:6]};
wire [5:0] HighMaskSel_Bot = crc[5:0]+{4'b0,crc[7:6]};
example example (/*AUTOINST*/
// Outputs
.LogicImm (LogicImm[63:0]),
.LowLogicImm (LowLogicImm[63:0]),
.HighLogicImm (HighLogicImm[63:0]),
// Inputs
.LowMaskSel_Top (LowMaskSel_Top[5:0]),
.HighMaskSel_Top (HighMaskSel_Top[5:0]),
.LowMaskSel_Bot (LowMaskSel_Bot[5:0]),
.HighMaskSel_Bot (HighMaskSel_Bot[5:0]));
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n",$time, cyc, crc,
LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot,
LowLogicImm, HighLogicImm, LogicImm);
`endif
if (cyc==0) begin
// Single case
crc <= 8'h0;
sum <= 64'h0;
end
else if (cyc==1) begin
// Setup
crc <= 8'hed;
sum <= 64'h0;
end
else if (cyc<90) begin
sum <= {sum[62:0],sum[63]} ^ LogicImm;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
if (crc !== 8'b00111000) $stop;
if (sum !== 64'h58743ffa61e41075) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module example (/*AUTOARG*/
// Outputs
LogicImm, LowLogicImm, HighLogicImm,
// Inputs
LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot
);
input [5:0] LowMaskSel_Top, HighMaskSel_Top;
input [5:0] LowMaskSel_Bot, HighMaskSel_Bot;
output [63:0] LogicImm;
output [63:0] LowLogicImm, HighLogicImm;
wire [63:0] LowLogicImm, HighLogicImm;
/* verilator lint_off UNSIGNED */
/* verilator lint_off CMPCONST */
genvar i;
generate
for (i=0;i<64;i=i+1) begin : MaskVal
if (i >= 32) begin
assign LowLogicImm[i] = (LowMaskSel_Top <= i[5:0]);
assign HighLogicImm[i] = (HighMaskSel_Top >= i[5:0]);
end
else begin
assign LowLogicImm[i] = (LowMaskSel_Bot <= i[5:0]);
assign HighLogicImm[i] = (HighMaskSel_Bot >= i[5:0]);
end
end
endgenerate
/* verilator lint_on UNSIGNED */
/* verilator lint_on CMPCONST */
assign LogicImm = LowLogicImm & HighLogicImm;
endmodule
|
module temp_sense_alttemp_sense_v8t
(
ce,
clk,
clr,
tsdcaldone,
tsdcalo) /* synthesis synthesis_clearbox=2 */;
input ce;
input clk;
input clr;
output tsdcaldone;
output [7:0] tsdcalo;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 ce;
tri0 clr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_sd1_tsdcaldone;
wire [7:0] wire_sd1_tsdcalo;
stratixv_tsdblock sd1
(
.ce(ce),
.clk(clk),
.clr(clr),
.tsdcaldone(wire_sd1_tsdcaldone),
.tsdcalo(wire_sd1_tsdcalo));
defparam
sd1.clock_divider_enable = "true",
sd1.clock_divider_value = 80,
sd1.sim_tsdcalo = 0,
sd1.lpm_type = "stratixv_tsdblock";
assign
tsdcaldone = wire_sd1_tsdcaldone,
tsdcalo = wire_sd1_tsdcalo;
endmodule
|
module temp_sense (
ce,
clk,
clr,
tsdcaldone,
tsdcalo)/* synthesis synthesis_clearbox = 2 */;
input ce;
input clk;
input clr;
output tsdcaldone;
output [7:0] tsdcalo;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [7:0] tsdcalo = sub_wire0[7:0];
wire tsdcaldone = sub_wire1;
temp_sense_alttemp_sense_v8t temp_sense_alttemp_sense_v8t_component (
.ce (ce),
.clk (clk),
.clr (clr),
.tsdcalo (sub_wire0),
.tsdcaldone (sub_wire1))/* synthesis synthesis_clearbox=2
clearbox_macroname = ALTTEMP_SENSE
clearbox_defparam = "clk_frequency=50.0;clock_divider_enable=ON;clock_divider_value=80;intended_device_family=Stratix V;lpm_hint=UNUSED;lpm_type=alttemp_sense;number_of_samples=128;poi_cal_temperature=85;sim_tsdcalo=0;user_offset_enable=off;use_wys=on;" */;
endmodule
|
module usb_packet_fifo
( input reset,
input clock_in,
input clock_out,
input [15:0]ram_data_in,
input write_enable,
output reg [15:0]ram_data_out,
output reg pkt_waiting,
output reg have_space,
input read_enable,
input skip_packet ) ;
/* Some parameters for usage later on */
parameter DATA_WIDTH = 16 ;
parameter NUM_PACKETS = 4 ;
/* Create the RAM here */
reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
/* Create the address signals */
reg [7-2+NUM_PACKETS:0] usb_ram_ain ;
reg [7:0] usb_ram_offset ;
reg [1:0] usb_ram_packet ;
wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
reg isfull;
assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ;
// Check if there is one full packet to process
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
pkt_waiting <= 0;
else if (usb_ram_ain == usb_ram_aout)
pkt_waiting <= isfull;
else if (usb_ram_ain > usb_ram_aout)
pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256;
else
pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256;
end
// Check if there is room
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
have_space <= 1;
else if (usb_ram_ain == usb_ram_aout)
have_space <= ~isfull;
else if (usb_ram_ain > usb_ram_aout)
have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1);
else
have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
end
/* RAM Write Address process */
always @(posedge clock_in)
begin
if( reset )
usb_ram_ain <= 0 ;
else
if( write_enable )
begin
usb_ram_ain <= usb_ram_ain + 1 ;
if (usb_ram_ain + 1 == usb_ram_aout)
isfull <= 1;
end
end
/* RAM Writing process */
always @(posedge clock_in)
begin
if( write_enable )
begin
usb_ram[usb_ram_ain] <= ram_data_in ;
end
end
/* RAM Read Address process */
always @(posedge clock_out)
begin
if( reset )
begin
usb_ram_packet <= 0 ;
usb_ram_offset <= 0 ;
isfull <= 0;
end
else
if( skip_packet )
begin
usb_ram_packet <= usb_ram_packet + 1 ;
usb_ram_offset <= 0 ;
end
else if(read_enable)
if( usb_ram_offset == 8'b11111111 )
begin
usb_ram_offset <= 0 ;
usb_ram_packet <= usb_ram_packet + 1 ;
end
else
usb_ram_offset <= usb_ram_offset + 1 ;
if (usb_ram_ain == usb_ram_aout)
isfull <= 0;
end
/* RAM Reading Process */
always @(posedge clock_out)
begin
ram_data_out <= usb_ram[usb_ram_aout] ;
end
endmodule
|
module usb_packet_fifo
( input reset,
input clock_in,
input clock_out,
input [15:0]ram_data_in,
input write_enable,
output reg [15:0]ram_data_out,
output reg pkt_waiting,
output reg have_space,
input read_enable,
input skip_packet ) ;
/* Some parameters for usage later on */
parameter DATA_WIDTH = 16 ;
parameter NUM_PACKETS = 4 ;
/* Create the RAM here */
reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
/* Create the address signals */
reg [7-2+NUM_PACKETS:0] usb_ram_ain ;
reg [7:0] usb_ram_offset ;
reg [1:0] usb_ram_packet ;
wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
reg isfull;
assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ;
// Check if there is one full packet to process
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
pkt_waiting <= 0;
else if (usb_ram_ain == usb_ram_aout)
pkt_waiting <= isfull;
else if (usb_ram_ain > usb_ram_aout)
pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256;
else
pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256;
end
// Check if there is room
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
have_space <= 1;
else if (usb_ram_ain == usb_ram_aout)
have_space <= ~isfull;
else if (usb_ram_ain > usb_ram_aout)
have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1);
else
have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
end
/* RAM Write Address process */
always @(posedge clock_in)
begin
if( reset )
usb_ram_ain <= 0 ;
else
if( write_enable )
begin
usb_ram_ain <= usb_ram_ain + 1 ;
if (usb_ram_ain + 1 == usb_ram_aout)
isfull <= 1;
end
end
/* RAM Writing process */
always @(posedge clock_in)
begin
if( write_enable )
begin
usb_ram[usb_ram_ain] <= ram_data_in ;
end
end
/* RAM Read Address process */
always @(posedge clock_out)
begin
if( reset )
begin
usb_ram_packet <= 0 ;
usb_ram_offset <= 0 ;
isfull <= 0;
end
else
if( skip_packet )
begin
usb_ram_packet <= usb_ram_packet + 1 ;
usb_ram_offset <= 0 ;
end
else if(read_enable)
if( usb_ram_offset == 8'b11111111 )
begin
usb_ram_offset <= 0 ;
usb_ram_packet <= usb_ram_packet + 1 ;
end
else
usb_ram_offset <= usb_ram_offset + 1 ;
if (usb_ram_ain == usb_ram_aout)
isfull <= 0;
end
/* RAM Reading Process */
always @(posedge clock_out)
begin
ram_data_out <= usb_ram[usb_ram_aout] ;
end
endmodule
|
module write_signal_breakout (
write_command_data_in, // descriptor from the write FIFO
write_command_data_out, // reformated descriptor to the write master
// breakout of command information
write_address,
write_length,
write_park,
write_end_on_eop,
write_transfer_complete_IRQ_mask,
write_early_termination_IRQ_mask,
write_error_IRQ_mask,
write_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
// additional control information that needs to go out asynchronously with the command data
write_stop,
write_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] write_command_data_in;
output wire [255:0] write_command_data_out;
output wire [63:0] write_address;
output wire [31:0] write_length;
output wire write_park;
output wire write_end_on_eop;
output wire write_transfer_complete_IRQ_mask;
output wire write_early_termination_IRQ_mask;
output wire [7:0] write_error_IRQ_mask;
output wire [7:0] write_burst_count;
output wire [15:0] write_stride;
output wire [15:0] write_sequence_number;
input write_stop;
input write_sw_reset;
assign write_address[31:0] = write_command_data_in[63:32];
assign write_length = write_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign write_park = write_command_data_in[235];
assign write_end_on_eop = write_command_data_in[236];
assign write_transfer_complete_IRQ_mask = write_command_data_in[238];
assign write_early_termination_IRQ_mask = write_command_data_in[239];
assign write_error_IRQ_mask = write_command_data_in[247:240];
assign write_burst_count = write_command_data_in[127:120];
assign write_stride = write_command_data_in[159:144];
assign write_sequence_number = write_command_data_in[111:96];
assign write_address[63:32] = write_command_data_in[223:192];
end
else
begin
assign write_park = write_command_data_in[107];
assign write_end_on_eop = write_command_data_in[108];
assign write_transfer_complete_IRQ_mask = write_command_data_in[110];
assign write_early_termination_IRQ_mask = write_command_data_in[111];
assign write_error_IRQ_mask = write_command_data_in[119:112];
assign write_burst_count = 8'h00;
assign write_stride = 16'h0000;
assign write_sequence_number = 16'h0000;
assign write_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the write master (MSBs to LSBs)
assign write_command_data_out = {{132{1'b0}}, // zero pad the upper 132 bits
write_address[63:32],
write_stride,
write_burst_count,
write_sw_reset,
write_stop,
1'b0, // used to be the early termination bit so now it's reserved
write_end_on_eop,
write_length,
write_address[31:0]};
endmodule
|
module unpipeline #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 1,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = slave_read & ~master_waitrequest;
assign slave_readdata = master_readdata;
endmodule
|
module unpipeline #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 1,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = slave_read & ~master_waitrequest;
assign slave_readdata = master_readdata;
endmodule
|
module unpipeline #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 1,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = slave_read & ~master_waitrequest;
assign slave_readdata = master_readdata;
endmodule
|
module unpipeline #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 1,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = slave_read & ~master_waitrequest;
assign slave_readdata = master_readdata;
endmodule
|
module csr_block (
clk,
reset,
csr_writedata,
csr_write,
csr_byteenable,
csr_readdata,
csr_read,
csr_address,
csr_irq,
done_strobe,
busy,
descriptor_buffer_empty,
descriptor_buffer_full,
stop_state,
stopped_on_error,
stopped_on_early_termination,
reset_stalled,
stop,
sw_reset,
stop_on_error,
stop_on_early_termination,
stop_descriptors,
sequence_number,
descriptor_watermark,
response_watermark,
response_buffer_empty,
response_buffer_full,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
error,
early_termination
);
parameter ADDRESS_WIDTH = 3;
localparam CONTROL_REGISTER_ADDRESS = 3'b001;
input clk;
input reset;
input [31:0] csr_writedata;
input csr_write;
input [3:0] csr_byteenable;
output wire [31:0] csr_readdata;
input csr_read;
input [ADDRESS_WIDTH-1:0] csr_address;
output wire csr_irq;
input done_strobe;
input busy;
input descriptor_buffer_empty;
input descriptor_buffer_full;
input stop_state; // when the DMA runs into some error condition and you have enabled the stop on error (or when the stop control bit is written to)
input reset_stalled; // the read or write master could be in the middle of a transfer/burst so it might take a while to flush the buffers
output wire stop;
output reg stopped_on_error;
output reg stopped_on_early_termination;
output reg sw_reset;
output wire stop_on_error;
output wire stop_on_early_termination;
output wire stop_descriptors;
input [31:0] sequence_number;
input [31:0] descriptor_watermark;
input [15:0] response_watermark;
input response_buffer_empty;
input response_buffer_full;
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input [7:0] error;
input early_termination;
/* Internal wires and registers */
wire [31:0] status;
reg [31:0] control;
reg [31:0] readdata;
reg [31:0] readdata_d1;
reg irq; // writing to the status register clears the irq bit
wire set_irq;
wire clear_irq;
reg [15:0] irq_count; // writing to bit 0 clears the counter
wire clear_irq_count;
wire incr_irq_count;
wire set_stopped_on_error;
wire set_stopped_on_early_termination;
wire set_stop;
wire clear_stop;
wire global_interrupt_enable;
wire sw_reset_strobe; // this strobe will be one cycle earlier than sw_reset
wire set_sw_reset;
wire clear_sw_reset;
/********************************************** Registers ***************************************************/
// read latency is 1 cycle
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdata_d1 <= 0;
end
else if (csr_read == 1)
begin
readdata_d1 <= readdata;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[31:1] <= 0;
end
else
begin
if (sw_reset_strobe == 1) // reset strobe is a strobe due to this sync reset
begin
control[31:1] <= 0;
end
else
begin
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1))
begin
control[7:1] <= csr_writedata[7:1]; // stop bit will be handled seperately since it can be set by the csr slave port access or the SGDMA hitting an error condition
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[1] == 1))
begin
control[15:8] <= csr_writedata[15:8];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[2] == 1))
begin
control[23:16] <= csr_writedata[23:16];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[3] == 1))
begin
control[31:24] <= csr_writedata[31:24];
end
end
end
end
// control bit 0 (stop) is set by different sources so handling it seperately
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[0] <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
control[0] <= 0;
end
else
begin
case ({set_stop, clear_stop})
2'b00: control[0] <= control[0];
2'b01: control[0] <= 1'b0;
2'b10: control[0] <= 1'b1;
2'b11: control[0] <= 1'b1; // setting will win, this case happens control[0] is being set to 0 (resume) at the same time an error/early termination stop condition occurs
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
sw_reset <= 0;
end
else
begin
if (set_sw_reset == 1)
begin
sw_reset <= 1;
end
else if (clear_sw_reset == 1)
begin
sw_reset <= 0;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_error <= 0;
end
else
begin
case ({set_stopped_on_error, clear_stop})
2'b00: stopped_on_error <= stopped_on_error;
2'b01: stopped_on_error <= 1'b0;
2'b10: stopped_on_error <= 1'b1;
2'b11: stopped_on_error <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_early_termination <= 0;
end
else
begin
case ({set_stopped_on_early_termination, clear_stop})
2'b00: stopped_on_early_termination <= stopped_on_early_termination;
2'b01: stopped_on_early_termination <= 1'b0;
2'b10: stopped_on_early_termination <= 1'b1;
2'b11: stopped_on_early_termination <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
irq <= 0;
end
else
begin
case ({clear_irq, set_irq})
2'b00: irq <= irq;
2'b01: irq <= 1'b1;
2'b10: irq <= 1'b0;
2'b11: irq <= 1'b1; // setting will win over a clear
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq_count <= {16{1'b0}};
end
else
begin
if (sw_reset_strobe == 1)
begin
irq_count <= {16{1'b0}};
end
else
begin
case ({clear_irq_count, incr_irq_count})
2'b00: irq_count <= irq_count;
2'b01: irq_count <= irq_count + 1;
2'b10: irq_count <= {16{1'b0}};
2'b11: irq_count <= {{15{1'b0}}, 1'b1};
endcase
end
end
end
/******************************************** End Registers *************************************************/
/**************************************** Combinational Signals *********************************************/
generate
if (ADDRESS_WIDTH == 3)
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark or sequence_number)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
3'b011: readdata = response_watermark;
default: readdata = sequence_number; // all other addresses will decode to the sequence number
endcase
end
end
else
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
default: readdata = response_watermark; // all other addresses will decode to the response watermark
endcase
end
end
endgenerate
assign clear_irq = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[1] == 1) & (csr_writedata[9] == 1); // this is the IRQ bit
assign set_irq = (global_interrupt_enable == 1) & (done_strobe == 1) & // transfer ended and interrupts are enabled
((transfer_complete_IRQ_mask == 1) | // transfer ended and the transfer complete IRQ is enabled
((error & error_IRQ_mask) != 0) | // transfer ended with an error and this IRQ is enabled
((early_termination & early_termination_IRQ_mask) == 1)); // transfer ended early due to early termination and this IRQ is enabled
assign csr_irq = irq;
// Done count
assign incr_irq_count = set_irq; // Done count just counts the number of interrupts since the last reset
assign clear_irq_count = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[2] == 1) & (csr_writedata[16] == 1); // the LSB irq_count bit
assign clear_stop = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 0);
assign set_stopped_on_error = (done_strobe == 1) & (stop_on_error == 1) & (error != 0); // when clear_stop is set then the stopped_on_error register will be cleared
assign set_stopped_on_early_termination = (done_strobe == 1) & (stop_on_early_termination == 1) & (early_termination == 1); // when clear_stop is set then the stopped_on_early_termination register will be cleared
assign set_stop = ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 1)) | // host set the stop bit
(set_stopped_on_error == 1) | // SGDMA setup to stop when an error occurs from the write master
(set_stopped_on_early_termination == 1) ; // SGDMA setup to stop when the write master overflows
assign stop = control[0];
assign set_sw_reset = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[1] == 1);
assign clear_sw_reset = (sw_reset == 1) & (reset_stalled == 0);
assign sw_reset_strobe = control[1];
assign stop_on_error = control[2];
assign stop_on_early_termination = control[3];
assign global_interrupt_enable = control[4];
assign stop_descriptors = control[5];
assign csr_readdata = readdata_d1;
assign status = {irq_count, {6{1'b0}}, irq, stopped_on_early_termination, stopped_on_error, sw_reset, stop_state, response_buffer_full, response_buffer_empty, descriptor_buffer_full, descriptor_buffer_empty, busy}; // writing to the lower byte of the status register clears the irq bit
/**************************************** Combinational Signals *********************************************/
endmodule
|
module csr_block (
clk,
reset,
csr_writedata,
csr_write,
csr_byteenable,
csr_readdata,
csr_read,
csr_address,
csr_irq,
done_strobe,
busy,
descriptor_buffer_empty,
descriptor_buffer_full,
stop_state,
stopped_on_error,
stopped_on_early_termination,
reset_stalled,
stop,
sw_reset,
stop_on_error,
stop_on_early_termination,
stop_descriptors,
sequence_number,
descriptor_watermark,
response_watermark,
response_buffer_empty,
response_buffer_full,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
error,
early_termination
);
parameter ADDRESS_WIDTH = 3;
localparam CONTROL_REGISTER_ADDRESS = 3'b001;
input clk;
input reset;
input [31:0] csr_writedata;
input csr_write;
input [3:0] csr_byteenable;
output wire [31:0] csr_readdata;
input csr_read;
input [ADDRESS_WIDTH-1:0] csr_address;
output wire csr_irq;
input done_strobe;
input busy;
input descriptor_buffer_empty;
input descriptor_buffer_full;
input stop_state; // when the DMA runs into some error condition and you have enabled the stop on error (or when the stop control bit is written to)
input reset_stalled; // the read or write master could be in the middle of a transfer/burst so it might take a while to flush the buffers
output wire stop;
output reg stopped_on_error;
output reg stopped_on_early_termination;
output reg sw_reset;
output wire stop_on_error;
output wire stop_on_early_termination;
output wire stop_descriptors;
input [31:0] sequence_number;
input [31:0] descriptor_watermark;
input [15:0] response_watermark;
input response_buffer_empty;
input response_buffer_full;
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input [7:0] error;
input early_termination;
/* Internal wires and registers */
wire [31:0] status;
reg [31:0] control;
reg [31:0] readdata;
reg [31:0] readdata_d1;
reg irq; // writing to the status register clears the irq bit
wire set_irq;
wire clear_irq;
reg [15:0] irq_count; // writing to bit 0 clears the counter
wire clear_irq_count;
wire incr_irq_count;
wire set_stopped_on_error;
wire set_stopped_on_early_termination;
wire set_stop;
wire clear_stop;
wire global_interrupt_enable;
wire sw_reset_strobe; // this strobe will be one cycle earlier than sw_reset
wire set_sw_reset;
wire clear_sw_reset;
/********************************************** Registers ***************************************************/
// read latency is 1 cycle
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdata_d1 <= 0;
end
else if (csr_read == 1)
begin
readdata_d1 <= readdata;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[31:1] <= 0;
end
else
begin
if (sw_reset_strobe == 1) // reset strobe is a strobe due to this sync reset
begin
control[31:1] <= 0;
end
else
begin
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1))
begin
control[7:1] <= csr_writedata[7:1]; // stop bit will be handled seperately since it can be set by the csr slave port access or the SGDMA hitting an error condition
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[1] == 1))
begin
control[15:8] <= csr_writedata[15:8];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[2] == 1))
begin
control[23:16] <= csr_writedata[23:16];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[3] == 1))
begin
control[31:24] <= csr_writedata[31:24];
end
end
end
end
// control bit 0 (stop) is set by different sources so handling it seperately
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[0] <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
control[0] <= 0;
end
else
begin
case ({set_stop, clear_stop})
2'b00: control[0] <= control[0];
2'b01: control[0] <= 1'b0;
2'b10: control[0] <= 1'b1;
2'b11: control[0] <= 1'b1; // setting will win, this case happens control[0] is being set to 0 (resume) at the same time an error/early termination stop condition occurs
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
sw_reset <= 0;
end
else
begin
if (set_sw_reset == 1)
begin
sw_reset <= 1;
end
else if (clear_sw_reset == 1)
begin
sw_reset <= 0;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_error <= 0;
end
else
begin
case ({set_stopped_on_error, clear_stop})
2'b00: stopped_on_error <= stopped_on_error;
2'b01: stopped_on_error <= 1'b0;
2'b10: stopped_on_error <= 1'b1;
2'b11: stopped_on_error <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_early_termination <= 0;
end
else
begin
case ({set_stopped_on_early_termination, clear_stop})
2'b00: stopped_on_early_termination <= stopped_on_early_termination;
2'b01: stopped_on_early_termination <= 1'b0;
2'b10: stopped_on_early_termination <= 1'b1;
2'b11: stopped_on_early_termination <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
irq <= 0;
end
else
begin
case ({clear_irq, set_irq})
2'b00: irq <= irq;
2'b01: irq <= 1'b1;
2'b10: irq <= 1'b0;
2'b11: irq <= 1'b1; // setting will win over a clear
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq_count <= {16{1'b0}};
end
else
begin
if (sw_reset_strobe == 1)
begin
irq_count <= {16{1'b0}};
end
else
begin
case ({clear_irq_count, incr_irq_count})
2'b00: irq_count <= irq_count;
2'b01: irq_count <= irq_count + 1;
2'b10: irq_count <= {16{1'b0}};
2'b11: irq_count <= {{15{1'b0}}, 1'b1};
endcase
end
end
end
/******************************************** End Registers *************************************************/
/**************************************** Combinational Signals *********************************************/
generate
if (ADDRESS_WIDTH == 3)
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark or sequence_number)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
3'b011: readdata = response_watermark;
default: readdata = sequence_number; // all other addresses will decode to the sequence number
endcase
end
end
else
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
default: readdata = response_watermark; // all other addresses will decode to the response watermark
endcase
end
end
endgenerate
assign clear_irq = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[1] == 1) & (csr_writedata[9] == 1); // this is the IRQ bit
assign set_irq = (global_interrupt_enable == 1) & (done_strobe == 1) & // transfer ended and interrupts are enabled
((transfer_complete_IRQ_mask == 1) | // transfer ended and the transfer complete IRQ is enabled
((error & error_IRQ_mask) != 0) | // transfer ended with an error and this IRQ is enabled
((early_termination & early_termination_IRQ_mask) == 1)); // transfer ended early due to early termination and this IRQ is enabled
assign csr_irq = irq;
// Done count
assign incr_irq_count = set_irq; // Done count just counts the number of interrupts since the last reset
assign clear_irq_count = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[2] == 1) & (csr_writedata[16] == 1); // the LSB irq_count bit
assign clear_stop = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 0);
assign set_stopped_on_error = (done_strobe == 1) & (stop_on_error == 1) & (error != 0); // when clear_stop is set then the stopped_on_error register will be cleared
assign set_stopped_on_early_termination = (done_strobe == 1) & (stop_on_early_termination == 1) & (early_termination == 1); // when clear_stop is set then the stopped_on_early_termination register will be cleared
assign set_stop = ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 1)) | // host set the stop bit
(set_stopped_on_error == 1) | // SGDMA setup to stop when an error occurs from the write master
(set_stopped_on_early_termination == 1) ; // SGDMA setup to stop when the write master overflows
assign stop = control[0];
assign set_sw_reset = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[1] == 1);
assign clear_sw_reset = (sw_reset == 1) & (reset_stalled == 0);
assign sw_reset_strobe = control[1];
assign stop_on_error = control[2];
assign stop_on_early_termination = control[3];
assign global_interrupt_enable = control[4];
assign stop_descriptors = control[5];
assign csr_readdata = readdata_d1;
assign status = {irq_count, {6{1'b0}}, irq, stopped_on_early_termination, stopped_on_error, sw_reset, stop_state, response_buffer_full, response_buffer_empty, descriptor_buffer_full, descriptor_buffer_empty, busy}; // writing to the lower byte of the status register clears the irq bit
/**************************************** Combinational Signals *********************************************/
endmodule
|
module generic_baseblocks_v2_1_0_carry_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN | S;
end else begin : USE_FPGA
wire S_n;
assign S_n = ~S;
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b1),
.S (S_n)
);
end
endgenerate
endmodule
|
module generic_baseblocks_v2_1_0_carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
module generic_baseblocks_v2_1_0_carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end
else if (start)
begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (start == 1)
begin
barrelshifter_B_d1 <= 0;
end
else if (fifo_readack == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end
else
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule
|
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end
else if (start)
begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (start == 1)
begin
barrelshifter_B_d1 <= 0;
end
else if (fifo_readack == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end
else
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule
|
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end
else if (start)
begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (start == 1)
begin
barrelshifter_B_d1 <= 0;
end
else if (fifo_readack == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end
else
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule
|
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end
else if (start)
begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (start == 1)
begin
barrelshifter_B_d1 <= 0;
end
else if (fifo_readack == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end
else
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule
|
module fifo_4k_18 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [17:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [17:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
wire sub_wire0;
wire [11:0] sub_wire1;
wire sub_wire2;
wire [17:0] sub_wire3;
wire [11:0] sub_wire4;
wire rdempty = sub_wire0;
wire [11:0] wrusedw = sub_wire1[11:0];
wire wrfull = sub_wire2;
wire [17:0] q = sub_wire3[17:0];
wire [11:0] rdusedw = sub_wire4[11:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4)
// synopsys translate_off
,
.rdfull (),
.wrempty ()
// synopsys translate_on
);
defparam
dcfifo_component.add_ram_output_register = "OFF",
dcfifo_component.clocks_are_synchronized = "FALSE",
dcfifo_component.intended_device_family = "Cyclone",
dcfifo_component.lpm_numwords = 4096,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 18,
dcfifo_component.lpm_widthu = 12,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON";
endmodule
|
module fifo_4k_18 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [17:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [17:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
wire sub_wire0;
wire [11:0] sub_wire1;
wire sub_wire2;
wire [17:0] sub_wire3;
wire [11:0] sub_wire4;
wire rdempty = sub_wire0;
wire [11:0] wrusedw = sub_wire1[11:0];
wire wrfull = sub_wire2;
wire [17:0] q = sub_wire3[17:0];
wire [11:0] rdusedw = sub_wire4[11:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4)
// synopsys translate_off
,
.rdfull (),
.wrempty ()
// synopsys translate_on
);
defparam
dcfifo_component.add_ram_output_register = "OFF",
dcfifo_component.clocks_are_synchronized = "FALSE",
dcfifo_component.intended_device_family = "Cyclone",
dcfifo_component.lpm_numwords = 4096,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 18,
dcfifo_component.lpm_widthu = 12,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON";
endmodule
|
module fifo_4k_18 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [17:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [17:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
wire sub_wire0;
wire [11:0] sub_wire1;
wire sub_wire2;
wire [17:0] sub_wire3;
wire [11:0] sub_wire4;
wire rdempty = sub_wire0;
wire [11:0] wrusedw = sub_wire1[11:0];
wire wrfull = sub_wire2;
wire [17:0] q = sub_wire3[17:0];
wire [11:0] rdusedw = sub_wire4[11:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4)
// synopsys translate_off
,
.rdfull (),
.wrempty ()
// synopsys translate_on
);
defparam
dcfifo_component.add_ram_output_register = "OFF",
dcfifo_component.clocks_are_synchronized = "FALSE",
dcfifo_component.intended_device_family = "Cyclone",
dcfifo_component.lpm_numwords = 4096,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 18,
dcfifo_component.lpm_widthu = 12,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON";
endmodule
|
module fifo_4k_18 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [17:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [17:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
wire sub_wire0;
wire [11:0] sub_wire1;
wire sub_wire2;
wire [17:0] sub_wire3;
wire [11:0] sub_wire4;
wire rdempty = sub_wire0;
wire [11:0] wrusedw = sub_wire1[11:0];
wire wrfull = sub_wire2;
wire [17:0] q = sub_wire3[17:0];
wire [11:0] rdusedw = sub_wire4[11:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4)
// synopsys translate_off
,
.rdfull (),
.wrempty ()
// synopsys translate_on
);
defparam
dcfifo_component.add_ram_output_register = "OFF",
dcfifo_component.clocks_are_synchronized = "FALSE",
dcfifo_component.intended_device_family = "Cyclone",
dcfifo_component.lpm_numwords = 4096,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 18,
dcfifo_component.lpm_widthu = 12,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON";
endmodule
|
module fifo_4k_18 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [17:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [17:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
wire sub_wire0;
wire [11:0] sub_wire1;
wire sub_wire2;
wire [17:0] sub_wire3;
wire [11:0] sub_wire4;
wire rdempty = sub_wire0;
wire [11:0] wrusedw = sub_wire1[11:0];
wire wrfull = sub_wire2;
wire [17:0] q = sub_wire3[17:0];
wire [11:0] rdusedw = sub_wire4[11:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4)
// synopsys translate_off
,
.rdfull (),
.wrempty ()
// synopsys translate_on
);
defparam
dcfifo_component.add_ram_output_register = "OFF",
dcfifo_component.clocks_are_synchronized = "FALSE",
dcfifo_component.intended_device_family = "Cyclone",
dcfifo_component.lpm_numwords = 4096,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 18,
dcfifo_component.lpm_widthu = 12,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON";
endmodule
|
module fake_nonburstboundary #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 6,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BURSTCOUNT_WIDTH-1:0] master_burstcount,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata,
input master_readdatavalid
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_burstcount = slave_burstcount;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = master_readdatavalid;
assign slave_readdata = master_readdata;
endmodule
|
module fake_nonburstboundary #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 6,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BURSTCOUNT_WIDTH-1:0] master_burstcount,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata,
input master_readdatavalid
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_burstcount = slave_burstcount;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = master_readdatavalid;
assign slave_readdata = master_readdata;
endmodule
|
module fake_nonburstboundary #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 6,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BURSTCOUNT_WIDTH-1:0] master_burstcount,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata,
input master_readdatavalid
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_burstcount = slave_burstcount;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = master_readdatavalid;
assign slave_readdata = master_readdata;
endmodule
|
module fake_nonburstboundary #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 6,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BURSTCOUNT_WIDTH-1:0] master_burstcount,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata,
input master_readdatavalid
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_burstcount = slave_burstcount;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = master_readdatavalid;
assign slave_readdata = master_readdata;
endmodule
|
module generic_baseblocks_v2_1_0_comparator_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 6;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
module generic_baseblocks_v2_1_0_comparator_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
module fifo_with_byteenables (
clk,
areset,
sreset,
write_data,
write_byteenables,
write,
push,
read_data,
pop,
used,
full,
empty
);
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 128;
parameter FIFO_DEPTH_LOG2 = 7; // this impacts the width of the used port so it can't be local
parameter LATENCY = 1; // number of clock cycles after asserting 'pop' that valid data comes out
input clk;
input areset;
input sreset;
input [DATA_WIDTH-1:0] write_data;
input [(DATA_WIDTH/8)-1:0] write_byteenables;
input write;
input push; // when you have written to all the byte lanes assert this to commit the word (you can use it at the same time as the byte enables)
output wire [DATA_WIDTH-1:0] read_data;
input pop; // use this to read a word out of the FIFO
output wire [FIFO_DEPTH_LOG2:0] used;
output wire full;
output wire empty;
reg [FIFO_DEPTH_LOG2-1:0] write_address;
reg [FIFO_DEPTH_LOG2-1:0] read_address;
reg [FIFO_DEPTH_LOG2:0] internal_used;
wire internal_full;
wire internal_empty;
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
write_address <= 0;
end
else
begin
if (sreset)
begin
write_address <= 0;
end
else if (push == 1)
begin
write_address <= write_address + 1'b1;
end
end
end
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
read_address <= 0;
end
else
begin
if (sreset)
begin
read_address <= 0;
end
else if (pop == 1)
begin
read_address <= read_address + 1'b1;
end
end
end
// TODO: Change this to an inferrered RAM when Quartus II supports byte enables for inferred RAM
altsyncram the_dp_ram (
.clock0 (clk),
.wren_a (write),
.byteena_a (write_byteenables),
.data_a (write_data),
.address_a (write_address),
.q_b (read_data),
.address_b (read_address)
);
defparam the_dp_ram.operation_mode = "DUAL_PORT"; // simple dual port (one read, one write port)
defparam the_dp_ram.lpm_type = "altsyncram";
defparam the_dp_ram.read_during_write_mode_mixed_ports = "DONT_CARE";
defparam the_dp_ram.power_up_uninitialized = "TRUE";
defparam the_dp_ram.byte_size = 8;
defparam the_dp_ram.width_a = DATA_WIDTH;
defparam the_dp_ram.width_b = DATA_WIDTH;
defparam the_dp_ram.widthad_a = FIFO_DEPTH_LOG2;
defparam the_dp_ram.widthad_b = FIFO_DEPTH_LOG2;
defparam the_dp_ram.width_byteena_a = (DATA_WIDTH/8);
defparam the_dp_ram.numwords_a = FIFO_DEPTH;
defparam the_dp_ram.numwords_b = FIFO_DEPTH;
defparam the_dp_ram.address_reg_b = "CLOCK0";
defparam the_dp_ram.outdata_reg_b = (LATENCY == 2)? "CLOCK0" : "UNREGISTERED";
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
internal_used <= 0;
end
else
begin
if (sreset)
begin
internal_used <= 0;
end
else
begin
case ({push, pop})
2'b01: internal_used <= internal_used - 1'b1;
2'b10: internal_used <= internal_used + 1'b1;
default: internal_used <= internal_used;
endcase
end
end
end
assign internal_empty = (read_address == write_address) & (internal_used == 0);
assign internal_full = (write_address == read_address) & (internal_used != 0);
assign used = internal_used; // this signal reflects the number of words in the FIFO
assign empty = internal_empty; // combinational so it'll glitch a little bit
assign full = internal_full; // dito
endmodule
|
module fifo_with_byteenables (
clk,
areset,
sreset,
write_data,
write_byteenables,
write,
push,
read_data,
pop,
used,
full,
empty
);
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 128;
parameter FIFO_DEPTH_LOG2 = 7; // this impacts the width of the used port so it can't be local
parameter LATENCY = 1; // number of clock cycles after asserting 'pop' that valid data comes out
input clk;
input areset;
input sreset;
input [DATA_WIDTH-1:0] write_data;
input [(DATA_WIDTH/8)-1:0] write_byteenables;
input write;
input push; // when you have written to all the byte lanes assert this to commit the word (you can use it at the same time as the byte enables)
output wire [DATA_WIDTH-1:0] read_data;
input pop; // use this to read a word out of the FIFO
output wire [FIFO_DEPTH_LOG2:0] used;
output wire full;
output wire empty;
reg [FIFO_DEPTH_LOG2-1:0] write_address;
reg [FIFO_DEPTH_LOG2-1:0] read_address;
reg [FIFO_DEPTH_LOG2:0] internal_used;
wire internal_full;
wire internal_empty;
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
write_address <= 0;
end
else
begin
if (sreset)
begin
write_address <= 0;
end
else if (push == 1)
begin
write_address <= write_address + 1'b1;
end
end
end
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
read_address <= 0;
end
else
begin
if (sreset)
begin
read_address <= 0;
end
else if (pop == 1)
begin
read_address <= read_address + 1'b1;
end
end
end
// TODO: Change this to an inferrered RAM when Quartus II supports byte enables for inferred RAM
altsyncram the_dp_ram (
.clock0 (clk),
.wren_a (write),
.byteena_a (write_byteenables),
.data_a (write_data),
.address_a (write_address),
.q_b (read_data),
.address_b (read_address)
);
defparam the_dp_ram.operation_mode = "DUAL_PORT"; // simple dual port (one read, one write port)
defparam the_dp_ram.lpm_type = "altsyncram";
defparam the_dp_ram.read_during_write_mode_mixed_ports = "DONT_CARE";
defparam the_dp_ram.power_up_uninitialized = "TRUE";
defparam the_dp_ram.byte_size = 8;
defparam the_dp_ram.width_a = DATA_WIDTH;
defparam the_dp_ram.width_b = DATA_WIDTH;
defparam the_dp_ram.widthad_a = FIFO_DEPTH_LOG2;
defparam the_dp_ram.widthad_b = FIFO_DEPTH_LOG2;
defparam the_dp_ram.width_byteena_a = (DATA_WIDTH/8);
defparam the_dp_ram.numwords_a = FIFO_DEPTH;
defparam the_dp_ram.numwords_b = FIFO_DEPTH;
defparam the_dp_ram.address_reg_b = "CLOCK0";
defparam the_dp_ram.outdata_reg_b = (LATENCY == 2)? "CLOCK0" : "UNREGISTERED";
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
internal_used <= 0;
end
else
begin
if (sreset)
begin
internal_used <= 0;
end
else
begin
case ({push, pop})
2'b01: internal_used <= internal_used - 1'b1;
2'b10: internal_used <= internal_used + 1'b1;
default: internal_used <= internal_used;
endcase
end
end
end
assign internal_empty = (read_address == write_address) & (internal_used == 0);
assign internal_full = (write_address == read_address) & (internal_used != 0);
assign used = internal_used; // this signal reflects the number of words in the FIFO
assign empty = internal_empty; // combinational so it'll glitch a little bit
assign full = internal_full; // dito
endmodule
|
module generic_baseblocks_v2_1_0_nto1_mux #
(
parameter integer C_RATIO = 1, // Range: >=1
parameter integer C_SEL_WIDTH = 1, // Range: >=1; recommended: ceil_log2(C_RATIO)
parameter integer C_DATAOUT_WIDTH = 1, // Range: >=1
parameter integer C_ONEHOT = 0 // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)
)
(
input wire [C_RATIO-1:0] SEL_ONEHOT, // One-hot generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=1)
input wire [C_SEL_WIDTH-1:0] SEL, // Binary-encoded generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=0)
input wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN, // Data input array (num_selections x data_width)
output wire [C_DATAOUT_WIDTH-1:0] OUT // Data output vector
);
wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;
genvar i;
generate
if (C_ONEHOT == 0) begin : gen_encoded
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1'b1:1'b0}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{(SEL==i)?1'b1:1'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end else begin : gen_onehot
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end
endgenerate
assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:
C_DATAOUT_WIDTH*(C_RATIO-1)];
endmodule
|
module mem_window (
clk,
reset,
// Memory slave port
s1_address,
s1_read,
s1_readdata,
s1_readdatavalid,
s1_write,
s1_writedata,
s1_burstcount,
s1_byteenable,
s1_waitrequest,
// Configuration register slave port
cra_write,
cra_writedata,
cra_byteenable,
// Bridged master port to memory
m1_address,
m1_read,
m1_readdata,
m1_readdatavalid,
m1_write,
m1_writedata,
m1_burstcount,
m1_byteenable,
m1_waitrequest
);
parameter PAGE_ADDRESS_WIDTH = 20;
parameter MEM_ADDRESS_WIDTH = 32;
parameter NUM_BYTES = 32;
parameter BURSTCOUNT_WIDTH = 1;
parameter CRA_BITWIDTH = 32;
localparam ADDRESS_SHIFT = $clog2(NUM_BYTES);
localparam PAGE_ID_WIDTH = MEM_ADDRESS_WIDTH - PAGE_ADDRESS_WIDTH - ADDRESS_SHIFT;
localparam DATA_WIDTH = NUM_BYTES * 8;
input clk;
input reset;
// Memory slave port
input [PAGE_ADDRESS_WIDTH-1:0] s1_address;
input s1_read;
output [DATA_WIDTH-1:0] s1_readdata;
output s1_readdatavalid;
input s1_write;
input [DATA_WIDTH-1:0] s1_writedata;
input [BURSTCOUNT_WIDTH-1:0] s1_burstcount;
input [NUM_BYTES-1:0] s1_byteenable;
output s1_waitrequest;
// Bridged master port to memory
output [MEM_ADDRESS_WIDTH-1:0] m1_address;
output m1_read;
input [DATA_WIDTH-1:0] m1_readdata;
input m1_readdatavalid;
output m1_write;
output [DATA_WIDTH-1:0] m1_writedata;
output [BURSTCOUNT_WIDTH-1:0] m1_burstcount;
output [NUM_BYTES-1:0] m1_byteenable;
input m1_waitrequest;
// CRA slave
input cra_write;
input [CRA_BITWIDTH-1:0] cra_writedata;
input [CRA_BITWIDTH/8-1:0] cra_byteenable;
// Architecture
// CRA slave allows the master to change the active page
reg [PAGE_ID_WIDTH-1:0] page_id;
reg [CRA_BITWIDTH-1:0] cra_writemask;
integer i;
always@*
for (i=0; i<CRA_BITWIDTH; i=i+1)
cra_writemask[i] = cra_byteenable[i/8] & cra_write;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
page_id <= {PAGE_ID_WIDTH{1'b0}};
else
page_id <= (cra_writedata & cra_writemask) | (page_id & ~cra_writemask);
end
// The s1 port bridges to the m1 port - with the page ID tacked on to the address
assign m1_address = {page_id, s1_address, {ADDRESS_SHIFT{1'b0}}};
assign m1_read = s1_read;
assign s1_readdata = m1_readdata;
assign s1_readdatavalid = m1_readdatavalid;
assign m1_write = s1_write;
assign m1_writedata = s1_writedata;
assign m1_burstcount = s1_burstcount;
assign m1_byteenable = s1_byteenable;
assign s1_waitrequest = m1_waitrequest;
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.