module_content
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1.05M
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module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
lpm_bustri lpm_bustri_component (
.tridata (tridata),
.enabledt (enabledt),
.data (data));
defparam
lpm_bustri_component.lpm_width = 16,
lpm_bustri_component.lpm_type = "LPM_BUSTRI";
endmodule
|
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
lpm_bustri lpm_bustri_component (
.tridata (tridata),
.enabledt (enabledt),
.data (data));
defparam
lpm_bustri_component.lpm_width = 16,
lpm_bustri_component.lpm_type = "LPM_BUSTRI";
endmodule
|
module sub32 (
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] dataa;
input [31:0] datab;
input clock;
input aclr;
input clken;
output [31:0] result;
endmodule
|
module sub32 (
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] dataa;
input [31:0] datab;
input clock;
input aclr;
input clken;
output [31:0] result;
endmodule
|
module sub32 (
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] dataa;
input [31:0] datab;
input clock;
input aclr;
input clken;
output [31:0] result;
endmodule
|
module rx_chain
(input clock,
input reset,
input enable,
input wire [7:0] decim_rate,
input sample_strobe,
input decimator_strobe,
output wire hb_strobe,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debugdata,output wire [15:0] debugctrl
);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
wire [31:0] phase;
wire [15:0] bb_i, bb_q;
wire [15:0] hb_in_i, hb_in_q;
assign debugdata = hb_in_i;
`ifdef RX_NCO_ON
phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc
(.clk(clock),.reset(reset),.enable(enable),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.strobe(sample_strobe),.phase(phase) );
cordic rx_cordic
( .clock(clock),.reset(reset),.enable(enable),
.xi(i_in),.yi(q_in),.zi(phase[31:16]),
.xo(bb_i),.yo(bb_q),.zo() );
`else
assign bb_i = i_in;
assign bb_q = q_in;
assign sample_strobe = 1;
`endif // !`ifdef RX_NCO_ON
`ifdef RX_CIC_ON
cic_decim cic_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i),.signal_out(hb_in_i) );
`else
assign hb_in_i = bb_i;
assign decimator_strobe = sample_strobe;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_i_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(hb_strobe),
.data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) );
`else
assign i_out = hb_in_i;
assign hb_strobe = decimator_strobe;
`endif
`ifdef RX_CIC_ON
cic_decim cic_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q),.signal_out(hb_in_q) );
`else
assign hb_in_q = bb_q;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_q_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(),
.data_in(hb_in_q),.data_out(q_out) );
`else
assign q_out = hb_in_q;
`endif
endmodule
|
module rx_chain
(input clock,
input reset,
input enable,
input wire [7:0] decim_rate,
input sample_strobe,
input decimator_strobe,
output wire hb_strobe,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debugdata,output wire [15:0] debugctrl
);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
wire [31:0] phase;
wire [15:0] bb_i, bb_q;
wire [15:0] hb_in_i, hb_in_q;
assign debugdata = hb_in_i;
`ifdef RX_NCO_ON
phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc
(.clk(clock),.reset(reset),.enable(enable),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.strobe(sample_strobe),.phase(phase) );
cordic rx_cordic
( .clock(clock),.reset(reset),.enable(enable),
.xi(i_in),.yi(q_in),.zi(phase[31:16]),
.xo(bb_i),.yo(bb_q),.zo() );
`else
assign bb_i = i_in;
assign bb_q = q_in;
assign sample_strobe = 1;
`endif // !`ifdef RX_NCO_ON
`ifdef RX_CIC_ON
cic_decim cic_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i),.signal_out(hb_in_i) );
`else
assign hb_in_i = bb_i;
assign decimator_strobe = sample_strobe;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_i_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(hb_strobe),
.data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) );
`else
assign i_out = hb_in_i;
assign hb_strobe = decimator_strobe;
`endif
`ifdef RX_CIC_ON
cic_decim cic_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q),.signal_out(hb_in_q) );
`else
assign hb_in_q = bb_q;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_q_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(),
.data_in(hb_in_q),.data_out(q_out) );
`else
assign q_out = hb_in_q;
`endif
endmodule
|
module rx_chain
(input clock,
input reset,
input enable,
input wire [7:0] decim_rate,
input sample_strobe,
input decimator_strobe,
output wire hb_strobe,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debugdata,output wire [15:0] debugctrl
);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
wire [31:0] phase;
wire [15:0] bb_i, bb_q;
wire [15:0] hb_in_i, hb_in_q;
assign debugdata = hb_in_i;
`ifdef RX_NCO_ON
phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc
(.clk(clock),.reset(reset),.enable(enable),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.strobe(sample_strobe),.phase(phase) );
cordic rx_cordic
( .clock(clock),.reset(reset),.enable(enable),
.xi(i_in),.yi(q_in),.zi(phase[31:16]),
.xo(bb_i),.yo(bb_q),.zo() );
`else
assign bb_i = i_in;
assign bb_q = q_in;
assign sample_strobe = 1;
`endif // !`ifdef RX_NCO_ON
`ifdef RX_CIC_ON
cic_decim cic_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i),.signal_out(hb_in_i) );
`else
assign hb_in_i = bb_i;
assign decimator_strobe = sample_strobe;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_i_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(hb_strobe),
.data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) );
`else
assign i_out = hb_in_i;
assign hb_strobe = decimator_strobe;
`endif
`ifdef RX_CIC_ON
cic_decim cic_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q),.signal_out(hb_in_q) );
`else
assign hb_in_q = bb_q;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_q_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(),
.data_in(hb_in_q),.data_out(q_out) );
`else
assign q_out = hb_in_q;
`endif
endmodule
|
module rx_chain
(input clock,
input reset,
input enable,
input wire [7:0] decim_rate,
input sample_strobe,
input decimator_strobe,
output wire hb_strobe,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debugdata,output wire [15:0] debugctrl
);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
wire [31:0] phase;
wire [15:0] bb_i, bb_q;
wire [15:0] hb_in_i, hb_in_q;
assign debugdata = hb_in_i;
`ifdef RX_NCO_ON
phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc
(.clk(clock),.reset(reset),.enable(enable),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.strobe(sample_strobe),.phase(phase) );
cordic rx_cordic
( .clock(clock),.reset(reset),.enable(enable),
.xi(i_in),.yi(q_in),.zi(phase[31:16]),
.xo(bb_i),.yo(bb_q),.zo() );
`else
assign bb_i = i_in;
assign bb_q = q_in;
assign sample_strobe = 1;
`endif // !`ifdef RX_NCO_ON
`ifdef RX_CIC_ON
cic_decim cic_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i),.signal_out(hb_in_i) );
`else
assign hb_in_i = bb_i;
assign decimator_strobe = sample_strobe;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_i_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(hb_strobe),
.data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) );
`else
assign i_out = hb_in_i;
assign hb_strobe = decimator_strobe;
`endif
`ifdef RX_CIC_ON
cic_decim cic_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q),.signal_out(hb_in_q) );
`else
assign hb_in_q = bb_q;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_q_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(),
.data_in(hb_in_q),.data_out(q_out) );
`else
assign q_out = hb_in_q;
`endif
endmodule
|
module my_dcm (
input CLKIN,
output CLKFX,
output LOCKED,
input RST,
output[7:0] STATUS
);
// DCM: Digital Clock Manager Circuit
// Spartan-3
// Xilinx HDL Language Template, version 11.1
DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(41.667), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hFFFF), // FACTORY JF values
// .LOC("DCM_X0Y0"),
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(CLK0), // 0 degree DCM CLK output
.CLK180(CLK180), // 180 degree DCM CLK output
.CLK270(CLK270), // 270 degree DCM CLK output
.CLK2X(CLK2X), // 2X DCM CLK output
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
.CLK90(CLK90), // 90 degree DCM CLK output
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
.LOCKED(LOCKED), // DCM LOCK status output
.PSDONE(PSDONE), // Dynamic phase adjust done output
.STATUS(STATUS), // 8-bit DCM status bits output
.CLKFB(CLKFB), // DCM clock feedback
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(PSCLK), // Dynamic phase adjust clock input
.PSEN(PSEN), // Dynamic phase adjust enable input
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
.RST(RST) // DCM asynchronous reset input
);
endmodule
|
module halfband_interp
(input clock, input reset, input enable,
input strobe_in, input strobe_out,
input [15:0] signal_in_i, input [15:0] signal_in_q,
output reg [15:0] signal_out_i, output reg [15:0] signal_out_q,
output wire [12:0] debug);
wire [15:0] coeff_ram_out;
wire [15:0] data_ram_out_i;
wire [15:0] data_ram_out_q;
wire [3:0] data_rd_addr;
reg [3:0] data_wr_addr;
reg [2:0] coeff_rd_addr;
wire filt_done;
wire [15:0] mac_out_i;
wire [15:0] mac_out_q;
reg [15:0] delayed_middle_i, delayed_middle_q;
wire [7:0] shift = 8'd9;
reg stb_out_happened;
wire [15:0] data_ram_out_i_b;
always @(posedge clock)
if(strobe_in)
stb_out_happened <= #1 1'b0;
else if(strobe_out)
stb_out_happened <= #1 1'b1;
assign debug = {filt_done,data_rd_addr,data_wr_addr,coeff_rd_addr};
wire [15:0] signal_out_i = stb_out_happened ? mac_out_i : delayed_middle_i;
wire [15:0] signal_out_q = stb_out_happened ? mac_out_q : delayed_middle_q;
/* always @(posedge clock)
if(reset)
begin
signal_out_i <= #1 16'd0;
signal_out_q <= #1 16'd0;
end
else if(strobe_in)
begin
signal_out_i <= #1 delayed_middle_i; // Multiply by 1 for middle coeff
signal_out_q <= #1 delayed_middle_q;
end
//else if(filt_done&stb_out_happened)
else if(stb_out_happened)
begin
signal_out_i <= #1 mac_out_i;
signal_out_q <= #1 mac_out_q;
end
*/
always @(posedge clock)
if(reset)
coeff_rd_addr <= #1 3'd0;
else if(coeff_rd_addr != 3'd0)
coeff_rd_addr <= #1 coeff_rd_addr + 3'd1;
else if(strobe_in)
coeff_rd_addr <= #1 3'd1;
reg filt_done_d1;
always@(posedge clock)
filt_done_d1 <= #1 filt_done;
always @(posedge clock)
if(reset)
data_wr_addr <= #1 4'd0;
//else if(strobe_in)
else if(filt_done & ~filt_done_d1)
data_wr_addr <= #1 data_wr_addr + 4'd1;
always @(posedge clock)
if(coeff_rd_addr == 3'd7)
begin
delayed_middle_i <= #1 data_ram_out_i_b;
// delayed_middle_q <= #1 data_ram_out_q_b;
end
// always @(posedge clock)
// if(reset)
// data_rd_addr <= #1 4'd0;
// else if(strobe_in)
// data_rd_addr <= #1 data_wr_addr + 4'd1;
// else if(!filt_done)
// data_rd_addr <= #1 data_rd_addr + 4'd1;
// else
// data_rd_addr <= #1 data_wr_addr;
wire [3:0] data_rd_addr1 = data_wr_addr + {1'b0,coeff_rd_addr};
wire [3:0] data_rd_addr2 = data_wr_addr + 15 - {1'b0,coeff_rd_addr};
// always @(posedge clock)
// if(reset)
// filt_done <= #1 1'b1;
// else if(strobe_in)
// filt_done <= #1 1'b0;
// else if(coeff_rd_addr == 4'd0)
// filt_done <= #1 1'b1;
assign filt_done = (coeff_rd_addr == 3'd0);
coeff_ram coeff_ram ( .clock(clock),.rd_addr({1'b0,coeff_rd_addr}),.rd_data(coeff_ram_out) );
ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_i),
.rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_i_b),.sum(data_ram_out_i));
ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_q),
.rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_q));
mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
.x(data_ram_out_i),.y(coeff_ram_out),.shift(shift),.z(mac_out_i) );
mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
.x(data_ram_out_q),.y(coeff_ram_out),.shift(shift),.z(mac_out_q) );
endmodule
|
module halfband_interp
(input clock, input reset, input enable,
input strobe_in, input strobe_out,
input [15:0] signal_in_i, input [15:0] signal_in_q,
output reg [15:0] signal_out_i, output reg [15:0] signal_out_q,
output wire [12:0] debug);
wire [15:0] coeff_ram_out;
wire [15:0] data_ram_out_i;
wire [15:0] data_ram_out_q;
wire [3:0] data_rd_addr;
reg [3:0] data_wr_addr;
reg [2:0] coeff_rd_addr;
wire filt_done;
wire [15:0] mac_out_i;
wire [15:0] mac_out_q;
reg [15:0] delayed_middle_i, delayed_middle_q;
wire [7:0] shift = 8'd9;
reg stb_out_happened;
wire [15:0] data_ram_out_i_b;
always @(posedge clock)
if(strobe_in)
stb_out_happened <= #1 1'b0;
else if(strobe_out)
stb_out_happened <= #1 1'b1;
assign debug = {filt_done,data_rd_addr,data_wr_addr,coeff_rd_addr};
wire [15:0] signal_out_i = stb_out_happened ? mac_out_i : delayed_middle_i;
wire [15:0] signal_out_q = stb_out_happened ? mac_out_q : delayed_middle_q;
/* always @(posedge clock)
if(reset)
begin
signal_out_i <= #1 16'd0;
signal_out_q <= #1 16'd0;
end
else if(strobe_in)
begin
signal_out_i <= #1 delayed_middle_i; // Multiply by 1 for middle coeff
signal_out_q <= #1 delayed_middle_q;
end
//else if(filt_done&stb_out_happened)
else if(stb_out_happened)
begin
signal_out_i <= #1 mac_out_i;
signal_out_q <= #1 mac_out_q;
end
*/
always @(posedge clock)
if(reset)
coeff_rd_addr <= #1 3'd0;
else if(coeff_rd_addr != 3'd0)
coeff_rd_addr <= #1 coeff_rd_addr + 3'd1;
else if(strobe_in)
coeff_rd_addr <= #1 3'd1;
reg filt_done_d1;
always@(posedge clock)
filt_done_d1 <= #1 filt_done;
always @(posedge clock)
if(reset)
data_wr_addr <= #1 4'd0;
//else if(strobe_in)
else if(filt_done & ~filt_done_d1)
data_wr_addr <= #1 data_wr_addr + 4'd1;
always @(posedge clock)
if(coeff_rd_addr == 3'd7)
begin
delayed_middle_i <= #1 data_ram_out_i_b;
// delayed_middle_q <= #1 data_ram_out_q_b;
end
// always @(posedge clock)
// if(reset)
// data_rd_addr <= #1 4'd0;
// else if(strobe_in)
// data_rd_addr <= #1 data_wr_addr + 4'd1;
// else if(!filt_done)
// data_rd_addr <= #1 data_rd_addr + 4'd1;
// else
// data_rd_addr <= #1 data_wr_addr;
wire [3:0] data_rd_addr1 = data_wr_addr + {1'b0,coeff_rd_addr};
wire [3:0] data_rd_addr2 = data_wr_addr + 15 - {1'b0,coeff_rd_addr};
// always @(posedge clock)
// if(reset)
// filt_done <= #1 1'b1;
// else if(strobe_in)
// filt_done <= #1 1'b0;
// else if(coeff_rd_addr == 4'd0)
// filt_done <= #1 1'b1;
assign filt_done = (coeff_rd_addr == 3'd0);
coeff_ram coeff_ram ( .clock(clock),.rd_addr({1'b0,coeff_rd_addr}),.rd_data(coeff_ram_out) );
ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_i),
.rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_i_b),.sum(data_ram_out_i));
ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_q),
.rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_q));
mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
.x(data_ram_out_i),.y(coeff_ram_out),.shift(shift),.z(mac_out_i) );
mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
.x(data_ram_out_q),.y(coeff_ram_out),.shift(shift),.z(mac_out_q) );
endmodule
|
module add32_add_sub_nq7
(
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] wire_add_sub_cella_combout;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [7:0] wire_add_sub_cella_dataa;
wire [7:0] wire_add_sub_cella_datab;
stratix_lcell add_sub_cella_0
(
.cin(1'b0),
.combout(wire_add_sub_cella_combout[0:0]),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]));
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "96e8",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_1
(
.cin(wire_add_sub_cella_0cout[0:0]),
.combout(wire_add_sub_cella_combout[1:1]),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]));
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "96e8",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_2
(
.cin(wire_add_sub_cella_1cout[0:0]),
.combout(wire_add_sub_cella_combout[2:2]),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]));
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "96e8",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_3
(
.cin(wire_add_sub_cella_2cout[0:0]),
.combout(wire_add_sub_cella_combout[3:3]),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]));
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "96e8",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_4
(
.cin(wire_add_sub_cella_3cout[0:0]),
.combout(wire_add_sub_cella_combout[4:4]),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]));
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "96e8",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_5
(
.cin(wire_add_sub_cella_4cout[0:0]),
.combout(wire_add_sub_cella_combout[5:5]),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]));
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "96e8",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_6
(
.cin(wire_add_sub_cella_5cout[0:0]),
.combout(wire_add_sub_cella_combout[6:6]),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]));
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "96e8",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_7
(
.cin(wire_add_sub_cella_6cout[0:0]),
.combout(wire_add_sub_cella_combout[7:7]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]));
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "9696",
add_sub_cella_7.operation_mode = "normal",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "stratix_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_combout;
endmodule
|
module add32 (
dataa,
datab,
result)/* synthesis synthesis_clearbox = 1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] sub_wire0;
wire [7:0] result = sub_wire0[7:0];
add32_add_sub_nq7 add32_add_sub_nq7_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0));
endmodule
|
module add32_add_sub_nq7
(
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] wire_add_sub_cella_combout;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [7:0] wire_add_sub_cella_dataa;
wire [7:0] wire_add_sub_cella_datab;
stratix_lcell add_sub_cella_0
(
.cin(1'b0),
.combout(wire_add_sub_cella_combout[0:0]),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]));
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "96e8",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_1
(
.cin(wire_add_sub_cella_0cout[0:0]),
.combout(wire_add_sub_cella_combout[1:1]),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]));
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "96e8",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_2
(
.cin(wire_add_sub_cella_1cout[0:0]),
.combout(wire_add_sub_cella_combout[2:2]),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]));
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "96e8",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_3
(
.cin(wire_add_sub_cella_2cout[0:0]),
.combout(wire_add_sub_cella_combout[3:3]),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]));
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "96e8",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_4
(
.cin(wire_add_sub_cella_3cout[0:0]),
.combout(wire_add_sub_cella_combout[4:4]),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]));
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "96e8",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_5
(
.cin(wire_add_sub_cella_4cout[0:0]),
.combout(wire_add_sub_cella_combout[5:5]),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]));
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "96e8",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_6
(
.cin(wire_add_sub_cella_5cout[0:0]),
.combout(wire_add_sub_cella_combout[6:6]),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]));
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "96e8",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_7
(
.cin(wire_add_sub_cella_6cout[0:0]),
.combout(wire_add_sub_cella_combout[7:7]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]));
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "9696",
add_sub_cella_7.operation_mode = "normal",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "stratix_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_combout;
endmodule
|
module add32 (
dataa,
datab,
result)/* synthesis synthesis_clearbox = 1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] sub_wire0;
wire [7:0] result = sub_wire0[7:0];
add32_add_sub_nq7 add32_add_sub_nq7_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0));
endmodule
|
module add32_add_sub_nq7
(
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] wire_add_sub_cella_combout;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [7:0] wire_add_sub_cella_dataa;
wire [7:0] wire_add_sub_cella_datab;
stratix_lcell add_sub_cella_0
(
.cin(1'b0),
.combout(wire_add_sub_cella_combout[0:0]),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]));
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "96e8",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_1
(
.cin(wire_add_sub_cella_0cout[0:0]),
.combout(wire_add_sub_cella_combout[1:1]),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]));
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "96e8",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_2
(
.cin(wire_add_sub_cella_1cout[0:0]),
.combout(wire_add_sub_cella_combout[2:2]),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]));
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "96e8",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_3
(
.cin(wire_add_sub_cella_2cout[0:0]),
.combout(wire_add_sub_cella_combout[3:3]),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]));
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "96e8",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_4
(
.cin(wire_add_sub_cella_3cout[0:0]),
.combout(wire_add_sub_cella_combout[4:4]),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]));
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "96e8",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_5
(
.cin(wire_add_sub_cella_4cout[0:0]),
.combout(wire_add_sub_cella_combout[5:5]),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]));
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "96e8",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_6
(
.cin(wire_add_sub_cella_5cout[0:0]),
.combout(wire_add_sub_cella_combout[6:6]),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]));
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "96e8",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_7
(
.cin(wire_add_sub_cella_6cout[0:0]),
.combout(wire_add_sub_cella_combout[7:7]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]));
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "9696",
add_sub_cella_7.operation_mode = "normal",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "stratix_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_combout;
endmodule
|
module add32 (
dataa,
datab,
result)/* synthesis synthesis_clearbox = 1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] sub_wire0;
wire [7:0] result = sub_wire0[7:0];
add32_add_sub_nq7 add32_add_sub_nq7_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0));
endmodule
|
module add32_add_sub_nq7
(
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] wire_add_sub_cella_combout;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [7:0] wire_add_sub_cella_dataa;
wire [7:0] wire_add_sub_cella_datab;
stratix_lcell add_sub_cella_0
(
.cin(1'b0),
.combout(wire_add_sub_cella_combout[0:0]),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]));
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "96e8",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_1
(
.cin(wire_add_sub_cella_0cout[0:0]),
.combout(wire_add_sub_cella_combout[1:1]),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]));
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "96e8",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_2
(
.cin(wire_add_sub_cella_1cout[0:0]),
.combout(wire_add_sub_cella_combout[2:2]),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]));
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "96e8",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_3
(
.cin(wire_add_sub_cella_2cout[0:0]),
.combout(wire_add_sub_cella_combout[3:3]),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]));
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "96e8",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_4
(
.cin(wire_add_sub_cella_3cout[0:0]),
.combout(wire_add_sub_cella_combout[4:4]),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]));
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "96e8",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_5
(
.cin(wire_add_sub_cella_4cout[0:0]),
.combout(wire_add_sub_cella_combout[5:5]),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]));
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "96e8",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_6
(
.cin(wire_add_sub_cella_5cout[0:0]),
.combout(wire_add_sub_cella_combout[6:6]),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]));
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "96e8",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_7
(
.cin(wire_add_sub_cella_6cout[0:0]),
.combout(wire_add_sub_cella_combout[7:7]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]));
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "9696",
add_sub_cella_7.operation_mode = "normal",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "stratix_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_combout;
endmodule
|
module add32 (
dataa,
datab,
result)/* synthesis synthesis_clearbox = 1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] sub_wire0;
wire [7:0] result = sub_wire0[7:0];
add32_add_sub_nq7 add32_add_sub_nq7_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0));
endmodule
|
module tx_chain
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out
);
wire [15:0] bb_i, bb_q;
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
.signal_in(i_in),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
.signal_in(q_in),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule
|
module tx_chain
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out
);
wire [15:0] bb_i, bb_q;
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
.signal_in(i_in),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
.signal_in(q_in),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule
|
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
endmodule
|
module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth <2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg[31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0)
random <= $random(RANDOM_SEED);
else
random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_last <= 1'b0;
else
din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= din;
end
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
|
module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth <2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg[31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0)
random <= $random(RANDOM_SEED);
else
random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_last <= 1'b0;
else
din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= din;
end
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
|
module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth <2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg[31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0)
random <= $random(RANDOM_SEED);
else
random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_last <= 1'b0;
else
din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= din;
end
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
|
module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth <2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg[31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0)
random <= $random(RANDOM_SEED);
else
random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_last <= 1'b0;
else
din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= din;
end
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
|
module accum32_accum_nta
(
aclr,
clken,
clock,
data,
result) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clken;
input clock;
input [31:0] data;
output [31:0] result;
wire [0:0] wire_acc_cella_0cout;
wire [0:0] wire_acc_cella_1cout;
wire [0:0] wire_acc_cella_2cout;
wire [0:0] wire_acc_cella_3cout;
wire [0:0] wire_acc_cella_4cout;
wire [0:0] wire_acc_cella_5cout;
wire [0:0] wire_acc_cella_6cout;
wire [0:0] wire_acc_cella_7cout;
wire [0:0] wire_acc_cella_8cout;
wire [0:0] wire_acc_cella_9cout;
wire [0:0] wire_acc_cella_10cout;
wire [0:0] wire_acc_cella_11cout;
wire [0:0] wire_acc_cella_12cout;
wire [0:0] wire_acc_cella_13cout;
wire [0:0] wire_acc_cella_14cout;
wire [0:0] wire_acc_cella_15cout;
wire [0:0] wire_acc_cella_16cout;
wire [0:0] wire_acc_cella_17cout;
wire [0:0] wire_acc_cella_18cout;
wire [0:0] wire_acc_cella_19cout;
wire [0:0] wire_acc_cella_20cout;
wire [0:0] wire_acc_cella_21cout;
wire [0:0] wire_acc_cella_22cout;
wire [0:0] wire_acc_cella_23cout;
wire [0:0] wire_acc_cella_24cout;
wire [0:0] wire_acc_cella_25cout;
wire [0:0] wire_acc_cella_26cout;
wire [0:0] wire_acc_cella_27cout;
wire [0:0] wire_acc_cella_28cout;
wire [0:0] wire_acc_cella_29cout;
wire [0:0] wire_acc_cella_30cout;
wire [31:0] wire_acc_cella_dataa;
wire [31:0] wire_acc_cella_datab;
wire [31:0] wire_acc_cella_datac;
wire [31:0] wire_acc_cella_regout;
wire sload;
stratix_lcell acc_cella_0
(
.aclr(aclr),
.cin(1'b0),
.clk(clock),
.cout(wire_acc_cella_0cout[0:0]),
.dataa(wire_acc_cella_dataa[0:0]),
.datab(wire_acc_cella_datab[0:0]),
.datac(wire_acc_cella_datac[0:0]),
.ena(clken),
.regout(wire_acc_cella_regout[0:0]),
.sload(sload));
defparam
acc_cella_0.cin_used = "true",
acc_cella_0.lut_mask = "96e8",
acc_cella_0.operation_mode = "arithmetic",
acc_cella_0.sum_lutc_input = "cin",
acc_cella_0.synch_mode = "on",
acc_cella_0.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_1
(
.aclr(aclr),
.cin(wire_acc_cella_0cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_1cout[0:0]),
.dataa(wire_acc_cella_dataa[1:1]),
.datab(wire_acc_cella_datab[1:1]),
.datac(wire_acc_cella_datac[1:1]),
.ena(clken),
.regout(wire_acc_cella_regout[1:1]),
.sload(sload));
defparam
acc_cella_1.cin_used = "true",
acc_cella_1.lut_mask = "96e8",
acc_cella_1.operation_mode = "arithmetic",
acc_cella_1.sum_lutc_input = "cin",
acc_cella_1.synch_mode = "on",
acc_cella_1.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_2
(
.aclr(aclr),
.cin(wire_acc_cella_1cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_2cout[0:0]),
.dataa(wire_acc_cella_dataa[2:2]),
.datab(wire_acc_cella_datab[2:2]),
.datac(wire_acc_cella_datac[2:2]),
.ena(clken),
.regout(wire_acc_cella_regout[2:2]),
.sload(sload));
defparam
acc_cella_2.cin_used = "true",
acc_cella_2.lut_mask = "96e8",
acc_cella_2.operation_mode = "arithmetic",
acc_cella_2.sum_lutc_input = "cin",
acc_cella_2.synch_mode = "on",
acc_cella_2.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_3
(
.aclr(aclr),
.cin(wire_acc_cella_2cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_3cout[0:0]),
.dataa(wire_acc_cella_dataa[3:3]),
.datab(wire_acc_cella_datab[3:3]),
.datac(wire_acc_cella_datac[3:3]),
.ena(clken),
.regout(wire_acc_cella_regout[3:3]),
.sload(sload));
defparam
acc_cella_3.cin_used = "true",
acc_cella_3.lut_mask = "96e8",
acc_cella_3.operation_mode = "arithmetic",
acc_cella_3.sum_lutc_input = "cin",
acc_cella_3.synch_mode = "on",
acc_cella_3.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_4
(
.aclr(aclr),
.cin(wire_acc_cella_3cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_4cout[0:0]),
.dataa(wire_acc_cella_dataa[4:4]),
.datab(wire_acc_cella_datab[4:4]),
.datac(wire_acc_cella_datac[4:4]),
.ena(clken),
.regout(wire_acc_cella_regout[4:4]),
.sload(sload));
defparam
acc_cella_4.cin_used = "true",
acc_cella_4.lut_mask = "96e8",
acc_cella_4.operation_mode = "arithmetic",
acc_cella_4.sum_lutc_input = "cin",
acc_cella_4.synch_mode = "on",
acc_cella_4.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_5
(
.aclr(aclr),
.cin(wire_acc_cella_4cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_5cout[0:0]),
.dataa(wire_acc_cella_dataa[5:5]),
.datab(wire_acc_cella_datab[5:5]),
.datac(wire_acc_cella_datac[5:5]),
.ena(clken),
.regout(wire_acc_cella_regout[5:5]),
.sload(sload));
defparam
acc_cella_5.cin_used = "true",
acc_cella_5.lut_mask = "96e8",
acc_cella_5.operation_mode = "arithmetic",
acc_cella_5.sum_lutc_input = "cin",
acc_cella_5.synch_mode = "on",
acc_cella_5.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_6
(
.aclr(aclr),
.cin(wire_acc_cella_5cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_6cout[0:0]),
.dataa(wire_acc_cella_dataa[6:6]),
.datab(wire_acc_cella_datab[6:6]),
.datac(wire_acc_cella_datac[6:6]),
.ena(clken),
.regout(wire_acc_cella_regout[6:6]),
.sload(sload));
defparam
acc_cella_6.cin_used = "true",
acc_cella_6.lut_mask = "96e8",
acc_cella_6.operation_mode = "arithmetic",
acc_cella_6.sum_lutc_input = "cin",
acc_cella_6.synch_mode = "on",
acc_cella_6.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_7
(
.aclr(aclr),
.cin(wire_acc_cella_6cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_7cout[0:0]),
.dataa(wire_acc_cella_dataa[7:7]),
.datab(wire_acc_cella_datab[7:7]),
.datac(wire_acc_cella_datac[7:7]),
.ena(clken),
.regout(wire_acc_cella_regout[7:7]),
.sload(sload));
defparam
acc_cella_7.cin_used = "true",
acc_cella_7.lut_mask = "96e8",
acc_cella_7.operation_mode = "arithmetic",
acc_cella_7.sum_lutc_input = "cin",
acc_cella_7.synch_mode = "on",
acc_cella_7.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_8
(
.aclr(aclr),
.cin(wire_acc_cella_7cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_8cout[0:0]),
.dataa(wire_acc_cella_dataa[8:8]),
.datab(wire_acc_cella_datab[8:8]),
.datac(wire_acc_cella_datac[8:8]),
.ena(clken),
.regout(wire_acc_cella_regout[8:8]),
.sload(sload));
defparam
acc_cella_8.cin_used = "true",
acc_cella_8.lut_mask = "96e8",
acc_cella_8.operation_mode = "arithmetic",
acc_cella_8.sum_lutc_input = "cin",
acc_cella_8.synch_mode = "on",
acc_cella_8.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_9
(
.aclr(aclr),
.cin(wire_acc_cella_8cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_9cout[0:0]),
.dataa(wire_acc_cella_dataa[9:9]),
.datab(wire_acc_cella_datab[9:9]),
.datac(wire_acc_cella_datac[9:9]),
.ena(clken),
.regout(wire_acc_cella_regout[9:9]),
.sload(sload));
defparam
acc_cella_9.cin_used = "true",
acc_cella_9.lut_mask = "96e8",
acc_cella_9.operation_mode = "arithmetic",
acc_cella_9.sum_lutc_input = "cin",
acc_cella_9.synch_mode = "on",
acc_cella_9.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_10
(
.aclr(aclr),
.cin(wire_acc_cella_9cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_10cout[0:0]),
.dataa(wire_acc_cella_dataa[10:10]),
.datab(wire_acc_cella_datab[10:10]),
.datac(wire_acc_cella_datac[10:10]),
.ena(clken),
.regout(wire_acc_cella_regout[10:10]),
.sload(sload));
defparam
acc_cella_10.cin_used = "true",
acc_cella_10.lut_mask = "96e8",
acc_cella_10.operation_mode = "arithmetic",
acc_cella_10.sum_lutc_input = "cin",
acc_cella_10.synch_mode = "on",
acc_cella_10.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_11
(
.aclr(aclr),
.cin(wire_acc_cella_10cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_11cout[0:0]),
.dataa(wire_acc_cella_dataa[11:11]),
.datab(wire_acc_cella_datab[11:11]),
.datac(wire_acc_cella_datac[11:11]),
.ena(clken),
.regout(wire_acc_cella_regout[11:11]),
.sload(sload));
defparam
acc_cella_11.cin_used = "true",
acc_cella_11.lut_mask = "96e8",
acc_cella_11.operation_mode = "arithmetic",
acc_cella_11.sum_lutc_input = "cin",
acc_cella_11.synch_mode = "on",
acc_cella_11.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_12
(
.aclr(aclr),
.cin(wire_acc_cella_11cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_12cout[0:0]),
.dataa(wire_acc_cella_dataa[12:12]),
.datab(wire_acc_cella_datab[12:12]),
.datac(wire_acc_cella_datac[12:12]),
.ena(clken),
.regout(wire_acc_cella_regout[12:12]),
.sload(sload));
defparam
acc_cella_12.cin_used = "true",
acc_cella_12.lut_mask = "96e8",
acc_cella_12.operation_mode = "arithmetic",
acc_cella_12.sum_lutc_input = "cin",
acc_cella_12.synch_mode = "on",
acc_cella_12.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_13
(
.aclr(aclr),
.cin(wire_acc_cella_12cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_13cout[0:0]),
.dataa(wire_acc_cella_dataa[13:13]),
.datab(wire_acc_cella_datab[13:13]),
.datac(wire_acc_cella_datac[13:13]),
.ena(clken),
.regout(wire_acc_cella_regout[13:13]),
.sload(sload));
defparam
acc_cella_13.cin_used = "true",
acc_cella_13.lut_mask = "96e8",
acc_cella_13.operation_mode = "arithmetic",
acc_cella_13.sum_lutc_input = "cin",
acc_cella_13.synch_mode = "on",
acc_cella_13.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_14
(
.aclr(aclr),
.cin(wire_acc_cella_13cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_14cout[0:0]),
.dataa(wire_acc_cella_dataa[14:14]),
.datab(wire_acc_cella_datab[14:14]),
.datac(wire_acc_cella_datac[14:14]),
.ena(clken),
.regout(wire_acc_cella_regout[14:14]),
.sload(sload));
defparam
acc_cella_14.cin_used = "true",
acc_cella_14.lut_mask = "96e8",
acc_cella_14.operation_mode = "arithmetic",
acc_cella_14.sum_lutc_input = "cin",
acc_cella_14.synch_mode = "on",
acc_cella_14.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_15
(
.aclr(aclr),
.cin(wire_acc_cella_14cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_15cout[0:0]),
.dataa(wire_acc_cella_dataa[15:15]),
.datab(wire_acc_cella_datab[15:15]),
.datac(wire_acc_cella_datac[15:15]),
.ena(clken),
.regout(wire_acc_cella_regout[15:15]),
.sload(sload));
defparam
acc_cella_15.cin_used = "true",
acc_cella_15.lut_mask = "96e8",
acc_cella_15.operation_mode = "arithmetic",
acc_cella_15.sum_lutc_input = "cin",
acc_cella_15.synch_mode = "on",
acc_cella_15.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_16
(
.aclr(aclr),
.cin(wire_acc_cella_15cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_16cout[0:0]),
.dataa(wire_acc_cella_dataa[16:16]),
.datab(wire_acc_cella_datab[16:16]),
.datac(wire_acc_cella_datac[16:16]),
.ena(clken),
.regout(wire_acc_cella_regout[16:16]),
.sload(sload));
defparam
acc_cella_16.cin_used = "true",
acc_cella_16.lut_mask = "96e8",
acc_cella_16.operation_mode = "arithmetic",
acc_cella_16.sum_lutc_input = "cin",
acc_cella_16.synch_mode = "on",
acc_cella_16.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_17
(
.aclr(aclr),
.cin(wire_acc_cella_16cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_17cout[0:0]),
.dataa(wire_acc_cella_dataa[17:17]),
.datab(wire_acc_cella_datab[17:17]),
.datac(wire_acc_cella_datac[17:17]),
.ena(clken),
.regout(wire_acc_cella_regout[17:17]),
.sload(sload));
defparam
acc_cella_17.cin_used = "true",
acc_cella_17.lut_mask = "96e8",
acc_cella_17.operation_mode = "arithmetic",
acc_cella_17.sum_lutc_input = "cin",
acc_cella_17.synch_mode = "on",
acc_cella_17.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_18
(
.aclr(aclr),
.cin(wire_acc_cella_17cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_18cout[0:0]),
.dataa(wire_acc_cella_dataa[18:18]),
.datab(wire_acc_cella_datab[18:18]),
.datac(wire_acc_cella_datac[18:18]),
.ena(clken),
.regout(wire_acc_cella_regout[18:18]),
.sload(sload));
defparam
acc_cella_18.cin_used = "true",
acc_cella_18.lut_mask = "96e8",
acc_cella_18.operation_mode = "arithmetic",
acc_cella_18.sum_lutc_input = "cin",
acc_cella_18.synch_mode = "on",
acc_cella_18.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_19
(
.aclr(aclr),
.cin(wire_acc_cella_18cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_19cout[0:0]),
.dataa(wire_acc_cella_dataa[19:19]),
.datab(wire_acc_cella_datab[19:19]),
.datac(wire_acc_cella_datac[19:19]),
.ena(clken),
.regout(wire_acc_cella_regout[19:19]),
.sload(sload));
defparam
acc_cella_19.cin_used = "true",
acc_cella_19.lut_mask = "96e8",
acc_cella_19.operation_mode = "arithmetic",
acc_cella_19.sum_lutc_input = "cin",
acc_cella_19.synch_mode = "on",
acc_cella_19.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_20
(
.aclr(aclr),
.cin(wire_acc_cella_19cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_20cout[0:0]),
.dataa(wire_acc_cella_dataa[20:20]),
.datab(wire_acc_cella_datab[20:20]),
.datac(wire_acc_cella_datac[20:20]),
.ena(clken),
.regout(wire_acc_cella_regout[20:20]),
.sload(sload));
defparam
acc_cella_20.cin_used = "true",
acc_cella_20.lut_mask = "96e8",
acc_cella_20.operation_mode = "arithmetic",
acc_cella_20.sum_lutc_input = "cin",
acc_cella_20.synch_mode = "on",
acc_cella_20.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_21
(
.aclr(aclr),
.cin(wire_acc_cella_20cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_21cout[0:0]),
.dataa(wire_acc_cella_dataa[21:21]),
.datab(wire_acc_cella_datab[21:21]),
.datac(wire_acc_cella_datac[21:21]),
.ena(clken),
.regout(wire_acc_cella_regout[21:21]),
.sload(sload));
defparam
acc_cella_21.cin_used = "true",
acc_cella_21.lut_mask = "96e8",
acc_cella_21.operation_mode = "arithmetic",
acc_cella_21.sum_lutc_input = "cin",
acc_cella_21.synch_mode = "on",
acc_cella_21.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_22
(
.aclr(aclr),
.cin(wire_acc_cella_21cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_22cout[0:0]),
.dataa(wire_acc_cella_dataa[22:22]),
.datab(wire_acc_cella_datab[22:22]),
.datac(wire_acc_cella_datac[22:22]),
.ena(clken),
.regout(wire_acc_cella_regout[22:22]),
.sload(sload));
defparam
acc_cella_22.cin_used = "true",
acc_cella_22.lut_mask = "96e8",
acc_cella_22.operation_mode = "arithmetic",
acc_cella_22.sum_lutc_input = "cin",
acc_cella_22.synch_mode = "on",
acc_cella_22.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_23
(
.aclr(aclr),
.cin(wire_acc_cella_22cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_23cout[0:0]),
.dataa(wire_acc_cella_dataa[23:23]),
.datab(wire_acc_cella_datab[23:23]),
.datac(wire_acc_cella_datac[23:23]),
.ena(clken),
.regout(wire_acc_cella_regout[23:23]),
.sload(sload));
defparam
acc_cella_23.cin_used = "true",
acc_cella_23.lut_mask = "96e8",
acc_cella_23.operation_mode = "arithmetic",
acc_cella_23.sum_lutc_input = "cin",
acc_cella_23.synch_mode = "on",
acc_cella_23.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_24
(
.aclr(aclr),
.cin(wire_acc_cella_23cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_24cout[0:0]),
.dataa(wire_acc_cella_dataa[24:24]),
.datab(wire_acc_cella_datab[24:24]),
.datac(wire_acc_cella_datac[24:24]),
.ena(clken),
.regout(wire_acc_cella_regout[24:24]),
.sload(sload));
defparam
acc_cella_24.cin_used = "true",
acc_cella_24.lut_mask = "96e8",
acc_cella_24.operation_mode = "arithmetic",
acc_cella_24.sum_lutc_input = "cin",
acc_cella_24.synch_mode = "on",
acc_cella_24.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_25
(
.aclr(aclr),
.cin(wire_acc_cella_24cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_25cout[0:0]),
.dataa(wire_acc_cella_dataa[25:25]),
.datab(wire_acc_cella_datab[25:25]),
.datac(wire_acc_cella_datac[25:25]),
.ena(clken),
.regout(wire_acc_cella_regout[25:25]),
.sload(sload));
defparam
acc_cella_25.cin_used = "true",
acc_cella_25.lut_mask = "96e8",
acc_cella_25.operation_mode = "arithmetic",
acc_cella_25.sum_lutc_input = "cin",
acc_cella_25.synch_mode = "on",
acc_cella_25.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_26
(
.aclr(aclr),
.cin(wire_acc_cella_25cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_26cout[0:0]),
.dataa(wire_acc_cella_dataa[26:26]),
.datab(wire_acc_cella_datab[26:26]),
.datac(wire_acc_cella_datac[26:26]),
.ena(clken),
.regout(wire_acc_cella_regout[26:26]),
.sload(sload));
defparam
acc_cella_26.cin_used = "true",
acc_cella_26.lut_mask = "96e8",
acc_cella_26.operation_mode = "arithmetic",
acc_cella_26.sum_lutc_input = "cin",
acc_cella_26.synch_mode = "on",
acc_cella_26.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_27
(
.aclr(aclr),
.cin(wire_acc_cella_26cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_27cout[0:0]),
.dataa(wire_acc_cella_dataa[27:27]),
.datab(wire_acc_cella_datab[27:27]),
.datac(wire_acc_cella_datac[27:27]),
.ena(clken),
.regout(wire_acc_cella_regout[27:27]),
.sload(sload));
defparam
acc_cella_27.cin_used = "true",
acc_cella_27.lut_mask = "96e8",
acc_cella_27.operation_mode = "arithmetic",
acc_cella_27.sum_lutc_input = "cin",
acc_cella_27.synch_mode = "on",
acc_cella_27.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_28
(
.aclr(aclr),
.cin(wire_acc_cella_27cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_28cout[0:0]),
.dataa(wire_acc_cella_dataa[28:28]),
.datab(wire_acc_cella_datab[28:28]),
.datac(wire_acc_cella_datac[28:28]),
.ena(clken),
.regout(wire_acc_cella_regout[28:28]),
.sload(sload));
defparam
acc_cella_28.cin_used = "true",
acc_cella_28.lut_mask = "96e8",
acc_cella_28.operation_mode = "arithmetic",
acc_cella_28.sum_lutc_input = "cin",
acc_cella_28.synch_mode = "on",
acc_cella_28.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_29
(
.aclr(aclr),
.cin(wire_acc_cella_28cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_29cout[0:0]),
.dataa(wire_acc_cella_dataa[29:29]),
.datab(wire_acc_cella_datab[29:29]),
.datac(wire_acc_cella_datac[29:29]),
.ena(clken),
.regout(wire_acc_cella_regout[29:29]),
.sload(sload));
defparam
acc_cella_29.cin_used = "true",
acc_cella_29.lut_mask = "96e8",
acc_cella_29.operation_mode = "arithmetic",
acc_cella_29.sum_lutc_input = "cin",
acc_cella_29.synch_mode = "on",
acc_cella_29.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_30
(
.aclr(aclr),
.cin(wire_acc_cella_29cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_30cout[0:0]),
.dataa(wire_acc_cella_dataa[30:30]),
.datab(wire_acc_cella_datab[30:30]),
.datac(wire_acc_cella_datac[30:30]),
.ena(clken),
.regout(wire_acc_cella_regout[30:30]),
.sload(sload));
defparam
acc_cella_30.cin_used = "true",
acc_cella_30.lut_mask = "96e8",
acc_cella_30.operation_mode = "arithmetic",
acc_cella_30.sum_lutc_input = "cin",
acc_cella_30.synch_mode = "on",
acc_cella_30.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_31
(
.aclr(aclr),
.cin(wire_acc_cella_30cout[0:0]),
.clk(clock),
.dataa(wire_acc_cella_dataa[31:31]),
.datab(wire_acc_cella_datab[31:31]),
.datac(wire_acc_cella_datac[31:31]),
.ena(clken),
.regout(wire_acc_cella_regout[31:31]),
.sload(sload));
defparam
acc_cella_31.cin_used = "true",
acc_cella_31.lut_mask = "9696",
acc_cella_31.operation_mode = "normal",
acc_cella_31.sum_lutc_input = "cin",
acc_cella_31.synch_mode = "on",
acc_cella_31.lpm_type = "stratix_lcell";
assign
wire_acc_cella_dataa = data,
wire_acc_cella_datab = wire_acc_cella_regout,
wire_acc_cella_datac = data;
assign
result = wire_acc_cella_regout,
sload = 1'b0;
endmodule
|
module accum32 (
data,
clock,
clken,
aclr,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] data;
input clock;
input clken;
input aclr;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
accum32_accum_nta accum32_accum_nta_component (
.clken (clken),
.aclr (aclr),
.clock (clock),
.data (data),
.result (sub_wire0));
endmodule
|
module accum32_accum_nta
(
aclr,
clken,
clock,
data,
result) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clken;
input clock;
input [31:0] data;
output [31:0] result;
wire [0:0] wire_acc_cella_0cout;
wire [0:0] wire_acc_cella_1cout;
wire [0:0] wire_acc_cella_2cout;
wire [0:0] wire_acc_cella_3cout;
wire [0:0] wire_acc_cella_4cout;
wire [0:0] wire_acc_cella_5cout;
wire [0:0] wire_acc_cella_6cout;
wire [0:0] wire_acc_cella_7cout;
wire [0:0] wire_acc_cella_8cout;
wire [0:0] wire_acc_cella_9cout;
wire [0:0] wire_acc_cella_10cout;
wire [0:0] wire_acc_cella_11cout;
wire [0:0] wire_acc_cella_12cout;
wire [0:0] wire_acc_cella_13cout;
wire [0:0] wire_acc_cella_14cout;
wire [0:0] wire_acc_cella_15cout;
wire [0:0] wire_acc_cella_16cout;
wire [0:0] wire_acc_cella_17cout;
wire [0:0] wire_acc_cella_18cout;
wire [0:0] wire_acc_cella_19cout;
wire [0:0] wire_acc_cella_20cout;
wire [0:0] wire_acc_cella_21cout;
wire [0:0] wire_acc_cella_22cout;
wire [0:0] wire_acc_cella_23cout;
wire [0:0] wire_acc_cella_24cout;
wire [0:0] wire_acc_cella_25cout;
wire [0:0] wire_acc_cella_26cout;
wire [0:0] wire_acc_cella_27cout;
wire [0:0] wire_acc_cella_28cout;
wire [0:0] wire_acc_cella_29cout;
wire [0:0] wire_acc_cella_30cout;
wire [31:0] wire_acc_cella_dataa;
wire [31:0] wire_acc_cella_datab;
wire [31:0] wire_acc_cella_datac;
wire [31:0] wire_acc_cella_regout;
wire sload;
stratix_lcell acc_cella_0
(
.aclr(aclr),
.cin(1'b0),
.clk(clock),
.cout(wire_acc_cella_0cout[0:0]),
.dataa(wire_acc_cella_dataa[0:0]),
.datab(wire_acc_cella_datab[0:0]),
.datac(wire_acc_cella_datac[0:0]),
.ena(clken),
.regout(wire_acc_cella_regout[0:0]),
.sload(sload));
defparam
acc_cella_0.cin_used = "true",
acc_cella_0.lut_mask = "96e8",
acc_cella_0.operation_mode = "arithmetic",
acc_cella_0.sum_lutc_input = "cin",
acc_cella_0.synch_mode = "on",
acc_cella_0.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_1
(
.aclr(aclr),
.cin(wire_acc_cella_0cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_1cout[0:0]),
.dataa(wire_acc_cella_dataa[1:1]),
.datab(wire_acc_cella_datab[1:1]),
.datac(wire_acc_cella_datac[1:1]),
.ena(clken),
.regout(wire_acc_cella_regout[1:1]),
.sload(sload));
defparam
acc_cella_1.cin_used = "true",
acc_cella_1.lut_mask = "96e8",
acc_cella_1.operation_mode = "arithmetic",
acc_cella_1.sum_lutc_input = "cin",
acc_cella_1.synch_mode = "on",
acc_cella_1.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_2
(
.aclr(aclr),
.cin(wire_acc_cella_1cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_2cout[0:0]),
.dataa(wire_acc_cella_dataa[2:2]),
.datab(wire_acc_cella_datab[2:2]),
.datac(wire_acc_cella_datac[2:2]),
.ena(clken),
.regout(wire_acc_cella_regout[2:2]),
.sload(sload));
defparam
acc_cella_2.cin_used = "true",
acc_cella_2.lut_mask = "96e8",
acc_cella_2.operation_mode = "arithmetic",
acc_cella_2.sum_lutc_input = "cin",
acc_cella_2.synch_mode = "on",
acc_cella_2.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_3
(
.aclr(aclr),
.cin(wire_acc_cella_2cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_3cout[0:0]),
.dataa(wire_acc_cella_dataa[3:3]),
.datab(wire_acc_cella_datab[3:3]),
.datac(wire_acc_cella_datac[3:3]),
.ena(clken),
.regout(wire_acc_cella_regout[3:3]),
.sload(sload));
defparam
acc_cella_3.cin_used = "true",
acc_cella_3.lut_mask = "96e8",
acc_cella_3.operation_mode = "arithmetic",
acc_cella_3.sum_lutc_input = "cin",
acc_cella_3.synch_mode = "on",
acc_cella_3.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_4
(
.aclr(aclr),
.cin(wire_acc_cella_3cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_4cout[0:0]),
.dataa(wire_acc_cella_dataa[4:4]),
.datab(wire_acc_cella_datab[4:4]),
.datac(wire_acc_cella_datac[4:4]),
.ena(clken),
.regout(wire_acc_cella_regout[4:4]),
.sload(sload));
defparam
acc_cella_4.cin_used = "true",
acc_cella_4.lut_mask = "96e8",
acc_cella_4.operation_mode = "arithmetic",
acc_cella_4.sum_lutc_input = "cin",
acc_cella_4.synch_mode = "on",
acc_cella_4.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_5
(
.aclr(aclr),
.cin(wire_acc_cella_4cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_5cout[0:0]),
.dataa(wire_acc_cella_dataa[5:5]),
.datab(wire_acc_cella_datab[5:5]),
.datac(wire_acc_cella_datac[5:5]),
.ena(clken),
.regout(wire_acc_cella_regout[5:5]),
.sload(sload));
defparam
acc_cella_5.cin_used = "true",
acc_cella_5.lut_mask = "96e8",
acc_cella_5.operation_mode = "arithmetic",
acc_cella_5.sum_lutc_input = "cin",
acc_cella_5.synch_mode = "on",
acc_cella_5.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_6
(
.aclr(aclr),
.cin(wire_acc_cella_5cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_6cout[0:0]),
.dataa(wire_acc_cella_dataa[6:6]),
.datab(wire_acc_cella_datab[6:6]),
.datac(wire_acc_cella_datac[6:6]),
.ena(clken),
.regout(wire_acc_cella_regout[6:6]),
.sload(sload));
defparam
acc_cella_6.cin_used = "true",
acc_cella_6.lut_mask = "96e8",
acc_cella_6.operation_mode = "arithmetic",
acc_cella_6.sum_lutc_input = "cin",
acc_cella_6.synch_mode = "on",
acc_cella_6.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_7
(
.aclr(aclr),
.cin(wire_acc_cella_6cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_7cout[0:0]),
.dataa(wire_acc_cella_dataa[7:7]),
.datab(wire_acc_cella_datab[7:7]),
.datac(wire_acc_cella_datac[7:7]),
.ena(clken),
.regout(wire_acc_cella_regout[7:7]),
.sload(sload));
defparam
acc_cella_7.cin_used = "true",
acc_cella_7.lut_mask = "96e8",
acc_cella_7.operation_mode = "arithmetic",
acc_cella_7.sum_lutc_input = "cin",
acc_cella_7.synch_mode = "on",
acc_cella_7.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_8
(
.aclr(aclr),
.cin(wire_acc_cella_7cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_8cout[0:0]),
.dataa(wire_acc_cella_dataa[8:8]),
.datab(wire_acc_cella_datab[8:8]),
.datac(wire_acc_cella_datac[8:8]),
.ena(clken),
.regout(wire_acc_cella_regout[8:8]),
.sload(sload));
defparam
acc_cella_8.cin_used = "true",
acc_cella_8.lut_mask = "96e8",
acc_cella_8.operation_mode = "arithmetic",
acc_cella_8.sum_lutc_input = "cin",
acc_cella_8.synch_mode = "on",
acc_cella_8.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_9
(
.aclr(aclr),
.cin(wire_acc_cella_8cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_9cout[0:0]),
.dataa(wire_acc_cella_dataa[9:9]),
.datab(wire_acc_cella_datab[9:9]),
.datac(wire_acc_cella_datac[9:9]),
.ena(clken),
.regout(wire_acc_cella_regout[9:9]),
.sload(sload));
defparam
acc_cella_9.cin_used = "true",
acc_cella_9.lut_mask = "96e8",
acc_cella_9.operation_mode = "arithmetic",
acc_cella_9.sum_lutc_input = "cin",
acc_cella_9.synch_mode = "on",
acc_cella_9.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_10
(
.aclr(aclr),
.cin(wire_acc_cella_9cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_10cout[0:0]),
.dataa(wire_acc_cella_dataa[10:10]),
.datab(wire_acc_cella_datab[10:10]),
.datac(wire_acc_cella_datac[10:10]),
.ena(clken),
.regout(wire_acc_cella_regout[10:10]),
.sload(sload));
defparam
acc_cella_10.cin_used = "true",
acc_cella_10.lut_mask = "96e8",
acc_cella_10.operation_mode = "arithmetic",
acc_cella_10.sum_lutc_input = "cin",
acc_cella_10.synch_mode = "on",
acc_cella_10.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_11
(
.aclr(aclr),
.cin(wire_acc_cella_10cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_11cout[0:0]),
.dataa(wire_acc_cella_dataa[11:11]),
.datab(wire_acc_cella_datab[11:11]),
.datac(wire_acc_cella_datac[11:11]),
.ena(clken),
.regout(wire_acc_cella_regout[11:11]),
.sload(sload));
defparam
acc_cella_11.cin_used = "true",
acc_cella_11.lut_mask = "96e8",
acc_cella_11.operation_mode = "arithmetic",
acc_cella_11.sum_lutc_input = "cin",
acc_cella_11.synch_mode = "on",
acc_cella_11.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_12
(
.aclr(aclr),
.cin(wire_acc_cella_11cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_12cout[0:0]),
.dataa(wire_acc_cella_dataa[12:12]),
.datab(wire_acc_cella_datab[12:12]),
.datac(wire_acc_cella_datac[12:12]),
.ena(clken),
.regout(wire_acc_cella_regout[12:12]),
.sload(sload));
defparam
acc_cella_12.cin_used = "true",
acc_cella_12.lut_mask = "96e8",
acc_cella_12.operation_mode = "arithmetic",
acc_cella_12.sum_lutc_input = "cin",
acc_cella_12.synch_mode = "on",
acc_cella_12.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_13
(
.aclr(aclr),
.cin(wire_acc_cella_12cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_13cout[0:0]),
.dataa(wire_acc_cella_dataa[13:13]),
.datab(wire_acc_cella_datab[13:13]),
.datac(wire_acc_cella_datac[13:13]),
.ena(clken),
.regout(wire_acc_cella_regout[13:13]),
.sload(sload));
defparam
acc_cella_13.cin_used = "true",
acc_cella_13.lut_mask = "96e8",
acc_cella_13.operation_mode = "arithmetic",
acc_cella_13.sum_lutc_input = "cin",
acc_cella_13.synch_mode = "on",
acc_cella_13.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_14
(
.aclr(aclr),
.cin(wire_acc_cella_13cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_14cout[0:0]),
.dataa(wire_acc_cella_dataa[14:14]),
.datab(wire_acc_cella_datab[14:14]),
.datac(wire_acc_cella_datac[14:14]),
.ena(clken),
.regout(wire_acc_cella_regout[14:14]),
.sload(sload));
defparam
acc_cella_14.cin_used = "true",
acc_cella_14.lut_mask = "96e8",
acc_cella_14.operation_mode = "arithmetic",
acc_cella_14.sum_lutc_input = "cin",
acc_cella_14.synch_mode = "on",
acc_cella_14.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_15
(
.aclr(aclr),
.cin(wire_acc_cella_14cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_15cout[0:0]),
.dataa(wire_acc_cella_dataa[15:15]),
.datab(wire_acc_cella_datab[15:15]),
.datac(wire_acc_cella_datac[15:15]),
.ena(clken),
.regout(wire_acc_cella_regout[15:15]),
.sload(sload));
defparam
acc_cella_15.cin_used = "true",
acc_cella_15.lut_mask = "96e8",
acc_cella_15.operation_mode = "arithmetic",
acc_cella_15.sum_lutc_input = "cin",
acc_cella_15.synch_mode = "on",
acc_cella_15.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_16
(
.aclr(aclr),
.cin(wire_acc_cella_15cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_16cout[0:0]),
.dataa(wire_acc_cella_dataa[16:16]),
.datab(wire_acc_cella_datab[16:16]),
.datac(wire_acc_cella_datac[16:16]),
.ena(clken),
.regout(wire_acc_cella_regout[16:16]),
.sload(sload));
defparam
acc_cella_16.cin_used = "true",
acc_cella_16.lut_mask = "96e8",
acc_cella_16.operation_mode = "arithmetic",
acc_cella_16.sum_lutc_input = "cin",
acc_cella_16.synch_mode = "on",
acc_cella_16.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_17
(
.aclr(aclr),
.cin(wire_acc_cella_16cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_17cout[0:0]),
.dataa(wire_acc_cella_dataa[17:17]),
.datab(wire_acc_cella_datab[17:17]),
.datac(wire_acc_cella_datac[17:17]),
.ena(clken),
.regout(wire_acc_cella_regout[17:17]),
.sload(sload));
defparam
acc_cella_17.cin_used = "true",
acc_cella_17.lut_mask = "96e8",
acc_cella_17.operation_mode = "arithmetic",
acc_cella_17.sum_lutc_input = "cin",
acc_cella_17.synch_mode = "on",
acc_cella_17.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_18
(
.aclr(aclr),
.cin(wire_acc_cella_17cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_18cout[0:0]),
.dataa(wire_acc_cella_dataa[18:18]),
.datab(wire_acc_cella_datab[18:18]),
.datac(wire_acc_cella_datac[18:18]),
.ena(clken),
.regout(wire_acc_cella_regout[18:18]),
.sload(sload));
defparam
acc_cella_18.cin_used = "true",
acc_cella_18.lut_mask = "96e8",
acc_cella_18.operation_mode = "arithmetic",
acc_cella_18.sum_lutc_input = "cin",
acc_cella_18.synch_mode = "on",
acc_cella_18.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_19
(
.aclr(aclr),
.cin(wire_acc_cella_18cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_19cout[0:0]),
.dataa(wire_acc_cella_dataa[19:19]),
.datab(wire_acc_cella_datab[19:19]),
.datac(wire_acc_cella_datac[19:19]),
.ena(clken),
.regout(wire_acc_cella_regout[19:19]),
.sload(sload));
defparam
acc_cella_19.cin_used = "true",
acc_cella_19.lut_mask = "96e8",
acc_cella_19.operation_mode = "arithmetic",
acc_cella_19.sum_lutc_input = "cin",
acc_cella_19.synch_mode = "on",
acc_cella_19.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_20
(
.aclr(aclr),
.cin(wire_acc_cella_19cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_20cout[0:0]),
.dataa(wire_acc_cella_dataa[20:20]),
.datab(wire_acc_cella_datab[20:20]),
.datac(wire_acc_cella_datac[20:20]),
.ena(clken),
.regout(wire_acc_cella_regout[20:20]),
.sload(sload));
defparam
acc_cella_20.cin_used = "true",
acc_cella_20.lut_mask = "96e8",
acc_cella_20.operation_mode = "arithmetic",
acc_cella_20.sum_lutc_input = "cin",
acc_cella_20.synch_mode = "on",
acc_cella_20.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_21
(
.aclr(aclr),
.cin(wire_acc_cella_20cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_21cout[0:0]),
.dataa(wire_acc_cella_dataa[21:21]),
.datab(wire_acc_cella_datab[21:21]),
.datac(wire_acc_cella_datac[21:21]),
.ena(clken),
.regout(wire_acc_cella_regout[21:21]),
.sload(sload));
defparam
acc_cella_21.cin_used = "true",
acc_cella_21.lut_mask = "96e8",
acc_cella_21.operation_mode = "arithmetic",
acc_cella_21.sum_lutc_input = "cin",
acc_cella_21.synch_mode = "on",
acc_cella_21.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_22
(
.aclr(aclr),
.cin(wire_acc_cella_21cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_22cout[0:0]),
.dataa(wire_acc_cella_dataa[22:22]),
.datab(wire_acc_cella_datab[22:22]),
.datac(wire_acc_cella_datac[22:22]),
.ena(clken),
.regout(wire_acc_cella_regout[22:22]),
.sload(sload));
defparam
acc_cella_22.cin_used = "true",
acc_cella_22.lut_mask = "96e8",
acc_cella_22.operation_mode = "arithmetic",
acc_cella_22.sum_lutc_input = "cin",
acc_cella_22.synch_mode = "on",
acc_cella_22.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_23
(
.aclr(aclr),
.cin(wire_acc_cella_22cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_23cout[0:0]),
.dataa(wire_acc_cella_dataa[23:23]),
.datab(wire_acc_cella_datab[23:23]),
.datac(wire_acc_cella_datac[23:23]),
.ena(clken),
.regout(wire_acc_cella_regout[23:23]),
.sload(sload));
defparam
acc_cella_23.cin_used = "true",
acc_cella_23.lut_mask = "96e8",
acc_cella_23.operation_mode = "arithmetic",
acc_cella_23.sum_lutc_input = "cin",
acc_cella_23.synch_mode = "on",
acc_cella_23.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_24
(
.aclr(aclr),
.cin(wire_acc_cella_23cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_24cout[0:0]),
.dataa(wire_acc_cella_dataa[24:24]),
.datab(wire_acc_cella_datab[24:24]),
.datac(wire_acc_cella_datac[24:24]),
.ena(clken),
.regout(wire_acc_cella_regout[24:24]),
.sload(sload));
defparam
acc_cella_24.cin_used = "true",
acc_cella_24.lut_mask = "96e8",
acc_cella_24.operation_mode = "arithmetic",
acc_cella_24.sum_lutc_input = "cin",
acc_cella_24.synch_mode = "on",
acc_cella_24.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_25
(
.aclr(aclr),
.cin(wire_acc_cella_24cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_25cout[0:0]),
.dataa(wire_acc_cella_dataa[25:25]),
.datab(wire_acc_cella_datab[25:25]),
.datac(wire_acc_cella_datac[25:25]),
.ena(clken),
.regout(wire_acc_cella_regout[25:25]),
.sload(sload));
defparam
acc_cella_25.cin_used = "true",
acc_cella_25.lut_mask = "96e8",
acc_cella_25.operation_mode = "arithmetic",
acc_cella_25.sum_lutc_input = "cin",
acc_cella_25.synch_mode = "on",
acc_cella_25.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_26
(
.aclr(aclr),
.cin(wire_acc_cella_25cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_26cout[0:0]),
.dataa(wire_acc_cella_dataa[26:26]),
.datab(wire_acc_cella_datab[26:26]),
.datac(wire_acc_cella_datac[26:26]),
.ena(clken),
.regout(wire_acc_cella_regout[26:26]),
.sload(sload));
defparam
acc_cella_26.cin_used = "true",
acc_cella_26.lut_mask = "96e8",
acc_cella_26.operation_mode = "arithmetic",
acc_cella_26.sum_lutc_input = "cin",
acc_cella_26.synch_mode = "on",
acc_cella_26.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_27
(
.aclr(aclr),
.cin(wire_acc_cella_26cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_27cout[0:0]),
.dataa(wire_acc_cella_dataa[27:27]),
.datab(wire_acc_cella_datab[27:27]),
.datac(wire_acc_cella_datac[27:27]),
.ena(clken),
.regout(wire_acc_cella_regout[27:27]),
.sload(sload));
defparam
acc_cella_27.cin_used = "true",
acc_cella_27.lut_mask = "96e8",
acc_cella_27.operation_mode = "arithmetic",
acc_cella_27.sum_lutc_input = "cin",
acc_cella_27.synch_mode = "on",
acc_cella_27.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_28
(
.aclr(aclr),
.cin(wire_acc_cella_27cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_28cout[0:0]),
.dataa(wire_acc_cella_dataa[28:28]),
.datab(wire_acc_cella_datab[28:28]),
.datac(wire_acc_cella_datac[28:28]),
.ena(clken),
.regout(wire_acc_cella_regout[28:28]),
.sload(sload));
defparam
acc_cella_28.cin_used = "true",
acc_cella_28.lut_mask = "96e8",
acc_cella_28.operation_mode = "arithmetic",
acc_cella_28.sum_lutc_input = "cin",
acc_cella_28.synch_mode = "on",
acc_cella_28.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_29
(
.aclr(aclr),
.cin(wire_acc_cella_28cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_29cout[0:0]),
.dataa(wire_acc_cella_dataa[29:29]),
.datab(wire_acc_cella_datab[29:29]),
.datac(wire_acc_cella_datac[29:29]),
.ena(clken),
.regout(wire_acc_cella_regout[29:29]),
.sload(sload));
defparam
acc_cella_29.cin_used = "true",
acc_cella_29.lut_mask = "96e8",
acc_cella_29.operation_mode = "arithmetic",
acc_cella_29.sum_lutc_input = "cin",
acc_cella_29.synch_mode = "on",
acc_cella_29.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_30
(
.aclr(aclr),
.cin(wire_acc_cella_29cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_30cout[0:0]),
.dataa(wire_acc_cella_dataa[30:30]),
.datab(wire_acc_cella_datab[30:30]),
.datac(wire_acc_cella_datac[30:30]),
.ena(clken),
.regout(wire_acc_cella_regout[30:30]),
.sload(sload));
defparam
acc_cella_30.cin_used = "true",
acc_cella_30.lut_mask = "96e8",
acc_cella_30.operation_mode = "arithmetic",
acc_cella_30.sum_lutc_input = "cin",
acc_cella_30.synch_mode = "on",
acc_cella_30.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_31
(
.aclr(aclr),
.cin(wire_acc_cella_30cout[0:0]),
.clk(clock),
.dataa(wire_acc_cella_dataa[31:31]),
.datab(wire_acc_cella_datab[31:31]),
.datac(wire_acc_cella_datac[31:31]),
.ena(clken),
.regout(wire_acc_cella_regout[31:31]),
.sload(sload));
defparam
acc_cella_31.cin_used = "true",
acc_cella_31.lut_mask = "9696",
acc_cella_31.operation_mode = "normal",
acc_cella_31.sum_lutc_input = "cin",
acc_cella_31.synch_mode = "on",
acc_cella_31.lpm_type = "stratix_lcell";
assign
wire_acc_cella_dataa = data,
wire_acc_cella_datab = wire_acc_cella_regout,
wire_acc_cella_datac = data;
assign
result = wire_acc_cella_regout,
sload = 1'b0;
endmodule
|
module accum32 (
data,
clock,
clken,
aclr,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] data;
input clock;
input clken;
input aclr;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
accum32_accum_nta accum32_accum_nta_component (
.clken (clken),
.aclr (aclr),
.clock (clock),
.data (data),
.result (sub_wire0));
endmodule
|
module accum32_accum_nta
(
aclr,
clken,
clock,
data,
result) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clken;
input clock;
input [31:0] data;
output [31:0] result;
wire [0:0] wire_acc_cella_0cout;
wire [0:0] wire_acc_cella_1cout;
wire [0:0] wire_acc_cella_2cout;
wire [0:0] wire_acc_cella_3cout;
wire [0:0] wire_acc_cella_4cout;
wire [0:0] wire_acc_cella_5cout;
wire [0:0] wire_acc_cella_6cout;
wire [0:0] wire_acc_cella_7cout;
wire [0:0] wire_acc_cella_8cout;
wire [0:0] wire_acc_cella_9cout;
wire [0:0] wire_acc_cella_10cout;
wire [0:0] wire_acc_cella_11cout;
wire [0:0] wire_acc_cella_12cout;
wire [0:0] wire_acc_cella_13cout;
wire [0:0] wire_acc_cella_14cout;
wire [0:0] wire_acc_cella_15cout;
wire [0:0] wire_acc_cella_16cout;
wire [0:0] wire_acc_cella_17cout;
wire [0:0] wire_acc_cella_18cout;
wire [0:0] wire_acc_cella_19cout;
wire [0:0] wire_acc_cella_20cout;
wire [0:0] wire_acc_cella_21cout;
wire [0:0] wire_acc_cella_22cout;
wire [0:0] wire_acc_cella_23cout;
wire [0:0] wire_acc_cella_24cout;
wire [0:0] wire_acc_cella_25cout;
wire [0:0] wire_acc_cella_26cout;
wire [0:0] wire_acc_cella_27cout;
wire [0:0] wire_acc_cella_28cout;
wire [0:0] wire_acc_cella_29cout;
wire [0:0] wire_acc_cella_30cout;
wire [31:0] wire_acc_cella_dataa;
wire [31:0] wire_acc_cella_datab;
wire [31:0] wire_acc_cella_datac;
wire [31:0] wire_acc_cella_regout;
wire sload;
stratix_lcell acc_cella_0
(
.aclr(aclr),
.cin(1'b0),
.clk(clock),
.cout(wire_acc_cella_0cout[0:0]),
.dataa(wire_acc_cella_dataa[0:0]),
.datab(wire_acc_cella_datab[0:0]),
.datac(wire_acc_cella_datac[0:0]),
.ena(clken),
.regout(wire_acc_cella_regout[0:0]),
.sload(sload));
defparam
acc_cella_0.cin_used = "true",
acc_cella_0.lut_mask = "96e8",
acc_cella_0.operation_mode = "arithmetic",
acc_cella_0.sum_lutc_input = "cin",
acc_cella_0.synch_mode = "on",
acc_cella_0.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_1
(
.aclr(aclr),
.cin(wire_acc_cella_0cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_1cout[0:0]),
.dataa(wire_acc_cella_dataa[1:1]),
.datab(wire_acc_cella_datab[1:1]),
.datac(wire_acc_cella_datac[1:1]),
.ena(clken),
.regout(wire_acc_cella_regout[1:1]),
.sload(sload));
defparam
acc_cella_1.cin_used = "true",
acc_cella_1.lut_mask = "96e8",
acc_cella_1.operation_mode = "arithmetic",
acc_cella_1.sum_lutc_input = "cin",
acc_cella_1.synch_mode = "on",
acc_cella_1.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_2
(
.aclr(aclr),
.cin(wire_acc_cella_1cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_2cout[0:0]),
.dataa(wire_acc_cella_dataa[2:2]),
.datab(wire_acc_cella_datab[2:2]),
.datac(wire_acc_cella_datac[2:2]),
.ena(clken),
.regout(wire_acc_cella_regout[2:2]),
.sload(sload));
defparam
acc_cella_2.cin_used = "true",
acc_cella_2.lut_mask = "96e8",
acc_cella_2.operation_mode = "arithmetic",
acc_cella_2.sum_lutc_input = "cin",
acc_cella_2.synch_mode = "on",
acc_cella_2.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_3
(
.aclr(aclr),
.cin(wire_acc_cella_2cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_3cout[0:0]),
.dataa(wire_acc_cella_dataa[3:3]),
.datab(wire_acc_cella_datab[3:3]),
.datac(wire_acc_cella_datac[3:3]),
.ena(clken),
.regout(wire_acc_cella_regout[3:3]),
.sload(sload));
defparam
acc_cella_3.cin_used = "true",
acc_cella_3.lut_mask = "96e8",
acc_cella_3.operation_mode = "arithmetic",
acc_cella_3.sum_lutc_input = "cin",
acc_cella_3.synch_mode = "on",
acc_cella_3.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_4
(
.aclr(aclr),
.cin(wire_acc_cella_3cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_4cout[0:0]),
.dataa(wire_acc_cella_dataa[4:4]),
.datab(wire_acc_cella_datab[4:4]),
.datac(wire_acc_cella_datac[4:4]),
.ena(clken),
.regout(wire_acc_cella_regout[4:4]),
.sload(sload));
defparam
acc_cella_4.cin_used = "true",
acc_cella_4.lut_mask = "96e8",
acc_cella_4.operation_mode = "arithmetic",
acc_cella_4.sum_lutc_input = "cin",
acc_cella_4.synch_mode = "on",
acc_cella_4.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_5
(
.aclr(aclr),
.cin(wire_acc_cella_4cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_5cout[0:0]),
.dataa(wire_acc_cella_dataa[5:5]),
.datab(wire_acc_cella_datab[5:5]),
.datac(wire_acc_cella_datac[5:5]),
.ena(clken),
.regout(wire_acc_cella_regout[5:5]),
.sload(sload));
defparam
acc_cella_5.cin_used = "true",
acc_cella_5.lut_mask = "96e8",
acc_cella_5.operation_mode = "arithmetic",
acc_cella_5.sum_lutc_input = "cin",
acc_cella_5.synch_mode = "on",
acc_cella_5.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_6
(
.aclr(aclr),
.cin(wire_acc_cella_5cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_6cout[0:0]),
.dataa(wire_acc_cella_dataa[6:6]),
.datab(wire_acc_cella_datab[6:6]),
.datac(wire_acc_cella_datac[6:6]),
.ena(clken),
.regout(wire_acc_cella_regout[6:6]),
.sload(sload));
defparam
acc_cella_6.cin_used = "true",
acc_cella_6.lut_mask = "96e8",
acc_cella_6.operation_mode = "arithmetic",
acc_cella_6.sum_lutc_input = "cin",
acc_cella_6.synch_mode = "on",
acc_cella_6.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_7
(
.aclr(aclr),
.cin(wire_acc_cella_6cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_7cout[0:0]),
.dataa(wire_acc_cella_dataa[7:7]),
.datab(wire_acc_cella_datab[7:7]),
.datac(wire_acc_cella_datac[7:7]),
.ena(clken),
.regout(wire_acc_cella_regout[7:7]),
.sload(sload));
defparam
acc_cella_7.cin_used = "true",
acc_cella_7.lut_mask = "96e8",
acc_cella_7.operation_mode = "arithmetic",
acc_cella_7.sum_lutc_input = "cin",
acc_cella_7.synch_mode = "on",
acc_cella_7.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_8
(
.aclr(aclr),
.cin(wire_acc_cella_7cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_8cout[0:0]),
.dataa(wire_acc_cella_dataa[8:8]),
.datab(wire_acc_cella_datab[8:8]),
.datac(wire_acc_cella_datac[8:8]),
.ena(clken),
.regout(wire_acc_cella_regout[8:8]),
.sload(sload));
defparam
acc_cella_8.cin_used = "true",
acc_cella_8.lut_mask = "96e8",
acc_cella_8.operation_mode = "arithmetic",
acc_cella_8.sum_lutc_input = "cin",
acc_cella_8.synch_mode = "on",
acc_cella_8.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_9
(
.aclr(aclr),
.cin(wire_acc_cella_8cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_9cout[0:0]),
.dataa(wire_acc_cella_dataa[9:9]),
.datab(wire_acc_cella_datab[9:9]),
.datac(wire_acc_cella_datac[9:9]),
.ena(clken),
.regout(wire_acc_cella_regout[9:9]),
.sload(sload));
defparam
acc_cella_9.cin_used = "true",
acc_cella_9.lut_mask = "96e8",
acc_cella_9.operation_mode = "arithmetic",
acc_cella_9.sum_lutc_input = "cin",
acc_cella_9.synch_mode = "on",
acc_cella_9.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_10
(
.aclr(aclr),
.cin(wire_acc_cella_9cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_10cout[0:0]),
.dataa(wire_acc_cella_dataa[10:10]),
.datab(wire_acc_cella_datab[10:10]),
.datac(wire_acc_cella_datac[10:10]),
.ena(clken),
.regout(wire_acc_cella_regout[10:10]),
.sload(sload));
defparam
acc_cella_10.cin_used = "true",
acc_cella_10.lut_mask = "96e8",
acc_cella_10.operation_mode = "arithmetic",
acc_cella_10.sum_lutc_input = "cin",
acc_cella_10.synch_mode = "on",
acc_cella_10.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_11
(
.aclr(aclr),
.cin(wire_acc_cella_10cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_11cout[0:0]),
.dataa(wire_acc_cella_dataa[11:11]),
.datab(wire_acc_cella_datab[11:11]),
.datac(wire_acc_cella_datac[11:11]),
.ena(clken),
.regout(wire_acc_cella_regout[11:11]),
.sload(sload));
defparam
acc_cella_11.cin_used = "true",
acc_cella_11.lut_mask = "96e8",
acc_cella_11.operation_mode = "arithmetic",
acc_cella_11.sum_lutc_input = "cin",
acc_cella_11.synch_mode = "on",
acc_cella_11.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_12
(
.aclr(aclr),
.cin(wire_acc_cella_11cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_12cout[0:0]),
.dataa(wire_acc_cella_dataa[12:12]),
.datab(wire_acc_cella_datab[12:12]),
.datac(wire_acc_cella_datac[12:12]),
.ena(clken),
.regout(wire_acc_cella_regout[12:12]),
.sload(sload));
defparam
acc_cella_12.cin_used = "true",
acc_cella_12.lut_mask = "96e8",
acc_cella_12.operation_mode = "arithmetic",
acc_cella_12.sum_lutc_input = "cin",
acc_cella_12.synch_mode = "on",
acc_cella_12.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_13
(
.aclr(aclr),
.cin(wire_acc_cella_12cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_13cout[0:0]),
.dataa(wire_acc_cella_dataa[13:13]),
.datab(wire_acc_cella_datab[13:13]),
.datac(wire_acc_cella_datac[13:13]),
.ena(clken),
.regout(wire_acc_cella_regout[13:13]),
.sload(sload));
defparam
acc_cella_13.cin_used = "true",
acc_cella_13.lut_mask = "96e8",
acc_cella_13.operation_mode = "arithmetic",
acc_cella_13.sum_lutc_input = "cin",
acc_cella_13.synch_mode = "on",
acc_cella_13.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_14
(
.aclr(aclr),
.cin(wire_acc_cella_13cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_14cout[0:0]),
.dataa(wire_acc_cella_dataa[14:14]),
.datab(wire_acc_cella_datab[14:14]),
.datac(wire_acc_cella_datac[14:14]),
.ena(clken),
.regout(wire_acc_cella_regout[14:14]),
.sload(sload));
defparam
acc_cella_14.cin_used = "true",
acc_cella_14.lut_mask = "96e8",
acc_cella_14.operation_mode = "arithmetic",
acc_cella_14.sum_lutc_input = "cin",
acc_cella_14.synch_mode = "on",
acc_cella_14.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_15
(
.aclr(aclr),
.cin(wire_acc_cella_14cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_15cout[0:0]),
.dataa(wire_acc_cella_dataa[15:15]),
.datab(wire_acc_cella_datab[15:15]),
.datac(wire_acc_cella_datac[15:15]),
.ena(clken),
.regout(wire_acc_cella_regout[15:15]),
.sload(sload));
defparam
acc_cella_15.cin_used = "true",
acc_cella_15.lut_mask = "96e8",
acc_cella_15.operation_mode = "arithmetic",
acc_cella_15.sum_lutc_input = "cin",
acc_cella_15.synch_mode = "on",
acc_cella_15.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_16
(
.aclr(aclr),
.cin(wire_acc_cella_15cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_16cout[0:0]),
.dataa(wire_acc_cella_dataa[16:16]),
.datab(wire_acc_cella_datab[16:16]),
.datac(wire_acc_cella_datac[16:16]),
.ena(clken),
.regout(wire_acc_cella_regout[16:16]),
.sload(sload));
defparam
acc_cella_16.cin_used = "true",
acc_cella_16.lut_mask = "96e8",
acc_cella_16.operation_mode = "arithmetic",
acc_cella_16.sum_lutc_input = "cin",
acc_cella_16.synch_mode = "on",
acc_cella_16.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_17
(
.aclr(aclr),
.cin(wire_acc_cella_16cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_17cout[0:0]),
.dataa(wire_acc_cella_dataa[17:17]),
.datab(wire_acc_cella_datab[17:17]),
.datac(wire_acc_cella_datac[17:17]),
.ena(clken),
.regout(wire_acc_cella_regout[17:17]),
.sload(sload));
defparam
acc_cella_17.cin_used = "true",
acc_cella_17.lut_mask = "96e8",
acc_cella_17.operation_mode = "arithmetic",
acc_cella_17.sum_lutc_input = "cin",
acc_cella_17.synch_mode = "on",
acc_cella_17.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_18
(
.aclr(aclr),
.cin(wire_acc_cella_17cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_18cout[0:0]),
.dataa(wire_acc_cella_dataa[18:18]),
.datab(wire_acc_cella_datab[18:18]),
.datac(wire_acc_cella_datac[18:18]),
.ena(clken),
.regout(wire_acc_cella_regout[18:18]),
.sload(sload));
defparam
acc_cella_18.cin_used = "true",
acc_cella_18.lut_mask = "96e8",
acc_cella_18.operation_mode = "arithmetic",
acc_cella_18.sum_lutc_input = "cin",
acc_cella_18.synch_mode = "on",
acc_cella_18.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_19
(
.aclr(aclr),
.cin(wire_acc_cella_18cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_19cout[0:0]),
.dataa(wire_acc_cella_dataa[19:19]),
.datab(wire_acc_cella_datab[19:19]),
.datac(wire_acc_cella_datac[19:19]),
.ena(clken),
.regout(wire_acc_cella_regout[19:19]),
.sload(sload));
defparam
acc_cella_19.cin_used = "true",
acc_cella_19.lut_mask = "96e8",
acc_cella_19.operation_mode = "arithmetic",
acc_cella_19.sum_lutc_input = "cin",
acc_cella_19.synch_mode = "on",
acc_cella_19.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_20
(
.aclr(aclr),
.cin(wire_acc_cella_19cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_20cout[0:0]),
.dataa(wire_acc_cella_dataa[20:20]),
.datab(wire_acc_cella_datab[20:20]),
.datac(wire_acc_cella_datac[20:20]),
.ena(clken),
.regout(wire_acc_cella_regout[20:20]),
.sload(sload));
defparam
acc_cella_20.cin_used = "true",
acc_cella_20.lut_mask = "96e8",
acc_cella_20.operation_mode = "arithmetic",
acc_cella_20.sum_lutc_input = "cin",
acc_cella_20.synch_mode = "on",
acc_cella_20.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_21
(
.aclr(aclr),
.cin(wire_acc_cella_20cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_21cout[0:0]),
.dataa(wire_acc_cella_dataa[21:21]),
.datab(wire_acc_cella_datab[21:21]),
.datac(wire_acc_cella_datac[21:21]),
.ena(clken),
.regout(wire_acc_cella_regout[21:21]),
.sload(sload));
defparam
acc_cella_21.cin_used = "true",
acc_cella_21.lut_mask = "96e8",
acc_cella_21.operation_mode = "arithmetic",
acc_cella_21.sum_lutc_input = "cin",
acc_cella_21.synch_mode = "on",
acc_cella_21.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_22
(
.aclr(aclr),
.cin(wire_acc_cella_21cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_22cout[0:0]),
.dataa(wire_acc_cella_dataa[22:22]),
.datab(wire_acc_cella_datab[22:22]),
.datac(wire_acc_cella_datac[22:22]),
.ena(clken),
.regout(wire_acc_cella_regout[22:22]),
.sload(sload));
defparam
acc_cella_22.cin_used = "true",
acc_cella_22.lut_mask = "96e8",
acc_cella_22.operation_mode = "arithmetic",
acc_cella_22.sum_lutc_input = "cin",
acc_cella_22.synch_mode = "on",
acc_cella_22.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_23
(
.aclr(aclr),
.cin(wire_acc_cella_22cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_23cout[0:0]),
.dataa(wire_acc_cella_dataa[23:23]),
.datab(wire_acc_cella_datab[23:23]),
.datac(wire_acc_cella_datac[23:23]),
.ena(clken),
.regout(wire_acc_cella_regout[23:23]),
.sload(sload));
defparam
acc_cella_23.cin_used = "true",
acc_cella_23.lut_mask = "96e8",
acc_cella_23.operation_mode = "arithmetic",
acc_cella_23.sum_lutc_input = "cin",
acc_cella_23.synch_mode = "on",
acc_cella_23.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_24
(
.aclr(aclr),
.cin(wire_acc_cella_23cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_24cout[0:0]),
.dataa(wire_acc_cella_dataa[24:24]),
.datab(wire_acc_cella_datab[24:24]),
.datac(wire_acc_cella_datac[24:24]),
.ena(clken),
.regout(wire_acc_cella_regout[24:24]),
.sload(sload));
defparam
acc_cella_24.cin_used = "true",
acc_cella_24.lut_mask = "96e8",
acc_cella_24.operation_mode = "arithmetic",
acc_cella_24.sum_lutc_input = "cin",
acc_cella_24.synch_mode = "on",
acc_cella_24.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_25
(
.aclr(aclr),
.cin(wire_acc_cella_24cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_25cout[0:0]),
.dataa(wire_acc_cella_dataa[25:25]),
.datab(wire_acc_cella_datab[25:25]),
.datac(wire_acc_cella_datac[25:25]),
.ena(clken),
.regout(wire_acc_cella_regout[25:25]),
.sload(sload));
defparam
acc_cella_25.cin_used = "true",
acc_cella_25.lut_mask = "96e8",
acc_cella_25.operation_mode = "arithmetic",
acc_cella_25.sum_lutc_input = "cin",
acc_cella_25.synch_mode = "on",
acc_cella_25.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_26
(
.aclr(aclr),
.cin(wire_acc_cella_25cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_26cout[0:0]),
.dataa(wire_acc_cella_dataa[26:26]),
.datab(wire_acc_cella_datab[26:26]),
.datac(wire_acc_cella_datac[26:26]),
.ena(clken),
.regout(wire_acc_cella_regout[26:26]),
.sload(sload));
defparam
acc_cella_26.cin_used = "true",
acc_cella_26.lut_mask = "96e8",
acc_cella_26.operation_mode = "arithmetic",
acc_cella_26.sum_lutc_input = "cin",
acc_cella_26.synch_mode = "on",
acc_cella_26.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_27
(
.aclr(aclr),
.cin(wire_acc_cella_26cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_27cout[0:0]),
.dataa(wire_acc_cella_dataa[27:27]),
.datab(wire_acc_cella_datab[27:27]),
.datac(wire_acc_cella_datac[27:27]),
.ena(clken),
.regout(wire_acc_cella_regout[27:27]),
.sload(sload));
defparam
acc_cella_27.cin_used = "true",
acc_cella_27.lut_mask = "96e8",
acc_cella_27.operation_mode = "arithmetic",
acc_cella_27.sum_lutc_input = "cin",
acc_cella_27.synch_mode = "on",
acc_cella_27.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_28
(
.aclr(aclr),
.cin(wire_acc_cella_27cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_28cout[0:0]),
.dataa(wire_acc_cella_dataa[28:28]),
.datab(wire_acc_cella_datab[28:28]),
.datac(wire_acc_cella_datac[28:28]),
.ena(clken),
.regout(wire_acc_cella_regout[28:28]),
.sload(sload));
defparam
acc_cella_28.cin_used = "true",
acc_cella_28.lut_mask = "96e8",
acc_cella_28.operation_mode = "arithmetic",
acc_cella_28.sum_lutc_input = "cin",
acc_cella_28.synch_mode = "on",
acc_cella_28.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_29
(
.aclr(aclr),
.cin(wire_acc_cella_28cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_29cout[0:0]),
.dataa(wire_acc_cella_dataa[29:29]),
.datab(wire_acc_cella_datab[29:29]),
.datac(wire_acc_cella_datac[29:29]),
.ena(clken),
.regout(wire_acc_cella_regout[29:29]),
.sload(sload));
defparam
acc_cella_29.cin_used = "true",
acc_cella_29.lut_mask = "96e8",
acc_cella_29.operation_mode = "arithmetic",
acc_cella_29.sum_lutc_input = "cin",
acc_cella_29.synch_mode = "on",
acc_cella_29.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_30
(
.aclr(aclr),
.cin(wire_acc_cella_29cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_30cout[0:0]),
.dataa(wire_acc_cella_dataa[30:30]),
.datab(wire_acc_cella_datab[30:30]),
.datac(wire_acc_cella_datac[30:30]),
.ena(clken),
.regout(wire_acc_cella_regout[30:30]),
.sload(sload));
defparam
acc_cella_30.cin_used = "true",
acc_cella_30.lut_mask = "96e8",
acc_cella_30.operation_mode = "arithmetic",
acc_cella_30.sum_lutc_input = "cin",
acc_cella_30.synch_mode = "on",
acc_cella_30.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_31
(
.aclr(aclr),
.cin(wire_acc_cella_30cout[0:0]),
.clk(clock),
.dataa(wire_acc_cella_dataa[31:31]),
.datab(wire_acc_cella_datab[31:31]),
.datac(wire_acc_cella_datac[31:31]),
.ena(clken),
.regout(wire_acc_cella_regout[31:31]),
.sload(sload));
defparam
acc_cella_31.cin_used = "true",
acc_cella_31.lut_mask = "9696",
acc_cella_31.operation_mode = "normal",
acc_cella_31.sum_lutc_input = "cin",
acc_cella_31.synch_mode = "on",
acc_cella_31.lpm_type = "stratix_lcell";
assign
wire_acc_cella_dataa = data,
wire_acc_cella_datab = wire_acc_cella_regout,
wire_acc_cella_datac = data;
assign
result = wire_acc_cella_regout,
sload = 1'b0;
endmodule
|
module accum32 (
data,
clock,
clken,
aclr,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] data;
input clock;
input clken;
input aclr;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
accum32_accum_nta accum32_accum_nta_component (
.clken (clken),
.aclr (aclr),
.clock (clock),
.data (data),
.result (sub_wire0));
endmodule
|
module accum32_accum_nta
(
aclr,
clken,
clock,
data,
result) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clken;
input clock;
input [31:0] data;
output [31:0] result;
wire [0:0] wire_acc_cella_0cout;
wire [0:0] wire_acc_cella_1cout;
wire [0:0] wire_acc_cella_2cout;
wire [0:0] wire_acc_cella_3cout;
wire [0:0] wire_acc_cella_4cout;
wire [0:0] wire_acc_cella_5cout;
wire [0:0] wire_acc_cella_6cout;
wire [0:0] wire_acc_cella_7cout;
wire [0:0] wire_acc_cella_8cout;
wire [0:0] wire_acc_cella_9cout;
wire [0:0] wire_acc_cella_10cout;
wire [0:0] wire_acc_cella_11cout;
wire [0:0] wire_acc_cella_12cout;
wire [0:0] wire_acc_cella_13cout;
wire [0:0] wire_acc_cella_14cout;
wire [0:0] wire_acc_cella_15cout;
wire [0:0] wire_acc_cella_16cout;
wire [0:0] wire_acc_cella_17cout;
wire [0:0] wire_acc_cella_18cout;
wire [0:0] wire_acc_cella_19cout;
wire [0:0] wire_acc_cella_20cout;
wire [0:0] wire_acc_cella_21cout;
wire [0:0] wire_acc_cella_22cout;
wire [0:0] wire_acc_cella_23cout;
wire [0:0] wire_acc_cella_24cout;
wire [0:0] wire_acc_cella_25cout;
wire [0:0] wire_acc_cella_26cout;
wire [0:0] wire_acc_cella_27cout;
wire [0:0] wire_acc_cella_28cout;
wire [0:0] wire_acc_cella_29cout;
wire [0:0] wire_acc_cella_30cout;
wire [31:0] wire_acc_cella_dataa;
wire [31:0] wire_acc_cella_datab;
wire [31:0] wire_acc_cella_datac;
wire [31:0] wire_acc_cella_regout;
wire sload;
stratix_lcell acc_cella_0
(
.aclr(aclr),
.cin(1'b0),
.clk(clock),
.cout(wire_acc_cella_0cout[0:0]),
.dataa(wire_acc_cella_dataa[0:0]),
.datab(wire_acc_cella_datab[0:0]),
.datac(wire_acc_cella_datac[0:0]),
.ena(clken),
.regout(wire_acc_cella_regout[0:0]),
.sload(sload));
defparam
acc_cella_0.cin_used = "true",
acc_cella_0.lut_mask = "96e8",
acc_cella_0.operation_mode = "arithmetic",
acc_cella_0.sum_lutc_input = "cin",
acc_cella_0.synch_mode = "on",
acc_cella_0.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_1
(
.aclr(aclr),
.cin(wire_acc_cella_0cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_1cout[0:0]),
.dataa(wire_acc_cella_dataa[1:1]),
.datab(wire_acc_cella_datab[1:1]),
.datac(wire_acc_cella_datac[1:1]),
.ena(clken),
.regout(wire_acc_cella_regout[1:1]),
.sload(sload));
defparam
acc_cella_1.cin_used = "true",
acc_cella_1.lut_mask = "96e8",
acc_cella_1.operation_mode = "arithmetic",
acc_cella_1.sum_lutc_input = "cin",
acc_cella_1.synch_mode = "on",
acc_cella_1.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_2
(
.aclr(aclr),
.cin(wire_acc_cella_1cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_2cout[0:0]),
.dataa(wire_acc_cella_dataa[2:2]),
.datab(wire_acc_cella_datab[2:2]),
.datac(wire_acc_cella_datac[2:2]),
.ena(clken),
.regout(wire_acc_cella_regout[2:2]),
.sload(sload));
defparam
acc_cella_2.cin_used = "true",
acc_cella_2.lut_mask = "96e8",
acc_cella_2.operation_mode = "arithmetic",
acc_cella_2.sum_lutc_input = "cin",
acc_cella_2.synch_mode = "on",
acc_cella_2.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_3
(
.aclr(aclr),
.cin(wire_acc_cella_2cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_3cout[0:0]),
.dataa(wire_acc_cella_dataa[3:3]),
.datab(wire_acc_cella_datab[3:3]),
.datac(wire_acc_cella_datac[3:3]),
.ena(clken),
.regout(wire_acc_cella_regout[3:3]),
.sload(sload));
defparam
acc_cella_3.cin_used = "true",
acc_cella_3.lut_mask = "96e8",
acc_cella_3.operation_mode = "arithmetic",
acc_cella_3.sum_lutc_input = "cin",
acc_cella_3.synch_mode = "on",
acc_cella_3.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_4
(
.aclr(aclr),
.cin(wire_acc_cella_3cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_4cout[0:0]),
.dataa(wire_acc_cella_dataa[4:4]),
.datab(wire_acc_cella_datab[4:4]),
.datac(wire_acc_cella_datac[4:4]),
.ena(clken),
.regout(wire_acc_cella_regout[4:4]),
.sload(sload));
defparam
acc_cella_4.cin_used = "true",
acc_cella_4.lut_mask = "96e8",
acc_cella_4.operation_mode = "arithmetic",
acc_cella_4.sum_lutc_input = "cin",
acc_cella_4.synch_mode = "on",
acc_cella_4.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_5
(
.aclr(aclr),
.cin(wire_acc_cella_4cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_5cout[0:0]),
.dataa(wire_acc_cella_dataa[5:5]),
.datab(wire_acc_cella_datab[5:5]),
.datac(wire_acc_cella_datac[5:5]),
.ena(clken),
.regout(wire_acc_cella_regout[5:5]),
.sload(sload));
defparam
acc_cella_5.cin_used = "true",
acc_cella_5.lut_mask = "96e8",
acc_cella_5.operation_mode = "arithmetic",
acc_cella_5.sum_lutc_input = "cin",
acc_cella_5.synch_mode = "on",
acc_cella_5.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_6
(
.aclr(aclr),
.cin(wire_acc_cella_5cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_6cout[0:0]),
.dataa(wire_acc_cella_dataa[6:6]),
.datab(wire_acc_cella_datab[6:6]),
.datac(wire_acc_cella_datac[6:6]),
.ena(clken),
.regout(wire_acc_cella_regout[6:6]),
.sload(sload));
defparam
acc_cella_6.cin_used = "true",
acc_cella_6.lut_mask = "96e8",
acc_cella_6.operation_mode = "arithmetic",
acc_cella_6.sum_lutc_input = "cin",
acc_cella_6.synch_mode = "on",
acc_cella_6.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_7
(
.aclr(aclr),
.cin(wire_acc_cella_6cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_7cout[0:0]),
.dataa(wire_acc_cella_dataa[7:7]),
.datab(wire_acc_cella_datab[7:7]),
.datac(wire_acc_cella_datac[7:7]),
.ena(clken),
.regout(wire_acc_cella_regout[7:7]),
.sload(sload));
defparam
acc_cella_7.cin_used = "true",
acc_cella_7.lut_mask = "96e8",
acc_cella_7.operation_mode = "arithmetic",
acc_cella_7.sum_lutc_input = "cin",
acc_cella_7.synch_mode = "on",
acc_cella_7.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_8
(
.aclr(aclr),
.cin(wire_acc_cella_7cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_8cout[0:0]),
.dataa(wire_acc_cella_dataa[8:8]),
.datab(wire_acc_cella_datab[8:8]),
.datac(wire_acc_cella_datac[8:8]),
.ena(clken),
.regout(wire_acc_cella_regout[8:8]),
.sload(sload));
defparam
acc_cella_8.cin_used = "true",
acc_cella_8.lut_mask = "96e8",
acc_cella_8.operation_mode = "arithmetic",
acc_cella_8.sum_lutc_input = "cin",
acc_cella_8.synch_mode = "on",
acc_cella_8.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_9
(
.aclr(aclr),
.cin(wire_acc_cella_8cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_9cout[0:0]),
.dataa(wire_acc_cella_dataa[9:9]),
.datab(wire_acc_cella_datab[9:9]),
.datac(wire_acc_cella_datac[9:9]),
.ena(clken),
.regout(wire_acc_cella_regout[9:9]),
.sload(sload));
defparam
acc_cella_9.cin_used = "true",
acc_cella_9.lut_mask = "96e8",
acc_cella_9.operation_mode = "arithmetic",
acc_cella_9.sum_lutc_input = "cin",
acc_cella_9.synch_mode = "on",
acc_cella_9.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_10
(
.aclr(aclr),
.cin(wire_acc_cella_9cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_10cout[0:0]),
.dataa(wire_acc_cella_dataa[10:10]),
.datab(wire_acc_cella_datab[10:10]),
.datac(wire_acc_cella_datac[10:10]),
.ena(clken),
.regout(wire_acc_cella_regout[10:10]),
.sload(sload));
defparam
acc_cella_10.cin_used = "true",
acc_cella_10.lut_mask = "96e8",
acc_cella_10.operation_mode = "arithmetic",
acc_cella_10.sum_lutc_input = "cin",
acc_cella_10.synch_mode = "on",
acc_cella_10.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_11
(
.aclr(aclr),
.cin(wire_acc_cella_10cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_11cout[0:0]),
.dataa(wire_acc_cella_dataa[11:11]),
.datab(wire_acc_cella_datab[11:11]),
.datac(wire_acc_cella_datac[11:11]),
.ena(clken),
.regout(wire_acc_cella_regout[11:11]),
.sload(sload));
defparam
acc_cella_11.cin_used = "true",
acc_cella_11.lut_mask = "96e8",
acc_cella_11.operation_mode = "arithmetic",
acc_cella_11.sum_lutc_input = "cin",
acc_cella_11.synch_mode = "on",
acc_cella_11.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_12
(
.aclr(aclr),
.cin(wire_acc_cella_11cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_12cout[0:0]),
.dataa(wire_acc_cella_dataa[12:12]),
.datab(wire_acc_cella_datab[12:12]),
.datac(wire_acc_cella_datac[12:12]),
.ena(clken),
.regout(wire_acc_cella_regout[12:12]),
.sload(sload));
defparam
acc_cella_12.cin_used = "true",
acc_cella_12.lut_mask = "96e8",
acc_cella_12.operation_mode = "arithmetic",
acc_cella_12.sum_lutc_input = "cin",
acc_cella_12.synch_mode = "on",
acc_cella_12.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_13
(
.aclr(aclr),
.cin(wire_acc_cella_12cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_13cout[0:0]),
.dataa(wire_acc_cella_dataa[13:13]),
.datab(wire_acc_cella_datab[13:13]),
.datac(wire_acc_cella_datac[13:13]),
.ena(clken),
.regout(wire_acc_cella_regout[13:13]),
.sload(sload));
defparam
acc_cella_13.cin_used = "true",
acc_cella_13.lut_mask = "96e8",
acc_cella_13.operation_mode = "arithmetic",
acc_cella_13.sum_lutc_input = "cin",
acc_cella_13.synch_mode = "on",
acc_cella_13.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_14
(
.aclr(aclr),
.cin(wire_acc_cella_13cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_14cout[0:0]),
.dataa(wire_acc_cella_dataa[14:14]),
.datab(wire_acc_cella_datab[14:14]),
.datac(wire_acc_cella_datac[14:14]),
.ena(clken),
.regout(wire_acc_cella_regout[14:14]),
.sload(sload));
defparam
acc_cella_14.cin_used = "true",
acc_cella_14.lut_mask = "96e8",
acc_cella_14.operation_mode = "arithmetic",
acc_cella_14.sum_lutc_input = "cin",
acc_cella_14.synch_mode = "on",
acc_cella_14.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_15
(
.aclr(aclr),
.cin(wire_acc_cella_14cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_15cout[0:0]),
.dataa(wire_acc_cella_dataa[15:15]),
.datab(wire_acc_cella_datab[15:15]),
.datac(wire_acc_cella_datac[15:15]),
.ena(clken),
.regout(wire_acc_cella_regout[15:15]),
.sload(sload));
defparam
acc_cella_15.cin_used = "true",
acc_cella_15.lut_mask = "96e8",
acc_cella_15.operation_mode = "arithmetic",
acc_cella_15.sum_lutc_input = "cin",
acc_cella_15.synch_mode = "on",
acc_cella_15.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_16
(
.aclr(aclr),
.cin(wire_acc_cella_15cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_16cout[0:0]),
.dataa(wire_acc_cella_dataa[16:16]),
.datab(wire_acc_cella_datab[16:16]),
.datac(wire_acc_cella_datac[16:16]),
.ena(clken),
.regout(wire_acc_cella_regout[16:16]),
.sload(sload));
defparam
acc_cella_16.cin_used = "true",
acc_cella_16.lut_mask = "96e8",
acc_cella_16.operation_mode = "arithmetic",
acc_cella_16.sum_lutc_input = "cin",
acc_cella_16.synch_mode = "on",
acc_cella_16.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_17
(
.aclr(aclr),
.cin(wire_acc_cella_16cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_17cout[0:0]),
.dataa(wire_acc_cella_dataa[17:17]),
.datab(wire_acc_cella_datab[17:17]),
.datac(wire_acc_cella_datac[17:17]),
.ena(clken),
.regout(wire_acc_cella_regout[17:17]),
.sload(sload));
defparam
acc_cella_17.cin_used = "true",
acc_cella_17.lut_mask = "96e8",
acc_cella_17.operation_mode = "arithmetic",
acc_cella_17.sum_lutc_input = "cin",
acc_cella_17.synch_mode = "on",
acc_cella_17.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_18
(
.aclr(aclr),
.cin(wire_acc_cella_17cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_18cout[0:0]),
.dataa(wire_acc_cella_dataa[18:18]),
.datab(wire_acc_cella_datab[18:18]),
.datac(wire_acc_cella_datac[18:18]),
.ena(clken),
.regout(wire_acc_cella_regout[18:18]),
.sload(sload));
defparam
acc_cella_18.cin_used = "true",
acc_cella_18.lut_mask = "96e8",
acc_cella_18.operation_mode = "arithmetic",
acc_cella_18.sum_lutc_input = "cin",
acc_cella_18.synch_mode = "on",
acc_cella_18.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_19
(
.aclr(aclr),
.cin(wire_acc_cella_18cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_19cout[0:0]),
.dataa(wire_acc_cella_dataa[19:19]),
.datab(wire_acc_cella_datab[19:19]),
.datac(wire_acc_cella_datac[19:19]),
.ena(clken),
.regout(wire_acc_cella_regout[19:19]),
.sload(sload));
defparam
acc_cella_19.cin_used = "true",
acc_cella_19.lut_mask = "96e8",
acc_cella_19.operation_mode = "arithmetic",
acc_cella_19.sum_lutc_input = "cin",
acc_cella_19.synch_mode = "on",
acc_cella_19.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_20
(
.aclr(aclr),
.cin(wire_acc_cella_19cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_20cout[0:0]),
.dataa(wire_acc_cella_dataa[20:20]),
.datab(wire_acc_cella_datab[20:20]),
.datac(wire_acc_cella_datac[20:20]),
.ena(clken),
.regout(wire_acc_cella_regout[20:20]),
.sload(sload));
defparam
acc_cella_20.cin_used = "true",
acc_cella_20.lut_mask = "96e8",
acc_cella_20.operation_mode = "arithmetic",
acc_cella_20.sum_lutc_input = "cin",
acc_cella_20.synch_mode = "on",
acc_cella_20.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_21
(
.aclr(aclr),
.cin(wire_acc_cella_20cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_21cout[0:0]),
.dataa(wire_acc_cella_dataa[21:21]),
.datab(wire_acc_cella_datab[21:21]),
.datac(wire_acc_cella_datac[21:21]),
.ena(clken),
.regout(wire_acc_cella_regout[21:21]),
.sload(sload));
defparam
acc_cella_21.cin_used = "true",
acc_cella_21.lut_mask = "96e8",
acc_cella_21.operation_mode = "arithmetic",
acc_cella_21.sum_lutc_input = "cin",
acc_cella_21.synch_mode = "on",
acc_cella_21.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_22
(
.aclr(aclr),
.cin(wire_acc_cella_21cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_22cout[0:0]),
.dataa(wire_acc_cella_dataa[22:22]),
.datab(wire_acc_cella_datab[22:22]),
.datac(wire_acc_cella_datac[22:22]),
.ena(clken),
.regout(wire_acc_cella_regout[22:22]),
.sload(sload));
defparam
acc_cella_22.cin_used = "true",
acc_cella_22.lut_mask = "96e8",
acc_cella_22.operation_mode = "arithmetic",
acc_cella_22.sum_lutc_input = "cin",
acc_cella_22.synch_mode = "on",
acc_cella_22.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_23
(
.aclr(aclr),
.cin(wire_acc_cella_22cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_23cout[0:0]),
.dataa(wire_acc_cella_dataa[23:23]),
.datab(wire_acc_cella_datab[23:23]),
.datac(wire_acc_cella_datac[23:23]),
.ena(clken),
.regout(wire_acc_cella_regout[23:23]),
.sload(sload));
defparam
acc_cella_23.cin_used = "true",
acc_cella_23.lut_mask = "96e8",
acc_cella_23.operation_mode = "arithmetic",
acc_cella_23.sum_lutc_input = "cin",
acc_cella_23.synch_mode = "on",
acc_cella_23.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_24
(
.aclr(aclr),
.cin(wire_acc_cella_23cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_24cout[0:0]),
.dataa(wire_acc_cella_dataa[24:24]),
.datab(wire_acc_cella_datab[24:24]),
.datac(wire_acc_cella_datac[24:24]),
.ena(clken),
.regout(wire_acc_cella_regout[24:24]),
.sload(sload));
defparam
acc_cella_24.cin_used = "true",
acc_cella_24.lut_mask = "96e8",
acc_cella_24.operation_mode = "arithmetic",
acc_cella_24.sum_lutc_input = "cin",
acc_cella_24.synch_mode = "on",
acc_cella_24.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_25
(
.aclr(aclr),
.cin(wire_acc_cella_24cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_25cout[0:0]),
.dataa(wire_acc_cella_dataa[25:25]),
.datab(wire_acc_cella_datab[25:25]),
.datac(wire_acc_cella_datac[25:25]),
.ena(clken),
.regout(wire_acc_cella_regout[25:25]),
.sload(sload));
defparam
acc_cella_25.cin_used = "true",
acc_cella_25.lut_mask = "96e8",
acc_cella_25.operation_mode = "arithmetic",
acc_cella_25.sum_lutc_input = "cin",
acc_cella_25.synch_mode = "on",
acc_cella_25.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_26
(
.aclr(aclr),
.cin(wire_acc_cella_25cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_26cout[0:0]),
.dataa(wire_acc_cella_dataa[26:26]),
.datab(wire_acc_cella_datab[26:26]),
.datac(wire_acc_cella_datac[26:26]),
.ena(clken),
.regout(wire_acc_cella_regout[26:26]),
.sload(sload));
defparam
acc_cella_26.cin_used = "true",
acc_cella_26.lut_mask = "96e8",
acc_cella_26.operation_mode = "arithmetic",
acc_cella_26.sum_lutc_input = "cin",
acc_cella_26.synch_mode = "on",
acc_cella_26.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_27
(
.aclr(aclr),
.cin(wire_acc_cella_26cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_27cout[0:0]),
.dataa(wire_acc_cella_dataa[27:27]),
.datab(wire_acc_cella_datab[27:27]),
.datac(wire_acc_cella_datac[27:27]),
.ena(clken),
.regout(wire_acc_cella_regout[27:27]),
.sload(sload));
defparam
acc_cella_27.cin_used = "true",
acc_cella_27.lut_mask = "96e8",
acc_cella_27.operation_mode = "arithmetic",
acc_cella_27.sum_lutc_input = "cin",
acc_cella_27.synch_mode = "on",
acc_cella_27.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_28
(
.aclr(aclr),
.cin(wire_acc_cella_27cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_28cout[0:0]),
.dataa(wire_acc_cella_dataa[28:28]),
.datab(wire_acc_cella_datab[28:28]),
.datac(wire_acc_cella_datac[28:28]),
.ena(clken),
.regout(wire_acc_cella_regout[28:28]),
.sload(sload));
defparam
acc_cella_28.cin_used = "true",
acc_cella_28.lut_mask = "96e8",
acc_cella_28.operation_mode = "arithmetic",
acc_cella_28.sum_lutc_input = "cin",
acc_cella_28.synch_mode = "on",
acc_cella_28.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_29
(
.aclr(aclr),
.cin(wire_acc_cella_28cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_29cout[0:0]),
.dataa(wire_acc_cella_dataa[29:29]),
.datab(wire_acc_cella_datab[29:29]),
.datac(wire_acc_cella_datac[29:29]),
.ena(clken),
.regout(wire_acc_cella_regout[29:29]),
.sload(sload));
defparam
acc_cella_29.cin_used = "true",
acc_cella_29.lut_mask = "96e8",
acc_cella_29.operation_mode = "arithmetic",
acc_cella_29.sum_lutc_input = "cin",
acc_cella_29.synch_mode = "on",
acc_cella_29.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_30
(
.aclr(aclr),
.cin(wire_acc_cella_29cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_30cout[0:0]),
.dataa(wire_acc_cella_dataa[30:30]),
.datab(wire_acc_cella_datab[30:30]),
.datac(wire_acc_cella_datac[30:30]),
.ena(clken),
.regout(wire_acc_cella_regout[30:30]),
.sload(sload));
defparam
acc_cella_30.cin_used = "true",
acc_cella_30.lut_mask = "96e8",
acc_cella_30.operation_mode = "arithmetic",
acc_cella_30.sum_lutc_input = "cin",
acc_cella_30.synch_mode = "on",
acc_cella_30.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_31
(
.aclr(aclr),
.cin(wire_acc_cella_30cout[0:0]),
.clk(clock),
.dataa(wire_acc_cella_dataa[31:31]),
.datab(wire_acc_cella_datab[31:31]),
.datac(wire_acc_cella_datac[31:31]),
.ena(clken),
.regout(wire_acc_cella_regout[31:31]),
.sload(sload));
defparam
acc_cella_31.cin_used = "true",
acc_cella_31.lut_mask = "9696",
acc_cella_31.operation_mode = "normal",
acc_cella_31.sum_lutc_input = "cin",
acc_cella_31.synch_mode = "on",
acc_cella_31.lpm_type = "stratix_lcell";
assign
wire_acc_cella_dataa = data,
wire_acc_cella_datab = wire_acc_cella_regout,
wire_acc_cella_datac = data;
assign
result = wire_acc_cella_regout,
sload = 1'b0;
endmodule
|
module accum32 (
data,
clock,
clken,
aclr,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] data;
input clock;
input clken;
input aclr;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
accum32_accum_nta accum32_accum_nta_component (
.clken (clken),
.aclr (aclr),
.clock (clock),
.data (data),
.result (sub_wire0));
endmodule
|
module accum32_accum_nta
(
aclr,
clken,
clock,
data,
result) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clken;
input clock;
input [31:0] data;
output [31:0] result;
wire [0:0] wire_acc_cella_0cout;
wire [0:0] wire_acc_cella_1cout;
wire [0:0] wire_acc_cella_2cout;
wire [0:0] wire_acc_cella_3cout;
wire [0:0] wire_acc_cella_4cout;
wire [0:0] wire_acc_cella_5cout;
wire [0:0] wire_acc_cella_6cout;
wire [0:0] wire_acc_cella_7cout;
wire [0:0] wire_acc_cella_8cout;
wire [0:0] wire_acc_cella_9cout;
wire [0:0] wire_acc_cella_10cout;
wire [0:0] wire_acc_cella_11cout;
wire [0:0] wire_acc_cella_12cout;
wire [0:0] wire_acc_cella_13cout;
wire [0:0] wire_acc_cella_14cout;
wire [0:0] wire_acc_cella_15cout;
wire [0:0] wire_acc_cella_16cout;
wire [0:0] wire_acc_cella_17cout;
wire [0:0] wire_acc_cella_18cout;
wire [0:0] wire_acc_cella_19cout;
wire [0:0] wire_acc_cella_20cout;
wire [0:0] wire_acc_cella_21cout;
wire [0:0] wire_acc_cella_22cout;
wire [0:0] wire_acc_cella_23cout;
wire [0:0] wire_acc_cella_24cout;
wire [0:0] wire_acc_cella_25cout;
wire [0:0] wire_acc_cella_26cout;
wire [0:0] wire_acc_cella_27cout;
wire [0:0] wire_acc_cella_28cout;
wire [0:0] wire_acc_cella_29cout;
wire [0:0] wire_acc_cella_30cout;
wire [31:0] wire_acc_cella_dataa;
wire [31:0] wire_acc_cella_datab;
wire [31:0] wire_acc_cella_datac;
wire [31:0] wire_acc_cella_regout;
wire sload;
stratix_lcell acc_cella_0
(
.aclr(aclr),
.cin(1'b0),
.clk(clock),
.cout(wire_acc_cella_0cout[0:0]),
.dataa(wire_acc_cella_dataa[0:0]),
.datab(wire_acc_cella_datab[0:0]),
.datac(wire_acc_cella_datac[0:0]),
.ena(clken),
.regout(wire_acc_cella_regout[0:0]),
.sload(sload));
defparam
acc_cella_0.cin_used = "true",
acc_cella_0.lut_mask = "96e8",
acc_cella_0.operation_mode = "arithmetic",
acc_cella_0.sum_lutc_input = "cin",
acc_cella_0.synch_mode = "on",
acc_cella_0.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_1
(
.aclr(aclr),
.cin(wire_acc_cella_0cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_1cout[0:0]),
.dataa(wire_acc_cella_dataa[1:1]),
.datab(wire_acc_cella_datab[1:1]),
.datac(wire_acc_cella_datac[1:1]),
.ena(clken),
.regout(wire_acc_cella_regout[1:1]),
.sload(sload));
defparam
acc_cella_1.cin_used = "true",
acc_cella_1.lut_mask = "96e8",
acc_cella_1.operation_mode = "arithmetic",
acc_cella_1.sum_lutc_input = "cin",
acc_cella_1.synch_mode = "on",
acc_cella_1.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_2
(
.aclr(aclr),
.cin(wire_acc_cella_1cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_2cout[0:0]),
.dataa(wire_acc_cella_dataa[2:2]),
.datab(wire_acc_cella_datab[2:2]),
.datac(wire_acc_cella_datac[2:2]),
.ena(clken),
.regout(wire_acc_cella_regout[2:2]),
.sload(sload));
defparam
acc_cella_2.cin_used = "true",
acc_cella_2.lut_mask = "96e8",
acc_cella_2.operation_mode = "arithmetic",
acc_cella_2.sum_lutc_input = "cin",
acc_cella_2.synch_mode = "on",
acc_cella_2.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_3
(
.aclr(aclr),
.cin(wire_acc_cella_2cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_3cout[0:0]),
.dataa(wire_acc_cella_dataa[3:3]),
.datab(wire_acc_cella_datab[3:3]),
.datac(wire_acc_cella_datac[3:3]),
.ena(clken),
.regout(wire_acc_cella_regout[3:3]),
.sload(sload));
defparam
acc_cella_3.cin_used = "true",
acc_cella_3.lut_mask = "96e8",
acc_cella_3.operation_mode = "arithmetic",
acc_cella_3.sum_lutc_input = "cin",
acc_cella_3.synch_mode = "on",
acc_cella_3.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_4
(
.aclr(aclr),
.cin(wire_acc_cella_3cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_4cout[0:0]),
.dataa(wire_acc_cella_dataa[4:4]),
.datab(wire_acc_cella_datab[4:4]),
.datac(wire_acc_cella_datac[4:4]),
.ena(clken),
.regout(wire_acc_cella_regout[4:4]),
.sload(sload));
defparam
acc_cella_4.cin_used = "true",
acc_cella_4.lut_mask = "96e8",
acc_cella_4.operation_mode = "arithmetic",
acc_cella_4.sum_lutc_input = "cin",
acc_cella_4.synch_mode = "on",
acc_cella_4.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_5
(
.aclr(aclr),
.cin(wire_acc_cella_4cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_5cout[0:0]),
.dataa(wire_acc_cella_dataa[5:5]),
.datab(wire_acc_cella_datab[5:5]),
.datac(wire_acc_cella_datac[5:5]),
.ena(clken),
.regout(wire_acc_cella_regout[5:5]),
.sload(sload));
defparam
acc_cella_5.cin_used = "true",
acc_cella_5.lut_mask = "96e8",
acc_cella_5.operation_mode = "arithmetic",
acc_cella_5.sum_lutc_input = "cin",
acc_cella_5.synch_mode = "on",
acc_cella_5.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_6
(
.aclr(aclr),
.cin(wire_acc_cella_5cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_6cout[0:0]),
.dataa(wire_acc_cella_dataa[6:6]),
.datab(wire_acc_cella_datab[6:6]),
.datac(wire_acc_cella_datac[6:6]),
.ena(clken),
.regout(wire_acc_cella_regout[6:6]),
.sload(sload));
defparam
acc_cella_6.cin_used = "true",
acc_cella_6.lut_mask = "96e8",
acc_cella_6.operation_mode = "arithmetic",
acc_cella_6.sum_lutc_input = "cin",
acc_cella_6.synch_mode = "on",
acc_cella_6.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_7
(
.aclr(aclr),
.cin(wire_acc_cella_6cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_7cout[0:0]),
.dataa(wire_acc_cella_dataa[7:7]),
.datab(wire_acc_cella_datab[7:7]),
.datac(wire_acc_cella_datac[7:7]),
.ena(clken),
.regout(wire_acc_cella_regout[7:7]),
.sload(sload));
defparam
acc_cella_7.cin_used = "true",
acc_cella_7.lut_mask = "96e8",
acc_cella_7.operation_mode = "arithmetic",
acc_cella_7.sum_lutc_input = "cin",
acc_cella_7.synch_mode = "on",
acc_cella_7.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_8
(
.aclr(aclr),
.cin(wire_acc_cella_7cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_8cout[0:0]),
.dataa(wire_acc_cella_dataa[8:8]),
.datab(wire_acc_cella_datab[8:8]),
.datac(wire_acc_cella_datac[8:8]),
.ena(clken),
.regout(wire_acc_cella_regout[8:8]),
.sload(sload));
defparam
acc_cella_8.cin_used = "true",
acc_cella_8.lut_mask = "96e8",
acc_cella_8.operation_mode = "arithmetic",
acc_cella_8.sum_lutc_input = "cin",
acc_cella_8.synch_mode = "on",
acc_cella_8.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_9
(
.aclr(aclr),
.cin(wire_acc_cella_8cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_9cout[0:0]),
.dataa(wire_acc_cella_dataa[9:9]),
.datab(wire_acc_cella_datab[9:9]),
.datac(wire_acc_cella_datac[9:9]),
.ena(clken),
.regout(wire_acc_cella_regout[9:9]),
.sload(sload));
defparam
acc_cella_9.cin_used = "true",
acc_cella_9.lut_mask = "96e8",
acc_cella_9.operation_mode = "arithmetic",
acc_cella_9.sum_lutc_input = "cin",
acc_cella_9.synch_mode = "on",
acc_cella_9.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_10
(
.aclr(aclr),
.cin(wire_acc_cella_9cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_10cout[0:0]),
.dataa(wire_acc_cella_dataa[10:10]),
.datab(wire_acc_cella_datab[10:10]),
.datac(wire_acc_cella_datac[10:10]),
.ena(clken),
.regout(wire_acc_cella_regout[10:10]),
.sload(sload));
defparam
acc_cella_10.cin_used = "true",
acc_cella_10.lut_mask = "96e8",
acc_cella_10.operation_mode = "arithmetic",
acc_cella_10.sum_lutc_input = "cin",
acc_cella_10.synch_mode = "on",
acc_cella_10.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_11
(
.aclr(aclr),
.cin(wire_acc_cella_10cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_11cout[0:0]),
.dataa(wire_acc_cella_dataa[11:11]),
.datab(wire_acc_cella_datab[11:11]),
.datac(wire_acc_cella_datac[11:11]),
.ena(clken),
.regout(wire_acc_cella_regout[11:11]),
.sload(sload));
defparam
acc_cella_11.cin_used = "true",
acc_cella_11.lut_mask = "96e8",
acc_cella_11.operation_mode = "arithmetic",
acc_cella_11.sum_lutc_input = "cin",
acc_cella_11.synch_mode = "on",
acc_cella_11.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_12
(
.aclr(aclr),
.cin(wire_acc_cella_11cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_12cout[0:0]),
.dataa(wire_acc_cella_dataa[12:12]),
.datab(wire_acc_cella_datab[12:12]),
.datac(wire_acc_cella_datac[12:12]),
.ena(clken),
.regout(wire_acc_cella_regout[12:12]),
.sload(sload));
defparam
acc_cella_12.cin_used = "true",
acc_cella_12.lut_mask = "96e8",
acc_cella_12.operation_mode = "arithmetic",
acc_cella_12.sum_lutc_input = "cin",
acc_cella_12.synch_mode = "on",
acc_cella_12.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_13
(
.aclr(aclr),
.cin(wire_acc_cella_12cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_13cout[0:0]),
.dataa(wire_acc_cella_dataa[13:13]),
.datab(wire_acc_cella_datab[13:13]),
.datac(wire_acc_cella_datac[13:13]),
.ena(clken),
.regout(wire_acc_cella_regout[13:13]),
.sload(sload));
defparam
acc_cella_13.cin_used = "true",
acc_cella_13.lut_mask = "96e8",
acc_cella_13.operation_mode = "arithmetic",
acc_cella_13.sum_lutc_input = "cin",
acc_cella_13.synch_mode = "on",
acc_cella_13.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_14
(
.aclr(aclr),
.cin(wire_acc_cella_13cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_14cout[0:0]),
.dataa(wire_acc_cella_dataa[14:14]),
.datab(wire_acc_cella_datab[14:14]),
.datac(wire_acc_cella_datac[14:14]),
.ena(clken),
.regout(wire_acc_cella_regout[14:14]),
.sload(sload));
defparam
acc_cella_14.cin_used = "true",
acc_cella_14.lut_mask = "96e8",
acc_cella_14.operation_mode = "arithmetic",
acc_cella_14.sum_lutc_input = "cin",
acc_cella_14.synch_mode = "on",
acc_cella_14.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_15
(
.aclr(aclr),
.cin(wire_acc_cella_14cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_15cout[0:0]),
.dataa(wire_acc_cella_dataa[15:15]),
.datab(wire_acc_cella_datab[15:15]),
.datac(wire_acc_cella_datac[15:15]),
.ena(clken),
.regout(wire_acc_cella_regout[15:15]),
.sload(sload));
defparam
acc_cella_15.cin_used = "true",
acc_cella_15.lut_mask = "96e8",
acc_cella_15.operation_mode = "arithmetic",
acc_cella_15.sum_lutc_input = "cin",
acc_cella_15.synch_mode = "on",
acc_cella_15.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_16
(
.aclr(aclr),
.cin(wire_acc_cella_15cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_16cout[0:0]),
.dataa(wire_acc_cella_dataa[16:16]),
.datab(wire_acc_cella_datab[16:16]),
.datac(wire_acc_cella_datac[16:16]),
.ena(clken),
.regout(wire_acc_cella_regout[16:16]),
.sload(sload));
defparam
acc_cella_16.cin_used = "true",
acc_cella_16.lut_mask = "96e8",
acc_cella_16.operation_mode = "arithmetic",
acc_cella_16.sum_lutc_input = "cin",
acc_cella_16.synch_mode = "on",
acc_cella_16.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_17
(
.aclr(aclr),
.cin(wire_acc_cella_16cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_17cout[0:0]),
.dataa(wire_acc_cella_dataa[17:17]),
.datab(wire_acc_cella_datab[17:17]),
.datac(wire_acc_cella_datac[17:17]),
.ena(clken),
.regout(wire_acc_cella_regout[17:17]),
.sload(sload));
defparam
acc_cella_17.cin_used = "true",
acc_cella_17.lut_mask = "96e8",
acc_cella_17.operation_mode = "arithmetic",
acc_cella_17.sum_lutc_input = "cin",
acc_cella_17.synch_mode = "on",
acc_cella_17.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_18
(
.aclr(aclr),
.cin(wire_acc_cella_17cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_18cout[0:0]),
.dataa(wire_acc_cella_dataa[18:18]),
.datab(wire_acc_cella_datab[18:18]),
.datac(wire_acc_cella_datac[18:18]),
.ena(clken),
.regout(wire_acc_cella_regout[18:18]),
.sload(sload));
defparam
acc_cella_18.cin_used = "true",
acc_cella_18.lut_mask = "96e8",
acc_cella_18.operation_mode = "arithmetic",
acc_cella_18.sum_lutc_input = "cin",
acc_cella_18.synch_mode = "on",
acc_cella_18.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_19
(
.aclr(aclr),
.cin(wire_acc_cella_18cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_19cout[0:0]),
.dataa(wire_acc_cella_dataa[19:19]),
.datab(wire_acc_cella_datab[19:19]),
.datac(wire_acc_cella_datac[19:19]),
.ena(clken),
.regout(wire_acc_cella_regout[19:19]),
.sload(sload));
defparam
acc_cella_19.cin_used = "true",
acc_cella_19.lut_mask = "96e8",
acc_cella_19.operation_mode = "arithmetic",
acc_cella_19.sum_lutc_input = "cin",
acc_cella_19.synch_mode = "on",
acc_cella_19.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_20
(
.aclr(aclr),
.cin(wire_acc_cella_19cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_20cout[0:0]),
.dataa(wire_acc_cella_dataa[20:20]),
.datab(wire_acc_cella_datab[20:20]),
.datac(wire_acc_cella_datac[20:20]),
.ena(clken),
.regout(wire_acc_cella_regout[20:20]),
.sload(sload));
defparam
acc_cella_20.cin_used = "true",
acc_cella_20.lut_mask = "96e8",
acc_cella_20.operation_mode = "arithmetic",
acc_cella_20.sum_lutc_input = "cin",
acc_cella_20.synch_mode = "on",
acc_cella_20.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_21
(
.aclr(aclr),
.cin(wire_acc_cella_20cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_21cout[0:0]),
.dataa(wire_acc_cella_dataa[21:21]),
.datab(wire_acc_cella_datab[21:21]),
.datac(wire_acc_cella_datac[21:21]),
.ena(clken),
.regout(wire_acc_cella_regout[21:21]),
.sload(sload));
defparam
acc_cella_21.cin_used = "true",
acc_cella_21.lut_mask = "96e8",
acc_cella_21.operation_mode = "arithmetic",
acc_cella_21.sum_lutc_input = "cin",
acc_cella_21.synch_mode = "on",
acc_cella_21.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_22
(
.aclr(aclr),
.cin(wire_acc_cella_21cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_22cout[0:0]),
.dataa(wire_acc_cella_dataa[22:22]),
.datab(wire_acc_cella_datab[22:22]),
.datac(wire_acc_cella_datac[22:22]),
.ena(clken),
.regout(wire_acc_cella_regout[22:22]),
.sload(sload));
defparam
acc_cella_22.cin_used = "true",
acc_cella_22.lut_mask = "96e8",
acc_cella_22.operation_mode = "arithmetic",
acc_cella_22.sum_lutc_input = "cin",
acc_cella_22.synch_mode = "on",
acc_cella_22.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_23
(
.aclr(aclr),
.cin(wire_acc_cella_22cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_23cout[0:0]),
.dataa(wire_acc_cella_dataa[23:23]),
.datab(wire_acc_cella_datab[23:23]),
.datac(wire_acc_cella_datac[23:23]),
.ena(clken),
.regout(wire_acc_cella_regout[23:23]),
.sload(sload));
defparam
acc_cella_23.cin_used = "true",
acc_cella_23.lut_mask = "96e8",
acc_cella_23.operation_mode = "arithmetic",
acc_cella_23.sum_lutc_input = "cin",
acc_cella_23.synch_mode = "on",
acc_cella_23.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_24
(
.aclr(aclr),
.cin(wire_acc_cella_23cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_24cout[0:0]),
.dataa(wire_acc_cella_dataa[24:24]),
.datab(wire_acc_cella_datab[24:24]),
.datac(wire_acc_cella_datac[24:24]),
.ena(clken),
.regout(wire_acc_cella_regout[24:24]),
.sload(sload));
defparam
acc_cella_24.cin_used = "true",
acc_cella_24.lut_mask = "96e8",
acc_cella_24.operation_mode = "arithmetic",
acc_cella_24.sum_lutc_input = "cin",
acc_cella_24.synch_mode = "on",
acc_cella_24.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_25
(
.aclr(aclr),
.cin(wire_acc_cella_24cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_25cout[0:0]),
.dataa(wire_acc_cella_dataa[25:25]),
.datab(wire_acc_cella_datab[25:25]),
.datac(wire_acc_cella_datac[25:25]),
.ena(clken),
.regout(wire_acc_cella_regout[25:25]),
.sload(sload));
defparam
acc_cella_25.cin_used = "true",
acc_cella_25.lut_mask = "96e8",
acc_cella_25.operation_mode = "arithmetic",
acc_cella_25.sum_lutc_input = "cin",
acc_cella_25.synch_mode = "on",
acc_cella_25.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_26
(
.aclr(aclr),
.cin(wire_acc_cella_25cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_26cout[0:0]),
.dataa(wire_acc_cella_dataa[26:26]),
.datab(wire_acc_cella_datab[26:26]),
.datac(wire_acc_cella_datac[26:26]),
.ena(clken),
.regout(wire_acc_cella_regout[26:26]),
.sload(sload));
defparam
acc_cella_26.cin_used = "true",
acc_cella_26.lut_mask = "96e8",
acc_cella_26.operation_mode = "arithmetic",
acc_cella_26.sum_lutc_input = "cin",
acc_cella_26.synch_mode = "on",
acc_cella_26.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_27
(
.aclr(aclr),
.cin(wire_acc_cella_26cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_27cout[0:0]),
.dataa(wire_acc_cella_dataa[27:27]),
.datab(wire_acc_cella_datab[27:27]),
.datac(wire_acc_cella_datac[27:27]),
.ena(clken),
.regout(wire_acc_cella_regout[27:27]),
.sload(sload));
defparam
acc_cella_27.cin_used = "true",
acc_cella_27.lut_mask = "96e8",
acc_cella_27.operation_mode = "arithmetic",
acc_cella_27.sum_lutc_input = "cin",
acc_cella_27.synch_mode = "on",
acc_cella_27.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_28
(
.aclr(aclr),
.cin(wire_acc_cella_27cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_28cout[0:0]),
.dataa(wire_acc_cella_dataa[28:28]),
.datab(wire_acc_cella_datab[28:28]),
.datac(wire_acc_cella_datac[28:28]),
.ena(clken),
.regout(wire_acc_cella_regout[28:28]),
.sload(sload));
defparam
acc_cella_28.cin_used = "true",
acc_cella_28.lut_mask = "96e8",
acc_cella_28.operation_mode = "arithmetic",
acc_cella_28.sum_lutc_input = "cin",
acc_cella_28.synch_mode = "on",
acc_cella_28.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_29
(
.aclr(aclr),
.cin(wire_acc_cella_28cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_29cout[0:0]),
.dataa(wire_acc_cella_dataa[29:29]),
.datab(wire_acc_cella_datab[29:29]),
.datac(wire_acc_cella_datac[29:29]),
.ena(clken),
.regout(wire_acc_cella_regout[29:29]),
.sload(sload));
defparam
acc_cella_29.cin_used = "true",
acc_cella_29.lut_mask = "96e8",
acc_cella_29.operation_mode = "arithmetic",
acc_cella_29.sum_lutc_input = "cin",
acc_cella_29.synch_mode = "on",
acc_cella_29.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_30
(
.aclr(aclr),
.cin(wire_acc_cella_29cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_30cout[0:0]),
.dataa(wire_acc_cella_dataa[30:30]),
.datab(wire_acc_cella_datab[30:30]),
.datac(wire_acc_cella_datac[30:30]),
.ena(clken),
.regout(wire_acc_cella_regout[30:30]),
.sload(sload));
defparam
acc_cella_30.cin_used = "true",
acc_cella_30.lut_mask = "96e8",
acc_cella_30.operation_mode = "arithmetic",
acc_cella_30.sum_lutc_input = "cin",
acc_cella_30.synch_mode = "on",
acc_cella_30.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_31
(
.aclr(aclr),
.cin(wire_acc_cella_30cout[0:0]),
.clk(clock),
.dataa(wire_acc_cella_dataa[31:31]),
.datab(wire_acc_cella_datab[31:31]),
.datac(wire_acc_cella_datac[31:31]),
.ena(clken),
.regout(wire_acc_cella_regout[31:31]),
.sload(sload));
defparam
acc_cella_31.cin_used = "true",
acc_cella_31.lut_mask = "9696",
acc_cella_31.operation_mode = "normal",
acc_cella_31.sum_lutc_input = "cin",
acc_cella_31.synch_mode = "on",
acc_cella_31.lpm_type = "stratix_lcell";
assign
wire_acc_cella_dataa = data,
wire_acc_cella_datab = wire_acc_cella_regout,
wire_acc_cella_datac = data;
assign
result = wire_acc_cella_regout,
sload = 1'b0;
endmodule
|
module accum32 (
data,
clock,
clken,
aclr,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] data;
input clock;
input clken;
input aclr;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
accum32_accum_nta accum32_accum_nta_component (
.clken (clken),
.aclr (aclr),
.clock (clock),
.data (data),
.result (sub_wire0));
endmodule
|
module spi(
input clk,
input SCK,
input MOSI,
inout MISO,
input SSEL,
output cmd_ready,
output param_ready,
output [7:0] cmd_data,
output [7:0] param_data,
output endmessage,
output startmessage,
input [7:0] input_data,
output [31:0] byte_cnt,
output [2:0] bit_cnt
);
reg [7:0] cmd_data_r;
reg [7:0] param_data_r;
reg [2:0] SSELr;
reg [2:0] SSELSCKr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
always @(posedge SCK) SSELSCKr <= {SSELSCKr[1:0], SSEL};
wire SSEL_inactive = SSELr[1];
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
assign endmessage = SSEL_endmessage;
assign startmessage = SSEL_startmessage;
// bit count for one SPI byte + byte count for the message
reg [2:0] bitcnt;
initial bitcnt = 3'b000;
wire bitcnt_msb = bitcnt[2];
reg [2:0] bitcnt_wrap_r;
always @(posedge clk) bitcnt_wrap_r <= {bitcnt_wrap_r[1:0], bitcnt_msb};
wire byte_received_sync = (bitcnt_wrap_r[2:1] == 2'b10);
reg [31:0] byte_cnt_r;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
assign bit_cnt = bitcnt;
always @(posedge SCK) begin
if(SSELSCKr[1]) bitcnt <= 3'b000;
else bitcnt <= bitcnt + 3'b001;
end
always @(posedge SCK) begin
if(~SSELSCKr[1])
byte_data_received <= {byte_data_received[6:0], MOSI};
if(~SSELSCKr[1] && bitcnt==3'b111)
byte_received <= 1'b1;
else byte_received <= 1'b0;
end
//reg [2:0] byte_received_r;
//always @(posedge clk) byte_received_r <= {byte_received_r[1:0], byte_received};
//wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
always @(posedge clk) begin
if(SSEL_inactive)
byte_cnt_r <= 16'h0000;
else if(byte_received_sync)
byte_cnt_r <= byte_cnt_r + 16'h0001;
end
reg [7:0] byte_data_sent;
assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first
reg cmd_ready_r;
reg param_ready_r;
reg cmd_ready_r2;
reg param_ready_r2;
assign cmd_ready = cmd_ready_r;
assign param_ready = param_ready_r;
assign cmd_data = cmd_data_r;
assign param_data = param_data_r;
assign byte_cnt = byte_cnt_r;
always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0;
always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0;
// fill registers
always @(posedge clk) begin
if (SSEL_startmessage)
cmd_data_r <= 8'h00;
else if(cmd_ready_r2)
cmd_data_r <= byte_data_received;
else if(param_ready_r2)
param_data_r <= byte_data_received;
end
// delay ready signals by one clock
always @(posedge clk) begin
cmd_ready_r <= cmd_ready_r2;
param_ready_r <= param_ready_r2;
end
endmodule
|
module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 16;
parameter depth = 1024;
parameter addr_bits = 10;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [width-1:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [width-1:0] q;
output rdfull;
output rdempty;
output reg [addr_bits-1:0] rdusedw;
output wrfull;
output wrempty;
output reg [addr_bits-1:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [addr_bits-1:0] rdptr;
reg [addr_bits-1:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule
|
module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 16;
parameter depth = 1024;
parameter addr_bits = 10;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [width-1:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [width-1:0] q;
output rdfull;
output rdempty;
output reg [addr_bits-1:0] rdusedw;
output wrfull;
output wrempty;
output reg [addr_bits-1:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [addr_bits-1:0] rdptr;
reg [addr_bits-1:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule
|
module bidir_reg
( inout wire [15:0] tristate,
input wire [15:0] oe,
input wire [15:0] reg_val );
// This would be much cleaner if all the tools
// supported "for generate"........
assign tristate[0] = oe[0] ? reg_val[0] : 1'bz;
assign tristate[1] = oe[1] ? reg_val[1] : 1'bz;
assign tristate[2] = oe[2] ? reg_val[2] : 1'bz;
assign tristate[3] = oe[3] ? reg_val[3] : 1'bz;
assign tristate[4] = oe[4] ? reg_val[4] : 1'bz;
assign tristate[5] = oe[5] ? reg_val[5] : 1'bz;
assign tristate[6] = oe[6] ? reg_val[6] : 1'bz;
assign tristate[7] = oe[7] ? reg_val[7] : 1'bz;
assign tristate[8] = oe[8] ? reg_val[8] : 1'bz;
assign tristate[9] = oe[9] ? reg_val[9] : 1'bz;
assign tristate[10] = oe[10] ? reg_val[10] : 1'bz;
assign tristate[11] = oe[11] ? reg_val[11] : 1'bz;
assign tristate[12] = oe[12] ? reg_val[12] : 1'bz;
assign tristate[13] = oe[13] ? reg_val[13] : 1'bz;
assign tristate[14] = oe[14] ? reg_val[14] : 1'bz;
assign tristate[15] = oe[15] ? reg_val[15] : 1'bz;
endmodule
|
module bidir_reg
( inout wire [15:0] tristate,
input wire [15:0] oe,
input wire [15:0] reg_val );
// This would be much cleaner if all the tools
// supported "for generate"........
assign tristate[0] = oe[0] ? reg_val[0] : 1'bz;
assign tristate[1] = oe[1] ? reg_val[1] : 1'bz;
assign tristate[2] = oe[2] ? reg_val[2] : 1'bz;
assign tristate[3] = oe[3] ? reg_val[3] : 1'bz;
assign tristate[4] = oe[4] ? reg_val[4] : 1'bz;
assign tristate[5] = oe[5] ? reg_val[5] : 1'bz;
assign tristate[6] = oe[6] ? reg_val[6] : 1'bz;
assign tristate[7] = oe[7] ? reg_val[7] : 1'bz;
assign tristate[8] = oe[8] ? reg_val[8] : 1'bz;
assign tristate[9] = oe[9] ? reg_val[9] : 1'bz;
assign tristate[10] = oe[10] ? reg_val[10] : 1'bz;
assign tristate[11] = oe[11] ? reg_val[11] : 1'bz;
assign tristate[12] = oe[12] ? reg_val[12] : 1'bz;
assign tristate[13] = oe[13] ? reg_val[13] : 1'bz;
assign tristate[14] = oe[14] ? reg_val[14] : 1'bz;
assign tristate[15] = oe[15] ? reg_val[15] : 1'bz;
endmodule
|
module bidir_reg
( inout wire [15:0] tristate,
input wire [15:0] oe,
input wire [15:0] reg_val );
// This would be much cleaner if all the tools
// supported "for generate"........
assign tristate[0] = oe[0] ? reg_val[0] : 1'bz;
assign tristate[1] = oe[1] ? reg_val[1] : 1'bz;
assign tristate[2] = oe[2] ? reg_val[2] : 1'bz;
assign tristate[3] = oe[3] ? reg_val[3] : 1'bz;
assign tristate[4] = oe[4] ? reg_val[4] : 1'bz;
assign tristate[5] = oe[5] ? reg_val[5] : 1'bz;
assign tristate[6] = oe[6] ? reg_val[6] : 1'bz;
assign tristate[7] = oe[7] ? reg_val[7] : 1'bz;
assign tristate[8] = oe[8] ? reg_val[8] : 1'bz;
assign tristate[9] = oe[9] ? reg_val[9] : 1'bz;
assign tristate[10] = oe[10] ? reg_val[10] : 1'bz;
assign tristate[11] = oe[11] ? reg_val[11] : 1'bz;
assign tristate[12] = oe[12] ? reg_val[12] : 1'bz;
assign tristate[13] = oe[13] ? reg_val[13] : 1'bz;
assign tristate[14] = oe[14] ? reg_val[14] : 1'bz;
assign tristate[15] = oe[15] ? reg_val[15] : 1'bz;
endmodule
|
module bidir_reg
( inout wire [15:0] tristate,
input wire [15:0] oe,
input wire [15:0] reg_val );
// This would be much cleaner if all the tools
// supported "for generate"........
assign tristate[0] = oe[0] ? reg_val[0] : 1'bz;
assign tristate[1] = oe[1] ? reg_val[1] : 1'bz;
assign tristate[2] = oe[2] ? reg_val[2] : 1'bz;
assign tristate[3] = oe[3] ? reg_val[3] : 1'bz;
assign tristate[4] = oe[4] ? reg_val[4] : 1'bz;
assign tristate[5] = oe[5] ? reg_val[5] : 1'bz;
assign tristate[6] = oe[6] ? reg_val[6] : 1'bz;
assign tristate[7] = oe[7] ? reg_val[7] : 1'bz;
assign tristate[8] = oe[8] ? reg_val[8] : 1'bz;
assign tristate[9] = oe[9] ? reg_val[9] : 1'bz;
assign tristate[10] = oe[10] ? reg_val[10] : 1'bz;
assign tristate[11] = oe[11] ? reg_val[11] : 1'bz;
assign tristate[12] = oe[12] ? reg_val[12] : 1'bz;
assign tristate[13] = oe[13] ? reg_val[13] : 1'bz;
assign tristate[14] = oe[14] ? reg_val[14] : 1'bz;
assign tristate[15] = oe[15] ? reg_val[15] : 1'bz;
endmodule
|
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_add_sub lpm_add_sub_component (
.dataa (dataa),
.add_sub (add_sub),
.datab (datab),
.clock (clock),
.result (sub_wire0));
defparam
lpm_add_sub_component.lpm_width = 16,
lpm_add_sub_component.lpm_direction = "UNUSED",
lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO",
lpm_add_sub_component.lpm_pipeline = 1;
endmodule
|
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_add_sub lpm_add_sub_component (
.dataa (dataa),
.add_sub (add_sub),
.datab (datab),
.clock (clock),
.result (sub_wire0));
defparam
lpm_add_sub_component.lpm_width = 16,
lpm_add_sub_component.lpm_direction = "UNUSED",
lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO",
lpm_add_sub_component.lpm_pipeline = 1;
endmodule
|
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_add_sub lpm_add_sub_component (
.dataa (dataa),
.add_sub (add_sub),
.datab (datab),
.clock (clock),
.result (sub_wire0));
defparam
lpm_add_sub_component.lpm_width = 16,
lpm_add_sub_component.lpm_direction = "UNUSED",
lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO",
lpm_add_sub_component.lpm_pipeline = 1;
endmodule
|
module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o);
input clk_i;
input rst_i;
input ena_i;
input tx_empty_i;
input [11:0] tx_delay_i;
input [11:0] rx_delay_i;
output atr_tx_o;
reg [3:0] state;
reg [11:0] count;
`define ST_RX_DELAY 4'b0001
`define ST_RX 4'b0010
`define ST_TX_DELAY 4'b0100
`define ST_TX 4'b1000
always @(posedge clk_i)
if (rst_i | ~ena_i)
begin
state <= `ST_RX;
count <= 12'b0;
end
else
case (state)
`ST_RX:
if (!tx_empty_i)
begin
state <= `ST_TX_DELAY;
count <= tx_delay_i;
end
`ST_TX_DELAY:
if (count == 0)
state <= `ST_TX;
else
count <= count - 1;
`ST_TX:
if (tx_empty_i)
begin
state <= `ST_RX_DELAY;
count <= rx_delay_i;
end
`ST_RX_DELAY:
if (count == 0)
state <= `ST_RX;
else
count <= count - 1;
default: // Error
begin
state <= `ST_RX;
count <= 0;
end
endcase
assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY);
endmodule
|
module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o);
input clk_i;
input rst_i;
input ena_i;
input tx_empty_i;
input [11:0] tx_delay_i;
input [11:0] rx_delay_i;
output atr_tx_o;
reg [3:0] state;
reg [11:0] count;
`define ST_RX_DELAY 4'b0001
`define ST_RX 4'b0010
`define ST_TX_DELAY 4'b0100
`define ST_TX 4'b1000
always @(posedge clk_i)
if (rst_i | ~ena_i)
begin
state <= `ST_RX;
count <= 12'b0;
end
else
case (state)
`ST_RX:
if (!tx_empty_i)
begin
state <= `ST_TX_DELAY;
count <= tx_delay_i;
end
`ST_TX_DELAY:
if (count == 0)
state <= `ST_TX;
else
count <= count - 1;
`ST_TX:
if (tx_empty_i)
begin
state <= `ST_RX_DELAY;
count <= rx_delay_i;
end
`ST_RX_DELAY:
if (count == 0)
state <= `ST_RX;
else
count <= count - 1;
default: // Error
begin
state <= `ST_RX;
count <= 0;
end
endcase
assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY);
endmodule
|
module dspclkpll (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [5:0] sub_wire0;
wire [0:0] sub_wire5 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0)
// synopsys translate_off
,
.fbin (),
.pllena (),
.clkswitch (),
.areset (),
.pfdena (),
.clkena (),
.extclkena (),
.scanclk (),
.scanaclr (),
.scandata (),
.scanread (),
.scanwrite (),
.extclk (),
.clkbad (),
.activeclock (),
.locked (),
.clkloss (),
.scandataout (),
.scandone (),
.sclkout1 (),
.sclkout0 (),
.enable0 (),
.enable1 ()
// synopsys translate_on
);
defparam
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 15625,
altpll_component.clk0_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.pll_type = "AUTO",
altpll_component.clk1_multiply_by = 2,
altpll_component.clk0_time_delay = "0",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk1_time_delay = "0",
altpll_component.clk0_phase_shift = "0";
endmodule
|
module dspclkpll (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [5:0] sub_wire0;
wire [0:0] sub_wire5 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0)
// synopsys translate_off
,
.fbin (),
.pllena (),
.clkswitch (),
.areset (),
.pfdena (),
.clkena (),
.extclkena (),
.scanclk (),
.scanaclr (),
.scandata (),
.scanread (),
.scanwrite (),
.extclk (),
.clkbad (),
.activeclock (),
.locked (),
.clkloss (),
.scandataout (),
.scandone (),
.sclkout1 (),
.sclkout0 (),
.enable0 (),
.enable1 ()
// synopsys translate_on
);
defparam
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 15625,
altpll_component.clk0_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.pll_type = "AUTO",
altpll_component.clk1_multiply_by = 2,
altpll_component.clk0_time_delay = "0",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk1_time_delay = "0",
altpll_component.clk0_phase_shift = "0";
endmodule
|
module dspclkpll (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [5:0] sub_wire0;
wire [0:0] sub_wire5 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0)
// synopsys translate_off
,
.fbin (),
.pllena (),
.clkswitch (),
.areset (),
.pfdena (),
.clkena (),
.extclkena (),
.scanclk (),
.scanaclr (),
.scandata (),
.scanread (),
.scanwrite (),
.extclk (),
.clkbad (),
.activeclock (),
.locked (),
.clkloss (),
.scandataout (),
.scandone (),
.sclkout1 (),
.sclkout0 (),
.enable0 (),
.enable1 ()
// synopsys translate_on
);
defparam
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 15625,
altpll_component.clk0_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.pll_type = "AUTO",
altpll_component.clk1_multiply_by = 2,
altpll_component.clk0_time_delay = "0",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk1_time_delay = "0",
altpll_component.clk0_phase_shift = "0";
endmodule
|
module dspclkpll (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [5:0] sub_wire0;
wire [0:0] sub_wire5 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0)
// synopsys translate_off
,
.fbin (),
.pllena (),
.clkswitch (),
.areset (),
.pfdena (),
.clkena (),
.extclkena (),
.scanclk (),
.scanaclr (),
.scandata (),
.scanread (),
.scanwrite (),
.extclk (),
.clkbad (),
.activeclock (),
.locked (),
.clkloss (),
.scandataout (),
.scandone (),
.sclkout1 (),
.sclkout0 (),
.enable0 (),
.enable1 ()
// synopsys translate_on
);
defparam
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 15625,
altpll_component.clk0_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.pll_type = "AUTO",
altpll_component.clk1_multiply_by = 2,
altpll_component.clk0_time_delay = "0",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk1_time_delay = "0",
altpll_component.clk0_phase_shift = "0";
endmodule
|
module strobe_gen
( input clock,
input reset,
input enable,
input [7:0] rate, // Rate should be 1 LESS THAN your desired divide ratio
input strobe_in,
output wire strobe );
// parameter width = 8;
reg [7:0] counter;
assign strobe = ~|counter && enable && strobe_in;
always @(posedge clock)
if(reset | ~enable)
counter <= #1 8'd0;
else if(strobe_in)
if(counter == 0)
counter <= #1 rate;
else
counter <= #1 counter - 8'd1;
endmodule
|
module strobe_gen
( input clock,
input reset,
input enable,
input [7:0] rate, // Rate should be 1 LESS THAN your desired divide ratio
input strobe_in,
output wire strobe );
// parameter width = 8;
reg [7:0] counter;
assign strobe = ~|counter && enable && strobe_in;
always @(posedge clock)
if(reset | ~enable)
counter <= #1 8'd0;
else if(strobe_in)
if(counter == 0)
counter <= #1 rate;
else
counter <= #1 counter - 8'd1;
endmodule
|
module cordic(clock, reset, enable, xi, yi, zi, xo, yo, zo );
parameter bitwidth = 16;
parameter zwidth = 16;
input clock;
input reset;
input enable;
input [bitwidth-1:0] xi, yi;
output [bitwidth-1:0] xo, yo;
input [zwidth-1:0] zi;
output [zwidth-1:0] zo;
reg [bitwidth+1:0] x0,y0;
reg [zwidth-2:0] z0;
wire [bitwidth+1:0] x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12;
wire [bitwidth+1:0] y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12;
wire [zwidth-2:0] z1,z2,z3,z4,z5,z6,z7,z8,z9,z10,z11,z12;
wire [bitwidth+1:0] xi_ext = {{2{xi[bitwidth-1]}},xi};
wire [bitwidth+1:0] yi_ext = {{2{yi[bitwidth-1]}},yi};
// Compute consts. Would be easier if vlog had atan...
// see gen_cordic_consts.py
`define c00 16'd8192
`define c01 16'd4836
`define c02 16'd2555
`define c03 16'd1297
`define c04 16'd651
`define c05 16'd326
`define c06 16'd163
`define c07 16'd81
`define c08 16'd41
`define c09 16'd20
`define c10 16'd10
`define c11 16'd5
`define c12 16'd3
`define c13 16'd1
`define c14 16'd1
`define c15 16'd0
`define c16 16'd0
always @(posedge clock)
if(reset)
begin
x0 <= #1 0; y0 <= #1 0; z0 <= #1 0;
end
else if(enable)
begin
z0 <= #1 zi[zwidth-2:0];
case (zi[zwidth-1:zwidth-2])
2'b00, 2'b11 :
begin
x0 <= #1 xi_ext;
y0 <= #1 yi_ext;
end
2'b01, 2'b10 :
begin
x0 <= #1 -xi_ext;
y0 <= #1 -yi_ext;
end
endcase // case(zi[zwidth-1:zwidth-2])
end // else: !if(reset)
// FIXME need to handle variable number of stages
// FIXME should be able to narrow zwidth but quartus makes it bigger...
// This would be easier if arrays worked better in vlog...
cordic_stage #(bitwidth+2,zwidth-1,0) cordic_stage0 (clock,reset,enable,x0,y0,z0,`c00,x1,y1,z1);
cordic_stage #(bitwidth+2,zwidth-1,1) cordic_stage1 (clock,reset,enable,x1,y1,z1,`c01,x2,y2,z2);
cordic_stage #(bitwidth+2,zwidth-1,2) cordic_stage2 (clock,reset,enable,x2,y2,z2,`c02,x3,y3,z3);
cordic_stage #(bitwidth+2,zwidth-1,3) cordic_stage3 (clock,reset,enable,x3,y3,z3,`c03,x4,y4,z4);
cordic_stage #(bitwidth+2,zwidth-1,4) cordic_stage4 (clock,reset,enable,x4,y4,z4,`c04,x5,y5,z5);
cordic_stage #(bitwidth+2,zwidth-1,5) cordic_stage5 (clock,reset,enable,x5,y5,z5,`c05,x6,y6,z6);
cordic_stage #(bitwidth+2,zwidth-1,6) cordic_stage6 (clock,reset,enable,x6,y6,z6,`c06,x7,y7,z7);
cordic_stage #(bitwidth+2,zwidth-1,7) cordic_stage7 (clock,reset,enable,x7,y7,z7,`c07,x8,y8,z8);
cordic_stage #(bitwidth+2,zwidth-1,8) cordic_stage8 (clock,reset,enable,x8,y8,z8,`c08,x9,y9,z9);
cordic_stage #(bitwidth+2,zwidth-1,9) cordic_stage9 (clock,reset,enable,x9,y9,z9,`c09,x10,y10,z10);
cordic_stage #(bitwidth+2,zwidth-1,10) cordic_stage10 (clock,reset,enable,x10,y10,z10,`c10,x11,y11,z11);
cordic_stage #(bitwidth+2,zwidth-1,11) cordic_stage11 (clock,reset,enable,x11,y11,z11,`c11,x12,y12,z12);
assign xo = x12[bitwidth:1];
assign yo = y12[bitwidth:1];
//assign xo = x12[bitwidth+1:2]; // CORDIC gain is ~1.6, plus gain from rotating vectors
//assign yo = y12[bitwidth+1:2];
assign zo = z12;
endmodule
|
module cordic(clock, reset, enable, xi, yi, zi, xo, yo, zo );
parameter bitwidth = 16;
parameter zwidth = 16;
input clock;
input reset;
input enable;
input [bitwidth-1:0] xi, yi;
output [bitwidth-1:0] xo, yo;
input [zwidth-1:0] zi;
output [zwidth-1:0] zo;
reg [bitwidth+1:0] x0,y0;
reg [zwidth-2:0] z0;
wire [bitwidth+1:0] x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12;
wire [bitwidth+1:0] y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12;
wire [zwidth-2:0] z1,z2,z3,z4,z5,z6,z7,z8,z9,z10,z11,z12;
wire [bitwidth+1:0] xi_ext = {{2{xi[bitwidth-1]}},xi};
wire [bitwidth+1:0] yi_ext = {{2{yi[bitwidth-1]}},yi};
// Compute consts. Would be easier if vlog had atan...
// see gen_cordic_consts.py
`define c00 16'd8192
`define c01 16'd4836
`define c02 16'd2555
`define c03 16'd1297
`define c04 16'd651
`define c05 16'd326
`define c06 16'd163
`define c07 16'd81
`define c08 16'd41
`define c09 16'd20
`define c10 16'd10
`define c11 16'd5
`define c12 16'd3
`define c13 16'd1
`define c14 16'd1
`define c15 16'd0
`define c16 16'd0
always @(posedge clock)
if(reset)
begin
x0 <= #1 0; y0 <= #1 0; z0 <= #1 0;
end
else if(enable)
begin
z0 <= #1 zi[zwidth-2:0];
case (zi[zwidth-1:zwidth-2])
2'b00, 2'b11 :
begin
x0 <= #1 xi_ext;
y0 <= #1 yi_ext;
end
2'b01, 2'b10 :
begin
x0 <= #1 -xi_ext;
y0 <= #1 -yi_ext;
end
endcase // case(zi[zwidth-1:zwidth-2])
end // else: !if(reset)
// FIXME need to handle variable number of stages
// FIXME should be able to narrow zwidth but quartus makes it bigger...
// This would be easier if arrays worked better in vlog...
cordic_stage #(bitwidth+2,zwidth-1,0) cordic_stage0 (clock,reset,enable,x0,y0,z0,`c00,x1,y1,z1);
cordic_stage #(bitwidth+2,zwidth-1,1) cordic_stage1 (clock,reset,enable,x1,y1,z1,`c01,x2,y2,z2);
cordic_stage #(bitwidth+2,zwidth-1,2) cordic_stage2 (clock,reset,enable,x2,y2,z2,`c02,x3,y3,z3);
cordic_stage #(bitwidth+2,zwidth-1,3) cordic_stage3 (clock,reset,enable,x3,y3,z3,`c03,x4,y4,z4);
cordic_stage #(bitwidth+2,zwidth-1,4) cordic_stage4 (clock,reset,enable,x4,y4,z4,`c04,x5,y5,z5);
cordic_stage #(bitwidth+2,zwidth-1,5) cordic_stage5 (clock,reset,enable,x5,y5,z5,`c05,x6,y6,z6);
cordic_stage #(bitwidth+2,zwidth-1,6) cordic_stage6 (clock,reset,enable,x6,y6,z6,`c06,x7,y7,z7);
cordic_stage #(bitwidth+2,zwidth-1,7) cordic_stage7 (clock,reset,enable,x7,y7,z7,`c07,x8,y8,z8);
cordic_stage #(bitwidth+2,zwidth-1,8) cordic_stage8 (clock,reset,enable,x8,y8,z8,`c08,x9,y9,z9);
cordic_stage #(bitwidth+2,zwidth-1,9) cordic_stage9 (clock,reset,enable,x9,y9,z9,`c09,x10,y10,z10);
cordic_stage #(bitwidth+2,zwidth-1,10) cordic_stage10 (clock,reset,enable,x10,y10,z10,`c10,x11,y11,z11);
cordic_stage #(bitwidth+2,zwidth-1,11) cordic_stage11 (clock,reset,enable,x11,y11,z11,`c11,x12,y12,z12);
assign xo = x12[bitwidth:1];
assign yo = y12[bitwidth:1];
//assign xo = x12[bitwidth+1:2]; // CORDIC gain is ~1.6, plus gain from rotating vectors
//assign yo = y12[bitwidth+1:2];
assign zo = z12;
endmodule
|
module fifo_4k_a_gray2bin_9m4
(
bin,
gray) /* synthesis synthesis_clearbox=1 */;
output [11:0] bin;
input [11:0] gray;
wire xor0;
wire xor1;
wire xor10;
wire xor2;
wire xor3;
wire xor4;
wire xor5;
wire xor6;
wire xor7;
wire xor8;
wire xor9;
assign
bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
xor0 = (gray[0] ^ xor1),
xor1 = (gray[1] ^ xor2),
xor10 = (gray[11] ^ gray[10]),
xor2 = (gray[2] ^ xor3),
xor3 = (gray[3] ^ xor4),
xor4 = (gray[4] ^ xor5),
xor5 = (gray[5] ^ xor6),
xor6 = (gray[6] ^ xor7),
xor7 = (gray[7] ^ xor8),
xor8 = (gray[8] ^ xor9),
xor9 = (gray[9] ^ xor10);
endmodule
|
module fifo_4k_a_graycounter_826
(
aclr,
clock,
cnt_en,
q) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [11:0] q;
wire [0:0] wire_countera_0cout;
wire [0:0] wire_countera_1cout;
wire [0:0] wire_countera_2cout;
wire [0:0] wire_countera_3cout;
wire [0:0] wire_countera_4cout;
wire [0:0] wire_countera_5cout;
wire [0:0] wire_countera_6cout;
wire [0:0] wire_countera_7cout;
wire [0:0] wire_countera_8cout;
wire [0:0] wire_countera_9cout;
wire [0:0] wire_countera_10cout;
wire [11:0] wire_countera_regout;
wire wire_parity_cout;
wire wire_parity_regout;
wire [11:0] power_modified_counter_values;
wire sclr;
wire updown;
cyclone_lcell countera_0
(
.aclr(aclr),
.cin(wire_parity_cout),
.clk(clock),
.combout(),
.cout(wire_countera_0cout[0:0]),
.dataa(cnt_en),
.datab(wire_countera_regout[0:0]),
.ena(1'b1),
.regout(wire_countera_regout[0:0]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_0.cin_used = "true",
countera_0.lut_mask = "c6a0",
countera_0.operation_mode = "arithmetic",
countera_0.sum_lutc_input = "cin",
countera_0.synch_mode = "on",
countera_0.lpm_type = "cyclone_lcell";
cyclone_lcell countera_1
(
.aclr(aclr),
.cin(wire_countera_0cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_1cout[0:0]),
.dataa(power_modified_counter_values[0]),
.datab(power_modified_counter_values[1]),
.ena(1'b1),
.regout(wire_countera_regout[1:1]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_1.cin_used = "true",
countera_1.lut_mask = "6c50",
countera_1.operation_mode = "arithmetic",
countera_1.sum_lutc_input = "cin",
countera_1.synch_mode = "on",
countera_1.lpm_type = "cyclone_lcell";
cyclone_lcell countera_2
(
.aclr(aclr),
.cin(wire_countera_1cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_2cout[0:0]),
.dataa(power_modified_counter_values[1]),
.datab(power_modified_counter_values[2]),
.ena(1'b1),
.regout(wire_countera_regout[2:2]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_2.cin_used = "true",
countera_2.lut_mask = "6c50",
countera_2.operation_mode = "arithmetic",
countera_2.sum_lutc_input = "cin",
countera_2.synch_mode = "on",
countera_2.lpm_type = "cyclone_lcell";
cyclone_lcell countera_3
(
.aclr(aclr),
.cin(wire_countera_2cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_3cout[0:0]),
.dataa(power_modified_counter_values[2]),
.datab(power_modified_counter_values[3]),
.ena(1'b1),
.regout(wire_countera_regout[3:3]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_3.cin_used = "true",
countera_3.lut_mask = "6c50",
countera_3.operation_mode = "arithmetic",
countera_3.sum_lutc_input = "cin",
countera_3.synch_mode = "on",
countera_3.lpm_type = "cyclone_lcell";
cyclone_lcell countera_4
(
.aclr(aclr),
.cin(wire_countera_3cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_4cout[0:0]),
.dataa(power_modified_counter_values[3]),
.datab(power_modified_counter_values[4]),
.ena(1'b1),
.regout(wire_countera_regout[4:4]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_4.cin_used = "true",
countera_4.lut_mask = "6c50",
countera_4.operation_mode = "arithmetic",
countera_4.sum_lutc_input = "cin",
countera_4.synch_mode = "on",
countera_4.lpm_type = "cyclone_lcell";
cyclone_lcell countera_5
(
.aclr(aclr),
.cin(wire_countera_4cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_5cout[0:0]),
.dataa(power_modified_counter_values[4]),
.datab(power_modified_counter_values[5]),
.ena(1'b1),
.regout(wire_countera_regout[5:5]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_5.cin_used = "true",
countera_5.lut_mask = "6c50",
countera_5.operation_mode = "arithmetic",
countera_5.sum_lutc_input = "cin",
countera_5.synch_mode = "on",
countera_5.lpm_type = "cyclone_lcell";
cyclone_lcell countera_6
(
.aclr(aclr),
.cin(wire_countera_5cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_6cout[0:0]),
.dataa(power_modified_counter_values[5]),
.datab(power_modified_counter_values[6]),
.ena(1'b1),
.regout(wire_countera_regout[6:6]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_6.cin_used = "true",
countera_6.lut_mask = "6c50",
countera_6.operation_mode = "arithmetic",
countera_6.sum_lutc_input = "cin",
countera_6.synch_mode = "on",
countera_6.lpm_type = "cyclone_lcell";
cyclone_lcell countera_7
(
.aclr(aclr),
.cin(wire_countera_6cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_7cout[0:0]),
.dataa(power_modified_counter_values[6]),
.datab(power_modified_counter_values[7]),
.ena(1'b1),
.regout(wire_countera_regout[7:7]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_7.cin_used = "true",
countera_7.lut_mask = "6c50",
countera_7.operation_mode = "arithmetic",
countera_7.sum_lutc_input = "cin",
countera_7.synch_mode = "on",
countera_7.lpm_type = "cyclone_lcell";
cyclone_lcell countera_8
(
.aclr(aclr),
.cin(wire_countera_7cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_8cout[0:0]),
.dataa(power_modified_counter_values[7]),
.datab(power_modified_counter_values[8]),
.ena(1'b1),
.regout(wire_countera_regout[8:8]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_8.cin_used = "true",
countera_8.lut_mask = "6c50",
countera_8.operation_mode = "arithmetic",
countera_8.sum_lutc_input = "cin",
countera_8.synch_mode = "on",
countera_8.lpm_type = "cyclone_lcell";
cyclone_lcell countera_9
(
.aclr(aclr),
.cin(wire_countera_8cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_9cout[0:0]),
.dataa(power_modified_counter_values[8]),
.datab(power_modified_counter_values[9]),
.ena(1'b1),
.regout(wire_countera_regout[9:9]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_9.cin_used = "true",
countera_9.lut_mask = "6c50",
countera_9.operation_mode = "arithmetic",
countera_9.sum_lutc_input = "cin",
countera_9.synch_mode = "on",
countera_9.lpm_type = "cyclone_lcell";
cyclone_lcell countera_10
(
.aclr(aclr),
.cin(wire_countera_9cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_10cout[0:0]),
.dataa(power_modified_counter_values[9]),
.datab(power_modified_counter_values[10]),
.ena(1'b1),
.regout(wire_countera_regout[10:10]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_10.cin_used = "true",
countera_10.lut_mask = "6c50",
countera_10.operation_mode = "arithmetic",
countera_10.sum_lutc_input = "cin",
countera_10.synch_mode = "on",
countera_10.lpm_type = "cyclone_lcell";
cyclone_lcell countera_11
(
.aclr(aclr),
.cin(wire_countera_10cout[0:0]),
.clk(clock),
.combout(),
.cout(),
.dataa(power_modified_counter_values[11]),
.ena(1'b1),
.regout(wire_countera_regout[11:11]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datab(1'b1),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_11.cin_used = "true",
countera_11.lut_mask = "5a5a",
countera_11.operation_mode = "normal",
countera_11.sum_lutc_input = "cin",
countera_11.synch_mode = "on",
countera_11.lpm_type = "cyclone_lcell";
cyclone_lcell parity
(
.aclr(aclr),
.cin(updown),
.clk(clock),
.combout(),
.cout(wire_parity_cout),
.dataa(cnt_en),
.datab(wire_parity_regout),
.ena(1'b1),
.regout(wire_parity_regout),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
parity.cin_used = "true",
parity.lut_mask = "6682",
parity.operation_mode = "arithmetic",
parity.synch_mode = "on",
parity.lpm_type = "cyclone_lcell";
assign
power_modified_counter_values = {wire_countera_regout[11:0]},
q = power_modified_counter_values,
sclr = 1'b0,
updown = 1'b1;
endmodule
|
module fifo_4k_a_graycounter_3r6
(
aclr,
clock,
cnt_en,
q) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [11:0] q;
wire [0:0] wire_countera_0cout;
wire [0:0] wire_countera_1cout;
wire [0:0] wire_countera_2cout;
wire [0:0] wire_countera_3cout;
wire [0:0] wire_countera_4cout;
wire [0:0] wire_countera_5cout;
wire [0:0] wire_countera_6cout;
wire [0:0] wire_countera_7cout;
wire [0:0] wire_countera_8cout;
wire [0:0] wire_countera_9cout;
wire [0:0] wire_countera_10cout;
wire [11:0] wire_countera_regout;
wire wire_parity_cout;
wire wire_parity_regout;
wire [11:0] power_modified_counter_values;
wire sclr;
wire updown;
cyclone_lcell countera_0
(
.aclr(aclr),
.cin(wire_parity_cout),
.clk(clock),
.combout(),
.cout(wire_countera_0cout[0:0]),
.dataa(cnt_en),
.datab(wire_countera_regout[0:0]),
.ena(1'b1),
.regout(wire_countera_regout[0:0]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_0.cin_used = "true",
countera_0.lut_mask = "c6a0",
countera_0.operation_mode = "arithmetic",
countera_0.sum_lutc_input = "cin",
countera_0.synch_mode = "on",
countera_0.lpm_type = "cyclone_lcell";
cyclone_lcell countera_1
(
.aclr(aclr),
.cin(wire_countera_0cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_1cout[0:0]),
.dataa(power_modified_counter_values[0]),
.datab(power_modified_counter_values[1]),
.ena(1'b1),
.regout(wire_countera_regout[1:1]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_1.cin_used = "true",
countera_1.lut_mask = "6c50",
countera_1.operation_mode = "arithmetic",
countera_1.sum_lutc_input = "cin",
countera_1.synch_mode = "on",
countera_1.lpm_type = "cyclone_lcell";
cyclone_lcell countera_2
(
.aclr(aclr),
.cin(wire_countera_1cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_2cout[0:0]),
.dataa(power_modified_counter_values[1]),
.datab(power_modified_counter_values[2]),
.ena(1'b1),
.regout(wire_countera_regout[2:2]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_2.cin_used = "true",
countera_2.lut_mask = "6c50",
countera_2.operation_mode = "arithmetic",
countera_2.sum_lutc_input = "cin",
countera_2.synch_mode = "on",
countera_2.lpm_type = "cyclone_lcell";
cyclone_lcell countera_3
(
.aclr(aclr),
.cin(wire_countera_2cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_3cout[0:0]),
.dataa(power_modified_counter_values[2]),
.datab(power_modified_counter_values[3]),
.ena(1'b1),
.regout(wire_countera_regout[3:3]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_3.cin_used = "true",
countera_3.lut_mask = "6c50",
countera_3.operation_mode = "arithmetic",
countera_3.sum_lutc_input = "cin",
countera_3.synch_mode = "on",
countera_3.lpm_type = "cyclone_lcell";
cyclone_lcell countera_4
(
.aclr(aclr),
.cin(wire_countera_3cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_4cout[0:0]),
.dataa(power_modified_counter_values[3]),
.datab(power_modified_counter_values[4]),
.ena(1'b1),
.regout(wire_countera_regout[4:4]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_4.cin_used = "true",
countera_4.lut_mask = "6c50",
countera_4.operation_mode = "arithmetic",
countera_4.sum_lutc_input = "cin",
countera_4.synch_mode = "on",
countera_4.lpm_type = "cyclone_lcell";
cyclone_lcell countera_5
(
.aclr(aclr),
.cin(wire_countera_4cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_5cout[0:0]),
.dataa(power_modified_counter_values[4]),
.datab(power_modified_counter_values[5]),
.ena(1'b1),
.regout(wire_countera_regout[5:5]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_5.cin_used = "true",
countera_5.lut_mask = "6c50",
countera_5.operation_mode = "arithmetic",
countera_5.sum_lutc_input = "cin",
countera_5.synch_mode = "on",
countera_5.lpm_type = "cyclone_lcell";
cyclone_lcell countera_6
(
.aclr(aclr),
.cin(wire_countera_5cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_6cout[0:0]),
.dataa(power_modified_counter_values[5]),
.datab(power_modified_counter_values[6]),
.ena(1'b1),
.regout(wire_countera_regout[6:6]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_6.cin_used = "true",
countera_6.lut_mask = "6c50",
countera_6.operation_mode = "arithmetic",
countera_6.sum_lutc_input = "cin",
countera_6.synch_mode = "on",
countera_6.lpm_type = "cyclone_lcell";
cyclone_lcell countera_7
(
.aclr(aclr),
.cin(wire_countera_6cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_7cout[0:0]),
.dataa(power_modified_counter_values[6]),
.datab(power_modified_counter_values[7]),
.ena(1'b1),
.regout(wire_countera_regout[7:7]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_7.cin_used = "true",
countera_7.lut_mask = "6c50",
countera_7.operation_mode = "arithmetic",
countera_7.sum_lutc_input = "cin",
countera_7.synch_mode = "on",
countera_7.lpm_type = "cyclone_lcell";
cyclone_lcell countera_8
(
.aclr(aclr),
.cin(wire_countera_7cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_8cout[0:0]),
.dataa(power_modified_counter_values[7]),
.datab(power_modified_counter_values[8]),
.ena(1'b1),
.regout(wire_countera_regout[8:8]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_8.cin_used = "true",
countera_8.lut_mask = "6c50",
countera_8.operation_mode = "arithmetic",
countera_8.sum_lutc_input = "cin",
countera_8.synch_mode = "on",
countera_8.lpm_type = "cyclone_lcell";
cyclone_lcell countera_9
(
.aclr(aclr),
.cin(wire_countera_8cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_9cout[0:0]),
.dataa(power_modified_counter_values[8]),
.datab(power_modified_counter_values[9]),
.ena(1'b1),
.regout(wire_countera_regout[9:9]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_9.cin_used = "true",
countera_9.lut_mask = "6c50",
countera_9.operation_mode = "arithmetic",
countera_9.sum_lutc_input = "cin",
countera_9.synch_mode = "on",
countera_9.lpm_type = "cyclone_lcell";
cyclone_lcell countera_10
(
.aclr(aclr),
.cin(wire_countera_9cout[0:0]),
.clk(clock),
.combout(),
.cout(wire_countera_10cout[0:0]),
.dataa(power_modified_counter_values[9]),
.datab(power_modified_counter_values[10]),
.ena(1'b1),
.regout(wire_countera_regout[10:10]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_10.cin_used = "true",
countera_10.lut_mask = "6c50",
countera_10.operation_mode = "arithmetic",
countera_10.sum_lutc_input = "cin",
countera_10.synch_mode = "on",
countera_10.lpm_type = "cyclone_lcell";
cyclone_lcell countera_11
(
.aclr(aclr),
.cin(wire_countera_10cout[0:0]),
.clk(clock),
.combout(),
.cout(),
.dataa(power_modified_counter_values[11]),
.ena(1'b1),
.regout(wire_countera_regout[11:11]),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datab(1'b1),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
countera_11.cin_used = "true",
countera_11.lut_mask = "5a5a",
countera_11.operation_mode = "normal",
countera_11.sum_lutc_input = "cin",
countera_11.synch_mode = "on",
countera_11.lpm_type = "cyclone_lcell";
cyclone_lcell parity
(
.aclr(aclr),
.cin(updown),
.clk(clock),
.combout(),
.cout(wire_parity_cout),
.dataa(cnt_en),
.datab((~ wire_parity_regout)),
.ena(1'b1),
.regout(wire_parity_regout),
.sclr(sclr)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aload(1'b0),
.datac(1'b1),
.datad(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
parity.cin_used = "true",
parity.lut_mask = "9982",
parity.operation_mode = "arithmetic",
parity.synch_mode = "on",
parity.lpm_type = "cyclone_lcell";
assign
power_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])},
q = power_modified_counter_values,
sclr = 1'b0,
updown = 1'b1;
endmodule
|
module fifo_4k_altsyncram_8pl
(
address_a,
address_b,
clock0,
clock1,
clocken1,
data_a,
q_b,
wren_a) /* synthesis synthesis_clearbox=1 */;
input [11:0] address_a;
input [11:0] address_b;
input clock0;
input clock1;
input clocken1;
input [15:0] data_a;
output [15:0] q_b;
input wren_a;
wire [0:0] wire_ram_block3a_0portbdataout;
wire [0:0] wire_ram_block3a_1portbdataout;
wire [0:0] wire_ram_block3a_2portbdataout;
wire [0:0] wire_ram_block3a_3portbdataout;
wire [0:0] wire_ram_block3a_4portbdataout;
wire [0:0] wire_ram_block3a_5portbdataout;
wire [0:0] wire_ram_block3a_6portbdataout;
wire [0:0] wire_ram_block3a_7portbdataout;
wire [0:0] wire_ram_block3a_8portbdataout;
wire [0:0] wire_ram_block3a_9portbdataout;
wire [0:0] wire_ram_block3a_10portbdataout;
wire [0:0] wire_ram_block3a_11portbdataout;
wire [0:0] wire_ram_block3a_12portbdataout;
wire [0:0] wire_ram_block3a_13portbdataout;
wire [0:0] wire_ram_block3a_14portbdataout;
wire [0:0] wire_ram_block3a_15portbdataout;
wire [11:0] address_a_wire;
wire [11:0] address_b_wire;
cyclone_ram_block ram_block3a_0
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[0]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_0portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_0.connectivity_checking = "OFF",
ram_block3a_0.logical_ram_name = "ALTSYNCRAM",
ram_block3a_0.mixed_port_feed_through_mode = "dont_care",
ram_block3a_0.operation_mode = "dual_port",
ram_block3a_0.port_a_address_width = 12,
ram_block3a_0.port_a_data_width = 1,
ram_block3a_0.port_a_first_address = 0,
ram_block3a_0.port_a_first_bit_number = 0,
ram_block3a_0.port_a_last_address = 4095,
ram_block3a_0.port_a_logical_ram_depth = 4096,
ram_block3a_0.port_a_logical_ram_width = 16,
ram_block3a_0.port_b_address_clear = "none",
ram_block3a_0.port_b_address_clock = "clock1",
ram_block3a_0.port_b_address_width = 12,
ram_block3a_0.port_b_data_out_clear = "none",
ram_block3a_0.port_b_data_out_clock = "none",
ram_block3a_0.port_b_data_width = 1,
ram_block3a_0.port_b_first_address = 0,
ram_block3a_0.port_b_first_bit_number = 0,
ram_block3a_0.port_b_last_address = 4095,
ram_block3a_0.port_b_logical_ram_depth = 4096,
ram_block3a_0.port_b_logical_ram_width = 16,
ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_0.ram_block_type = "auto",
ram_block3a_0.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_1
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[1]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_1portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_1.connectivity_checking = "OFF",
ram_block3a_1.logical_ram_name = "ALTSYNCRAM",
ram_block3a_1.mixed_port_feed_through_mode = "dont_care",
ram_block3a_1.operation_mode = "dual_port",
ram_block3a_1.port_a_address_width = 12,
ram_block3a_1.port_a_data_width = 1,
ram_block3a_1.port_a_first_address = 0,
ram_block3a_1.port_a_first_bit_number = 1,
ram_block3a_1.port_a_last_address = 4095,
ram_block3a_1.port_a_logical_ram_depth = 4096,
ram_block3a_1.port_a_logical_ram_width = 16,
ram_block3a_1.port_b_address_clear = "none",
ram_block3a_1.port_b_address_clock = "clock1",
ram_block3a_1.port_b_address_width = 12,
ram_block3a_1.port_b_data_out_clear = "none",
ram_block3a_1.port_b_data_out_clock = "none",
ram_block3a_1.port_b_data_width = 1,
ram_block3a_1.port_b_first_address = 0,
ram_block3a_1.port_b_first_bit_number = 1,
ram_block3a_1.port_b_last_address = 4095,
ram_block3a_1.port_b_logical_ram_depth = 4096,
ram_block3a_1.port_b_logical_ram_width = 16,
ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_1.ram_block_type = "auto",
ram_block3a_1.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_2
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[2]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_2portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_2.connectivity_checking = "OFF",
ram_block3a_2.logical_ram_name = "ALTSYNCRAM",
ram_block3a_2.mixed_port_feed_through_mode = "dont_care",
ram_block3a_2.operation_mode = "dual_port",
ram_block3a_2.port_a_address_width = 12,
ram_block3a_2.port_a_data_width = 1,
ram_block3a_2.port_a_first_address = 0,
ram_block3a_2.port_a_first_bit_number = 2,
ram_block3a_2.port_a_last_address = 4095,
ram_block3a_2.port_a_logical_ram_depth = 4096,
ram_block3a_2.port_a_logical_ram_width = 16,
ram_block3a_2.port_b_address_clear = "none",
ram_block3a_2.port_b_address_clock = "clock1",
ram_block3a_2.port_b_address_width = 12,
ram_block3a_2.port_b_data_out_clear = "none",
ram_block3a_2.port_b_data_out_clock = "none",
ram_block3a_2.port_b_data_width = 1,
ram_block3a_2.port_b_first_address = 0,
ram_block3a_2.port_b_first_bit_number = 2,
ram_block3a_2.port_b_last_address = 4095,
ram_block3a_2.port_b_logical_ram_depth = 4096,
ram_block3a_2.port_b_logical_ram_width = 16,
ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_2.ram_block_type = "auto",
ram_block3a_2.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_3
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[3]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_3portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_3.connectivity_checking = "OFF",
ram_block3a_3.logical_ram_name = "ALTSYNCRAM",
ram_block3a_3.mixed_port_feed_through_mode = "dont_care",
ram_block3a_3.operation_mode = "dual_port",
ram_block3a_3.port_a_address_width = 12,
ram_block3a_3.port_a_data_width = 1,
ram_block3a_3.port_a_first_address = 0,
ram_block3a_3.port_a_first_bit_number = 3,
ram_block3a_3.port_a_last_address = 4095,
ram_block3a_3.port_a_logical_ram_depth = 4096,
ram_block3a_3.port_a_logical_ram_width = 16,
ram_block3a_3.port_b_address_clear = "none",
ram_block3a_3.port_b_address_clock = "clock1",
ram_block3a_3.port_b_address_width = 12,
ram_block3a_3.port_b_data_out_clear = "none",
ram_block3a_3.port_b_data_out_clock = "none",
ram_block3a_3.port_b_data_width = 1,
ram_block3a_3.port_b_first_address = 0,
ram_block3a_3.port_b_first_bit_number = 3,
ram_block3a_3.port_b_last_address = 4095,
ram_block3a_3.port_b_logical_ram_depth = 4096,
ram_block3a_3.port_b_logical_ram_width = 16,
ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_3.ram_block_type = "auto",
ram_block3a_3.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_4
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[4]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_4portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_4.connectivity_checking = "OFF",
ram_block3a_4.logical_ram_name = "ALTSYNCRAM",
ram_block3a_4.mixed_port_feed_through_mode = "dont_care",
ram_block3a_4.operation_mode = "dual_port",
ram_block3a_4.port_a_address_width = 12,
ram_block3a_4.port_a_data_width = 1,
ram_block3a_4.port_a_first_address = 0,
ram_block3a_4.port_a_first_bit_number = 4,
ram_block3a_4.port_a_last_address = 4095,
ram_block3a_4.port_a_logical_ram_depth = 4096,
ram_block3a_4.port_a_logical_ram_width = 16,
ram_block3a_4.port_b_address_clear = "none",
ram_block3a_4.port_b_address_clock = "clock1",
ram_block3a_4.port_b_address_width = 12,
ram_block3a_4.port_b_data_out_clear = "none",
ram_block3a_4.port_b_data_out_clock = "none",
ram_block3a_4.port_b_data_width = 1,
ram_block3a_4.port_b_first_address = 0,
ram_block3a_4.port_b_first_bit_number = 4,
ram_block3a_4.port_b_last_address = 4095,
ram_block3a_4.port_b_logical_ram_depth = 4096,
ram_block3a_4.port_b_logical_ram_width = 16,
ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_4.ram_block_type = "auto",
ram_block3a_4.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_5
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[5]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_5portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_5.connectivity_checking = "OFF",
ram_block3a_5.logical_ram_name = "ALTSYNCRAM",
ram_block3a_5.mixed_port_feed_through_mode = "dont_care",
ram_block3a_5.operation_mode = "dual_port",
ram_block3a_5.port_a_address_width = 12,
ram_block3a_5.port_a_data_width = 1,
ram_block3a_5.port_a_first_address = 0,
ram_block3a_5.port_a_first_bit_number = 5,
ram_block3a_5.port_a_last_address = 4095,
ram_block3a_5.port_a_logical_ram_depth = 4096,
ram_block3a_5.port_a_logical_ram_width = 16,
ram_block3a_5.port_b_address_clear = "none",
ram_block3a_5.port_b_address_clock = "clock1",
ram_block3a_5.port_b_address_width = 12,
ram_block3a_5.port_b_data_out_clear = "none",
ram_block3a_5.port_b_data_out_clock = "none",
ram_block3a_5.port_b_data_width = 1,
ram_block3a_5.port_b_first_address = 0,
ram_block3a_5.port_b_first_bit_number = 5,
ram_block3a_5.port_b_last_address = 4095,
ram_block3a_5.port_b_logical_ram_depth = 4096,
ram_block3a_5.port_b_logical_ram_width = 16,
ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_5.ram_block_type = "auto",
ram_block3a_5.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_6
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[6]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_6portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_6.connectivity_checking = "OFF",
ram_block3a_6.logical_ram_name = "ALTSYNCRAM",
ram_block3a_6.mixed_port_feed_through_mode = "dont_care",
ram_block3a_6.operation_mode = "dual_port",
ram_block3a_6.port_a_address_width = 12,
ram_block3a_6.port_a_data_width = 1,
ram_block3a_6.port_a_first_address = 0,
ram_block3a_6.port_a_first_bit_number = 6,
ram_block3a_6.port_a_last_address = 4095,
ram_block3a_6.port_a_logical_ram_depth = 4096,
ram_block3a_6.port_a_logical_ram_width = 16,
ram_block3a_6.port_b_address_clear = "none",
ram_block3a_6.port_b_address_clock = "clock1",
ram_block3a_6.port_b_address_width = 12,
ram_block3a_6.port_b_data_out_clear = "none",
ram_block3a_6.port_b_data_out_clock = "none",
ram_block3a_6.port_b_data_width = 1,
ram_block3a_6.port_b_first_address = 0,
ram_block3a_6.port_b_first_bit_number = 6,
ram_block3a_6.port_b_last_address = 4095,
ram_block3a_6.port_b_logical_ram_depth = 4096,
ram_block3a_6.port_b_logical_ram_width = 16,
ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_6.ram_block_type = "auto",
ram_block3a_6.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_7
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[7]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_7portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_7.connectivity_checking = "OFF",
ram_block3a_7.logical_ram_name = "ALTSYNCRAM",
ram_block3a_7.mixed_port_feed_through_mode = "dont_care",
ram_block3a_7.operation_mode = "dual_port",
ram_block3a_7.port_a_address_width = 12,
ram_block3a_7.port_a_data_width = 1,
ram_block3a_7.port_a_first_address = 0,
ram_block3a_7.port_a_first_bit_number = 7,
ram_block3a_7.port_a_last_address = 4095,
ram_block3a_7.port_a_logical_ram_depth = 4096,
ram_block3a_7.port_a_logical_ram_width = 16,
ram_block3a_7.port_b_address_clear = "none",
ram_block3a_7.port_b_address_clock = "clock1",
ram_block3a_7.port_b_address_width = 12,
ram_block3a_7.port_b_data_out_clear = "none",
ram_block3a_7.port_b_data_out_clock = "none",
ram_block3a_7.port_b_data_width = 1,
ram_block3a_7.port_b_first_address = 0,
ram_block3a_7.port_b_first_bit_number = 7,
ram_block3a_7.port_b_last_address = 4095,
ram_block3a_7.port_b_logical_ram_depth = 4096,
ram_block3a_7.port_b_logical_ram_width = 16,
ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_7.ram_block_type = "auto",
ram_block3a_7.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_8
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[8]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_8portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_8.connectivity_checking = "OFF",
ram_block3a_8.logical_ram_name = "ALTSYNCRAM",
ram_block3a_8.mixed_port_feed_through_mode = "dont_care",
ram_block3a_8.operation_mode = "dual_port",
ram_block3a_8.port_a_address_width = 12,
ram_block3a_8.port_a_data_width = 1,
ram_block3a_8.port_a_first_address = 0,
ram_block3a_8.port_a_first_bit_number = 8,
ram_block3a_8.port_a_last_address = 4095,
ram_block3a_8.port_a_logical_ram_depth = 4096,
ram_block3a_8.port_a_logical_ram_width = 16,
ram_block3a_8.port_b_address_clear = "none",
ram_block3a_8.port_b_address_clock = "clock1",
ram_block3a_8.port_b_address_width = 12,
ram_block3a_8.port_b_data_out_clear = "none",
ram_block3a_8.port_b_data_out_clock = "none",
ram_block3a_8.port_b_data_width = 1,
ram_block3a_8.port_b_first_address = 0,
ram_block3a_8.port_b_first_bit_number = 8,
ram_block3a_8.port_b_last_address = 4095,
ram_block3a_8.port_b_logical_ram_depth = 4096,
ram_block3a_8.port_b_logical_ram_width = 16,
ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_8.ram_block_type = "auto",
ram_block3a_8.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_9
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[9]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_9portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_9.connectivity_checking = "OFF",
ram_block3a_9.logical_ram_name = "ALTSYNCRAM",
ram_block3a_9.mixed_port_feed_through_mode = "dont_care",
ram_block3a_9.operation_mode = "dual_port",
ram_block3a_9.port_a_address_width = 12,
ram_block3a_9.port_a_data_width = 1,
ram_block3a_9.port_a_first_address = 0,
ram_block3a_9.port_a_first_bit_number = 9,
ram_block3a_9.port_a_last_address = 4095,
ram_block3a_9.port_a_logical_ram_depth = 4096,
ram_block3a_9.port_a_logical_ram_width = 16,
ram_block3a_9.port_b_address_clear = "none",
ram_block3a_9.port_b_address_clock = "clock1",
ram_block3a_9.port_b_address_width = 12,
ram_block3a_9.port_b_data_out_clear = "none",
ram_block3a_9.port_b_data_out_clock = "none",
ram_block3a_9.port_b_data_width = 1,
ram_block3a_9.port_b_first_address = 0,
ram_block3a_9.port_b_first_bit_number = 9,
ram_block3a_9.port_b_last_address = 4095,
ram_block3a_9.port_b_logical_ram_depth = 4096,
ram_block3a_9.port_b_logical_ram_width = 16,
ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_9.ram_block_type = "auto",
ram_block3a_9.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_10
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[10]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_10portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_10.connectivity_checking = "OFF",
ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
ram_block3a_10.operation_mode = "dual_port",
ram_block3a_10.port_a_address_width = 12,
ram_block3a_10.port_a_data_width = 1,
ram_block3a_10.port_a_first_address = 0,
ram_block3a_10.port_a_first_bit_number = 10,
ram_block3a_10.port_a_last_address = 4095,
ram_block3a_10.port_a_logical_ram_depth = 4096,
ram_block3a_10.port_a_logical_ram_width = 16,
ram_block3a_10.port_b_address_clear = "none",
ram_block3a_10.port_b_address_clock = "clock1",
ram_block3a_10.port_b_address_width = 12,
ram_block3a_10.port_b_data_out_clear = "none",
ram_block3a_10.port_b_data_out_clock = "none",
ram_block3a_10.port_b_data_width = 1,
ram_block3a_10.port_b_first_address = 0,
ram_block3a_10.port_b_first_bit_number = 10,
ram_block3a_10.port_b_last_address = 4095,
ram_block3a_10.port_b_logical_ram_depth = 4096,
ram_block3a_10.port_b_logical_ram_width = 16,
ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_10.ram_block_type = "auto",
ram_block3a_10.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_11
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[11]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_11portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_11.connectivity_checking = "OFF",
ram_block3a_11.logical_ram_name = "ALTSYNCRAM",
ram_block3a_11.mixed_port_feed_through_mode = "dont_care",
ram_block3a_11.operation_mode = "dual_port",
ram_block3a_11.port_a_address_width = 12,
ram_block3a_11.port_a_data_width = 1,
ram_block3a_11.port_a_first_address = 0,
ram_block3a_11.port_a_first_bit_number = 11,
ram_block3a_11.port_a_last_address = 4095,
ram_block3a_11.port_a_logical_ram_depth = 4096,
ram_block3a_11.port_a_logical_ram_width = 16,
ram_block3a_11.port_b_address_clear = "none",
ram_block3a_11.port_b_address_clock = "clock1",
ram_block3a_11.port_b_address_width = 12,
ram_block3a_11.port_b_data_out_clear = "none",
ram_block3a_11.port_b_data_out_clock = "none",
ram_block3a_11.port_b_data_width = 1,
ram_block3a_11.port_b_first_address = 0,
ram_block3a_11.port_b_first_bit_number = 11,
ram_block3a_11.port_b_last_address = 4095,
ram_block3a_11.port_b_logical_ram_depth = 4096,
ram_block3a_11.port_b_logical_ram_width = 16,
ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_11.ram_block_type = "auto",
ram_block3a_11.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_12
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[12]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_12portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_12.connectivity_checking = "OFF",
ram_block3a_12.logical_ram_name = "ALTSYNCRAM",
ram_block3a_12.mixed_port_feed_through_mode = "dont_care",
ram_block3a_12.operation_mode = "dual_port",
ram_block3a_12.port_a_address_width = 12,
ram_block3a_12.port_a_data_width = 1,
ram_block3a_12.port_a_first_address = 0,
ram_block3a_12.port_a_first_bit_number = 12,
ram_block3a_12.port_a_last_address = 4095,
ram_block3a_12.port_a_logical_ram_depth = 4096,
ram_block3a_12.port_a_logical_ram_width = 16,
ram_block3a_12.port_b_address_clear = "none",
ram_block3a_12.port_b_address_clock = "clock1",
ram_block3a_12.port_b_address_width = 12,
ram_block3a_12.port_b_data_out_clear = "none",
ram_block3a_12.port_b_data_out_clock = "none",
ram_block3a_12.port_b_data_width = 1,
ram_block3a_12.port_b_first_address = 0,
ram_block3a_12.port_b_first_bit_number = 12,
ram_block3a_12.port_b_last_address = 4095,
ram_block3a_12.port_b_logical_ram_depth = 4096,
ram_block3a_12.port_b_logical_ram_width = 16,
ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_12.ram_block_type = "auto",
ram_block3a_12.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_13
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[13]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_13portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_13.connectivity_checking = "OFF",
ram_block3a_13.logical_ram_name = "ALTSYNCRAM",
ram_block3a_13.mixed_port_feed_through_mode = "dont_care",
ram_block3a_13.operation_mode = "dual_port",
ram_block3a_13.port_a_address_width = 12,
ram_block3a_13.port_a_data_width = 1,
ram_block3a_13.port_a_first_address = 0,
ram_block3a_13.port_a_first_bit_number = 13,
ram_block3a_13.port_a_last_address = 4095,
ram_block3a_13.port_a_logical_ram_depth = 4096,
ram_block3a_13.port_a_logical_ram_width = 16,
ram_block3a_13.port_b_address_clear = "none",
ram_block3a_13.port_b_address_clock = "clock1",
ram_block3a_13.port_b_address_width = 12,
ram_block3a_13.port_b_data_out_clear = "none",
ram_block3a_13.port_b_data_out_clock = "none",
ram_block3a_13.port_b_data_width = 1,
ram_block3a_13.port_b_first_address = 0,
ram_block3a_13.port_b_first_bit_number = 13,
ram_block3a_13.port_b_last_address = 4095,
ram_block3a_13.port_b_logical_ram_depth = 4096,
ram_block3a_13.port_b_logical_ram_width = 16,
ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_13.ram_block_type = "auto",
ram_block3a_13.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_14
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[14]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_14portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_14.connectivity_checking = "OFF",
ram_block3a_14.logical_ram_name = "ALTSYNCRAM",
ram_block3a_14.mixed_port_feed_through_mode = "dont_care",
ram_block3a_14.operation_mode = "dual_port",
ram_block3a_14.port_a_address_width = 12,
ram_block3a_14.port_a_data_width = 1,
ram_block3a_14.port_a_first_address = 0,
ram_block3a_14.port_a_first_bit_number = 14,
ram_block3a_14.port_a_last_address = 4095,
ram_block3a_14.port_a_logical_ram_depth = 4096,
ram_block3a_14.port_a_logical_ram_width = 16,
ram_block3a_14.port_b_address_clear = "none",
ram_block3a_14.port_b_address_clock = "clock1",
ram_block3a_14.port_b_address_width = 12,
ram_block3a_14.port_b_data_out_clear = "none",
ram_block3a_14.port_b_data_out_clock = "none",
ram_block3a_14.port_b_data_width = 1,
ram_block3a_14.port_b_first_address = 0,
ram_block3a_14.port_b_first_bit_number = 14,
ram_block3a_14.port_b_last_address = 4095,
ram_block3a_14.port_b_logical_ram_depth = 4096,
ram_block3a_14.port_b_logical_ram_width = 16,
ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_14.ram_block_type = "auto",
ram_block3a_14.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block3a_15
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[15]}),
.portadataout(),
.portawe(1'b1),
.portbaddr({address_b_wire[11:0]}),
.portbdataout(wire_ram_block3a_15portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portabyteenamasks(1'b1),
.portbbyteenamasks(1'b1),
.portbdatain(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
ram_block3a_15.connectivity_checking = "OFF",
ram_block3a_15.logical_ram_name = "ALTSYNCRAM",
ram_block3a_15.mixed_port_feed_through_mode = "dont_care",
ram_block3a_15.operation_mode = "dual_port",
ram_block3a_15.port_a_address_width = 12,
ram_block3a_15.port_a_data_width = 1,
ram_block3a_15.port_a_first_address = 0,
ram_block3a_15.port_a_first_bit_number = 15,
ram_block3a_15.port_a_last_address = 4095,
ram_block3a_15.port_a_logical_ram_depth = 4096,
ram_block3a_15.port_a_logical_ram_width = 16,
ram_block3a_15.port_b_address_clear = "none",
ram_block3a_15.port_b_address_clock = "clock1",
ram_block3a_15.port_b_address_width = 12,
ram_block3a_15.port_b_data_out_clear = "none",
ram_block3a_15.port_b_data_out_clock = "none",
ram_block3a_15.port_b_data_width = 1,
ram_block3a_15.port_b_first_address = 0,
ram_block3a_15.port_b_first_bit_number = 15,
ram_block3a_15.port_b_last_address = 4095,
ram_block3a_15.port_b_logical_ram_depth = 4096,
ram_block3a_15.port_b_logical_ram_width = 16,
ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_15.ram_block_type = "auto",
ram_block3a_15.lpm_type = "cyclone_ram_block";
assign
address_a_wire = address_a,
address_b_wire = address_b,
q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
endmodule
|
module fifo_4k_dffpipe_bb3
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
input clock;
input clrn;
input [11:0] d;
output [11:0] q;
wire [11:0] wire_dffe4a_D;
reg [11:0] dffe4a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[0:0] <= 1'b1;
else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0;
else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0];
// synopsys translate_off
initial
dffe4a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[1:1] <= 1'b1;
else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0;
else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1];
// synopsys translate_off
initial
dffe4a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[2:2] <= 1'b1;
else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0;
else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2];
// synopsys translate_off
initial
dffe4a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[3:3] <= 1'b1;
else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0;
else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3];
// synopsys translate_off
initial
dffe4a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[4:4] <= 1'b1;
else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0;
else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4];
// synopsys translate_off
initial
dffe4a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[5:5] <= 1'b1;
else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0;
else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5];
// synopsys translate_off
initial
dffe4a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[6:6] <= 1'b1;
else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0;
else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6];
// synopsys translate_off
initial
dffe4a[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[7:7] <= 1'b1;
else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0;
else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7];
// synopsys translate_off
initial
dffe4a[8:8] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[8:8] <= 1'b1;
else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0;
else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8];
// synopsys translate_off
initial
dffe4a[9:9] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[9:9] <= 1'b1;
else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0;
else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9];
// synopsys translate_off
initial
dffe4a[10:10] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[10:10] <= 1'b1;
else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0;
else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10];
// synopsys translate_off
initial
dffe4a[11:11] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a[11:11] <= 1'b1;
else if (clrn == 1'b0) dffe4a[11:11] <= 1'b0;
else if (ena == 1'b1) dffe4a[11:11] <= wire_dffe4a_D[11:11];
assign
wire_dffe4a_D = (d & {12{(~ sclr)}});
assign
ena = 1'b1,
prn = 1'b1,
q = dffe4a,
sclr = 1'b0;
endmodule
|
module fifo_4k_dffpipe_em2
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
input clock;
input clrn;
input [11:0] d;
output [11:0] q;
wire [11:0] wire_dffe6a_D;
reg [11:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe6a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[0:0] <= 1'b1;
else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0;
else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0];
// synopsys translate_off
initial
dffe6a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[1:1] <= 1'b1;
else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0;
else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1];
// synopsys translate_off
initial
dffe6a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[2:2] <= 1'b1;
else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0;
else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2];
// synopsys translate_off
initial
dffe6a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[3:3] <= 1'b1;
else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0;
else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3];
// synopsys translate_off
initial
dffe6a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[4:4] <= 1'b1;
else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0;
else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4];
// synopsys translate_off
initial
dffe6a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[5:5] <= 1'b1;
else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0;
else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5];
// synopsys translate_off
initial
dffe6a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[6:6] <= 1'b1;
else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0;
else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6];
// synopsys translate_off
initial
dffe6a[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[7:7] <= 1'b1;
else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0;
else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7];
// synopsys translate_off
initial
dffe6a[8:8] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[8:8] <= 1'b1;
else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0;
else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8];
// synopsys translate_off
initial
dffe6a[9:9] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[9:9] <= 1'b1;
else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0;
else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9];
// synopsys translate_off
initial
dffe6a[10:10] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[10:10] <= 1'b1;
else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0;
else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10];
// synopsys translate_off
initial
dffe6a[11:11] = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a[11:11] <= 1'b1;
else if (clrn == 1'b0) dffe6a[11:11] <= 1'b0;
else if (ena == 1'b1) dffe6a[11:11] <= wire_dffe6a_D[11:11];
assign
wire_dffe6a_D = (d & {12{(~ sclr)}});
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule
|
module fifo_4k_alt_synch_pipe_em2
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
input clock;
input clrn;
input [11:0] d;
output [11:0] q;
wire [11:0] wire_dffpipe5_q;
fifo_4k_dffpipe_em2 dffpipe5
(
.clock(clock),
.clrn(clrn),
.d(d),
.q(wire_dffpipe5_q));
assign
q = wire_dffpipe5_q;
endmodule
|
module fifo_4k_add_sub_b18
(
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input [11:0] dataa;
input [11:0] datab;
output [11:0] result;
wire [11:0] wire_add_sub_cella_combout;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [0:0] wire_add_sub_cella_7cout;
wire [0:0] wire_add_sub_cella_8cout;
wire [0:0] wire_add_sub_cella_9cout;
wire [0:0] wire_add_sub_cella_10cout;
wire [11:0] wire_add_sub_cella_dataa;
wire [11:0] wire_add_sub_cella_datab;
cyclone_lcell add_sub_cella_0
(
.cin(1'b1),
.combout(wire_add_sub_cella_combout[0:0]),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "69b2",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_1
(
.cin(wire_add_sub_cella_0cout[0:0]),
.combout(wire_add_sub_cella_combout[1:1]),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "69b2",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_2
(
.cin(wire_add_sub_cella_1cout[0:0]),
.combout(wire_add_sub_cella_combout[2:2]),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "69b2",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_3
(
.cin(wire_add_sub_cella_2cout[0:0]),
.combout(wire_add_sub_cella_combout[3:3]),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "69b2",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_4
(
.cin(wire_add_sub_cella_3cout[0:0]),
.combout(wire_add_sub_cella_combout[4:4]),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "69b2",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_5
(
.cin(wire_add_sub_cella_4cout[0:0]),
.combout(wire_add_sub_cella_combout[5:5]),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "69b2",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_6
(
.cin(wire_add_sub_cella_5cout[0:0]),
.combout(wire_add_sub_cella_combout[6:6]),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "69b2",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_7
(
.cin(wire_add_sub_cella_6cout[0:0]),
.combout(wire_add_sub_cella_combout[7:7]),
.cout(wire_add_sub_cella_7cout[0:0]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "69b2",
add_sub_cella_7.operation_mode = "arithmetic",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_8
(
.cin(wire_add_sub_cella_7cout[0:0]),
.combout(wire_add_sub_cella_combout[8:8]),
.cout(wire_add_sub_cella_8cout[0:0]),
.dataa(wire_add_sub_cella_dataa[8:8]),
.datab(wire_add_sub_cella_datab[8:8]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_8.cin_used = "true",
add_sub_cella_8.lut_mask = "69b2",
add_sub_cella_8.operation_mode = "arithmetic",
add_sub_cella_8.sum_lutc_input = "cin",
add_sub_cella_8.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_9
(
.cin(wire_add_sub_cella_8cout[0:0]),
.combout(wire_add_sub_cella_combout[9:9]),
.cout(wire_add_sub_cella_9cout[0:0]),
.dataa(wire_add_sub_cella_dataa[9:9]),
.datab(wire_add_sub_cella_datab[9:9]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_9.cin_used = "true",
add_sub_cella_9.lut_mask = "69b2",
add_sub_cella_9.operation_mode = "arithmetic",
add_sub_cella_9.sum_lutc_input = "cin",
add_sub_cella_9.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_10
(
.cin(wire_add_sub_cella_9cout[0:0]),
.combout(wire_add_sub_cella_combout[10:10]),
.cout(wire_add_sub_cella_10cout[0:0]),
.dataa(wire_add_sub_cella_dataa[10:10]),
.datab(wire_add_sub_cella_datab[10:10]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_10.cin_used = "true",
add_sub_cella_10.lut_mask = "69b2",
add_sub_cella_10.operation_mode = "arithmetic",
add_sub_cella_10.sum_lutc_input = "cin",
add_sub_cella_10.lpm_type = "cyclone_lcell";
cyclone_lcell add_sub_cella_11
(
.cin(wire_add_sub_cella_10cout[0:0]),
.combout(wire_add_sub_cella_combout[11:11]),
.cout(),
.dataa(wire_add_sub_cella_dataa[11:11]),
.datab(wire_add_sub_cella_datab[11:11]),
.regout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.clk(1'b1),
.datac(1'b1),
.datad(1'b1),
.ena(1'b1),
.inverta(1'b0),
.regcascin(1'b0),
.sclr(1'b0),
.sload(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.cin0(),
.cin1(),
.cout0(),
.cout1(),
.devclrn(),
.devpor()
// synopsys translate_on
);
defparam
add_sub_cella_11.cin_used = "true",
add_sub_cella_11.lut_mask = "6969",
add_sub_cella_11.operation_mode = "normal",
add_sub_cella_11.sum_lutc_input = "cin",
add_sub_cella_11.lpm_type = "cyclone_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_combout;
endmodule
|
module fifo_4k_dcfifo_6cq
(
aclr,
data,
q,
rdclk,
rdempty,
rdreq,
rdusedw,
wrclk,
wrfull,
wrreq,
wrusedw) /* synthesis synthesis_clearbox=1 */
/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */;
input aclr;
input [15:0] data;
output [15:0] q;
input rdclk;
output rdempty;
input rdreq;
output [11:0] rdusedw;
input wrclk;
output wrfull;
input wrreq;
output [11:0] wrusedw;
wire [11:0] wire_rdptr_g_gray2bin_bin;
wire [11:0] wire_rs_dgwp_gray2bin_bin;
wire [11:0] wire_wrptr_g_gray2bin_bin;
wire [11:0] wire_ws_dgrp_gray2bin_bin;
wire [11:0] wire_rdptr_g_q;
wire [11:0] wire_rdptr_g1p_q;
wire [11:0] wire_wrptr_g1p_q;
wire [15:0] wire_fifo_ram_q_b;
reg [11:0] delayed_wrptr_g;
reg [11:0] wrptr_g;
wire [11:0] wire_rs_brp_q;
wire [11:0] wire_rs_bwp_q;
wire [11:0] wire_rs_dgwp_q;
wire [11:0] wire_ws_brp_q;
wire [11:0] wire_ws_bwp_q;
wire [11:0] wire_ws_dgrp_q;
wire [11:0] wire_rdusedw_sub_result;
wire [11:0] wire_wrusedw_sub_result;
reg wire_rdempty_eq_comp_aeb_int;
wire wire_rdempty_eq_comp_aeb;
wire [11:0] wire_rdempty_eq_comp_dataa;
wire [11:0] wire_rdempty_eq_comp_datab;
reg wire_wrfull_eq_comp_aeb_int;
wire wire_wrfull_eq_comp_aeb;
wire [11:0] wire_wrfull_eq_comp_dataa;
wire [11:0] wire_wrfull_eq_comp_datab;
wire int_rdempty;
wire int_wrfull;
wire valid_rdreq;
wire valid_wrreq;
fifo_4k_a_gray2bin_9m4 rdptr_g_gray2bin
(
.bin(wire_rdptr_g_gray2bin_bin),
.gray(wire_rdptr_g_q));
fifo_4k_a_gray2bin_9m4 rs_dgwp_gray2bin
(
.bin(wire_rs_dgwp_gray2bin_bin),
.gray(wire_rs_dgwp_q));
fifo_4k_a_gray2bin_9m4 wrptr_g_gray2bin
(
.bin(wire_wrptr_g_gray2bin_bin),
.gray(wrptr_g));
fifo_4k_a_gray2bin_9m4 ws_dgrp_gray2bin
(
.bin(wire_ws_dgrp_gray2bin_bin),
.gray(wire_ws_dgrp_q));
fifo_4k_a_graycounter_826 rdptr_g
(
.aclr(aclr),
.clock(rdclk),
.cnt_en(valid_rdreq),
.q(wire_rdptr_g_q));
fifo_4k_a_graycounter_3r6 rdptr_g1p
(
.aclr(aclr),
.clock(rdclk),
.cnt_en(valid_rdreq),
.q(wire_rdptr_g1p_q));
fifo_4k_a_graycounter_3r6 wrptr_g1p
(
.aclr(aclr),
.clock(wrclk),
.cnt_en(valid_wrreq),
.q(wire_wrptr_g1p_q));
fifo_4k_altsyncram_8pl fifo_ram
(
.address_a(wrptr_g),
.address_b(((wire_rdptr_g_q & {12{int_rdempty}}) | (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))),
.clock0(wrclk),
.clock1(rdclk),
.clocken1((valid_rdreq | int_rdempty)),
.data_a(data),
.q_b(wire_fifo_ram_q_b),
.wren_a(valid_wrreq));
// synopsys translate_off
initial
delayed_wrptr_g = 0;
// synopsys translate_on
always @ ( posedge wrclk or posedge aclr)
if (aclr == 1'b1) delayed_wrptr_g <= 12'b0;
else delayed_wrptr_g <= wrptr_g;
// synopsys translate_off
initial
wrptr_g = 0;
// synopsys translate_on
always @ ( posedge wrclk or posedge aclr)
if (aclr == 1'b1) wrptr_g <= 12'b0;
else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q;
fifo_4k_dffpipe_bb3 rs_brp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(wire_rdptr_g_gray2bin_bin),
.q(wire_rs_brp_q));
fifo_4k_dffpipe_bb3 rs_bwp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(wire_rs_dgwp_gray2bin_bin),
.q(wire_rs_bwp_q));
fifo_4k_alt_synch_pipe_em2 rs_dgwp
(
.clock(rdclk),
.clrn((~ aclr)),
.d(delayed_wrptr_g),
.q(wire_rs_dgwp_q));
fifo_4k_dffpipe_bb3 ws_brp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_ws_dgrp_gray2bin_bin),
.q(wire_ws_brp_q));
fifo_4k_dffpipe_bb3 ws_bwp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_wrptr_g_gray2bin_bin),
.q(wire_ws_bwp_q));
fifo_4k_alt_synch_pipe_em2 ws_dgrp
(
.clock(wrclk),
.clrn((~ aclr)),
.d(wire_rdptr_g_q),
.q(wire_ws_dgrp_q));
fifo_4k_add_sub_b18 rdusedw_sub
(
.dataa(wire_rs_bwp_q),
.datab(wire_rs_brp_q),
.result(wire_rdusedw_sub_result));
fifo_4k_add_sub_b18 wrusedw_sub
(
.dataa(wire_ws_bwp_q),
.datab(wire_ws_brp_q),
.result(wire_wrusedw_sub_result));
always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab)
begin
wire_rdempty_eq_comp_aeb_int = 1'b1;
end
else
begin
wire_rdempty_eq_comp_aeb_int = 1'b0;
end
assign
wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
assign
wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
wire_rdempty_eq_comp_datab = wire_rdptr_g_q;
always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab)
begin
wire_wrfull_eq_comp_aeb_int = 1'b1;
end
else
begin
wire_wrfull_eq_comp_aeb_int = 1'b0;
end
assign
wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
assign
wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
assign
int_rdempty = wire_rdempty_eq_comp_aeb,
int_wrfull = wire_wrfull_eq_comp_aeb,
q = wire_fifo_ram_q_b,
rdempty = int_rdempty,
rdusedw = wire_rdusedw_sub_result,
valid_rdreq = rdreq,
valid_wrreq = wrreq,
wrfull = int_wrfull,
wrusedw = wire_wrusedw_sub_result;
endmodule
|
module fifo_4k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
wire sub_wire0;
wire [11:0] sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire [11:0] sub_wire4;
wire rdempty = sub_wire0;
wire [11:0] wrusedw = sub_wire1[11:0];
wire wrfull = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire [11:0] rdusedw = sub_wire4[11:0];
fifo_4k_dcfifo_6cq fifo_4k_dcfifo_6cq_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4));
endmodule
|
module serial_io
( input master_clk,
input serial_clock,
input serial_data_in,
input enable,
input reset,
inout wire serial_data_out,
output reg [6:0] serial_addr,
output reg [31:0] serial_data,
output wire serial_strobe,
input wire [31:0] readback_0,
input wire [31:0] readback_1,
input wire [31:0] readback_2,
input wire [31:0] readback_3,
input wire [31:0] readback_4,
input wire [31:0] readback_5,
input wire [31:0] readback_6,
input wire [31:0] readback_7
);
reg is_read;
reg [7:0] ser_ctr;
reg write_done;
assign serial_data_out = is_read ? serial_data[31] : 1'bz;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
ser_ctr <= #1 8'd0;
else if(~enable)
ser_ctr <= #1 8'd0;
else if(ser_ctr == 39)
ser_ctr <= #1 8'd0;
else
ser_ctr <= #1 ser_ctr + 8'd1;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
is_read <= #1 1'b0;
else if(~enable)
is_read <= #1 1'b0;
else if((ser_ctr == 7)&&(serial_addr[6]==1))
is_read <= #1 1'b1;
always @(posedge serial_clock, posedge reset)
if(reset)
begin
serial_addr <= #1 7'b0;
serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else if(~enable)
begin
//serial_addr <= #1 7'b0;
//serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else
begin
if(~is_read && (ser_ctr == 39))
write_done <= #1 1'b1;
else
write_done <= #1 1'b0;
if(is_read & (ser_ctr==8))
case (serial_addr)
7'd1: serial_data <= #1 readback_0;
7'd2: serial_data <= #1 readback_1;
7'd3: serial_data <= #1 readback_2;
7'd4: serial_data <= #1 readback_3;
7'd5: serial_data <= #1 readback_4;
7'd6: serial_data <= #1 readback_5;
7'd7: serial_data <= #1 readback_6;
7'd8: serial_data <= #1 readback_7;
default: serial_data <= #1 32'd0;
endcase // case(serial_addr)
else if(ser_ctr >= 8)
serial_data <= #1 {serial_data[30:0],serial_data_in};
else if(ser_ctr < 8)
serial_addr <= #1 {serial_addr[5:0],serial_data_in};
end // else: !if(~enable)
reg enable_d1, enable_d2;
always @(posedge master_clk)
begin
enable_d1 <= #1 enable;
enable_d2 <= #1 enable_d1;
end
assign serial_strobe = enable_d2 & ~enable_d1;
endmodule
|
module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
parameter bitwidth = 16;
parameter zwidth = 16;
parameter shift = 1;
input clock;
input reset;
input enable;
input [bitwidth-1:0] xi,yi;
input [zwidth-1:0] zi;
input [zwidth-1:0] constant;
output [bitwidth-1:0] xo,yo;
output [zwidth-1:0] zo;
wire z_is_pos = ~zi[zwidth-1];
reg [bitwidth-1:0] xo,yo;
reg [zwidth-1:0] zo;
always @(posedge clock)
if(reset)
begin
xo <= #1 0;
yo <= #1 0;
zo <= #1 0;
end
else if(enable)
begin
xo <= #1 z_is_pos ?
xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} :
xi + {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]};
yo <= #1 z_is_pos ?
yi + {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]} :
yi - {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]};
zo <= #1 z_is_pos ?
zi - constant :
zi + constant;
end
endmodule
|
module axi_crossbar_v2_1_wdata_router #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of all data signals
parameter integer C_NUM_MASTER_SLOTS = 1, // Number of M_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of S_ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_WMESG_WIDTH-1:0] S_WMESG,
input wire S_WLAST,
input wire S_WVALID,
output wire S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG, // Broadcast to all MI-slots
output wire M_WLAST, // Broadcast to all MI-slots
output wire [C_NUM_MASTER_SLOTS-1:0] M_WVALID, // Per MI-slot
input wire [C_NUM_MASTER_SLOTS-1:0] M_WREADY, // Per MI-slot
// Address Arbiter Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // Target MI-slot index from SI-side AW command
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_MASTER_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_MASTER_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
//---------------------------------------------------------------------------
// Internal signal declarations
//---------------------------------------------------------------------------
wire [C_NUM_MASTER_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
//---------------------------------------------------------------------------
// Router
//---------------------------------------------------------------------------
// SI-side write command queue
axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (1)
)
wrouter_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// W-channel payload and LAST are broadcast to all MI-slot's W-mux
assign M_WMESG = S_WMESG;
assign M_WLAST = S_WLAST;
// Assert m_aready when last beat acknowledged by slave
assign m_aready = m_avalid & S_WVALID & S_WLAST & (|(M_WREADY & m_select_hot));
// M_WVALID is generated per MI-slot (including error handler at slot C_NUM_MASTER_SLOTS).
// The slot selected by the head of the queue (m_select_enc) is enabled.
assign M_WVALID = {C_NUM_MASTER_SLOTS{S_WVALID & m_avalid}} & m_select_hot;
// S_WREADY is muxed from the MI slot selected by the head of the queue (m_select_enc).
assign S_WREADY = m_avalid & (|(M_WREADY & m_select_hot));
endmodule
|
module axi_crossbar_v2_1_wdata_router #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of all data signals
parameter integer C_NUM_MASTER_SLOTS = 1, // Number of M_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of S_ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_WMESG_WIDTH-1:0] S_WMESG,
input wire S_WLAST,
input wire S_WVALID,
output wire S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG, // Broadcast to all MI-slots
output wire M_WLAST, // Broadcast to all MI-slots
output wire [C_NUM_MASTER_SLOTS-1:0] M_WVALID, // Per MI-slot
input wire [C_NUM_MASTER_SLOTS-1:0] M_WREADY, // Per MI-slot
// Address Arbiter Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // Target MI-slot index from SI-side AW command
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_MASTER_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_MASTER_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
//---------------------------------------------------------------------------
// Internal signal declarations
//---------------------------------------------------------------------------
wire [C_NUM_MASTER_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
//---------------------------------------------------------------------------
// Router
//---------------------------------------------------------------------------
// SI-side write command queue
axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (1)
)
wrouter_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// W-channel payload and LAST are broadcast to all MI-slot's W-mux
assign M_WMESG = S_WMESG;
assign M_WLAST = S_WLAST;
// Assert m_aready when last beat acknowledged by slave
assign m_aready = m_avalid & S_WVALID & S_WLAST & (|(M_WREADY & m_select_hot));
// M_WVALID is generated per MI-slot (including error handler at slot C_NUM_MASTER_SLOTS).
// The slot selected by the head of the queue (m_select_enc) is enabled.
assign M_WVALID = {C_NUM_MASTER_SLOTS{S_WVALID & m_avalid}} & m_select_hot;
// S_WREADY is muxed from the MI slot selected by the head of the queue (m_select_enc).
assign S_WREADY = m_avalid & (|(M_WREADY & m_select_hot));
endmodule
|
module mac (input clock, input reset, input enable, input clear,
input signed [15:0] x, input signed [15:0] y,
input [7:0] shift, output [15:0] z );
reg signed [30:0] product;
reg signed [39:0] z_int;
reg signed [15:0] z_shift;
reg enable_d1;
always @(posedge clock)
enable_d1 <= #1 enable;
always @(posedge clock)
if(reset | clear)
z_int <= #1 40'd0;
else if(enable_d1)
z_int <= #1 z_int + {{9{product[30]}},product};
always @(posedge clock)
product <= #1 x*y;
always @* // FIXME full case? parallel case?
case(shift)
//8'd0 : z_shift <= z_int[39:24];
//8'd1 : z_shift <= z_int[38:23];
//8'd2 : z_shift <= z_int[37:22];
//8'd3 : z_shift <= z_int[36:21];
//8'd4 : z_shift <= z_int[35:20];
//8'd5 : z_shift <= z_int[34:19];
8'd6 : z_shift <= z_int[33:18];
8'd7 : z_shift <= z_int[32:17];
8'd8 : z_shift <= z_int[31:16];
8'd9 : z_shift <= z_int[30:15];
8'd10 : z_shift <= z_int[29:14];
8'd11 : z_shift <= z_int[28:13];
//8'd12 : z_shift <= z_int[27:12];
//8'd13 : z_shift <= z_int[26:11];
//8'd14 : z_shift <= z_int[25:10];
//8'd15 : z_shift <= z_int[24:9];
//8'd16 : z_shift <= z_int[23:8];
//8'd17 : z_shift <= z_int[22:7];
//8'd18 : z_shift <= z_int[21:6];
//8'd19 : z_shift <= z_int[20:5];
//8'd20 : z_shift <= z_int[19:4];
//8'd21 : z_shift <= z_int[18:3];
//8'd22 : z_shift <= z_int[17:2];
//8'd23 : z_shift <= z_int[16:1];
//8'd24 : z_shift <= z_int[15:0];
default : z_shift <= z_int[15:0];
endcase // case(shift)
// FIXME do we need to saturate?
//assign z = z_shift;
assign z = z_int[15:0];
endmodule
|
module mac (input clock, input reset, input enable, input clear,
input signed [15:0] x, input signed [15:0] y,
input [7:0] shift, output [15:0] z );
reg signed [30:0] product;
reg signed [39:0] z_int;
reg signed [15:0] z_shift;
reg enable_d1;
always @(posedge clock)
enable_d1 <= #1 enable;
always @(posedge clock)
if(reset | clear)
z_int <= #1 40'd0;
else if(enable_d1)
z_int <= #1 z_int + {{9{product[30]}},product};
always @(posedge clock)
product <= #1 x*y;
always @* // FIXME full case? parallel case?
case(shift)
//8'd0 : z_shift <= z_int[39:24];
//8'd1 : z_shift <= z_int[38:23];
//8'd2 : z_shift <= z_int[37:22];
//8'd3 : z_shift <= z_int[36:21];
//8'd4 : z_shift <= z_int[35:20];
//8'd5 : z_shift <= z_int[34:19];
8'd6 : z_shift <= z_int[33:18];
8'd7 : z_shift <= z_int[32:17];
8'd8 : z_shift <= z_int[31:16];
8'd9 : z_shift <= z_int[30:15];
8'd10 : z_shift <= z_int[29:14];
8'd11 : z_shift <= z_int[28:13];
//8'd12 : z_shift <= z_int[27:12];
//8'd13 : z_shift <= z_int[26:11];
//8'd14 : z_shift <= z_int[25:10];
//8'd15 : z_shift <= z_int[24:9];
//8'd16 : z_shift <= z_int[23:8];
//8'd17 : z_shift <= z_int[22:7];
//8'd18 : z_shift <= z_int[21:6];
//8'd19 : z_shift <= z_int[20:5];
//8'd20 : z_shift <= z_int[19:4];
//8'd21 : z_shift <= z_int[18:3];
//8'd22 : z_shift <= z_int[17:2];
//8'd23 : z_shift <= z_int[16:1];
//8'd24 : z_shift <= z_int[15:0];
default : z_shift <= z_int[15:0];
endcase // case(shift)
// FIXME do we need to saturate?
//assign z = z_shift;
assign z = z_int[15:0];
endmodule
|
module mac (input clock, input reset, input enable, input clear,
input signed [15:0] x, input signed [15:0] y,
input [7:0] shift, output [15:0] z );
reg signed [30:0] product;
reg signed [39:0] z_int;
reg signed [15:0] z_shift;
reg enable_d1;
always @(posedge clock)
enable_d1 <= #1 enable;
always @(posedge clock)
if(reset | clear)
z_int <= #1 40'd0;
else if(enable_d1)
z_int <= #1 z_int + {{9{product[30]}},product};
always @(posedge clock)
product <= #1 x*y;
always @* // FIXME full case? parallel case?
case(shift)
//8'd0 : z_shift <= z_int[39:24];
//8'd1 : z_shift <= z_int[38:23];
//8'd2 : z_shift <= z_int[37:22];
//8'd3 : z_shift <= z_int[36:21];
//8'd4 : z_shift <= z_int[35:20];
//8'd5 : z_shift <= z_int[34:19];
8'd6 : z_shift <= z_int[33:18];
8'd7 : z_shift <= z_int[32:17];
8'd8 : z_shift <= z_int[31:16];
8'd9 : z_shift <= z_int[30:15];
8'd10 : z_shift <= z_int[29:14];
8'd11 : z_shift <= z_int[28:13];
//8'd12 : z_shift <= z_int[27:12];
//8'd13 : z_shift <= z_int[26:11];
//8'd14 : z_shift <= z_int[25:10];
//8'd15 : z_shift <= z_int[24:9];
//8'd16 : z_shift <= z_int[23:8];
//8'd17 : z_shift <= z_int[22:7];
//8'd18 : z_shift <= z_int[21:6];
//8'd19 : z_shift <= z_int[20:5];
//8'd20 : z_shift <= z_int[19:4];
//8'd21 : z_shift <= z_int[18:3];
//8'd22 : z_shift <= z_int[17:2];
//8'd23 : z_shift <= z_int[16:1];
//8'd24 : z_shift <= z_int[15:0];
default : z_shift <= z_int[15:0];
endcase // case(shift)
// FIXME do we need to saturate?
//assign z = z_shift;
assign z = z_int[15:0];
endmodule
|
module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr);
parameter depth = 4;
parameter width = 16;
parameter size = 16;
input wclk;
input [width-1:0] wdata;
input [depth-1:0] waddr;
input wen;
input rclk;
output reg [width-1:0] rdata;
input [depth-1:0] raddr;
reg [width-1:0] ram [0:size-1];
always @(posedge wclk)
if(wen)
ram[waddr] <= #1 wdata;
always @(posedge rclk)
rdata <= #1 ram[raddr];
endmodule
|
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
endmodule
|
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
endmodule
|
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
endmodule
|
module clk_doubler (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.activeclock (),
.areset (),
.clkbad (),
.clkena (),
.clkloss (),
.clkswitch (),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena (),
.fbin (),
.locked (),
.pfdena (),
.pllena (),
.scanaclr (),
.scanclk (),
.scandata (),
.scandataout (),
.scandone (),
.scanread (),
.scanwrite (),
.sclkout0 (),
.sclkout1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 2,
altpll_component.inclk0_input_frequency = 15625,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "0";
endmodule
|
module fifo_2k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [10:0] rdusedw;
output wrfull;
output [10:0] wrusedw;
endmodule
|
module fifo_4k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
endmodule
|
module fifo_4k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
endmodule
|
module tx_chain_hb
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input hb_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debug, output [15:0] hb_i_out
);
assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe};
wire [15:0] bb_i, bb_q;
wire [15:0] hb_i_out, hb_q_out;
halfband_interp hb
(.clock(clock),.reset(reset),.enable(enable),
.strobe_in(interpolator_strobe),.strobe_out(hb_strobe),
.signal_in_i(i_in),.signal_in_q(q_in),
.signal_out_i(hb_i_out),.signal_out_q(hb_q_out),
.debug(debug[12:0]));
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_i_out),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_q_out),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule
|
module ddr3_int_example_top (
// inputs:
clock_source,
global_reset_n,
// outputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
pnf,
pnf_per_byte,
test_complete,
test_status
)
;
output [ 12: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 3: 0] mem_dm;
inout [ 31: 0] mem_dq;
inout [ 3: 0] mem_dqs;
inout [ 3: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output pnf;
output [ 15: 0] pnf_per_byte;
output test_complete;
output [ 7: 0] test_status;
input clock_source;
input global_reset_n;
wire [ 0: 0] cs_n;
wire dll_reference_clk_sig;
wire [ 5: 0] dqs_delay_ctrl_export_sig;
wire local_burstbegin_sig;
wire [ 12: 0] mem_addr;
wire mem_aux_full_rate_clk;
wire mem_aux_half_rate_clk;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 3: 0] mem_dm;
wire [ 31: 0] mem_dq;
wire [ 3: 0] mem_dqs;
wire [ 3: 0] mem_dqsn;
wire [ 23: 0] mem_local_addr;
wire [ 15: 0] mem_local_be;
wire [ 9: 0] mem_local_col_addr;
wire mem_local_cs_addr;
wire [127: 0] mem_local_rdata;
wire mem_local_rdata_valid;
wire mem_local_read_req;
wire mem_local_ready;
wire [ 5: 0] mem_local_size;
wire [127: 0] mem_local_wdata;
wire mem_local_write_req;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pnf;
wire [ 15: 0] pnf_per_byte;
wire reset_phy_clk_n;
wire test_complete;
wire [ 7: 0] test_status;
wire tie_high;
wire tie_low;
//
//
assign mem_cs_n = cs_n;
//<< END MEGAWIZARD INSERT MODULE
assign tie_high = 1'b1;
assign tie_low = 1'b0;
//<< START MEGAWIZARD INSERT WRAPPER_NAME
ddr3_int ddr3_int_inst
(
.aux_full_rate_clk (mem_aux_full_rate_clk),
.aux_half_rate_clk (mem_aux_half_rate_clk),
.dll_reference_clk (dll_reference_clk_sig),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export_sig),
.global_reset_n (global_reset_n),
.local_address (mem_local_addr),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_init_done (),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_refresh_ack (),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_wdata_req (),
.local_write_req (mem_local_write_req),
.mem_addr (mem_addr[12 : 0]),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (cs_n),
.mem_dm (mem_dm[3 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[3 : 0]),
.mem_dqsn (mem_dqsn[3 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.phy_clk (phy_clk),
.pll_ref_clk (clock_source),
.reset_phy_clk_n (reset_phy_clk_n),
.reset_request_n (),
.soft_reset_n (tie_high)
);
//<< END MEGAWIZARD INSERT WRAPPER_NAME
//<< START MEGAWIZARD INSERT CS_ADDR_MAP
//connect up the column address bits, dropping 2 bits from example driver output because of 4:1 data rate
assign mem_local_addr[7 : 0] = mem_local_col_addr[9 : 2];
//<< END MEGAWIZARD INSERT CS_ADDR_MAP
//<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
//Self-test, synthesisable code to exercise the DDR SDRAM Controller
ddr3_int_example_driver driver
(
.clk (phy_clk),
.local_bank_addr (mem_local_addr[23 : 21]),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_col_addr (mem_local_col_addr),
.local_cs_addr (mem_local_cs_addr),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_row_addr (mem_local_addr[20 : 8]),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.pnf_per_byte (pnf_per_byte[15 : 0]),
.pnf_persist (pnf),
.reset_n (reset_phy_clk_n),
.test_complete (test_complete),
.test_status (test_status)
);
//<< END MEGAWIZARD INSERT EXAMPLE_DRIVER
//<< START MEGAWIZARD INSERT DLL
//<< END MEGAWIZARD INSERT DLL
//<< START MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< END MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< start europa
endmodule
|
module ddr3_int_example_top (
// inputs:
clock_source,
global_reset_n,
// outputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
pnf,
pnf_per_byte,
test_complete,
test_status
)
;
output [ 12: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 3: 0] mem_dm;
inout [ 31: 0] mem_dq;
inout [ 3: 0] mem_dqs;
inout [ 3: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output pnf;
output [ 15: 0] pnf_per_byte;
output test_complete;
output [ 7: 0] test_status;
input clock_source;
input global_reset_n;
wire [ 0: 0] cs_n;
wire dll_reference_clk_sig;
wire [ 5: 0] dqs_delay_ctrl_export_sig;
wire local_burstbegin_sig;
wire [ 12: 0] mem_addr;
wire mem_aux_full_rate_clk;
wire mem_aux_half_rate_clk;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 3: 0] mem_dm;
wire [ 31: 0] mem_dq;
wire [ 3: 0] mem_dqs;
wire [ 3: 0] mem_dqsn;
wire [ 23: 0] mem_local_addr;
wire [ 15: 0] mem_local_be;
wire [ 9: 0] mem_local_col_addr;
wire mem_local_cs_addr;
wire [127: 0] mem_local_rdata;
wire mem_local_rdata_valid;
wire mem_local_read_req;
wire mem_local_ready;
wire [ 5: 0] mem_local_size;
wire [127: 0] mem_local_wdata;
wire mem_local_write_req;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pnf;
wire [ 15: 0] pnf_per_byte;
wire reset_phy_clk_n;
wire test_complete;
wire [ 7: 0] test_status;
wire tie_high;
wire tie_low;
//
//
assign mem_cs_n = cs_n;
//<< END MEGAWIZARD INSERT MODULE
assign tie_high = 1'b1;
assign tie_low = 1'b0;
//<< START MEGAWIZARD INSERT WRAPPER_NAME
ddr3_int ddr3_int_inst
(
.aux_full_rate_clk (mem_aux_full_rate_clk),
.aux_half_rate_clk (mem_aux_half_rate_clk),
.dll_reference_clk (dll_reference_clk_sig),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export_sig),
.global_reset_n (global_reset_n),
.local_address (mem_local_addr),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_init_done (),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_refresh_ack (),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_wdata_req (),
.local_write_req (mem_local_write_req),
.mem_addr (mem_addr[12 : 0]),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (cs_n),
.mem_dm (mem_dm[3 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[3 : 0]),
.mem_dqsn (mem_dqsn[3 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.phy_clk (phy_clk),
.pll_ref_clk (clock_source),
.reset_phy_clk_n (reset_phy_clk_n),
.reset_request_n (),
.soft_reset_n (tie_high)
);
//<< END MEGAWIZARD INSERT WRAPPER_NAME
//<< START MEGAWIZARD INSERT CS_ADDR_MAP
//connect up the column address bits, dropping 2 bits from example driver output because of 4:1 data rate
assign mem_local_addr[7 : 0] = mem_local_col_addr[9 : 2];
//<< END MEGAWIZARD INSERT CS_ADDR_MAP
//<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
//Self-test, synthesisable code to exercise the DDR SDRAM Controller
ddr3_int_example_driver driver
(
.clk (phy_clk),
.local_bank_addr (mem_local_addr[23 : 21]),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_col_addr (mem_local_col_addr),
.local_cs_addr (mem_local_cs_addr),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_row_addr (mem_local_addr[20 : 8]),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.pnf_per_byte (pnf_per_byte[15 : 0]),
.pnf_persist (pnf),
.reset_n (reset_phy_clk_n),
.test_complete (test_complete),
.test_status (test_status)
);
//<< END MEGAWIZARD INSERT EXAMPLE_DRIVER
//<< START MEGAWIZARD INSERT DLL
//<< END MEGAWIZARD INSERT DLL
//<< START MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< END MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< start europa
endmodule
|
module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);
reg [7:0] counter;
// FIXME maybe should use PLL or switch to double edge version
always @(posedge in_clk or posedge reset)
if(reset)
counter <= #1 8'd0;
else if(counter == 0)
counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
else
counter <= #1 counter-8'd1;
always @(posedge in_clk or posedge reset)
if(reset)
out_clk <= #1 1'b0;
else if(counter == 0)
out_clk <= #1 ~out_clk;
endmodule
|
module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);
reg [7:0] counter;
// FIXME maybe should use PLL or switch to double edge version
always @(posedge in_clk or posedge reset)
if(reset)
counter <= #1 8'd0;
else if(counter == 0)
counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
else
counter <= #1 counter-8'd1;
always @(posedge in_clk or posedge reset)
if(reset)
out_clk <= #1 1'b0;
else if(counter == 0)
out_clk <= #1 ~out_clk;
endmodule
|
module cic_decim
( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
parameter bw = 16;
parameter N = 4;
parameter log2_of_max_rate = 7;
parameter maxbitgain = N * log2_of_max_rate;
input clock;
input reset;
input enable;
input [7:0] rate;
input strobe_in,strobe_out;
input [bw-1:0] signal_in;
output [bw-1:0] signal_out;
reg [bw-1:0] signal_out;
wire [bw-1:0] signal_out_unreg;
wire [bw+maxbitgain-1:0] signal_in_ext;
reg [bw+maxbitgain-1:0] integrator [0:N-1];
reg [bw+maxbitgain-1:0] differentiator [0:N-1];
reg [bw+maxbitgain-1:0] pipeline [0:N-1];
reg [bw+maxbitgain-1:0] sampler;
integer i;
sign_extend #(bw,bw+maxbitgain)
ext_input (.in(signal_in),.out(signal_in_ext));
always @(posedge clock)
if(reset)
for(i=0;i<N;i=i+1)
integrator[i] <= #1 0;
else if (enable && strobe_in)
begin
integrator[0] <= #1 integrator[0] + signal_in_ext;
for(i=1;i<N;i=i+1)
integrator[i] <= #1 integrator[i] + integrator[i-1];
end
always @(posedge clock)
if(reset)
begin
sampler <= #1 0;
for(i=0;i<N;i=i+1)
begin
pipeline[i] <= #1 0;
differentiator[i] <= #1 0;
end
end
else if (enable && strobe_out)
begin
sampler <= #1 integrator[N-1];
differentiator[0] <= #1 sampler;
pipeline[0] <= #1 sampler - differentiator[0];
for(i=1;i<N;i=i+1)
begin
differentiator[i] <= #1 pipeline[i-1];
pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
end
end // if (enable && strobe_out)
wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1];
cic_dec_shifter #(bw)
cic_dec_shifter(rate,signal_out_unnorm,signal_out_unreg);
always @(posedge clock)
signal_out <= #1 signal_out_unreg;
endmodule
|
module clk_doubler (
inclk0,
c0);
input inclk0;
output c0;
endmodule
|
module clk_doubler (
inclk0,
c0);
input inclk0;
output c0;
endmodule
|
module clk_doubler (
inclk0,
c0);
input inclk0;
output c0;
endmodule
|
module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 4096;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output wrempty;
output [7:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [7:0] rdusedw;
reg [7:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
endmodule
|
module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 4096;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output wrempty;
output [7:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [7:0] rdusedw;
reg [7:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
endmodule
|
module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 4096;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output wrempty;
output [7:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [7:0] rdusedw;
reg [7:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
endmodule
|
module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used);
parameter width=32;
parameter depth=10;
input reset; // Asynchronous
input [width-1:0] data;
input write;
input wrclk;
output [depth-1:0] wr_used;
output [width-1:0] q;
input read_ack;
input rdclk;
output [depth-1:0] rd_used;
reg [depth-1:0] read_addr, write_addr,
read_addr_gray, read_addr_gray_sync,
write_addr_gray, write_addr_gray_sync;
// Pseudo-dual-port RAM
dpram #(.depth(10),.width(width),.size(1024))
fifo_ram (.wclk(wrclk),.wdata(data),.waddr(write_addr),.wen(write),
.rclk(rdclk), .rdata(q),.raddr(read_addr) );
wire [depth-1:0] wag,rag;
// Keep track of own side's pointer
always @(posedge wrclk or posedge reset)
if(reset) write_addr <= #1 0;
else if(write) write_addr <= #1 write_addr + 1;
always @(posedge rdclk or posedge reset)
if(reset) read_addr <= #1 0;
else if(read_ack) read_addr <= #1 read_addr + 1;
// Convert own side pointer to gray
bin2gray #(depth) write_b2g (write_addr,wag);
bin2gray #(depth) read_b2g (read_addr,rag);
// Latch it
always @(posedge wrclk or posedge reset)
if(reset) write_addr_gray <= #1 0;
else write_addr_gray <= #1 wag;
always @(posedge rdclk or posedge reset)
if(reset) read_addr_gray <= #1 0;
else read_addr_gray <= #1 rag;
// Send it to other side and latch
always @(posedge wrclk or posedge reset)
if(reset) read_addr_gray_sync <= #1 0;
else read_addr_gray_sync <= #1 read_addr_gray;
always @(posedge rdclk or posedge reset)
if(reset) write_addr_gray_sync <= #1 0;
else write_addr_gray_sync <= #1 write_addr_gray;
wire [depth-1:0] write_addr_sync, read_addr_sync;
// Convert back to binary
gray2bin #(depth) write_g2b (write_addr_gray_sync, write_addr_sync);
gray2bin #(depth) read_g2b (read_addr_gray_sync, read_addr_sync);
assign rd_used = write_addr_sync - read_addr;
assign wr_used = write_addr - read_addr_sync;
endmodule
|
module bin2gray(bin_val,gray_val);
parameter width = 8;
input [width-1:0] bin_val;
output reg [width-1:0] gray_val;
integer i;
always @*
begin
gray_val[width-1] = bin_val[width-1];
for(i=0;i<width-1;i=i+1)
gray_val[i] = bin_val[i] ^ bin_val[i+1];
end
endmodule
|
module gray2bin(gray_val,bin_val);
parameter width = 8;
input [width-1:0] gray_val;
output reg [width-1:0] bin_val;
integer i;
always @*
begin
bin_val[width-1] = gray_val[width-1];
for(i=width-2;i>=0;i=i-1)
bin_val[i] = bin_val[i+1] ^ gray_val[i];
end
endmodule
|
module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used);
parameter width=32;
parameter depth=10;
input reset; // Asynchronous
input [width-1:0] data;
input write;
input wrclk;
output [depth-1:0] wr_used;
output [width-1:0] q;
input read_ack;
input rdclk;
output [depth-1:0] rd_used;
reg [depth-1:0] read_addr, write_addr,
read_addr_gray, read_addr_gray_sync,
write_addr_gray, write_addr_gray_sync;
// Pseudo-dual-port RAM
dpram #(.depth(10),.width(width),.size(1024))
fifo_ram (.wclk(wrclk),.wdata(data),.waddr(write_addr),.wen(write),
.rclk(rdclk), .rdata(q),.raddr(read_addr) );
wire [depth-1:0] wag,rag;
// Keep track of own side's pointer
always @(posedge wrclk or posedge reset)
if(reset) write_addr <= #1 0;
else if(write) write_addr <= #1 write_addr + 1;
always @(posedge rdclk or posedge reset)
if(reset) read_addr <= #1 0;
else if(read_ack) read_addr <= #1 read_addr + 1;
// Convert own side pointer to gray
bin2gray #(depth) write_b2g (write_addr,wag);
bin2gray #(depth) read_b2g (read_addr,rag);
// Latch it
always @(posedge wrclk or posedge reset)
if(reset) write_addr_gray <= #1 0;
else write_addr_gray <= #1 wag;
always @(posedge rdclk or posedge reset)
if(reset) read_addr_gray <= #1 0;
else read_addr_gray <= #1 rag;
// Send it to other side and latch
always @(posedge wrclk or posedge reset)
if(reset) read_addr_gray_sync <= #1 0;
else read_addr_gray_sync <= #1 read_addr_gray;
always @(posedge rdclk or posedge reset)
if(reset) write_addr_gray_sync <= #1 0;
else write_addr_gray_sync <= #1 write_addr_gray;
wire [depth-1:0] write_addr_sync, read_addr_sync;
// Convert back to binary
gray2bin #(depth) write_g2b (write_addr_gray_sync, write_addr_sync);
gray2bin #(depth) read_g2b (read_addr_gray_sync, read_addr_sync);
assign rd_used = write_addr_sync - read_addr;
assign wr_used = write_addr - read_addr_sync;
endmodule
|
module bin2gray(bin_val,gray_val);
parameter width = 8;
input [width-1:0] bin_val;
output reg [width-1:0] gray_val;
integer i;
always @*
begin
gray_val[width-1] = bin_val[width-1];
for(i=0;i<width-1;i=i+1)
gray_val[i] = bin_val[i] ^ bin_val[i+1];
end
endmodule
|
module gray2bin(gray_val,bin_val);
parameter width = 8;
input [width-1:0] gray_val;
output reg [width-1:0] bin_val;
integer i;
always @*
begin
bin_val[width-1] = gray_val[width-1];
for(i=width-2;i>=0;i=i-1)
bin_val[i] = bin_val[i+1] ^ gray_val[i];
end
endmodule
|
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