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--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: DAQ_MEM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY DAQ_MEM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE DAQ_MEM_synth_ARCH OF DAQ_MEM_synth IS
COMPONENT DAQ_MEM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(10 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(10 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 14,
READ_WIDTH => 7 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: DAQ_MEM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
use work.config.all;
library unisim;
use unisim.vcomponents.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk48 : in std_ulogic;
errorn : out std_logic;
-- DDR SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n: inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
dsuact : out std_ulogic; -- Debug Unit break (connect to button)
-- AHB UART (debug link)
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- SD card
sd_dat : inout std_logic;
sd_cmd : inout std_logic;
sd_sck : inout std_logic;
sd_dat3 : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal clk200 : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal cgo_ddr : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal lclk, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 48000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk48_pad : clkpad generic map (tech => padtech) port map (clk48, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_DDR2 = 1) generate
clkgen_ddr : clkgen
generic map (fabtech, 25, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clk200, open, open, open, open, cgi, cgo_ddr, open, open, open);
ddrc : entity work.ahb2mig_ztex generic map(
hindex => 4, haddr => 16#400#, hmask => CFG_MIG_HMASK,
pindex => 5, paddr => 5)
port map(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(5),
calib_done => lock,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem => clk200,
test_error => open
);
end generate;
noddr : if CFG_MIG_DDR2 = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- General purpose timer unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
-- NOTE:
-- GPIO pads are not instantiated here. If you want to use
-- GPIO then add a top-level port, update the UCF and
-- instantiate pads for the GPIO lines as is done in other
-- template designs.
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => CFG_SPICTRL_ODMODE,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
miso_pad : iopad generic map (tech => padtech)
port map (sd_dat, spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (sd_sck, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (sd_dat3, slvsel(0));
spii.spisel <= '1'; -- Master only
end generate spic;
nospic: if CFG_SPICTRL_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for ZTEX USB-FPGA Module 1.15",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
-- Units present in this block (refer to DP schematic):
-- adder1
-- adder2
-- jreg_mux21
-- concatenate16
-- oprnd1_mux41
-- oprnd2_mux41
-- regaddr_mux21
-- forwarding unit
-- alusrc_mux21
-- ALU
-- plus4_adder
-- branch_circ
-- PSW
-- link_mux21
-- lhi_mux21
-- movs2i_mux21
entity execute is
port(
clk : in std_logic;
rst : in std_logic;
-- inputs from IDEX pipeline reg
controls_in : in std_logic_vector(21 downto 0); -- we have 22 signals: CU generates a total of 23 signals (including 5 ALUOP signals), but 1 signal (unsigned) is already exhausted in the DECODE stage
ext25_0 : in std_logic_vector(31 downto 0); -- bits 25_0 of instr. sign/unsign extended to 32 bits
nextPC : in std_logic_vector(31 downto 0);
op_A : in std_logic_vector(31 downto 0);
op_B : in std_logic_vector(31 downto 0);
ext15_0 : in std_logic_vector(31 downto 0); -- bits 15_0 of instr. sign/unsign extended to 32 bits
inst15_0 : in std_logic_vector(15 downto 0); -- bits 15_0 of instr.
rt_inst : in std_logic_vector(4 downto 0);
rd_inst : in std_logic_vector(4 downto 0);
rs_inst : in std_logic_vector(4 downto 0);
-- inputs from other sources
unaligned : in std_logic; -- from MMU, '1' when an unaligned access to memory has been done
forw_dataWB : in std_logic_vector(31 downto 0); -- data from WB stage that is used if forwarding needed
forw_dataMEM : in std_logic_vector(31 downto 0); -- data from MEM stage that is used if forwarding needed
RFaddr_WB : in std_logic_vector(4 downto 0); -- addr of RF from WB stage, goes to forwarding unit
RFaddr_MEM : in std_logic_vector(4 downto 0); -- addr of RF from MEM stage, goes to forwarding unit
regwriteWB : in std_logic; -- reg_write ctrl signal from WB stage
regwriteMEM : in std_logic; -- reg_write ctrl signal from MEM stage
-- outputs
controls_out : out std_logic_vector(10 downto 0); -- 11 control signals go to MEM stage (11 are exhausted in the EXE stage)
toPC1 : out std_logic_vector(31 downto 0);
toPC2 : out std_logic_vector(31 downto 0);
branchTaken : out std_logic;
addrMem : out std_logic_vector(31 downto 0);
writeData : out std_logic_vector(31 downto 0);
addrRF : out std_logic_vector(4 downto 0);
IDEX_rt : out std_logic_vector(4 downto 0); -- goes to hazard unit
IDEX_memread : out std_logic_vector(3 downto 0) -- goes to hazard unit
);
end execute;
architecture rtl of execute is
-- component declarations
component adder is
port(
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
res : out std_logic_vector(31 downto 0)
);
end component;
component ALU is
port(
-- inputs
alu_op : in std_logic_vector(4 downto 0); -- specifies alu operation to be performed (from CU in ID stage)
a : in std_logic_vector(31 downto 0); -- operand 1
b : in std_logic_vector(31 downto 0); -- operand 2
-- outputs
-- cout : out std_logic; -- cout of operation; to PSW
ovf : out std_logic; -- ovf of operation; to PSW
zero : out std_logic; -- zero when res is all 0s; to branch_circ
res : out std_logic_vector(31 downto 0) -- result of the arit-log operation on a and b
);
end component;
component branch_circ is
port(
branch_type : in std_logic; -- BNEZ is branch_type = '1', BEQZ is branch_type = '0'
zero : in std_logic; -- from ALU, 1 when the result of an operation yields zero
branch_taken : out std_logic -- 1 means the branch has to be taken
);
end component;
component concat16 is
port(
string16 : in std_logic_vector(15 downto 0);
string32 : out std_logic_vector(31 downto 0) -- this goes to lhi_mux21
);
end component;
component forward is
port(
rt_addr_IDEX : in std_logic_vector(4 downto 0);
rs_addr_IDEX : in std_logic_vector(4 downto 0);
rd_addr_EXMEM : in std_logic_vector(4 downto 0);
rd_addr_MEMWB : in std_logic_vector(4 downto 0);
regwrite_EXMEM : in std_logic;
regwrite_MEMWB : in std_logic;
forwardA : out std_logic_vector(1 downto 0); -- 00 from regfile, 01 from memwb, 10 from previous alu result
forwardB : out std_logic_vector(1 downto 0) -- as above
);
end component;
component mux21 is
generic(
NBIT : integer := 32
);
port (
a : in std_logic_vector(NBIT - 1 downto 0);
b : in std_logic_vector(NBIT - 1 downto 0);
s : in std_logic;
y : out std_logic_vector(NBIT - 1 downto 0)
);
end component;
component mux41 is
generic(
NBIT : integer := 32
);
port (
a : in std_logic_vector(NBIT - 1 downto 0);
b : in std_logic_vector(NBIT - 1 downto 0);
c : in std_logic_vector(NBIT - 1 downto 0);
s : in std_logic_vector(1 downto 0);
y : out std_logic_vector(NBIT - 1 downto 0)
);
end component;
component PSWreg is
port(
-- inputs
rst : in std_logic;
clk : in std_logic;
unaligned : in std_logic;
-- cout : in std_logic;
ovf : in std_logic;
-- outputs
status : out std_logic_vector(31 downto 0)
);
end component;
--signal declarations
signal lhi_value_i : std_logic_vector(31 downto 0); -- inst15_0 ## 0...0 for lhi instruction
signal zero_i : std_logic; -- driven by ALU: '0' when result of ALU operation is all 0s
signal psw_status_i : std_logic_vector(31 downto 0); -- content of PSW reg
signal ovf_i : std_logic; -- driven by ALU: '1' when operation had overflow
signal A_inALU_i : std_logic_vector(31 downto 0);
signal B_inALU_i : std_logic_vector(31 downto 0);
signal res_outALU_i : std_logic_vector(31 downto 0);
signal resAdd1_i : std_logic_vector(31 downto 0);
signal link_value_i : std_logic_vector(31 downto 0);
signal link2lhi_wire_i : std_logic_vector(31 downto 0); -- goes from link mux to lhi mux
signal lhi2mov_wire_i : std_logic_vector(31 downto 0); -- goes from lhi mux to movs2i mux
signal mux41B_wire_i : std_logic_vector(31 downto 0); -- goes from oprnd2_mux41 to alusrc_mux
signal forwardA_i : std_logic_vector(1 downto 0);
signal forwardB_i : std_logic_vector(1 downto 0);
begin
-- concurrent signal assignments
controls_out <= controls_in(21) & controls_in(18) & controls_in (13 downto 5); --- regwrite, link, sb, sw, lbu, lw, lhu, lb, memtoreg, jump, branch
writeData <= mux41B_wire_i; -- data that goes into Data Ram for writing
IDEX_rt <= rt_inst;
IDEX_memread <= controls_in(11 downto 8);
--component instantiations
adder1 : adder port map (ext25_0, nextPC, resAdd1_i);
adder2 : adder port map (nextPC, ext15_0, toPC2);
plus4_adder : adder port map(nextPC, X"00000004", link_value_i);
jreg_mux21 : mux21 generic map (32) port map (A_inALU_i, resAdd1_i, controls_in(20),toPC1);
link_mux21 : mux21 generic map (32) port map (link_value_i, res_outALU_i, controls_in(18), link2lhi_wire_i);
lhi_mux21 : mux21 generic map (32) port map (lhi_value_i, link2lhi_wire_i,controls_in(17), lhi2mov_wire_i);
regaddr_mux21 : mux21 generic map (5) port map (rd_inst, rt_inst, controls_in(16), addrRF);
movs2i_mux21 : mux21 generic map (32) port map (psw_status_i, lhi2mov_wire_i, controls_in(15), addrMem);
alusrc_mux21 : mux21 generic map (32) port map (ext15_0, mux41B_wire_i, controls_in(14), B_inALU_i);
oprnd1_mux41 : mux41 generic map (32) port map (op_A, forw_dataWB, forw_dataMEM, forwardA_i, A_inALU_i);
oprnd2_mux41 : mux41 generic map (32) port map (op_B, forw_dataWB, forw_dataMEM, forwardB_i, mux41B_wire_i);
concatenate16 : concat16 port map (inst15_0, lhi_value_i);
forwarding_unit : forward port map (rt_inst, rs_inst, RFaddr_MEM, RFaddr_WB, regwriteMEM, regwriteWB, forwardA_i, forwardB_i);
branch_circuit : branch_circ port map (controls_in(19), zero_i, branchTaken);
PSW : PSWreg port map (rst, clk, unaligned, ovf_i, psw_status_i);
EXALU : ALU port map (controls_in(4 downto 0), A_inALU_i, B_inALU_i, ovf_i, zero_i, res_outALU_i);
end rtl;
|
-------------------------------------------------------------------------------
--
-- The Decoder unit.
-- It decodes the instruction opcodes and executes them.
--
-- $Id: decoder-c.vhd,v 1.3 2008-04-29 21:19:21 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t48_decoder_rtl_c0 of t48_decoder is
for rtl
for int_b: t48_int
use configuration work.t48_int_rtl_c0;
end for;
end for;
end t48_decoder_rtl_c0;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity piso_tb is
end entity;
architecture behav of piso_tb is
component piso is
port (
clk : in std_logic;
se : in std_logic_vector(1 downto 0);
D : in std_logic_vector(3 downto 0);
Din : in std_logic;
Q : out std_logic :='0'
);
end component;
for piso_0 : piso use entity work.piso;
signal clk, Din, Q : std_logic :='0';
signal D : std_logic_vector(3 downto 0);
signal se : std_logic_vector(1 downto 0);
constant period : time := 10 ns;
begin
piso_0 : piso port map (clk=>clk, se=>se, D=>D, Din=>Din, Q=>Q);
clk_process:
process
begin
clk <= not clk;
wait for period/2;
end process;
stim_proc:
process
begin
D<="1101";
se<="01";
wait for 5 ns;
se<="10";
wait for 50 ns;
se<="01";
wait for 10 ns;
Din<='1';
se<="10";
wait for 80 ns;
wait ;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- dlmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v2_10_b;
use lmb_bram_if_cntlr_v2_10_b.all;
entity dlmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31)
);
attribute x_core_info : STRING;
attribute x_core_info of dlmb_cntlr_wrapper : entity is "lmb_bram_if_cntlr_v2_10_b";
end dlmb_cntlr_wrapper;
architecture STRUCTURE of dlmb_cntlr_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_MASK : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to (C_LMB_DWIDTH/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1)
);
end component;
begin
dlmb_cntlr : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00007fff",
C_MASK => X"80000000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A
);
end architecture STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity intra_prediction_core is
port(
clk : in std_logic;
rst : in std_logic;
--interface to enable "set samples" command
sample_data : in std_logic_vector(31 downto 0);
sample_write_addr : in unsigned(7 downto 0);
sample_write_enable : in std_logic;
--interface to enable "perform prediction" command
block_size : in unsigned(7 downto 0);
mode : in unsigned(7 downto 0);
row_addr : in unsigned(7 downto 0);
availible_mask : in std_logic_vector(31 downto 0);
row_data : out unsigned(127 downto 0)
);
end entity intra_prediction_core;
architecture rtl of intra_prediction_core is
constant dc_default : unsigned := "0000000010000000";
type row is array(15 downto 0) of unsigned(7 downto 0);
type macroblock_type is array (15 downto 0) of row;
signal macroblock : macroblock_type;
type sample_reg is array(8 downto 0) of std_logic_vector(31 downto 0);
signal samples_d, samples_q : sample_reg;
type samples_type is array(32 downto 0) of std_logic_vector(7 downto 0);
signal the_samples : samples_type;
type sample_array_row is array(16 downto 0) of unsigned(9 downto 0);
type sample_array_type is array(16 downto 0) of sample_array_row;
signal sample_array : sample_array_type;
signal dc_4_value : unsigned(15 downto 0);
signal dc_8_value : unsigned(15 downto 0);
signal dc_16_value : unsigned(15 downto 0);
signal dc_value : unsigned(9 downto 0);
type plane_value_row_type is array(16 downto 0) of signed(33 downto 0);
type plane_value_array_type is array(16 downto 0) of plane_value_row_type;
type plane_hv_type is array(7 downto 0) of signed(17 downto 0);
signal h,v : plane_hv_type;
signal a,b,c : signed(25 downto 0);
begin
--register file for holding sample data
reg_file: process(clk, rst) begin
if rst = '1' then
samples_q <= (others => (others => '0'));
elsif rising_edge(clk) then
samples_q <= samples_d;
end if;
end process;
reg_file_update: for i in 8 downto 0 generate
samples_d(i) <= sample_data when sample_write_enable = '1' and i = to_integer(unsigned(sample_write_addr))
else samples_q(i);
end generate;
--place neighbor samples into sample array
-- y\x-->
-- | \ |<--0--->| |<--1--->| |<--2--->| |<--3--->| |<-4->|
-- | \ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
-- | \___________________________________________________
--___ V 0 |0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
-- 1 |17 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 5 2 |18 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 3 |19 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
--___ 4 |20 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 5 |21 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 6 6 |22 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 7 |23 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
--___ 8 |24 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 9 |25 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 7 10 |26 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 11 |27 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
--___ 12 |28 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 13 |29 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 8 14 |30 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 15 |31 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
--___ 16 |32 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
the_samples(0) <= samples_q(0)(31 downto 24);
the_samples(1) <= samples_q(0)(23 downto 16);
the_samples(2) <= samples_q(0)(15 downto 8 );
the_samples(3) <= samples_q(0)(7 downto 0 );
the_samples(4) <= samples_q(1)(31 downto 24);
the_samples(5) <= samples_q(1)(23 downto 16);
the_samples(6) <= samples_q(1)(15 downto 8 );
the_samples(7) <= samples_q(1)(7 downto 0 );
the_samples(8) <= samples_q(2)(31 downto 24);
the_samples(9) <= samples_q(2)(23 downto 16);
the_samples(10) <= samples_q(2)(15 downto 8 );
the_samples(11) <= samples_q(2)(7 downto 0 );
the_samples(12) <= samples_q(3)(31 downto 24);
the_samples(13) <= samples_q(3)(23 downto 16);
the_samples(14) <= samples_q(3)(15 downto 8 );
the_samples(15) <= samples_q(3)(7 downto 0 );
the_samples(16) <= samples_q(4)(7 downto 0 );
the_samples(17) <= samples_q(5)(31 downto 24);
the_samples(18) <= samples_q(5)(23 downto 16);
the_samples(19) <= samples_q(5)(15 downto 8 );
the_samples(20) <= samples_q(5)(7 downto 0 );
the_samples(21) <= samples_q(6)(31 downto 24);
the_samples(22) <= samples_q(6)(23 downto 16);
the_samples(23) <= samples_q(6)(15 downto 8 );
the_samples(24) <= samples_q(6)(7 downto 0 );
the_samples(25) <= samples_q(7)(31 downto 24);
the_samples(26) <= samples_q(7)(23 downto 16);
the_samples(27) <= samples_q(7)(15 downto 8 );
the_samples(28) <= samples_q(7)(7 downto 0 );
the_samples(29) <= samples_q(8)(31 downto 24);
the_samples(30) <= samples_q(8)(23 downto 16);
the_samples(31) <= samples_q(8)(15 downto 8 );
the_samples(32) <= samples_q(8)(7 downto 0 );
sample_array( 0 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 0 )));
sample_array( 0 )( 1 ) <= unsigned(std_logic_vector'("00"&the_samples( 1 )));
sample_array( 0 )( 2 ) <= unsigned(std_logic_vector'("00"&the_samples( 2 )));
sample_array( 0 )( 3 ) <= unsigned(std_logic_vector'("00"&the_samples( 3 )));
sample_array( 0 )( 4 ) <= unsigned(std_logic_vector'("00"&the_samples( 4 )));
sample_array( 0 )( 5 ) <= unsigned(std_logic_vector'("00"&the_samples( 5 )));
sample_array( 0 )( 6 ) <= unsigned(std_logic_vector'("00"&the_samples( 6 )));
sample_array( 0 )( 7 ) <= unsigned(std_logic_vector'("00"&the_samples( 7 )));
sample_array( 0 )( 8 ) <= unsigned(std_logic_vector'("00"&the_samples( 8 )));
sample_array( 0 )( 9 ) <= unsigned(std_logic_vector'("00"&the_samples( 9 )));
sample_array( 0 )( 10 ) <= unsigned(std_logic_vector'("00"&the_samples( 10 )));
sample_array( 0 )( 11 ) <= unsigned(std_logic_vector'("00"&the_samples( 11 )));
sample_array( 0 )( 12 ) <= unsigned(std_logic_vector'("00"&the_samples( 12 )));
sample_array( 0 )( 13 ) <= unsigned(std_logic_vector'("00"&the_samples( 13 )));
sample_array( 0 )( 14 ) <= unsigned(std_logic_vector'("00"&the_samples( 14 )));
sample_array( 0 )( 15 ) <= unsigned(std_logic_vector'("00"&the_samples( 15 )));
sample_array( 0 )( 16 ) <= unsigned(std_logic_vector'("00"&the_samples( 16 )));
sample_array( 1 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 17 )));
sample_array( 2 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 18 )));
sample_array( 3 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 19 )));
sample_array( 4 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 20 )));
sample_array( 5 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 21 )));
sample_array( 6 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 22 )));
sample_array( 7 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 23 )));
sample_array( 8 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 24 )));
sample_array( 9 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 25 )));
sample_array( 10 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 26 )));
sample_array( 11 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 27 )));
sample_array( 12 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 28 )));
sample_array( 13 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 29 )));
sample_array( 14 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 30 )));
sample_array( 15 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 31 )));
sample_array( 16 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 32 )));
--calculate dc values
dc_4_value <= shift_right(("000000"&sample_array(1)(0)) +
("000000"&sample_array(2)(0)) +
("000000"&sample_array(3)(0)) +
("000000"&sample_array(4)(0)) +
("000000"&sample_array(0)(1)) +
("000000"&sample_array(0)(2)) +
("000000"&sample_array(0)(3)) +
("000000"&sample_array(0)(4)) +
to_unsigned(4, 16), 3) when (and_reduce(availible_mask(31 downto 28)) and
and_reduce(availible_mask(15 downto 12))) = '1' else
shift_right(("000000"&sample_array(1)(0)) +
("000000"&sample_array(2)(0)) +
("000000"&sample_array(3)(0)) +
("000000"&sample_array(4)(0)) +
to_unsigned(2, 16), 2) when and_reduce(availible_mask(31 downto 28)) = '1' else
shift_right(("000000"&sample_array(0)(1)) +
("000000"&sample_array(0)(2)) +
("000000"&sample_array(0)(3)) +
("000000"&sample_array(0)(4)) +
to_unsigned(2, 16), 2) when and_reduce(availible_mask(15 downto 12)) = '1' else
dc_default;
--dc_8_value <= shift_right(("000000"&sample_array(1)(0)) +
-- ("000000"&sample_array(2)(0)) +
-- ("000000"&sample_array(3)(0)) +
-- ("000000"&sample_array(4)(0)) +
-- ("000000"&sample_array(5)(0)) +
-- ("000000"&sample_array(6)(0)) +
-- ("000000"&sample_array(7)(0)) +
-- ("000000"&sample_array(8)(0)) +
-- ("000000"&sample_array(0)(1)) +
-- ("000000"&sample_array(0)(2)) +
-- ("000000"&sample_array(0)(3)) +
-- ("000000"&sample_array(0)(4)) +
-- ("000000"&sample_array(0)(5)) +
-- ("000000"&sample_array(0)(6)) +
-- ("000000"&sample_array(0)(7)) +
-- ("000000"&sample_array(0)(8)) +
-- to_unsigned(8, 16), 4) when (and_reduce(availible_mask(31 downto 24)) and
-- and_reduce(availible_mask(15 downto 8))) = '1' else
-- shift_right(("000000"&sample_array(1)(0)) +
-- ("000000"&sample_array(2)(0)) +
-- ("000000"&sample_array(3)(0)) +
-- ("000000"&sample_array(4)(0)) +
-- ("000000"&sample_array(4)(0)) +
-- ("000000"&sample_array(5)(0)) +
-- ("000000"&sample_array(6)(0)) +
-- ("000000"&sample_array(7)(0)) +
-- ("000000"&sample_array(8)(0)) +
-- to_unsigned(4, 16), 3) when and_reduce(availible_mask(31 downto 24)) = '1' else
-- shift_right(("000000"&sample_array(0)(1)) +
-- ("000000"&sample_array(0)(2)) +
-- ("000000"&sample_array(0)(3)) +
-- ("000000"&sample_array(0)(4)) +
-- ("000000"&sample_array(0)(4)) +
-- ("000000"&sample_array(0)(5)) +
-- ("000000"&sample_array(0)(6)) +
-- ("000000"&sample_array(0)(7)) +
-- ("000000"&sample_array(0)(8)) +
-- to_unsigned(4, 16), 3) when and_reduce(availible_mask(15 downto 8)) = '1' else
-- dc_default;
dc_16_value <= shift_right(("000000"&sample_array(1 )(0)) +
("000000"&sample_array(2 )(0)) +
("000000"&sample_array(3 )(0)) +
("000000"&sample_array(4 )(0)) +
("000000"&sample_array(5 )(0)) +
("000000"&sample_array(6 )(0)) +
("000000"&sample_array(7 )(0)) +
("000000"&sample_array(8 )(0)) +
("000000"&sample_array(9 )(0)) +
("000000"&sample_array(10)(0)) +
("000000"&sample_array(11)(0)) +
("000000"&sample_array(12)(0)) +
("000000"&sample_array(13)(0)) +
("000000"&sample_array(14)(0)) +
("000000"&sample_array(15)(0)) +
("000000"&sample_array(16)(0)) +
("000000"&sample_array(0)(1 )) +
("000000"&sample_array(0)(2 )) +
("000000"&sample_array(0)(3 )) +
("000000"&sample_array(0)(4 )) +
("000000"&sample_array(0)(5 )) +
("000000"&sample_array(0)(6 )) +
("000000"&sample_array(0)(7 )) +
("000000"&sample_array(0)(8 )) +
("000000"&sample_array(0)(9 )) +
("000000"&sample_array(0)(10)) +
("000000"&sample_array(0)(11)) +
("000000"&sample_array(0)(12)) +
("000000"&sample_array(0)(13)) +
("000000"&sample_array(0)(14)) +
("000000"&sample_array(0)(15)) +
("000000"&sample_array(0)(16)) +
to_unsigned(16, 16), 5) when and_reduce(availible_mask(31 downto 0)) = '1' else
shift_right(("000000"&sample_array(1 )(0)) +
("000000"&sample_array(2 )(0)) +
("000000"&sample_array(3 )(0)) +
("000000"&sample_array(4 )(0)) +
("000000"&sample_array(5 )(0)) +
("000000"&sample_array(6 )(0)) +
("000000"&sample_array(7 )(0)) +
("000000"&sample_array(8 )(0)) +
("000000"&sample_array(9 )(0)) +
("000000"&sample_array(10)(0)) +
("000000"&sample_array(11)(0)) +
("000000"&sample_array(12)(0)) +
("000000"&sample_array(13)(0)) +
("000000"&sample_array(14)(0)) +
("000000"&sample_array(15)(0)) +
("000000"&sample_array(16)(0)) +
to_unsigned(8, 16), 4) when and_reduce(availible_mask(31 downto 16)) = '1' else
shift_right(("000000"&sample_array(0)(1 )) +
("000000"&sample_array(0)(2 )) +
("000000"&sample_array(0)(3 )) +
("000000"&sample_array(0)(4 )) +
("000000"&sample_array(0)(5 )) +
("000000"&sample_array(0)(6 )) +
("000000"&sample_array(0)(7 )) +
("000000"&sample_array(0)(8 )) +
("000000"&sample_array(0)(9 )) +
("000000"&sample_array(0)(10)) +
("000000"&sample_array(0)(11)) +
("000000"&sample_array(0)(12)) +
("000000"&sample_array(0)(13)) +
("000000"&sample_array(0)(14)) +
("000000"&sample_array(0)(15)) +
("000000"&sample_array(0)(16)) +
to_unsigned(8, 16), 4) when and_reduce(availible_mask(15 downto 0)) = '1' else
dc_default;
dc_value <= dc_4_value(9 downto 0) when block_size = to_unsigned(4, 8) else
--dc_8_value(9 downto 0) when block_size = to_unsigned(8, 8) else
dc_16_value(9 downto 0) when block_size = to_unsigned(16, 8) else
"1010101010"; --make errors obvious
-- some values needed for plane mode
a <= signed(shift_left( ("0000000000000000"&sample_array(0)(16)) + ("000000000000000"&sample_array(16)(0)), 4)) when block_size = 16 else
signed(shift_left( ("0000000000000000"&sample_array(0)(8 )) + ("000000000000000"&sample_array(8 )(0)), 4));
b <= shift_right( to_signed(5, 8) * h(7) + to_signed(32, 26) , 6) when block_size = 16 else
shift_right( to_signed(34, 8) * h(7) + to_signed(32, 26) , 6);
c <= shift_right( to_signed(5, 8) * v(7) + to_signed(32, 26) , 6) when block_size = 16 else
shift_right( to_signed(34, 8) * v(7) + to_signed(32, 26) , 6);
v(0) <= to_signed(1, 8) * (signed(sample_array(9)(0)) - signed(sample_array(7)(0))) when block_size = 16 else
to_signed(1, 8) * (signed(sample_array(5)(0)) - signed(sample_array(3)(0)));
h(0) <= to_signed(1, 8) * (signed(sample_array(0)(9)) - signed(sample_array(0)(7))) when block_size = 16 else
to_signed(1, 8) * (signed(sample_array(0)(5)) - signed(sample_array(0)(3)));
calc_h_v_plane: for xy in 7 downto 1 generate
v(xy) <= v(xy-1) + to_signed(xy+1,8) * (signed(sample_array(9+xy)(0)) - signed(sample_array(7-xy)(0))) when block_size = 16 else
v(xy-1) + to_signed(xy+1,8) * (signed(sample_array(5+xy)(0)) - signed(sample_array(3-xy)(0))) when block_size = 8 and xy <= 3 else
v(xy-1);
h(xy) <= h(xy-1) + to_signed(xy+1,8) * (signed(sample_array(0)(9+xy)) - signed(sample_array(0)(7-xy))) when block_size = 16 else
h(xy-1) + to_signed(xy+1,8) * (signed(sample_array(0)(5+xy)) - signed(sample_array(0)(3-xy))) when block_size = 8 and xy <= 3 else
h(xy-1);
end generate;
--calculate predicted samples
calculate_samples_row: for i in 16 downto 1 generate
calculate_samples_col: for j in 16 downto 1 generate
constant x : integer := j-1;
constant y : integer := i-1;
constant zVR : integer := 2 * x - y;
constant zVR_mod_2 : integer := zVR mod 2;
constant zVR_sign : integer := integer(sign(real(zVR)));
constant zHD : integer := 2 * y - x;
constant zHD_mod_2 : integer := zHD mod 2;
constant zHD_sign : integer := integer(sign(real(zHD)));
constant y_mod_2 : integer := y mod 2;
constant zHU : integer := x + 2 * y;
constant zHU_mod_2 : integer := zHU mod 2;
constant zHU_13_comp : integer := integer(sign(real(zHU-13)));
signal plane_pre_clip : plane_value_array_type;
signal plane_value : sample_array_type;
begin
plane_pre_clip(i)(j) <= shift_right(("00000000"&a) + b * to_signed(x-7, 8) + c * to_signed(y-7, 8) + to_signed(16, 34) , 5) when block_size = 16 else
shift_right(("00000000"&a) + b * to_signed(x-3, 8) + c * to_signed(y-3, 8) + to_signed(16, 34) , 5);
plane_value(i)(j) <= to_unsigned(0, 10) when plane_pre_clip(i)(j) < to_signed(0, 34) else
to_unsigned(255, 10) when plane_pre_clip(i)(j) > to_signed(255, 34) else
unsigned(plane_pre_clip(i)(j)(9 downto 0));
sample_array(i)(j) <=
--vertical
sample_array(i-1)(j) when mode = 0 else
--horizontal
sample_array(i)(j-1) when mode = 1 else
--dc prediction
dc_value when mode = 2 else
--diag down left
shift_right(sample_array(0)(7) + to_unsigned(3,2) * sample_array(0)(8)(7 downto 0) + to_unsigned(2,10) , 2) when mode = 3 and block_size = 4 and x = 3 and y = 3 else
shift_right(sample_array(0)((y+x+1) mod 17) + to_unsigned(2,2) * sample_array(0)((y+x+2) mod 17)(7 downto 0) + sample_array(0)((y+x+3) mod 17) + to_unsigned(2,10) , 2) when mode = 3 and block_size = 4 and (not(x = 3 and y = 3)) and ((y+x+3) <= 16) else
--shift_right(sample_array(0)(15) + to_unsigned(3,2) * sample_array(0)(16)(7 downto 0) + to_unsigned(2,10) , 2) when mode = 3 and block_size = 8 and x = 7 and y = 7 else
--shift_right(sample_array(0)((y+x+1) mod 17) + to_unsigned(2,2) * sample_array(0)((y+x+2) mod 17)(7 downto 0) + sample_array(0)((y+x+3) mod 17) + to_unsigned(2,10) , 2) when mode = 3 and block_size = 8 and (not(x = 7 and y = 7)) and ((y+x+3) <= 16) else
--diag down right
shift_right(sample_array(abs(y-x-1))(0) + to_unsigned(2,2) * sample_array(abs(y-x))(0)(7 downto 0) + sample_array(abs(y-x+1))(0) + to_unsigned(2,10) , 2) when mode = 4 and (block_size = 4) and (y > x) and ((y-x-1) >= 0)else
shift_right(sample_array(0)(abs(x-y-1)) + to_unsigned(2,2) * sample_array(0)(abs(x-y))(7 downto 0) + sample_array(0)(abs(x-y+1)) + to_unsigned(2,10) , 2) when mode = 4 and (block_size = 4) and (y < x) and ((x-y-1) >= 0)else
shift_right(sample_array(1)(0) + to_unsigned(2,2) * sample_array(0)(0)(7 downto 0) + sample_array(0)(1) + to_unsigned(2,10) , 2) when mode = 4 and (block_size = 4) and (y = x) else
--vertical right
shift_right(sample_array(0)(abs(x - y/2 ) mod 17) + sample_array(0)(abs(x - y/2 + 1) mod 17)(7 downto 0) + to_unsigned(1,10) , 1) when mode = 5 and (block_size = 4) and (zVR_mod_2 = 0) and ((x - y/2 ) >= 0) else
shift_right(sample_array(0)(abs(x - y/2 -1) mod 17) + to_unsigned(2,2) * sample_array(0)(abs(x - y/2 ) mod 17)(7 downto 0) + sample_array(0)(abs(x - y/2+1) mod 17) + to_unsigned(2,10) , 2) when mode = 5 and (block_size = 4) and (zVR_mod_2 = 1) and ((x - y/2 -1) >= 0) else
shift_right(sample_array(1)(0) + to_unsigned(2,2) * sample_array(0)(0)(7 downto 0) + sample_array(0)(1) + to_unsigned(2,10) , 2) when mode = 5 and (block_size = 4) and (zVR = -1) else
shift_right(sample_array(y)(0) + to_unsigned(2,2) * sample_array(y-1)(0)(7 downto 0) + sample_array(y-2)(0) + to_unsigned(2,10) , 2) when mode = 5 and (block_size = 4) and (zVR < -1) and ((y-2) >= 0) else
--horizontal down
shift_right(sample_array(abs(y - x/2) mod 17)(0) + sample_array(abs(y - x/2 + 1) mod 17)(0)(7 downto 0) + to_unsigned(1,10) , 1) when mode = 6 and (block_size = 4) and (zHD_mod_2 = 0) and (zHD >= 0) and ((y - x/2) >= 0)else
shift_right(sample_array(abs(y - x/2-1) mod 17)(0) + to_unsigned(2,2) * sample_array(abs(y - x/2 ) mod 17)(0)(7 downto 0) + sample_array(abs(y - x/2 + 1) mod 17)(0) + to_unsigned(2,10) , 2) when mode = 6 and (block_size = 4) and (zHD_mod_2 = 1) and (zHD >= 0) and ((y - x/2 - 1) >= 0) else
shift_right(sample_array(0)(1) + to_unsigned(2,2) * sample_array(0)(0)(7 downto 0) + sample_array(1)(0) + to_unsigned(2,10) , 2) when mode = 6 and (block_size = 4) and (zHD = -1) else
shift_right(sample_array(0)(x) + to_unsigned(2,2) * sample_array(0)(x-1)(7 downto 0) + sample_array(0)(x-2) + to_unsigned(2,10) , 2) when mode = 6 and (block_size = 4) and (zHD < -1) and ((x-2) >= 0) else
--vertical left
shift_right(sample_array(0)((x + y /2 + 1) mod 17) + sample_array(0)((x+y/2+2) mod 17)(7 downto 0) + to_unsigned(1,10) , 1) when mode = 7 and (block_size = 4) and y_mod_2 = 0 and ((x + y/2+2) <= 16) else
shift_right(sample_array(0)((x + y /2 + 1) mod 17) + to_unsigned(2,2) * sample_array(0)((x+y/2+2) mod 17)(7 downto 0) + sample_array(0)((x+y/2+3) mod 17) + to_unsigned(2,10) , 2) when mode = 7 and (block_size = 4) and y_mod_2 /= 0 and ((x + y/2+3) <= 16) else
--horizontal up
shift_right(sample_array((y + x/2 + 1) mod 17)(0) + sample_array((y+x/2+2) mod 17)(0)(7 downto 0) + to_unsigned(1,10) , 1) when mode = 8 and ((block_size = 4 and zHU < 5) ) and (zHU >= 0) and zHU_mod_2 = 0 else
shift_right(sample_array((y + x/2 + 1) mod 17)(0) + to_unsigned(2,2) * sample_array((y+x/2+2) mod 17)(0)(7 downto 0) + sample_array((y+x/2+3) mod 17)(0) + to_unsigned(2,10) , 2) when mode = 8 and ((block_size = 4 and zHU < 5) ) and (zHU >= 0) and zHU_mod_2 = 1 else
--shift_right(sample_array(7)(0) + to_unsigned(3,2) * sample_array(8)(0)(7 downto 0) + to_unsigned(2,10) , 2) when mode = 8 and block_size = 8 and zHU = 13 else
shift_right(sample_array(3)(0) + to_unsigned(3,2) * sample_array(4)(0)(7 downto 0) + to_unsigned(2,10) , 2) when mode = 8 and block_size = 4 and zHU = 5 else
--sample_array(8)(0) when mode = 8 and block_size = 8 and zHU > 13 else
sample_array(4)(0) when mode = 8 and block_size = 4 and zHU > 5 else
--plane
plane_value(i)(j) when mode = 3 and (block_size = 16 or block_size = 8) else
"0000000001";
end generate;
end generate;
--assign calculated samples to output macro block
assign_smpls_2_mb_row: for i in 15 downto 0 generate
assign_smpls_2_mb_col: for j in 15 downto 0 generate
macroblock(i)(j) <= sample_array(i+1)(j+1)(7 downto 0);
end generate;
end generate;
--output selected macroblock row
--todo: replace with something more reasonable...
row_data <= macroblock(0 )(0)¯oblock(0 )(1)¯oblock(0 )(2)¯oblock(0 )(3)¯oblock(0 )(4)¯oblock(0 )(5)¯oblock(0 )(6)¯oblock(0 )(7)¯oblock(0 )(8)¯oblock(0 )(9)¯oblock(0 )(10)¯oblock(0 )(11)¯oblock(0 )(12)¯oblock(0 )(13)¯oblock(0 )(14)¯oblock(0 )(15) when row_addr = to_unsigned(0 , 8) else
macroblock(1 )(0)¯oblock(1 )(1)¯oblock(1 )(2)¯oblock(1 )(3)¯oblock(1 )(4)¯oblock(1 )(5)¯oblock(1 )(6)¯oblock(1 )(7)¯oblock(1 )(8)¯oblock(1 )(9)¯oblock(1 )(10)¯oblock(1 )(11)¯oblock(1 )(12)¯oblock(1 )(13)¯oblock(1 )(14)¯oblock(1 )(15) when row_addr = to_unsigned(1 , 8) else
macroblock(2 )(0)¯oblock(2 )(1)¯oblock(2 )(2)¯oblock(2 )(3)¯oblock(2 )(4)¯oblock(2 )(5)¯oblock(2 )(6)¯oblock(2 )(7)¯oblock(2 )(8)¯oblock(2 )(9)¯oblock(2 )(10)¯oblock(2 )(11)¯oblock(2 )(12)¯oblock(2 )(13)¯oblock(2 )(14)¯oblock(2 )(15) when row_addr = to_unsigned(2 , 8) else
macroblock(3 )(0)¯oblock(3 )(1)¯oblock(3 )(2)¯oblock(3 )(3)¯oblock(3 )(4)¯oblock(3 )(5)¯oblock(3 )(6)¯oblock(3 )(7)¯oblock(3 )(8)¯oblock(3 )(9)¯oblock(3 )(10)¯oblock(3 )(11)¯oblock(3 )(12)¯oblock(3 )(13)¯oblock(3 )(14)¯oblock(3 )(15) when row_addr = to_unsigned(3 , 8) else
macroblock(4 )(0)¯oblock(4 )(1)¯oblock(4 )(2)¯oblock(4 )(3)¯oblock(4 )(4)¯oblock(4 )(5)¯oblock(4 )(6)¯oblock(4 )(7)¯oblock(4 )(8)¯oblock(4 )(9)¯oblock(4 )(10)¯oblock(4 )(11)¯oblock(4 )(12)¯oblock(4 )(13)¯oblock(4 )(14)¯oblock(4 )(15) when row_addr = to_unsigned(4 , 8) else
macroblock(5 )(0)¯oblock(5 )(1)¯oblock(5 )(2)¯oblock(5 )(3)¯oblock(5 )(4)¯oblock(5 )(5)¯oblock(5 )(6)¯oblock(5 )(7)¯oblock(5 )(8)¯oblock(5 )(9)¯oblock(5 )(10)¯oblock(5 )(11)¯oblock(5 )(12)¯oblock(5 )(13)¯oblock(5 )(14)¯oblock(5 )(15) when row_addr = to_unsigned(5 , 8) else
macroblock(6 )(0)¯oblock(6 )(1)¯oblock(6 )(2)¯oblock(6 )(3)¯oblock(6 )(4)¯oblock(6 )(5)¯oblock(6 )(6)¯oblock(6 )(7)¯oblock(6 )(8)¯oblock(6 )(9)¯oblock(6 )(10)¯oblock(6 )(11)¯oblock(6 )(12)¯oblock(6 )(13)¯oblock(6 )(14)¯oblock(6 )(15) when row_addr = to_unsigned(6 , 8) else
macroblock(7 )(0)¯oblock(7 )(1)¯oblock(7 )(2)¯oblock(7 )(3)¯oblock(7 )(4)¯oblock(7 )(5)¯oblock(7 )(6)¯oblock(7 )(7)¯oblock(7 )(8)¯oblock(7 )(9)¯oblock(7 )(10)¯oblock(7 )(11)¯oblock(7 )(12)¯oblock(7 )(13)¯oblock(7 )(14)¯oblock(7 )(15) when row_addr = to_unsigned(7 , 8) else
macroblock(8 )(0)¯oblock(8 )(1)¯oblock(8 )(2)¯oblock(8 )(3)¯oblock(8 )(4)¯oblock(8 )(5)¯oblock(8 )(6)¯oblock(8 )(7)¯oblock(8 )(8)¯oblock(8 )(9)¯oblock(8 )(10)¯oblock(8 )(11)¯oblock(8 )(12)¯oblock(8 )(13)¯oblock(8 )(14)¯oblock(8 )(15) when row_addr = to_unsigned(8 , 8) else
macroblock(9 )(0)¯oblock(9 )(1)¯oblock(9 )(2)¯oblock(9 )(3)¯oblock(9 )(4)¯oblock(9 )(5)¯oblock(9 )(6)¯oblock(9 )(7)¯oblock(9 )(8)¯oblock(9 )(9)¯oblock(9 )(10)¯oblock(9 )(11)¯oblock(9 )(12)¯oblock(9 )(13)¯oblock(9 )(14)¯oblock(9 )(15) when row_addr = to_unsigned(9 , 8) else
macroblock(10)(0)¯oblock(10)(1)¯oblock(10)(2)¯oblock(10)(3)¯oblock(10)(4)¯oblock(10)(5)¯oblock(10)(6)¯oblock(10)(7)¯oblock(10)(8)¯oblock(10)(9)¯oblock(10)(10)¯oblock(10)(11)¯oblock(10)(12)¯oblock(10)(13)¯oblock(10)(14)¯oblock(10)(15) when row_addr = to_unsigned(10, 8) else
macroblock(11)(0)¯oblock(11)(1)¯oblock(11)(2)¯oblock(11)(3)¯oblock(11)(4)¯oblock(11)(5)¯oblock(11)(6)¯oblock(11)(7)¯oblock(11)(8)¯oblock(11)(9)¯oblock(11)(10)¯oblock(11)(11)¯oblock(11)(12)¯oblock(11)(13)¯oblock(11)(14)¯oblock(11)(15) when row_addr = to_unsigned(11, 8) else
macroblock(12)(0)¯oblock(12)(1)¯oblock(12)(2)¯oblock(12)(3)¯oblock(12)(4)¯oblock(12)(5)¯oblock(12)(6)¯oblock(12)(7)¯oblock(12)(8)¯oblock(12)(9)¯oblock(12)(10)¯oblock(12)(11)¯oblock(12)(12)¯oblock(12)(13)¯oblock(12)(14)¯oblock(12)(15) when row_addr = to_unsigned(12, 8) else
macroblock(13)(0)¯oblock(13)(1)¯oblock(13)(2)¯oblock(13)(3)¯oblock(13)(4)¯oblock(13)(5)¯oblock(13)(6)¯oblock(13)(7)¯oblock(13)(8)¯oblock(13)(9)¯oblock(13)(10)¯oblock(13)(11)¯oblock(13)(12)¯oblock(13)(13)¯oblock(13)(14)¯oblock(13)(15) when row_addr = to_unsigned(13, 8) else
macroblock(14)(0)¯oblock(14)(1)¯oblock(14)(2)¯oblock(14)(3)¯oblock(14)(4)¯oblock(14)(5)¯oblock(14)(6)¯oblock(14)(7)¯oblock(14)(8)¯oblock(14)(9)¯oblock(14)(10)¯oblock(14)(11)¯oblock(14)(12)¯oblock(14)(13)¯oblock(14)(14)¯oblock(14)(15) when row_addr = to_unsigned(14, 8) else
macroblock(15)(0)¯oblock(15)(1)¯oblock(15)(2)¯oblock(15)(3)¯oblock(15)(4)¯oblock(15)(5)¯oblock(15)(6)¯oblock(15)(7)¯oblock(15)(8)¯oblock(15)(9)¯oblock(15)(10)¯oblock(15)(11)¯oblock(15)(12)¯oblock(15)(13)¯oblock(15)(14)¯oblock(15)(15) when row_addr = to_unsigned(15, 8) else
to_unsigned(0, 128);
end architecture rtl; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:15:00 11/12/2015
-- Design Name:
-- Module Name: reg_read - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity reg_read is
port( re_clk: in std_logic;
re_rst: in std_logic;
re_ld: in std_logic;
re_reg_in: in std_logic_vector(15 downto 0);
re_reg_out: out std_logic_vector(15 downto 0)
);
end reg_read;
architecture Behavioral of reg_read is
begin
process(re_clk, re_rst, re_ld)
begin
if (re_rst='1') then
re_reg_out <= (others=>'0');
elsif (re_clk'event and re_clk='1') then
if (re_ld='1') then
re_reg_out <= re_reg_in;
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity hostmotid is
generic (
buswidth : integer;
cookie : std_logic_vector(31 downto 0);
namelow : std_logic_vector(31 downto 0);
namehigh : std_logic_vector(31 downto 0);
idromoffset : std_logic_vector(31 downto 0));
port (
readid : in std_logic;
addr : in std_logic_vector(1 downto 0);
obus : out std_logic_vector (buswidth-1 downto 0));
end hostmotid;
architecture Behavioral of hostmotid is
begin
hostmotidproc: process (readid,addr)
begin
obus <= ( others => 'Z');
if readid = '1' then
case addr is
when "00" => obus <= cookie;
when "01" => obus <= namelow;
when "10" => obus <= namehigh;
when "11" => obus <= idromoffset;
when others => null;
end case;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- $Id: lmb_bram_if_funcs.vhd,v 1.1.2.4 2010/09/28 11:56:10 rolandp Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: lmb_bram_if_funcs.vhd
--
-- Description: Support functions for lmb_bram_if_cntlr
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_funcs.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-- Revision: $Revision: 1.1.2.4 $
-- Date: $Date: 2010/09/28 11:56:10 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package lmb_bram_if_funcs is
type TARGET_FAMILY_TYPE is (
-- pragma xilinx_rtl_off
VIRTEX7,
KINTEX7,
ARTIX7,
ZYNQ,
VIRTEXU,
KINTEXU,
ARTIXU,
-- pragma xilinx_rtl_on
RTL
);
function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE;
-- Get the maximum number of inputs to a LUT.
function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer;
end package lmb_bram_if_funcs;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package body lmb_bram_if_funcs is
function LowerCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' or char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
when 'Y' => return 'y'; when 'Z' => return 'z';
when others => return char;
end case;
end LowerCase_Char;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function Equal_String( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (LowerCase_Char(str1(i)) = LowerCase_Char(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END Equal_String;
function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE is
begin -- function String_To_Family
if ((Select_RTL) or Equal_String(S, "rtl")) then
return RTL;
elsif Equal_String(S, "virtex7") or Equal_String(S, "qvirtex7") then
return VIRTEX7;
elsif Equal_String(S, "kintex7") or Equal_String(S, "kintex7l") or
Equal_String(S, "qkintex7") or Equal_String(S, "qkintex7l") then
return KINTEX7;
elsif Equal_String(S, "artix7") or Equal_String(S, "artix7l") or Equal_String(S, "aartix7") or
Equal_String(S, "qartix7") or Equal_String(S, "qartix7l") then
return ARTIX7;
elsif Equal_String(S, "zynq") or Equal_String(S, "azynq") or Equal_String(S, "qzynq") then
return ZYNQ;
elsif Equal_String(S, "virtexu") or Equal_String(S, "qvirtexu") then
return VIRTEXU;
elsif Equal_String(S, "kintexu") or Equal_String(S, "kintexul") or
Equal_String(S, "qkintexu") or Equal_String(S, "qkintexul") then
return KINTEXU;
elsif Equal_String(S, "artixu") or Equal_String(S, "artixul") or Equal_String(S, "aartixu") or
Equal_String(S, "qartixu") or Equal_String(S, "qartixul") then
return ARTIXU;
else
-- assert (false) report "No known target family" severity failure;
return RTL;
end if;
end function String_To_Family;
function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer is
begin
return 6;
end function Family_To_LUT_Size;
end package body lmb_bram_if_funcs;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSR is
Port ( NZVC : in STD_LOGIC_VECTOR (3 downto 0);
Rst : in STD_LOGIC;
clk : in STD_LOGIC;
Ncwp : in STD_LOGIC;
Carry : out STD_LOGIC;
Cwp : out STD_LOGIC
);
end PSR;
architecture Behavioral of PSR is
begin
process(clk,Rst,NZVC)
begin
if (rising_edge(clk)) then
if (Rst = '1') then
Carry <= '0';
Cwp <= '0';
else
Cwp <= Ncwp;
Carry <=NZVC(0);
end if;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : ElectronFpga_duo.vhf
-- /___/ /\ Timestamp : 28/07/2015
-- \ \ / \
-- \___\/\___\
--
--Design Name: ElectronFpga_duo
--Device: Spartan6 LX9
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ElectronFpga_duo is
port (
clk_32M00 : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
ERST : in std_logic;
red : out std_logic_vector (3 downto 0);
green : out std_logic_vector (3 downto 0);
blue : out std_logic_vector (3 downto 0);
vsync : out std_logic;
hsync : out std_logic;
audiol : out std_logic;
audioR : out std_logic;
casIn : in std_logic;
casOut : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
ARDUINO_RESET : out std_logic;
SW1 : in std_logic;
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic;
DIP : in std_logic_vector(1 downto 0)
);
end;
architecture behavioral of ElectronFpga_duo is
signal clk_16M00 : std_logic;
signal clk_33M33 : std_logic;
signal clk_40M00 : std_logic;
signal ERSTn : std_logic;
signal pwrup_RSTn : std_logic;
signal reset_ctr : std_logic_vector (7 downto 0) := (others => '0');
begin
inst_dcm4 : entity work.dcm4 port map(
CLKIN_IN => clk_32M00,
CLK0_OUT => clk_40M00,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
inst_dcm5 : entity work.dcm5 port map(
CLKIN_IN => clk_32M00,
CLK0_OUT => clk_16M00,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
inst_dcm6 : entity work.dcm6 port map(
CLKIN_IN => clk_32M00,
CLK0_OUT => clk_33M33,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
inst_ElectronFpga_core : entity work.ElectronFpga_core
port map (
clk_16M00 => clk_16M00,
clk_33M33 => clk_33M33,
clk_40M00 => clk_40M00,
ps2_clk => ps2_clk,
ps2_data => ps2_data,
ERSTn => ERSTn,
red => red,
green => green,
blue => blue,
vsync => vsync,
hsync => hsync,
audiol => audiol,
audioR => audioR,
casIn => casIn,
casOut => casOut,
LED1 => LED1,
LED2 => LED2,
SDMISO => SDMISO,
SDSS => SDSS,
SDCLK => SDCLK,
SDMOSI => SDMOSI,
DIP => DIP
);
ERSTn <= pwrup_RSTn and not ERST;
ARDUINO_RESET <= SW1;
-- On the Duo the external reset signal is not asserted on power up
-- This internal counter forces power up reset to happen
-- This is needed by the GODIL to initialize some of the registers
ResetProcess : process (clk_16M00)
begin
if rising_edge(clk_16M00) then
if (pwrup_RSTn = '0') then
reset_ctr <= reset_ctr + 1;
end if;
end if;
end process;
pwrup_RSTn <= reset_ctr(7);
end behavioral;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 8;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 1;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
entity tb_dff08c is
end tb_dff08c;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff08c is
signal clk : std_logic;
signal rst : std_logic;
signal en : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.dff08c
port map (
q => dout,
d => din,
en => en,
clk => clk,
rst => rst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
wait for 1 ns;
assert dout = x"aa" severity failure;
rst <= '1';
en <= '1';
pulse;
assert dout = x"aa" severity failure;
rst <= '0';
din <= x"38";
pulse;
assert dout = x"38" severity failure;
din <= x"af";
pulse;
assert dout = x"af" severity failure;
en <= '0';
din <= x"b3";
pulse;
assert dout = x"af" severity failure;
en <= '0';
rst <= '1';
din <= x"b4";
pulse;
assert dout = x"af" severity failure;
en <= '1';
rst <= '1';
din <= x"b5";
pulse;
assert dout = x"aa" severity failure;
wait;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
entity dut is
port (
sig_i : in std_logic_vector;
sig_o : out std_logic_vector
);
end entity;
architecture arch of dut is
begin
sig_o <= sig_i;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity tb is
end entity;
architecture bench of tb is
signal sin : std_ulogic_vector(31 downto 0);
signal sout : std_ulogic_vector(31 downto 0);
begin
stim : process
begin
wait for 1 ns;
report to_string(sin);
report to_string(sout);
std.env.finish;
end process;
dut_inst: entity work.dut port map (
sig_i => sin,
sig_o => sout
);
end architecture;
|
-- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:10.0
-- IP Revision: 128000
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v10_0;
USE fifo_generator_v10_0.fifo_generator_v10_0;
ENTITY golden_ticket_fifo IS
PORT (
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END golden_ticket_fifo;
ARCHITECTURE golden_ticket_fifo_arch OF golden_ticket_fifo IS
COMPONENT fifo_generator_v10_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v10_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF golden_ticket_fifo_arch : ARCHITECTURE IS "fifo_generator_v10_0,Vivado 2013.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF golden_ticket_fifo_arch : ARCHITECTURE IS "golden_ticket_fifo,fifo_generator_v10_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF golden_ticket_fifo_arch : ARCHITECTURE IS "golden_ticket_fifo,fifo_generator_v10_0,{x_ipProduct=Vivado 2013.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=10.0,x_ipCoreRevision=128000,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=kintex7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=2,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1021,C_PROG_FULL_THRESH_NEGATE_VAL=1020,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=0,C_USE_ECC=0,C_USE_EMBEDDED_REG=1,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=0,C_HAS_AXI_WR_CHANNEL=0,C_HAS_AXI_RD_CHANNEL=0,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=0,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=64,C_AXIS_TID_WIDTH=8,C_AXIS_TDEST_WIDTH=4,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=8,C_AXIS_TKEEP_WIDTH=8,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
BEGIN
U0 : fifo_generator_v10_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 2,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1021,
C_PROG_FULL_THRESH_NEGATE_VAL => 1020,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 0,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 1,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 0,
C_HAS_AXI_WR_CHANNEL => 0,
C_HAS_AXI_RD_CHANNEL => 0,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 4,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 0,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 0,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 64,
C_AXIS_TID_WIDTH => 8,
C_AXIS_TDEST_WIDTH => 4,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 8,
C_AXIS_TKEEP_WIDTH => 8,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END golden_ticket_fifo_arch;
|
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--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:10.0
-- IP Revision: 128000
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v10_0;
USE fifo_generator_v10_0.fifo_generator_v10_0;
ENTITY golden_ticket_fifo IS
PORT (
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END golden_ticket_fifo;
ARCHITECTURE golden_ticket_fifo_arch OF golden_ticket_fifo IS
COMPONENT fifo_generator_v10_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v10_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF golden_ticket_fifo_arch : ARCHITECTURE IS "fifo_generator_v10_0,Vivado 2013.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF golden_ticket_fifo_arch : ARCHITECTURE IS "golden_ticket_fifo,fifo_generator_v10_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF golden_ticket_fifo_arch : ARCHITECTURE IS "golden_ticket_fifo,fifo_generator_v10_0,{x_ipProduct=Vivado 2013.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=10.0,x_ipCoreRevision=128000,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=kintex7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=2,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1021,C_PROG_FULL_THRESH_NEGATE_VAL=1020,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=0,C_USE_ECC=0,C_USE_EMBEDDED_REG=1,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=0,C_HAS_AXI_WR_CHANNEL=0,C_HAS_AXI_RD_CHANNEL=0,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=0,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=64,C_AXIS_TID_WIDTH=8,C_AXIS_TDEST_WIDTH=4,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=8,C_AXIS_TKEEP_WIDTH=8,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
BEGIN
U0 : fifo_generator_v10_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 2,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1021,
C_PROG_FULL_THRESH_NEGATE_VAL => 1020,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 0,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 1,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 0,
C_HAS_AXI_WR_CHANNEL => 0,
C_HAS_AXI_RD_CHANNEL => 0,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 4,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 0,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 0,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 64,
C_AXIS_TID_WIDTH => 8,
C_AXIS_TDEST_WIDTH => 4,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 8,
C_AXIS_TKEEP_WIDTH => 8,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END golden_ticket_fifo_arch;
|
-- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:10.0
-- IP Revision: 128000
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v10_0;
USE fifo_generator_v10_0.fifo_generator_v10_0;
ENTITY golden_ticket_fifo IS
PORT (
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END golden_ticket_fifo;
ARCHITECTURE golden_ticket_fifo_arch OF golden_ticket_fifo IS
COMPONENT fifo_generator_v10_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v10_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF golden_ticket_fifo_arch : ARCHITECTURE IS "fifo_generator_v10_0,Vivado 2013.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF golden_ticket_fifo_arch : ARCHITECTURE IS "golden_ticket_fifo,fifo_generator_v10_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF golden_ticket_fifo_arch : ARCHITECTURE IS "golden_ticket_fifo,fifo_generator_v10_0,{x_ipProduct=Vivado 2013.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=10.0,x_ipCoreRevision=128000,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=kintex7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=2,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1021,C_PROG_FULL_THRESH_NEGATE_VAL=1020,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=0,C_USE_ECC=0,C_USE_EMBEDDED_REG=1,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=0,C_HAS_AXI_WR_CHANNEL=0,C_HAS_AXI_RD_CHANNEL=0,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=0,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=64,C_AXIS_TID_WIDTH=8,C_AXIS_TDEST_WIDTH=4,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=8,C_AXIS_TKEEP_WIDTH=8,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
BEGIN
U0 : fifo_generator_v10_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 2,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1021,
C_PROG_FULL_THRESH_NEGATE_VAL => 1020,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 0,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 1,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 0,
C_HAS_AXI_WR_CHANNEL => 0,
C_HAS_AXI_RD_CHANNEL => 0,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 4,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 0,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 0,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 64,
C_AXIS_TID_WIDTH => 8,
C_AXIS_TDEST_WIDTH => 4,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 8,
C_AXIS_TKEEP_WIDTH => 8,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END golden_ticket_fifo_arch;
|
-- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:10.0
-- IP Revision: 128000
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v10_0;
USE fifo_generator_v10_0.fifo_generator_v10_0;
ENTITY golden_ticket_fifo IS
PORT (
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END golden_ticket_fifo;
ARCHITECTURE golden_ticket_fifo_arch OF golden_ticket_fifo IS
COMPONENT fifo_generator_v10_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v10_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF golden_ticket_fifo_arch : ARCHITECTURE IS "fifo_generator_v10_0,Vivado 2013.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF golden_ticket_fifo_arch : ARCHITECTURE IS "golden_ticket_fifo,fifo_generator_v10_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF golden_ticket_fifo_arch : ARCHITECTURE IS "golden_ticket_fifo,fifo_generator_v10_0,{x_ipProduct=Vivado 2013.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=10.0,x_ipCoreRevision=128000,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=kintex7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=2,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1021,C_PROG_FULL_THRESH_NEGATE_VAL=1020,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=0,C_USE_ECC=0,C_USE_EMBEDDED_REG=1,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=0,C_HAS_AXI_WR_CHANNEL=0,C_HAS_AXI_RD_CHANNEL=0,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=0,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=64,C_AXIS_TID_WIDTH=8,C_AXIS_TDEST_WIDTH=4,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=8,C_AXIS_TKEEP_WIDTH=8,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
BEGIN
U0 : fifo_generator_v10_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 2,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1021,
C_PROG_FULL_THRESH_NEGATE_VAL => 1020,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 0,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 1,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 0,
C_HAS_AXI_WR_CHANNEL => 0,
C_HAS_AXI_RD_CHANNEL => 0,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 4,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 0,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 0,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 64,
C_AXIS_TID_WIDTH => 8,
C_AXIS_TDEST_WIDTH => 4,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 8,
C_AXIS_TKEEP_WIDTH => 8,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END golden_ticket_fifo_arch;
|
-- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:10.0
-- IP Revision: 128000
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v10_0;
USE fifo_generator_v10_0.fifo_generator_v10_0;
ENTITY golden_ticket_fifo IS
PORT (
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END golden_ticket_fifo;
ARCHITECTURE golden_ticket_fifo_arch OF golden_ticket_fifo IS
COMPONENT fifo_generator_v10_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v10_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF golden_ticket_fifo_arch : ARCHITECTURE IS "fifo_generator_v10_0,Vivado 2013.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF golden_ticket_fifo_arch : ARCHITECTURE IS "golden_ticket_fifo,fifo_generator_v10_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF golden_ticket_fifo_arch : ARCHITECTURE IS "golden_ticket_fifo,fifo_generator_v10_0,{x_ipProduct=Vivado 2013.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=10.0,x_ipCoreRevision=128000,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=kintex7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=2,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1021,C_PROG_FULL_THRESH_NEGATE_VAL=1020,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=0,C_USE_ECC=0,C_USE_EMBEDDED_REG=1,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=0,C_HAS_AXI_WR_CHANNEL=0,C_HAS_AXI_RD_CHANNEL=0,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=0,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=64,C_AXIS_TID_WIDTH=8,C_AXIS_TDEST_WIDTH=4,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=8,C_AXIS_TKEEP_WIDTH=8,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
BEGIN
U0 : fifo_generator_v10_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 2,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1021,
C_PROG_FULL_THRESH_NEGATE_VAL => 1020,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 0,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 1,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 0,
C_HAS_AXI_WR_CHANNEL => 0,
C_HAS_AXI_RD_CHANNEL => 0,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 4,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 0,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 0,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 64,
C_AXIS_TID_WIDTH => 8,
C_AXIS_TDEST_WIDTH => 4,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 8,
C_AXIS_TKEEP_WIDTH => 8,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END golden_ticket_fifo_arch;
|
-- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:10.0
-- IP Revision: 128000
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v10_0;
USE fifo_generator_v10_0.fifo_generator_v10_0;
ENTITY golden_ticket_fifo IS
PORT (
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END golden_ticket_fifo;
ARCHITECTURE golden_ticket_fifo_arch OF golden_ticket_fifo IS
COMPONENT fifo_generator_v10_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v10_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF golden_ticket_fifo_arch : ARCHITECTURE IS "fifo_generator_v10_0,Vivado 2013.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF golden_ticket_fifo_arch : ARCHITECTURE IS "golden_ticket_fifo,fifo_generator_v10_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF golden_ticket_fifo_arch : ARCHITECTURE IS "golden_ticket_fifo,fifo_generator_v10_0,{x_ipProduct=Vivado 2013.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=10.0,x_ipCoreRevision=128000,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=kintex7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=2,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1021,C_PROG_FULL_THRESH_NEGATE_VAL=1020,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=0,C_USE_ECC=0,C_USE_EMBEDDED_REG=1,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=0,C_HAS_AXI_WR_CHANNEL=0,C_HAS_AXI_RD_CHANNEL=0,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=0,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=64,C_AXIS_TID_WIDTH=8,C_AXIS_TDEST_WIDTH=4,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=8,C_AXIS_TKEEP_WIDTH=8,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
BEGIN
U0 : fifo_generator_v10_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 2,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1021,
C_PROG_FULL_THRESH_NEGATE_VAL => 1020,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 0,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 1,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 0,
C_HAS_AXI_WR_CHANNEL => 0,
C_HAS_AXI_RD_CHANNEL => 0,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 4,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 0,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 0,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 64,
C_AXIS_TID_WIDTH => 8,
C_AXIS_TDEST_WIDTH => 4,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 8,
C_AXIS_TKEEP_WIDTH => 8,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END golden_ticket_fifo_arch;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF1_1_block2.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_1_block2
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF1_1
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF1_1_block2 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_7_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
twdlXdin_7_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
twdlXdin_8_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
twdlXdin_8_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_7_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_8_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_8_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_7_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_1_block2;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_1_block2 IS
-- Signals
SIGNAL twdlXdin_7_re_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdlXdin_7_im_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdlXdin_8_re_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdlXdin_8_im_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_7_re_tmp : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_7_im_tmp : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_8_re_tmp : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_8_im_tmp : signed(16 DOWNTO 0); -- sfix17_En13
BEGIN
twdlXdin_7_re_signed <= signed(twdlXdin_7_re);
twdlXdin_7_im_signed <= signed(twdlXdin_7_im);
twdlXdin_8_re_signed <= signed(twdlXdin_8_re);
twdlXdin_8_im_signed <= signed(twdlXdin_8_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_7_re_signed,
twdlXdin_7_im_signed, twdlXdin_8_re_signed, twdlXdin_8_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(17 DOWNTO 0);
VARIABLE add_cast_0 : signed(17 DOWNTO 0);
VARIABLE sub_cast : signed(17 DOWNTO 0);
VARIABLE sub_cast_0 : signed(17 DOWNTO 0);
VARIABLE add_cast_1 : signed(17 DOWNTO 0);
VARIABLE add_cast_2 : signed(17 DOWNTO 0);
VARIABLE sub_cast_1 : signed(17 DOWNTO 0);
VARIABLE sub_cast_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_7_re_signed, 18);
add_cast_0 := resize(twdlXdin_8_re_signed, 18);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_7_re_signed, 18);
sub_cast_0 := resize(twdlXdin_8_re_signed, 18);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_7_im_signed, 18);
add_cast_2 := resize(twdlXdin_8_im_signed, 18);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_7_im_signed, 18);
sub_cast_2 := resize(twdlXdin_8_im_signed, 18);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
dout_7_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(16 DOWNTO 0);
dout_7_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(16 DOWNTO 0);
dout_8_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(16 DOWNTO 0);
dout_8_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(16 DOWNTO 0);
dout_7_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_7_re <= std_logic_vector(dout_7_re_tmp);
dout_7_im <= std_logic_vector(dout_7_im_tmp);
dout_8_re <= std_logic_vector(dout_8_re_tmp);
dout_8_im <= std_logic_vector(dout_8_im_tmp);
END rtl;
|
entity proc4 is
end entity;
architecture rtl of proc4 is
procedure test1(x : inout integer) is
begin
x := x + 1;
end procedure;
procedure test2(x : inout bit_vector) is
begin
for i in x'range loop
x(i) := not x(i);
end loop;
end procedure;
procedure test3(x : inout bit_vector(3 downto 0)) is
begin
for i in 3 downto 0 loop
x(i) := not x(i);
end loop;
end procedure;
procedure test4(signal x : inout integer) is
begin
x <= x + 1;
end procedure;
procedure test5(signal x : inout bit_vector; l : out integer) is
begin
l := x'length;
for i in x'range loop
x(i) <= not x(i);
end loop;
end procedure;
signal s : integer;
signal k : bit_vector(1 downto 0);
begin
process is
variable v : integer;
variable b : bit_vector(3 downto 0);
begin
k <= "10";
v := 5;
test1(v);
assert v = 6;
b := "1010";
test2(b);
assert b = "0101";
test3(b);
assert b = "1010";
s <= 5;
wait for 1 ns;
test4(s);
wait for 1 ns;
assert s = 6;
test5(k, v);
wait for 1 ns;
assert v = 2;
assert k = "01";
wait;
end process;
end architecture;
|
entity proc4 is
end entity;
architecture rtl of proc4 is
procedure test1(x : inout integer) is
begin
x := x + 1;
end procedure;
procedure test2(x : inout bit_vector) is
begin
for i in x'range loop
x(i) := not x(i);
end loop;
end procedure;
procedure test3(x : inout bit_vector(3 downto 0)) is
begin
for i in 3 downto 0 loop
x(i) := not x(i);
end loop;
end procedure;
procedure test4(signal x : inout integer) is
begin
x <= x + 1;
end procedure;
procedure test5(signal x : inout bit_vector; l : out integer) is
begin
l := x'length;
for i in x'range loop
x(i) <= not x(i);
end loop;
end procedure;
signal s : integer;
signal k : bit_vector(1 downto 0);
begin
process is
variable v : integer;
variable b : bit_vector(3 downto 0);
begin
k <= "10";
v := 5;
test1(v);
assert v = 6;
b := "1010";
test2(b);
assert b = "0101";
test3(b);
assert b = "1010";
s <= 5;
wait for 1 ns;
test4(s);
wait for 1 ns;
assert s = 6;
test5(k, v);
wait for 1 ns;
assert v = 2;
assert k = "01";
wait;
end process;
end architecture;
|
entity proc4 is
end entity;
architecture rtl of proc4 is
procedure test1(x : inout integer) is
begin
x := x + 1;
end procedure;
procedure test2(x : inout bit_vector) is
begin
for i in x'range loop
x(i) := not x(i);
end loop;
end procedure;
procedure test3(x : inout bit_vector(3 downto 0)) is
begin
for i in 3 downto 0 loop
x(i) := not x(i);
end loop;
end procedure;
procedure test4(signal x : inout integer) is
begin
x <= x + 1;
end procedure;
procedure test5(signal x : inout bit_vector; l : out integer) is
begin
l := x'length;
for i in x'range loop
x(i) <= not x(i);
end loop;
end procedure;
signal s : integer;
signal k : bit_vector(1 downto 0);
begin
process is
variable v : integer;
variable b : bit_vector(3 downto 0);
begin
k <= "10";
v := 5;
test1(v);
assert v = 6;
b := "1010";
test2(b);
assert b = "0101";
test3(b);
assert b = "1010";
s <= 5;
wait for 1 ns;
test4(s);
wait for 1 ns;
assert s = 6;
test5(k, v);
wait for 1 ns;
assert v = 2;
assert k = "01";
wait;
end process;
end architecture;
|
entity proc4 is
end entity;
architecture rtl of proc4 is
procedure test1(x : inout integer) is
begin
x := x + 1;
end procedure;
procedure test2(x : inout bit_vector) is
begin
for i in x'range loop
x(i) := not x(i);
end loop;
end procedure;
procedure test3(x : inout bit_vector(3 downto 0)) is
begin
for i in 3 downto 0 loop
x(i) := not x(i);
end loop;
end procedure;
procedure test4(signal x : inout integer) is
begin
x <= x + 1;
end procedure;
procedure test5(signal x : inout bit_vector; l : out integer) is
begin
l := x'length;
for i in x'range loop
x(i) <= not x(i);
end loop;
end procedure;
signal s : integer;
signal k : bit_vector(1 downto 0);
begin
process is
variable v : integer;
variable b : bit_vector(3 downto 0);
begin
k <= "10";
v := 5;
test1(v);
assert v = 6;
b := "1010";
test2(b);
assert b = "0101";
test3(b);
assert b = "1010";
s <= 5;
wait for 1 ns;
test4(s);
wait for 1 ns;
assert s = 6;
test5(k, v);
wait for 1 ns;
assert v = 2;
assert k = "01";
wait;
end process;
end architecture;
|
entity proc4 is
end entity;
architecture rtl of proc4 is
procedure test1(x : inout integer) is
begin
x := x + 1;
end procedure;
procedure test2(x : inout bit_vector) is
begin
for i in x'range loop
x(i) := not x(i);
end loop;
end procedure;
procedure test3(x : inout bit_vector(3 downto 0)) is
begin
for i in 3 downto 0 loop
x(i) := not x(i);
end loop;
end procedure;
procedure test4(signal x : inout integer) is
begin
x <= x + 1;
end procedure;
procedure test5(signal x : inout bit_vector; l : out integer) is
begin
l := x'length;
for i in x'range loop
x(i) <= not x(i);
end loop;
end procedure;
signal s : integer;
signal k : bit_vector(1 downto 0);
begin
process is
variable v : integer;
variable b : bit_vector(3 downto 0);
begin
k <= "10";
v := 5;
test1(v);
assert v = 6;
b := "1010";
test2(b);
assert b = "0101";
test3(b);
assert b = "1010";
s <= 5;
wait for 1 ns;
test4(s);
wait for 1 ns;
assert s = 6;
test5(k, v);
wait for 1 ns;
assert v = 2;
assert k = "01";
wait;
end process;
end architecture;
|
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
-- ZyEHW is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ZyEHW. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.zyehw_pkg.all;
entity fifo_flags is
generic (
AWIDTH: integer
);
port (
rdclk: in std_logic;
wrclk: in std_logic;
rden: in std_logic;
wren: in std_logic;
rdaddr: in std_logic_vector(AWIDTH-1 downto 0);
wraddr: in std_logic_vector(AWIDTH-1 downto 0);
grdaddr: in std_logic_vector(AWIDTH-1 downto 0);
gwraddr: in std_logic_vector(AWIDTH-1 downto 0);
rderr: out std_logic;
wrerr: out std_logic;
near_full: out std_logic;
half_full: out std_logic
);
end fifo_flags;
architecture struct_fifo_flags of fifo_flags is
component fifo_flags_int_sync is
generic (
AWIDTH: integer
);
port (
rdclk: in std_logic;
wrclk: in std_logic;
rden: in std_logic;
wren: in std_logic;
rdaddr: in std_logic_vector(AWIDTH-1 downto 0);
wraddr: in std_logic_vector(AWIDTH-1 downto 0);
grdaddr: in std_logic_vector(AWIDTH-1 downto 0);
gwraddr: in std_logic_vector(AWIDTH-1 downto 0);
rden_del: out std_logic;
wren_del: out std_logic;
rdaddr_del: out std_logic_vector(AWIDTH-1 downto 0);
wraddr_del: out std_logic_vector(AWIDTH-1 downto 0);
wrclk_rdaddr: out std_logic_vector(AWIDTH-1 downto 0);
rdclk_wraddr: out std_logic_vector(AWIDTH-1 downto 0)
);
end component;
constant capacity: integer:= 2**(AWIDTH-1);
constant near_full_count: integer:= capacity-100;
constant half_full_count: integer:= capacity/2;
signal rden_del: std_logic;
signal wren_del: std_logic;
signal rdaddr_del: std_logic_vector(AWIDTH-1 downto 0);
signal wraddr_del: std_logic_vector(AWIDTH-1 downto 0);
signal wrclk_rdaddr: std_logic_vector(AWIDTH-1 downto 0);
signal rdclk_wraddr: std_logic_vector(AWIDTH-1 downto 0);
signal diff: std_logic_vector(AWIDTH-1 downto 0):= (others => '0');
signal rderr_reg: std_logic:= '0';
signal wrerr_reg: std_logic:= '0';
signal half_full_reg: std_logic:= '0';
signal near_full_reg: std_logic:= '0';
signal empty, full: std_logic;
signal tmp_near_full, tmp_half_full: std_logic;
begin
fifo_flags_int_sync_i: fifo_flags_int_sync
generic map (
AWIDTH => AWIDTH
)
port map (
rdclk => rdclk,
wrclk => wrclk,
rden => rden,
wren => wren,
rdaddr => rdaddr,
wraddr => wraddr,
grdaddr => grdaddr,
gwraddr => gwraddr,
rden_del => rden_del,
wren_del => wren_del,
rdaddr_del => rdaddr_del,
wraddr_del => wraddr_del,
wrclk_rdaddr => wrclk_rdaddr,
rdclk_wraddr => rdclk_wraddr
);
process (wrclk_rdaddr, wraddr_del, diff)
begin
-- The most significant bit is used to distinguish between full and
-- empty
if ((not(wrclk_rdaddr(wrclk_rdaddr'high))) &
wrclk_rdaddr(wrclk_rdaddr'high-1 downto wrclk_rdaddr'low)) =
wraddr_del then
full <= '1';
else
full <= '0';
end if;
if diff >= std_logic_vector(to_unsigned(half_full_count, AWIDTH))
then
tmp_half_full <= '1';
else
tmp_half_full <= '0';
end if;
if diff >= std_logic_vector(to_unsigned(near_full_count, AWIDTH))
then
tmp_near_full <= '1';
else
tmp_near_full <= '0';
end if;
end process;
process (rdclk_wraddr, rdaddr_del)
begin
if rdclk_wraddr = rdaddr_del then
empty <= '1';
else
empty <= '0';
end if;
end process;
process (wrclk)
variable tmp_diff: std_logic_vector(diff'high+1 downto diff'low);
begin
if wrclk'event and wrclk = '1' then
if wren_del = '1' then
wrerr_reg <= full;
end if;
tmp_diff:= std_logic_vector(('0' & signed(wraddr_del)) - ('0' &
signed(wrclk_rdaddr)));
-- If wradd_del is bigger then removing the sign (0) gives the
-- difference. Otherwise, removing the negative sign (1) will give
-- max. value minus absolute difference plus one (exactly what we
-- want).
diff <= tmp_diff(diff'range);
near_full_reg <= tmp_near_full;
half_full_reg <= tmp_half_full;
end if;
end process;
process (rdclk)
begin
if rdclk'event and rdclk = '1' then
if rden_del = '1' then
rderr_reg <= empty;
end if;
end if;
end process;
rderr <= rderr_reg;
wrerr <= wrerr_reg;
half_full <= half_full_reg;
near_full <= near_full_reg;
end struct_fifo_flags;
|
-------------------------------------------------------------------------------
-- Title : 8-bit Client-to-LocalLink Transmitter FIFO
-- Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- File : tx_client_fifo_8.vhd
-- Version : 1.4
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Description: This is a transmit-side LocalLink FIFO implementation for
-- the example design of the Virtex-6 Embedded Tri-Mode Ethernet
-- MAC Wrapper core.
--
-- The transmit FIFO is created from a Block RAM of size 4096
-- words of 8-bits per word.
--
-- Valid frame data received from LocalLink interface is written
-- into the Block RAM on the write clock. The FIFO will store
-- frames upto 4kbytes in length. If larger frames are written
-- to the FIFO the LocalLink interface will accept the rest of the
-- frame, but that frame will be dropped by the FIFO and
-- the overflow signal will be asserted.
--
-- The FIFO is designed to work with a minimum frame length of 14
-- bytes.
--
-- When there is at least one complete frame in the FIFO,
-- the MAC transmitter client interface will be driven to
-- request frame transmission by placing the first byte of
-- the frame onto tx_data[15:0] and by asserting
-- tx_data_valid. The MAC will later respond by asserting
-- tx_ack. At this point the remaining frame data is read
-- out of the FIFO in a continuous burst. Data is read out
-- of the FIFO on the rd_clk.
--
-- The FIFO has been designed to operate with different clocks
-- on the write and read sides. The write clock (LocalLink clock)
-- can be an equal or faster frequency than the read clock
-- (client clock). The minimum write clock frequency is the read
-- clock frequency divided by 2.5.
--
-- The FIFO memory size can be increased by expanding the rd_addr
-- and wr_addr signal widths, to address further BRAMs.
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity tx_client_fifo_8 is
generic (
-- If FULL_DUPLEX_ONLY is true then all the half duplex logic in the FIFO is removed.
-- The default for the fifo is to include the half duplex functionality
FULL_DUPLEX_ONLY : boolean := false);
port (
-- MAC Interface
rd_clk : in std_logic;
rd_sreset : in std_logic;
rd_enable : in std_logic;
tx_data : out std_logic_vector(7 downto 0);
tx_data_valid : out std_logic;
tx_ack : in std_logic;
tx_collision : in std_logic;
tx_retransmit : in std_logic;
overflow : out std_logic;
-- LocalLink Interface
wr_clk : in std_logic;
wr_sreset : in std_logic; -- synchronous reset (write_clock)
wr_data : in std_logic_vector(7 downto 0);
wr_sof_n : in std_logic;
wr_eof_n : in std_logic;
wr_src_rdy_n : in std_logic;
wr_dst_rdy_n : out std_logic;
wr_fifo_status : out std_logic_vector(3 downto 0)
);
end tx_client_fifo_8;
architecture RTL of tx_client_fifo_8 is
signal GND : std_logic;
signal VCC : std_logic;
signal GND_BUS : std_logic_vector(31 downto 0);
type rd_state_typ is (IDLE_s, QUEUE1_s, QUEUE2_s, QUEUE3_s, QUEUE_ACK_s, WAIT_ACK_s, FRAME_s, DROP_s, RETRANSMIT_s);
signal rd_state : rd_state_typ;
signal rd_nxt_state : rd_state_typ;
type wr_state_typ is (WAIT_s, DATA_s, EOF_s, OVFLOW_s);
signal wr_state : wr_state_typ;
signal wr_nxt_state : wr_state_typ;
type data_pipe is array(0 to 1) of std_logic_vector(7 downto 0);
type cntl_pipe is array(0 to 1) of std_logic;
signal wr_data_bram : std_logic_vector(7 downto 0);
signal wr_data_pipe : data_pipe;
signal wr_sof_pipe : cntl_pipe;
signal wr_eof_pipe : cntl_pipe;
signal wr_accept_pipe : cntl_pipe;
signal wr_accept_bram : std_logic;
signal wr_eof_bram : std_logic_vector(0 downto 0);
signal wr_addr : unsigned(11 downto 0);
signal wr_addr_inc : std_logic;
signal wr_start_addr_load : std_logic;
signal wr_addr_reload : std_logic;
signal wr_start_addr : unsigned(11 downto 0);
signal wr_fifo_full : std_logic;
signal wr_en : std_logic;
signal wr_ovflow_dst_rdy : std_logic;
signal wr_dst_rdy_int_n : std_logic;
signal frame_in_fifo : std_logic;
signal frame_in_fifo_sync : std_logic;
signal rd_eof_bram : std_logic;
signal rd_eof : std_logic;
signal rd_eof_reg : std_logic;
signal rd_addr : unsigned(11 downto 0);
signal rd_addr_inc : std_logic;
signal rd_addr_reload : std_logic;
signal rd_data_bram : std_logic_vector(7 downto 0);
signal rd_data_pipe : std_logic_vector(7 downto 0);
signal rd_en : std_logic;
signal rd_en_bram : std_logic;
signal dob_bram : std_logic_vector(31 downto 0);
signal dopb_bram : std_logic_vector(3 downto 0);
signal rd_tran_frame_tog : std_logic;
signal wr_tran_frame_tog : std_logic;
signal wr_tran_frame_sync : std_logic;
signal wr_tran_frame_delay : std_logic;
signal rd_retran_frame_tog : std_logic;
signal wr_retran_frame_tog : std_logic;
signal wr_retran_frame_sync : std_logic;
signal wr_retran_frame_delay : std_logic;
signal wr_store_frame : std_logic;
signal wr_eof_state : std_logic;
signal wr_eof_state_reg : std_logic;
signal wr_transmit_frame : std_logic;
signal wr_retransmit_frame : std_logic;
signal wr_frames : std_logic_vector(8 downto 0);
signal wr_frame_in_fifo : std_logic;
signal rd_16_count : unsigned(3 downto 0);
signal rd_txfer_en : std_logic;
signal rd_addr_txfer : unsigned(11 downto 0);
signal rd_txfer_tog : std_logic;
signal wr_txfer_tog : std_logic;
signal wr_txfer_tog_sync : std_logic;
signal wr_txfer_tog_delay : std_logic;
signal wr_txfer_en : std_logic;
signal wr_rd_addr : unsigned(11 downto 0);
signal wr_addr_diff : unsigned(11 downto 0);
signal rd_drop_frame : std_logic;
signal rd_retransmit : std_logic;
signal rd_start_addr : unsigned(11 downto 0);
signal rd_start_addr_load : std_logic;
signal rd_start_addr_reload : std_logic;
signal rd_dec_addr : unsigned(11 downto 0);
signal rd_transmit_frame : std_logic;
signal rd_retransmit_frame : std_logic;
signal rd_col_window_expire : std_logic;
signal rd_col_window_pipe : cntl_pipe;
signal wr_col_window_pipe : cntl_pipe;
signal wr_fifo_overflow : std_logic;
signal rd_slot_timer : unsigned(9 downto 0);
signal wr_col_window_expire : std_logic;
signal rd_idle_state : std_logic;
signal rd_enable_delay : std_logic;
signal rd_enable_delay2 : std_logic;
-- Small delay for simulation purposes.
constant dly : time := 1 ps;
-----------------------------------------------------------------------------
-- Attributes for FIFO simulation and synthesis
-----------------------------------------------------------------------------
-- ASYNC_REG attributes added to simulate actual behaviour under
-- asynchronous operating conditions.
attribute ASYNC_REG : string;
attribute ASYNC_REG of wr_tran_frame_tog : signal is "TRUE";
attribute ASYNC_REG of wr_retran_frame_tog : signal is "TRUE";
attribute ASYNC_REG of frame_in_fifo_sync : signal is "TRUE";
attribute ASYNC_REG of wr_rd_addr : signal is "TRUE";
attribute ASYNC_REG of wr_txfer_tog : signal is "TRUE";
attribute ASYNC_REG of wr_col_window_pipe : signal is "TRUE";
-------------------------------------------------------------------------------
-- Begin FIFO architecture
-------------------------------------------------------------------------------
begin
GND <= '0';
VCC <= '1';
GND_BUS <= (others => '0');
rd_enable_del_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_enable_delay <= '0' after dly;
rd_enable_delay2 <= '0' after dly;
else
rd_enable_delay <= rd_enable after dly;
rd_enable_delay2 <= rd_enable_delay after dly;
end if;
end if;
end process rd_enable_del_p;
-----------------------------------------------------------------------------
-- Write state machine and control
-----------------------------------------------------------------------------
-- Write state machine
-- states are WAIT, DATA, EOF, OVFLOW
-- clock through next state of sm
clock_wrs_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
if wr_sreset = '1' then
wr_state <= WAIT_s after dly;
else
wr_state <= wr_nxt_state after dly;
end if;
end if;
end process clock_wrs_p;
-- decode next state, combinitorial
-- should never be able to overflow whilst not in the data state.
next_wrs_p : process(wr_state, wr_sof_pipe(1), wr_eof_pipe, wr_eof_bram(0), wr_fifo_overflow)
begin
case wr_state is
when WAIT_s =>
-- when the sof is detected move to frame state
if wr_sof_pipe(1) = '1' then
wr_nxt_state <= DATA_s;
else
wr_nxt_state <= WAIT_s;
end if;
when DATA_s =>
-- wait for the end of frame to be detected
if wr_fifo_overflow = '1' and wr_eof_pipe = "00" then
wr_nxt_state <= OVFLOW_s;
elsif wr_eof_pipe(1) = '1' then
wr_nxt_state <= EOF_s;
else
wr_nxt_state <= DATA_s;
end if;
when EOF_s =>
-- if the start of frame is already in the pipe, a back to back frame
-- transmission has occured. move straight back to frame state
if wr_sof_pipe(1) = '1' then
wr_nxt_state <= DATA_s;
elsif wr_eof_bram(0) = '1' then
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= EOF_s;
end if;
when OVFLOW_s =>
-- wait until the end of frame is reached before clearing the overflow
if wr_eof_bram(0) = '1' then
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= OVFLOW_s;
end if;
when others =>
wr_nxt_state <= WAIT_s;
end case;
end process;
-- decode output signals.
wr_en <= '0' when wr_state = OVFLOW_s else wr_accept_bram;
wr_addr_inc <= wr_en;
wr_addr_reload <= '1' when wr_state = OVFLOW_s else '0';
wr_start_addr_load <= '1' when wr_state = EOF_s and wr_nxt_state = WAIT_s else
'1' when wr_state = EOF_s and wr_nxt_state = DATA_s else '0';
-- pause the LocalLink flow when the fifo is full.
wr_dst_rdy_int_n <= wr_ovflow_dst_rdy when wr_state = OVFLOW_s else wr_fifo_full;
wr_dst_rdy_n <= wr_dst_rdy_int_n;
overflow <= '1' when wr_state = OVFLOW_s else '0';
-- when in overflow and have captured ovflow eof send dst rdy high again.
p_ovflow_dst_rdy : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_ovflow_dst_rdy <= '0' after dly;
else
if wr_fifo_overflow = '1' and wr_state = DATA_s then
wr_ovflow_dst_rdy <= '0' after dly;
elsif wr_eof_n = '0' and wr_src_rdy_n = '0' then
wr_ovflow_dst_rdy <= '1' after dly;
end if;
end if;
end if;
end process;
-- eof signals for use in overflow logic
wr_eof_state <= '1' when wr_state = EOF_s else '0';
p_reg_eof_st : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_eof_state_reg <= '0' after dly;
else
wr_eof_state_reg <= wr_eof_state after dly;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Read state machine and control
-----------------------------------------------------------------------------
-- clock through the read state machine
clock_rds_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_state <= IDLE_s after dly;
elsif rd_enable = '1' then
rd_state <= rd_nxt_state after dly;
end if;
end if;
end process clock_rds_p;
-- Full duplex only state machine
gen_fd_sm : if (FULL_DUPLEX_ONLY = TRUE) generate
-- decode the next state
next_rds_p : process(rd_state, frame_in_fifo, rd_eof, tx_ack)
begin
case rd_state is
when IDLE_s =>
-- if there is a frame in the fifo start to queue the new frame
-- to the output
if frame_in_fifo = '1' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end if;
when QUEUE1_s =>
rd_nxt_state <= QUEUE2_s;
when QUEUE2_s =>
rd_nxt_state <= QUEUE3_s;
when QUEUE3_s =>
rd_nxt_state <= QUEUE_ACK_s;
when QUEUE_ACK_s =>
rd_nxt_state <= WAIT_ACK_s;
when WAIT_ACK_s =>
-- the output pipe line is fully loaded, so wait for ack from mac
-- before moving on
if tx_ack = '1' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= WAIT_ACK_s;
end if;
when FRAME_s =>
-- when the end of frame has been reached wait another frame in
-- the fifo
if rd_eof = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FRAME_s;
end if;
when others =>
rd_nxt_state <= IDLE_s;
end case;
end process next_rds_p;
end generate gen_fd_sm;
-- Full and Half Duplex State Machine
gen_hd_sm : if (FULL_DUPLEX_ONLY = FALSE) generate
-- decode the next state
-- should never receive a rd_drop_frame pulse outside of the Frame state
next_rds_p : process(rd_state, frame_in_fifo, rd_eof_reg, tx_ack, rd_drop_frame, rd_retransmit)
begin
case rd_state is
when IDLE_s =>
-- if a retransmit request is detected go to retransmit state
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_s;
-- if there is a frame in the fifo then queue the new frame to
-- the output
elsif frame_in_fifo = '1' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end if;
when QUEUE1_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= QUEUE2_s;
end if;
when QUEUE2_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= QUEUE3_s;
end if;
when QUEUE3_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= QUEUE_ACK_s;
end if;
when QUEUE_ACK_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= WAIT_ACK_s;
end if;
when WAIT_ACK_s =>
-- the output pipeline is now fully loaded so wait for ack from
-- mac before moving on.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_s;
elsif tx_ack = '1' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= WAIT_ACK_s;
end if;
when FRAME_s =>
-- if a collision only request, then must drop the rest of the
-- current frame, move to drop state
if rd_drop_frame = '1' then
rd_nxt_state <= DROP_s;
elsif rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_s;
-- continue transmitting frame until the end of the frame is
-- detected, then wait for a new frame to be sent.
elsif rd_eof_reg = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FRAME_s;
end if;
when DROP_s =>
-- wait until rest of frame has been cleared.
if rd_eof_reg = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= DROP_s;
end if;
when RETRANSMIT_s =>
-- reload the data pipe from the start of the frame
rd_nxt_state <= QUEUE1_s;
when others =>
rd_nxt_state <= IDLE_s;
end case;
end process next_rds_p;
end generate gen_hd_sm;
-- decode output signals
-- decode output data
rd_data_decode_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_enable = '1' then
if rd_nxt_state = FRAME_s then
tx_data <= rd_data_pipe after dly;
else
case rd_state is
when QUEUE_ACK_s =>
tx_data <= rd_data_pipe after dly;
when WAIT_ACK_s => null;
when FRAME_s =>
tx_data <= rd_data_pipe after dly;
when others =>
tx_data <= (others => '0') after dly;
end case;
end if;
end if;
end if;
end process rd_data_decode_p;
-- decode output data valid
rd_dv_decode_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_enable = '1' then
if rd_nxt_state = FRAME_s then
tx_data_valid <= not(tx_collision and not(tx_retransmit)) after dly;
else
case rd_state is
when QUEUE_ACK_s =>
tx_data_valid <= '1' after dly;
when WAIT_ACK_s =>
tx_data_valid <= '1' after dly;
when FRAME_s =>
if (rd_nxt_state /= DROP_s) then
tx_data_valid <= '1' after dly;
else
tx_data_valid <= '0' after dly;
end if;
when others =>
tx_data_valid <= '0' after dly;
end case;
end if;
end if;
end if;
end process rd_dv_decode_p;
-- decode full duplex only control signals
gen_fd_decode : if (FULL_DUPLEX_ONLY = TRUE) generate
rd_en <= '0' when rd_state = IDLE_s else
'1' when rd_nxt_state = FRAME_s else
'0' when rd_state = WAIT_ACK_s else '1';
rd_addr_inc <= rd_en;
rd_addr_reload <= '1' when rd_state = FRAME_s and rd_nxt_state = IDLE_s else '0';
-- Transmit frame pulse is only 1 clock enabled pulse long.
-- Transmit frame pulse must never be more frequent than 64 clocks to allow toggle to cross clock domain
rd_transmit_frame <= '1' when rd_state = WAIT_ACK_s and rd_nxt_state = FRAME_s else '0';
-- unused for full duplex only
rd_start_addr_reload <= '0';
rd_start_addr_load <= '0';
rd_retransmit_frame <= '0';
end generate gen_fd_decode;
-- decode half duplex control signals
gen_hd_decode : if (FULL_DUPLEX_ONLY = FALSE) generate
rd_en <= '0' when rd_state = IDLE_s else
'0' when (rd_nxt_state = DROP_s and rd_eof = '1') else
'1' when rd_nxt_state = FRAME_s else
'0' when rd_state = RETRANSMIT_s else
'0' when rd_state = WAIT_ACK_s else '1';
rd_addr_inc <= rd_en;
rd_addr_reload <= '1' when rd_state = FRAME_s and rd_nxt_state = IDLE_s else
'1' when rd_state = DROP_s and rd_nxt_state = IDLE_s else '0';
rd_start_addr_reload <= '1' when rd_state = RETRANSMIT_s else '0';
rd_start_addr_load <= '1' when rd_state = WAIT_ACK_s and rd_nxt_state = FRAME_s else
'1' when rd_col_window_expire = '1' else '0';
-- Transmit frame pulse must never be more frequent than 64 clocks to allow toggle to cross clock domain
rd_transmit_frame <= '1' when rd_state = WAIT_ACK_s and rd_nxt_state = FRAME_s else '0';
-- Retransmit frame pulse must never be more frequent than 16 clocks to allow toggle to cross clock domain
rd_retransmit_frame <= '1' when rd_state = RETRANSMIT_s else '0';
end generate gen_hd_decode;
-----------------------------------------------------------------------------
-- Frame Count
-- We need to maintain a count of frames in the fifo, so that we know when a
-- frame is available for transmission. The counter must be held on the
-- write clock domain as this is the faster clock.
-----------------------------------------------------------------------------
-- A frame has been written to the fifo
wr_store_frame <= '1' when wr_state = EOF_s and wr_nxt_state /= EOF_s else '0';
-- generate a toggle to indicate when a frame has been transmitted from the fifo
p_rd_trans_tog : process (rd_clk)
begin -- process
if rd_clk'event and rd_clk = '1' then
if rd_sreset = '1' then
rd_tran_frame_tog <= '0' after dly;
elsif rd_enable = '1' then
if rd_transmit_frame = '1' then
rd_tran_frame_tog <= not rd_tran_frame_tog after dly;
end if;
end if;
end if;
end process;
-- move the read transmit frame signal onto the write clock domain
p_sync_wr_trans : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_tran_frame_tog <= '0' after dly;
wr_tran_frame_sync <= '0' after dly;
wr_tran_frame_delay <= '0' after dly;
wr_transmit_frame <= '0' after dly;
else
wr_tran_frame_tog <= rd_tran_frame_tog after dly;
wr_tran_frame_sync <= wr_tran_frame_tog after dly;
wr_tran_frame_delay <= wr_tran_frame_sync after dly;
-- edge detector
if (wr_tran_frame_delay xor wr_tran_frame_sync) = '1' then
wr_transmit_frame <= '1' after dly;
else
wr_transmit_frame <= '0' after dly;
end if;
end if;
end if;
end process p_sync_wr_trans;
gen_fd_count : if (FULL_DUPLEX_ONLY = TRUE) generate
-- count the number of frames in the fifo. the counter is incremented when a
-- frame is stored and decremented when a frame is transmitted. Need to keep
-- the counter on the write clock as this is the fastest clock.
p_wr_frames : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_frames <= (others => '0') after dly;
else
if (wr_store_frame and not wr_transmit_frame) = '1' then
wr_frames <= wr_frames + 1 after dly;
elsif (not wr_store_frame and wr_transmit_frame) = '1' then
wr_frames <= wr_frames - 1 after dly;
end if;
end if;
end if;
end process p_wr_frames;
end generate gen_fd_count;
gen_hd_count : if (FULL_DUPLEX_ONLY = FALSE) generate
-- generate a toggle to indicate when a frame has been transmitted from the fifo
p_rd_retran_tog : process (rd_clk)
begin -- process
if rd_clk'event and rd_clk = '1' then
if rd_sreset = '1' then
rd_retran_frame_tog <= '0' after dly;
elsif rd_enable = '1' then
if rd_retransmit_frame = '1' then
rd_retran_frame_tog <= not rd_retran_frame_tog after dly;
end if;
end if;
end if;
end process;
-- move the read retransmit frame signal onto the write clock domain
p_sync_wr_trans : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_retran_frame_tog <= '0' after dly;
wr_retran_frame_sync <= '0' after dly;
wr_retran_frame_delay <= '0' after dly;
wr_retransmit_frame <= '0' after dly;
else
wr_retran_frame_tog <= rd_retran_frame_tog after dly;
wr_retran_frame_sync <= wr_retran_frame_tog after dly;
wr_retran_frame_delay <= wr_retran_frame_sync after dly;
-- edge detector
if (wr_retran_frame_delay xor wr_retran_frame_sync) = '1' then
wr_retransmit_frame <= '1' after dly;
else
wr_retransmit_frame <= '0' after dly;
end if;
end if;
end if;
end process p_sync_wr_trans;
-- count the number of frames in the fifo. the counter is incremented when a
-- frame is stored or retransmitted and decremented when a frame is transmitted. Need to keep
-- the counter on the write clock as this is the fastest clock.
-- Assumes transmit and retransmit cannot happen at same time
p_wr_frames : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_frames <= (others => '0') after dly;
else
if (wr_store_frame and wr_retransmit_frame) = '1' then
wr_frames <= wr_frames + 2 after dly;
elsif ((wr_store_frame or wr_retransmit_frame) and not wr_transmit_frame) = '1' then
wr_frames <= wr_frames + 1 after dly;
elsif (wr_transmit_frame and not wr_store_frame) = '1' then
wr_frames <= wr_frames - 1 after dly;
end if;
end if;
end if;
end process p_wr_frames;
end generate gen_hd_count;
-- generate a frame in fifo signal for use in control logic
p_wr_avail : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_frame_in_fifo <= '0' after dly;
else
if wr_frames /= (wr_frames'range => '0') then
wr_frame_in_fifo <= '1' after dly;
else
wr_frame_in_fifo <= '0' after dly;
end if;
end if;
end if;
end process p_wr_avail;
-- register back onto read domain for use in the read logic
p_rd_avail : process (rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
if rd_sreset = '1' then
frame_in_fifo_sync <= '0' after dly;
frame_in_fifo <= '0' after dly;
elsif rd_enable = '1' then
frame_in_fifo_sync <= wr_frame_in_fifo after dly;
frame_in_fifo <= frame_in_fifo_sync after dly;
end if;
end if;
end process p_rd_avail;
-----------------------------------------------------------------------------
-- Address counters
-----------------------------------------------------------------------------
-- Address counters
-- write address is incremented when write enable signal has been asserted
wr_addr_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
if wr_sreset = '1' then
wr_addr <= (others => '0') after dly;
elsif wr_addr_reload = '1' then
wr_addr <= wr_start_addr after dly;
elsif wr_addr_inc = '1' then
wr_addr <= wr_addr + 1 after dly;
end if;
end if;
end process wr_addr_p;
-- store the start address incase the address must be reset
wr_staddr_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
if wr_sreset = '1' then
wr_start_addr <= (others => '0') after dly;
elsif wr_start_addr_load = '1' then
wr_start_addr <= wr_addr + 1 after dly;
end if;
end if;
end process wr_staddr_p;
gen_fd_addr : if (FULL_DUPLEX_ONLY = TRUE) generate
-- read address is incremented when read enable signal has been asserted
rd_addr_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_addr <= (others => '0') after dly;
elsif rd_enable = '1' then
if rd_addr_reload = '1' then
rd_addr <= rd_dec_addr after dly;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1 after dly;
end if;
end if;
end if;
end process rd_addr_p;
-- do not need to keep a start address, but the address is needed to
-- calculate fifo occupancy.
rd_start_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_start_addr <= (others => '0') after dly;
elsif rd_enable = '1' then
rd_start_addr <= rd_addr after dly;
end if;
end if;
end process rd_start_p;
end generate gen_fd_addr;
gen_hd_addr : if (FULL_DUPLEX_ONLY = FALSE) generate
-- read address is incremented when read enable signal has been asserted
rd_addr_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_addr <= (others => '0') after dly;
elsif rd_enable = '1' then
if rd_addr_reload = '1' then
rd_addr <= rd_dec_addr after dly;
elsif rd_start_addr_reload = '1' then
rd_addr <= rd_start_addr after dly;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1 after dly;
end if;
end if;
end if;
end process rd_addr_p;
rd_staddr_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_start_addr <= (others => '0') after dly;
elsif rd_enable = '1' then
if rd_start_addr_load = '1' then
rd_start_addr <= rd_addr - 4 after dly;
end if;
end if;
end if;
end process rd_staddr_p;
-- Collision window expires after MAC has been transmitting for required slot
-- time. This is 512 clock cycles at 1G. Also if the end of frame has fully
-- been transmitted by the mac then a collision cannot occur. This collision
-- expire signal goes high at 768 cycles from the start of the frame.
-- Inefficient for short frames, however should be enough to prevent fifo
-- locking up.
rd_col_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_col_window_expire <= '0' after dly;
elsif rd_enable = '1' then
if rd_transmit_frame = '1' then
rd_col_window_expire <= '0' after dly;
elsif rd_slot_timer(9 downto 8) = "11" then
rd_col_window_expire <= '1' after dly;
end if;
end if;
end if;
end process;
rd_idle_state <= '1' when rd_state = IDLE_s else '0';
rd_colreg_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_enable = '1' then
rd_col_window_pipe(0) <= rd_col_window_expire and rd_idle_state after dly;
if rd_txfer_en = '1' then
rd_col_window_pipe(1) <= rd_col_window_pipe(0) after dly;
end if;
end if;
end if;
end process;
rd_slot_time_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then -- will not count until after first
-- frame is sent.
rd_slot_timer <= (others => '0') after dly;
elsif rd_enable = '1' then
if rd_transmit_frame = '1' then -- reset counter
rd_slot_timer <= (others => '0') after dly;
-- do not allow counter to role over.
-- only count when frame is being transmitted.
elsif rd_slot_timer /= "1111111111" then
rd_slot_timer <= rd_slot_timer + 1 after dly;
end if;
end if;
end if;
end process;
end generate gen_hd_addr;
-----------------------------------------------------------------------------
-- rd_dec addr dhouls be addr-2 assumes that rd_addr_reload will NOT happen
-- on very first packet in the fifo
-- should be ok as pipe is not loaded until data is present
rd_decaddr_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_dec_addr <= (others => '0') after dly;
elsif rd_enable = '1' then
if rd_addr_inc = '1' then
rd_dec_addr <= rd_addr - 1 after dly;
end if;
end if;
end if;
end process rd_decaddr_p;
-----------------------------------------------------------------------------
-- Data pipelines
-----------------------------------------------------------------------------
-- register input signals to fifo
-- no reset to allow srl16 target
reg_din_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
wr_data_pipe(0) <= wr_data after dly;
if wr_accept_pipe(0) = '1' then
wr_data_pipe(1) <= wr_data_pipe(0) after dly;
end if;
if wr_accept_pipe(1) = '1' then
wr_data_bram <= wr_data_pipe(1) after dly;
end if;
end if;
end process reg_din_p;
-- no reset to allow srl16 target
reg_sof_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
wr_sof_pipe(0) <= not wr_sof_n after dly;
if wr_accept_pipe(0) = '1' then
wr_sof_pipe(1) <= wr_sof_pipe(0) after dly;
end if;
end if;
end process reg_sof_p;
reg_acc_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
if (wr_sreset = '1') then
wr_accept_pipe(0) <= '0' after dly;
wr_accept_pipe(1) <= '0' after dly;
wr_accept_bram <= '0' after dly;
else
wr_accept_pipe(0) <= wr_src_rdy_n nor wr_dst_rdy_int_n after dly;
wr_accept_pipe(1) <= wr_accept_pipe(0) after dly;
wr_accept_bram <= wr_accept_pipe(1) after dly;
end if;
end if;
end process reg_acc_p;
reg_eof_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
wr_eof_pipe(0) <= not wr_eof_n after dly;
if wr_accept_pipe(0) = '1' then
wr_eof_pipe(1) <= wr_eof_pipe(0) after dly;
end if;
if wr_accept_pipe(1) = '1' then
wr_eof_bram(0) <= wr_eof_pipe(1) after dly;
end if;
end if;
end process reg_eof_p;
-- register data output
-- no reset to allow srl16 target
reg_dout_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_enable = '1' then
if rd_en = '1' then
rd_data_pipe <= rd_data_bram after dly;
end if;
end if;
end if;
end process reg_dout_p;
-- register data output
-- no reset to allow srl16 target
reg_eofout_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_enable = '1' then
if rd_en = '1' then
rd_eof <= rd_eof_bram after dly;
rd_eof_reg <= rd_eof or rd_eof_bram after dly;
end if;
end if;
end if;
end process reg_eofout_p;
gen_hd_input : if (FULL_DUPLEX_ONLY = FALSE) generate
-- register the collision and retransmit signals
reg_col_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_enable = '1' then
rd_drop_frame <= tx_collision and not tx_retransmit after dly;
end if;
end if;
end process reg_col_p;
reg_retr_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_enable = '1' then
rd_retransmit <= tx_collision and tx_retransmit after dly;
end if;
end if;
end process reg_retr_p;
end generate gen_hd_input;
-----------------------------------------------------------------------------
-- FIFO full functionality
-----------------------------------------------------------------------------
-- when full duplex full functionality is difference between read and write addresses.
-- when in half duplex is difference between read start and write addresses.
-- Cannot use gray code this time as the read address and read start addresses jump by more than 1
-- generate an enable pulse for the read side every 16 read clocks. This provides for the worst case
-- situation where wr clk is 20Mhz and rd clk is 125 Mhz.
p_rd_16_pulse : process (rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
if rd_sreset = '1' then
rd_16_count <= (others => '0') after dly;
elsif rd_enable = '1' then
rd_16_count <= rd_16_count + 1 after dly;
end if;
end if;
end process;
rd_txfer_en <= '1' when rd_16_count = "1111" else '0';
-- register the start address on the enable pulse
p_rd_addr_txfer : process (rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
if rd_sreset = '1' then
rd_addr_txfer <= (others => '0') after dly;
elsif rd_enable = '1' then
if rd_txfer_en = '1' then
rd_addr_txfer <= rd_start_addr after dly;
end if;
end if;
end if;
end process;
-- generate a toggle to indicate that the address has been loaded.
p_rd_tog_txfer : process (rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
if rd_sreset = '1' then
rd_txfer_tog <= '0' after dly;
elsif rd_enable = '1' then
if rd_txfer_en = '1' then
rd_txfer_tog <= not rd_txfer_tog after dly;
end if;
end if;
end if;
end process;
-- pass the toggle to the write side
p_wr_tog_txfer : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_txfer_tog <= '0' after dly;
wr_txfer_tog_sync <= '0' after dly;
wr_txfer_tog_delay <= '0' after dly;
else
wr_txfer_tog <= rd_txfer_tog after dly;
wr_txfer_tog_sync <= wr_txfer_tog after dly;
wr_txfer_tog_delay <= wr_txfer_tog_sync after dly;
end if;
end if;
end process;
-- generate an enable pulse from the toggle, the address should have been steady on the wr clock input for at least one clock
wr_txfer_en <= wr_txfer_tog_delay xor wr_txfer_tog_sync;
-- capture the address on the write clock when the enable pulse is high.
p_wr_addr_txfer : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_rd_addr <= (others => '0') after dly;
elsif wr_txfer_en = '1' then
wr_rd_addr <= rd_addr_txfer after dly;
end if;
end if;
end process;
-- Obtain the difference between write and read pointers
p_wr_addr_diff : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_addr_diff <= (others => '0') after dly;
else
wr_addr_diff <= wr_rd_addr - wr_addr after dly;
end if;
end if;
end process;
-- Detect when the FIFO is full
p_wr_full : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_fifo_full <= '0' after dly;
else
-- The FIFO is considered to be full if the write address
-- pointer is within 1 to 3 of the read address pointer.
if wr_addr_diff(11 downto 4) = 0 and wr_addr_diff(3 downto 2) /= "00" then
wr_fifo_full <= '1' after dly;
else
wr_fifo_full <= '0' after dly;
end if;
end if;
end if;
end process p_wr_full;
-- memory overflow occurs when the fifo is full and there are no frames
-- available in the fifo for transmission. If the collision window has
-- expired and there are no frames in the fifo and the fifo is full, then the
-- fifo is in an overflow state. we must accept the rest of the incoming
-- frame in overflow condition.
gen_fd_ovflow : if (FULL_DUPLEX_ONLY = TRUE) generate
-- in full duplex mode, the fifo memory can only overflow if the fifo goes
-- full but there is no frame available to be retranmsitted
-- prevent signal from being asserted when store_frame signal is high, as frame count is being updated
wr_fifo_overflow <= '1' when wr_fifo_full = '1' and wr_frame_in_fifo = '0'
and wr_eof_state = '0' and wr_eof_state_reg = '0' else '0';
end generate gen_fd_ovflow;
gen_hd_ovflow : if (FULL_DUPLEX_ONLY = FALSE) generate
-- register wr col window to give address counter sufficient time to update.
-- prevent signal from being asserted when store_frame signal is high, as frame count is being updated
wr_fifo_overflow <= '1' when wr_fifo_full = '1' and wr_frame_in_fifo = '0'
and wr_eof_state = '0' and wr_eof_state_reg = '0' and wr_col_window_expire = '1' else '0';
-- register rd_col_window signal
-- this signal is long, and will remain high until overflow functionality
-- has finished, so save just to register the once.
p_wr_col_expire : process (wr_clk)
begin -- process
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_col_window_pipe(0) <= '0' after dly;
wr_col_window_pipe(1) <= '0' after dly;
wr_col_window_expire <= '0' after dly;
else
if wr_txfer_en = '1' then
wr_col_window_pipe(0) <= rd_col_window_pipe(1) after dly;
end if;
wr_col_window_pipe(1) <= wr_col_window_pipe(0) after dly;
wr_col_window_expire <= wr_col_window_pipe(1) after dly;
end if;
end if;
end process;
end generate gen_hd_ovflow;
----------------------------------------------------------------------
-- Create FIFO Status Signals in the Write Domain
----------------------------------------------------------------------
-- The FIFO status signal is four bits which represents the occupancy
-- of the FIFO in 16'ths. To generate this signal we therefore only
-- need to compare the 4 most significant bits of the write address
-- pointer with the 4 most significant bits of the read address
-- pointer.
-- The 4 most significant bits of the write pointer minus the 4 msb of
-- the read pointer gives us our FIFO status.
p_fifo_status : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_fifo_status <= "0000" after dly;
else
if wr_addr_diff = (wr_addr_diff'range => '0') then
wr_fifo_status <= "0000" after dly;
else
wr_fifo_status(3) <= not wr_addr_diff(11) after dly;
wr_fifo_status(2) <= not wr_addr_diff(10) after dly;
wr_fifo_status(1) <= not wr_addr_diff(9) after dly;
wr_fifo_status(0) <= not wr_addr_diff(8) after dly;
end if;
end if;
end if;
end process p_fifo_status;
-----------------------------------------------------------------------------
-- Memory
-----------------------------------------------------------------------------
rd_en_bram <= rd_en and rd_enable_delay2;
ramgen : RAMB36E1
generic map (
DOB_REG => 1,
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SRVAL_B => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9)
port map (
ENARDEN => VCC,
CLKARDCLK => wr_clk,
RSTRAMARSTRAM => wr_sreset,
RSTREGARSTREG => GND,
CASCADEINA => GND,
REGCEAREGCE => GND,
ENBWREN => rd_en_bram,
CLKBWRCLK => rd_clk,
RSTRAMB => rd_sreset,
RSTREGB => rd_sreset,
CASCADEINB => GND,
REGCEB => rd_en_bram,
INJECTDBITERR => GND,
INJECTSBITERR => GND,
ADDRARDADDR(15) => GND,
ADDRARDADDR(14 downto 3) => std_logic_vector(wr_addr),
ADDRARDADDR(2 downto 0) => GND_BUS(2 downto 0),
ADDRBWRADDR(15) => GND,
ADDRBWRADDR(14 downto 3) => std_logic_vector(rd_addr),
ADDRBWRADDR(2 downto 0) => GND_BUS(2 downto 0),
DIADI(31 downto 8) => GND_BUS(23 downto 0),
DIADI(7 downto 0) => wr_data_bram,
DIBDI => GND_BUS,
DIPADIP(3 downto 1) => GND_BUS(2 downto 0),
DIPADIP(0) => wr_eof_bram(0),
DIPBDIP => GND_BUS(3 downto 0),
WEA(3 downto 1) => GND_BUS(2 downto 0),
WEA(0) => wr_en,
WEBWE => GND_BUS(7 downto 0),
CASCADEOUTA => open,
CASCADEOUTB => open,
DOADO => open,
DOBDO => dob_bram,
DOPADOP => open,
DOPBDOP => dopb_bram,
ECCPARITY => open,
RDADDRECC => open,
SBITERR => open,
DBITERR => open
);
rd_data_bram <= dob_bram(7 downto 0);
rd_eof_bram <= dopb_bram(0);
end RTL;
|
architecture rtl of fifo is
begin
block_label : block is
begin
end block block_label;
------------------------------<- 80 chars ->------------------------------
--! FPGA RX to Avalon-ST TX interface
--------------------------------------------------------------------------------
------------------------------<- 80 chars ->------------------------------
--------------------------------------------------------------------------------
------------------------------<- 80 chars ->------------------------------
------------------------------<- 80 chars ->------------------------------
--! FPGA RX to Avalon-ST TX interface
--! FPGA RX to Avalon-ST TX interface
--! FPGA RX to Avalon-ST TX interface
--------------------------------------------------------------------------------
------------------------------<- 80 chars ->------------------------------
--! FPGA RX to Avalon-ST TX interface
--! FPGA RX to Avalon-ST TX interface
--! FPGA RX to Avalon-ST TX interface
--! FPGA RX to Avalon-ST TX interface
--------------------------------------------------------------------------------
-- vsg_off comment_010
------------------------------<- 80 chars ->------------------------------
--! FPGA RX to Avalon-ST TX interface
--! FPGA RX to Avalon-ST TX interface
--! FPGA RX to Avalon-ST TX interface
--! FPGA RX to Avalon-ST TX interface
--------------------------------------------------------------------------------
-- vsg_on comment_010
-- vsg_off signal_001
------------------------------<- 80 chars ->------------------------------
--! FPGA RX to Avalon-ST TX interface
--------------------------------------------------------------------------------
-- vsg_on signal_001
-- vsg_off signal_001
------------------------------<- 80 chars ->------------------------------
--------------------------------------------------------------------------------
-- vsg_on signal_001
a <= b;
end architecture rtl;
|
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC ADC 250MS/s core registers
---------------------------------------------------------------------------------------
-- File : wb_fmc516_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from wb_fmc516_regs.wb
-- Created : Thu Apr 11 13:17:23 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc516_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package fmc516_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_fmc516_in_registers is record
fmc_sta_lmk_locked_i : std_logic;
fmc_sta_mmcm_locked_i : std_logic;
fmc_sta_pwr_good_i : std_logic;
fmc_sta_prst_i : std_logic;
fmc_sta_reserved_i : std_logic_vector(27 downto 0);
adc_sta_clk_chains_i : std_logic_vector(3 downto 0);
adc_sta_reserved_clk_chains_i : std_logic_vector(3 downto 0);
adc_sta_data_chains_i : std_logic_vector(3 downto 0);
adc_sta_reserved_data_chains_i : std_logic_vector(3 downto 0);
adc_sta_adc_pkt_size_i : std_logic_vector(15 downto 0);
adc_ctl_reserved_i : std_logic_vector(27 downto 0);
ch0_sta_val_i : std_logic_vector(15 downto 0);
ch0_sta_reserved_i : std_logic_vector(15 downto 0);
ch0_fn_dly_clk_chain_dly_i : std_logic_vector(4 downto 0);
ch0_fn_dly_reserved_clk_chain_dly_i : std_logic_vector(2 downto 0);
ch0_fn_dly_data_chain_dly_i : std_logic_vector(4 downto 0);
ch0_fn_dly_reserved_data_chain_dly_i : std_logic_vector(2 downto 0);
ch1_sta_val_i : std_logic_vector(15 downto 0);
ch1_sta_reserved_i : std_logic_vector(15 downto 0);
ch1_fn_dly_clk_chain_dly_i : std_logic_vector(4 downto 0);
ch1_fn_dly_reserved_clk_chain_dly_i : std_logic_vector(2 downto 0);
ch1_fn_dly_data_chain_dly_i : std_logic_vector(4 downto 0);
ch1_fn_dly_reserved_data_chain_dly_i : std_logic_vector(2 downto 0);
ch2_sta_val_i : std_logic_vector(15 downto 0);
ch2_sta_reserved_i : std_logic_vector(15 downto 0);
ch2_fn_dly_clk_chain_dly_i : std_logic_vector(4 downto 0);
ch2_fn_dly_reserved_clk_chain_dly_i : std_logic_vector(2 downto 0);
ch2_fn_dly_data_chain_dly_i : std_logic_vector(4 downto 0);
ch2_fn_dly_reserved_data_chain_dly_i : std_logic_vector(2 downto 0);
ch3_sta_val_i : std_logic_vector(15 downto 0);
ch3_sta_reserved_i : std_logic_vector(15 downto 0);
ch3_fn_dly_clk_chain_dly_i : std_logic_vector(4 downto 0);
ch3_fn_dly_reserved_clk_chain_dly_i : std_logic_vector(2 downto 0);
ch3_fn_dly_data_chain_dly_i : std_logic_vector(4 downto 0);
ch3_fn_dly_reserved_data_chain_dly_i : std_logic_vector(2 downto 0);
end record;
constant c_fmc516_in_registers_init_value: t_fmc516_in_registers := (
fmc_sta_lmk_locked_i => '0',
fmc_sta_mmcm_locked_i => '0',
fmc_sta_pwr_good_i => '0',
fmc_sta_prst_i => '0',
fmc_sta_reserved_i => (others => '0'),
adc_sta_clk_chains_i => (others => '0'),
adc_sta_reserved_clk_chains_i => (others => '0'),
adc_sta_data_chains_i => (others => '0'),
adc_sta_reserved_data_chains_i => (others => '0'),
adc_sta_adc_pkt_size_i => (others => '0'),
adc_ctl_reserved_i => (others => '0'),
ch0_sta_val_i => (others => '0'),
ch0_sta_reserved_i => (others => '0'),
ch0_fn_dly_clk_chain_dly_i => (others => '0'),
ch0_fn_dly_reserved_clk_chain_dly_i => (others => '0'),
ch0_fn_dly_data_chain_dly_i => (others => '0'),
ch0_fn_dly_reserved_data_chain_dly_i => (others => '0'),
ch1_sta_val_i => (others => '0'),
ch1_sta_reserved_i => (others => '0'),
ch1_fn_dly_clk_chain_dly_i => (others => '0'),
ch1_fn_dly_reserved_clk_chain_dly_i => (others => '0'),
ch1_fn_dly_data_chain_dly_i => (others => '0'),
ch1_fn_dly_reserved_data_chain_dly_i => (others => '0'),
ch2_sta_val_i => (others => '0'),
ch2_sta_reserved_i => (others => '0'),
ch2_fn_dly_clk_chain_dly_i => (others => '0'),
ch2_fn_dly_reserved_clk_chain_dly_i => (others => '0'),
ch2_fn_dly_data_chain_dly_i => (others => '0'),
ch2_fn_dly_reserved_data_chain_dly_i => (others => '0'),
ch3_sta_val_i => (others => '0'),
ch3_sta_reserved_i => (others => '0'),
ch3_fn_dly_clk_chain_dly_i => (others => '0'),
ch3_fn_dly_reserved_clk_chain_dly_i => (others => '0'),
ch3_fn_dly_data_chain_dly_i => (others => '0'),
ch3_fn_dly_reserved_data_chain_dly_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_fmc516_out_registers is record
fmc_ctl_test_data_en_o : std_logic;
fmc_ctl_led_0_o : std_logic;
fmc_ctl_led_1_o : std_logic;
fmc_ctl_clk_sel_o : std_logic;
fmc_ctl_vcxo_out_en_o : std_logic;
fmc_ctl_reserved_o : std_logic_vector(26 downto 0);
trig_cfg_hw_trig_pol_o : std_logic;
trig_cfg_hw_trig_en_o : std_logic;
trig_cfg_reserved_o : std_logic_vector(29 downto 0);
adc_ctl_update_clk_dly_o : std_logic;
adc_ctl_update_data_dly_o : std_logic;
adc_ctl_rst_adcs_o : std_logic;
adc_ctl_rst_div_adcs_o : std_logic;
ch0_fn_dly_clk_chain_dly_o : std_logic_vector(4 downto 0);
ch0_fn_dly_clk_chain_dly_load_o : std_logic;
ch0_fn_dly_data_chain_dly_o : std_logic_vector(4 downto 0);
ch0_fn_dly_data_chain_dly_load_o : std_logic;
ch0_fn_dly_inc_clk_chain_dly_o : std_logic;
ch0_fn_dly_dec_clk_chain_dly_o : std_logic;
ch0_fn_dly_reserved_clk_incdec_dly_o : std_logic_vector(5 downto 0);
ch0_fn_dly_inc_data_chain_dly_o : std_logic;
ch0_fn_dly_dec_data_chain_dly_o : std_logic;
ch0_fn_dly_reserved_data_incdec_dly_o : std_logic_vector(5 downto 0);
ch0_cs_dly_fe_dly_o : std_logic_vector(1 downto 0);
ch0_cs_dly_reserved_fe_dly_o : std_logic_vector(5 downto 0);
ch0_cs_dly_rg_dly_o : std_logic_vector(1 downto 0);
ch0_cs_dly_reserved_rg_dly_o : std_logic_vector(21 downto 0);
ch1_fn_dly_clk_chain_dly_o : std_logic_vector(4 downto 0);
ch1_fn_dly_clk_chain_dly_load_o : std_logic;
ch1_fn_dly_data_chain_dly_o : std_logic_vector(4 downto 0);
ch1_fn_dly_data_chain_dly_load_o : std_logic;
ch1_fn_dly_inc_clk_chain_dly_o : std_logic;
ch1_fn_dly_dec_clk_chain_dly_o : std_logic;
ch1_fn_dly_reserved_clk_incdec_dly_o : std_logic_vector(5 downto 0);
ch1_fn_dly_inc_data_chain_dly_o : std_logic;
ch1_fn_dly_dec_data_chain_dly_o : std_logic;
ch1_fn_dly_reserved_data_incdec_dly_o : std_logic_vector(5 downto 0);
ch1_cs_dly_fe_dly_o : std_logic_vector(1 downto 0);
ch1_cs_dly_reserved_fe_dly_o : std_logic_vector(5 downto 0);
ch1_cs_dly_rg_dly_o : std_logic_vector(1 downto 0);
ch1_cs_dly_reserved_rg_dly_o : std_logic_vector(21 downto 0);
ch2_fn_dly_clk_chain_dly_o : std_logic_vector(4 downto 0);
ch2_fn_dly_clk_chain_dly_load_o : std_logic;
ch2_fn_dly_data_chain_dly_o : std_logic_vector(4 downto 0);
ch2_fn_dly_data_chain_dly_load_o : std_logic;
ch2_fn_dly_inc_clk_chain_dly_o : std_logic;
ch2_fn_dly_dec_clk_chain_dly_o : std_logic;
ch2_fn_dly_reserved_clk_incdec_dly_o : std_logic_vector(5 downto 0);
ch2_fn_dly_inc_data_chain_dly_o : std_logic;
ch2_fn_dly_dec_data_chain_dly_o : std_logic;
ch2_fn_dly_reserved_data_incdec_dly_o : std_logic_vector(5 downto 0);
ch2_cs_dly_fe_dly_o : std_logic_vector(1 downto 0);
ch2_cs_dly_reserved_fe_dly_o : std_logic_vector(5 downto 0);
ch2_cs_dly_rg_dly_o : std_logic_vector(1 downto 0);
ch2_cs_dly_reserved_rg_dly_o : std_logic_vector(21 downto 0);
ch3_fn_dly_clk_chain_dly_o : std_logic_vector(4 downto 0);
ch3_fn_dly_clk_chain_dly_load_o : std_logic;
ch3_fn_dly_data_chain_dly_o : std_logic_vector(4 downto 0);
ch3_fn_dly_data_chain_dly_load_o : std_logic;
ch3_fn_dly_inc_clk_chain_dly_o : std_logic;
ch3_fn_dly_dec_clk_chain_dly_o : std_logic;
ch3_fn_dly_reserved_clk_incdec_dly_o : std_logic_vector(5 downto 0);
ch3_fn_dly_inc_data_chain_dly_o : std_logic;
ch3_fn_dly_dec_data_chain_dly_o : std_logic;
ch3_fn_dly_reserved_data_incdec_dly_o : std_logic_vector(5 downto 0);
ch3_cs_dly_fe_dly_o : std_logic_vector(1 downto 0);
ch3_cs_dly_reserved_fe_dly_o : std_logic_vector(5 downto 0);
ch3_cs_dly_rg_dly_o : std_logic_vector(1 downto 0);
ch3_cs_dly_reserved_rg_dly_o : std_logic_vector(21 downto 0);
end record;
constant c_fmc516_out_registers_init_value: t_fmc516_out_registers := (
fmc_ctl_test_data_en_o => '0',
fmc_ctl_led_0_o => '0',
fmc_ctl_led_1_o => '0',
fmc_ctl_clk_sel_o => '0',
fmc_ctl_vcxo_out_en_o => '0',
fmc_ctl_reserved_o => (others => '0'),
trig_cfg_hw_trig_pol_o => '0',
trig_cfg_hw_trig_en_o => '0',
trig_cfg_reserved_o => (others => '0'),
adc_ctl_update_clk_dly_o => '0',
adc_ctl_update_data_dly_o => '0',
adc_ctl_rst_adcs_o => '0',
adc_ctl_rst_div_adcs_o => '0',
ch0_fn_dly_clk_chain_dly_o => (others => '0'),
ch0_fn_dly_clk_chain_dly_load_o => '0',
ch0_fn_dly_data_chain_dly_o => (others => '0'),
ch0_fn_dly_data_chain_dly_load_o => '0',
ch0_fn_dly_inc_clk_chain_dly_o => '0',
ch0_fn_dly_dec_clk_chain_dly_o => '0',
ch0_fn_dly_reserved_clk_incdec_dly_o => (others => '0'),
ch0_fn_dly_inc_data_chain_dly_o => '0',
ch0_fn_dly_dec_data_chain_dly_o => '0',
ch0_fn_dly_reserved_data_incdec_dly_o => (others => '0'),
ch0_cs_dly_fe_dly_o => (others => '0'),
ch0_cs_dly_reserved_fe_dly_o => (others => '0'),
ch0_cs_dly_rg_dly_o => (others => '0'),
ch0_cs_dly_reserved_rg_dly_o => (others => '0'),
ch1_fn_dly_clk_chain_dly_o => (others => '0'),
ch1_fn_dly_clk_chain_dly_load_o => '0',
ch1_fn_dly_data_chain_dly_o => (others => '0'),
ch1_fn_dly_data_chain_dly_load_o => '0',
ch1_fn_dly_inc_clk_chain_dly_o => '0',
ch1_fn_dly_dec_clk_chain_dly_o => '0',
ch1_fn_dly_reserved_clk_incdec_dly_o => (others => '0'),
ch1_fn_dly_inc_data_chain_dly_o => '0',
ch1_fn_dly_dec_data_chain_dly_o => '0',
ch1_fn_dly_reserved_data_incdec_dly_o => (others => '0'),
ch1_cs_dly_fe_dly_o => (others => '0'),
ch1_cs_dly_reserved_fe_dly_o => (others => '0'),
ch1_cs_dly_rg_dly_o => (others => '0'),
ch1_cs_dly_reserved_rg_dly_o => (others => '0'),
ch2_fn_dly_clk_chain_dly_o => (others => '0'),
ch2_fn_dly_clk_chain_dly_load_o => '0',
ch2_fn_dly_data_chain_dly_o => (others => '0'),
ch2_fn_dly_data_chain_dly_load_o => '0',
ch2_fn_dly_inc_clk_chain_dly_o => '0',
ch2_fn_dly_dec_clk_chain_dly_o => '0',
ch2_fn_dly_reserved_clk_incdec_dly_o => (others => '0'),
ch2_fn_dly_inc_data_chain_dly_o => '0',
ch2_fn_dly_dec_data_chain_dly_o => '0',
ch2_fn_dly_reserved_data_incdec_dly_o => (others => '0'),
ch2_cs_dly_fe_dly_o => (others => '0'),
ch2_cs_dly_reserved_fe_dly_o => (others => '0'),
ch2_cs_dly_rg_dly_o => (others => '0'),
ch2_cs_dly_reserved_rg_dly_o => (others => '0'),
ch3_fn_dly_clk_chain_dly_o => (others => '0'),
ch3_fn_dly_clk_chain_dly_load_o => '0',
ch3_fn_dly_data_chain_dly_o => (others => '0'),
ch3_fn_dly_data_chain_dly_load_o => '0',
ch3_fn_dly_inc_clk_chain_dly_o => '0',
ch3_fn_dly_dec_clk_chain_dly_o => '0',
ch3_fn_dly_reserved_clk_incdec_dly_o => (others => '0'),
ch3_fn_dly_inc_data_chain_dly_o => '0',
ch3_fn_dly_dec_data_chain_dly_o => '0',
ch3_fn_dly_reserved_data_incdec_dly_o => (others => '0'),
ch3_cs_dly_fe_dly_o => (others => '0'),
ch3_cs_dly_reserved_fe_dly_o => (others => '0'),
ch3_cs_dly_rg_dly_o => (others => '0'),
ch3_cs_dly_reserved_rg_dly_o => (others => '0')
);
function "or" (left, right: t_fmc516_in_registers) return t_fmc516_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body fmc516_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_fmc516_in_registers) return t_fmc516_in_registers is
variable tmp: t_fmc516_in_registers;
begin
tmp.fmc_sta_lmk_locked_i := f_x_to_zero(left.fmc_sta_lmk_locked_i) or f_x_to_zero(right.fmc_sta_lmk_locked_i);
tmp.fmc_sta_mmcm_locked_i := f_x_to_zero(left.fmc_sta_mmcm_locked_i) or f_x_to_zero(right.fmc_sta_mmcm_locked_i);
tmp.fmc_sta_pwr_good_i := f_x_to_zero(left.fmc_sta_pwr_good_i) or f_x_to_zero(right.fmc_sta_pwr_good_i);
tmp.fmc_sta_prst_i := f_x_to_zero(left.fmc_sta_prst_i) or f_x_to_zero(right.fmc_sta_prst_i);
tmp.fmc_sta_reserved_i := f_x_to_zero(left.fmc_sta_reserved_i) or f_x_to_zero(right.fmc_sta_reserved_i);
tmp.adc_sta_clk_chains_i := f_x_to_zero(left.adc_sta_clk_chains_i) or f_x_to_zero(right.adc_sta_clk_chains_i);
tmp.adc_sta_reserved_clk_chains_i := f_x_to_zero(left.adc_sta_reserved_clk_chains_i) or f_x_to_zero(right.adc_sta_reserved_clk_chains_i);
tmp.adc_sta_data_chains_i := f_x_to_zero(left.adc_sta_data_chains_i) or f_x_to_zero(right.adc_sta_data_chains_i);
tmp.adc_sta_reserved_data_chains_i := f_x_to_zero(left.adc_sta_reserved_data_chains_i) or f_x_to_zero(right.adc_sta_reserved_data_chains_i);
tmp.adc_sta_adc_pkt_size_i := f_x_to_zero(left.adc_sta_adc_pkt_size_i) or f_x_to_zero(right.adc_sta_adc_pkt_size_i);
tmp.adc_ctl_reserved_i := f_x_to_zero(left.adc_ctl_reserved_i) or f_x_to_zero(right.adc_ctl_reserved_i);
tmp.ch0_sta_val_i := f_x_to_zero(left.ch0_sta_val_i) or f_x_to_zero(right.ch0_sta_val_i);
tmp.ch0_sta_reserved_i := f_x_to_zero(left.ch0_sta_reserved_i) or f_x_to_zero(right.ch0_sta_reserved_i);
tmp.ch0_fn_dly_clk_chain_dly_i := f_x_to_zero(left.ch0_fn_dly_clk_chain_dly_i) or f_x_to_zero(right.ch0_fn_dly_clk_chain_dly_i);
tmp.ch0_fn_dly_reserved_clk_chain_dly_i := f_x_to_zero(left.ch0_fn_dly_reserved_clk_chain_dly_i) or f_x_to_zero(right.ch0_fn_dly_reserved_clk_chain_dly_i);
tmp.ch0_fn_dly_data_chain_dly_i := f_x_to_zero(left.ch0_fn_dly_data_chain_dly_i) or f_x_to_zero(right.ch0_fn_dly_data_chain_dly_i);
tmp.ch0_fn_dly_reserved_data_chain_dly_i := f_x_to_zero(left.ch0_fn_dly_reserved_data_chain_dly_i) or f_x_to_zero(right.ch0_fn_dly_reserved_data_chain_dly_i);
tmp.ch1_sta_val_i := f_x_to_zero(left.ch1_sta_val_i) or f_x_to_zero(right.ch1_sta_val_i);
tmp.ch1_sta_reserved_i := f_x_to_zero(left.ch1_sta_reserved_i) or f_x_to_zero(right.ch1_sta_reserved_i);
tmp.ch1_fn_dly_clk_chain_dly_i := f_x_to_zero(left.ch1_fn_dly_clk_chain_dly_i) or f_x_to_zero(right.ch1_fn_dly_clk_chain_dly_i);
tmp.ch1_fn_dly_reserved_clk_chain_dly_i := f_x_to_zero(left.ch1_fn_dly_reserved_clk_chain_dly_i) or f_x_to_zero(right.ch1_fn_dly_reserved_clk_chain_dly_i);
tmp.ch1_fn_dly_data_chain_dly_i := f_x_to_zero(left.ch1_fn_dly_data_chain_dly_i) or f_x_to_zero(right.ch1_fn_dly_data_chain_dly_i);
tmp.ch1_fn_dly_reserved_data_chain_dly_i := f_x_to_zero(left.ch1_fn_dly_reserved_data_chain_dly_i) or f_x_to_zero(right.ch1_fn_dly_reserved_data_chain_dly_i);
tmp.ch2_sta_val_i := f_x_to_zero(left.ch2_sta_val_i) or f_x_to_zero(right.ch2_sta_val_i);
tmp.ch2_sta_reserved_i := f_x_to_zero(left.ch2_sta_reserved_i) or f_x_to_zero(right.ch2_sta_reserved_i);
tmp.ch2_fn_dly_clk_chain_dly_i := f_x_to_zero(left.ch2_fn_dly_clk_chain_dly_i) or f_x_to_zero(right.ch2_fn_dly_clk_chain_dly_i);
tmp.ch2_fn_dly_reserved_clk_chain_dly_i := f_x_to_zero(left.ch2_fn_dly_reserved_clk_chain_dly_i) or f_x_to_zero(right.ch2_fn_dly_reserved_clk_chain_dly_i);
tmp.ch2_fn_dly_data_chain_dly_i := f_x_to_zero(left.ch2_fn_dly_data_chain_dly_i) or f_x_to_zero(right.ch2_fn_dly_data_chain_dly_i);
tmp.ch2_fn_dly_reserved_data_chain_dly_i := f_x_to_zero(left.ch2_fn_dly_reserved_data_chain_dly_i) or f_x_to_zero(right.ch2_fn_dly_reserved_data_chain_dly_i);
tmp.ch3_sta_val_i := f_x_to_zero(left.ch3_sta_val_i) or f_x_to_zero(right.ch3_sta_val_i);
tmp.ch3_sta_reserved_i := f_x_to_zero(left.ch3_sta_reserved_i) or f_x_to_zero(right.ch3_sta_reserved_i);
tmp.ch3_fn_dly_clk_chain_dly_i := f_x_to_zero(left.ch3_fn_dly_clk_chain_dly_i) or f_x_to_zero(right.ch3_fn_dly_clk_chain_dly_i);
tmp.ch3_fn_dly_reserved_clk_chain_dly_i := f_x_to_zero(left.ch3_fn_dly_reserved_clk_chain_dly_i) or f_x_to_zero(right.ch3_fn_dly_reserved_clk_chain_dly_i);
tmp.ch3_fn_dly_data_chain_dly_i := f_x_to_zero(left.ch3_fn_dly_data_chain_dly_i) or f_x_to_zero(right.ch3_fn_dly_data_chain_dly_i);
tmp.ch3_fn_dly_reserved_data_chain_dly_i := f_x_to_zero(left.ch3_fn_dly_reserved_data_chain_dly_i) or f_x_to_zero(right.ch3_fn_dly_reserved_data_chain_dly_i);
return tmp;
end function;
end package body;
|
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
end;
|
use work.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu_testbench is
end;
architecture behavioral of alu_testbench is
constant TB_WIDTH : integer := 8;
signal a, b, q : std_logic_vector(TB_WIDTH-1 downto 0);
signal ctrl : std_logic_vector (1 DOWNTO 0);
signal cout, cin : std_logic := '0';
component alu
generic (
WIDTH: INTEGER:= TB_WIDTH);
port (
a : in std_logic_vector (WIDTH-1 downto 0);
b : in std_logic_vector (WIDTH-1 downto 0);
cin : in std_logic;
ctrl : in std_logic_vector ( 1 downto 0);
cout : out std_logic;
q : out std_logic_vector (WIDTH-1 downto 0));
end component;
function to_std_logicvector(a: integer; length: natural) return std_logic_vector IS
begin
return std_logic_vector(to_signed(a,length));
end;
procedure behave_alu(a: integer; b: integer; ctrl: integer; q: out std_logic_vector(TB_WIDTH-1 downto 0); cout: out std_logic) is
variable ret: std_logic_vector(TB_WIDTH downto 0);
begin
case ctrl is
when 0 => ret := to_std_logicvector(a+b, TB_WIDTH+1);
when 1 => ret := to_std_logicvector(a-b,TB_WIDTH+1);
ret(TB_WIDTH):= not ret(TB_WIDTH);
when 2 => ret := '0' & (to_std_logicvector(a,TB_WIDTH) nand to_std_logicvector(b,TB_WIDTH));
when 3 => ret := '0' & (to_std_logicvector(a,TB_WIDTH) nor to_std_logicvector(b,TB_WIDTH));
when OTHERS =>
assert false
report "ctrl out of range, testbench error"
severity error;
end case;
q := ret(TB_WIDTH-1 downto 0);
cout := ret(TB_WIDTH);
end;
begin process
variable res: std_logic_vector ( TB_WIDTH-1 downto 0);
variable c: std_logic;
begin
for i in 0 to TB_WIDTH-1 loop
a <= to_std_logicvector(i,TB_WIDTH);
for j in 0 to TB_WIDTH loop
b <= to_std_logicvector(j,TB_WIDTH);
for k in 0 to 1 loop
ctrl<= to_std_logicvector(k,3)(1 downto 0);
wait for 10 ns;
behave_alu(i,j,k,res,c);
assert q = res
report "wrong result from ALU:" & integer'image(to_integer(unsigned(res))) & " a:" & integer'image(to_integer(unsigned(a))) & " b:" & integer'image(to_integer(unsigned(b))) & " ctrl:" & integer'image(to_integer(unsigned(ctrl)))
severity warning;
assert cout = c
report "wrong carry from ALU:" & std_logic'image(cout) & " expected:" & std_logic'image(c) & " a:" & integer'image(to_integer(unsigned(a))) & " b:" & integer'image(to_integer(unsigned(b))) & " ctrl:" & integer'image(to_integer(unsigned(ctrl)))
severity warning;
end loop;
end loop;
end loop;
report "ALU testbench finished";
wait;
end process;
uut: alu port map (a, b, cin, ctrl, cout, q);
end behavioral;
|
-------------------------------------------------------------------------------
-- mdio_if.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : mdio_if.vhd
-- Version : v2.0
-- Description : This entity provides the interface between the physical layer
-- management control, and the host interface through the MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- MDIO_Clk -- 2.5Mhz clock
-- MDIO_en -- MDIO enable
-- MDIO_OP -- MDIO OP code
-- MDIO_Req -- MDIO transmission request
-- MDIO_PHY_AD -- The physical layer address
-- MDIO_REG_AD -- The individual register address
-- MDIO_WR_DATA -- The data to be written on MDIO
-- MDIO_RD_DATA -- The data read from MDIO
-- PHY_MDIO_I -- MDIO Tri-state input from PHY
-- PHY_MDIO_O -- MDIO Tri-state output to PHY
-- PHY_MDIO_T -- MDIO Tri-state control
-- PHY_MDC -- 2.5Mhz communication clock to PHY
-- MDIO_done -- RX FIFO read ack
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity mdio_if is
port (
Clk : in std_logic; -- System Clock
Rst : in std_logic; -- System Reset
MDIO_Clk : in std_logic; -- 2.5Mhz clock
MDIO_en : in std_logic; -- MDIO enable
MDIO_OP : in std_logic; -- MDIO OP code
MDIO_Req : in std_logic; -- MDIO transmission request
MDIO_PHY_AD : in std_logic_vector(4 downto 0);
-- The physical layer address
MDIO_REG_AD : in std_logic_vector(4 downto 0);
-- The individual register address
MDIO_WR_DATA : in std_logic_vector(15 downto 0);
-- The data to be written on MDIO
MDIO_RD_DATA : out std_logic_vector(15 downto 0);
-- The data read from MDIO
PHY_MDIO_I : in std_logic; -- MDIO Tri-state input from PHY
PHY_MDIO_O : out std_logic; -- MDIO Tri-state output to PHY
PHY_MDIO_T : out std_logic; -- MDIO Tri-state control
PHY_MDC : out std_logic; -- 2.5Mhz communication clock
MDIO_done : out std_logic -- MDIO tranfer done indicator
);
end mdio_if;
architecture imp of mdio_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
type mdio_state_type is (IDLE, PREAMBLE, ST1, ST2, OP1, OP2, TA1, TA2,
PHY_ADDR, REG_ADDR, WRITE, READ, DONE);
signal mdio_state, next_state : mdio_state_type;
signal mdio_xfer_done : std_logic; -- pulse to inidcate end of activity
signal mdio_idle : std_logic; -- internal READY signal
signal rd_data_en : std_logic_vector(15 downto 0); -- decoded write
-- MDIO_en for RD_DATA
signal mdio_en_reg : std_logic; -- MDIO_en signal latched at start of
-- transmission
signal mdio_o_cmb : std_logic; -- rising edge version of MDIO_OUT
signal mdio_t_comb : std_logic; -- combinatorial term to produce
-- MDIO_TRISTATE
signal mdio_clk_reg : std_logic; -- registering MDIO_Clk to use it as a
-- clock MDIO_en
signal mdio_in_reg1 : std_logic; -- compensate in pipeline delay caused
-- by using MDC as a clock MDIO_en
signal mdio_in_reg2 : std_logic; -- compensate in pipeline delay caused by
-- using MDC as a clock MDIO_en
signal clk_cnt : integer range 0 to 32; -- Clk counter
signal ld_cnt_data_cmb : integer range 0 to 32; -- Counter load comb
signal ld_cnt_data_reg : integer range 0 to 32; -- Counter load reg
signal ld_cnt_en_cmb : std_logic; -- Counter load enable
signal clk_cnt_en : std_logic; -- Counter enable
signal mdc_falling : std_logic; -- MDC falling edge
signal mdc_rising : std_logic; -- MDC rising edge
signal ld_cnt_en_reg : std_logic; -- Counter load enable reg
begin
----------------------------------------------------------------------------
-- PROCESS : INPUT_REG_CLK
----------------------------------------------------------------------------
-- Registering PHY_MDIO_I and MDC signals w.r.t SAXI clock.
----------------------------------------------------------------------------
INPUT_REG_CLK: process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_clk_reg <= '0';
mdio_in_reg1 <= '0';
mdio_in_reg2 <= '0';
else
mdio_clk_reg <= MDIO_Clk;
mdio_in_reg1 <= PHY_MDIO_I;
mdio_in_reg2 <= mdio_in_reg1;
end if;
end if;
end process INPUT_REG_CLK;
-- Falling edge and rising edge generation of MDC clock
mdc_falling <= not MDIO_Clk and mdio_clk_reg;
mdc_rising <= MDIO_Clk and not mdio_clk_reg;
-- Enable MDC only when MDIO interface is enabled.
PHY_MDC <= MDIO_Clk; -- making the MDC clk contineous
--PHY_MDC <= MDIO_Clk and mdio_en_reg;
-- Informs MDIO interface about the MDIO transfer complete.
MDIO_done <= mdio_xfer_done;
----------------------------------------------------------------------------
-- PROCESS : REG_MDIO_en
----------------------------------------------------------------------------
-- Latch MDIO_en bit on falling edge of MDC and when MDIO master is IDLE.
-- MDIO Master will complete the existing transfer even if MDIO interface
-- is disable in middle of the transaction.
----------------------------------------------------------------------------
REG_MDIO_en : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_en_reg <= '0';
elsif mdc_falling='1' then
if mdio_idle = '1' then
mdio_en_reg <= MDIO_en;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : PHY_MDIO_T_REG
----------------------------------------------------------------------------
-- The mdio_t_comb signal is driven high only for read operation starting
-- from the Turn arround state.
-- It is driven on falling clock edge to match up with PHY_MDIO_O
----------------------------------------------------------------------------
PHY_MDIO_T_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
PHY_MDIO_T <= '1';
elsif (mdc_falling='1') then -- falling edge of MDC
PHY_MDIO_T <= mdio_t_comb;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : PHY_MDIO_O_REG
----------------------------------------------------------------------------
-- Generating PHY_MDIO_O output singnal on falling edge of MDC
----------------------------------------------------------------------------
PHY_MDIO_O_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
PHY_MDIO_O <= '0';
elsif (mdc_falling='1') then -- falling edge of MDC
PHY_MDIO_O <= mdio_o_cmb;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : MDIO_IDLE_REG
----------------------------------------------------------------------------
-- The mdio_idle signal is used to indicate no activity on the MDIO.
-- Set at reset amd at the end of transmission.
-- Rst at start of transmission as long as device is MDIO_end
----------------------------------------------------------------------------
MDIO_IDLE_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_idle <= '1';
elsif (mdc_rising='1') then -- rising edge of MDC
if (mdio_xfer_done = '1') then
mdio_idle <= '1';
elsif (MDIO_Req = '1' and mdio_en_reg = '1') then
mdio_idle <= '0';
end if;
end if;
end if;
end process ;
----------------------------------------------------------------------------
-- PROCESS : MDIO_CAPTURE_DATA
----------------------------------------------------------------------------
-- This process captures registered PHY_MDIO_i input on rising edge of the
-- MDC clock. The rd_data_en signal is generated in MDIO State machine for
-- respective captured bit.
----------------------------------------------------------------------------
MDIO_CAPTURE_DATA : for i in 15 downto 0 generate
MDIO_DATA_IN : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
MDIO_RD_DATA(i) <= '0';
elsif (mdc_rising='1') then -- rising edge of MDC
if(rd_data_en(i) = '1') then
MDIO_RD_DATA(i) <= mdio_in_reg2;
end if;
end if;
end if;
end process MDIO_DATA_IN;
end generate;
----------------------------------------------------------------------------
-- PROCESS : MDIO_DOWN_COUNTER
----------------------------------------------------------------------------
-- This counter is used in Preamble and PHY_ADDR and REG_ADDR state.
-- This counter is loaded for the required values for each above states.
----------------------------------------------------------------------------
MDIO_DOWN_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
clk_cnt <= 0;
elsif (mdc_rising='1') then -- falling edge of MDC
if (ld_cnt_en_reg = '1') then -- Load counter with load data
clk_cnt <= ld_cnt_data_reg;
elsif (clk_cnt_en='1') then -- Enable Down Counter
clk_cnt <= clk_cnt - 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : MDIO_NEXT_STATE_GEN
----------------------------------------------------------------------------
-- MDIO next state register process
----------------------------------------------------------------------------
MDIO_NEXT_STATE_GEN : process (Clk)
begin
if Clk'event and Clk = '1' then
if (Rst = '1') then
mdio_state <= IDLE;
elsif (mdc_rising='1') then
mdio_state <= next_state;
end if;
end if;
end process MDIO_NEXT_STATE_GEN;
----------------------------------------------------------------------------
-- PROCESS : MDIO_COMB_REG_GEN
----------------------------------------------------------------------------
-- Combinational signal register process
----------------------------------------------------------------------------
MDIO_COMB_REG_GEN : process (Clk)
begin
if Clk'event and Clk = '1' then
if (Rst = '1') then
ld_cnt_data_reg <= 0;
ld_cnt_en_reg <= '0';
else
ld_cnt_data_reg <= ld_cnt_data_cmb;
ld_cnt_en_reg <= ld_cnt_en_cmb;
end if;
end if;
end process MDIO_COMB_REG_GEN;
----------------------------------------------------------------------------
-- PROCESS : MDIO_STATE_COMB
----------------------------------------------------------------------------
-- This process generates mdio_o_cmb signal in command and Write phase as
-- per the required MDIO protocol. This process also generate mdio_t_comb
-- tristate signal and rd_data_en to capture the respective bit in Read
-- operation.
----------------------------------------------------------------------------
MDIO_STATE_COMB : process (mdio_state, mdio_idle, clk_cnt, MDIO_OP,
MDIO_PHY_AD, MDIO_REG_AD, MDIO_WR_DATA)
begin
-- state machine defaults
mdio_o_cmb <= '1';
rd_data_en <= "0000000000000000";
mdio_xfer_done <= '0';
ld_cnt_en_cmb <= '0';
clk_cnt_en <= '0';
mdio_t_comb <= '0';
next_state <= mdio_state;
ld_cnt_data_cmb <= 0;
case mdio_state is
when IDLE =>
mdio_o_cmb <= '1';
mdio_t_comb <= '1';
ld_cnt_en_cmb <= '1';
-- leave IDLE state when new mdio request is received.
if mdio_idle = '0' then
-- Load counter for 32-bit preamble
ld_cnt_data_cmb <= 31;
next_state <= PREAMBLE;
end if;
when PREAMBLE =>
clk_cnt_en <= '1';
-- Move to ST1 after 32-bit preamble.
if clk_cnt = 0 then
next_state <= ST1;
clk_cnt_en <= '0';
end if;
when ST1 => -- Start Code-1
mdio_o_cmb <= '0';
next_state <= ST2;
when ST2 => -- Start Code-2
mdio_o_cmb <= '1';
next_state <= OP1;
when OP1 => -- Opcode-1
next_state <= OP2;
if MDIO_OP='1' then
mdio_o_cmb <= '1';
else
mdio_o_cmb <= '0';
end if;
when OP2 => -- Opcode-2
next_state <= PHY_ADDR;
-- Load counter for 5-bit PHYaddress transfer
ld_cnt_data_cmb <= 4;
ld_cnt_en_cmb <= '1';
if MDIO_OP='1' then
mdio_o_cmb <= '0';
else
mdio_o_cmb <= '1';
end if;
when PHY_ADDR => -- PHY Device Address
clk_cnt_en <= '1';
mdio_o_cmb <= MDIO_PHY_AD(clk_cnt);
-- Send 5-bit PHY device address
if clk_cnt=0 then
next_state <= REG_ADDR;
-- Load counter for 5-bit REG address transfer
ld_cnt_data_cmb <= 4;
ld_cnt_en_cmb <= '1';
end if;
when REG_ADDR => -- PHY Device Address
clk_cnt_en <= '1';
mdio_o_cmb <= MDIO_REG_AD(clk_cnt);
-- Send 5-bit PHY Register address
if clk_cnt=0 then
next_state <= TA1;
clk_cnt_en <= '0';
end if;
when TA1 => -- Turn Around Time-1
mdio_o_cmb <= '1';
next_state <= TA2;
-- For Read operation generate high impedence on
-- MDIO bus
if MDIO_OP='1' then
mdio_t_comb <= '1';
else
mdio_t_comb <= '0';
end if;
when TA2 => -- Turn Around Time-2
mdio_o_cmb <= '0';
-- Load the down counter for 16 bit data transfer
ld_cnt_data_cmb <= 15;
ld_cnt_en_cmb <= '1';
-- Move to Write state if opcode is '0'
if MDIO_OP='0' then
next_state <= WRITE;
mdio_t_comb <= '0';
else
next_state <= READ;
mdio_t_comb <= '1';
end if;
when WRITE => -- MDIO DATA Write
clk_cnt_en <= '1';
-- Send 16-bit Write Data on the MDIO data line
mdio_o_cmb <= MDIO_WR_DATA(clk_cnt);
-- Wait for 16 bit transfer
if clk_cnt=0 then
next_state <= DONE;
clk_cnt_en <= '0';
end if;
when READ => -- MDIO DATA Read
clk_cnt_en <= '1';
mdio_t_comb <= '1';
-- Generate read data enable for respective bit
rd_data_en(clk_cnt) <= '1';
-- Wait for 16 bit transfer
if clk_cnt=0 then
next_state <= DONE;
clk_cnt_en <= '0';
end if;
when DONE => -- MDIO Transfer Done
mdio_o_cmb <= '1';
mdio_t_comb <= '1';
next_state <= IDLE;
-- Mdio trasnfer complete
mdio_xfer_done <= '1';
-- coverage off
when others =>
next_state <= IDLE;
-- coverage on
end case;
end process MDIO_STATE_COMB;
end imp;
|
-------------------------------------------------------------------------------
-- mdio_if.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : mdio_if.vhd
-- Version : v2.0
-- Description : This entity provides the interface between the physical layer
-- management control, and the host interface through the MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- MDIO_Clk -- 2.5Mhz clock
-- MDIO_en -- MDIO enable
-- MDIO_OP -- MDIO OP code
-- MDIO_Req -- MDIO transmission request
-- MDIO_PHY_AD -- The physical layer address
-- MDIO_REG_AD -- The individual register address
-- MDIO_WR_DATA -- The data to be written on MDIO
-- MDIO_RD_DATA -- The data read from MDIO
-- PHY_MDIO_I -- MDIO Tri-state input from PHY
-- PHY_MDIO_O -- MDIO Tri-state output to PHY
-- PHY_MDIO_T -- MDIO Tri-state control
-- PHY_MDC -- 2.5Mhz communication clock to PHY
-- MDIO_done -- RX FIFO read ack
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity mdio_if is
port (
Clk : in std_logic; -- System Clock
Rst : in std_logic; -- System Reset
MDIO_Clk : in std_logic; -- 2.5Mhz clock
MDIO_en : in std_logic; -- MDIO enable
MDIO_OP : in std_logic; -- MDIO OP code
MDIO_Req : in std_logic; -- MDIO transmission request
MDIO_PHY_AD : in std_logic_vector(4 downto 0);
-- The physical layer address
MDIO_REG_AD : in std_logic_vector(4 downto 0);
-- The individual register address
MDIO_WR_DATA : in std_logic_vector(15 downto 0);
-- The data to be written on MDIO
MDIO_RD_DATA : out std_logic_vector(15 downto 0);
-- The data read from MDIO
PHY_MDIO_I : in std_logic; -- MDIO Tri-state input from PHY
PHY_MDIO_O : out std_logic; -- MDIO Tri-state output to PHY
PHY_MDIO_T : out std_logic; -- MDIO Tri-state control
PHY_MDC : out std_logic; -- 2.5Mhz communication clock
MDIO_done : out std_logic -- MDIO tranfer done indicator
);
end mdio_if;
architecture imp of mdio_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
type mdio_state_type is (IDLE, PREAMBLE, ST1, ST2, OP1, OP2, TA1, TA2,
PHY_ADDR, REG_ADDR, WRITE, READ, DONE);
signal mdio_state, next_state : mdio_state_type;
signal mdio_xfer_done : std_logic; -- pulse to inidcate end of activity
signal mdio_idle : std_logic; -- internal READY signal
signal rd_data_en : std_logic_vector(15 downto 0); -- decoded write
-- MDIO_en for RD_DATA
signal mdio_en_reg : std_logic; -- MDIO_en signal latched at start of
-- transmission
signal mdio_o_cmb : std_logic; -- rising edge version of MDIO_OUT
signal mdio_t_comb : std_logic; -- combinatorial term to produce
-- MDIO_TRISTATE
signal mdio_clk_reg : std_logic; -- registering MDIO_Clk to use it as a
-- clock MDIO_en
signal mdio_in_reg1 : std_logic; -- compensate in pipeline delay caused
-- by using MDC as a clock MDIO_en
signal mdio_in_reg2 : std_logic; -- compensate in pipeline delay caused by
-- using MDC as a clock MDIO_en
signal clk_cnt : integer range 0 to 32; -- Clk counter
signal ld_cnt_data_cmb : integer range 0 to 32; -- Counter load comb
signal ld_cnt_data_reg : integer range 0 to 32; -- Counter load reg
signal ld_cnt_en_cmb : std_logic; -- Counter load enable
signal clk_cnt_en : std_logic; -- Counter enable
signal mdc_falling : std_logic; -- MDC falling edge
signal mdc_rising : std_logic; -- MDC rising edge
signal ld_cnt_en_reg : std_logic; -- Counter load enable reg
begin
----------------------------------------------------------------------------
-- PROCESS : INPUT_REG_CLK
----------------------------------------------------------------------------
-- Registering PHY_MDIO_I and MDC signals w.r.t SAXI clock.
----------------------------------------------------------------------------
INPUT_REG_CLK: process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_clk_reg <= '0';
mdio_in_reg1 <= '0';
mdio_in_reg2 <= '0';
else
mdio_clk_reg <= MDIO_Clk;
mdio_in_reg1 <= PHY_MDIO_I;
mdio_in_reg2 <= mdio_in_reg1;
end if;
end if;
end process INPUT_REG_CLK;
-- Falling edge and rising edge generation of MDC clock
mdc_falling <= not MDIO_Clk and mdio_clk_reg;
mdc_rising <= MDIO_Clk and not mdio_clk_reg;
-- Enable MDC only when MDIO interface is enabled.
PHY_MDC <= MDIO_Clk; -- making the MDC clk contineous
--PHY_MDC <= MDIO_Clk and mdio_en_reg;
-- Informs MDIO interface about the MDIO transfer complete.
MDIO_done <= mdio_xfer_done;
----------------------------------------------------------------------------
-- PROCESS : REG_MDIO_en
----------------------------------------------------------------------------
-- Latch MDIO_en bit on falling edge of MDC and when MDIO master is IDLE.
-- MDIO Master will complete the existing transfer even if MDIO interface
-- is disable in middle of the transaction.
----------------------------------------------------------------------------
REG_MDIO_en : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_en_reg <= '0';
elsif mdc_falling='1' then
if mdio_idle = '1' then
mdio_en_reg <= MDIO_en;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : PHY_MDIO_T_REG
----------------------------------------------------------------------------
-- The mdio_t_comb signal is driven high only for read operation starting
-- from the Turn arround state.
-- It is driven on falling clock edge to match up with PHY_MDIO_O
----------------------------------------------------------------------------
PHY_MDIO_T_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
PHY_MDIO_T <= '1';
elsif (mdc_falling='1') then -- falling edge of MDC
PHY_MDIO_T <= mdio_t_comb;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : PHY_MDIO_O_REG
----------------------------------------------------------------------------
-- Generating PHY_MDIO_O output singnal on falling edge of MDC
----------------------------------------------------------------------------
PHY_MDIO_O_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
PHY_MDIO_O <= '0';
elsif (mdc_falling='1') then -- falling edge of MDC
PHY_MDIO_O <= mdio_o_cmb;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : MDIO_IDLE_REG
----------------------------------------------------------------------------
-- The mdio_idle signal is used to indicate no activity on the MDIO.
-- Set at reset amd at the end of transmission.
-- Rst at start of transmission as long as device is MDIO_end
----------------------------------------------------------------------------
MDIO_IDLE_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_idle <= '1';
elsif (mdc_rising='1') then -- rising edge of MDC
if (mdio_xfer_done = '1') then
mdio_idle <= '1';
elsif (MDIO_Req = '1' and mdio_en_reg = '1') then
mdio_idle <= '0';
end if;
end if;
end if;
end process ;
----------------------------------------------------------------------------
-- PROCESS : MDIO_CAPTURE_DATA
----------------------------------------------------------------------------
-- This process captures registered PHY_MDIO_i input on rising edge of the
-- MDC clock. The rd_data_en signal is generated in MDIO State machine for
-- respective captured bit.
----------------------------------------------------------------------------
MDIO_CAPTURE_DATA : for i in 15 downto 0 generate
MDIO_DATA_IN : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
MDIO_RD_DATA(i) <= '0';
elsif (mdc_rising='1') then -- rising edge of MDC
if(rd_data_en(i) = '1') then
MDIO_RD_DATA(i) <= mdio_in_reg2;
end if;
end if;
end if;
end process MDIO_DATA_IN;
end generate;
----------------------------------------------------------------------------
-- PROCESS : MDIO_DOWN_COUNTER
----------------------------------------------------------------------------
-- This counter is used in Preamble and PHY_ADDR and REG_ADDR state.
-- This counter is loaded for the required values for each above states.
----------------------------------------------------------------------------
MDIO_DOWN_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
clk_cnt <= 0;
elsif (mdc_rising='1') then -- falling edge of MDC
if (ld_cnt_en_reg = '1') then -- Load counter with load data
clk_cnt <= ld_cnt_data_reg;
elsif (clk_cnt_en='1') then -- Enable Down Counter
clk_cnt <= clk_cnt - 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : MDIO_NEXT_STATE_GEN
----------------------------------------------------------------------------
-- MDIO next state register process
----------------------------------------------------------------------------
MDIO_NEXT_STATE_GEN : process (Clk)
begin
if Clk'event and Clk = '1' then
if (Rst = '1') then
mdio_state <= IDLE;
elsif (mdc_rising='1') then
mdio_state <= next_state;
end if;
end if;
end process MDIO_NEXT_STATE_GEN;
----------------------------------------------------------------------------
-- PROCESS : MDIO_COMB_REG_GEN
----------------------------------------------------------------------------
-- Combinational signal register process
----------------------------------------------------------------------------
MDIO_COMB_REG_GEN : process (Clk)
begin
if Clk'event and Clk = '1' then
if (Rst = '1') then
ld_cnt_data_reg <= 0;
ld_cnt_en_reg <= '0';
else
ld_cnt_data_reg <= ld_cnt_data_cmb;
ld_cnt_en_reg <= ld_cnt_en_cmb;
end if;
end if;
end process MDIO_COMB_REG_GEN;
----------------------------------------------------------------------------
-- PROCESS : MDIO_STATE_COMB
----------------------------------------------------------------------------
-- This process generates mdio_o_cmb signal in command and Write phase as
-- per the required MDIO protocol. This process also generate mdio_t_comb
-- tristate signal and rd_data_en to capture the respective bit in Read
-- operation.
----------------------------------------------------------------------------
MDIO_STATE_COMB : process (mdio_state, mdio_idle, clk_cnt, MDIO_OP,
MDIO_PHY_AD, MDIO_REG_AD, MDIO_WR_DATA)
begin
-- state machine defaults
mdio_o_cmb <= '1';
rd_data_en <= "0000000000000000";
mdio_xfer_done <= '0';
ld_cnt_en_cmb <= '0';
clk_cnt_en <= '0';
mdio_t_comb <= '0';
next_state <= mdio_state;
ld_cnt_data_cmb <= 0;
case mdio_state is
when IDLE =>
mdio_o_cmb <= '1';
mdio_t_comb <= '1';
ld_cnt_en_cmb <= '1';
-- leave IDLE state when new mdio request is received.
if mdio_idle = '0' then
-- Load counter for 32-bit preamble
ld_cnt_data_cmb <= 31;
next_state <= PREAMBLE;
end if;
when PREAMBLE =>
clk_cnt_en <= '1';
-- Move to ST1 after 32-bit preamble.
if clk_cnt = 0 then
next_state <= ST1;
clk_cnt_en <= '0';
end if;
when ST1 => -- Start Code-1
mdio_o_cmb <= '0';
next_state <= ST2;
when ST2 => -- Start Code-2
mdio_o_cmb <= '1';
next_state <= OP1;
when OP1 => -- Opcode-1
next_state <= OP2;
if MDIO_OP='1' then
mdio_o_cmb <= '1';
else
mdio_o_cmb <= '0';
end if;
when OP2 => -- Opcode-2
next_state <= PHY_ADDR;
-- Load counter for 5-bit PHYaddress transfer
ld_cnt_data_cmb <= 4;
ld_cnt_en_cmb <= '1';
if MDIO_OP='1' then
mdio_o_cmb <= '0';
else
mdio_o_cmb <= '1';
end if;
when PHY_ADDR => -- PHY Device Address
clk_cnt_en <= '1';
mdio_o_cmb <= MDIO_PHY_AD(clk_cnt);
-- Send 5-bit PHY device address
if clk_cnt=0 then
next_state <= REG_ADDR;
-- Load counter for 5-bit REG address transfer
ld_cnt_data_cmb <= 4;
ld_cnt_en_cmb <= '1';
end if;
when REG_ADDR => -- PHY Device Address
clk_cnt_en <= '1';
mdio_o_cmb <= MDIO_REG_AD(clk_cnt);
-- Send 5-bit PHY Register address
if clk_cnt=0 then
next_state <= TA1;
clk_cnt_en <= '0';
end if;
when TA1 => -- Turn Around Time-1
mdio_o_cmb <= '1';
next_state <= TA2;
-- For Read operation generate high impedence on
-- MDIO bus
if MDIO_OP='1' then
mdio_t_comb <= '1';
else
mdio_t_comb <= '0';
end if;
when TA2 => -- Turn Around Time-2
mdio_o_cmb <= '0';
-- Load the down counter for 16 bit data transfer
ld_cnt_data_cmb <= 15;
ld_cnt_en_cmb <= '1';
-- Move to Write state if opcode is '0'
if MDIO_OP='0' then
next_state <= WRITE;
mdio_t_comb <= '0';
else
next_state <= READ;
mdio_t_comb <= '1';
end if;
when WRITE => -- MDIO DATA Write
clk_cnt_en <= '1';
-- Send 16-bit Write Data on the MDIO data line
mdio_o_cmb <= MDIO_WR_DATA(clk_cnt);
-- Wait for 16 bit transfer
if clk_cnt=0 then
next_state <= DONE;
clk_cnt_en <= '0';
end if;
when READ => -- MDIO DATA Read
clk_cnt_en <= '1';
mdio_t_comb <= '1';
-- Generate read data enable for respective bit
rd_data_en(clk_cnt) <= '1';
-- Wait for 16 bit transfer
if clk_cnt=0 then
next_state <= DONE;
clk_cnt_en <= '0';
end if;
when DONE => -- MDIO Transfer Done
mdio_o_cmb <= '1';
mdio_t_comb <= '1';
next_state <= IDLE;
-- Mdio trasnfer complete
mdio_xfer_done <= '1';
-- coverage off
when others =>
next_state <= IDLE;
-- coverage on
end case;
end process MDIO_STATE_COMB;
end imp;
|
-------------------------------------------------------------------------------
-- mdio_if.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : mdio_if.vhd
-- Version : v2.0
-- Description : This entity provides the interface between the physical layer
-- management control, and the host interface through the MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- MDIO_Clk -- 2.5Mhz clock
-- MDIO_en -- MDIO enable
-- MDIO_OP -- MDIO OP code
-- MDIO_Req -- MDIO transmission request
-- MDIO_PHY_AD -- The physical layer address
-- MDIO_REG_AD -- The individual register address
-- MDIO_WR_DATA -- The data to be written on MDIO
-- MDIO_RD_DATA -- The data read from MDIO
-- PHY_MDIO_I -- MDIO Tri-state input from PHY
-- PHY_MDIO_O -- MDIO Tri-state output to PHY
-- PHY_MDIO_T -- MDIO Tri-state control
-- PHY_MDC -- 2.5Mhz communication clock to PHY
-- MDIO_done -- RX FIFO read ack
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity mdio_if is
port (
Clk : in std_logic; -- System Clock
Rst : in std_logic; -- System Reset
MDIO_Clk : in std_logic; -- 2.5Mhz clock
MDIO_en : in std_logic; -- MDIO enable
MDIO_OP : in std_logic; -- MDIO OP code
MDIO_Req : in std_logic; -- MDIO transmission request
MDIO_PHY_AD : in std_logic_vector(4 downto 0);
-- The physical layer address
MDIO_REG_AD : in std_logic_vector(4 downto 0);
-- The individual register address
MDIO_WR_DATA : in std_logic_vector(15 downto 0);
-- The data to be written on MDIO
MDIO_RD_DATA : out std_logic_vector(15 downto 0);
-- The data read from MDIO
PHY_MDIO_I : in std_logic; -- MDIO Tri-state input from PHY
PHY_MDIO_O : out std_logic; -- MDIO Tri-state output to PHY
PHY_MDIO_T : out std_logic; -- MDIO Tri-state control
PHY_MDC : out std_logic; -- 2.5Mhz communication clock
MDIO_done : out std_logic -- MDIO tranfer done indicator
);
end mdio_if;
architecture imp of mdio_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
type mdio_state_type is (IDLE, PREAMBLE, ST1, ST2, OP1, OP2, TA1, TA2,
PHY_ADDR, REG_ADDR, WRITE, READ, DONE);
signal mdio_state, next_state : mdio_state_type;
signal mdio_xfer_done : std_logic; -- pulse to inidcate end of activity
signal mdio_idle : std_logic; -- internal READY signal
signal rd_data_en : std_logic_vector(15 downto 0); -- decoded write
-- MDIO_en for RD_DATA
signal mdio_en_reg : std_logic; -- MDIO_en signal latched at start of
-- transmission
signal mdio_o_cmb : std_logic; -- rising edge version of MDIO_OUT
signal mdio_t_comb : std_logic; -- combinatorial term to produce
-- MDIO_TRISTATE
signal mdio_clk_reg : std_logic; -- registering MDIO_Clk to use it as a
-- clock MDIO_en
signal mdio_in_reg1 : std_logic; -- compensate in pipeline delay caused
-- by using MDC as a clock MDIO_en
signal mdio_in_reg2 : std_logic; -- compensate in pipeline delay caused by
-- using MDC as a clock MDIO_en
signal clk_cnt : integer range 0 to 32; -- Clk counter
signal ld_cnt_data_cmb : integer range 0 to 32; -- Counter load comb
signal ld_cnt_data_reg : integer range 0 to 32; -- Counter load reg
signal ld_cnt_en_cmb : std_logic; -- Counter load enable
signal clk_cnt_en : std_logic; -- Counter enable
signal mdc_falling : std_logic; -- MDC falling edge
signal mdc_rising : std_logic; -- MDC rising edge
signal ld_cnt_en_reg : std_logic; -- Counter load enable reg
begin
----------------------------------------------------------------------------
-- PROCESS : INPUT_REG_CLK
----------------------------------------------------------------------------
-- Registering PHY_MDIO_I and MDC signals w.r.t SAXI clock.
----------------------------------------------------------------------------
INPUT_REG_CLK: process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_clk_reg <= '0';
mdio_in_reg1 <= '0';
mdio_in_reg2 <= '0';
else
mdio_clk_reg <= MDIO_Clk;
mdio_in_reg1 <= PHY_MDIO_I;
mdio_in_reg2 <= mdio_in_reg1;
end if;
end if;
end process INPUT_REG_CLK;
-- Falling edge and rising edge generation of MDC clock
mdc_falling <= not MDIO_Clk and mdio_clk_reg;
mdc_rising <= MDIO_Clk and not mdio_clk_reg;
-- Enable MDC only when MDIO interface is enabled.
PHY_MDC <= MDIO_Clk; -- making the MDC clk contineous
--PHY_MDC <= MDIO_Clk and mdio_en_reg;
-- Informs MDIO interface about the MDIO transfer complete.
MDIO_done <= mdio_xfer_done;
----------------------------------------------------------------------------
-- PROCESS : REG_MDIO_en
----------------------------------------------------------------------------
-- Latch MDIO_en bit on falling edge of MDC and when MDIO master is IDLE.
-- MDIO Master will complete the existing transfer even if MDIO interface
-- is disable in middle of the transaction.
----------------------------------------------------------------------------
REG_MDIO_en : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_en_reg <= '0';
elsif mdc_falling='1' then
if mdio_idle = '1' then
mdio_en_reg <= MDIO_en;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : PHY_MDIO_T_REG
----------------------------------------------------------------------------
-- The mdio_t_comb signal is driven high only for read operation starting
-- from the Turn arround state.
-- It is driven on falling clock edge to match up with PHY_MDIO_O
----------------------------------------------------------------------------
PHY_MDIO_T_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
PHY_MDIO_T <= '1';
elsif (mdc_falling='1') then -- falling edge of MDC
PHY_MDIO_T <= mdio_t_comb;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : PHY_MDIO_O_REG
----------------------------------------------------------------------------
-- Generating PHY_MDIO_O output singnal on falling edge of MDC
----------------------------------------------------------------------------
PHY_MDIO_O_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
PHY_MDIO_O <= '0';
elsif (mdc_falling='1') then -- falling edge of MDC
PHY_MDIO_O <= mdio_o_cmb;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : MDIO_IDLE_REG
----------------------------------------------------------------------------
-- The mdio_idle signal is used to indicate no activity on the MDIO.
-- Set at reset amd at the end of transmission.
-- Rst at start of transmission as long as device is MDIO_end
----------------------------------------------------------------------------
MDIO_IDLE_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_idle <= '1';
elsif (mdc_rising='1') then -- rising edge of MDC
if (mdio_xfer_done = '1') then
mdio_idle <= '1';
elsif (MDIO_Req = '1' and mdio_en_reg = '1') then
mdio_idle <= '0';
end if;
end if;
end if;
end process ;
----------------------------------------------------------------------------
-- PROCESS : MDIO_CAPTURE_DATA
----------------------------------------------------------------------------
-- This process captures registered PHY_MDIO_i input on rising edge of the
-- MDC clock. The rd_data_en signal is generated in MDIO State machine for
-- respective captured bit.
----------------------------------------------------------------------------
MDIO_CAPTURE_DATA : for i in 15 downto 0 generate
MDIO_DATA_IN : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
MDIO_RD_DATA(i) <= '0';
elsif (mdc_rising='1') then -- rising edge of MDC
if(rd_data_en(i) = '1') then
MDIO_RD_DATA(i) <= mdio_in_reg2;
end if;
end if;
end if;
end process MDIO_DATA_IN;
end generate;
----------------------------------------------------------------------------
-- PROCESS : MDIO_DOWN_COUNTER
----------------------------------------------------------------------------
-- This counter is used in Preamble and PHY_ADDR and REG_ADDR state.
-- This counter is loaded for the required values for each above states.
----------------------------------------------------------------------------
MDIO_DOWN_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
clk_cnt <= 0;
elsif (mdc_rising='1') then -- falling edge of MDC
if (ld_cnt_en_reg = '1') then -- Load counter with load data
clk_cnt <= ld_cnt_data_reg;
elsif (clk_cnt_en='1') then -- Enable Down Counter
clk_cnt <= clk_cnt - 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : MDIO_NEXT_STATE_GEN
----------------------------------------------------------------------------
-- MDIO next state register process
----------------------------------------------------------------------------
MDIO_NEXT_STATE_GEN : process (Clk)
begin
if Clk'event and Clk = '1' then
if (Rst = '1') then
mdio_state <= IDLE;
elsif (mdc_rising='1') then
mdio_state <= next_state;
end if;
end if;
end process MDIO_NEXT_STATE_GEN;
----------------------------------------------------------------------------
-- PROCESS : MDIO_COMB_REG_GEN
----------------------------------------------------------------------------
-- Combinational signal register process
----------------------------------------------------------------------------
MDIO_COMB_REG_GEN : process (Clk)
begin
if Clk'event and Clk = '1' then
if (Rst = '1') then
ld_cnt_data_reg <= 0;
ld_cnt_en_reg <= '0';
else
ld_cnt_data_reg <= ld_cnt_data_cmb;
ld_cnt_en_reg <= ld_cnt_en_cmb;
end if;
end if;
end process MDIO_COMB_REG_GEN;
----------------------------------------------------------------------------
-- PROCESS : MDIO_STATE_COMB
----------------------------------------------------------------------------
-- This process generates mdio_o_cmb signal in command and Write phase as
-- per the required MDIO protocol. This process also generate mdio_t_comb
-- tristate signal and rd_data_en to capture the respective bit in Read
-- operation.
----------------------------------------------------------------------------
MDIO_STATE_COMB : process (mdio_state, mdio_idle, clk_cnt, MDIO_OP,
MDIO_PHY_AD, MDIO_REG_AD, MDIO_WR_DATA)
begin
-- state machine defaults
mdio_o_cmb <= '1';
rd_data_en <= "0000000000000000";
mdio_xfer_done <= '0';
ld_cnt_en_cmb <= '0';
clk_cnt_en <= '0';
mdio_t_comb <= '0';
next_state <= mdio_state;
ld_cnt_data_cmb <= 0;
case mdio_state is
when IDLE =>
mdio_o_cmb <= '1';
mdio_t_comb <= '1';
ld_cnt_en_cmb <= '1';
-- leave IDLE state when new mdio request is received.
if mdio_idle = '0' then
-- Load counter for 32-bit preamble
ld_cnt_data_cmb <= 31;
next_state <= PREAMBLE;
end if;
when PREAMBLE =>
clk_cnt_en <= '1';
-- Move to ST1 after 32-bit preamble.
if clk_cnt = 0 then
next_state <= ST1;
clk_cnt_en <= '0';
end if;
when ST1 => -- Start Code-1
mdio_o_cmb <= '0';
next_state <= ST2;
when ST2 => -- Start Code-2
mdio_o_cmb <= '1';
next_state <= OP1;
when OP1 => -- Opcode-1
next_state <= OP2;
if MDIO_OP='1' then
mdio_o_cmb <= '1';
else
mdio_o_cmb <= '0';
end if;
when OP2 => -- Opcode-2
next_state <= PHY_ADDR;
-- Load counter for 5-bit PHYaddress transfer
ld_cnt_data_cmb <= 4;
ld_cnt_en_cmb <= '1';
if MDIO_OP='1' then
mdio_o_cmb <= '0';
else
mdio_o_cmb <= '1';
end if;
when PHY_ADDR => -- PHY Device Address
clk_cnt_en <= '1';
mdio_o_cmb <= MDIO_PHY_AD(clk_cnt);
-- Send 5-bit PHY device address
if clk_cnt=0 then
next_state <= REG_ADDR;
-- Load counter for 5-bit REG address transfer
ld_cnt_data_cmb <= 4;
ld_cnt_en_cmb <= '1';
end if;
when REG_ADDR => -- PHY Device Address
clk_cnt_en <= '1';
mdio_o_cmb <= MDIO_REG_AD(clk_cnt);
-- Send 5-bit PHY Register address
if clk_cnt=0 then
next_state <= TA1;
clk_cnt_en <= '0';
end if;
when TA1 => -- Turn Around Time-1
mdio_o_cmb <= '1';
next_state <= TA2;
-- For Read operation generate high impedence on
-- MDIO bus
if MDIO_OP='1' then
mdio_t_comb <= '1';
else
mdio_t_comb <= '0';
end if;
when TA2 => -- Turn Around Time-2
mdio_o_cmb <= '0';
-- Load the down counter for 16 bit data transfer
ld_cnt_data_cmb <= 15;
ld_cnt_en_cmb <= '1';
-- Move to Write state if opcode is '0'
if MDIO_OP='0' then
next_state <= WRITE;
mdio_t_comb <= '0';
else
next_state <= READ;
mdio_t_comb <= '1';
end if;
when WRITE => -- MDIO DATA Write
clk_cnt_en <= '1';
-- Send 16-bit Write Data on the MDIO data line
mdio_o_cmb <= MDIO_WR_DATA(clk_cnt);
-- Wait for 16 bit transfer
if clk_cnt=0 then
next_state <= DONE;
clk_cnt_en <= '0';
end if;
when READ => -- MDIO DATA Read
clk_cnt_en <= '1';
mdio_t_comb <= '1';
-- Generate read data enable for respective bit
rd_data_en(clk_cnt) <= '1';
-- Wait for 16 bit transfer
if clk_cnt=0 then
next_state <= DONE;
clk_cnt_en <= '0';
end if;
when DONE => -- MDIO Transfer Done
mdio_o_cmb <= '1';
mdio_t_comb <= '1';
next_state <= IDLE;
-- Mdio trasnfer complete
mdio_xfer_done <= '1';
-- coverage off
when others =>
next_state <= IDLE;
-- coverage on
end case;
end process MDIO_STATE_COMB;
end imp;
|
-------------------------------------------------------------------------------
-- mdio_if.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : mdio_if.vhd
-- Version : v2.0
-- Description : This entity provides the interface between the physical layer
-- management control, and the host interface through the MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- MDIO_Clk -- 2.5Mhz clock
-- MDIO_en -- MDIO enable
-- MDIO_OP -- MDIO OP code
-- MDIO_Req -- MDIO transmission request
-- MDIO_PHY_AD -- The physical layer address
-- MDIO_REG_AD -- The individual register address
-- MDIO_WR_DATA -- The data to be written on MDIO
-- MDIO_RD_DATA -- The data read from MDIO
-- PHY_MDIO_I -- MDIO Tri-state input from PHY
-- PHY_MDIO_O -- MDIO Tri-state output to PHY
-- PHY_MDIO_T -- MDIO Tri-state control
-- PHY_MDC -- 2.5Mhz communication clock to PHY
-- MDIO_done -- RX FIFO read ack
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity mdio_if is
port (
Clk : in std_logic; -- System Clock
Rst : in std_logic; -- System Reset
MDIO_Clk : in std_logic; -- 2.5Mhz clock
MDIO_en : in std_logic; -- MDIO enable
MDIO_OP : in std_logic; -- MDIO OP code
MDIO_Req : in std_logic; -- MDIO transmission request
MDIO_PHY_AD : in std_logic_vector(4 downto 0);
-- The physical layer address
MDIO_REG_AD : in std_logic_vector(4 downto 0);
-- The individual register address
MDIO_WR_DATA : in std_logic_vector(15 downto 0);
-- The data to be written on MDIO
MDIO_RD_DATA : out std_logic_vector(15 downto 0);
-- The data read from MDIO
PHY_MDIO_I : in std_logic; -- MDIO Tri-state input from PHY
PHY_MDIO_O : out std_logic; -- MDIO Tri-state output to PHY
PHY_MDIO_T : out std_logic; -- MDIO Tri-state control
PHY_MDC : out std_logic; -- 2.5Mhz communication clock
MDIO_done : out std_logic -- MDIO tranfer done indicator
);
end mdio_if;
architecture imp of mdio_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
type mdio_state_type is (IDLE, PREAMBLE, ST1, ST2, OP1, OP2, TA1, TA2,
PHY_ADDR, REG_ADDR, WRITE, READ, DONE);
signal mdio_state, next_state : mdio_state_type;
signal mdio_xfer_done : std_logic; -- pulse to inidcate end of activity
signal mdio_idle : std_logic; -- internal READY signal
signal rd_data_en : std_logic_vector(15 downto 0); -- decoded write
-- MDIO_en for RD_DATA
signal mdio_en_reg : std_logic; -- MDIO_en signal latched at start of
-- transmission
signal mdio_o_cmb : std_logic; -- rising edge version of MDIO_OUT
signal mdio_t_comb : std_logic; -- combinatorial term to produce
-- MDIO_TRISTATE
signal mdio_clk_reg : std_logic; -- registering MDIO_Clk to use it as a
-- clock MDIO_en
signal mdio_in_reg1 : std_logic; -- compensate in pipeline delay caused
-- by using MDC as a clock MDIO_en
signal mdio_in_reg2 : std_logic; -- compensate in pipeline delay caused by
-- using MDC as a clock MDIO_en
signal clk_cnt : integer range 0 to 32; -- Clk counter
signal ld_cnt_data_cmb : integer range 0 to 32; -- Counter load comb
signal ld_cnt_data_reg : integer range 0 to 32; -- Counter load reg
signal ld_cnt_en_cmb : std_logic; -- Counter load enable
signal clk_cnt_en : std_logic; -- Counter enable
signal mdc_falling : std_logic; -- MDC falling edge
signal mdc_rising : std_logic; -- MDC rising edge
signal ld_cnt_en_reg : std_logic; -- Counter load enable reg
begin
----------------------------------------------------------------------------
-- PROCESS : INPUT_REG_CLK
----------------------------------------------------------------------------
-- Registering PHY_MDIO_I and MDC signals w.r.t SAXI clock.
----------------------------------------------------------------------------
INPUT_REG_CLK: process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_clk_reg <= '0';
mdio_in_reg1 <= '0';
mdio_in_reg2 <= '0';
else
mdio_clk_reg <= MDIO_Clk;
mdio_in_reg1 <= PHY_MDIO_I;
mdio_in_reg2 <= mdio_in_reg1;
end if;
end if;
end process INPUT_REG_CLK;
-- Falling edge and rising edge generation of MDC clock
mdc_falling <= not MDIO_Clk and mdio_clk_reg;
mdc_rising <= MDIO_Clk and not mdio_clk_reg;
-- Enable MDC only when MDIO interface is enabled.
PHY_MDC <= MDIO_Clk; -- making the MDC clk contineous
--PHY_MDC <= MDIO_Clk and mdio_en_reg;
-- Informs MDIO interface about the MDIO transfer complete.
MDIO_done <= mdio_xfer_done;
----------------------------------------------------------------------------
-- PROCESS : REG_MDIO_en
----------------------------------------------------------------------------
-- Latch MDIO_en bit on falling edge of MDC and when MDIO master is IDLE.
-- MDIO Master will complete the existing transfer even if MDIO interface
-- is disable in middle of the transaction.
----------------------------------------------------------------------------
REG_MDIO_en : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_en_reg <= '0';
elsif mdc_falling='1' then
if mdio_idle = '1' then
mdio_en_reg <= MDIO_en;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : PHY_MDIO_T_REG
----------------------------------------------------------------------------
-- The mdio_t_comb signal is driven high only for read operation starting
-- from the Turn arround state.
-- It is driven on falling clock edge to match up with PHY_MDIO_O
----------------------------------------------------------------------------
PHY_MDIO_T_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
PHY_MDIO_T <= '1';
elsif (mdc_falling='1') then -- falling edge of MDC
PHY_MDIO_T <= mdio_t_comb;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : PHY_MDIO_O_REG
----------------------------------------------------------------------------
-- Generating PHY_MDIO_O output singnal on falling edge of MDC
----------------------------------------------------------------------------
PHY_MDIO_O_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
PHY_MDIO_O <= '0';
elsif (mdc_falling='1') then -- falling edge of MDC
PHY_MDIO_O <= mdio_o_cmb;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : MDIO_IDLE_REG
----------------------------------------------------------------------------
-- The mdio_idle signal is used to indicate no activity on the MDIO.
-- Set at reset amd at the end of transmission.
-- Rst at start of transmission as long as device is MDIO_end
----------------------------------------------------------------------------
MDIO_IDLE_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_idle <= '1';
elsif (mdc_rising='1') then -- rising edge of MDC
if (mdio_xfer_done = '1') then
mdio_idle <= '1';
elsif (MDIO_Req = '1' and mdio_en_reg = '1') then
mdio_idle <= '0';
end if;
end if;
end if;
end process ;
----------------------------------------------------------------------------
-- PROCESS : MDIO_CAPTURE_DATA
----------------------------------------------------------------------------
-- This process captures registered PHY_MDIO_i input on rising edge of the
-- MDC clock. The rd_data_en signal is generated in MDIO State machine for
-- respective captured bit.
----------------------------------------------------------------------------
MDIO_CAPTURE_DATA : for i in 15 downto 0 generate
MDIO_DATA_IN : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
MDIO_RD_DATA(i) <= '0';
elsif (mdc_rising='1') then -- rising edge of MDC
if(rd_data_en(i) = '1') then
MDIO_RD_DATA(i) <= mdio_in_reg2;
end if;
end if;
end if;
end process MDIO_DATA_IN;
end generate;
----------------------------------------------------------------------------
-- PROCESS : MDIO_DOWN_COUNTER
----------------------------------------------------------------------------
-- This counter is used in Preamble and PHY_ADDR and REG_ADDR state.
-- This counter is loaded for the required values for each above states.
----------------------------------------------------------------------------
MDIO_DOWN_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
clk_cnt <= 0;
elsif (mdc_rising='1') then -- falling edge of MDC
if (ld_cnt_en_reg = '1') then -- Load counter with load data
clk_cnt <= ld_cnt_data_reg;
elsif (clk_cnt_en='1') then -- Enable Down Counter
clk_cnt <= clk_cnt - 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : MDIO_NEXT_STATE_GEN
----------------------------------------------------------------------------
-- MDIO next state register process
----------------------------------------------------------------------------
MDIO_NEXT_STATE_GEN : process (Clk)
begin
if Clk'event and Clk = '1' then
if (Rst = '1') then
mdio_state <= IDLE;
elsif (mdc_rising='1') then
mdio_state <= next_state;
end if;
end if;
end process MDIO_NEXT_STATE_GEN;
----------------------------------------------------------------------------
-- PROCESS : MDIO_COMB_REG_GEN
----------------------------------------------------------------------------
-- Combinational signal register process
----------------------------------------------------------------------------
MDIO_COMB_REG_GEN : process (Clk)
begin
if Clk'event and Clk = '1' then
if (Rst = '1') then
ld_cnt_data_reg <= 0;
ld_cnt_en_reg <= '0';
else
ld_cnt_data_reg <= ld_cnt_data_cmb;
ld_cnt_en_reg <= ld_cnt_en_cmb;
end if;
end if;
end process MDIO_COMB_REG_GEN;
----------------------------------------------------------------------------
-- PROCESS : MDIO_STATE_COMB
----------------------------------------------------------------------------
-- This process generates mdio_o_cmb signal in command and Write phase as
-- per the required MDIO protocol. This process also generate mdio_t_comb
-- tristate signal and rd_data_en to capture the respective bit in Read
-- operation.
----------------------------------------------------------------------------
MDIO_STATE_COMB : process (mdio_state, mdio_idle, clk_cnt, MDIO_OP,
MDIO_PHY_AD, MDIO_REG_AD, MDIO_WR_DATA)
begin
-- state machine defaults
mdio_o_cmb <= '1';
rd_data_en <= "0000000000000000";
mdio_xfer_done <= '0';
ld_cnt_en_cmb <= '0';
clk_cnt_en <= '0';
mdio_t_comb <= '0';
next_state <= mdio_state;
ld_cnt_data_cmb <= 0;
case mdio_state is
when IDLE =>
mdio_o_cmb <= '1';
mdio_t_comb <= '1';
ld_cnt_en_cmb <= '1';
-- leave IDLE state when new mdio request is received.
if mdio_idle = '0' then
-- Load counter for 32-bit preamble
ld_cnt_data_cmb <= 31;
next_state <= PREAMBLE;
end if;
when PREAMBLE =>
clk_cnt_en <= '1';
-- Move to ST1 after 32-bit preamble.
if clk_cnt = 0 then
next_state <= ST1;
clk_cnt_en <= '0';
end if;
when ST1 => -- Start Code-1
mdio_o_cmb <= '0';
next_state <= ST2;
when ST2 => -- Start Code-2
mdio_o_cmb <= '1';
next_state <= OP1;
when OP1 => -- Opcode-1
next_state <= OP2;
if MDIO_OP='1' then
mdio_o_cmb <= '1';
else
mdio_o_cmb <= '0';
end if;
when OP2 => -- Opcode-2
next_state <= PHY_ADDR;
-- Load counter for 5-bit PHYaddress transfer
ld_cnt_data_cmb <= 4;
ld_cnt_en_cmb <= '1';
if MDIO_OP='1' then
mdio_o_cmb <= '0';
else
mdio_o_cmb <= '1';
end if;
when PHY_ADDR => -- PHY Device Address
clk_cnt_en <= '1';
mdio_o_cmb <= MDIO_PHY_AD(clk_cnt);
-- Send 5-bit PHY device address
if clk_cnt=0 then
next_state <= REG_ADDR;
-- Load counter for 5-bit REG address transfer
ld_cnt_data_cmb <= 4;
ld_cnt_en_cmb <= '1';
end if;
when REG_ADDR => -- PHY Device Address
clk_cnt_en <= '1';
mdio_o_cmb <= MDIO_REG_AD(clk_cnt);
-- Send 5-bit PHY Register address
if clk_cnt=0 then
next_state <= TA1;
clk_cnt_en <= '0';
end if;
when TA1 => -- Turn Around Time-1
mdio_o_cmb <= '1';
next_state <= TA2;
-- For Read operation generate high impedence on
-- MDIO bus
if MDIO_OP='1' then
mdio_t_comb <= '1';
else
mdio_t_comb <= '0';
end if;
when TA2 => -- Turn Around Time-2
mdio_o_cmb <= '0';
-- Load the down counter for 16 bit data transfer
ld_cnt_data_cmb <= 15;
ld_cnt_en_cmb <= '1';
-- Move to Write state if opcode is '0'
if MDIO_OP='0' then
next_state <= WRITE;
mdio_t_comb <= '0';
else
next_state <= READ;
mdio_t_comb <= '1';
end if;
when WRITE => -- MDIO DATA Write
clk_cnt_en <= '1';
-- Send 16-bit Write Data on the MDIO data line
mdio_o_cmb <= MDIO_WR_DATA(clk_cnt);
-- Wait for 16 bit transfer
if clk_cnt=0 then
next_state <= DONE;
clk_cnt_en <= '0';
end if;
when READ => -- MDIO DATA Read
clk_cnt_en <= '1';
mdio_t_comb <= '1';
-- Generate read data enable for respective bit
rd_data_en(clk_cnt) <= '1';
-- Wait for 16 bit transfer
if clk_cnt=0 then
next_state <= DONE;
clk_cnt_en <= '0';
end if;
when DONE => -- MDIO Transfer Done
mdio_o_cmb <= '1';
mdio_t_comb <= '1';
next_state <= IDLE;
-- Mdio trasnfer complete
mdio_xfer_done <= '1';
-- coverage off
when others =>
next_state <= IDLE;
-- coverage on
end case;
end process MDIO_STATE_COMB;
end imp;
|
-- ============================================================
-- File Name: control_path.vhd
-- ============================================================
-- ************************************************************
-- THIS IS A AUTO-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 2.0 BUILD. GENERATED ON 2016-11-22
-- ************************************************************
LIBRARY IEEE;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
ENTITY control_path IS
PORT(
start: IN STD_LOGIC := '0';
complete: OUT STD_LOGIC := '0';
clk: IN STD_LOGIC := '0';
reset: IN STD_LOGIC := '0';
T: OUT STD_LOGIC_VECTOR( 0 TO 36 ) := (others => '0'));
END ENTITY;
ARCHITECTURE control OF control_path IS
TYPE fsm_state IS ( init, S0, S1, S2, S3, S4, S5, done );
SIGNAL nQ, Q: fsm_state := init;
BEGIN
clock: PROCESS(clk)
BEGIN
if(clk'EVENT AND clk = '1') THEN
Q <= nQ;
END IF;
END PROCESS;
next_state: PROCESS( reset, start, Q )
begin
nQ <= Q;
IF (reset = '1') THEN
nQ <= init;
ELSE
CASE Q IS
WHEN init =>
if (start = '1') then nQ <= S0;
END IF;
WHEN S0 => nQ <= S1;
WHEN S1 => nQ <= S2;
WHEN S2 => nQ <= S3;
WHEN S3 => nQ <= S4;
WHEN S4 => nQ <= S5;
WHEN S5 => nQ <= done;
WHEN done => nQ <= init;
WHEN OTHERS => nQ <= init;
END CASE;
END IF;
END PROCESS;
T_process: PROCESS ( Q )
BEGIN
T <= (OTHERS => '0');
complete <= '0';
CASE Q IS
WHEN init =>
T(12) <= '1';
T(13) <= '1';
T(14) <= '1';
T(15) <= '1';
WHEN S0 =>
T(16) <= '1';
T(17) <= '1';
T ( 6 TO 8 ) <= "110";
T ( 9 TO 11 ) <= "111";
T ( 23 TO 24 ) <= "10";
T ( 29 TO 30 ) <= "01";
T ( 35 TO 35 ) <= "1";
WHEN S1 =>
T(18) <= '1';
T(19) <= '1';
T ( 23 TO 24 ) <= "10";
T ( 29 TO 30 ) <= "01";
T ( 31 TO 31 ) <= "1";
T ( 32 TO 32 ) <= "1";
WHEN S2 =>
T(20) <= '1';
T(21) <= '1';
T(22) <= '1';
T ( 0 TO 2 ) <= "100";
T ( 3 TO 5 ) <= "101";
T ( 23 TO 24 ) <= "11";
T ( 25 TO 26 ) <= "01";
T ( 27 TO 28 ) <= "10";
T ( 29 TO 30 ) <= "10";
T ( 31 TO 31 ) <= "1";
T ( 32 TO 32 ) <= "1";
T ( 33 TO 33 ) <= "1";
T ( 34 TO 34 ) <= "1";
T ( 36 TO 36 ) <= "1";
WHEN S3 =>
T(16) <= '1';
T(17) <= '1';
T ( 3 TO 5 ) <= "111";
T ( 25 TO 26 ) <= "10";
T ( 27 TO 28 ) <= "01";
T ( 33 TO 33 ) <= "1";
T ( 34 TO 34 ) <= "1";
WHEN S4 =>
T(21) <= '1';
T ( 25 TO 26 ) <= "10";
WHEN S5 =>
T(20) <= '1';
T ( 0 TO 2 ) <= "110";
T ( 23 TO 24 ) <= "01";
T ( 25 TO 26 ) <= "01";
WHEN done => complete <= '1';
END CASE;
END PROCESS;
END ARCHITECTURE; |
library ieee;
use ieee.std_logic_1164.all;
use work.memory_types.all;
entity test_vga_rom is
end test_vga_rom;
architecture behavioural of test_vga_rom is
component VGA_ROM is
generic (
contents: vga_memory
);
port (
clock : in std_logic;
enable : in std_logic;
address : in natural range vga_memory'range;
data : out std_logic
);
end component;
signal clock : std_logic;
signal enable : std_logic;
signal address : natural range vga_memory'range;
signal output : std_logic;
constant test_storage : vga_memory := (
0 => '0',
1 => '1',
2 => '1',
3 => '0',
others => '0'
);
begin
ROMCELL : VGA_ROM generic map (test_storage)
port map (clock, enable, address, output);
process
begin
enable <= '1';
address <= 0;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert output = '0'
report "result should be 0" severity error;
address <= 1;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert output = '1'
report "result should be 1" severity error;
address <= 2;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert output = '1'
report "result should be 1" severity error;
address <= 3;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert output = '0'
report "result should be 1" severity error;
enable <= '0';
address <= 1;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert output = '0'
report "result should be 0 when disabled" severity error;
wait;
end process;
end behavioural;
|
-------------------------------------------------------------------------------
-- Title : FSMC Slave, synchronous
-------------------------------------------------------------------------------
-- Author :
-------------------------------------------------------------------------------
-- Description: This is slave to the flexible static memory controller (FSMC)
-- of a STM32 device. The slave is a busmaster to the local bus.
-- Data can be transfered to and from the bus slaves on the bus.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.fsmcslave_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity fsmc_slave is
port (
fsmc_i : out fsmc_out_type;
fsmc_o : in fsmc_in_type;
bus_o : out busmaster_out_type;
bus_i : in busmaster_in_type;
clk : in std_logic
);
end fsmc_slave;
-------------------------------------------------------------------------------
architecture behavioral of fsmc_slave is
begin
end behavioral;
|
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end PROCEDURE proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end PROCEDURE proc_name;
begin
end architecture RTL;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_05.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity SR_flipflop is
port ( s_n, r_n : in bit; q, q_n : inout bit );
begin
postponed process (q, q_n) is
begin
assert now = 0 fs or q = not q_n
report "implementation error: q /= not q_n";
end postponed process;
end entity SR_flipflop;
--------------------------------------------------
architecture dataflow of SR_flipflop is
begin
gate_1 : q <= s_n nand q_n;
gate_2 : q_n <= r_n nand q;
end architecture dataflow;
-- not in book
entity fg_21_05 is
end entity fg_21_05;
architecture test of fg_21_05 is
signal s_n, r_n, q, q_n : bit;
begin
dut : entity work.SR_flipflop
port map ( s_n, r_n, q, q_n );
s_n <= '1',
'0' after 10 ns, '1' after 15 ns,
'0' after 30 ns, '1' after 40 ns;
r_n <= '0', '1' after 5 ns,
'0' after 20 ns, '1' after 25 ns,
'0' after 30 ns, '1' after 35 ns;
end architecture test;
-- end not in book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_05.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity SR_flipflop is
port ( s_n, r_n : in bit; q, q_n : inout bit );
begin
postponed process (q, q_n) is
begin
assert now = 0 fs or q = not q_n
report "implementation error: q /= not q_n";
end postponed process;
end entity SR_flipflop;
--------------------------------------------------
architecture dataflow of SR_flipflop is
begin
gate_1 : q <= s_n nand q_n;
gate_2 : q_n <= r_n nand q;
end architecture dataflow;
-- not in book
entity fg_21_05 is
end entity fg_21_05;
architecture test of fg_21_05 is
signal s_n, r_n, q, q_n : bit;
begin
dut : entity work.SR_flipflop
port map ( s_n, r_n, q, q_n );
s_n <= '1',
'0' after 10 ns, '1' after 15 ns,
'0' after 30 ns, '1' after 40 ns;
r_n <= '0', '1' after 5 ns,
'0' after 20 ns, '1' after 25 ns,
'0' after 30 ns, '1' after 35 ns;
end architecture test;
-- end not in book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_05.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity SR_flipflop is
port ( s_n, r_n : in bit; q, q_n : inout bit );
begin
postponed process (q, q_n) is
begin
assert now = 0 fs or q = not q_n
report "implementation error: q /= not q_n";
end postponed process;
end entity SR_flipflop;
--------------------------------------------------
architecture dataflow of SR_flipflop is
begin
gate_1 : q <= s_n nand q_n;
gate_2 : q_n <= r_n nand q;
end architecture dataflow;
-- not in book
entity fg_21_05 is
end entity fg_21_05;
architecture test of fg_21_05 is
signal s_n, r_n, q, q_n : bit;
begin
dut : entity work.SR_flipflop
port map ( s_n, r_n, q, q_n );
s_n <= '1',
'0' after 10 ns, '1' after 15 ns,
'0' after 30 ns, '1' after 40 ns;
r_n <= '0', '1' after 5 ns,
'0' after 20 ns, '1' after 25 ns,
'0' after 30 ns, '1' after 35 ns;
end architecture test;
-- end not in book
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:18:22 07/06/2014
-- Design Name:
-- Module Name: triple_buffer_arbiter - triple_buffer_arbiter_arch
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity triple_buffer_arbiter is
generic (
offset : integer;
size : integer;
addr : integer := 32);
port (
input_clk : in std_logic;
output_clk : in std_logic;
input_addr : out unsigned(addr-1 downto 0);
output_addr : out unsigned(addr-1 downto 0);
rst : in std_logic);
end triple_buffer_arbiter;
architecture triple_buffer_arbiter_arch of triple_buffer_arbiter is
constant lock_initial : unsigned(1 downto 0) := "11";
signal input_lock: unsigned(1 downto 0);
signal output_lock: unsigned(1 downto 0);
signal n0_buffer: unsigned(1 downto 0);
signal n1_buffer: unsigned(1 downto 0);
signal n2_buffer: unsigned(1 downto 0);
constant buffer0: unsigned(1 downto 0) := "00";
constant buffer1: unsigned(1 downto 0) := "01";
constant buffer2: unsigned(1 downto 0) := "10";
constant buffer0_addr : unsigned(addr-1 downto 0) := to_unsigned(offset, addr);
constant buffer1_addr : unsigned(addr-1 downto 0) := to_unsigned(offset + size, addr);
constant buffer2_addr : unsigned(addr-1 downto 0) := to_unsigned(offset + size * 2, addr);
signal okay: std_logic := '1';
begin
okay_process: process (input_lock) is
begin
case n2_buffer & n1_buffer & n0_buffer is
when buffer0 & buffer1 & buffer2 =>
okay <= '1';
when buffer2 & buffer0 & buffer1 =>
okay <= '1';
when buffer1 & buffer2 & buffer0 =>
okay <= '1';
when buffer0 & buffer2 & buffer1 =>
okay <= '1';
when buffer1 & buffer0 & buffer2 =>
okay <= '1';
when buffer2 & buffer1 & buffer0 =>
okay <= '1';
when others =>
okay <= '0';
end case;
end process okay_process;
-- Locking a buffer for input generates the address on input_addr
input_addr_process: process (input_lock) is
begin
case input_lock is
when buffer0 =>
input_addr <= buffer0_addr;
when buffer1 =>
input_addr <= buffer1_addr;
when buffer2 =>
input_addr <= buffer2_addr;
when others =>
input_addr <= "UUUUUUUU";
end case;
end process input_addr_process;
-- Locking a buffer for output generates the address on output_addr
output_addr_process: process (output_lock) is
begin
case output_lock is
when buffer0 =>
output_addr <= buffer0_addr;
when buffer1 =>
output_addr <= buffer1_addr;
when buffer2 =>
output_addr <= buffer2_addr;
when others =>
output_addr <= "UUUUUUUU";
end case;
end process output_addr_process;
input_process: process (input_clk, rst) is
begin
-- Reset
if rising_edge(rst) then
input_lock <= lock_initial;
n0_buffer <= buffer2;
n1_buffer <= buffer1;
n2_buffer <= buffer0;
end if;
-- On falling edge, update buffer ages and unlock.
if falling_edge(input_clk) then
-- Update buffer ages
if (n2_buffer /= output_lock) then
n2_buffer <= n1_buffer;
end if;
n1_buffer <= n0_buffer;
n0_buffer <= input_lock;
-- Unlock the buffers
input_lock <= lock_initial;
end if;
-- On falling edge, unlock buffers.
if rising_edge(input_clk) then
-- Figure out the oldest unlocked buffer to use.
if (n2_buffer /= output_lock) then
input_lock <= n2_buffer;
else
input_lock <= n1_buffer;
end if;
end if;
end process input_process;
output_process: process (output_clk, rst) is
begin
-- Reset
if rising_edge(rst) then
output_lock <= lock_initial;
end if;
-- On falling edge, unlock buffer.
if falling_edge(output_clk) then
output_lock <= lock_initial;
end if;
-- On rising edge, find the newest buffer and lock for reading.
if rising_edge(output_clk) then
-- Figure out the newest buffer to use.
if (n0_buffer /= input_lock) then
output_lock <= n0_buffer;
else
output_lock <= n1_buffer;
end if;
end if;
end process output_process;
end triple_buffer_arbiter_arch;
|
--------------------------------------------------------------------------------
--
-- AM2901 Benchmark -- mem component
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept 17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept 17, 92 ZYCAD
--------------------------------------------------------------------------------
--library ZYCAD;
use work.TYPES.all;
use work.MVL7_functions.all;
use work.synthesis_types.all;
entity mem is
port (
RAM : inout Memory(15 downto 0);
F : in MVL7_vector(3 downto 0);
clk : in clock;
I : in MVL7_vector(8 downto 0);
RAM0, RAM3 : in MVL7;
Aadd, Badd : in integer range 15 downto 0
);
end mem;
architecture mem of mem is
begin
mem1 : block ( (clk = '1') and (not clk'stable) )
begin
-- WRITE TO RAM WITH/WITHOUT SHIFTING. RAM DESTINATIONS ARE
-- ADDRESSED BY "Badd".
RAM(Badd) <= guarded F when ((not(I(8)) and I(7)) = '1') else
RAM3 & F(3 downto 1) when ((I(8) and not(I(7))) = '1') else
F(2 downto 0) & RAM0 when ((I(8) and I(7)) = '1') else
RAM(Badd);
end block mem1;
end mem; |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_d_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_d_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:40 wig Exp $
-- $Date: 2004/04/06 10:50:40 $
-- $Log: inst_d_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:40 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_d_e
--
architecture rtl of inst_d_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity sigma_delta_dac is
generic (
g_divider : natural := 1;
g_width : positive := 12;
g_invert : boolean := false;
g_use_mid_only : boolean := true;
g_left_shift : natural := 1 );
port (
clock : in std_logic;
reset : in std_logic;
dac_in : in signed(g_width-1 downto 0);
dac_out : out std_logic );
end sigma_delta_dac;
architecture gideon of sigma_delta_dac is
signal dac_in_scaled : signed(g_width-1 downto g_left_shift);
signal converted : unsigned(g_width downto g_left_shift);
signal out_i : std_logic;
signal accu : unsigned(converted'range);
signal divider : integer range 0 to g_divider-1;
begin
dac_in_scaled <= left_scale(dac_in, g_left_shift);
converted <= (not dac_in_scaled(dac_in_scaled'high) & unsigned(dac_in_scaled(dac_in_scaled'high downto g_left_shift))) when g_use_mid_only else
(not dac_in_scaled(dac_in_scaled'high) & unsigned(dac_in_scaled(dac_in_scaled'high-1 downto g_left_shift))) & '0';
process(clock)
procedure sum_with_carry(a, b : unsigned; y : out unsigned; c : out std_logic ) is
variable a_ext : unsigned(a'length downto 0);
variable b_ext : unsigned(a'length downto 0);
variable summed : unsigned(a'length downto 0);
begin
a_ext := '0' & a;
b_ext := '0' & b;
summed := a_ext + b_ext;
c := summed(summed'left);
y := summed(a'length-1 downto 0);
end procedure;
variable a_new : unsigned(accu'range);
variable carry : std_logic;
begin
if rising_edge(clock) then
if divider = g_divider - 1 then
divider <= 0;
sum_with_carry(accu, converted, a_new, carry);
accu <= a_new;
if g_invert then
out_i <= not carry;
else
out_i <= carry;
end if;
else
divider <= divider + 1;
end if;
if reset='1' then
out_i <= not out_i;
accu <= (others => '0');
end if;
end if;
end process;
dac_out <= out_i;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_132 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_132;
architecture augh of cmp_132 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_132 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_132;
architecture augh of cmp_132 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
entity operator1 is
end entity;
architecture test of operator1 is
type t is (A, B);
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
begin
process is
variable x, y : t;
begin
x := A;
y := A;
assert (x and y) = A;
y := B;
assert (x and y) = B;
wait;
end process;
end architecture;
|
entity operator1 is
end entity;
architecture test of operator1 is
type t is (A, B);
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
begin
process is
variable x, y : t;
begin
x := A;
y := A;
assert (x and y) = A;
y := B;
assert (x and y) = B;
wait;
end process;
end architecture;
|
entity operator1 is
end entity;
architecture test of operator1 is
type t is (A, B);
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
begin
process is
variable x, y : t;
begin
x := A;
y := A;
assert (x and y) = A;
y := B;
assert (x and y) = B;
wait;
end process;
end architecture;
|
entity operator1 is
end entity;
architecture test of operator1 is
type t is (A, B);
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
begin
process is
variable x, y : t;
begin
x := A;
y := A;
assert (x and y) = A;
y := B;
assert (x and y) = B;
wait;
end process;
end architecture;
|
entity operator1 is
end entity;
architecture test of operator1 is
type t is (A, B);
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
begin
process is
variable x, y : t;
begin
x := A;
y := A;
assert (x and y) = A;
y := B;
assert (x and y) = B;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wrapper is
port(
clk : in std_logic;
reset : in std_logic;
write : in std_logic;
ack : out std_logic
);
end wrapper;
architecture a of wrapper is
-- compiling with std=93 produces an error here
component write is
port(
clk : in std_logic;
reset : in std_logic;
write : in std_logic;
ack : out std_logic
);
end component;
begin
--dut : entity work.write(a) -- compilation works with this type of instanciation/declaration, std=08 and component declaration on line 17 commented
dut: component write
port map(
clk => clk,
reset => reset,
write => write, --compiling with std=08 produces a error here
ack => ack
);
end architecture;
|
-------------------------------------------------------------------
-- FPGA Audio Project SoC IP
-- V0.1
-- Ultra-Embedded.com
--
-- This file was derived from the Plasma project by Steve Rhoads.
-- It has been modified to support dual port block RAM and contains
-- the FPGA-Audio Bootloader image.
--
-- Original copyright notice:
--
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic
(
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1
);
port
(
-- Port A
clka_i : in std_logic;
ena_i : in std_logic;
wea_i : in std_logic_vector(3 downto 0);
addra_i : in std_logic_vector(31 downto 2);
dataa_i : in std_logic_vector(31 downto 0);
dataa_o : out std_logic_vector(31 downto 0);
-- Port B
clkb_i : in std_logic;
enb_i : in std_logic;
web_i : in std_logic_vector(3 downto 0);
addrb_i : in std_logic_vector(31 downto 2);
datab_i : in std_logic_vector(31 downto 0);
datab_o : out std_logic_vector(31 downto 0)
);
end;
architecture logic of ram is
-----------------------------------------------
-- Signals
-----------------------------------------------
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
-- Which 8KB block
alias block_a_sel: std_logic_vector(2 downto 0) is addra_i(15 downto 13);
alias block_b_sel: std_logic_vector(2 downto 0) is addrb_i(15 downto 13);
-- Address within a 8KB block (without lower two bits)
alias block_a_addr : std_logic_vector(10 downto 0) is addra_i(12 downto 2);
alias block_b_addr : std_logic_vector(10 downto 0) is addrb_i(12 downto 2);
-- Block ena_i with 1 bit per memory block
signal block_a_enable: std_logic_vector(7 downto 0);
signal block_b_enable: std_logic_vector(7 downto 0);
-- Block Data Out
signal block_a_do: mem32_vector(7 downto 0);
signal block_b_do: mem32_vector(7 downto 0);
-- Remember which block was selected
signal block_a_sel_buf: std_logic_vector(2 downto 0);
signal block_b_sel_buf: std_logic_vector(2 downto 0);
constant ZERO : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
begin
-----------------------------------------------
-- Port A
-----------------------------------------------
block_a_enable <= "00000001" when (ena_i='1') and (block_a_sel="000") else
"00000010" when (ena_i='1') and (block_a_sel="001") else
"00000100" when (ena_i='1') and (block_a_sel="010") else
"00001000" when (ena_i='1') and (block_a_sel="011") else
"00010000" when (ena_i='1') and (block_a_sel="100") else
"00100000" when (ena_i='1') and (block_a_sel="101") else
"01000000" when (ena_i='1') and (block_a_sel="110") else
"10000000" when (ena_i='1') and (block_a_sel="111") else
"00000000";
process (clka_i, block_a_sel) is
begin
if rising_edge(clka_i) then
block_a_sel_buf <= block_a_sel;
end if;
end process;
process (block_a_do, block_a_sel_buf) is
begin
dataa_o <= block_a_do(conv_integer(block_a_sel_buf));
end process;
-----------------------------------------------
-- Port B
-----------------------------------------------
block_b_enable <= "00000001" when (enb_i='1') and (block_b_sel="000") else
"00000010" when (enb_i='1') and (block_b_sel="001") else
"00000100" when (enb_i='1') and (block_b_sel="010") else
"00001000" when (enb_i='1') and (block_b_sel="011") else
"00010000" when (enb_i='1') and (block_b_sel="100") else
"00100000" when (enb_i='1') and (block_b_sel="101") else
"01000000" when (enb_i='1') and (block_b_sel="110") else
"10000000" when (enb_i='1') and (block_b_sel="111") else
"00000000";
process (clkb_i, block_b_sel) is
begin
if rising_edge(clkb_i) then
block_b_sel_buf <= block_b_sel;
end if;
end process;
process (block_b_do, block_b_sel_buf) is
begin
datab_o <= block_b_do(conv_integer(block_b_sel_buf));
end process;
-----------------------------------------------
-- BRAM
-----------------------------------------------
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"00243c27038f8faf14af2c27000c40000008000c241400ac273c243c243c273c",
INIT_01 => X"0c263c0008020c263c0008020c263c0008020c263c0008020c263c0000008c00",
INIT_02 => X"0c00140010000c262426243c0c3c243c40afafafafaf270008020c263c000802",
INIT_03 => X"8f8f001430008c3cac3caf12240000af27000300083c0c020c0014000c240c02",
INIT_04 => X"82260c2610008000afaf2730038c3c240300038c001030008c3c3c08240c2703",
INIT_05 => X"2400900000243c001800108f000300140000008c3c8c3c000327038f8f001400",
INIT_06 => X"1424108f2d01110003af01af001424a0009000002424013c8f00148f2d01a014",
INIT_07 => X"8f8e3cafafaf2700080000008faf04af020c260caf3c2424af3c3caf27af0800",
INIT_08 => X"10afafafafafafafafafaf278faf03af27038f8f8f00142c00008e0004000000",
INIT_09 => X"00008f8e00040000008faf008e00008f3c3c24243c24afaf0000242410008f00",
INIT_0A => X"008faf008eafafa22610248f0010001000088f0018008faf000024008f00142c",
INIT_0B => X"04af00008f8eaf08241400008f8faf0c000024008f00142c00008f8e3c040000",
INIT_0C => X"af003c0024248f8f00082400008f240c001400040000008f00102c00008f8e00",
INIT_0D => X"8f8f028f0002002400008f000c0008af0caf000024248f001130009191a01025",
INIT_0E => X"24000824002490273c002531010091912512af0824a22427038f8f8f8f8f8f8f",
INIT_0F => X"00000800153000919126af082415302624120014001430142438000400003010",
INIT_10 => X"8f2400008f2400008f240c0008af0caf000024008f241000913014002490273c",
INIT_11 => X"4b42004153000000000000000000240832088fafaf2624242624020008240000",
INIT_12 => X"0000000000000000617420740a00617420740a0020740a0044214d5446004945",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(0)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(0),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(0)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(0),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"044202bde0b0bfb040bf82bd0000040000000000a560a4a0bd1d8404a5059c1c",
INIT_01 => X"0010100000000010100000000010100000000010100000000010100040008244",
INIT_02 => X"0000510050000052117310120013840480b0b1b2b3bfbd000000001010000000",
INIT_03 => X"b0bf0040420062035002bf02021004b0bd00e000000400600000500000040040",
INIT_04 => X"0410001080008480bfb0bd42e0420202e000e04200606300430202000400bde0",
INIT_05 => X"42e26682e8e70700a000a08800e00060646200a305420200e0bde0b0bf008000",
INIT_06 => X"6003408902050000e085258044464243006344e246e722078200408902056645",
INIT_07 => X"821110b1bfb0bd00000040008280408000001000bf1084a5b0040584bd880000",
INIT_08 => X"40b0b1b2b3b5b6b7bebfb4bd8285e084bde0b0b1bf0040425100020041004000",
INIT_09 => X"4300a302004100400082a600060040a4131e15161017a5a30000050360008380",
INIT_0A => X"0082a30003a0a66246a303a50055005600008200a000a5a20202a200a5004042",
INIT_0B => X"41a640008206a6000640c300a3a6a2000202a200a50040424400a40203410040",
INIT_0C => X"a6a6086663c6a5a6000004400082110000550040004000820060636400a40300",
INIT_0D => X"b7be20bf0080000440008200000000a500a202026205a3002242020902826008",
INIT_0E => X"63a200e70503e5c70400084a420a020a0640a600126206bde0b0b1b2b3b4b5b6",
INIT_0F => X"00000000224202090268a300032242e205e9004a00e8426063c202a10502c260",
INIT_10 => X"82044000820440008211000000a500a202026200a3054300026346654245c204",
INIT_11 => X"2152004c590000000000000000001100f70082a6a5310605f784800000044000",
INIT_12 => X"00000000000000006c65285242006c6528524200565242004900552141004e58",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(0)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(0),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(0)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(0),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"2008000000000000000000ff000068000000000000ff18000e000e0009008900",
INIT_01 => X"0008000000200009000000200009000000200009000000200009000000000020",
INIT_02 => X"0000ff00000000090009000000000900600000000000ff000020000800000020",
INIT_03 => X"000000ff000000200020000000868600ff000000001000200000ff0000200020",
INIT_04 => X"ff000000000000800000ff00000020ff00000000000000000020200000000000",
INIT_05 => X"001800183809001000000080000000ff1818000020002000000000000000ff00",
INIT_06 => X"ff00ff800040ff100080288018ff0000000018200009100080180080004000ff",
INIT_07 => X"800020000000ff000000f8008080ff80200102010000010200000080ff800000",
INIT_08 => X"0100000000000000000000ff80800080000000000000ff0310000000ff00f800",
INIT_09 => X"10000000000000f8008000000000f800000000002000000090880000010080a0",
INIT_0A => X"008000000000000a000000000000000000018000000000001616ff000000ff03",
INIT_0B => X"0000f8008000000100001000000000001616ff000000ff0310000000000000f8",
INIT_0C => X"001800200a000000000100f80080ff0000ff00ff00f8008000ff031800000000",
INIT_0D => X"0000100028f82000f80080000000010000001616ff000000000010000000ff0a",
INIT_0E => X"ff1001002a00000a001000ff5052000000000001000a00000000000000000000",
INIT_0F => X"18000100ff001000000a0001000000ff000000ff00ffffffff1030ff2c2cff00",
INIT_10 => X"8000f8008000f80080ff0000010000001616ff000000ff000000ff1800000a00",
INIT_11 => X"0045004c53000000000000000100ff010001800000000000000af8000100f800",
INIT_12 => X"00000000000000002972494f6f002972454f6f00324f6f0056004c0055005454",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(0)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(0),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(0)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(0),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"80c8001808101410051409e800140000000e004904fd2a008000900070006001",
INIT_01 => X"95f800003921950000003321950c00002d21951400002721951c000008000021",
INIT_02 => X"9500fb000b00864c49344500950024000014181c2024d800452195ec00003f21",
INIT_03 => X"101400fc080004000800140d0a030010e80008005900e3219500f7008600e321",
INIT_04 => X"ff016f01070000211410e801080400ff0800080800040100040000770d6f1808",
INIT_05 => X"01210021218800210a002318000800fb2a23001000100000081808101400fb00",
INIT_06 => X"e701e9148021fd210814211821fb0100000021238088210010211914802100fb",
INIT_07 => X"201000181c14e000f70009001018fc142113d0101400bc1810000010e818d500",
INIT_08 => X"102024282c34383c404430b81c20081c200814181c00f5e823001000fa000900",
INIT_09 => X"230010100015000900201000100009140000180400011418212143100c002021",
INIT_0A => X"0020100010141c08827243140027006200301c00c90018180300ff001800f4e8",
INIT_0B => X"0e10090020101449157f2a00141c18f90300ff001800f4e82300101000350009",
INIT_0C => X"142a002108011c1400bc0609001cfff900c500f40009002000cde82300101000",
INIT_0D => X"3c4021442109210609001c00f9004914f9180300ff15180026ff27010200b908",
INIT_0E => X"ff26e2010008000b002183ff2100848383301c5a01088348082024282c303438",
INIT_0F => X"2100ce00adff2701020814490622ffff803600bc00eefff9ff2140fa0300ff09",
INIT_10 => X"1c1809001c1809001cfff9004914f9180300ff001815e40083fffc2101000b00",
INIT_11 => X"00410021439494acacc4dcf40c64ffbcff301c1418800610010b0900bc180900",
INIT_12 => X"00000000000000000a6e6e4d6f000a6e784d6f000a4d6f00210054004c00215f",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(0)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(0),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(0)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(0),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(1)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(1),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(1)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(1),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(1)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(1),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(1)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(1),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(1)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(1),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(1)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(1),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(1)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(1),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(1)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(1),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(2)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(2),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(2)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(2),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(2)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(2),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(2)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(2),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(2)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(2),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(2)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(2),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(2)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(2),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(2)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(2),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(3)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(3),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(3)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(3),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(3)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(3),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(3)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(3),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(3)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(3),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(3)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(3),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(3)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(3),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(3)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(3),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(4)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(4),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(4)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(4),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(4)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(4),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(4)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(4),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(4)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(4),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(4)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(4),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(4)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(4),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(4)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(4),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(5)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(5),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(5)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(5),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(5)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(5),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(5)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(5),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(5)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(5),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(5)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(5),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(5)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(5),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(5)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(5),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(6)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(6),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(6)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(6),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(6)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(6),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(6)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(6),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(6)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(6),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(6)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(6),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(6)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(6),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(6)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(6),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(7)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(7),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(7)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(7),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(7)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(7),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(7)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(7),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(7)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(7),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(7)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(7),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(7)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(7),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(7)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(7),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block7
end; --architecture logic
|
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pci_exp_usrapp_tx.vhd
-- Description: PCI Express dsport Tx interface.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity pci_exp_usrapp_tx is
port (
trn_td : out std_logic_vector (63 downto 0 );
trn_trem_n : out std_logic_vector (7 downto 0 );
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_terrfwd_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_clk : in std_logic;
trn_reset_n : in std_logic;
trn_lnk_up_n : in std_logic;
trn_tdst_rdy_n : in std_logic;
trn_tdst_dsc_n : in std_logic;
trn_tbuf_av : in std_logic_vector (5 downto 0);
rx_tx_read_data : in std_logic_vector(31 downto 0);
rx_tx_read_data_valid : in std_logic;
tx_rx_read_data_valid : out std_logic
);
end pci_exp_usrapp_tx;
architecture rtl of pci_exp_usrapp_tx is
component tests
generic (
test_selector : in string := String'("pio_writeReadBack_test0")
);
port (
trn_td : out std_logic_vector (63 downto 0 );
trn_trem_n : out std_logic_vector (7 downto 0 );
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_terrfwd_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_clk : in std_logic;
trn_reset_n : in std_logic;
trn_lnk_up_n : in std_logic;
trn_tdst_rdy_n : in std_logic;
trn_tdst_dsc_n : in std_logic;
trn_tbuf_av : in std_logic_vector(5 downto 0);
rx_tx_read_data : in std_logic_vector(31 downto 0);
rx_tx_read_data_valid : in std_logic;
tx_rx_read_data_valid : out std_logic
);
end component;
begin
TESTS_INST : tests
generic map (
test_selector => String'("pio_writeReadBack_test0")
)
port map (
trn_td => trn_td,
trn_trem_n => trn_trem_n,
trn_tsof_n => trn_tsof_n,
trn_teof_n => trn_teof_n,
trn_terrfwd_n => trn_terrfwd_n,
trn_tsrc_rdy_n => trn_tsrc_rdy_n,
trn_tsrc_dsc_n => trn_tsrc_dsc_n,
trn_clk => trn_clk,
trn_reset_n => trn_reset_n,
trn_lnk_up_n => trn_lnk_up_n,
trn_tdst_rdy_n => trn_tdst_rdy_n,
trn_tdst_dsc_n => trn_tdst_dsc_n,
trn_tbuf_av => trn_tbuf_av,
rx_tx_read_data => rx_tx_read_data,
rx_tx_read_data_valid => rx_tx_read_data_valid,
tx_rx_read_data_valid => tx_rx_read_data_valid
);
end; -- pci_exp_usrapp_tx
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ab_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 08:31:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ab_e-rtl-a.vhd,v 1.5 2006/06/26 08:39:42 wig Exp $
-- $Date: 2006/06/26 08:39:42 $
-- $Log: inst_ab_e-rtl-a.vhd,v $
-- Revision 1.5 2006/06/26 08:39:42 wig
-- Update more testcases (up to generic)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ab_e
--
architecture rtl of inst_ab_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
entity unidade_controle_recepcao is
port(liga : in std_logic;
reset : in std_logic;
CD : in std_logic;
clock : in std_logic;
enable_recepcao : out std_logic;
DTR : out std_logic;
s_estado : out std_logic_vector(1 downto 0)); -- depuracao
end unidade_controle_recepcao;
architecture unidade_controle_recepcao_arch of unidade_controle_recepcao is
type tipo_estado is (inicial, ligado, recepcao);
signal estado : tipo_estado;
begin
process (clock, estado, reset, liga, CD)
begin
if reset = '1' then
estado <= inicial;
elsif (clock'event and clock = '1') then
case estado is
when inicial =>
if liga = '1' then
estado <= ligado;
end if;
when ligado =>
if liga = '1' then
if CD = '1' then
estado <= recepcao;
end if;
else
estado <= inicial;
end if;
when recepcao =>
if CD = '0' then
estado <= inicial;
end if;
end case;
end if;
end process;
process (estado)
begin
case estado is
when inicial =>
s_estado <= "00";
DTR <= '1';
when ligado =>
s_estado <= "01";
when recepcao =>
s_estado <= "10";
enable_recepcao <= '1';
end case;
end process;
end unidade_controle_recepcao_arch; |
------------------------------------------------------------------------
-- RS232RefCom.vhd
------------------------------------------------------------------------
-- Author: Dan Pederson
-- Copyright 2004 Digilent, Inc.
------------------------------------------------------------------------
-- Description: This file defines a UART which tranfers data from
-- serial form to parallel form and vice versa.
------------------------------------------------------------------------
-- Revision History:
-- 07/15/04 (Created) DanP
-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant
-- in the Clock Dividing Processes
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Rs232RefComp is
Port (
TXD : out std_logic := '1';
RXD : in std_logic;
CLK : in std_logic; --Master Clock = 50MHz
DBIN : in std_logic_vector (7 downto 0); --Data Bus in
DBOUT : out std_logic_vector (7 downto 0); --Data Bus out
RDA : inout std_logic; --Read Data Available
TBE : inout std_logic := '1'; --Transfer Bus Empty
RD : in std_logic; --Read Strobe
WR : in std_logic; --Write Strobe
PE : out std_logic; --Parity Error Flag
FE : out std_logic; --Frame Error Flag
OE : out std_logic; --Overwrite Error Flag
RST : in std_logic := '0'); --Master Reset
end Rs232RefComp;
architecture Behavioral of Rs232RefComp is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
--Receive state machine
type rstate is (
strIdle, --Idle state
strEightDelay, --Delays for 8 clock cycles
strGetData, --Shifts in the 8 data bits, and checks parity
strCheckStop --Sets framing error flag if Stop bit is wrong
);
type tstate is (
sttIdle, --Idle state
sttTransfer, --Move data into shift register
sttShift --Shift out data
);
type TBEstate is (
stbeIdle,
stbeSetTBE,
stbeWaitLoad,
stbeWaitWrite
);
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
constant baudDivide : std_logic_vector(7 downto 0) := "10100011"; --Baud Rate dividor, set now for a rate of 9600.
--Found by dividing 50MHz by 9600 and 16.
signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register
signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register
signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register
signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register
signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk
signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk
signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times
signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer
signal rClk : std_logic := '0'; --Receiving Clock
signal tClk : std_logic; --Transfering Clock
signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits
signal parError: std_logic; --Parity error bit
signal frameError: std_logic; --Frame error bit
signal CE : std_logic; --Clock enable for the latch
signal ctRst : std_logic := '0';
signal load : std_logic := '0';
signal shift : std_logic := '0';
signal par : std_logic;
signal tClkRST : std_logic := '0';
signal rShift : std_logic := '0';
signal dataRST : std_logic := '0';
signal dataIncr: std_logic := '0';
signal strCur : rstate := strIdle; --Current state in the Receive state machine
signal strNext : rstate; --Next state in the Receive state machine
signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine
signal sttNext : tstate; --Next state in the Transfer staet machine
signal stbeCur : TBEstate := stbeIdle;
signal stbeNext: TBEstate;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
frameError <= not rdSReg(9);
parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) );
DBOUT <= rdReg;
tfReg <= DBIN;
par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) );
--Clock Dividing Functions--
process (CLK, clkDiv) --set up clock divide for rClk
begin
if (Clk = '1' and Clk'event) then
if (clkDiv = baudDivide) then
clkDiv <= "000000000";
else
clkDiv <= clkDiv +1;
end if;
end if;
end process;
process (clkDiv, rClk, CLK) --Define rClk
begin
if CLK = '1' and CLK'Event then
if clkDiv = baudDivide then
rClk <= not rClk;
else
rClk <= rClk;
end if;
end if;
end process;
process (rClk) --set up clock divide for tClk
begin
if (rClk = '1' and rClk'event) then
rClkDiv <= rClkDiv +1;
end if;
end process;
tClk <= rClkDiv(3); --define tClk
process (rClk, ctRst) --set up a counter based on rClk
begin
if rClk = '1' and rClk'Event then
if ctRst = '1' then
ctr <= "0000";
else
ctr <= ctr +1;
end if;
end if;
end process;
process (tClk, tClkRST) --set up a counter based on tClk
begin
if (tClk = '1' and tClk'event) then
if tClkRST = '1' then
tfCtr <= "0000";
else
tfCtr <= tfCtr +1;
end if;
end if;
end process;
--This process controls the error flags--
process (rClk, RST, RD, CE)
begin
if RD = '1' or RST = '1' then
FE <= '0';
OE <= '0';
RDA <= '0';
PE <= '0';
elsif rClk = '1' and rClk'event then
if CE = '1' then
FE <= frameError;
OE <= RDA;
RDA <= '1';
PE <= parError;
rdReg(7 downto 0) <= rdSReg (7 downto 0);
end if;
end if;
end process;
--This process controls the receiving shift register--
process (rClk, rShift)
begin
if rClk = '1' and rClk'Event then
if rShift = '1' then
rdSReg <= (RXD & rdSReg(9 downto 1));
end if;
end if;
end process;
--This process controls the dataCtr to keep track of shifted values--
process (rClk, dataRST)
begin
if (rClk = '1' and rClk'event) then
if dataRST = '1' then
dataCtr <= "0000";
elsif dataIncr = '1' then
dataCtr <= dataCtr +1;
end if;
end if;
end process;
--Receiving State Machine--
process (rClk, RST)
begin
if rClk = '1' and rClk'Event then
if RST = '1' then
strCur <= strIdle;
else
strCur <= strNext;
end if;
end if;
end process;
--This process generates the sequence of steps needed receive the data
process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA)
begin
case strCur is
when strIdle =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
CE <= '0';
if RXD = '0' then
ctRst <= '1';
strNext <= strEightDelay;
else
ctRst <= '0';
strNext <= strIdle;
end if;
when strEightDelay =>
dataIncr <= '0';
rShift <= '0';
CE <= '0';
if ctr(2 downto 0) = "111" then
ctRst <= '1';
dataRST <= '1';
strNext <= strGetData;
else
ctRst <= '0';
dataRST <= '0';
strNext <= strEightDelay;
end if;
when strGetData =>
CE <= '0';
dataRst <= '0';
if ctr(3 downto 0) = "1111" then
ctRst <= '1';
dataIncr <= '1';
rShift <= '1';
else
ctRst <= '0';
dataIncr <= '0';
rShift <= '0';
end if;
if dataCtr = "1010" then
strNext <= strCheckStop;
else
strNext <= strGetData;
end if;
when strCheckStop =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
ctRst <= '0';
CE <= '1';
strNext <= strIdle;
end case;
end process;
--TBE State Machine--
process (CLK, RST)
begin
if CLK = '1' and CLK'Event then
if RST = '1' then
stbeCur <= stbeIdle;
else
stbeCur <= stbeNext;
end if;
end if;
end process;
--This process gererates the sequence of events needed to control the TBE flag--
process (stbeCur, CLK, WR, DBIN, load)
begin
case stbeCur is
when stbeIdle =>
TBE <= '1';
if WR = '1' then
stbeNext <= stbeSetTBE;
else
stbeNext <= stbeIdle;
end if;
when stbeSetTBE =>
TBE <= '0';
if load = '1' then
stbeNext <= stbeWaitLoad;
else
stbeNext <= stbeSetTBE;
end if;
when stbeWaitLoad =>
if load = '0' then
stbeNext <= stbeWaitWrite;
else
stbeNext <= stbeWaitLoad;
end if;
when stbeWaitWrite =>
if WR = '0' then
stbeNext <= stbeIdle;
else
stbeNext <= stbeWaitWrite;
end if;
end case;
end process;
--This process loads and shifts out the transfer shift register--
process (load, shift, tClk, tfSReg)
begin
TXD <= tfsReg(0);
if tClk = '1' and tClk'Event then
if load = '1' then
tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0');
end if;
if shift = '1' then
tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1));
end if;
end if;
end process;
-- Transfer State Machine--
process (tClk, RST)
begin
if (tClk = '1' and tClk'Event) then
if RST = '1' then
sttCur <= sttIdle;
else
sttCur <= sttNext;
end if;
end if;
end process;
-- This process generates the sequence of steps needed transfer the data--
process (sttCur, tfCtr, tfReg, TBE, tclk)
begin
case sttCur is
when sttIdle =>
tClkRST <= '0';
shift <= '0';
load <= '0';
if TBE = '1' then
sttNext <= sttIdle;
else
sttNext <= sttTransfer;
end if;
when sttTransfer =>
shift <= '0';
load <= '1';
tClkRST <= '1';
sttNext <= sttShift;
when sttShift =>
shift <= '1';
load <= '0';
tClkRST <= '0';
if tfCtr = "1100" then
sttNext <= sttIdle;
else
sttNext <= sttShift;
end if;
end case;
end process;
end Behavioral; |
------------------------------------------------------------------------
-- RS232RefCom.vhd
------------------------------------------------------------------------
-- Author: Dan Pederson
-- Copyright 2004 Digilent, Inc.
------------------------------------------------------------------------
-- Description: This file defines a UART which tranfers data from
-- serial form to parallel form and vice versa.
------------------------------------------------------------------------
-- Revision History:
-- 07/15/04 (Created) DanP
-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant
-- in the Clock Dividing Processes
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Rs232RefComp is
Port (
TXD : out std_logic := '1';
RXD : in std_logic;
CLK : in std_logic; --Master Clock = 50MHz
DBIN : in std_logic_vector (7 downto 0); --Data Bus in
DBOUT : out std_logic_vector (7 downto 0); --Data Bus out
RDA : inout std_logic; --Read Data Available
TBE : inout std_logic := '1'; --Transfer Bus Empty
RD : in std_logic; --Read Strobe
WR : in std_logic; --Write Strobe
PE : out std_logic; --Parity Error Flag
FE : out std_logic; --Frame Error Flag
OE : out std_logic; --Overwrite Error Flag
RST : in std_logic := '0'); --Master Reset
end Rs232RefComp;
architecture Behavioral of Rs232RefComp is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
--Receive state machine
type rstate is (
strIdle, --Idle state
strEightDelay, --Delays for 8 clock cycles
strGetData, --Shifts in the 8 data bits, and checks parity
strCheckStop --Sets framing error flag if Stop bit is wrong
);
type tstate is (
sttIdle, --Idle state
sttTransfer, --Move data into shift register
sttShift --Shift out data
);
type TBEstate is (
stbeIdle,
stbeSetTBE,
stbeWaitLoad,
stbeWaitWrite
);
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
constant baudDivide : std_logic_vector(7 downto 0) := "10100011"; --Baud Rate dividor, set now for a rate of 9600.
--Found by dividing 50MHz by 9600 and 16.
signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register
signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register
signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register
signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register
signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk
signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk
signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times
signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer
signal rClk : std_logic := '0'; --Receiving Clock
signal tClk : std_logic; --Transfering Clock
signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits
signal parError: std_logic; --Parity error bit
signal frameError: std_logic; --Frame error bit
signal CE : std_logic; --Clock enable for the latch
signal ctRst : std_logic := '0';
signal load : std_logic := '0';
signal shift : std_logic := '0';
signal par : std_logic;
signal tClkRST : std_logic := '0';
signal rShift : std_logic := '0';
signal dataRST : std_logic := '0';
signal dataIncr: std_logic := '0';
signal strCur : rstate := strIdle; --Current state in the Receive state machine
signal strNext : rstate; --Next state in the Receive state machine
signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine
signal sttNext : tstate; --Next state in the Transfer staet machine
signal stbeCur : TBEstate := stbeIdle;
signal stbeNext: TBEstate;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
frameError <= not rdSReg(9);
parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) );
DBOUT <= rdReg;
tfReg <= DBIN;
par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) );
--Clock Dividing Functions--
process (CLK, clkDiv) --set up clock divide for rClk
begin
if (Clk = '1' and Clk'event) then
if (clkDiv = baudDivide) then
clkDiv <= "000000000";
else
clkDiv <= clkDiv +1;
end if;
end if;
end process;
process (clkDiv, rClk, CLK) --Define rClk
begin
if CLK = '1' and CLK'Event then
if clkDiv = baudDivide then
rClk <= not rClk;
else
rClk <= rClk;
end if;
end if;
end process;
process (rClk) --set up clock divide for tClk
begin
if (rClk = '1' and rClk'event) then
rClkDiv <= rClkDiv +1;
end if;
end process;
tClk <= rClkDiv(3); --define tClk
process (rClk, ctRst) --set up a counter based on rClk
begin
if rClk = '1' and rClk'Event then
if ctRst = '1' then
ctr <= "0000";
else
ctr <= ctr +1;
end if;
end if;
end process;
process (tClk, tClkRST) --set up a counter based on tClk
begin
if (tClk = '1' and tClk'event) then
if tClkRST = '1' then
tfCtr <= "0000";
else
tfCtr <= tfCtr +1;
end if;
end if;
end process;
--This process controls the error flags--
process (rClk, RST, RD, CE)
begin
if RD = '1' or RST = '1' then
FE <= '0';
OE <= '0';
RDA <= '0';
PE <= '0';
elsif rClk = '1' and rClk'event then
if CE = '1' then
FE <= frameError;
OE <= RDA;
RDA <= '1';
PE <= parError;
rdReg(7 downto 0) <= rdSReg (7 downto 0);
end if;
end if;
end process;
--This process controls the receiving shift register--
process (rClk, rShift)
begin
if rClk = '1' and rClk'Event then
if rShift = '1' then
rdSReg <= (RXD & rdSReg(9 downto 1));
end if;
end if;
end process;
--This process controls the dataCtr to keep track of shifted values--
process (rClk, dataRST)
begin
if (rClk = '1' and rClk'event) then
if dataRST = '1' then
dataCtr <= "0000";
elsif dataIncr = '1' then
dataCtr <= dataCtr +1;
end if;
end if;
end process;
--Receiving State Machine--
process (rClk, RST)
begin
if rClk = '1' and rClk'Event then
if RST = '1' then
strCur <= strIdle;
else
strCur <= strNext;
end if;
end if;
end process;
--This process generates the sequence of steps needed receive the data
process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA)
begin
case strCur is
when strIdle =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
CE <= '0';
if RXD = '0' then
ctRst <= '1';
strNext <= strEightDelay;
else
ctRst <= '0';
strNext <= strIdle;
end if;
when strEightDelay =>
dataIncr <= '0';
rShift <= '0';
CE <= '0';
if ctr(2 downto 0) = "111" then
ctRst <= '1';
dataRST <= '1';
strNext <= strGetData;
else
ctRst <= '0';
dataRST <= '0';
strNext <= strEightDelay;
end if;
when strGetData =>
CE <= '0';
dataRst <= '0';
if ctr(3 downto 0) = "1111" then
ctRst <= '1';
dataIncr <= '1';
rShift <= '1';
else
ctRst <= '0';
dataIncr <= '0';
rShift <= '0';
end if;
if dataCtr = "1010" then
strNext <= strCheckStop;
else
strNext <= strGetData;
end if;
when strCheckStop =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
ctRst <= '0';
CE <= '1';
strNext <= strIdle;
end case;
end process;
--TBE State Machine--
process (CLK, RST)
begin
if CLK = '1' and CLK'Event then
if RST = '1' then
stbeCur <= stbeIdle;
else
stbeCur <= stbeNext;
end if;
end if;
end process;
--This process gererates the sequence of events needed to control the TBE flag--
process (stbeCur, CLK, WR, DBIN, load)
begin
case stbeCur is
when stbeIdle =>
TBE <= '1';
if WR = '1' then
stbeNext <= stbeSetTBE;
else
stbeNext <= stbeIdle;
end if;
when stbeSetTBE =>
TBE <= '0';
if load = '1' then
stbeNext <= stbeWaitLoad;
else
stbeNext <= stbeSetTBE;
end if;
when stbeWaitLoad =>
if load = '0' then
stbeNext <= stbeWaitWrite;
else
stbeNext <= stbeWaitLoad;
end if;
when stbeWaitWrite =>
if WR = '0' then
stbeNext <= stbeIdle;
else
stbeNext <= stbeWaitWrite;
end if;
end case;
end process;
--This process loads and shifts out the transfer shift register--
process (load, shift, tClk, tfSReg)
begin
TXD <= tfsReg(0);
if tClk = '1' and tClk'Event then
if load = '1' then
tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0');
end if;
if shift = '1' then
tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1));
end if;
end if;
end process;
-- Transfer State Machine--
process (tClk, RST)
begin
if (tClk = '1' and tClk'Event) then
if RST = '1' then
sttCur <= sttIdle;
else
sttCur <= sttNext;
end if;
end if;
end process;
-- This process generates the sequence of steps needed transfer the data--
process (sttCur, tfCtr, tfReg, TBE, tclk)
begin
case sttCur is
when sttIdle =>
tClkRST <= '0';
shift <= '0';
load <= '0';
if TBE = '1' then
sttNext <= sttIdle;
else
sttNext <= sttTransfer;
end if;
when sttTransfer =>
shift <= '0';
load <= '1';
tClkRST <= '1';
sttNext <= sttShift;
when sttShift =>
shift <= '1';
load <= '0';
tClkRST <= '0';
if tfCtr = "1100" then
sttNext <= sttIdle;
else
sttNext <= sttShift;
end if;
end case;
end process;
end Behavioral; |
------------------------------------------------------------------------
-- RS232RefCom.vhd
------------------------------------------------------------------------
-- Author: Dan Pederson
-- Copyright 2004 Digilent, Inc.
------------------------------------------------------------------------
-- Description: This file defines a UART which tranfers data from
-- serial form to parallel form and vice versa.
------------------------------------------------------------------------
-- Revision History:
-- 07/15/04 (Created) DanP
-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant
-- in the Clock Dividing Processes
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Rs232RefComp is
Port (
TXD : out std_logic := '1';
RXD : in std_logic;
CLK : in std_logic; --Master Clock = 50MHz
DBIN : in std_logic_vector (7 downto 0); --Data Bus in
DBOUT : out std_logic_vector (7 downto 0); --Data Bus out
RDA : inout std_logic; --Read Data Available
TBE : inout std_logic := '1'; --Transfer Bus Empty
RD : in std_logic; --Read Strobe
WR : in std_logic; --Write Strobe
PE : out std_logic; --Parity Error Flag
FE : out std_logic; --Frame Error Flag
OE : out std_logic; --Overwrite Error Flag
RST : in std_logic := '0'); --Master Reset
end Rs232RefComp;
architecture Behavioral of Rs232RefComp is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
--Receive state machine
type rstate is (
strIdle, --Idle state
strEightDelay, --Delays for 8 clock cycles
strGetData, --Shifts in the 8 data bits, and checks parity
strCheckStop --Sets framing error flag if Stop bit is wrong
);
type tstate is (
sttIdle, --Idle state
sttTransfer, --Move data into shift register
sttShift --Shift out data
);
type TBEstate is (
stbeIdle,
stbeSetTBE,
stbeWaitLoad,
stbeWaitWrite
);
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
constant baudDivide : std_logic_vector(7 downto 0) := "10100011"; --Baud Rate dividor, set now for a rate of 9600.
--Found by dividing 50MHz by 9600 and 16.
signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register
signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register
signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register
signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register
signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk
signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk
signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times
signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer
signal rClk : std_logic := '0'; --Receiving Clock
signal tClk : std_logic; --Transfering Clock
signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits
signal parError: std_logic; --Parity error bit
signal frameError: std_logic; --Frame error bit
signal CE : std_logic; --Clock enable for the latch
signal ctRst : std_logic := '0';
signal load : std_logic := '0';
signal shift : std_logic := '0';
signal par : std_logic;
signal tClkRST : std_logic := '0';
signal rShift : std_logic := '0';
signal dataRST : std_logic := '0';
signal dataIncr: std_logic := '0';
signal strCur : rstate := strIdle; --Current state in the Receive state machine
signal strNext : rstate; --Next state in the Receive state machine
signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine
signal sttNext : tstate; --Next state in the Transfer staet machine
signal stbeCur : TBEstate := stbeIdle;
signal stbeNext: TBEstate;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
frameError <= not rdSReg(9);
parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) );
DBOUT <= rdReg;
tfReg <= DBIN;
par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) );
--Clock Dividing Functions--
process (CLK, clkDiv) --set up clock divide for rClk
begin
if (Clk = '1' and Clk'event) then
if (clkDiv = baudDivide) then
clkDiv <= "000000000";
else
clkDiv <= clkDiv +1;
end if;
end if;
end process;
process (clkDiv, rClk, CLK) --Define rClk
begin
if CLK = '1' and CLK'Event then
if clkDiv = baudDivide then
rClk <= not rClk;
else
rClk <= rClk;
end if;
end if;
end process;
process (rClk) --set up clock divide for tClk
begin
if (rClk = '1' and rClk'event) then
rClkDiv <= rClkDiv +1;
end if;
end process;
tClk <= rClkDiv(3); --define tClk
process (rClk, ctRst) --set up a counter based on rClk
begin
if rClk = '1' and rClk'Event then
if ctRst = '1' then
ctr <= "0000";
else
ctr <= ctr +1;
end if;
end if;
end process;
process (tClk, tClkRST) --set up a counter based on tClk
begin
if (tClk = '1' and tClk'event) then
if tClkRST = '1' then
tfCtr <= "0000";
else
tfCtr <= tfCtr +1;
end if;
end if;
end process;
--This process controls the error flags--
process (rClk, RST, RD, CE)
begin
if RD = '1' or RST = '1' then
FE <= '0';
OE <= '0';
RDA <= '0';
PE <= '0';
elsif rClk = '1' and rClk'event then
if CE = '1' then
FE <= frameError;
OE <= RDA;
RDA <= '1';
PE <= parError;
rdReg(7 downto 0) <= rdSReg (7 downto 0);
end if;
end if;
end process;
--This process controls the receiving shift register--
process (rClk, rShift)
begin
if rClk = '1' and rClk'Event then
if rShift = '1' then
rdSReg <= (RXD & rdSReg(9 downto 1));
end if;
end if;
end process;
--This process controls the dataCtr to keep track of shifted values--
process (rClk, dataRST)
begin
if (rClk = '1' and rClk'event) then
if dataRST = '1' then
dataCtr <= "0000";
elsif dataIncr = '1' then
dataCtr <= dataCtr +1;
end if;
end if;
end process;
--Receiving State Machine--
process (rClk, RST)
begin
if rClk = '1' and rClk'Event then
if RST = '1' then
strCur <= strIdle;
else
strCur <= strNext;
end if;
end if;
end process;
--This process generates the sequence of steps needed receive the data
process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA)
begin
case strCur is
when strIdle =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
CE <= '0';
if RXD = '0' then
ctRst <= '1';
strNext <= strEightDelay;
else
ctRst <= '0';
strNext <= strIdle;
end if;
when strEightDelay =>
dataIncr <= '0';
rShift <= '0';
CE <= '0';
if ctr(2 downto 0) = "111" then
ctRst <= '1';
dataRST <= '1';
strNext <= strGetData;
else
ctRst <= '0';
dataRST <= '0';
strNext <= strEightDelay;
end if;
when strGetData =>
CE <= '0';
dataRst <= '0';
if ctr(3 downto 0) = "1111" then
ctRst <= '1';
dataIncr <= '1';
rShift <= '1';
else
ctRst <= '0';
dataIncr <= '0';
rShift <= '0';
end if;
if dataCtr = "1010" then
strNext <= strCheckStop;
else
strNext <= strGetData;
end if;
when strCheckStop =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
ctRst <= '0';
CE <= '1';
strNext <= strIdle;
end case;
end process;
--TBE State Machine--
process (CLK, RST)
begin
if CLK = '1' and CLK'Event then
if RST = '1' then
stbeCur <= stbeIdle;
else
stbeCur <= stbeNext;
end if;
end if;
end process;
--This process gererates the sequence of events needed to control the TBE flag--
process (stbeCur, CLK, WR, DBIN, load)
begin
case stbeCur is
when stbeIdle =>
TBE <= '1';
if WR = '1' then
stbeNext <= stbeSetTBE;
else
stbeNext <= stbeIdle;
end if;
when stbeSetTBE =>
TBE <= '0';
if load = '1' then
stbeNext <= stbeWaitLoad;
else
stbeNext <= stbeSetTBE;
end if;
when stbeWaitLoad =>
if load = '0' then
stbeNext <= stbeWaitWrite;
else
stbeNext <= stbeWaitLoad;
end if;
when stbeWaitWrite =>
if WR = '0' then
stbeNext <= stbeIdle;
else
stbeNext <= stbeWaitWrite;
end if;
end case;
end process;
--This process loads and shifts out the transfer shift register--
process (load, shift, tClk, tfSReg)
begin
TXD <= tfsReg(0);
if tClk = '1' and tClk'Event then
if load = '1' then
tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0');
end if;
if shift = '1' then
tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1));
end if;
end if;
end process;
-- Transfer State Machine--
process (tClk, RST)
begin
if (tClk = '1' and tClk'Event) then
if RST = '1' then
sttCur <= sttIdle;
else
sttCur <= sttNext;
end if;
end if;
end process;
-- This process generates the sequence of steps needed transfer the data--
process (sttCur, tfCtr, tfReg, TBE, tclk)
begin
case sttCur is
when sttIdle =>
tClkRST <= '0';
shift <= '0';
load <= '0';
if TBE = '1' then
sttNext <= sttIdle;
else
sttNext <= sttTransfer;
end if;
when sttTransfer =>
shift <= '0';
load <= '1';
tClkRST <= '1';
sttNext <= sttShift;
when sttShift =>
shift <= '1';
load <= '0';
tClkRST <= '0';
if tfCtr = "1100" then
sttNext <= sttIdle;
else
sttNext <= sttShift;
end if;
end case;
end process;
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity MAR is
port(
clk, lat: in std_logic;
busC : in std_logic_vector(15 downto 0);
M_ad16: out std_logic_vector(15 downto 0);
M_ad8: out std_logic_vector(7 downto 0)
);
end MAR;
architecture BEHAVIOR of MAR is
signal rst:std_logic_vector(15 downto 0);
begin
M_ad16 <= rst;
M_ad8 <= rst(7 downto 0);
process(clk)begin
if (clk'event and (clk = '1') and (lat ='1')) then
rst <= busC;
else
null;
end if;
end process;
end BEHAVIOR;
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity MAR is
port(
clk, lat: in std_logic;
busC : in std_logic_vector(15 downto 0);
M_ad16: out std_logic_vector(15 downto 0);
M_ad8: out std_logic_vector(7 downto 0)
);
end MAR;
architecture BEHAVIOR of MAR is
signal rst:std_logic_vector(15 downto 0);
begin
M_ad16 <= rst;
M_ad8 <= rst(7 downto 0);
process(clk)begin
if (clk'event and (clk = '1') and (lat ='1')) then
rst <= busC;
else
null;
end if;
end process;
end BEHAVIOR;
|
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY conv_grande_tb IS
END conv_grande_tb;
ARCHITECTURE behavior OF conv_grande_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bcd_g
PORT(
entrada_int : IN std_logic_vector(31 downto 0);
decenas_millones : OUT std_logic_vector(3 downto 0);
millones : OUT std_logic_vector(3 downto 0);
centenas_mill : OUT std_logic_vector(3 downto 0);
decenas_mill : OUT std_logic_vector(3 downto 0);
millares : OUT std_logic_vector(3 downto 0);
centenas : OUT std_logic_vector(3 downto 0);
decenas : OUT std_logic_vector(3 downto 0);
unidades : OUT std_logic_vector(3 downto 0);
prueba : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal entrada_int : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal decenas_millones : std_logic_vector(3 downto 0);
signal millones : std_logic_vector(3 downto 0);
signal centenas_mill : std_logic_vector(3 downto 0);
signal decenas_mill : std_logic_vector(3 downto 0);
signal millares : std_logic_vector(3 downto 0);
signal centenas : std_logic_vector(3 downto 0);
signal decenas : std_logic_vector(3 downto 0);
signal unidades : std_logic_vector(3 downto 0);
signal prueba : std_logic_vector(15 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bcd_g PORT MAP (
entrada_int => entrada_int,
decenas_millones => decenas_millones,
millones => millones,
centenas_mill => centenas_mill,
decenas_mill => decenas_mill,
millares => millares,
centenas => centenas,
decenas => decenas,
unidades => unidades,
prueba=>prueba
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
entrada_int<="00000000000000000000000001000100";
wait for 100 ns;
--
-- insert stimulus here
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY conv_grande_tb IS
END conv_grande_tb;
ARCHITECTURE behavior OF conv_grande_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bcd_g
PORT(
entrada_int : IN std_logic_vector(31 downto 0);
decenas_millones : OUT std_logic_vector(3 downto 0);
millones : OUT std_logic_vector(3 downto 0);
centenas_mill : OUT std_logic_vector(3 downto 0);
decenas_mill : OUT std_logic_vector(3 downto 0);
millares : OUT std_logic_vector(3 downto 0);
centenas : OUT std_logic_vector(3 downto 0);
decenas : OUT std_logic_vector(3 downto 0);
unidades : OUT std_logic_vector(3 downto 0);
prueba : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal entrada_int : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal decenas_millones : std_logic_vector(3 downto 0);
signal millones : std_logic_vector(3 downto 0);
signal centenas_mill : std_logic_vector(3 downto 0);
signal decenas_mill : std_logic_vector(3 downto 0);
signal millares : std_logic_vector(3 downto 0);
signal centenas : std_logic_vector(3 downto 0);
signal decenas : std_logic_vector(3 downto 0);
signal unidades : std_logic_vector(3 downto 0);
signal prueba : std_logic_vector(15 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bcd_g PORT MAP (
entrada_int => entrada_int,
decenas_millones => decenas_millones,
millones => millones,
centenas_mill => centenas_mill,
decenas_mill => decenas_mill,
millares => millares,
centenas => centenas,
decenas => decenas,
unidades => unidades,
prueba=>prueba
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
entrada_int<="00000000000000000000000001000100";
wait for 100 ns;
--
-- insert stimulus here
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:48:07 05/19/2016
-- Design Name:
-- Module Name: Komp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Komp is
Port ( x : in STD_LOGIC_VECTOR(5 downto 1);
y : out STD_LOGIC_VECTOR(5 downto 1));
end Komp;
architecture Behavioral of Komp is
component Zelle is port (
Cin, Xi: in STD_LOGIC;
Cout, Yi: out STD_LOGIC);
end component;
signal C1, C2, C3, C4, C5: std_logic;
begin
cell0: Zelle port map ('0', x(1), C1, y(1));
cell1: Zelle port map (C1, x(2), C2, y(2));
cell2: Zelle port map (C2, x(3), C3, y(3));
cell3: Zelle port map (C3, x(4), C4, y(4));
cell4: Zelle port map (C4, x(5), C5, y(5));
end Behavioral;
|
entity vecorder1 is
end entity;
architecture test of vecorder1 is
type int_array is array (integer range <>) of integer;
signal s : int_array(0 to 1) := ( 0 => 0, 1 => 1 );
begin
process is
variable x : int_array(0 to 1) := ( 0 => 0, 1 => 1 );
variable y : int_array(1 downto 0) := ( 0 => 0, 1 => 1 );
begin
assert x(0) = 0 report "one";
assert x(1) = 1 report "two";
assert x = ( 0, 1 );
x := ( 2, 3 );
report integer'image(x(0));
report integer'image(x(1));
assert x(0) = 2 report "three";
assert x(1) = 3 report "four";
assert x = ( 2, 3 ) report "five";
assert ( 2, 3 ) = x report "six";
assert s(0) = 0 report "s one";
assert s(1) = 1 report "s two";
s <= ( 2, 3 );
wait for 0 ns;
report integer'image(s(0));
report integer'image(s(1));
assert s(0) = 2 report "s three";
assert s(1) = 3 report "s four";
assert y(0) = 0 report "y one";
assert y(1) = 1 report "y two";
assert y = ( 1, 0 );
y := ( 2, 3 );
report integer'image(y(0));
report integer'image(y(1));
assert y(0) = 3 report "y three";
assert y(1) = 2 report "y four";
assert y = ( 2, 3 ) report "y five";
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
entity cipher_tb is
end cipher_tb;
architecture behavior of cipher_tb is
component cipher
port (
din : in state;
dout : out state
);
end component;
--Inputs
signal din : state;
--Outputs
signal dout : state;
begin
uut: cipher port map (
din => din,
dout => dout
);
stim_proc: process
begin
--din <= x"d42711aee0bf98f1b8b45de51e415230";
din <= x"d4bf5d30e0b452aeb84111f11e2798e5";
wait for 10 ns;
--assert dout = x"d4bf5d30e0b452aeb84111f11e2798e5" report "cipher: lookup failure" severity failure;
assert dout = x"046681e5e0cb199a48f8d37a2806264c" report "cipher: mix failure" severity failure;
wait;
end process;
end;
|
-- Author: Ronaldo Dall'Agnol Veiga
-- @roniveiga
-- UFRGS - Instituto de Informática
-- Sistemas Digitais
-- Profa. Dra. Fernanda Gusmão de Lima Kastensmidt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity control_unit is
Port (
-- inputs
clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
enable_neander : in STD_LOGIC;
N : in STD_LOGIC;
Z : in STD_LOGIC;
s_exec_nop, s_exec_sta, s_exec_lda, s_exec_add, s_exec_or, s_exec_shr, s_exec_shl, s_exec_mul,
s_exec_and, s_exec_not, s_exec_jmp, s_exec_jn, s_exec_jz, s_exec_hlt : in STD_LOGIC;
-- outputs--
-- operation selector
sel_ula : out STD_LOGIC_VECTOR(2 downto 0);
-- registers loads
loadAC : out STD_LOGIC;
loadPC : out STD_LOGIC;
loadREM : out STD_LOGIC;
loadRDM : out STD_LOGIC;
loadRI : out STD_LOGIC;
loadN : out STD_LOGIC;
loadZ : out STD_LOGIC;
-- write in memory
wr_enable_mem : out STD_LOGIC_VECTOR (0 downto 0);
-- selector for mux_rem: 0 for PC, 1 for RDM
sel : out STD_LOGIC;
-- Program Counter increment
PC_inc : out STD_LOGIC;
-- selector for mux_rdm: 0 for mem(read), 1 for AC
sel_mux_RDM : out STD_LOGIC;
-- stop signal
stop : out STD_LOGIC
);
end control_unit;
architecture Behavioral of control_unit is
type state_machine is (IDLE, BUSCA_INSTRUCAO, LER_INSTRUCAO, CARREGA_RI,
EXEC_STA2, BUSCA_DADOS, BUSCA_ENDERECO, TRATA_JUMP, TRATA_JUMP_FAIL,
READ_MEMORY, EXEC_STA, TRATA_HLT, EXEC_ULA, EXEC_ULA2);
signal current_state : state_machine;
signal next_state : state_machine;
signal stop_s : STD_LOGIC;
begin
process (clk_in, rst_in)
variable state_timer: integer; -- states for two cicles
begin
if (rst_in = '1') then
stop_s <= '0';
loadAC <= '0';
loadPC <= '0';
PC_inc <= '0';
loadREM <= '0';
loadRDM <= '0';
loadRI <= '0';
loadN <= '0';
loadZ <= '0';
wr_enable_mem <= "0";
state_timer := 1;
next_state <= IDLE;
elsif (clk_in = '1' and clk_in'EVENT) then
case current_state is
when IDLE =>
if (enable_neander = '1' and stop_s = '0') then -- start signal
next_state <= BUSCA_INSTRUCAO;
else
next_state <= IDLE;
end if;
-- E0: REM <- PC
when BUSCA_INSTRUCAO =>
sel_mux_RDM <= '0';
loadAC <= '0';
loadPC <= '0';
PC_inc <= '0';
loadRDM <= '0';
loadRI <= '0';
wr_enable_mem <= "0";
loadN <= '0';
loadZ <= '0';
-- select 0 for PC->REM
sel <= '0';
-- load REM
loadREM <= '1';
next_state <= LER_INSTRUCAO;
-- E1: RDM <- MEM(read), PC+
when LER_INSTRUCAO =>
loadREM <= '0';
loadRDM <= '1';
PC_inc <= '1';
next_state <= CARREGA_RI;
-- E2: RI <- RDM
when CARREGA_RI =>
loadRDM <= '0';
PC_inc <= '0';
loadRI <= '1';
if (s_exec_hlt = '1') then -- HLT
next_state <= TRATA_HLT;
elsif (s_exec_nop = '1') then -- NOP
next_state <= BUSCA_INSTRUCAO;
elsif (s_exec_not = '1') then -- NOT
next_state <= EXEC_ULA2;
elsif ((s_exec_jn = '1') and (N = '0')) or ((s_exec_jz = '1') and (z = '0')) then -- jump fail
next_state <= TRATA_JUMP_FAIL;
else
next_state <= BUSCA_DADOS;
end if;
-- E3: REM <- PC
when BUSCA_DADOS =>
loadRI <= '0';
sel <= '0';
loadREM <= '1';
next_state <= READ_MEMORY;
-- E4: RDM <- MEM(read), PC+
WHEN READ_MEMORY =>
loadREM <= '0';
loadRDM <= '1';
PC_inc <= '1';
if (s_exec_add = '1') then -- ADD
next_state <= BUSCA_ENDERECO;
elsif (s_exec_or = '1') then -- OR
next_state <= BUSCA_ENDERECO;
elsif (s_exec_and = '1') then -- AND
next_state <= BUSCA_ENDERECO;
elsif (s_exec_lda = '1') then -- LDA
next_state <= BUSCA_ENDERECO;
elsif (s_exec_shr = '1') then -- SHR
next_state <= BUSCA_ENDERECO;
elsif (s_exec_shl = '1') then -- SHL
next_state <= BUSCA_ENDERECO;
elsif (s_exec_mul = '1') then -- MUL
next_state <= BUSCA_ENDERECO;
elsif (s_exec_sta = '1') then -- STA
next_state <= BUSCA_ENDERECO;
elsif ((s_exec_jmp = '1') or ((s_exec_jn = '1') and (N = '1')) or ((s_exec_jz = '1') and (z = '1'))) then -- real jump
next_state <= TRATA_JUMP;
else
next_state <= IDLE;
end if;
-- E5: REM <- RDM
when BUSCA_ENDERECO =>
loadRDM <= '0';
PC_inc <= '0';
sel <= '1'; -- select 1 for RDM->REM
loadREM <= '1';
if (s_exec_add = '1') then -- ADD
next_state <= EXEC_ULA;
elsif (s_exec_or = '1') then -- OR
next_state <= EXEC_ULA;
elsif (s_exec_and = '1') then -- AND
next_state <= EXEC_ULA;
elsif (s_exec_lda = '1') then -- LDA
next_state <= EXEC_ULA;
elsif (s_exec_shr = '1') then -- SHR
next_state <= EXEC_ULA;
elsif (s_exec_shl = '1') then -- SHL
next_state <= EXEC_ULA;
elsif (s_exec_mul = '1') then -- MUL
next_state <= EXEC_ULA;
elsif (s_exec_sta = '1') then -- STA
next_state <= EXEC_STA;
end if;
-- E6: RDM <- MEM(read)
when EXEC_ULA =>
loadREM <= '0';
loadRDM <= '1';
if (s_exec_add = '1') then -- ADD
sel_ula <= "000";
elsif (s_exec_or = '1') then -- OR
sel_ula <= "010";
elsif (s_exec_and = '1') then -- AND
sel_ula <= "001";
elsif (s_exec_not = '1') then -- NOT
sel_ula <= "011";
elsif (s_exec_lda = '1') then -- LDA
sel_ula <= "100";
elsif (s_exec_shr = '1') then -- SHR
sel_ula <= "101";
elsif (s_exec_shl = '1') then -- SHL
sel_ula <= "110";
elsif (s_exec_mul = '1') then -- MUL
sel_ula <= "111";
end if;
next_state <= EXEC_ULA2;
-- E7: AC <- ULA
when EXEC_ULA2 =>
loadRDM <= '0';
loadRI <= '0';
loadAC <= '1';
loadN <= '1';
loadZ <= '1';
next_state <= BUSCA_INSTRUCAO;
-- E8: RDM <- AC
when EXEC_STA =>
loadREM <= '0';
sel_mux_RDM <= '1'; -- select 1 for AC->RDM
loadRDM <= '1';
next_state <= EXEC_STA2;
-- E9: MEM <- RDM(write)
when EXEC_STA2 =>
sel_mux_RDM <= '0';
loadRDM <= '0';
wr_enable_mem <= "1";
next_state <= BUSCA_INSTRUCAO;
-- E10: PC <- RDM
when TRATA_JUMP =>
loadRDM <= '0';
PC_inc <= '0';
loadPC <= '1';
next_state <= BUSCA_INSTRUCAO;
-- E11: PC+
when TRATA_JUMP_FAIL =>
loadRI <= '0';
PC_inc <= '1';
next_state <= BUSCA_INSTRUCAO;
-- E12: STOP
when TRATA_HLT =>
loadRI <= '0';
stop_s <= '1';
next_state <= IDLE;
-- others
when others =>
next_state <= IDLE;
end case;
if state_timer = 0 then -- states for two cicles
current_state <= next_state;
state_timer := 1;
else
current_state <= current_state;
state_timer := state_timer -1;
end if;
end if;
stop <= stop_s;
end process;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_grain128 is
generic (
DEBUG : boolean := false;
FAST : boolean := false
);
end entity;
architecture test of tb_grain128 is
-- some testvectors:
constant GRAIN_KEY1 : unsigned(127 downto 0) := (others => '0');
constant GRAIN_IV1 : unsigned( 95 downto 0) := (others => '0');
constant GRAIN_KS1 : unsigned(127 downto 0) := x"0fd9deefeb6fad437bf43fce35849cfe";
constant GRAIN_KEY2 : unsigned(127 downto 0) := x"0123456789abcdef123456789abcdef0";
constant GRAIN_IV2 : unsigned( 95 downto 0) := x"0123456789abcdef12345678";
constant GRAIN_KS2 : unsigned(127 downto 0) := x"db032aff3788498b57cb894fffb6bb96";
-- DUT signal
signal clk, clken, areset : std_logic;
signal key_in, iv_in : std_logic;
signal key : unsigned(127 downto 0);
signal iv : unsigned(95 downto 0);
signal init, keystream, keystream_valid : std_logic;
-- monitor the output:
signal key_memory : unsigned(127 downto 0);
signal key_count : integer;
begin
-- the one and only, the DUT
DUT: entity work.grain128
generic map (
DEBUG => DEBUG,
FAST => FAST
)
port map (
CLK_I => clk,
CLKEN_I => clken,
ARESET_I => areset,
KEY_I => key_in,
IV_I => iv_in,
INIT_I => init,
KEYSTREAM_O => keystream,
KEYSTREAM_VALID_O => keystream_valid
);
-- clock generator:
clkgen_proc: process
begin
clk <= '0'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
end process;
-- dummy clock enable: every fourth cycle
clken_proc: process
begin
clken <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
clken <= '1';
wait until rising_edge(clk);
end process;
-- output monitor:
mon_proc: process(clk, areset)
begin
if areset = '1' then
key_memory <= (others => 'X');
key_count <= 0;
elsif rising_edge(clk) then
if clken = '1' then
if keystream_valid = '1' then
key_count <= key_count + 1;
key_memory <= key_memory(key_memory'high-1 downto 0) & keystream;
else
key_memory <= (others => 'X');
key_count <= 0;
end if;
end if;
end if;
end process;
-- this process will do all the testing
tester_proc: process
-- reset everything
procedure do_reset is
begin
key_in <= 'X';
iv_in <= 'X';
init <= '0';
areset <= '1';
wait for 100 ns;
areset <= '0';
end procedure;
-- initialize grain with key and IV
procedure do_init is
begin
wait until rising_edge(clk) and clken = '1';
init <= '1';
wait until rising_edge(clk) and clken = '1';
init <= '0';
for i in key'range loop
key_in <= key(key'high);
iv_in <= iv(iv'high);
key <= key rol 1;
iv <= iv rol 1;
wait until rising_edge(clk) and clken = '1';
end loop;
end procedure;
begin
-- 1. start with a reset:
do_reset;
-- 2. inject key and IV
key <= GRAIN_KEY1;
iv <= GRAIN_IV1;
do_init;
-- 3. verify output:
wait on clk until key_count = 128;
assert key_memory = GRAIN_KS1
report "incorrect output with IV = 0 and KEY = 0"
severity failure;
-- 4. try the other testvector
-- do_reset;
key <= GRAIN_KEY2;
iv <= GRAIN_IV2;
do_init;
wait on clk until key_count = 128;
assert
key_memory = GRAIN_KS2
report "incorrect output with IV = 0123.. and KEY = 0123.."
severity failure;
-- done:
report "ALL DONE" severity failure;
wait;
end process;
end test;
-- asim tb_grain128 ; wave /DUT/* ; run 100 us
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
use work.mem_pkg.all;
entity memory_stage is
port (mem_d : in mem_in;
mem_q : out mem_out);
end entity memory_stage;
architecture Behavioral of memory_stage is
begin -- architecture Behavioral
end architecture Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
use work.mem_pkg.all;
entity memory_stage is
port (mem_d : in mem_in;
mem_q : out mem_out);
end entity memory_stage;
architecture Behavioral of memory_stage is
begin -- architecture Behavioral
end architecture Behavioral;
|
library ieee;
--Comment
use ieee.std_logic_1164.all;
--Comment
use ieee.numeric_std.all;
library ieee;
-- Comment
use ieee.std_logic_1164.all;
-- Comment
-- Comment 2
-- Comment 3
use ieee.numeric_std.all;
-- Comment
use ieee.std_logic_arith.all;
library ieee;
-- Comment
use ieee.std_logic_1164.all;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_g8j_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
addr2 : in std_logic_vector(awidth-1 downto 0);
ce2 : in std_logic;
q2 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_g8j_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
signal addr2_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem0 : mem_array := (
0 => "00000000", 1 => "00001000", 2 => "00001100", 3 => "00010000",
4 => "00010011", 5 => "00010110", 6 => "00011000", 7 => "00011011",
8 => "00011101", 9 => "00100000", 10 => "00100010", 11 => "00100100",
12 => "00100110", 13 => "00101000", 14 => "00101010", 15 => "00101011",
16 => "00101101", 17 => "00101111", 18 => "00110001", 19 => "00110010",
20 => "00110100", 21 => "00110110", 22 => "00110111", 23 => "00111001",
24 => "00111010", 25 => "00111100", 26 => "00111101", 27 => "00111111",
28 => "01000000", 29 => "01000010", 30 => "01000011", 31 => "01000100",
32 => "01000110", 33 => "01000111", 34 => "01001000", 35 => "01001010",
36 => "01001011", 37 => "01001100", 38 => "01001110", 39 => "01001111",
40 => "01010000", 41 => "01010001", 42 => "01010011", 43 => "01010100",
44 => "01010101", 45 => "01010110", 46 => "01010111", 47 => "01011001",
48 => "01011010", 49 => "01011011", 50 => "01011100", 51 => "01011101",
52 => "01011110", 53 => "01100000", 54 => "01100001", 55 => "01100010",
56 => "01100011", 57 => "01100100", 58 => "01100101", 59 => "01100110",
60 => "01100111", 61 => "01101000", 62 => "01101001", 63 => "01101010",
64 => "01101011", 65 => "01101101", 66 => "01101110", 67 => "01101111",
68 => "01110000", 69 => "01110001", 70 => "01110010", 71 => "01110011",
72 => "01110100", 73 => "01110101", 74 => "01110110", 75 => "01110111",
76 => "01111000", 77 => "01111001", 78 => "01111010", 79 => "01111011",
80 => "01111100", 81 to 82=> "01111101", 83 => "01111110", 84 => "01111111",
85 => "10000000", 86 => "10000001", 87 => "10000010", 88 => "10000011",
89 => "10000100", 90 => "10000101", 91 => "10000110", 92 => "10000111",
93 => "10001000", 94 => "10001001", 95 to 96=> "10001010", 97 => "10001011",
98 => "10001100", 99 => "10001101", 100 => "10001110", 101 => "10001111",
102 => "10010000", 103 => "10010001", 104 to 105=> "10010010", 106 => "10010011",
107 => "10010100", 108 => "10010101", 109 => "10010110", 110 => "10010111",
111 to 112=> "10011000", 113 => "10011001", 114 => "10011010", 115 => "10011011",
116 => "10011100", 117 => "10011101", 118 to 119=> "10011110", 120 => "10011111",
121 => "10100000", 122 => "10100001", 123 to 124=> "10100010", 125 => "10100011",
126 => "10100100", 127 => "10100101", 128 => "10100110", 129 to 130=> "10100111",
131 => "10101000", 132 => "10101001", 133 => "10101010", 134 to 135=> "10101011",
136 => "10101100", 137 => "10101101", 138 => "10101110", 139 to 140=> "10101111",
141 => "10110000", 142 => "10110001", 143 to 144=> "10110010", 145 => "10110011",
146 => "10110100", 147 to 148=> "10110101", 149 => "10110110", 150 => "10110111",
151 => "10111000", 152 to 153=> "10111001", 154 => "10111010", 155 => "10111011",
156 to 157=> "10111100", 158 => "10111101", 159 => "10111110", 160 to 161=> "10111111",
162 => "11000000", 163 => "11000001", 164 to 165=> "11000010", 166 => "11000011",
167 to 168=> "11000100", 169 => "11000101", 170 => "11000110", 171 to 172=> "11000111",
173 => "11001000", 174 => "11001001", 175 to 176=> "11001010", 177 => "11001011",
178 to 179=> "11001100", 180 => "11001101", 181 => "11001110", 182 to 183=> "11001111",
184 => "11010000", 185 to 186=> "11010001", 187 => "11010010", 188 to 189=> "11010011",
190 => "11010100", 191 => "11010101", 192 to 193=> "11010110", 194 => "11010111",
195 to 196=> "11011000", 197 => "11011001", 198 to 199=> "11011010", 200 => "11011011",
201 to 202=> "11011100", 203 => "11011101", 204 to 205=> "11011110", 206 => "11011111",
207 => "11100000", 208 to 209=> "11100001", 210 => "11100010", 211 to 212=> "11100011",
213 => "11100100", 214 to 215=> "11100101", 216 => "11100110", 217 to 218=> "11100111",
219 => "11101000", 220 to 221=> "11101001", 222 => "11101010", 223 to 224=> "11101011",
225 to 226=> "11101100", 227 => "11101101", 228 to 229=> "11101110", 230 => "11101111",
231 to 232=> "11110000", 233 => "11110001", 234 to 235=> "11110010", 236 => "11110011",
237 to 238=> "11110100", 239 => "11110101", 240 to 241=> "11110110", 242 to 243=> "11110111",
244 => "11111000", 245 to 246=> "11111001", 247 => "11111010", 248 to 249=> "11111011",
250 to 251=> "11111100", 252 => "11111101", 253 to 254=> "11111110", 255 => "11111111" );
signal mem1 : mem_array := (
0 => "00000000", 1 => "00001000", 2 => "00001100", 3 => "00010000",
4 => "00010011", 5 => "00010110", 6 => "00011000", 7 => "00011011",
8 => "00011101", 9 => "00100000", 10 => "00100010", 11 => "00100100",
12 => "00100110", 13 => "00101000", 14 => "00101010", 15 => "00101011",
16 => "00101101", 17 => "00101111", 18 => "00110001", 19 => "00110010",
20 => "00110100", 21 => "00110110", 22 => "00110111", 23 => "00111001",
24 => "00111010", 25 => "00111100", 26 => "00111101", 27 => "00111111",
28 => "01000000", 29 => "01000010", 30 => "01000011", 31 => "01000100",
32 => "01000110", 33 => "01000111", 34 => "01001000", 35 => "01001010",
36 => "01001011", 37 => "01001100", 38 => "01001110", 39 => "01001111",
40 => "01010000", 41 => "01010001", 42 => "01010011", 43 => "01010100",
44 => "01010101", 45 => "01010110", 46 => "01010111", 47 => "01011001",
48 => "01011010", 49 => "01011011", 50 => "01011100", 51 => "01011101",
52 => "01011110", 53 => "01100000", 54 => "01100001", 55 => "01100010",
56 => "01100011", 57 => "01100100", 58 => "01100101", 59 => "01100110",
60 => "01100111", 61 => "01101000", 62 => "01101001", 63 => "01101010",
64 => "01101011", 65 => "01101101", 66 => "01101110", 67 => "01101111",
68 => "01110000", 69 => "01110001", 70 => "01110010", 71 => "01110011",
72 => "01110100", 73 => "01110101", 74 => "01110110", 75 => "01110111",
76 => "01111000", 77 => "01111001", 78 => "01111010", 79 => "01111011",
80 => "01111100", 81 to 82=> "01111101", 83 => "01111110", 84 => "01111111",
85 => "10000000", 86 => "10000001", 87 => "10000010", 88 => "10000011",
89 => "10000100", 90 => "10000101", 91 => "10000110", 92 => "10000111",
93 => "10001000", 94 => "10001001", 95 to 96=> "10001010", 97 => "10001011",
98 => "10001100", 99 => "10001101", 100 => "10001110", 101 => "10001111",
102 => "10010000", 103 => "10010001", 104 to 105=> "10010010", 106 => "10010011",
107 => "10010100", 108 => "10010101", 109 => "10010110", 110 => "10010111",
111 to 112=> "10011000", 113 => "10011001", 114 => "10011010", 115 => "10011011",
116 => "10011100", 117 => "10011101", 118 to 119=> "10011110", 120 => "10011111",
121 => "10100000", 122 => "10100001", 123 to 124=> "10100010", 125 => "10100011",
126 => "10100100", 127 => "10100101", 128 => "10100110", 129 to 130=> "10100111",
131 => "10101000", 132 => "10101001", 133 => "10101010", 134 to 135=> "10101011",
136 => "10101100", 137 => "10101101", 138 => "10101110", 139 to 140=> "10101111",
141 => "10110000", 142 => "10110001", 143 to 144=> "10110010", 145 => "10110011",
146 => "10110100", 147 to 148=> "10110101", 149 => "10110110", 150 => "10110111",
151 => "10111000", 152 to 153=> "10111001", 154 => "10111010", 155 => "10111011",
156 to 157=> "10111100", 158 => "10111101", 159 => "10111110", 160 to 161=> "10111111",
162 => "11000000", 163 => "11000001", 164 to 165=> "11000010", 166 => "11000011",
167 to 168=> "11000100", 169 => "11000101", 170 => "11000110", 171 to 172=> "11000111",
173 => "11001000", 174 => "11001001", 175 to 176=> "11001010", 177 => "11001011",
178 to 179=> "11001100", 180 => "11001101", 181 => "11001110", 182 to 183=> "11001111",
184 => "11010000", 185 to 186=> "11010001", 187 => "11010010", 188 to 189=> "11010011",
190 => "11010100", 191 => "11010101", 192 to 193=> "11010110", 194 => "11010111",
195 to 196=> "11011000", 197 => "11011001", 198 to 199=> "11011010", 200 => "11011011",
201 to 202=> "11011100", 203 => "11011101", 204 to 205=> "11011110", 206 => "11011111",
207 => "11100000", 208 to 209=> "11100001", 210 => "11100010", 211 to 212=> "11100011",
213 => "11100100", 214 to 215=> "11100101", 216 => "11100110", 217 to 218=> "11100111",
219 => "11101000", 220 to 221=> "11101001", 222 => "11101010", 223 to 224=> "11101011",
225 to 226=> "11101100", 227 => "11101101", 228 to 229=> "11101110", 230 => "11101111",
231 to 232=> "11110000", 233 => "11110001", 234 to 235=> "11110010", 236 => "11110011",
237 to 238=> "11110100", 239 => "11110101", 240 to 241=> "11110110", 242 to 243=> "11110111",
244 => "11111000", 245 to 246=> "11111001", 247 => "11111010", 248 to 249=> "11111011",
250 to 251=> "11111100", 252 => "11111101", 253 to 254=> "11111110", 255 => "11111111" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem0 : signal is "block_rom";
attribute syn_rom_style of mem1 : signal is "block_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem0 : signal is "block";
attribute ROM_STYLE of mem1 : signal is "block";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
memory_access_guard_2: process (addr2)
begin
addr2_tmp <= addr2;
--synthesis translate_off
if (CONV_INTEGER(addr2) > mem_size-1) then
addr2_tmp <= (others => '0');
else
addr2_tmp <= addr2;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem0(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem0(CONV_INTEGER(addr1_tmp));
end if;
if (ce2 = '1') then
q2 <= mem1(CONV_INTEGER(addr2_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_g8j is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_g8j is
component Loop_loop_height_g8j_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR;
addr2 : IN STD_LOGIC_VECTOR;
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_g8j_rom_U : component Loop_loop_height_g8j_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1,
addr2 => address2,
ce2 => ce2,
q2 => q2);
end architecture;
|
----------------------------------------------------------------------
-- OscChpGat
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Blink some LEDs based only on OnChip resources.
-- Use the OnDie RC-Oscillator plus a bunch
-- of registers for the FlipFlip toggle counter.
--
-- Added the CCC clock gating unit to demonstrate its behaivour.
-- Watch how it controls gating the clock input.
--
-- GATE -> (Din) -> LATCH -> (Dout) -> AND(a)
-- CLOCK -> (Ena) -> LATCH CLOCK -> AND(b) -> GATED_CLOCK
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
entity OscChpGat is
port( LED0 : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
LED3 : out std_logic;
LED4 : out std_logic;
LED5 : out std_logic;
LED6 : out std_logic;
LED7 : out std_logic );
end OscChpGat;
----------------------------------------------------------------------
architecture rtl of OscChpGat is
component brdLexSwx is
port ( o_lex, o_pbx : out std_logic );
end component;
component myChpOsc is
port ( i_rst_n : in std_logic;
o_clk : out std_logic );
end component;
component myDffCnt
generic (N : Integer);
port ( i_rst_n, i_clk : in std_logic;
o_q : out std_logic_vector(N-1 downto 0) );
end component;
component myCccGat is
port( i_clk, i_gat : in std_logic;
o_clk : out std_logic );
end component;
signal s_clk, s_ccc, s_gat : std_logic;
signal s_cnt : std_logic_vector(29 downto 0);
signal s_led : std_logic_vector(7 downto 0);
signal s_lex : std_logic;
begin
brdLexSwx_0 : brdLexSwx
port map(
o_lex => s_lex,
o_pbx => open );
myChpOsc_0 : myChpOsc
port map(
i_rst_n => '1',
o_clk => s_clk );
myDffCnt_0 : myDffCnt
generic map( N => s_cnt'high+1 )
port map(
i_rst_n => '1',
i_clk => s_clk,
o_q => s_cnt );
myCccGat_0 : myCccGat
port map(
i_clk => s_led(3),
i_gat => s_gat,
o_clk => s_ccc );
s_gat <= s_led(7) xor (s_led(6) and s_led(1));
s_led <= s_cnt(s_cnt'high downto s_cnt'high-7);
LED0 <= s_lex;
LED1 <= s_lex xor s_led(3); -- blink clock
LED2 <= s_lex;
LED3 <= s_lex xor s_gat;
LED4 <= s_lex;
LED5 <= s_lex xor s_ccc;
LED6 <= s_lex xor s_led(6);
LED7 <= s_lex xor s_led(7);
end rtl;
----------------------------------------------------------------------
|
library IEEE;
use ieee.std_logic_1164.all;
entity recursive_stack is
generic ( size: natural := 4);
port (
data_in : in natural;
data_out : out natural;
enable : in std_logic;
push_pop: in std_logic;
clk : in std_logic
);
end recursive_stack;
architecture arch_recursive_stack of recursive_stack is
type data_stack_type is array (0 to size) of natural;
signal data : data_stack_type := (others => 0);
signal zero_addr : std_logic := '0';
begin
process(clk)
variable addr : natural := 0;
begin
if falling_edge(clk) and enable = '1' then
if push_pop = '1' then
if addr < size then
if zero_addr = '0' then
zero_addr <= '1';
else
addr := addr + 1;
end if;
data(addr) <= data_in;
data_out <= data_in;
end if;
else
if addr > 0 then
addr := addr - 1;
else -- if addr = 0
zero_addr <= '0';
end if;
data_out <= data(addr);
end if;
end if;
end process;
end arch_recursive_stack;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-15 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_02300_good.vhd
-- File Creation date : 2015-04-15
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Preservation of clock name: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
--CODE
entity CNE_02300_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end CNE_02300_good;
architecture Behavioral of CNE_02300_good is
begin
DFF1:DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_D,
o_Q => o_Q,
o_Q_n => open
);
end Behavioral;
--CODE |
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: filtering_algorithm_pkg - Package
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
use ieee.math_real.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package filtering_algorithm_pkg is
constant N_MAX : integer := 32768;
constant D : integer := 3;
constant L_MAX : integer := 6;
constant K_MAX : integer := 256;
constant N_MAX_TREE_NODES : integer := 2*N_MAX;
constant STACK_SIZE : integer := 32768;
constant HEAP_SIZE : integer := 256;
constant COORD_BITWIDTH : integer := 16;
constant COORD_BITWIDTH_EXT : integer := 32;
constant INDEX_BITWIDTH : integer := integer(ceil(log2(real(K_MAX))));
constant NODE_POINTER_BITWIDTH : integer := integer(ceil(log2(real(N_MAX_TREE_NODES))));
constant CNTR_POINTER_BITWIDTH : integer := integer(ceil(log2(real(HEAP_SIZE))));
constant MUL_FRACTIONAL_BITS : integer := 6;
constant MUL_INTEGER_BITS : integer := 12;
constant MUL_BITWIDTH : integer := MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS;
constant MUL_CORE_LATENCY : integer := 3;
constant DYN_ALLOC : boolean := true;
constant SYNTHESIS : boolean := false;
constant VIRTEX7 : boolean := true;
constant USE_DSP_FOR_ADD : boolean := false;
constant PARALLEL_UNITS : integer := 1;
subtype coord_type is std_logic_vector(COORD_BITWIDTH-1 downto 0);
subtype centre_index_type is unsigned(INDEX_BITWIDTH-1 downto 0);
subtype node_address_type is std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
subtype centre_list_address_type is std_logic_vector(CNTR_POINTER_BITWIDTH-1 downto 0);
type data_type is array(0 to D-1) of coord_type;
subtype coord_type_ext is std_logic_vector(COORD_BITWIDTH_EXT-1 downto 0);
type data_type_ext is array(0 to D-1) of coord_type_ext;
type node_data_type is
record
wgtCent : data_type_ext;
midPoint : data_type;
bnd_lo : data_type;
bnd_hi : data_type;
sum_sq : coord_type_ext;
count : coord_type;
left : node_address_type;
right : node_address_type;
end record;
-- size of node_data_type : 3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH
-- array types for parallelism
type par_centre_index_type is array(0 to PARALLEL_UNITS-1) of centre_index_type;
type par_centre_list_address_type is array(0 to PARALLEL_UNITS-1) of centre_list_address_type;
type par_coord_type is array(0 to PARALLEL_UNITS-1) of coord_type;
type par_coord_type_ext is array(0 to PARALLEL_UNITS-1) of coord_type_ext;
type par_data_type is array(0 to PARALLEL_UNITS-1) of data_type;
type par_data_type_ext is array(0 to PARALLEL_UNITS-1) of data_type_ext;
type par_node_address_type is array(0 to PARALLEL_UNITS-1) of node_address_type;
type par_node_data_type is array(0 to PARALLEL_UNITS-1) of node_data_type;
type par_element_type_ext is array(0 to D-1) of std_logic_vector(PARALLEL_UNITS*COORD_BITWIDTH_EXT-1 downto 0);
type par_element_type_ext_sum is array(0 to D-1) of std_logic_vector(COORD_BITWIDTH_EXT+integer(ceil(log2(real(PARALLEL_UNITS))))-1 downto 0);
-- helper functions
function stdlogic_2_datapoint(c : std_logic_vector) return data_type;
function stdlogic_2_datapoint_ext(c : std_logic_vector) return data_type_ext;
function datapoint_2_stdlogic(c : data_type) return std_logic_vector;
function datapoint_ext_2_stdlogic(c : data_type_ext) return std_logic_vector;
function nodedata_2_stdlogic(n : node_data_type) return std_logic_vector;
function stdlogic_2_nodedata(n : std_logic_vector) return node_data_type;
function saturate(val : std_logic_vector) return std_logic_vector;
function sext(val : std_logic_vector; length : integer) return std_logic_vector;
function zext(val : std_logic_vector; length : integer) return std_logic_vector;
function conv_ext_2_normal(val : data_type_ext) return data_type;
function conv_normal_2_ext(val : data_type) return data_type_ext;
end filtering_algorithm_pkg;
package body filtering_algorithm_pkg is
function datapoint_2_stdlogic(c : data_type) return std_logic_vector is
variable result : std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
begin
for I in 0 to D-1 loop
result((I+1)*COORD_BITWIDTH-1 downto I*COORD_BITWIDTH) := std_logic_vector(c(I));
end loop;
return result;
end datapoint_2_stdlogic;
function datapoint_ext_2_stdlogic(c : data_type_ext) return std_logic_vector is
variable result : std_logic_vector(D*COORD_BITWIDTH_EXT-1 downto 0);
begin
for I in 0 to D-1 loop
result((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT) := std_logic_vector(c(I));
end loop;
return result;
end datapoint_ext_2_stdlogic;
function stdlogic_2_datapoint(c : std_logic_vector) return data_type is
variable result : data_type;
begin
for I in 0 to D-1 loop
result(I) := c((I+1)*COORD_BITWIDTH-1 downto I*COORD_BITWIDTH);
end loop;
return result;
end stdlogic_2_datapoint;
function stdlogic_2_datapoint_ext(c : std_logic_vector) return data_type_ext is
variable result : data_type_ext;
begin
for I in 0 to D-1 loop
result(I) := c((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT);
end loop;
return result;
end stdlogic_2_datapoint_ext;
function nodedata_2_stdlogic(n : node_data_type) return std_logic_vector is
variable result : std_logic_vector(D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+COORD_BITWIDTH_EXT+COORD_BITWIDTH+2*NODE_POINTER_BITWIDTH-1 downto 0);
begin
for I in 0 to D-1 loop
result((I+1)*COORD_BITWIDTH_EXT+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto I*COORD_BITWIDTH_EXT+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.wgtCent(I);
result(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.midPoint(I);
result(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+1*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+1*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.bnd_lo(I);
result(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+2*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+2*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.bnd_hi(I);
end loop;
result(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.sum_sq;
result(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.count;
result(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+1*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := std_logic_vector(n.left);
result(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+2*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+1*NODE_POINTER_BITWIDTH) := std_logic_vector(n.right);
return result;
end nodedata_2_stdlogic;
function stdlogic_2_nodedata(n : std_logic_vector) return node_data_type is
variable result : node_data_type;
begin
for I in 0 to D-1 loop
result.wgtCent(I) := n((I+1)*COORD_BITWIDTH_EXT+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto I*COORD_BITWIDTH_EXT+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.midPoint(I) := n(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.bnd_lo(I) := n(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+1*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+1*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.bnd_hi(I) := n(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+2*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+2*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
end loop;
result.sum_sq := n(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.count := n(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.left := n(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+1*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.right := n(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+2*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+1*NODE_POINTER_BITWIDTH);
return result;
end stdlogic_2_nodedata;
function saturate(val : std_logic_vector) return std_logic_vector is
variable val_msb : std_logic;
variable comp : std_logic_vector((val'length-MUL_INTEGER_BITS-MUL_FRACTIONAL_BITS)-1 downto 0);
variable result : std_logic_vector(MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS-1 downto 0);
begin
if MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS < val'length then
val_msb := val(val'length-1);
for I in (val'length-MUL_INTEGER_BITS-MUL_FRACTIONAL_BITS)-1 downto 0 loop
comp(I) := val_msb;
end loop;
if val(val'length-2 downto MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS-1) = comp then
result := val(MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS-1 downto 0);
else
result(MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS-1) := val_msb;
result(MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS-2 downto 0) := (others => NOT(val_msb));
end if;
else
result := sext(val,MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS);
end if;
return result;
end saturate;
function sext(val : std_logic_vector; length : integer) return std_logic_vector is
variable val_msb : std_logic;
variable result : std_logic_vector(length-1 downto 0);
begin
val_msb := val(val'length-1);
result(val'length-1 downto 0) := val;
result(length-1 downto val'length) := (others => val_msb);
return result;
end sext;
function zext(val : std_logic_vector; length : integer) return std_logic_vector is
variable result : std_logic_vector(length-1 downto 0);
begin
result(val'length-1 downto 0) := val;
result(length-1 downto val'length) := (others => '0');
return result;
end zext;
function conv_ext_2_normal(val : data_type_ext) return data_type is
variable result : data_type;
begin
for I in 0 to D-1 loop
result(I) := val(I)(COORD_BITWIDTH-1 downto 0);
end loop;
return result;
end conv_ext_2_normal;
function conv_normal_2_ext(val : data_type) return data_type_ext is
variable result : data_type_ext;
begin
for I in 0 to D-1 loop
result(I) := sext(val(I),COORD_BITWIDTH_EXT);
end loop;
return result;
end conv_normal_2_ext;
end package body;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grspw_gen
-- File: grspw_gen.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: Generic GRSPW core
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library spw;
use spw.spwcomp.all;
entity grspw_gen is
generic(
tech : integer := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end entity;
architecture rtl of grspw_gen is
constant fabits1 : integer := log2(fifosize1);
constant fabits2 : integer := log2(fifosize2);
constant rfifo : integer := 5 + log2(rmapbufs);
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(4 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(4 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(4 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(4 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--nchar fifo
signal ncrenable : std_ulogic;
signal ncraddress : std_logic_vector(5 downto 0);
signal ncwrite : std_ulogic;
signal ncwdata : std_logic_vector(8 downto 0);
signal ncwaddress : std_logic_vector(5 downto 0);
signal ncrdata : std_logic_vector(8 downto 0);
--rmap buf
signal rmrenable : std_ulogic;
signal rmrenablex : std_ulogic;
signal rmraddress : std_logic_vector(7 downto 0);
signal rmwrite : std_ulogic;
signal rmwdata : std_logic_vector(7 downto 0);
signal rmwaddress : std_logic_vector(7 downto 0);
signal rmrdata : std_logic_vector(7 downto 0);
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
begin
grspwc0 : grspwc
generic map(
sysfreq => sysfreq,
usegen => usegen,
nsync => nsync,
rmap => rmap,
rmapcrc => rmapcrc,
fifosize1 => fifosize1,
fifosize2 => fifosize2,
rxunaligned => rxunaligned,
rmapbufs => rmapbufs,
scantest => scantest,
ports => ports,
tech => tech,
nodeaddr => nodeaddr,
destkey => destkey)
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--spw in
d => d,
nd => nd,
dconnect => dconnect,
--spw out
do => do,
so => so,
rxrsto => rxrsto,
--time iface
tickin => tickin,
tickout => tickout,
--clk bufs
rxclki => rxclk,
--irq
irq => irq,
--misc
clkdiv10 => clkdiv10,
dcrstval => dcrstval,
timerrstval => timerrstval,
--rmapen
rmapen => rmapen,
rmapnodeaddr => rmapnodeaddr,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => linkdis,
testclk => clk,
testrst => testrst,
testen => testen
);
ntst: if scantest = 0 generate
rmrenablex <= rmrenable;
end generate;
tst: if scantest = 1 generate
rmrenablex <= rmrenable and not testen;
end generate;
------------------------------------------------------------------------------
-- FIFOS ---------------------------------------------------------------------
------------------------------------------------------------------------------
nft : if ft = 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2p generic map(memtech*techfifo, fabits2, 9)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap /= 0) generate
ram0 : syncram_2p generic map(memtech, rfifo, 8)
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
ft1 : if ft /= 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2pft generic map(memtech*techfifo, fabits2, 9, 0, 0, 2*techfifo)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap /= 0) generate
ram0 : syncram_2pft generic map(memtech, rfifo, 8, 0, 0, 2)
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
end architecture;
|
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity AudioIO_tl is
port (
sampleButton : in std_logic;
vauxn : in std_logic;
vauxp : in std_logic;
leds : out std_logic_vector(15 downto 0);
clk : in std_logic;
reset : in std_logic
) ;
end entity ; -- AudioIO_tl
architecture arch of AudioIO_tl is
signal registerOutput : std_logic_vector(15 downto 0);
signal sampleOutput : std_logic_vector(15 downto 0);
begin
leds(14 downto 0) <= sampleOutput(14 downto 0);
leds(15) <= sampleButton;
sampler : entity work.ADSampler
port map (
vauxn => vauxn,
vauxp => vauxp,
output => sampleOutput,
clk => clk,
reset => reset
);
-- reg : entity work.Delay
-- generic map (
-- wordLength => 12
-- )
-- port map (
-- input => sampleOutput,
-- output => registerOutput,
--
-- clk => sampleButton,
-- reset => reset
-- );
end architecture ; -- arch |
-------------------------------------------------------------------------------
-- Copyright (C) 2022 Nick Gasson
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
package body env is
-- Forward slash is a legal separator on both Windows and Unix
constant DIR_SEPARATOR : string := "/";
procedure stop_impl(finish, have_status : boolean; status : integer);
attribute foreign of stop_impl : procedure is "_std_env_stop";
procedure stop(status : integer) is
begin
stop_impl(finish => false, have_status => true, status => status);
end procedure;
procedure stop is
begin
stop_impl(finish => false, have_status => false, status => 0);
end procedure;
procedure finish(status : integer) is
begin
stop_impl(finish => true, have_status => true, status => status);
end procedure;
procedure finish is
begin
stop_impl(finish => true, have_status => false, status => 0);
end procedure;
function resolution_limit return delay_length is
begin
return fs;
end function;
impure function localtime return time_record is
begin
return localtime(epoch);
end function;
impure function gmtime return time_record is
begin
return gmtime(epoch);
end function;
impure function epoch return real is
impure function impl return real;
attribute foreign of impl : function is "_std_env_epoch";
begin
return impl;
end function;
function localtime (timer : real) return time_record is
procedure impl (timer : real; tr : out time_record);
attribute foreign of impl : procedure is "_std_env_localtime";
variable result : time_record;
begin
impl(timer, result);
return result;
end function;
function gmtime (timer : real) return time_record is
procedure impl (timer : real; tr : out time_record);
attribute foreign of impl : procedure is "_std_env_gmtime";
variable result : time_record;
begin
impl(timer, result);
return result;
end function;
function epoch (trec : time_record) return real is
begin
report "not implemented" severity failure;
end function;
function localtime (trec : time_record) return time_record is
begin
report "not implemented" severity failure;
end function;
function gmtime (trec : time_record) return time_record is
begin
report "not implemented" severity failure;
end function;
function "+" (trec : time_record; delta : real) return time_record is
begin
report "not implemented" severity failure;
end function;
function "+" (delta : real; trec : time_record) return time_record is
begin
report "not implemented" severity failure;
end function;
function "-" (trec : time_record; delta : real) return time_record is
begin
report "not implemented" severity failure;
end function;
function "-" (delta : real; trec : time_record) return time_record is
begin
report "not implemented" severity failure;
end function;
function "-" (tr1, tr2 : time_record) return real is
begin
report "not implemented" severity warning;
return 0.0;
end function;
function time_to_seconds (time_val : in time) return real is
begin
report "not implemented" severity warning;
return 0.0;
end function;
function seconds_to_time (real_val : in real) return time is
begin
report "not implemented" severity warning;
return 0 fs;
end function;
function to_string (trec : time_record;
frac_digits : integer range 0 to 6 := 0)
return string
is
function zero_pad (value, width : integer) return string is
variable result : string(1 to width);
variable temp : integer := value;
begin
for i in width downto 1 loop
result(i to i) := to_string(temp rem 10);
temp := temp / 10;
end loop;
return result;
end function;
variable buf : string(1 to 26);
begin
buf(1 to 4) := zero_pad(trec.year, 4);
buf(5) := '-';
buf(6 to 7) := zero_pad(trec.month, 2);
buf(8) := '-';
buf(9 to 10) := zero_pad(trec.day, 2);
buf(11) := 'T';
buf(12 to 13) := zero_pad(trec.hour, 2);
buf(14) := ':';
buf(15 to 16) := zero_pad(trec.minute, 2);
buf(17) := ':';
buf(18 to 19) := zero_pad(trec.second, 2);
if frac_digits > 0 then
buf(20) := '.';
buf(21 to 26) := zero_pad(trec.microsecond, 6);
return buf(1 to 20 + frac_digits);
else
return buf(1 to 19);
end if;
end function;
impure function getenv (name : string) return string is
impure function impl (name : string) return string;
attribute foreign of impl : function is "_std_env_getenv";
begin
return impl(name);
end function;
impure function getenv (name : string) return line is
begin
return new string'(getenv(name));
end function;
impure function vhdl_version return STRING is
impure function impl return string;
attribute foreign of impl : function is "_std_env_vhdl_version";
begin
return impl;
end function;
function tool_type return STRING is
begin
return "SIMULATION";
end function;
function tool_vendor return string is
begin
return "https://www.nickg.me.uk/nvc";
end function;
function tool_name return string is
begin
return "nvc";
end function;
function tool_edition return string is
begin
return "";
end function;
function tool_version return string is
function impl return string;
attribute foreign of impl : function is "_std_env_tool_version";
begin
return impl;
end function;
procedure dir_open (dir : out directory;
path : in string;
status : out dir_open_status) is
begin
report "not implemented" severity failure;
end procedure;
impure function dir_open (dir : out directory;
path : in string) return dir_open_status is
begin
report "not implemented" severity failure;
end function;
procedure dir_close (variable dir : inout directory) is
begin
report "not implemented" severity failure;
end procedure;
impure function dir_itemexists (path : in string) return boolean is
impure function impl (path : in string) return boolean;
attribute foreign of impl : function is "_std_env_itemexists";
begin
return impl(path);
end function;
impure function dir_itemisdir (path : in string) return boolean is
impure function impl (path : in string) return boolean;
attribute foreign of impl : function is "_std_env_itemisdir";
begin
return impl(path);
end function;
impure function dir_itemisfile (path : in string) return boolean is
impure function impl (path : in string) return boolean;
attribute foreign of impl : function is "_std_env_itemisfile";
begin
return impl(path);
end function;
procedure dir_workingdir (path : in string;
status : out dir_open_status) is
procedure impl (path : in string;
status : out dir_open_status);
attribute foreign of impl : procedure is "_std_env_set_workingdir";
begin
impl(path, status);
end procedure;
impure function dir_workingdir (path : in string)
return dir_open_status
is
variable status : dir_open_status;
begin
dir_workingdir(path, status);
return status;
end function;
impure function dir_workingdir return string is
impure function impl return string;
attribute foreign of impl : function is "_std_env_get_workingdir";
begin
return impl;
end function;
procedure dir_createdir (path : in string;
status : out dir_create_status) is
begin
dir_createdir(path, false, status);
end procedure;
procedure dir_createdir (path : in string;
parents : in boolean;
status : out dir_create_status) is
procedure impl (path : in string;
parents : in boolean;
status : out dir_create_status);
attribute foreign of impl : procedure is "_std_env_createdir";
begin
assert not parents report "PARENTS flag not supported"
severity failure;
impl(path, parents, status);
end procedure;
impure function dir_createdir (path : in string;
parents : in boolean := false)
return dir_create_status
is
variable status : dir_create_status;
begin
dir_createdir(path, parents, status);
return status;
end function;
procedure dir_deletedir (path : in string;
status : out dir_delete_status) is
begin
report "not implemented" severity failure;
end procedure;
procedure dir_deletedir (path : in string;
recursive : in boolean;
status : out dir_delete_status) is
begin
report "not implemented" severity failure;
end procedure;
impure function dir_deletedir (path : in string;
recursive : in boolean := false)
return dir_delete_status is
begin
report "not implemented" severity failure;
end function;
procedure dir_deletefile (path : in string;
status : out file_delete_status) is
begin
report "not implemented" severity failure;
end procedure;
impure function dir_deletefile (path : in string) return file_delete_status is
begin
report "not implemented" severity failure;
end function;
impure function to_string (variable call_path : inout call_path_element)
return string is
begin
report "not implemented" severity failure;
end function;
impure function to_string (variable call_path : inout call_path_vector;
separator : string := "" & lf)
return string is
begin
report "not implemented" severity failure;
end function;
impure function to_string (variable call_path : inout call_path_vector_ptr; separator : string := "" & lf) return string is
begin
report "not implemented" severity failure;
end function;
impure function get_call_path return call_path_vector_ptr is
begin
report "not implemented" severity failure;
end function;
impure function file_name return line is
begin
report "not implemented" severity failure;
end function;
impure function file_name return string is
begin
report "not implemented" severity failure;
end function;
impure function file_path return line is
begin
report "not implemented" severity failure;
end function;
impure function file_path return string is
begin
report "not implemented" severity failure;
end function;
impure function file_line return positive is
begin
report "not implemented" severity failure;
end function;
impure function file_line return string is
begin
report "not implemented" severity failure;
end function;
impure function IsVhdlAssertFailed return boolean is
begin
report "not implemented" severity failure;
end function;
impure function IsVhdlAssertFailed (Level : severity_level)
return boolean is
begin
report "not implemented" severity failure;
end function;
impure function GetVhdlAssertCount return natural is
begin
report "not implemented" severity failure;
end function;
impure function GetVhdlAssertCount (Level : severity_level)
return natural is
begin
report "not implemented" severity failure;
end function;
procedure ClearVhdlAssert is
begin
report "not implemented" severity failure;
end procedure;
procedure SetVhdlAssertEnable (Enable : boolean := true) is
begin
report "not implemented" severity failure;
end procedure;
procedure SetVhdlAssertEnable (Level : severity_level := note;
Enable : boolean := true) is
begin
report "not implemented" severity failure;
end procedure;
impure function GetVhdlAssertEnable (Level : severity_level := note)
return boolean is
begin
report "not implemented" severity failure;
end function;
procedure SetVhdlAssertFormat(Level : SEVERITY_LEVEL;
Format : string) is
begin
report "not implemented" severity failure;
end procedure;
procedure SetVhdlAssertFormat (Level : severity_level;
Format : string;
Valid : out boolean) is
begin
report "not implemented" severity failure;
end procedure;
impure function GetVhdlAssertFormat (Level : severity_level)
return string is
begin
report "not implemented" severity failure;
end function;
procedure SetVhdlReadSeverity (Level : severity_level := failure) is
begin
report "not implemented" severity failure;
end procedure;
impure function GetVhdlReadSeverity return severity_level is
begin
report "not implemented" severity failure;
end function;
impure function PslAssertFailed return boolean is
begin
report "not implemented" severity failure;
end function;
impure function PslIsCovered return boolean is
begin
report "not implemented" severity failure;
end function;
procedure SetPslCoverAssert (Enable : boolean := TRUE) is
begin
report "not implemented" severity warning;
end procedure;
impure function GetPslCoverAssert return boolean is
begin
report "not implemented" severity warning;
return false;
end function;
impure function PslIsAssertCovered return boolean is
begin
report "not implemented" severity warning;
return false;
end function;
procedure ClearPslState is
begin
report "not implemented" severity warning;
end procedure;
end package body;
|
-- NEED RESULT: ARCH00437: comments passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00437
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 13.8 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00437)
-- ENT00437_Test_Bench(ARCH00437_Test_Bench)
--
-- REVISION HISTORY:
--
-- 4-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00437 of E00000 is
begin
P :
process
variable x,y,z,w : integer := 999;
begin
x := 25 ;
-- x := 26 ;
y := -25 ; -- y := 299 ;
z := x -- + 1
- 2*y ;
w -- !
:= -- !
x -- !
+ -- !
1 -- !
; -- !
test_report ( "ARCH00437" ,
"comments" ,
(x = 25) and
(y = -25) and
(z = 75) and
(w = 26)
) ;
wait ;
end process P ;
end ARCH00437 ;
entity ENT00437_Test_Bench is
end ENT00437_Test_Bench ;
architecture ARCH00437_Test_Bench of ENT00437_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00437 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00437_Test_Bench ;
|
--------------------------------------------------------------------------------
--
-- AM2901 Benchmark output_shifter
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept 17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept 17, 92 ZYCAD
--------------------------------------------------------------------------------
--library ZYCAD;
use work.TYPES.all;
use work.MVL7_functions.all;
entity output_and_shifter is
port (
I : in MVL7_vector(8 downto 0);
A, F, Q : in MVL7_vector(3 downto 0);
OEbar : in MVL7;
Y : out MVL7_vector(3 downto 0);
RAM0, RAM3, Q0, Q3 : out MVL7
);
end output_and_shifter;
architecture output_and_shifter of output_and_shifter is
begin
-- GENERATE DATA OUTPUT "Y"
Y <= A when (( I(8 downto 6) = "010") and ( OEbar = '0')) else
F when (not(( I(8 downto 6) = "010")) and ( OEbar = '0')) else
"ZZZZ";
-- GENERATE BIDIRECTIONAL SHIFTER SIGNALS.
RAM0 <= F(0) when ( I(8) = '1') and ( I(7) = '0' ) else
'Z';
RAM3 <= F(3) when ( I(8) = '1') and ( I(7) = '1' ) else
'Z';
Q3 <= Q(3) when ( I(8) = '1') and ( I(7) = '1') else
'Z';
Q0 <= Q(0) when ( I(8) = '1') and ( I(7) = '0') else
'Z';
end output_and_shifter;
------------------------------------------------ |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity VOICE_DELAY is
port
(
clk:in std_logic;
start:in std_logic:='0';
total:in std_logic_vector(7 downto 0);
finish:out std_logic:='1'
);
end entity;
architecture delayx of VOICE_DELAY is
signal delay_total:integer range 0 to 511:=0;
signal start_last:std_logic;
begin
process(clk)
variable con:integer range 0 to 400:=0;
begin
if clk'event and clk='1' then
start_last<=start;
if start_last='0' and start='1' then
con:=1;
delay_total<=conv_integer(total);
finish<='0';
end if;
if con=400 then
if delay_total=0 then
finish<='1';
con:=0;
else
delay_total<=delay_total-1;
con:=1;
end if;
elsif con>0 then
con:=con+1;
end if;
end if;
end process;
end delayx;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity VOICE_DELAY is
port
(
clk:in std_logic;
start:in std_logic:='0';
total:in std_logic_vector(7 downto 0);
finish:out std_logic:='1'
);
end entity;
architecture delayx of VOICE_DELAY is
signal delay_total:integer range 0 to 511:=0;
signal start_last:std_logic;
begin
process(clk)
variable con:integer range 0 to 400:=0;
begin
if clk'event and clk='1' then
start_last<=start;
if start_last='0' and start='1' then
con:=1;
delay_total<=conv_integer(total);
finish<='0';
end if;
if con=400 then
if delay_total=0 then
finish<='1';
con:=0;
else
delay_total<=delay_total-1;
con:=1;
end if;
elsif con>0 then
con:=con+1;
end if;
end if;
end process;
end delayx;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_sitodp_4_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_sitodp_4_no_dsp_32;
ARCHITECTURE sin_taylor_series_ap_sitodp_4_no_dsp_32_arch OF sin_taylor_series_ap_sitodp_4_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_sitodp_4_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 1,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 0,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 0,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 0,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_sitodp_4_no_dsp_32_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_sitodp_4_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_sitodp_4_no_dsp_32;
ARCHITECTURE sin_taylor_series_ap_sitodp_4_no_dsp_32_arch OF sin_taylor_series_ap_sitodp_4_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_sitodp_4_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 1,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 0,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 0,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 0,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_sitodp_4_no_dsp_32_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_sitodp_4_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_sitodp_4_no_dsp_32;
ARCHITECTURE sin_taylor_series_ap_sitodp_4_no_dsp_32_arch OF sin_taylor_series_ap_sitodp_4_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_sitodp_4_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 1,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 0,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 0,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 0,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_sitodp_4_no_dsp_32_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_sitodp_4_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_sitodp_4_no_dsp_32;
ARCHITECTURE sin_taylor_series_ap_sitodp_4_no_dsp_32_arch OF sin_taylor_series_ap_sitodp_4_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_sitodp_4_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 1,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 0,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 0,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 0,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_sitodp_4_no_dsp_32_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_sitodp_4_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_sitodp_4_no_dsp_32;
ARCHITECTURE sin_taylor_series_ap_sitodp_4_no_dsp_32_arch OF sin_taylor_series_ap_sitodp_4_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_sitodp_4_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 1,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 0,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 0,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 0,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_sitodp_4_no_dsp_32_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_sitodp_4_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_sitodp_4_no_dsp_32;
ARCHITECTURE sin_taylor_series_ap_sitodp_4_no_dsp_32_arch OF sin_taylor_series_ap_sitodp_4_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_sitodp_4_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 1,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 0,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 0,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 0,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_sitodp_4_no_dsp_32_arch;
|
---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_UDC3.vhd
-- Creation Date:
-- Description:
-- 1050 Typewriter Console interface section
-- Will also include Selector Channel(s) eventually
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY udc3 IS
port
(
-- Inputs
E_SW_SEL_BUS : IN E_SW_BUS_Type;
USE_MANUAL_DECODER : IN STD_LOGIC;
USE_ALT_CA_DECODER, USE_BASIC_CA_DECO : IN STD_LOGIC;
GTD_CA_BITS : STD_LOGIC_VECTOR(0 to 3);
Z_BUS : IN STD_LOGIC_VECTOR(0 to 8);
GT_1050_TAGS_OUT : IN STD_LOGIC;
GT_1050_BUS_OUT : IN STD_LOGIC;
-- PCH_CONN_ENTRY : IN PCH_CONN;
P_1050_SEL_IN : IN STD_LOGIC;
P_1050_SEL_OUT : IN STD_LOGIC;
SUPPRESS_OUT : IN STD_LOGIC;
CK_SAL_P_BIT : IN STD_LOGIC;
RECYCLE_RESET : IN STD_LOGIC;
MPX_OPN_LT_GATE : IN STD_LOGIC;
ADDR_OUT : IN STD_LOGIC;
-- Outputs
A_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 111111111 when inactive
M_ASSM_BUS,N_ASSM_BUS : OUT STD_LOGIC_VECTOR(0 to 8);
T_REQUEST : OUT STD_LOGIC;
n1050_INTRV_REQ : OUT STD_LOGIC;
TT6_POS_ATTN : OUT STD_LOGIC;
n1050_INSTALLED : OUT STD_LOGIC;
n1050_REQ_IN : OUT STD_LOGIC;
n1050_OP_IN : OUT STD_LOGIC;
n1050_CE_MODE : OUT STD_LOGIC;
n1050_SEL_O : OUT STD_LOGIC;
DEBUG : INOUT DEBUG_BUS;
-- Hardware Serial Port
serialInput : in Serial_Input_Lines;
serialOutput : out Serial_Output_Lines;
-- Clocks
clk : IN STD_LOGIC;
Clock1ms : IN STD_LOGIC;
Clock60Hz : IN STD_LOGIC;
T1,T2,T3,T4 : IN STD_LOGIC;
P1,P2,P3,P4 : IN STD_LOGIC
);
END udc3;
ARCHITECTURE FMD OF udc3 IS
signal WRITE_LCH : STD_LOGIC;
signal RST_ATTACH : STD_LOGIC;
signal PUNCH_1_CLUTCH, RDR_1_CLUTCH : STD_LOGIC;
signal READ_CLK_INTLK_LCH : STD_LOGIC;
signal CRLF : STD_LOGIC;
signal CLOCK_1 : STD_LOGIC;
signal CLK_STT_RST : STD_LOGIC;
signal W_TIME,X_TIME,Y_TIME,Z_TIME : STD_LOGIC;
signal RD_OR_RD_INQ : STD_LOGIC;
signal RD_INLK_RST : STD_LOGIC;
signal WRITE_LCH_RST : STD_LOGIC;
signal TT2_POS_END : STD_LOGIC;
signal CE_DATA_ENTER_GT : STD_LOGIC;
signal CE_TA_DECODE : STD_LOGIC;
signal CE_RESET : STD_LOGIC;
signal RUN : STD_LOGIC;
signal TAGS_OUT_BUS : STD_LOGIC_VECTOR(0 to 7);
signal sn1050_CE_MODE : STD_LOGIC;
signal EXIT_MPLX_SHARE : STD_LOGIC;
signal RD_SHARE_REQ : STD_LOGIC;
signal WR_SHARE_REQ : STD_LOGIC;
signal CE_SEL_O : STD_LOGIC;
signal sn1050_INTRV_REQ : STD_LOGIC;
signal UNGATED_RUN : STD_LOGIC;
signal REQUEST_KEY : STD_LOGIC;
signal n1050_RST_LCH : STD_LOGIC;
signal HOME_RDR_START_LCH : STD_LOGIC;
signal HOME_RDR_STOP : STD_LOGIC;
signal PROCEED_LCH : STD_LOGIC;
signal MICRO_SHARE_LCH : STD_LOGIC;
signal RDR_ON_LCH : STD_LOGIC;
signal TA_REG_POS_4 : STD_LOGIC;
signal AUDIBLE_ALARM : STD_LOGIC;
signal TA_REG_POS_6_ATTENTION_RST : STD_LOGIC;
signal SHARE_REQ_RST : STD_LOGIC;
signal CPU_REQUEST_IN : STD_LOGIC;
signal sTT6_POS_ATTN : STD_LOGIC;
signal XLATE_UC : STD_LOGIC;
signal sn1050_OP_IN : STD_LOGIC;
signal SET_SHIFT_LCH : STD_LOGIC;
signal TA_REG_SET : STD_LOGIC;
signal n1050_OPER : STD_LOGIC;
signal READ_INQ : STD_LOGIC;
signal RD_SHARE_REQ_LCH : STD_LOGIC;
signal READ : STD_LOGIC;
signal RESTORE : STD_LOGIC;
signal OUTPUT_SEL_AND_READY : STD_LOGIC;
signal UC_CHARACTER, LC_CHARACTER : STD_LOGIC;
signal PCH_BITS : STD_LOGIC_VECTOR(0 to 6);
signal CE_GT_TA_OR_TE, CE_TE_DECODE : STD_LOGIC;
signal CE_RUN_MODE : STD_LOGIC;
signal CE_BITS : STD_LOGIC_VECTOR(0 to 7);
signal DATA_REG_BUS : STD_LOGIC_VECTOR(0 to 7);
signal TE_LCH : STD_LOGIC;
signal ALLOW_STROBE : STD_LOGIC;
signal GT_WRITE_REG : STD_LOGIC;
signal FORCE_SHIFT_CHAR, FORCE_LC_SHIFT : STD_LOGIC;
signal SET_LOWER_CASE : STD_LOGIC;
signal READY_SHARE : STD_LOGIC;
signal TT_BUS : STD_LOGIC_VECTOR(0 to 7);
signal WRITE_MODE : STD_LOGIC;
signal NPL_BITS : STD_LOGIC_VECTOR(0 to 7);
signal PTT_BITS : STD_LOGIC_VECTOR(0 to 6);
signal WRITE_UC : STD_LOGIC;
signal WR_STROBE : STD_LOGIC;
signal PCH_1_HOME : STD_LOGIC;
signal TT5_POS_INTRV_REQ : STD_LOGIC;
signal CPU_LINES_ENTRY : CONN_1050;
signal CE_MODE_AND_TE_LCH : STD_LOGIC;
signal CE_SEL_OUT : STD_LOGIC;
signal CE_TI_DECODE : STD_LOGIC;
signal CE_BUS : STD_LOGIC_VECTOR(0 to 7);
signal CE_DATA_ENTER_NC : STD_LOGIC;
signal GTD_TT3 : STD_LOGIC;
BEGIN
M_ASSM_BUS <= (others=>'0');
N_ASSM_BUS <= (others=>'0');
-- Fig 5-09C
n1050_TRANSLATE : entity work.n1050_TRANSLATE port map(
-- Inputs
DATA_REG_BUS => DATA_REG_BUS,
RDR_ON_LCH => RDR_ON_LCH,
PUNCH_1_CLUTCH_1050 => PUNCH_1_CLUTCH,
HOME_RDR_STT_LCH => HOME_RDR_START_LCH,
CLOCK_STT_RST => CLK_STT_RST,
RST_ATTACH => RST_ATTACH,
W_TIME => W_TIME,
X_TIME => X_TIME,
Y_TIME => Y_TIME,
Z_TIME => Z_TIME,
n1050_RST => n1050_RST_LCH,
ALLOW_STROBE => ALLOW_STROBE,
PROCEED_LCH => PROCEED_LCH,
SHARE_REQ_RST => SHARE_REQ_RST,
CE_RUN_MODE => CE_RUN_MODE,
CE_TI_DECODE => CE_TI_DECODE,
SET_LOWER_CASE => SET_LOWER_CASE,
n1050_RST_LCH => n1050_RST_LCH,
READY_SHARE => READY_SHARE,
-- Outputs
TT2_POS_END => TT2_POS_END,
XLATE_UC => XLATE_UC,
RD_SHARE_REQ_LCH => RD_SHARE_REQ_LCH,
READ_SHARE_REQ => RD_SHARE_REQ,
WRITE_UC => WRITE_UC,
SET_SHIFT_LCH => SET_SHIFT_LCH,
PCH_1_HOME => PCH_1_HOME,
RUN => RUN,
UNGATED_RUN => UNGATED_RUN,
READ => READ,
READ_INQ => READ_INQ,
RD_OR_RD_INQ => RD_OR_RD_INQ,
LC_CHARACTER =>LC_CHARACTER,
UC_CHARACTER => UC_CHARACTER,
WRITE_LCH => WRITE_LCH,
WRITE_MODE => WRITE_MODE,
WRITE_STROBE => WR_STROBE,
WRITE_LCH_RST => WRITE_LCH_RST,
DEBUG => open
);
-- Fig 5-10A
n1050_CLOCK : entity work.n1050_CLOCK port map (
-- Inputs
WRITE_LCH => WRITE_LCH, -- 09CD2
READ_OR_READ_INQ => RD_OR_RD_INQ, -- 09CC5
RST_ATTACH => RST_ATTACH, -- 10BC2
PUNCH_1_CLUTCH => PUNCH_1_CLUTCH, -- 10DD5
READ_CLK_INTLK_LCH => READ_CLK_INTLK_LCH, -- 10BA2
RDR_1_CLUTCH => RDR_1_CLUTCH, -- 10DD5
CRLF => CRLF, -- ?
-- Outputs
CLOCK_1 => CLOCK_1, -- 10CD1 10CA4
W_TIME => W_TIME,
X_TIME => X_TIME,
Y_TIME => Y_TIME,
Z_TIME => Z_TIME,
CLK_STT_RST => CLK_STT_RST, -- 09CE1
clk => clk -- 50MHz
);
-- Fig 5-10B
n1050_TAGS : entity work.n1050_TAGS port map (
-- Inputs
RD_OR_RD_INQ => RD_OR_RD_INQ, -- 09CC5
Y_TIME => Y_TIME, -- 10AXX
RD_INLK_RST => RD_INLK_RST, -- 10DC5
WRITE_LCH_RST => WRITE_LCH_RST, -- 09CE2
PCH_1_CLUTCH => PUNCH_1_CLUTCH, -- 10DD5
TT2_POS_END => TT2_POS_END, -- 09CB5
WRITE_LCH => WRITE_LCH, -- 09CD2
Z_TIME => Z_TIME, -- 10AXX
CE_DATA_ENTER_GT => CE_DATA_ENTER_GT, -- 10DA2
CE_TA_DECODE => CE_TA_DECODE, -- 10DA1
GT_1050_TAGS_OUT => GT_1050_TAGS_OUT, -- 10CE2
RECYCLE_RESET => RECYCLE_RESET, -- 04CA5
CE_RESET => CE_RESET, -- 10DC2
RUN => RUN, -- 09CE6
TT3_POS_1050_OPER => TT_BUS(3), -- 10DD4
TAGS_OUT_BUS => TAGS_OUT_BUS, -- 10CD1
n1050_CE_MODE => sn1050_CE_MODE, -- 10DB3
n1050_SEL_O => n1050_SEL_O, -- 08DD6
P_1050_SEL_IN => P_1050_SEL_IN, -- 08DC1
P_1050_SEL_OUT => P_1050_SEL_OUT, -- 08DD6
MPX_OPN_LCH_GT => MPX_OPN_LT_GATE, -- 08CE3
CK_SAL_P_BIT => CK_SAL_P_BIT, -- 01CXX
EXIT_MPLX_SHARE => EXIT_MPLX_SHARE, -- 10DB3
ADDR_OUT => ADDR_OUT, -- 08DA5
RD_SHARE_REQ => RD_SHARE_REQ, -- 09CC6
RD_SHARE_REQ_LCH => RD_SHARE_REQ_LCH, -- 09CC6
SUPPRESS_OUT => SUPPRESS_OUT, -- 08DD6
WR_SHARE_REQ => WR_SHARE_REQ, -- 10CA6
CE_SEL_O => CE_SEL_O, -- 10DB2
INTRV_REQ => sn1050_INTRV_REQ, -- 10CD6
RDY_SHARE => READY_SHARE, -- 10CE6
UNGATED_RUN => UNGATED_RUN, -- 09CE6
REQUEST_KEY => REQUEST_KEY, -- 10DE5
-- Outputs
n1050_RST_LCH => n1050_RST_LCH, -- 10DF2 09CD1 10CA5 09CE5
HOME_RDR_START_LCH => HOME_RDR_START_LCH, -- 09CE4 09CE1 10DE2
HOME_RDR_STOP => HOME_RDR_STOP, -- 10DC5
PROCEED_LCH => PROCEED_LCH, -- 09CE4 10CC2 10DE2
MICRO_SHARE_LCH => MICRO_SHARE_LCH, -- 10DE2
RDR_ON_LCH => RDR_ON_LCH, -- 09CE4 10DE2 09CE1
TA_REG_POS_4 => TA_REG_POS_4, -- 10DE2
AUDIBLE_ALARM => AUDIBLE_ALARM, -- 14AXX
CR_LF => CRLF, -- 10AC1 10DE2
TA_REG_POS_6_ATTENTION_RST => TA_REG_POS_6_ATTENTION_RST, -- ---D4 10DE2 10CE5
CPU_LINES_TO_1050 => CPU_LINES_ENTRY, -- 10DE3
SHARE_REQ_RST => SHARE_REQ_RST, -- 09CC5 10CE4 10CA5
T_REQUEST => T_REQUEST, -- 07BD3 06BA3 07BB3
CPU_REQUEST_IN => CPU_REQUEST_IN, -- 10DE3
n1050_OP_IN => sn1050_OP_IN, -- 08DD4 10CA4
n1050_REQ_IN => n1050_REQ_IN, -- 08DD2
TT6_POS_ATTN => sTT6_POS_ATTN, -- 10DC4 04AB6
n1050_INSTALLED => n1050_INSTALLED, -- 08DC1
TA_REG_SET => TA_REG_SET,
RD_CLK_INLK_LCH => READ_CLK_INTLK_LCH,
RESTORE => RESTORE,
RST_ATTACH => RST_ATTACH,
DEBUG => DEBUG,
-- Clocks
clk => clk,
Clock1ms => Clock1ms,
Clock60Hz => Clock60Hz,
P1 => P1,
P2 => P2,
P3 => P3,
P4 => P4,
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4
);
TT6_POS_ATTN <= sTT6_POS_ATTN;
n1050_OP_IN <= sn1050_OP_IN;
-- Fig 5-10C
n1050_DATA : entity work.n1050_DATA port map (
-- Inputs
E_SW_SEL_BUS => E_SW_SEL_BUS,
USE_MANUAL_DECODER => USE_MANUAL_DECODER,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
USE_BASIC_CA_DECO => USE_BASIC_CA_DECO,
GTD_CA_BITS => GTD_CA_BITS,
XLATE_UC => XLATE_UC,
WR_LCH => WRITE_LCH,
RUN => RUN,
PROCEED_LCH => PROCEED_LCH,
-- TT4_POS_HOME_STT => TT4_POS_HOME_STT,
RD_OR_RD_INQ => RD_OR_RD_INQ,
W_TIME => W_TIME,
X_TIME => X_TIME,
Y_TIME => Y_TIME,
Z_TIME => Z_TIME,
Z_BUS => Z_BUS,
CLOCK_1 => CLOCK_1,
PCH_1_CLUTCH => PUNCH_1_CLUTCH,
GT_1050_BUS_OUT => GT_1050_BUS_OUT,
GT_1050_TAGS_OUT => GT_1050_TAGS_OUT,
n1050_OP_IN => sn1050_OP_IN,
SET_SHIFT_LCH => SET_SHIFT_LCH,
TA_REG_SET => TA_REG_SET,
RST_ATTACH => RST_ATTACH,
n1050_OPER => n1050_OPER,
READ_INQ => READ_INQ,
RD_SHARE_REQ_LCH => RD_SHARE_REQ_LCH,
READ => READ,
WRITE_MODE => WRITE_MODE,
RESTORE => RESTORE,
OUTPUT_SEL_AND_READY => OUTPUT_SEL_AND_READY,
SHARE_REQ_RST => SHARE_REQ_RST,
n1050_RST_LCH => n1050_RST_LCH,
RDR_1_CLUTCH => RDR_1_CLUTCH,
UC_CHARACTER => UC_CHARACTER,
LC_CHARACTER => LC_CHARACTER,
-- Z_BUS_0 => Z_BUS(0),
-- Z_BUS_3 => Z_BUS(3),
-- TT3_POS_1050_OPER => TT3_POS_1050_OPER,
TA_REG_POS_6_ATTN_RST => TA_REG_POS_6_ATTENTION_RST,
PCH_BITS => PCH_BITS,
-- CE controls
CE_GT_TA_OR_TE => CE_GT_TA_OR_TE,
CE_DATA_ENTER_GT => CE_DATA_ENTER_GT,
CE_TE_DECODE => CE_TE_DECODE,
CE_RUN_MODE => CE_RUN_MODE,
n1050_CE_MODE => sn1050_CE_MODE,
CE_BITS => CE_BITS,
-- Outputs
A_REG_BUS => A_BUS,
DATA_REG_BUS => DATA_REG_BUS,
TAGS_OUT => TAGS_OUT_BUS,
NPL_BITS => NPL_BITS,
PTT_BITS => PTT_BITS,
TE_LCH => TE_LCH,
WR_SHARE_REQ => WR_SHARE_REQ,
ALLOW_STROBE => ALLOW_STROBE,
GT_WRITE_REG => GT_WRITE_REG,
FORCE_SHIFT_CHAR => FORCE_SHIFT_CHAR,
FORCE_LC_SHIFT => FORCE_LC_SHIFT,
SET_LOWER_CASE => SET_LOWER_CASE,
n1050_INTRV_REQ => sn1050_INTRV_REQ,
READY_SHARE => READY_SHARE,
TT5_POS_INTRV_REQ => TT5_POS_INTRV_REQ,
-- Buses
TT_BUS => TT_BUS,
GTD_TT3 => GTD_TT3,
DEBUG => open,
-- Clocks
P1 => P1,
P2 => P2,
P3 => P3,
P4 => P4,
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4
);
n1050_INTRV_REQ <= sn1050_INTRV_REQ;
-- Fig 5-10D
n1050_ATTACH : entity work.n1050_ATTACH port map (
-- Inputs
-- CE Cable
CE_CABLE_IN => open,
-- CE DATA BUS From 1050 DATA section
PTT_BITS => PTT_BITS,
DATA_REG => DATA_REG_BUS,
NPL_BITS => NPL_BITS,
-- Other stuff
TE_LCH => TE_LCH,
WRITE_UC => WRITE_UC,
XLATE_UC => XLATE_UC,
CPU_REQUEST_IN => CPU_REQUEST_IN,
n1050_OP_IN => sn1050_OP_IN,
HOME_RDR_STT_LCH => HOME_RDR_START_LCH,
RDR_ON_LCH => RDR_ON_LCH,
MICRO_SHARE_LCH => MICRO_SHARE_LCH,
PROCEED_LCH => PROCEED_LCH,
TA_REG_POS_4 => TA_REG_POS_4,
CR_LF => CRLF,
TA_REG_POS_6 => TA_REG_POS_6_ATTENTION_RST,
n1050_RST => n1050_RST_LCH,
GT_WR_REG => GT_WRITE_REG,
FORCE_LC_SHIFT => FORCE_LC_SHIFT,
FORCE_SHIFT_CHAR => FORCE_SHIFT_CHAR,
WR_STROBE => WR_STROBE,
PCH_1_HOME => PCH_1_HOME,
HOME_RDR_STOP => HOME_RDR_STOP,
TT2_POS_END => TT2_POS_END,
TT5_POS_INTRV_REQ => TT5_POS_INTRV_REQ,
TT6_POS_ATTN => sTT6_POS_ATTN,
CPU_LINES_ENTRY => CPU_LINES_ENTRY,
-- PCH_CONN_ENTRY => PCH_CONN_ENTRY,
RDR_1_CLUTCH => RDR_1_CLUTCH,
-- Outputs
-- CE Cable
CE_CABLE_OUT => open,
-- CE DATA BUS to 10C (1050 DATA)
CE_GT_TA_OR_TE => CE_GT_TA_OR_TE,
CE_DATA_ENTER_GT => CE_DATA_ENTER_GT,
CE_TE_DECODE => CE_TE_DECODE,
CE_MODE_AND_TE_LCH => CE_MODE_AND_TE_LCH,
n1050_CE_MODE => sn1050_CE_MODE,
-- Other stuff
CE_SEL_OUT => CE_SEL_OUT,
CE_TI_DECODE => CE_TI_DECODE,
CE_RUN_MODE => CE_RUN_MODE,
CE_TA_DECODE => CE_TA_DECODE,
CE_BUS => CE_BUS,
EXIT_MPLX_SHARE => EXIT_MPLX_SHARE,
CE_DATA_ENTER_NC => CE_DATA_ENTER_NC,
-- TT3_POS_1050_OPER => TT_BUS(3),
-- TT4_POS_HOME_STT => TT_BUS(4),
OUTPUT_SEL_AND_RDY => OUTPUT_SEL_AND_READY,
n1050_OPER => n1050_OPER,
PUNCH_BITS => PCH_BITS,
READ_INTLK_RST => RD_INLK_RST,
PUNCH_1_CLUTCH => PUNCH_1_CLUTCH,
-- PCH_1_CLUTCH_1050 => PCH_1_CLUTCH_1050,
REQUEST_KEY => REQUEST_KEY,
-- RDR_1_CONN_EXIT => RDR_1_CONN_EXIT,
-- CPU_LINES_EXIT => n1050_CONTROL,
-- In/Out TT bus
TT_BUS => TT_BUS,
GTD_TT3 => GTD_TT3,
SerialInput => SerialInput,
SerialOutput => SerialOutput,
-- Clocks
P1 => P1,
P2 => P2,
P3 => P3,
P4 => P4,
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4,
clk => clk
);
n1050_CE_MODE <= sn1050_CE_MODE;
-- PCH_1_CLUTCH <= PCH_CONN_ENTRY.PCH_1_CLUTCH_1050;
END FMD;
|
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`protect begin_protected
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|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5296)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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GJDW36qBP5Bj/b1u1ME=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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bA66q2PSTKNLTr4xOU/9HIDRXVIaPzR1uLrkDg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5296)
`protect data_block
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`protect end_protected
|
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